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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.62 97.96 93.90 97.44 81.25 96.42 98.17 90.23


Total test records in report: 3234
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T3076 /workspace/coverage/default/23.usbdev_low_speed_traffic.3851749052 Aug 05 05:37:01 PM PDT 24 Aug 05 05:39:30 PM PDT 24 5032828102 ps
T3077 /workspace/coverage/default/30.usbdev_random_length_out_transaction.1233616930 Aug 05 05:37:51 PM PDT 24 Aug 05 05:37:52 PM PDT 24 162375438 ps
T3078 /workspace/coverage/default/182.usbdev_endpoint_types.3289791434 Aug 05 05:40:49 PM PDT 24 Aug 05 05:40:50 PM PDT 24 732865991 ps
T3079 /workspace/coverage/default/25.usbdev_streaming_out.1017482000 Aug 05 05:37:12 PM PDT 24 Aug 05 05:37:48 PM PDT 24 3608908369 ps
T3080 /workspace/coverage/default/12.usbdev_streaming_out.3770111655 Aug 05 05:35:22 PM PDT 24 Aug 05 05:35:41 PM PDT 24 2352285493 ps
T3081 /workspace/coverage/default/32.usbdev_pkt_sent.3333025787 Aug 05 05:38:19 PM PDT 24 Aug 05 05:38:20 PM PDT 24 247790231 ps
T3082 /workspace/coverage/default/9.usbdev_invalid_sync.3630374002 Aug 05 05:34:48 PM PDT 24 Aug 05 05:35:45 PM PDT 24 5739807537 ps
T3083 /workspace/coverage/default/46.usbdev_aon_wake_disconnect.4079104077 Aug 05 05:39:49 PM PDT 24 Aug 05 05:40:03 PM PDT 24 11106009216 ps
T3084 /workspace/coverage/default/3.usbdev_max_length_out_transaction.2663500174 Aug 05 05:33:38 PM PDT 24 Aug 05 05:33:39 PM PDT 24 221822564 ps
T3085 /workspace/coverage/default/16.usbdev_aon_wake_resume.1351717229 Aug 05 05:35:48 PM PDT 24 Aug 05 05:36:23 PM PDT 24 29648451973 ps
T3086 /workspace/coverage/default/47.usbdev_disconnected.2474549776 Aug 05 05:40:03 PM PDT 24 Aug 05 05:40:04 PM PDT 24 177787665 ps
T3087 /workspace/coverage/default/29.usbdev_enable.3883925469 Aug 05 05:37:50 PM PDT 24 Aug 05 05:37:51 PM PDT 24 35525597 ps
T3088 /workspace/coverage/default/12.usbdev_phy_pins_sense.3433791370 Aug 05 05:35:16 PM PDT 24 Aug 05 05:35:17 PM PDT 24 76731250 ps
T3089 /workspace/coverage/default/38.usbdev_av_buffer.689331710 Aug 05 05:38:58 PM PDT 24 Aug 05 05:38:59 PM PDT 24 190193127 ps
T3090 /workspace/coverage/default/13.usbdev_max_length_out_transaction.1519405850 Aug 05 05:35:30 PM PDT 24 Aug 05 05:35:31 PM PDT 24 226611608 ps
T3091 /workspace/coverage/default/49.usbdev_fifo_rst.549033315 Aug 05 05:40:24 PM PDT 24 Aug 05 05:40:25 PM PDT 24 228019729 ps
T3092 /workspace/coverage/default/25.usbdev_in_iso.2543751407 Aug 05 05:37:02 PM PDT 24 Aug 05 05:37:04 PM PDT 24 255276961 ps
T3093 /workspace/coverage/default/12.usbdev_resume_link_active.211217196 Aug 05 05:35:21 PM PDT 24 Aug 05 05:35:45 PM PDT 24 20159423504 ps
T3094 /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.2759693152 Aug 05 05:40:31 PM PDT 24 Aug 05 05:41:07 PM PDT 24 4909933377 ps
T3095 /workspace/coverage/default/5.usbdev_spurious_pids_ignored.3556169209 Aug 05 05:34:03 PM PDT 24 Aug 05 05:34:23 PM PDT 24 2648149900 ps
T3096 /workspace/coverage/default/42.usbdev_data_toggle_clear.174345584 Aug 05 05:39:20 PM PDT 24 Aug 05 05:39:21 PM PDT 24 548838003 ps
T3097 /workspace/coverage/default/148.usbdev_endpoint_types.1130077567 Aug 05 05:40:57 PM PDT 24 Aug 05 05:40:59 PM PDT 24 488676806 ps
T3098 /workspace/coverage/default/42.usbdev_pkt_buffer.627235935 Aug 05 05:39:37 PM PDT 24 Aug 05 05:39:54 PM PDT 24 6393646494 ps
T3099 /workspace/coverage/default/38.usbdev_pkt_sent.2279235207 Aug 05 05:38:58 PM PDT 24 Aug 05 05:38:59 PM PDT 24 227902228 ps
T3100 /workspace/coverage/default/24.usbdev_alert_test.2022741720 Aug 05 05:37:07 PM PDT 24 Aug 05 05:37:08 PM PDT 24 45158564 ps
T3101 /workspace/coverage/default/5.usbdev_random_length_in_transaction.2494707041 Aug 05 05:34:03 PM PDT 24 Aug 05 05:34:04 PM PDT 24 187021100 ps
T3102 /workspace/coverage/default/10.usbdev_pkt_buffer.447917507 Aug 05 05:35:00 PM PDT 24 Aug 05 05:35:19 PM PDT 24 7012095068 ps
T3103 /workspace/coverage/default/47.usbdev_invalid_sync.3367453253 Aug 05 05:40:10 PM PDT 24 Aug 05 05:40:38 PM PDT 24 3678417518 ps
T3104 /workspace/coverage/default/3.usbdev_aon_wake_disconnect.58921538 Aug 05 05:33:32 PM PDT 24 Aug 05 05:33:41 PM PDT 24 5981196458 ps
T3105 /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.641057084 Aug 05 05:38:59 PM PDT 24 Aug 05 05:39:00 PM PDT 24 160224034 ps
T3106 /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2516553995 Aug 05 05:33:03 PM PDT 24 Aug 05 05:33:26 PM PDT 24 2181051613 ps
T3107 /workspace/coverage/default/25.usbdev_out_stall.3102922354 Aug 05 05:37:11 PM PDT 24 Aug 05 05:37:12 PM PDT 24 162598150 ps
T3108 /workspace/coverage/default/93.usbdev_endpoint_types.3829639598 Aug 05 05:40:56 PM PDT 24 Aug 05 05:40:57 PM PDT 24 185131088 ps
T3109 /workspace/coverage/default/34.usbdev_link_suspend.2832772037 Aug 05 05:38:22 PM PDT 24 Aug 05 05:38:33 PM PDT 24 9869256168 ps
T3110 /workspace/coverage/default/1.usbdev_stream_len_max.1872651600 Aug 05 05:33:11 PM PDT 24 Aug 05 05:33:13 PM PDT 24 725387948 ps
T3111 /workspace/coverage/default/27.usbdev_stall_trans.102765590 Aug 05 05:37:37 PM PDT 24 Aug 05 05:37:38 PM PDT 24 176808114 ps
T3112 /workspace/coverage/default/44.usbdev_phy_config_pinflip.1523358943 Aug 05 05:39:37 PM PDT 24 Aug 05 05:39:38 PM PDT 24 306348213 ps
T328 /workspace/coverage/default/3.usbdev_pkt_buffer.3589965390 Aug 05 05:33:38 PM PDT 24 Aug 05 05:34:26 PM PDT 24 19430283672 ps
T3113 /workspace/coverage/default/1.usbdev_iso_retraction.3761555370 Aug 05 05:33:05 PM PDT 24 Aug 05 05:34:05 PM PDT 24 8535442793 ps
T3114 /workspace/coverage/default/25.usbdev_pending_in_trans.36496854 Aug 05 05:37:12 PM PDT 24 Aug 05 05:37:13 PM PDT 24 174064508 ps
T3115 /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3860070470 Aug 05 05:38:32 PM PDT 24 Aug 05 05:38:40 PM PDT 24 6219239921 ps
T3116 /workspace/coverage/default/49.usbdev_pkt_buffer.4269980899 Aug 05 05:40:32 PM PDT 24 Aug 05 05:41:15 PM PDT 24 17368903473 ps
T3117 /workspace/coverage/default/27.usbdev_pkt_received.3324879525 Aug 05 05:37:36 PM PDT 24 Aug 05 05:37:37 PM PDT 24 151596975 ps
T3118 /workspace/coverage/default/40.usbdev_phy_pins_sense.2694273185 Aug 05 05:39:23 PM PDT 24 Aug 05 05:39:24 PM PDT 24 34851728 ps
T3119 /workspace/coverage/default/7.usbdev_link_in_err.1519436870 Aug 05 05:34:27 PM PDT 24 Aug 05 05:34:28 PM PDT 24 219293166 ps
T3120 /workspace/coverage/default/30.usbdev_in_stall.2647141556 Aug 05 05:37:45 PM PDT 24 Aug 05 05:37:46 PM PDT 24 166054642 ps
T3121 /workspace/coverage/default/7.usbdev_invalid_sync.3514667311 Aug 05 05:34:22 PM PDT 24 Aug 05 05:34:59 PM PDT 24 4443031656 ps
T3122 /workspace/coverage/default/6.usbdev_aon_wake_disconnect.2552767875 Aug 05 05:34:02 PM PDT 24 Aug 05 05:34:14 PM PDT 24 10076284963 ps
T3123 /workspace/coverage/default/28.usbdev_pkt_buffer.729362463 Aug 05 05:37:49 PM PDT 24 Aug 05 05:38:36 PM PDT 24 20061143483 ps
T3124 /workspace/coverage/default/8.usbdev_spurious_pids_ignored.2577678494 Aug 05 05:34:44 PM PDT 24 Aug 05 05:35:15 PM PDT 24 3191673384 ps
T3125 /workspace/coverage/default/33.usbdev_streaming_out.3503073325 Aug 05 05:38:22 PM PDT 24 Aug 05 05:38:40 PM PDT 24 2228153128 ps
T3126 /workspace/coverage/default/0.usbdev_low_speed_traffic.131896242 Aug 05 05:32:52 PM PDT 24 Aug 05 05:34:10 PM PDT 24 2873960070 ps
T3127 /workspace/coverage/default/39.usbdev_bitstuff_err.2075079422 Aug 05 05:39:04 PM PDT 24 Aug 05 05:39:05 PM PDT 24 134651390 ps
T3128 /workspace/coverage/default/35.usbdev_max_length_out_transaction.441063507 Aug 05 05:38:48 PM PDT 24 Aug 05 05:38:49 PM PDT 24 218803636 ps
T3129 /workspace/coverage/default/40.usbdev_setup_stage.4057713570 Aug 05 05:39:14 PM PDT 24 Aug 05 05:39:15 PM PDT 24 144420488 ps
T3130 /workspace/coverage/default/25.usbdev_min_length_out_transaction.3887335231 Aug 05 05:37:12 PM PDT 24 Aug 05 05:37:13 PM PDT 24 142189392 ps
T3131 /workspace/coverage/default/3.usbdev_bitstuff_err.1349392795 Aug 05 05:33:30 PM PDT 24 Aug 05 05:33:31 PM PDT 24 169823042 ps
T3132 /workspace/coverage/default/8.usbdev_max_length_in_transaction.1851028169 Aug 05 05:34:32 PM PDT 24 Aug 05 05:34:33 PM PDT 24 240635332 ps
T3133 /workspace/coverage/default/42.usbdev_out_trans_nak.3172195766 Aug 05 05:39:24 PM PDT 24 Aug 05 05:39:25 PM PDT 24 187493640 ps
T203 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2580225977 Aug 05 04:58:02 PM PDT 24 Aug 05 04:58:04 PM PDT 24 70230451 ps
T206 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2255371405 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:06 PM PDT 24 69599266 ps
T204 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2584629803 Aug 05 04:58:03 PM PDT 24 Aug 05 04:58:05 PM PDT 24 69660651 ps
T3134 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2217818551 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:59 PM PDT 24 289911203 ps
T261 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4293239509 Aug 05 04:58:08 PM PDT 24 Aug 05 04:58:09 PM PDT 24 55286553 ps
T205 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2042590515 Aug 05 04:57:48 PM PDT 24 Aug 05 04:57:50 PM PDT 24 57889506 ps
T213 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1061507746 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:05 PM PDT 24 39820286 ps
T224 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.481607137 Aug 05 04:57:46 PM PDT 24 Aug 05 04:57:47 PM PDT 24 84311406 ps
T221 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.621921906 Aug 05 04:57:58 PM PDT 24 Aug 05 04:58:01 PM PDT 24 111782009 ps
T222 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3732443646 Aug 05 04:57:58 PM PDT 24 Aug 05 04:58:00 PM PDT 24 175226724 ps
T225 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.711624975 Aug 05 04:57:50 PM PDT 24 Aug 05 04:57:51 PM PDT 24 57292170 ps
T223 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2648385299 Aug 05 04:57:48 PM PDT 24 Aug 05 04:57:50 PM PDT 24 188776595 ps
T226 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.580497349 Aug 05 04:57:55 PM PDT 24 Aug 05 04:57:57 PM PDT 24 163669997 ps
T233 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2007404275 Aug 05 04:57:51 PM PDT 24 Aug 05 04:57:53 PM PDT 24 219540583 ps
T211 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.4129198788 Aug 05 04:57:56 PM PDT 24 Aug 05 04:57:56 PM PDT 24 42910592 ps
T212 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.277727518 Aug 05 04:58:11 PM PDT 24 Aug 05 04:58:12 PM PDT 24 47020241 ps
T214 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3605976266 Aug 05 04:57:59 PM PDT 24 Aug 05 04:58:00 PM PDT 24 53455974 ps
T280 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1964928584 Aug 05 04:58:13 PM PDT 24 Aug 05 04:58:14 PM PDT 24 40682653 ps
T3135 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2561479767 Aug 05 04:57:45 PM PDT 24 Aug 05 04:57:50 PM PDT 24 162697879 ps
T269 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3806032489 Aug 05 04:57:58 PM PDT 24 Aug 05 04:57:59 PM PDT 24 121275011 ps
T270 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3371775673 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:59 PM PDT 24 465273953 ps
T281 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3497741216 Aug 05 04:58:12 PM PDT 24 Aug 05 04:58:13 PM PDT 24 42696985 ps
T271 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.648227188 Aug 05 04:58:07 PM PDT 24 Aug 05 04:58:08 PM PDT 24 80443222 ps
T282 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.793197819 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:58 PM PDT 24 40739154 ps
T243 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1518468016 Aug 05 04:58:07 PM PDT 24 Aug 05 04:58:14 PM PDT 24 112065301 ps
T272 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.760181407 Aug 05 04:57:40 PM PDT 24 Aug 05 04:57:41 PM PDT 24 74721774 ps
T228 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4246921219 Aug 05 04:58:06 PM PDT 24 Aug 05 04:58:08 PM PDT 24 146200297 ps
T303 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2593370494 Aug 05 04:58:13 PM PDT 24 Aug 05 04:58:13 PM PDT 24 39053482 ps
T230 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2909304609 Aug 05 04:57:55 PM PDT 24 Aug 05 04:57:58 PM PDT 24 792464286 ps
T234 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.665863895 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:06 PM PDT 24 135256188 ps
T273 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.196906183 Aug 05 04:57:59 PM PDT 24 Aug 05 04:58:01 PM PDT 24 289168209 ps
T305 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.4228086740 Aug 05 04:58:05 PM PDT 24 Aug 05 04:58:06 PM PDT 24 48731963 ps
T231 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3256280366 Aug 05 04:58:06 PM PDT 24 Aug 05 04:58:11 PM PDT 24 743349467 ps
T252 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2754378952 Aug 05 04:58:00 PM PDT 24 Aug 05 04:58:04 PM PDT 24 338966256 ps
T302 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2445169241 Aug 05 04:58:14 PM PDT 24 Aug 05 04:58:14 PM PDT 24 36175850 ps
T301 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1604299257 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:05 PM PDT 24 39121450 ps
T307 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3916660188 Aug 05 04:58:00 PM PDT 24 Aug 05 04:58:01 PM PDT 24 36371471 ps
T3136 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3455086215 Aug 05 04:57:51 PM PDT 24 Aug 05 04:57:54 PM PDT 24 257584935 ps
T253 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4193194574 Aug 05 04:57:47 PM PDT 24 Aug 05 04:57:48 PM PDT 24 59719765 ps
T232 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2479813007 Aug 05 04:57:53 PM PDT 24 Aug 05 04:57:56 PM PDT 24 411811695 ps
T238 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3990217519 Aug 05 04:57:49 PM PDT 24 Aug 05 04:57:53 PM PDT 24 462954283 ps
T304 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3791353869 Aug 05 04:58:17 PM PDT 24 Aug 05 04:58:23 PM PDT 24 44583860 ps
T3137 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2674404037 Aug 05 04:58:06 PM PDT 24 Aug 05 04:58:08 PM PDT 24 144858621 ps
T236 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.674108748 Aug 05 04:57:58 PM PDT 24 Aug 05 04:58:00 PM PDT 24 74816091 ps
T3138 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3156732883 Aug 05 04:57:54 PM PDT 24 Aug 05 04:57:55 PM PDT 24 49587608 ps
T254 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2193926015 Aug 05 04:58:03 PM PDT 24 Aug 05 04:58:04 PM PDT 24 93900486 ps
T306 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2252625718 Aug 05 04:58:03 PM PDT 24 Aug 05 04:58:04 PM PDT 24 81335005 ps
T274 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1063423806 Aug 05 04:57:59 PM PDT 24 Aug 05 04:58:01 PM PDT 24 198809239 ps
T235 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2904211839 Aug 05 04:57:59 PM PDT 24 Aug 05 04:58:03 PM PDT 24 300554508 ps
T3139 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2191681894 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:58 PM PDT 24 74246558 ps
T3140 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2668559915 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:58 PM PDT 24 93336698 ps
T3141 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2525328200 Aug 05 04:57:59 PM PDT 24 Aug 05 04:57:59 PM PDT 24 42546260 ps
T311 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3432917022 Aug 05 04:58:07 PM PDT 24 Aug 05 04:58:12 PM PDT 24 1010765507 ps
T3142 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1239727140 Aug 05 04:57:55 PM PDT 24 Aug 05 04:57:56 PM PDT 24 98372175 ps
T3143 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3783912146 Aug 05 04:58:17 PM PDT 24 Aug 05 04:58:18 PM PDT 24 88573305 ps
T237 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3275938569 Aug 05 04:58:35 PM PDT 24 Aug 05 04:58:38 PM PDT 24 103843286 ps
T3144 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4065392141 Aug 05 04:58:05 PM PDT 24 Aug 05 04:58:06 PM PDT 24 40911370 ps
T255 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3934237237 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:58 PM PDT 24 59961482 ps
T256 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3584824914 Aug 05 04:57:52 PM PDT 24 Aug 05 04:57:58 PM PDT 24 755878941 ps
T3145 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1759836798 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:05 PM PDT 24 58223618 ps
T319 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1301204447 Aug 05 04:57:50 PM PDT 24 Aug 05 04:57:55 PM PDT 24 536229331 ps
T3146 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1168392773 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:58 PM PDT 24 73351283 ps
T3147 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.592899542 Aug 05 04:58:03 PM PDT 24 Aug 05 04:58:06 PM PDT 24 230709403 ps
T278 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.242205153 Aug 05 04:58:06 PM PDT 24 Aug 05 04:58:07 PM PDT 24 108701409 ps
T279 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.833621688 Aug 05 04:57:40 PM PDT 24 Aug 05 04:57:43 PM PDT 24 200869096 ps
T3148 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3340972610 Aug 05 04:57:48 PM PDT 24 Aug 05 04:57:50 PM PDT 24 239120559 ps
T3149 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.31273139 Aug 05 04:57:58 PM PDT 24 Aug 05 04:57:59 PM PDT 24 91536794 ps
T3150 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3730341934 Aug 05 04:57:58 PM PDT 24 Aug 05 04:58:01 PM PDT 24 264800703 ps
T257 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2144520039 Aug 05 04:57:51 PM PDT 24 Aug 05 04:57:53 PM PDT 24 94874032 ps
T3151 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2002257032 Aug 05 04:57:59 PM PDT 24 Aug 05 04:58:00 PM PDT 24 57135147 ps
T309 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3208740254 Aug 05 04:57:51 PM PDT 24 Aug 05 04:57:54 PM PDT 24 330193278 ps
T3152 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1166056827 Aug 05 04:58:20 PM PDT 24 Aug 05 04:58:21 PM PDT 24 41865919 ps
T258 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3262400180 Aug 05 04:57:54 PM PDT 24 Aug 05 04:57:55 PM PDT 24 82448095 ps
T283 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.445581092 Aug 05 04:57:46 PM PDT 24 Aug 05 04:57:47 PM PDT 24 139639389 ps
T3153 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2118100906 Aug 05 04:57:59 PM PDT 24 Aug 05 04:58:02 PM PDT 24 131038685 ps
T239 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.449387606 Aug 05 04:58:16 PM PDT 24 Aug 05 04:58:19 PM PDT 24 287722770 ps
T312 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.545284049 Aug 05 04:58:07 PM PDT 24 Aug 05 04:58:10 PM PDT 24 529762564 ps
T3154 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.579748755 Aug 05 04:57:47 PM PDT 24 Aug 05 04:57:48 PM PDT 24 96338733 ps
T3155 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2504407914 Aug 05 04:58:02 PM PDT 24 Aug 05 04:58:06 PM PDT 24 185123044 ps
T259 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.188133494 Aug 05 04:57:56 PM PDT 24 Aug 05 04:57:57 PM PDT 24 55136139 ps
T3156 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2007419147 Aug 05 04:57:51 PM PDT 24 Aug 05 04:57:53 PM PDT 24 106649274 ps
T3157 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3963876483 Aug 05 04:57:44 PM PDT 24 Aug 05 04:57:49 PM PDT 24 761314372 ps
T3158 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2278689117 Aug 05 04:58:08 PM PDT 24 Aug 05 04:58:09 PM PDT 24 48751457 ps
T3159 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3758309200 Aug 05 04:58:01 PM PDT 24 Aug 05 04:58:03 PM PDT 24 61934171 ps
T3160 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1172153914 Aug 05 04:58:08 PM PDT 24 Aug 05 04:58:09 PM PDT 24 53169869 ps
T260 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2139157908 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:05 PM PDT 24 68054442 ps
T3161 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1286130917 Aug 05 04:58:00 PM PDT 24 Aug 05 04:58:01 PM PDT 24 50503586 ps
T3162 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4001107550 Aug 05 04:58:07 PM PDT 24 Aug 05 04:58:08 PM PDT 24 39123123 ps
T3163 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3783944698 Aug 05 04:58:08 PM PDT 24 Aug 05 04:58:09 PM PDT 24 74196260 ps
T3164 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.4214129866 Aug 05 04:58:06 PM PDT 24 Aug 05 04:58:08 PM PDT 24 190300872 ps
T262 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.802866408 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:58 PM PDT 24 55000567 ps
T3165 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.150224762 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:58 PM PDT 24 29396354 ps
T3166 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3787181802 Aug 05 04:57:50 PM PDT 24 Aug 05 04:57:51 PM PDT 24 181349389 ps
T3167 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2811732162 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:04 PM PDT 24 45602321 ps
T3168 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1867256930 Aug 05 04:57:56 PM PDT 24 Aug 05 04:57:57 PM PDT 24 83260647 ps
T3169 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3675230263 Aug 05 04:58:03 PM PDT 24 Aug 05 04:58:14 PM PDT 24 2569558096 ps
T240 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1965625995 Aug 05 04:58:03 PM PDT 24 Aug 05 04:58:05 PM PDT 24 83470000 ps
T3170 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2223208500 Aug 05 04:57:49 PM PDT 24 Aug 05 04:57:52 PM PDT 24 223699420 ps
T3171 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3689740118 Aug 05 04:58:13 PM PDT 24 Aug 05 04:58:14 PM PDT 24 87048925 ps
T3172 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1784446784 Aug 05 04:58:05 PM PDT 24 Aug 05 04:58:06 PM PDT 24 44279336 ps
T3173 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3800881489 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:59 PM PDT 24 270544477 ps
T3174 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.764718420 Aug 05 04:58:05 PM PDT 24 Aug 05 04:58:08 PM PDT 24 324698299 ps
T3175 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.360001950 Aug 05 04:58:05 PM PDT 24 Aug 05 04:58:07 PM PDT 24 76774329 ps
T3176 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3774959088 Aug 05 04:57:54 PM PDT 24 Aug 05 04:57:55 PM PDT 24 85821805 ps
T3177 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1617136311 Aug 05 04:58:08 PM PDT 24 Aug 05 04:58:10 PM PDT 24 96113907 ps
T3178 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2070146880 Aug 05 04:58:02 PM PDT 24 Aug 05 04:58:05 PM PDT 24 99602519 ps
T3179 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2406326685 Aug 05 04:58:09 PM PDT 24 Aug 05 04:58:10 PM PDT 24 126397997 ps
T263 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3459842444 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:59 PM PDT 24 76093551 ps
T3180 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3920780299 Aug 05 04:58:00 PM PDT 24 Aug 05 04:58:02 PM PDT 24 59721385 ps
T3181 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1170737369 Aug 05 04:57:46 PM PDT 24 Aug 05 04:57:48 PM PDT 24 127068461 ps
T3182 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1488226056 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:59 PM PDT 24 109260973 ps
T264 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.510298017 Aug 05 04:57:59 PM PDT 24 Aug 05 04:58:00 PM PDT 24 120372607 ps
T3183 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4082869838 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:05 PM PDT 24 61911896 ps
T265 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.394527545 Aug 05 04:58:05 PM PDT 24 Aug 05 04:58:06 PM PDT 24 142408217 ps
T314 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3211882120 Aug 05 04:58:00 PM PDT 24 Aug 05 04:58:03 PM PDT 24 356413232 ps
T3184 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3816707321 Aug 05 04:58:07 PM PDT 24 Aug 05 04:58:08 PM PDT 24 76318842 ps
T310 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1795724571 Aug 05 04:58:02 PM PDT 24 Aug 05 04:58:07 PM PDT 24 787292343 ps
T3185 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3216880623 Aug 05 04:58:08 PM PDT 24 Aug 05 04:58:09 PM PDT 24 65969505 ps
T313 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.140594138 Aug 05 04:58:08 PM PDT 24 Aug 05 04:58:13 PM PDT 24 929618701 ps
T3186 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1453011844 Aug 05 04:57:52 PM PDT 24 Aug 05 04:57:53 PM PDT 24 106944984 ps
T3187 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1813038616 Aug 05 04:57:47 PM PDT 24 Aug 05 04:57:48 PM PDT 24 84759283 ps
T3188 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2410074237 Aug 05 04:58:03 PM PDT 24 Aug 05 04:58:05 PM PDT 24 86429572 ps
T3189 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1006592510 Aug 05 04:58:06 PM PDT 24 Aug 05 04:58:09 PM PDT 24 368254988 ps
T3190 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1632522130 Aug 05 04:57:54 PM PDT 24 Aug 05 04:57:55 PM PDT 24 49027194 ps
T3191 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.958388900 Aug 05 04:58:06 PM PDT 24 Aug 05 04:58:07 PM PDT 24 49412003 ps
T3192 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.68364153 Aug 05 04:58:12 PM PDT 24 Aug 05 04:58:12 PM PDT 24 29311065 ps
T3193 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.976651123 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:06 PM PDT 24 130415816 ps
T3194 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1576140746 Aug 05 04:57:56 PM PDT 24 Aug 05 04:57:58 PM PDT 24 210439542 ps
T3195 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.234054266 Aug 05 04:58:00 PM PDT 24 Aug 05 04:58:01 PM PDT 24 104081820 ps
T3196 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3769676119 Aug 05 04:57:58 PM PDT 24 Aug 05 04:57:59 PM PDT 24 62585968 ps
T316 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3931465548 Aug 05 04:57:41 PM PDT 24 Aug 05 04:57:44 PM PDT 24 385366633 ps
T315 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.452924633 Aug 05 04:57:59 PM PDT 24 Aug 05 04:58:02 PM PDT 24 661430824 ps
T3197 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3864913961 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:08 PM PDT 24 185228345 ps
T3198 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2523828062 Aug 05 04:57:59 PM PDT 24 Aug 05 04:58:00 PM PDT 24 109072429 ps
T3199 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2398594282 Aug 05 04:58:05 PM PDT 24 Aug 05 04:58:10 PM PDT 24 1481620849 ps
T3200 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4185131255 Aug 05 04:58:02 PM PDT 24 Aug 05 04:58:03 PM PDT 24 42131466 ps
T3201 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2969357770 Aug 05 04:57:45 PM PDT 24 Aug 05 04:57:52 PM PDT 24 153490160 ps
T317 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1725451778 Aug 05 04:58:01 PM PDT 24 Aug 05 04:58:07 PM PDT 24 905125308 ps
T3202 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.218359058 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:05 PM PDT 24 181556135 ps
T3203 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2647309205 Aug 05 04:58:12 PM PDT 24 Aug 05 04:58:13 PM PDT 24 47975555 ps
T3204 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3054574611 Aug 05 04:58:07 PM PDT 24 Aug 05 04:58:08 PM PDT 24 88638318 ps
T3205 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4151083929 Aug 05 04:57:40 PM PDT 24 Aug 05 04:57:41 PM PDT 24 45635682 ps
T266 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2191828380 Aug 05 04:57:40 PM PDT 24 Aug 05 04:57:43 PM PDT 24 121230379 ps
T267 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2589871322 Aug 05 04:57:50 PM PDT 24 Aug 05 04:57:52 PM PDT 24 122863850 ps
T3206 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1615602377 Aug 05 04:57:37 PM PDT 24 Aug 05 04:57:41 PM PDT 24 340083249 ps
T3207 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1515630467 Aug 05 04:57:58 PM PDT 24 Aug 05 04:57:59 PM PDT 24 93696781 ps
T3208 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.816119617 Aug 05 04:58:06 PM PDT 24 Aug 05 04:58:08 PM PDT 24 177304647 ps
T3209 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2870684190 Aug 05 04:58:12 PM PDT 24 Aug 05 04:58:13 PM PDT 24 73540217 ps
T3210 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4220478448 Aug 05 04:58:41 PM PDT 24 Aug 05 04:58:42 PM PDT 24 124367709 ps
T3211 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.674024087 Aug 05 04:58:07 PM PDT 24 Aug 05 04:58:07 PM PDT 24 39489768 ps
T268 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1867945708 Aug 05 04:57:52 PM PDT 24 Aug 05 04:57:55 PM PDT 24 92194568 ps
T3212 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2415831766 Aug 05 04:58:04 PM PDT 24 Aug 05 04:58:05 PM PDT 24 39257079 ps
T3213 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2878633368 Aug 05 04:57:52 PM PDT 24 Aug 05 04:57:54 PM PDT 24 336199628 ps
T3214 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2240315800 Aug 05 04:57:57 PM PDT 24 Aug 05 04:57:58 PM PDT 24 44503726 ps
T3215 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1596829270 Aug 05 04:58:24 PM PDT 24 Aug 05 04:58:25 PM PDT 24 82279627 ps
T318 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.322257654 Aug 05 04:58:11 PM PDT 24 Aug 05 04:58:14 PM PDT 24 407082339 ps
T3216 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4040549839 Aug 05 04:58:09 PM PDT 24 Aug 05 04:58:10 PM PDT 24 42366199 ps
T3217 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.708203354 Aug 05 04:57:43 PM PDT 24 Aug 05 04:57:45 PM PDT 24 181516266 ps
T3218 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3979168780 Aug 05 04:57:51 PM PDT 24 Aug 05 04:57:53 PM PDT 24 73934746 ps
T3219 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1670815153 Aug 05 04:57:41 PM PDT 24 Aug 05 04:57:44 PM PDT 24 178367569 ps
T3220 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3931209642 Aug 05 04:57:59 PM PDT 24 Aug 05 04:58:02 PM PDT 24 362570351 ps
T3221 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1111118263 Aug 05 04:57:52 PM PDT 24 Aug 05 04:57:56 PM PDT 24 369388370 ps
T3222 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1497793882 Aug 05 04:57:57 PM PDT 24 Aug 05 04:58:00 PM PDT 24 294701276 ps
T3223 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.106401575 Aug 05 04:57:51 PM PDT 24 Aug 05 04:57:53 PM PDT 24 184936062 ps
T3224 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4119672742 Aug 05 04:58:01 PM PDT 24 Aug 05 04:58:02 PM PDT 24 124411345 ps
T3225 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2934720198 Aug 05 04:58:18 PM PDT 24 Aug 05 04:58:19 PM PDT 24 63624061 ps
T3226 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2448808032 Aug 05 04:58:08 PM PDT 24 Aug 05 04:58:10 PM PDT 24 259735178 ps
T3227 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2144950559 Aug 05 04:58:00 PM PDT 24 Aug 05 04:58:04 PM PDT 24 1295072144 ps
T3228 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1267876280 Aug 05 04:57:46 PM PDT 24 Aug 05 04:57:47 PM PDT 24 46410219 ps
T3229 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2872530850 Aug 05 04:57:53 PM PDT 24 Aug 05 04:57:56 PM PDT 24 494170460 ps
T3230 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2138567220 Aug 05 04:57:49 PM PDT 24 Aug 05 04:57:52 PM PDT 24 256869019 ps
T3231 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.380996205 Aug 05 04:58:01 PM PDT 24 Aug 05 04:58:02 PM PDT 24 171431596 ps
T3232 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1160563085 Aug 05 04:58:08 PM PDT 24 Aug 05 04:58:10 PM PDT 24 191423313 ps
T3233 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3430518105 Aug 05 04:57:56 PM PDT 24 Aug 05 04:57:57 PM PDT 24 44907013 ps
T3234 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2369873587 Aug 05 04:58:13 PM PDT 24 Aug 05 04:58:15 PM PDT 24 118427293 ps


Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2629691802
Short name T30
Test name
Test status
Simulation time 462574135 ps
CPU time 1.39 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 207404 kb
Host smart-910705fb-0930-424a-a92b-fa1c28107794
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2629691802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2629691802
Directory /workspace/40.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1709725854
Short name T64
Test name
Test status
Simulation time 12682910770 ps
CPU time 340.37 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:38:52 PM PDT 24
Peak memory 215880 kb
Host smart-1a6c91c9-982a-440c-919e-f989020a86c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709725854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1709725854
Directory /workspace/1.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.4123236729
Short name T7
Test name
Test status
Simulation time 28753254697 ps
CPU time 31.58 seconds
Started Aug 05 05:35:15 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 207572 kb
Host smart-84e18791-784c-4b0a-9270-695986820b73
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123236729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.4123236729
Directory /workspace/12.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/31.usbdev_device_address.766692928
Short name T20
Test name
Test status
Simulation time 62420660710 ps
CPU time 89.47 seconds
Started Aug 05 05:38:05 PM PDT 24
Finished Aug 05 05:39:35 PM PDT 24
Peak memory 207616 kb
Host smart-bbadde9a-1dec-4f8d-935f-1a6fdb3879be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76669
2928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.766692928
Directory /workspace/31.usbdev_device_address/latest


Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3605976266
Short name T214
Test name
Test status
Simulation time 53455974 ps
CPU time 0.73 seconds
Started Aug 05 04:57:59 PM PDT 24
Finished Aug 05 04:58:00 PM PDT 24
Peak memory 206864 kb
Host smart-9606c4d3-5a23-4d71-90ff-116b68f465f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3605976266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3605976266
Directory /workspace/37.usbdev_intr_test/latest


Test location /workspace/coverage/default/13.usbdev_resume_link_active.4039075735
Short name T39
Test name
Test status
Simulation time 20158055111 ps
CPU time 25.11 seconds
Started Aug 05 05:35:30 PM PDT 24
Finished Aug 05 05:35:55 PM PDT 24
Peak memory 207464 kb
Host smart-355a540b-f99e-4b05-8d67-4dcdfe2d7917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40390
75735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.4039075735
Directory /workspace/13.usbdev_resume_link_active/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2007404275
Short name T233
Test name
Test status
Simulation time 219540583 ps
CPU time 1.88 seconds
Started Aug 05 04:57:51 PM PDT 24
Finished Aug 05 04:57:53 PM PDT 24
Peak memory 215456 kb
Host smart-e0b73309-c83d-4cf1-a77c-7868af093175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007404275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2007404275
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.1482172853
Short name T122
Test name
Test status
Simulation time 3402323188 ps
CPU time 31.79 seconds
Started Aug 05 05:34:49 PM PDT 24
Finished Aug 05 05:35:21 PM PDT 24
Peak memory 215880 kb
Host smart-36111cc4-53bb-4418-88a1-7f58cf7d22fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1482172853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.1482172853
Directory /workspace/9.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/1.usbdev_sec_cm.2283831211
Short name T200
Test name
Test status
Simulation time 920837623 ps
CPU time 2.04 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:13 PM PDT 24
Peak memory 224248 kb
Host smart-5a6b52bb-7025-4b9b-bc58-d30fd6468600
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2283831211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2283831211
Directory /workspace/1.usbdev_sec_cm/latest


Test location /workspace/coverage/default/19.usbdev_link_resume.3345862070
Short name T113
Test name
Test status
Simulation time 7683548636 ps
CPU time 9.96 seconds
Started Aug 05 05:36:19 PM PDT 24
Finished Aug 05 05:36:29 PM PDT 24
Peak memory 207624 kb
Host smart-89061086-a385-4433-831e-d118cef53b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33458
62070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3345862070
Directory /workspace/19.usbdev_link_resume/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3957490982
Short name T105
Test name
Test status
Simulation time 314248341 ps
CPU time 1.08 seconds
Started Aug 05 05:32:53 PM PDT 24
Finished Aug 05 05:32:54 PM PDT 24
Peak memory 207312 kb
Host smart-f3e6ab99-048d-414d-99d2-d05131b38b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39574
90982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3957490982
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest


Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.4056810500
Short name T27
Test name
Test status
Simulation time 49942447 ps
CPU time 0.73 seconds
Started Aug 05 05:35:08 PM PDT 24
Finished Aug 05 05:35:09 PM PDT 24
Peak memory 207288 kb
Host smart-8cb92d28-3ba9-409c-8704-af5279e4d13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40568
10500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.4056810500
Directory /workspace/10.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/13.usbdev_disconnected.3386635097
Short name T631
Test name
Test status
Simulation time 156561980 ps
CPU time 0.88 seconds
Started Aug 05 05:35:25 PM PDT 24
Finished Aug 05 05:35:26 PM PDT 24
Peak memory 207316 kb
Host smart-c1847858-9962-4f6b-a1fe-cfb92ad276eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33866
35097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3386635097
Directory /workspace/13.usbdev_disconnected/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.4228086740
Short name T305
Test name
Test status
Simulation time 48731963 ps
CPU time 0.73 seconds
Started Aug 05 04:58:05 PM PDT 24
Finished Aug 05 04:58:06 PM PDT 24
Peak memory 206864 kb
Host smart-ff055ae4-a00a-4e10-a077-b8a2844aeb3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4228086740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.4228086740
Directory /workspace/14.usbdev_intr_test/latest


Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1822205724
Short name T109
Test name
Test status
Simulation time 19145208325 ps
CPU time 20.11 seconds
Started Aug 05 05:33:02 PM PDT 24
Finished Aug 05 05:33:22 PM PDT 24
Peak memory 207560 kb
Host smart-88d9f958-3ae7-4a6f-82aa-4ff83e7fd272
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822205724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1822205724
Directory /workspace/1.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/1.usbdev_pkt_buffer.4235564126
Short name T241
Test name
Test status
Simulation time 23502469617 ps
CPU time 59.25 seconds
Started Aug 05 05:33:04 PM PDT 24
Finished Aug 05 05:34:03 PM PDT 24
Peak memory 215828 kb
Host smart-fe688298-8525-4c9d-ad01-c1f0741dfc35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42355
64126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.4235564126
Directory /workspace/1.usbdev_pkt_buffer/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3432917022
Short name T311
Test name
Test status
Simulation time 1010765507 ps
CPU time 4.68 seconds
Started Aug 05 04:58:07 PM PDT 24
Finished Aug 05 04:58:12 PM PDT 24
Peak memory 207288 kb
Host smart-91eaed64-f3fa-4112-a1b8-8e492349c268
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3432917022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3432917022
Directory /workspace/18.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.481607137
Short name T224
Test name
Test status
Simulation time 84311406 ps
CPU time 0.87 seconds
Started Aug 05 04:57:46 PM PDT 24
Finished Aug 05 04:57:47 PM PDT 24
Peak memory 207040 kb
Host smart-289e9bca-ab37-40d2-b253-a93e2fea68be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=481607137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.481607137
Directory /workspace/0.usbdev_csr_rw/latest


Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3029433023
Short name T13
Test name
Test status
Simulation time 5611481294 ps
CPU time 7.58 seconds
Started Aug 05 05:34:54 PM PDT 24
Finished Aug 05 05:35:01 PM PDT 24
Peak memory 215732 kb
Host smart-c74f2710-9a83-43ff-8c97-88c609ed17b2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029433023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.3029433023
Directory /workspace/10.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/26.usbdev_device_timeout.2487792786
Short name T488
Test name
Test status
Simulation time 5621745502 ps
CPU time 39.11 seconds
Started Aug 05 05:37:21 PM PDT 24
Finished Aug 05 05:38:00 PM PDT 24
Peak memory 207612 kb
Host smart-ec63cf72-ea5e-4e7e-8118-541f81754028
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487792786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.2487792786
Directory /workspace/26.usbdev_device_timeout/latest


Test location /workspace/coverage/default/17.usbdev_device_address.956678376
Short name T38
Test name
Test status
Simulation time 39560918283 ps
CPU time 69.85 seconds
Started Aug 05 05:35:58 PM PDT 24
Finished Aug 05 05:37:08 PM PDT 24
Peak memory 207536 kb
Host smart-1bed5b9c-14cb-4fbf-8565-6ee87a6ef996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95667
8376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.956678376
Directory /workspace/17.usbdev_device_address/latest


Test location /workspace/coverage/default/196.usbdev_endpoint_types.1602745577
Short name T363
Test name
Test status
Simulation time 618093257 ps
CPU time 1.49 seconds
Started Aug 05 05:41:02 PM PDT 24
Finished Aug 05 05:41:04 PM PDT 24
Peak memory 207220 kb
Host smart-acec9457-94af-49d4-90ba-e4d7acf4a17a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1602745577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.1602745577
Directory /workspace/196.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/40.usbdev_rx_full.1928945072
Short name T55
Test name
Test status
Simulation time 271204772 ps
CPU time 1.07 seconds
Started Aug 05 05:39:21 PM PDT 24
Finished Aug 05 05:39:22 PM PDT 24
Peak memory 207268 kb
Host smart-f8d94b2d-7f62-4d3b-95f3-66a7e3490585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19289
45072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.1928945072
Directory /workspace/40.usbdev_rx_full/latest


Test location /workspace/coverage/default/130.usbdev_endpoint_types.2980213036
Short name T21
Test name
Test status
Simulation time 988679721 ps
CPU time 2.23 seconds
Started Aug 05 05:40:29 PM PDT 24
Finished Aug 05 05:40:31 PM PDT 24
Peak memory 207240 kb
Host smart-f93362c9-8f83-4179-9ece-d030fee8b5fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2980213036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.2980213036
Directory /workspace/130.usbdev_endpoint_types/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.621921906
Short name T221
Test name
Test status
Simulation time 111782009 ps
CPU time 2.92 seconds
Started Aug 05 04:57:58 PM PDT 24
Finished Aug 05 04:58:01 PM PDT 24
Peak memory 222816 kb
Host smart-ca6e0a6d-aa26-4758-aa66-0dfab39592dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=621921906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.621921906
Directory /workspace/3.usbdev_tl_errors/latest


Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2824920756
Short name T78
Test name
Test status
Simulation time 158374396 ps
CPU time 0.83 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 207244 kb
Host smart-b2e9b70a-48a2-4b63-8756-e029ec36922c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28249
20756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2824920756
Directory /workspace/49.usbdev_bitstuff_err/latest


Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3791353869
Short name T304
Test name
Test status
Simulation time 44583860 ps
CPU time 0.69 seconds
Started Aug 05 04:58:17 PM PDT 24
Finished Aug 05 04:58:23 PM PDT 24
Peak memory 206836 kb
Host smart-5fe99d3f-e81f-4db4-a8db-eb75c97ca1e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3791353869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3791353869
Directory /workspace/30.usbdev_intr_test/latest


Test location /workspace/coverage/default/11.usbdev_endpoint_types.3329218657
Short name T390
Test name
Test status
Simulation time 752086453 ps
CPU time 1.93 seconds
Started Aug 05 05:35:09 PM PDT 24
Finished Aug 05 05:35:11 PM PDT 24
Peak memory 207244 kb
Host smart-d3ea3908-b41b-4fdf-8f20-87a3a4f65cac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3329218657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.3329218657
Directory /workspace/11.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/21.usbdev_device_address.55736841
Short name T94
Test name
Test status
Simulation time 25302030766 ps
CPU time 47.4 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 207640 kb
Host smart-d5d11465-f0d4-4685-ba6e-da0ed0f9a735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55736
841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.55736841
Directory /workspace/21.usbdev_device_address/latest


Test location /workspace/coverage/default/122.usbdev_endpoint_types.2308758493
Short name T399
Test name
Test status
Simulation time 413317052 ps
CPU time 1.26 seconds
Started Aug 05 05:40:48 PM PDT 24
Finished Aug 05 05:40:50 PM PDT 24
Peak memory 207292 kb
Host smart-21dc725c-e262-40dd-bf0a-2c9cd665dadd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2308758493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.2308758493
Directory /workspace/122.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/192.usbdev_endpoint_types.2872466837
Short name T341
Test name
Test status
Simulation time 821428551 ps
CPU time 1.86 seconds
Started Aug 05 05:40:46 PM PDT 24
Finished Aug 05 05:40:48 PM PDT 24
Peak memory 207368 kb
Host smart-07864f1d-3e38-43df-b539-e623f0695042
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2872466837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.2872466837
Directory /workspace/192.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/81.usbdev_endpoint_types.1467237651
Short name T348
Test name
Test status
Simulation time 871550674 ps
CPU time 1.87 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207296 kb
Host smart-8c2466d5-1959-402d-aa80-e49cb132286e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1467237651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.1467237651
Directory /workspace/81.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/10.usbdev_rx_crc_err.897506112
Short name T80
Test name
Test status
Simulation time 156569569 ps
CPU time 0.85 seconds
Started Aug 05 05:35:05 PM PDT 24
Finished Aug 05 05:35:06 PM PDT 24
Peak memory 207256 kb
Host smart-4d6ec9fe-31b0-455e-a528-3a0c7f719485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89750
6112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.897506112
Directory /workspace/10.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/100.usbdev_endpoint_types.755629059
Short name T402
Test name
Test status
Simulation time 680954092 ps
CPU time 1.6 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:32 PM PDT 24
Peak memory 207360 kb
Host smart-1eb07fd4-cf40-4c07-82b7-3dbe577ecf60
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=755629059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.755629059
Directory /workspace/100.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/48.usbdev_endpoint_types.2642595434
Short name T418
Test name
Test status
Simulation time 482597159 ps
CPU time 1.41 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207272 kb
Host smart-a4d544a9-1250-400e-9563-61bd669d7be3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2642595434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.2642595434
Directory /workspace/48.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/6.usbdev_endpoint_types.2178089569
Short name T115
Test name
Test status
Simulation time 417802504 ps
CPU time 1.36 seconds
Started Aug 05 05:34:10 PM PDT 24
Finished Aug 05 05:34:11 PM PDT 24
Peak memory 207372 kb
Host smart-16603810-9c50-4d18-8b92-6409d830013b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2178089569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.2178089569
Directory /workspace/6.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/21.usbdev_pkt_received.3597863239
Short name T48
Test name
Test status
Simulation time 184834222 ps
CPU time 0.94 seconds
Started Aug 05 05:36:45 PM PDT 24
Finished Aug 05 05:36:46 PM PDT 24
Peak memory 207380 kb
Host smart-e3f5db06-d0dc-4b0c-98d2-7e836b0daa58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35978
63239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3597863239
Directory /workspace/21.usbdev_pkt_received/latest


Test location /workspace/coverage/default/56.usbdev_endpoint_types.2188606568
Short name T407
Test name
Test status
Simulation time 597059031 ps
CPU time 1.5 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207300 kb
Host smart-3158db11-6a56-4566-9824-add79ed68564
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2188606568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.2188606568
Directory /workspace/56.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/64.usbdev_endpoint_types.1081880420
Short name T460
Test name
Test status
Simulation time 572920611 ps
CPU time 1.69 seconds
Started Aug 05 05:40:47 PM PDT 24
Finished Aug 05 05:40:49 PM PDT 24
Peak memory 207244 kb
Host smart-24c3a95f-9a50-4302-bffc-dd2014590f48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1081880420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.1081880420
Directory /workspace/64.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.311652002
Short name T165
Test name
Test status
Simulation time 3084868472 ps
CPU time 21.74 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:37:03 PM PDT 24
Peak memory 215832 kb
Host smart-bc2c56fb-7074-4ceb-a6e0-0480bf538f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
2002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.311652002
Directory /workspace/21.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/155.usbdev_endpoint_types.2834933540
Short name T361
Test name
Test status
Simulation time 468438656 ps
CPU time 1.26 seconds
Started Aug 05 05:40:46 PM PDT 24
Finished Aug 05 05:40:48 PM PDT 24
Peak memory 207452 kb
Host smart-ff49744c-d2fd-4e2b-ae82-d1721782e2cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2834933540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.2834933540
Directory /workspace/155.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/165.usbdev_endpoint_types.491659587
Short name T412
Test name
Test status
Simulation time 520879623 ps
CPU time 1.45 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207216 kb
Host smart-f407202a-e424-4254-9135-1344c1f1d5a9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=491659587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.491659587
Directory /workspace/165.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/177.usbdev_endpoint_types.1522454335
Short name T379
Test name
Test status
Simulation time 372268735 ps
CPU time 1.25 seconds
Started Aug 05 05:40:44 PM PDT 24
Finished Aug 05 05:40:46 PM PDT 24
Peak memory 207348 kb
Host smart-32c68afd-602f-445b-b6ce-6bb8c030002e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1522454335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.1522454335
Directory /workspace/177.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/46.usbdev_device_address.1033026455
Short name T186
Test name
Test status
Simulation time 57456133841 ps
CPU time 102.67 seconds
Started Aug 05 05:40:06 PM PDT 24
Finished Aug 05 05:41:49 PM PDT 24
Peak memory 207664 kb
Host smart-48bcfaed-8808-4e1b-be70-1beb5588f2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10330
26455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.1033026455
Directory /workspace/46.usbdev_device_address/latest


Test location /workspace/coverage/default/0.usbdev_setup_priority.3836282966
Short name T53
Test name
Test status
Simulation time 433711077 ps
CPU time 1.46 seconds
Started Aug 05 05:32:58 PM PDT 24
Finished Aug 05 05:32:59 PM PDT 24
Peak memory 207400 kb
Host smart-ecdd1e87-5466-4f45-858d-32bb8189bbd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38362
82966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3836282966
Directory /workspace/0.usbdev_setup_priority/latest


Test location /workspace/coverage/default/116.usbdev_endpoint_types.3802868934
Short name T344
Test name
Test status
Simulation time 585571671 ps
CPU time 1.52 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:34 PM PDT 24
Peak memory 207220 kb
Host smart-4c7dfe1d-2715-4b44-9187-49034bb0a8d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3802868934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.3802868934
Directory /workspace/116.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/176.usbdev_endpoint_types.1224170828
Short name T384
Test name
Test status
Simulation time 627417629 ps
CPU time 1.53 seconds
Started Aug 05 05:40:36 PM PDT 24
Finished Aug 05 05:40:38 PM PDT 24
Peak memory 207368 kb
Host smart-6067c69a-f236-43cf-9b5a-6e93d4839b05
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1224170828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.1224170828
Directory /workspace/176.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/186.usbdev_endpoint_types.1457995936
Short name T400
Test name
Test status
Simulation time 816203769 ps
CPU time 1.81 seconds
Started Aug 05 05:40:37 PM PDT 24
Finished Aug 05 05:40:39 PM PDT 24
Peak memory 207216 kb
Host smart-85198218-301a-4ab4-ab41-2962beca599b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1457995936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.1457995936
Directory /workspace/186.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/12.usbdev_alert_test.3052903164
Short name T840
Test name
Test status
Simulation time 32939913 ps
CPU time 0.73 seconds
Started Aug 05 05:35:23 PM PDT 24
Finished Aug 05 05:35:24 PM PDT 24
Peak memory 207416 kb
Host smart-ae34f27f-e49b-4444-8b3c-ca059a939ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3052903164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.3052903164
Directory /workspace/12.usbdev_alert_test/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.196906183
Short name T273
Test name
Test status
Simulation time 289168209 ps
CPU time 1.86 seconds
Started Aug 05 04:57:59 PM PDT 24
Finished Aug 05 04:58:01 PM PDT 24
Peak memory 207156 kb
Host smart-7c7e1d80-2b0d-48e8-9a15-5752f4affc42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=196906183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.196906183
Directory /workspace/13.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/default/0.usbdev_av_overflow.3141155633
Short name T102
Test name
Test status
Simulation time 139385169 ps
CPU time 0.81 seconds
Started Aug 05 05:32:51 PM PDT 24
Finished Aug 05 05:32:52 PM PDT 24
Peak memory 207332 kb
Host smart-71e88436-f43c-4d8f-b948-e49c7d8136de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31411
55633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3141155633
Directory /workspace/0.usbdev_av_overflow/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3208740254
Short name T309
Test name
Test status
Simulation time 330193278 ps
CPU time 2.52 seconds
Started Aug 05 04:57:51 PM PDT 24
Finished Aug 05 04:57:54 PM PDT 24
Peak memory 207176 kb
Host smart-1cc16734-16b9-4e98-a4a4-558f57a31c94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3208740254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3208740254
Directory /workspace/6.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/101.usbdev_endpoint_types.762702517
Short name T3035
Test name
Test status
Simulation time 224913194 ps
CPU time 0.94 seconds
Started Aug 05 05:40:50 PM PDT 24
Finished Aug 05 05:40:51 PM PDT 24
Peak memory 207556 kb
Host smart-72cbec85-4be4-4f37-aa57-2f5d53bff781
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=762702517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.762702517
Directory /workspace/101.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/169.usbdev_endpoint_types.350650867
Short name T339
Test name
Test status
Simulation time 289667447 ps
CPU time 1.06 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:32 PM PDT 24
Peak memory 207352 kb
Host smart-c6bd02a0-6a53-4bcc-85a4-82112b7e8df2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=350650867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.350650867
Directory /workspace/169.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/187.usbdev_endpoint_types.98248037
Short name T417
Test name
Test status
Simulation time 385369696 ps
CPU time 1.21 seconds
Started Aug 05 05:40:43 PM PDT 24
Finished Aug 05 05:40:44 PM PDT 24
Peak memory 207312 kb
Host smart-fe4bf12b-826b-4310-8498-e8cf9b6707d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=98248037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.98248037
Directory /workspace/187.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/83.usbdev_endpoint_types.566816174
Short name T373
Test name
Test status
Simulation time 800384288 ps
CPU time 2.06 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207300 kb
Host smart-90149543-ae5c-4a82-84a1-6ce0fc9360c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=566816174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.566816174
Directory /workspace/83.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2833577694
Short name T75
Test name
Test status
Simulation time 487166784 ps
CPU time 1.62 seconds
Started Aug 05 05:32:44 PM PDT 24
Finished Aug 05 05:32:46 PM PDT 24
Peak memory 207372 kb
Host smart-e0bcb8c0-e58b-46c1-80db-f603aba71cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28335
77694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2833577694
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest


Test location /workspace/coverage/default/40.usbdev_endpoint_types.2967722318
Short name T375
Test name
Test status
Simulation time 494191647 ps
CPU time 1.44 seconds
Started Aug 05 05:39:00 PM PDT 24
Finished Aug 05 05:39:02 PM PDT 24
Peak memory 207224 kb
Host smart-96ad4049-faac-4190-a542-e3a8c8cab46b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2967722318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.2967722318
Directory /workspace/40.usbdev_endpoint_types/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3584824914
Short name T256
Test name
Test status
Simulation time 755878941 ps
CPU time 5.91 seconds
Started Aug 05 04:57:52 PM PDT 24
Finished Aug 05 04:57:58 PM PDT 24
Peak memory 207096 kb
Host smart-7418a499-d7f0-433c-a3a7-0a0d590a9637
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3584824914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3584824914
Directory /workspace/0.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2593370494
Short name T303
Test name
Test status
Simulation time 39053482 ps
CPU time 0.68 seconds
Started Aug 05 04:58:13 PM PDT 24
Finished Aug 05 04:58:13 PM PDT 24
Peak memory 206752 kb
Host smart-e9df92a8-9a52-45ba-aba4-46649e0d1d61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2593370494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2593370494
Directory /workspace/11.usbdev_intr_test/latest


Test location /workspace/coverage/default/1.usbdev_freq_hiclk.3562311497
Short name T484
Test name
Test status
Simulation time 102236129642 ps
CPU time 162.9 seconds
Started Aug 05 05:33:05 PM PDT 24
Finished Aug 05 05:35:48 PM PDT 24
Peak memory 207504 kb
Host smart-3faf1e94-650b-49b2-a5c4-4bf0dd986fbc
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3562311497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.3562311497
Directory /workspace/1.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/173.usbdev_endpoint_types.1739540220
Short name T473
Test name
Test status
Simulation time 649027133 ps
CPU time 1.49 seconds
Started Aug 05 05:40:39 PM PDT 24
Finished Aug 05 05:40:41 PM PDT 24
Peak memory 207444 kb
Host smart-74dd5a82-32d7-41ac-ae3e-27ef5c1643bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1739540220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.1739540220
Directory /workspace/173.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/188.usbdev_endpoint_types.4019298994
Short name T419
Test name
Test status
Simulation time 393869825 ps
CPU time 1.43 seconds
Started Aug 05 05:40:54 PM PDT 24
Finished Aug 05 05:40:55 PM PDT 24
Peak memory 207348 kb
Host smart-6d829d82-ce9f-49e6-8262-9c2751aef4a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4019298994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.4019298994
Directory /workspace/188.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/194.usbdev_endpoint_types.1243088317
Short name T416
Test name
Test status
Simulation time 361092872 ps
CPU time 1.21 seconds
Started Aug 05 05:40:57 PM PDT 24
Finished Aug 05 05:40:59 PM PDT 24
Peak memory 207244 kb
Host smart-f0c20745-51ff-4334-ab13-0b337f1c831b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1243088317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.1243088317
Directory /workspace/194.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/58.usbdev_endpoint_types.1252448950
Short name T352
Test name
Test status
Simulation time 667866098 ps
CPU time 1.63 seconds
Started Aug 05 05:40:45 PM PDT 24
Finished Aug 05 05:40:47 PM PDT 24
Peak memory 207284 kb
Host smart-92e63bdb-9eaa-45ca-976e-a58cb50810a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1252448950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.1252448950
Directory /workspace/58.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/10.usbdev_nak_trans.2633319712
Short name T150
Test name
Test status
Simulation time 211798476 ps
CPU time 0.97 seconds
Started Aug 05 05:35:02 PM PDT 24
Finished Aug 05 05:35:04 PM PDT 24
Peak memory 207336 kb
Host smart-01ea1d35-a2a5-42dd-b597-8c49799e1590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26333
19712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2633319712
Directory /workspace/10.usbdev_nak_trans/latest


Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3238795534
Short name T157
Test name
Test status
Simulation time 3705905301 ps
CPU time 111.34 seconds
Started Aug 05 05:34:21 PM PDT 24
Finished Aug 05 05:36:12 PM PDT 24
Peak memory 218156 kb
Host smart-29d52df6-faeb-4af5-b9cc-d85aca44ea71
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3238795534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3238795534
Directory /workspace/6.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/37.usbdev_device_address.2973715682
Short name T2222
Test name
Test status
Simulation time 48301306290 ps
CPU time 75.8 seconds
Started Aug 05 05:38:46 PM PDT 24
Finished Aug 05 05:40:02 PM PDT 24
Peak memory 207660 kb
Host smart-808376f0-75bc-4e74-aac5-fc795849cb5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29737
15682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.2973715682
Directory /workspace/37.usbdev_device_address/latest


Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.4096287506
Short name T121
Test name
Test status
Simulation time 17137079135 ps
CPU time 412.52 seconds
Started Aug 05 05:33:37 PM PDT 24
Finished Aug 05 05:40:30 PM PDT 24
Peak memory 215820 kb
Host smart-4551f79a-0e4b-4aa8-aefb-3aff8cc89383
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096287506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.4096287506
Directory /workspace/3.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.322257654
Short name T318
Test name
Test status
Simulation time 407082339 ps
CPU time 2.55 seconds
Started Aug 05 04:58:11 PM PDT 24
Finished Aug 05 04:58:14 PM PDT 24
Peak memory 207268 kb
Host smart-b9725977-c4d5-4944-b812-8abe3aade21c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=322257654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.322257654
Directory /workspace/15.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3211882120
Short name T314
Test name
Test status
Simulation time 356413232 ps
CPU time 2.48 seconds
Started Aug 05 04:58:00 PM PDT 24
Finished Aug 05 04:58:03 PM PDT 24
Peak memory 207152 kb
Host smart-a6c38b26-c6d7-4076-adc4-91abc3f00e28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3211882120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3211882120
Directory /workspace/7.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.2770650509
Short name T479
Test name
Test status
Simulation time 19485491128 ps
CPU time 20.1 seconds
Started Aug 05 05:32:48 PM PDT 24
Finished Aug 05 05:33:09 PM PDT 24
Peak memory 207588 kb
Host smart-38db49c6-e0dd-49af-b49b-3d56efbf41a8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770650509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2770650509
Directory /workspace/0.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1681804922
Short name T482
Test name
Test status
Simulation time 5134291864 ps
CPU time 49.57 seconds
Started Aug 05 05:32:50 PM PDT 24
Finished Aug 05 05:33:40 PM PDT 24
Peak memory 215812 kb
Host smart-120b8b92-d5e1-4ac8-be7d-c051f2ddb96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16818
04922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1681804922
Directory /workspace/0.usbdev_dpi_config_host/latest


Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.561526285
Short name T489
Test name
Test status
Simulation time 192727552 ps
CPU time 0.95 seconds
Started Aug 05 05:32:50 PM PDT 24
Finished Aug 05 05:32:51 PM PDT 24
Peak memory 207324 kb
Host smart-685634f4-d1c5-4880-a7ea-5eef31e19370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56152
6285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.561526285
Directory /workspace/0.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1740325756
Short name T293
Test name
Test status
Simulation time 172702843 ps
CPU time 0.9 seconds
Started Aug 05 05:32:56 PM PDT 24
Finished Aug 05 05:32:57 PM PDT 24
Peak memory 207324 kb
Host smart-d4956656-7404-49fd-9baa-87e6321b0b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17403
25756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1740325756
Directory /workspace/0.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/1.usbdev_endpoint_types.2374427876
Short name T430
Test name
Test status
Simulation time 181197671 ps
CPU time 0.95 seconds
Started Aug 05 05:32:57 PM PDT 24
Finished Aug 05 05:32:58 PM PDT 24
Peak memory 207356 kb
Host smart-c526bc5f-7d6a-4c0c-aa56-92781dc5f708
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2374427876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.2374427876
Directory /workspace/1.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/10.usbdev_endpoint_types.3866543276
Short name T330
Test name
Test status
Simulation time 346631350 ps
CPU time 1.24 seconds
Started Aug 05 05:34:57 PM PDT 24
Finished Aug 05 05:34:58 PM PDT 24
Peak memory 207244 kb
Host smart-024d74fa-64b3-466a-a316-95c3b6b4472f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3866543276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.3866543276
Directory /workspace/10.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/10.usbdev_rx_full.4158319728
Short name T3028
Test name
Test status
Simulation time 285866985 ps
CPU time 1.17 seconds
Started Aug 05 05:35:03 PM PDT 24
Finished Aug 05 05:35:04 PM PDT 24
Peak memory 207460 kb
Host smart-76c8d5be-f259-426a-bee2-21f237465833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41583
19728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.4158319728
Directory /workspace/10.usbdev_rx_full/latest


Test location /workspace/coverage/default/103.usbdev_endpoint_types.1822089928
Short name T298
Test name
Test status
Simulation time 792919340 ps
CPU time 1.86 seconds
Started Aug 05 05:40:39 PM PDT 24
Finished Aug 05 05:40:41 PM PDT 24
Peak memory 207320 kb
Host smart-7ec9fb3d-8e0a-4109-8eee-6174d5fd3ac0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1822089928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.1822089928
Directory /workspace/103.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/104.usbdev_endpoint_types.2088736897
Short name T465
Test name
Test status
Simulation time 554091856 ps
CPU time 1.46 seconds
Started Aug 05 05:40:40 PM PDT 24
Finished Aug 05 05:40:41 PM PDT 24
Peak memory 207300 kb
Host smart-27d8d5ef-601a-402c-b666-ad4e2bd268e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2088736897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.2088736897
Directory /workspace/104.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/108.usbdev_endpoint_types.3063908681
Short name T447
Test name
Test status
Simulation time 404621157 ps
CPU time 1.25 seconds
Started Aug 05 05:40:44 PM PDT 24
Finished Aug 05 05:40:45 PM PDT 24
Peak memory 207444 kb
Host smart-e06b1517-e512-436a-a8ac-f8a27050c767
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3063908681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.3063908681
Directory /workspace/108.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/112.usbdev_endpoint_types.1572916278
Short name T2628
Test name
Test status
Simulation time 422671983 ps
CPU time 1.35 seconds
Started Aug 05 05:40:26 PM PDT 24
Finished Aug 05 05:40:28 PM PDT 24
Peak memory 207372 kb
Host smart-b3c07b12-7364-4362-b4ed-934614aa5df5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1572916278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.1572916278
Directory /workspace/112.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/117.usbdev_endpoint_types.1987841089
Short name T432
Test name
Test status
Simulation time 647165104 ps
CPU time 1.79 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207244 kb
Host smart-c1450edc-3f64-4142-89dc-727f0e587d4b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1987841089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.1987841089
Directory /workspace/117.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/181.usbdev_endpoint_types.1986064639
Short name T2107
Test name
Test status
Simulation time 642966225 ps
CPU time 1.59 seconds
Started Aug 05 05:40:48 PM PDT 24
Finished Aug 05 05:40:50 PM PDT 24
Peak memory 207368 kb
Host smart-5c96da30-24c1-43cc-9dc3-420278f888c6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1986064639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.1986064639
Directory /workspace/181.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/19.usbdev_rx_full.2547152815
Short name T292
Test name
Test status
Simulation time 353472870 ps
CPU time 1.33 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:36:27 PM PDT 24
Peak memory 207396 kb
Host smart-6bf2e8ca-3555-4438-9215-ba3a3449349f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25471
52815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.2547152815
Directory /workspace/19.usbdev_rx_full/latest


Test location /workspace/coverage/default/191.usbdev_endpoint_types.137936563
Short name T420
Test name
Test status
Simulation time 290929882 ps
CPU time 1.2 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:41:01 PM PDT 24
Peak memory 207372 kb
Host smart-16d4df32-eaf6-458b-92d0-1e076e232bae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=137936563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.137936563
Directory /workspace/191.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/193.usbdev_endpoint_types.51223222
Short name T468
Test name
Test status
Simulation time 475555529 ps
CPU time 1.29 seconds
Started Aug 05 05:40:42 PM PDT 24
Finished Aug 05 05:40:43 PM PDT 24
Peak memory 207340 kb
Host smart-426718e3-9561-452e-8537-77b1e9eb7b83
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=51223222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.51223222
Directory /workspace/193.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/198.usbdev_endpoint_types.1418231630
Short name T371
Test name
Test status
Simulation time 877604674 ps
CPU time 2.06 seconds
Started Aug 05 05:40:54 PM PDT 24
Finished Aug 05 05:40:56 PM PDT 24
Peak memory 207320 kb
Host smart-35f09eae-cddb-43c9-836e-bba4ef31f714
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1418231630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.1418231630
Directory /workspace/198.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/22.usbdev_rx_full.1606876603
Short name T286
Test name
Test status
Simulation time 263161299 ps
CPU time 1.1 seconds
Started Aug 05 05:36:47 PM PDT 24
Finished Aug 05 05:36:49 PM PDT 24
Peak memory 207308 kb
Host smart-0f296a8e-0c1f-4d5a-89f9-6e6558dee57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16068
76603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.1606876603
Directory /workspace/22.usbdev_rx_full/latest


Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.4027672681
Short name T326
Test name
Test status
Simulation time 3172896635 ps
CPU time 24.15 seconds
Started Aug 05 05:37:42 PM PDT 24
Finished Aug 05 05:38:07 PM PDT 24
Peak memory 215864 kb
Host smart-da4b85f7-7089-45f4-8435-05b4fe234d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40276
72681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.4027672681
Directory /workspace/29.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.2986412330
Short name T325
Test name
Test status
Simulation time 4686391538 ps
CPU time 44.9 seconds
Started Aug 05 05:39:01 PM PDT 24
Finished Aug 05 05:39:46 PM PDT 24
Peak memory 224092 kb
Host smart-6a39a12c-d4fe-4261-bb49-87e9c22e6c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29864
12330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2986412330
Directory /workspace/40.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/59.usbdev_endpoint_types.237163713
Short name T355
Test name
Test status
Simulation time 578224720 ps
CPU time 1.58 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207300 kb
Host smart-b1cc968b-eba6-42bc-9fb7-6ae13a0453e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=237163713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.237163713
Directory /workspace/59.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1724977398
Short name T664
Test name
Test status
Simulation time 146346999 ps
CPU time 0.84 seconds
Started Aug 05 05:32:51 PM PDT 24
Finished Aug 05 05:32:52 PM PDT 24
Peak memory 207344 kb
Host smart-061382d9-5134-409f-bc47-7d0a4a813a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17249
77398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1724977398
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.948411066
Short name T195
Test name
Test status
Simulation time 26234322560 ps
CPU time 34.43 seconds
Started Aug 05 05:36:19 PM PDT 24
Finished Aug 05 05:36:54 PM PDT 24
Peak memory 215740 kb
Host smart-11e3b14a-0adc-404f-9a96-eedff42502f8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948411066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_resume.948411066
Directory /workspace/19.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1965625995
Short name T240
Test name
Test status
Simulation time 83470000 ps
CPU time 1.8 seconds
Started Aug 05 04:58:03 PM PDT 24
Finished Aug 05 04:58:05 PM PDT 24
Peak memory 207224 kb
Host smart-319be528-ab99-4e02-87b3-8e4e28d87352
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1965625995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1965625995
Directory /workspace/18.usbdev_tl_errors/latest


Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.675465108
Short name T1614
Test name
Test status
Simulation time 42390955 ps
CPU time 0.69 seconds
Started Aug 05 05:32:50 PM PDT 24
Finished Aug 05 05:32:51 PM PDT 24
Peak memory 207312 kb
Host smart-da1083fd-18c2-41c1-8116-4062afc6db30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67546
5108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.675465108
Directory /workspace/0.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/1.usbdev_av_overflow.3753450120
Short name T67
Test name
Test status
Simulation time 156896614 ps
CPU time 0.83 seconds
Started Aug 05 05:32:57 PM PDT 24
Finished Aug 05 05:32:58 PM PDT 24
Peak memory 207348 kb
Host smart-ac7c6329-a482-4b0b-8c01-7b7aac5de9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37534
50120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.3753450120
Directory /workspace/1.usbdev_av_overflow/latest


Test location /workspace/coverage/default/16.usbdev_invalid_sync.1539366308
Short name T541
Test name
Test status
Simulation time 5073974256 ps
CPU time 40.22 seconds
Started Aug 05 05:35:54 PM PDT 24
Finished Aug 05 05:36:34 PM PDT 24
Peak memory 224028 kb
Host smart-47420d8b-e418-4121-9c93-d93c1e26688c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1539366308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.1539366308
Directory /workspace/16.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1159759753
Short name T83
Test name
Test status
Simulation time 4972218252 ps
CPU time 33.83 seconds
Started Aug 05 05:33:28 PM PDT 24
Finished Aug 05 05:34:02 PM PDT 24
Peak memory 218468 kb
Host smart-7a400ec4-c0d0-4d1c-a553-bd87463226c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159759753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1159759753
Directory /workspace/2.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/0.usbdev_av_empty.1027559843
Short name T50
Test name
Test status
Simulation time 187668085 ps
CPU time 0.92 seconds
Started Aug 05 05:32:45 PM PDT 24
Finished Aug 05 05:32:46 PM PDT 24
Peak memory 207328 kb
Host smart-a02844ba-4821-4738-afb7-0b83484dbea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10275
59843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.1027559843
Directory /workspace/0.usbdev_av_empty/latest


Test location /workspace/coverage/default/0.usbdev_host_lost.4090665510
Short name T72
Test name
Test status
Simulation time 4170267087 ps
CPU time 10.53 seconds
Started Aug 05 05:32:45 PM PDT 24
Finished Aug 05 05:32:55 PM PDT 24
Peak memory 207712 kb
Host smart-e527ea1d-7d65-4780-b9b4-ff55d12aeefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40906
65510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.4090665510
Directory /workspace/0.usbdev_host_lost/latest


Test location /workspace/coverage/default/0.usbdev_link_reset.3420162324
Short name T73
Test name
Test status
Simulation time 170843826 ps
CPU time 0.87 seconds
Started Aug 05 05:32:49 PM PDT 24
Finished Aug 05 05:32:49 PM PDT 24
Peak memory 207332 kb
Host smart-0c61f13c-4e9a-43f9-9409-5fa6f76b6281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34201
62324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.3420162324
Directory /workspace/0.usbdev_link_reset/latest


Test location /workspace/coverage/default/0.usbdev_rx_pid_err.475723028
Short name T2820
Test name
Test status
Simulation time 198576378 ps
CPU time 0.93 seconds
Started Aug 05 05:33:02 PM PDT 24
Finished Aug 05 05:33:03 PM PDT 24
Peak memory 207288 kb
Host smart-39b04d5b-df69-47d4-9659-fd8c3429d74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47572
3028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.475723028
Directory /workspace/0.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/2.usbdev_av_empty.3902076230
Short name T62
Test name
Test status
Simulation time 153965810 ps
CPU time 0.85 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:12 PM PDT 24
Peak memory 207308 kb
Host smart-e254e4b1-7cde-4637-b8f8-89e94fa0040c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39020
76230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3902076230
Directory /workspace/2.usbdev_av_empty/latest


Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.4084488876
Short name T1643
Test name
Test status
Simulation time 2029993433 ps
CPU time 54.06 seconds
Started Aug 05 05:32:52 PM PDT 24
Finished Aug 05 05:33:46 PM PDT 24
Peak memory 223844 kb
Host smart-893f2b36-8e4b-46d8-a20a-f14aa969bb55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4084488876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.4084488876
Directory /workspace/0.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/0.usbdev_nak_trans.3647146988
Short name T128
Test name
Test status
Simulation time 191810775 ps
CPU time 0.93 seconds
Started Aug 05 05:32:53 PM PDT 24
Finished Aug 05 05:32:54 PM PDT 24
Peak memory 207368 kb
Host smart-7ab77902-f894-4ade-99a7-77a858160fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36471
46988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3647146988
Directory /workspace/0.usbdev_nak_trans/latest


Test location /workspace/coverage/default/1.usbdev_nak_trans.1462719903
Short name T155
Test name
Test status
Simulation time 229676770 ps
CPU time 0.99 seconds
Started Aug 05 05:33:07 PM PDT 24
Finished Aug 05 05:33:08 PM PDT 24
Peak memory 207344 kb
Host smart-8540ceb0-730f-4e2c-98c9-015d715d7948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14627
19903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1462719903
Directory /workspace/1.usbdev_nak_trans/latest


Test location /workspace/coverage/default/11.usbdev_fifo_rst.887896922
Short name T775
Test name
Test status
Simulation time 274027511 ps
CPU time 1.6 seconds
Started Aug 05 05:35:11 PM PDT 24
Finished Aug 05 05:35:12 PM PDT 24
Peak memory 207488 kb
Host smart-88090e82-3a27-4a6f-9af6-10854efb56aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88789
6922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.887896922
Directory /workspace/11.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/12.usbdev_nak_trans.4291744600
Short name T1967
Test name
Test status
Simulation time 201817316 ps
CPU time 0.97 seconds
Started Aug 05 05:35:17 PM PDT 24
Finished Aug 05 05:35:18 PM PDT 24
Peak memory 207368 kb
Host smart-08381354-53b3-4550-b4ce-838b9e6df72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42917
44600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.4291744600
Directory /workspace/12.usbdev_nak_trans/latest


Test location /workspace/coverage/default/13.usbdev_nak_trans.123946608
Short name T2750
Test name
Test status
Simulation time 231604578 ps
CPU time 0.96 seconds
Started Aug 05 05:35:34 PM PDT 24
Finished Aug 05 05:35:35 PM PDT 24
Peak memory 207244 kb
Host smart-2f2cfc46-67de-4302-9a82-8a66894eb795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12394
6608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.123946608
Directory /workspace/13.usbdev_nak_trans/latest


Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.3587672631
Short name T42
Test name
Test status
Simulation time 93910231 ps
CPU time 0.75 seconds
Started Aug 05 05:35:30 PM PDT 24
Finished Aug 05 05:35:31 PM PDT 24
Peak memory 207228 kb
Host smart-8b68d021-f0f6-42b0-9bd4-b184b0b8b8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35876
72631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.3587672631
Directory /workspace/13.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/14.usbdev_iso_retraction.3003442809
Short name T1027
Test name
Test status
Simulation time 4596254356 ps
CPU time 49.62 seconds
Started Aug 05 05:35:38 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207640 kb
Host smart-b8b28f51-f108-4f95-86c8-bfb45b2ccf1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3003442809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.3003442809
Directory /workspace/14.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/14.usbdev_nak_trans.524661662
Short name T137
Test name
Test status
Simulation time 195676376 ps
CPU time 0.91 seconds
Started Aug 05 05:35:36 PM PDT 24
Finished Aug 05 05:35:36 PM PDT 24
Peak memory 207272 kb
Host smart-e0a6ba68-d2bc-4c7e-81b3-e20cbe01c9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52466
1662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.524661662
Directory /workspace/14.usbdev_nak_trans/latest


Test location /workspace/coverage/default/16.usbdev_nak_trans.1975433116
Short name T152
Test name
Test status
Simulation time 204781195 ps
CPU time 0.94 seconds
Started Aug 05 05:35:55 PM PDT 24
Finished Aug 05 05:35:57 PM PDT 24
Peak memory 207312 kb
Host smart-0caad6d6-a4c9-4b47-ad0e-c3e4e4759d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
33116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1975433116
Directory /workspace/16.usbdev_nak_trans/latest


Test location /workspace/coverage/default/17.usbdev_nak_trans.1747992696
Short name T1883
Test name
Test status
Simulation time 177971281 ps
CPU time 0.86 seconds
Started Aug 05 05:36:08 PM PDT 24
Finished Aug 05 05:36:08 PM PDT 24
Peak memory 207340 kb
Host smart-4af52328-20a2-4b60-bac7-88122eef7dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17479
92696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1747992696
Directory /workspace/17.usbdev_nak_trans/latest


Test location /workspace/coverage/default/21.usbdev_nak_trans.3999621542
Short name T134
Test name
Test status
Simulation time 312404452 ps
CPU time 1.03 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:36:43 PM PDT 24
Peak memory 207364 kb
Host smart-69fad2f6-ed83-4c54-a0eb-4b17ee05a97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39996
21542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3999621542
Directory /workspace/21.usbdev_nak_trans/latest


Test location /workspace/coverage/default/25.usbdev_nak_trans.3319720517
Short name T139
Test name
Test status
Simulation time 236385707 ps
CPU time 0.97 seconds
Started Aug 05 05:37:10 PM PDT 24
Finished Aug 05 05:37:11 PM PDT 24
Peak memory 207344 kb
Host smart-620f0519-8646-4323-bfcc-a6fa5a0fc514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33197
20517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3319720517
Directory /workspace/25.usbdev_nak_trans/latest


Test location /workspace/coverage/default/3.usbdev_nak_trans.3243786234
Short name T131
Test name
Test status
Simulation time 185505362 ps
CPU time 0.92 seconds
Started Aug 05 05:33:34 PM PDT 24
Finished Aug 05 05:33:35 PM PDT 24
Peak memory 207408 kb
Host smart-d0e6437d-7d9f-4ca9-9768-9a692c8670cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32437
86234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3243786234
Directory /workspace/3.usbdev_nak_trans/latest


Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.2492703097
Short name T176
Test name
Test status
Simulation time 7254589919 ps
CPU time 43.8 seconds
Started Aug 05 05:33:52 PM PDT 24
Finished Aug 05 05:34:36 PM PDT 24
Peak memory 219428 kb
Host smart-c0b5c27b-3630-4088-bb3f-3b4a8660dbe3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492703097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.2492703097
Directory /workspace/4.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/9.usbdev_nak_trans.2986070057
Short name T145
Test name
Test status
Simulation time 238263812 ps
CPU time 1.08 seconds
Started Aug 05 05:34:47 PM PDT 24
Finished Aug 05 05:34:48 PM PDT 24
Peak memory 207396 kb
Host smart-47dedb66-7eb5-4677-8025-5bd7d617df21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29860
70057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2986070057
Directory /workspace/9.usbdev_nak_trans/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2223208500
Short name T3170
Test name
Test status
Simulation time 223699420 ps
CPU time 2.23 seconds
Started Aug 05 04:57:49 PM PDT 24
Finished Aug 05 04:57:52 PM PDT 24
Peak memory 207172 kb
Host smart-a5e82953-6b0e-4597-ab3f-18cedab2c5ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2223208500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2223208500
Directory /workspace/0.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3787181802
Short name T3166
Test name
Test status
Simulation time 181349389 ps
CPU time 0.98 seconds
Started Aug 05 04:57:50 PM PDT 24
Finished Aug 05 04:57:51 PM PDT 24
Peak memory 206900 kb
Host smart-adae439e-5f1f-482e-b3ba-278f93c3f0fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3787181802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3787181802
Directory /workspace/0.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2969357770
Short name T3201
Test name
Test status
Simulation time 153490160 ps
CPU time 1.98 seconds
Started Aug 05 04:57:45 PM PDT 24
Finished Aug 05 04:57:52 PM PDT 24
Peak memory 223428 kb
Host smart-505e802a-c440-4b08-9afb-4abeb7df1d18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969357770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2969357770
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.674024087
Short name T3211
Test name
Test status
Simulation time 39489768 ps
CPU time 0.68 seconds
Started Aug 05 04:58:07 PM PDT 24
Finished Aug 05 04:58:07 PM PDT 24
Peak memory 206864 kb
Host smart-670468c5-a84e-4218-ac75-f119dcbe633b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=674024087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.674024087
Directory /workspace/0.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.802866408
Short name T262
Test name
Test status
Simulation time 55000567 ps
CPU time 1.38 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:58 PM PDT 24
Peak memory 215332 kb
Host smart-52aef6a9-c7bd-465c-aa6d-0b660928ceb7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=802866408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.802866408
Directory /workspace/0.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2217818551
Short name T3134
Test name
Test status
Simulation time 289911203 ps
CPU time 2.57 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:59 PM PDT 24
Peak memory 207068 kb
Host smart-93c08db4-f44b-4d8b-9e80-553b4c7d1aca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2217818551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2217818551
Directory /workspace/0.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.708203354
Short name T3217
Test name
Test status
Simulation time 181516266 ps
CPU time 1.61 seconds
Started Aug 05 04:57:43 PM PDT 24
Finished Aug 05 04:57:45 PM PDT 24
Peak memory 207368 kb
Host smart-d3a0818a-39af-4e37-9c5a-103ce09da73d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=708203354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.708203354
Directory /workspace/0.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2648385299
Short name T223
Test name
Test status
Simulation time 188776595 ps
CPU time 1.87 seconds
Started Aug 05 04:57:48 PM PDT 24
Finished Aug 05 04:57:50 PM PDT 24
Peak memory 207264 kb
Host smart-e98c227f-8ffd-4c59-90a1-d37544fd9cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2648385299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2648385299
Directory /workspace/0.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.452924633
Short name T315
Test name
Test status
Simulation time 661430824 ps
CPU time 2.87 seconds
Started Aug 05 04:57:59 PM PDT 24
Finished Aug 05 04:58:02 PM PDT 24
Peak memory 207224 kb
Host smart-e5af2478-f281-40cc-be4d-8c8d82fabd25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=452924633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.452924633
Directory /workspace/0.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2118100906
Short name T3153
Test name
Test status
Simulation time 131038685 ps
CPU time 3.23 seconds
Started Aug 05 04:57:59 PM PDT 24
Finished Aug 05 04:58:02 PM PDT 24
Peak memory 207148 kb
Host smart-3b8f1dc1-e42e-480c-9206-0251cbb8cb29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2118100906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2118100906
Directory /workspace/1.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3675230263
Short name T3169
Test name
Test status
Simulation time 2569558096 ps
CPU time 11 seconds
Started Aug 05 04:58:03 PM PDT 24
Finished Aug 05 04:58:14 PM PDT 24
Peak memory 207444 kb
Host smart-13b544e8-2023-4a2c-8029-e4a8a64e28d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3675230263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3675230263
Directory /workspace/1.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2878633368
Short name T3213
Test name
Test status
Simulation time 336199628 ps
CPU time 1.28 seconds
Started Aug 05 04:57:52 PM PDT 24
Finished Aug 05 04:57:54 PM PDT 24
Peak memory 206916 kb
Host smart-a0ad4eec-4c5d-418c-85f2-648a3d57b2b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2878633368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2878633368
Directory /workspace/1.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1488226056
Short name T3182
Test name
Test status
Simulation time 109260973 ps
CPU time 2.49 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:59 PM PDT 24
Peak memory 215404 kb
Host smart-ea58c56a-fd4c-40d8-b076-9e5a13ba1328
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488226056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1488226056
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.760181407
Short name T272
Test name
Test status
Simulation time 74721774 ps
CPU time 0.88 seconds
Started Aug 05 04:57:40 PM PDT 24
Finished Aug 05 04:57:41 PM PDT 24
Peak memory 207032 kb
Host smart-89259483-6e5c-4b18-9345-dd57cf303628
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=760181407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.760181407
Directory /workspace/1.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3156732883
Short name T3138
Test name
Test status
Simulation time 49587608 ps
CPU time 0.76 seconds
Started Aug 05 04:57:54 PM PDT 24
Finished Aug 05 04:57:55 PM PDT 24
Peak memory 206864 kb
Host smart-49b2bea9-bb7f-4d49-bd77-f1643fc69120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3156732883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3156732883
Directory /workspace/1.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3459842444
Short name T263
Test name
Test status
Simulation time 76093551 ps
CPU time 2.2 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:59 PM PDT 24
Peak memory 215268 kb
Host smart-8f8460cc-9280-41b8-b326-06289f4ee271
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3459842444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3459842444
Directory /workspace/1.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3455086215
Short name T3136
Test name
Test status
Simulation time 257584935 ps
CPU time 2.61 seconds
Started Aug 05 04:57:51 PM PDT 24
Finished Aug 05 04:57:54 PM PDT 24
Peak memory 207092 kb
Host smart-a3a324d4-5f0f-49ca-bbf7-1ded0be40894
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3455086215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3455086215
Directory /workspace/1.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1006592510
Short name T3189
Test name
Test status
Simulation time 368254988 ps
CPU time 2.3 seconds
Started Aug 05 04:58:06 PM PDT 24
Finished Aug 05 04:58:09 PM PDT 24
Peak memory 207224 kb
Host smart-9c3eb20c-fc4a-43d2-a2ba-ea29f647ad04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1006592510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1006592510
Directory /workspace/1.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3340972610
Short name T3148
Test name
Test status
Simulation time 239120559 ps
CPU time 2.32 seconds
Started Aug 05 04:57:48 PM PDT 24
Finished Aug 05 04:57:50 PM PDT 24
Peak memory 207244 kb
Host smart-8c033d5b-6282-464f-af69-8a531e40826a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3340972610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3340972610
Directory /workspace/1.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3931209642
Short name T3220
Test name
Test status
Simulation time 362570351 ps
CPU time 2.84 seconds
Started Aug 05 04:57:59 PM PDT 24
Finished Aug 05 04:58:02 PM PDT 24
Peak memory 207184 kb
Host smart-a3df8d16-3ea1-4f01-9b84-4a08b477da59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3931209642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3931209642
Directory /workspace/1.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1813038616
Short name T3187
Test name
Test status
Simulation time 84759283 ps
CPU time 1.24 seconds
Started Aug 05 04:57:47 PM PDT 24
Finished Aug 05 04:57:48 PM PDT 24
Peak memory 215404 kb
Host smart-befeb0e8-a554-4584-88b5-af73141207cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813038616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1813038616
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.234054266
Short name T3195
Test name
Test status
Simulation time 104081820 ps
CPU time 1.04 seconds
Started Aug 05 04:58:00 PM PDT 24
Finished Aug 05 04:58:01 PM PDT 24
Peak memory 206860 kb
Host smart-28ff2e74-350e-4d00-980a-f34e4ab5e7d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=234054266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.234054266
Directory /workspace/10.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2934720198
Short name T3225
Test name
Test status
Simulation time 63624061 ps
CPU time 0.72 seconds
Started Aug 05 04:58:18 PM PDT 24
Finished Aug 05 04:58:19 PM PDT 24
Peak memory 206864 kb
Host smart-91d6402c-d58b-47e0-b8db-560821e313aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2934720198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2934720198
Directory /workspace/10.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1239727140
Short name T3142
Test name
Test status
Simulation time 98372175 ps
CPU time 1.15 seconds
Started Aug 05 04:57:55 PM PDT 24
Finished Aug 05 04:57:56 PM PDT 24
Peak memory 207204 kb
Host smart-20822f66-5ad1-41e7-9836-224391807690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1239727140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1239727140
Directory /workspace/10.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.764718420
Short name T3174
Test name
Test status
Simulation time 324698299 ps
CPU time 3.25 seconds
Started Aug 05 04:58:05 PM PDT 24
Finished Aug 05 04:58:08 PM PDT 24
Peak memory 215336 kb
Host smart-5158b66f-63d4-4040-a129-96bb88a52346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=764718420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.764718420
Directory /workspace/10.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2144950559
Short name T3227
Test name
Test status
Simulation time 1295072144 ps
CPU time 3.89 seconds
Started Aug 05 04:58:00 PM PDT 24
Finished Aug 05 04:58:04 PM PDT 24
Peak memory 207232 kb
Host smart-c6bcd652-71c5-4bce-8483-93742e765d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2144950559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2144950559
Directory /workspace/10.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2674404037
Short name T3137
Test name
Test status
Simulation time 144858621 ps
CPU time 1.79 seconds
Started Aug 05 04:58:06 PM PDT 24
Finished Aug 05 04:58:08 PM PDT 24
Peak memory 217860 kb
Host smart-eee7bdff-f919-4062-8b5a-1ad53f40f1cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674404037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2674404037
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3216880623
Short name T3185
Test name
Test status
Simulation time 65969505 ps
CPU time 1.03 seconds
Started Aug 05 04:58:08 PM PDT 24
Finished Aug 05 04:58:09 PM PDT 24
Peak memory 207004 kb
Host smart-feb045cd-6c84-4984-98c5-5bd4fea9d44a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3216880623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3216880623
Directory /workspace/11.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.106401575
Short name T3223
Test name
Test status
Simulation time 184936062 ps
CPU time 1.8 seconds
Started Aug 05 04:57:51 PM PDT 24
Finished Aug 05 04:57:53 PM PDT 24
Peak memory 207124 kb
Host smart-d2010162-bfab-41b6-84f1-7e9ea1badec7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=106401575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.106401575
Directory /workspace/11.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.976651123
Short name T3193
Test name
Test status
Simulation time 130415816 ps
CPU time 1.76 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:06 PM PDT 24
Peak memory 207224 kb
Host smart-5d640ba7-f656-4f98-9f57-23744a05f415
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=976651123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.976651123
Directory /workspace/11.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1725451778
Short name T317
Test name
Test status
Simulation time 905125308 ps
CPU time 4.7 seconds
Started Aug 05 04:58:01 PM PDT 24
Finished Aug 05 04:58:07 PM PDT 24
Peak memory 207160 kb
Host smart-3c5726ea-6380-4535-b2a8-dcdf2a0442d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1725451778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1725451778
Directory /workspace/11.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.579748755
Short name T3154
Test name
Test status
Simulation time 96338733 ps
CPU time 1.16 seconds
Started Aug 05 04:57:47 PM PDT 24
Finished Aug 05 04:57:48 PM PDT 24
Peak memory 215292 kb
Host smart-22b41392-73c4-453d-94d1-138873ad284a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579748755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.579748755
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4119672742
Short name T3224
Test name
Test status
Simulation time 124411345 ps
CPU time 1.07 seconds
Started Aug 05 04:58:01 PM PDT 24
Finished Aug 05 04:58:02 PM PDT 24
Peak memory 206940 kb
Host smart-0f5a7902-644c-42ad-a426-1ca955edb3c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4119672742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.4119672742
Directory /workspace/12.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1061507746
Short name T213
Test name
Test status
Simulation time 39820286 ps
CPU time 0.72 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:05 PM PDT 24
Peak memory 206892 kb
Host smart-d438bb34-f21e-478b-aec2-44baab479e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1061507746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1061507746
Directory /workspace/12.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3800881489
Short name T3173
Test name
Test status
Simulation time 270544477 ps
CPU time 2 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:59 PM PDT 24
Peak memory 207176 kb
Host smart-e58b29fc-b128-4bca-a05b-613b2eb3f74a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3800881489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3800881489
Directory /workspace/12.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2406326685
Short name T3179
Test name
Test status
Simulation time 126397997 ps
CPU time 1.65 seconds
Started Aug 05 04:58:09 PM PDT 24
Finished Aug 05 04:58:10 PM PDT 24
Peak memory 215400 kb
Host smart-742cf496-19dd-4f5a-a6fb-a76f5bf72a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2406326685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2406326685
Directory /workspace/12.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.140594138
Short name T313
Test name
Test status
Simulation time 929618701 ps
CPU time 5.05 seconds
Started Aug 05 04:58:08 PM PDT 24
Finished Aug 05 04:58:13 PM PDT 24
Peak memory 207144 kb
Host smart-06213f8b-d0fb-43cb-b49d-88371a63f372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=140594138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.140594138
Directory /workspace/12.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2070146880
Short name T3178
Test name
Test status
Simulation time 99602519 ps
CPU time 2.46 seconds
Started Aug 05 04:58:02 PM PDT 24
Finished Aug 05 04:58:05 PM PDT 24
Peak memory 215476 kb
Host smart-a7697cde-d99e-4588-af06-61565b26bec3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070146880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2070146880
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1286130917
Short name T3161
Test name
Test status
Simulation time 50503586 ps
CPU time 0.81 seconds
Started Aug 05 04:58:00 PM PDT 24
Finished Aug 05 04:58:01 PM PDT 24
Peak memory 206988 kb
Host smart-3730f0e4-1148-4d97-ab78-e2dd4cf4fa33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1286130917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1286130917
Directory /workspace/13.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1632522130
Short name T3190
Test name
Test status
Simulation time 49027194 ps
CPU time 0.72 seconds
Started Aug 05 04:57:54 PM PDT 24
Finished Aug 05 04:57:55 PM PDT 24
Peak memory 206804 kb
Host smart-713cb73e-f290-4634-a77a-bb4396d24b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1632522130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1632522130
Directory /workspace/13.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1617136311
Short name T3177
Test name
Test status
Simulation time 96113907 ps
CPU time 1.62 seconds
Started Aug 05 04:58:08 PM PDT 24
Finished Aug 05 04:58:10 PM PDT 24
Peak memory 207164 kb
Host smart-3b12e250-bf81-45e0-a94f-2b2becf0d0f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1617136311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1617136311
Directory /workspace/13.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3256280366
Short name T231
Test name
Test status
Simulation time 743349467 ps
CPU time 4.78 seconds
Started Aug 05 04:58:06 PM PDT 24
Finished Aug 05 04:58:11 PM PDT 24
Peak memory 207252 kb
Host smart-5f7ef088-f5a6-49a5-9042-5649713913fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3256280366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3256280366
Directory /workspace/13.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2580225977
Short name T203
Test name
Test status
Simulation time 70230451 ps
CPU time 1.7 seconds
Started Aug 05 04:58:02 PM PDT 24
Finished Aug 05 04:58:04 PM PDT 24
Peak memory 215384 kb
Host smart-b995d41f-e103-4d82-ac94-ae5a9ecc253e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580225977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2580225977
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4293239509
Short name T261
Test name
Test status
Simulation time 55286553 ps
CPU time 0.79 seconds
Started Aug 05 04:58:08 PM PDT 24
Finished Aug 05 04:58:09 PM PDT 24
Peak memory 207000 kb
Host smart-0b2a55a2-3694-4109-b6d2-b56a2a5ca2bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4293239509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4293239509
Directory /workspace/14.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3806032489
Short name T269
Test name
Test status
Simulation time 121275011 ps
CPU time 1.07 seconds
Started Aug 05 04:57:58 PM PDT 24
Finished Aug 05 04:57:59 PM PDT 24
Peak memory 207032 kb
Host smart-ef910d1e-07ff-442a-9127-eb59a2c8385f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3806032489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3806032489
Directory /workspace/14.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.449387606
Short name T239
Test name
Test status
Simulation time 287722770 ps
CPU time 3.19 seconds
Started Aug 05 04:58:16 PM PDT 24
Finished Aug 05 04:58:19 PM PDT 24
Peak memory 220820 kb
Host smart-c18dd1e3-1fa9-4cee-be2a-187b430b6b1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=449387606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.449387606
Directory /workspace/14.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2872530850
Short name T3229
Test name
Test status
Simulation time 494170460 ps
CPU time 2.59 seconds
Started Aug 05 04:57:53 PM PDT 24
Finished Aug 05 04:57:56 PM PDT 24
Peak memory 207200 kb
Host smart-0ac4649d-7ab3-404d-8ac9-6fb0613150fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2872530850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2872530850
Directory /workspace/14.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2139157908
Short name T260
Test name
Test status
Simulation time 68054442 ps
CPU time 0.83 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:05 PM PDT 24
Peak memory 207016 kb
Host smart-4eb5e9d3-bd9e-40df-8fd6-e3653a938298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2139157908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2139157908
Directory /workspace/15.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1515630467
Short name T3207
Test name
Test status
Simulation time 93696781 ps
CPU time 0.76 seconds
Started Aug 05 04:57:58 PM PDT 24
Finished Aug 05 04:57:59 PM PDT 24
Peak memory 206356 kb
Host smart-3d6f7756-7cd5-45ab-b8fb-f990fec99366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1515630467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1515630467
Directory /workspace/15.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1160563085
Short name T3232
Test name
Test status
Simulation time 191423313 ps
CPU time 1.64 seconds
Started Aug 05 04:58:08 PM PDT 24
Finished Aug 05 04:58:10 PM PDT 24
Peak memory 207192 kb
Host smart-ce34274e-bc5d-4c12-9155-62fde1e1fde7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1160563085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1160563085
Directory /workspace/15.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3864913961
Short name T3197
Test name
Test status
Simulation time 185228345 ps
CPU time 3.5 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:08 PM PDT 24
Peak memory 207468 kb
Host smart-fb31ab36-3419-4f54-b3f3-70a4a914055e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3864913961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3864913961
Directory /workspace/15.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.360001950
Short name T3175
Test name
Test status
Simulation time 76774329 ps
CPU time 1.8 seconds
Started Aug 05 04:58:05 PM PDT 24
Finished Aug 05 04:58:07 PM PDT 24
Peak memory 215356 kb
Host smart-09cc7efe-2901-4d8e-b37d-62e1656e3c02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360001950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.360001950
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3262400180
Short name T258
Test name
Test status
Simulation time 82448095 ps
CPU time 1.04 seconds
Started Aug 05 04:57:54 PM PDT 24
Finished Aug 05 04:57:55 PM PDT 24
Peak memory 206944 kb
Host smart-db6b09d7-38ed-4ead-8762-2f1c9f4fcaca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3262400180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3262400180
Directory /workspace/16.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1168392773
Short name T3146
Test name
Test status
Simulation time 73351283 ps
CPU time 0.75 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:58 PM PDT 24
Peak memory 206848 kb
Host smart-0b09b488-f8c0-474f-9754-6008304d11bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1168392773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1168392773
Directory /workspace/16.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2668559915
Short name T3140
Test name
Test status
Simulation time 93336698 ps
CPU time 1.16 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:58 PM PDT 24
Peak memory 206984 kb
Host smart-88919a41-dcb6-49e7-9c35-0fd05bf47f4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2668559915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2668559915
Directory /workspace/16.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4246921219
Short name T228
Test name
Test status
Simulation time 146200297 ps
CPU time 1.75 seconds
Started Aug 05 04:58:06 PM PDT 24
Finished Aug 05 04:58:08 PM PDT 24
Peak memory 223280 kb
Host smart-4117c5ee-d130-471f-93a8-882563c5b589
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4246921219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.4246921219
Directory /workspace/16.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1497793882
Short name T3222
Test name
Test status
Simulation time 294701276 ps
CPU time 2.57 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:58:00 PM PDT 24
Peak memory 207212 kb
Host smart-5065e01d-5f1b-4707-bd1d-9947d8410fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1497793882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1497793882
Directory /workspace/16.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2369873587
Short name T3234
Test name
Test status
Simulation time 118427293 ps
CPU time 1.79 seconds
Started Aug 05 04:58:13 PM PDT 24
Finished Aug 05 04:58:15 PM PDT 24
Peak memory 215488 kb
Host smart-cc54fd75-514a-4964-b4e8-e2aeb472e3bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369873587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2369873587
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.648227188
Short name T271
Test name
Test status
Simulation time 80443222 ps
CPU time 0.98 seconds
Started Aug 05 04:58:07 PM PDT 24
Finished Aug 05 04:58:08 PM PDT 24
Peak memory 207036 kb
Host smart-db1b5ed2-cd5e-49a5-857f-d4e49f9e38d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=648227188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.648227188
Directory /workspace/17.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.150224762
Short name T3165
Test name
Test status
Simulation time 29396354 ps
CPU time 0.69 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:58 PM PDT 24
Peak memory 206804 kb
Host smart-277ce3cd-8960-48d7-98b2-d61fa26dfa54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=150224762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.150224762
Directory /workspace/17.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.242205153
Short name T278
Test name
Test status
Simulation time 108701409 ps
CPU time 1.18 seconds
Started Aug 05 04:58:06 PM PDT 24
Finished Aug 05 04:58:07 PM PDT 24
Peak memory 207200 kb
Host smart-2fc80719-2294-41b6-af67-b73058b1dd23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=242205153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.242205153
Directory /workspace/17.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3732443646
Short name T222
Test name
Test status
Simulation time 175226724 ps
CPU time 2.16 seconds
Started Aug 05 04:57:58 PM PDT 24
Finished Aug 05 04:58:00 PM PDT 24
Peak memory 206628 kb
Host smart-860e0c41-61c0-4702-bec9-cea878668e48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3732443646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3732443646
Directory /workspace/17.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1795724571
Short name T310
Test name
Test status
Simulation time 787292343 ps
CPU time 4.84 seconds
Started Aug 05 04:58:02 PM PDT 24
Finished Aug 05 04:58:07 PM PDT 24
Peak memory 207208 kb
Host smart-7f4455db-5d01-4951-8502-0764c22f131f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1795724571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1795724571
Directory /workspace/17.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3275938569
Short name T237
Test name
Test status
Simulation time 103843286 ps
CPU time 2.41 seconds
Started Aug 05 04:58:35 PM PDT 24
Finished Aug 05 04:58:38 PM PDT 24
Peak memory 215380 kb
Host smart-aefd53d2-04a5-4570-a8ab-8e50e95c6897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275938569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3275938569
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.394527545
Short name T265
Test name
Test status
Simulation time 142408217 ps
CPU time 1.05 seconds
Started Aug 05 04:58:05 PM PDT 24
Finished Aug 05 04:58:06 PM PDT 24
Peak memory 207000 kb
Host smart-ee481cee-bd84-462b-9c92-5dc92aa3d309
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=394527545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.394527545
Directory /workspace/18.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4001107550
Short name T3162
Test name
Test status
Simulation time 39123123 ps
CPU time 0.72 seconds
Started Aug 05 04:58:07 PM PDT 24
Finished Aug 05 04:58:08 PM PDT 24
Peak memory 206788 kb
Host smart-11dda357-7b74-4077-bbad-eb2ad9c009b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4001107550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.4001107550
Directory /workspace/18.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2448808032
Short name T3226
Test name
Test status
Simulation time 259735178 ps
CPU time 1.57 seconds
Started Aug 05 04:58:08 PM PDT 24
Finished Aug 05 04:58:10 PM PDT 24
Peak memory 207212 kb
Host smart-8a624be7-af85-4b53-a5b9-6cbd9e08dbd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2448808032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2448808032
Directory /workspace/18.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2584629803
Short name T204
Test name
Test status
Simulation time 69660651 ps
CPU time 1.85 seconds
Started Aug 05 04:58:03 PM PDT 24
Finished Aug 05 04:58:05 PM PDT 24
Peak memory 215488 kb
Host smart-de9c050c-1dfa-4039-ae79-61be3d2f38c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584629803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2584629803
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1596829270
Short name T3215
Test name
Test status
Simulation time 82279627 ps
CPU time 1.05 seconds
Started Aug 05 04:58:24 PM PDT 24
Finished Aug 05 04:58:25 PM PDT 24
Peak memory 207000 kb
Host smart-97ad9311-1553-4dea-9c94-2ea8c678db38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1596829270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1596829270
Directory /workspace/19.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1166056827
Short name T3152
Test name
Test status
Simulation time 41865919 ps
CPU time 0.7 seconds
Started Aug 05 04:58:20 PM PDT 24
Finished Aug 05 04:58:21 PM PDT 24
Peak memory 206760 kb
Host smart-d7e0b4dd-aae7-48cd-986a-8ee6320bf41f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1166056827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1166056827
Directory /workspace/19.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.218359058
Short name T3202
Test name
Test status
Simulation time 181556135 ps
CPU time 1.39 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:05 PM PDT 24
Peak memory 207204 kb
Host smart-5439d7d2-d528-41ad-abf4-635f8398e54b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=218359058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.218359058
Directory /workspace/19.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.674108748
Short name T236
Test name
Test status
Simulation time 74816091 ps
CPU time 2 seconds
Started Aug 05 04:57:58 PM PDT 24
Finished Aug 05 04:58:00 PM PDT 24
Peak memory 207212 kb
Host smart-621fb532-7c23-44b9-8554-4e7d4f39bab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=674108748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.674108748
Directory /workspace/19.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.545284049
Short name T312
Test name
Test status
Simulation time 529762564 ps
CPU time 2.58 seconds
Started Aug 05 04:58:07 PM PDT 24
Finished Aug 05 04:58:10 PM PDT 24
Peak memory 207180 kb
Host smart-ae84f1eb-6a61-4830-8da3-9fdf8a0548ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=545284049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.545284049
Directory /workspace/19.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1111118263
Short name T3221
Test name
Test status
Simulation time 369388370 ps
CPU time 3.58 seconds
Started Aug 05 04:57:52 PM PDT 24
Finished Aug 05 04:57:56 PM PDT 24
Peak memory 207240 kb
Host smart-d015a017-85b0-424d-a481-930aea9ba7c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1111118263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1111118263
Directory /workspace/2.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3963876483
Short name T3157
Test name
Test status
Simulation time 761314372 ps
CPU time 4.25 seconds
Started Aug 05 04:57:44 PM PDT 24
Finished Aug 05 04:57:49 PM PDT 24
Peak memory 207196 kb
Host smart-70c34017-21df-4efa-8e83-e2b34e36ebb9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3963876483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3963876483
Directory /workspace/2.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4193194574
Short name T253
Test name
Test status
Simulation time 59719765 ps
CPU time 0.79 seconds
Started Aug 05 04:57:47 PM PDT 24
Finished Aug 05 04:57:48 PM PDT 24
Peak memory 206844 kb
Host smart-5736ed71-0b45-4b92-b903-63e4b0bec278
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4193194574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.4193194574
Directory /workspace/2.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1670815153
Short name T3219
Test name
Test status
Simulation time 178367569 ps
CPU time 2.74 seconds
Started Aug 05 04:57:41 PM PDT 24
Finished Aug 05 04:57:44 PM PDT 24
Peak memory 215476 kb
Host smart-0bb33333-3cdc-4e3e-9fc4-4e6849b67c4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670815153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1670815153
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2193926015
Short name T254
Test name
Test status
Simulation time 93900486 ps
CPU time 0.9 seconds
Started Aug 05 04:58:03 PM PDT 24
Finished Aug 05 04:58:04 PM PDT 24
Peak memory 206944 kb
Host smart-76b5395e-c7f9-4d4c-8c59-c39e1b183288
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2193926015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2193926015
Directory /workspace/2.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2002257032
Short name T3151
Test name
Test status
Simulation time 57135147 ps
CPU time 0.74 seconds
Started Aug 05 04:57:59 PM PDT 24
Finished Aug 05 04:58:00 PM PDT 24
Peak memory 206780 kb
Host smart-b43bf9ca-01a0-4ea6-a765-082244e6b466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2002257032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2002257032
Directory /workspace/2.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2144520039
Short name T257
Test name
Test status
Simulation time 94874032 ps
CPU time 2.17 seconds
Started Aug 05 04:57:51 PM PDT 24
Finished Aug 05 04:57:53 PM PDT 24
Peak memory 207420 kb
Host smart-2e7dd976-7cbc-4111-8f49-1307ad84f6fe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2144520039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2144520039
Directory /workspace/2.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1170737369
Short name T3181
Test name
Test status
Simulation time 127068461 ps
CPU time 2.39 seconds
Started Aug 05 04:57:46 PM PDT 24
Finished Aug 05 04:57:48 PM PDT 24
Peak memory 207092 kb
Host smart-2cada52c-7e31-434e-bcfc-8ae8a5d41481
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1170737369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1170737369
Directory /workspace/2.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3783912146
Short name T3143
Test name
Test status
Simulation time 88573305 ps
CPU time 1.07 seconds
Started Aug 05 04:58:17 PM PDT 24
Finished Aug 05 04:58:18 PM PDT 24
Peak memory 207132 kb
Host smart-1bb581d3-a8a0-4c5f-bc5e-c304ac4ba162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3783912146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3783912146
Directory /workspace/2.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3979168780
Short name T3218
Test name
Test status
Simulation time 73934746 ps
CPU time 1.93 seconds
Started Aug 05 04:57:51 PM PDT 24
Finished Aug 05 04:57:53 PM PDT 24
Peak memory 223256 kb
Host smart-87ef06f9-1112-4bad-a594-b868fa9380d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3979168780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3979168780
Directory /workspace/2.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1301204447
Short name T319
Test name
Test status
Simulation time 536229331 ps
CPU time 4.39 seconds
Started Aug 05 04:57:50 PM PDT 24
Finished Aug 05 04:57:55 PM PDT 24
Peak memory 207200 kb
Host smart-7caff2d5-457c-45e5-8f72-c5b8019fa756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1301204447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1301204447
Directory /workspace/2.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2191681894
Short name T3139
Test name
Test status
Simulation time 74246558 ps
CPU time 0.8 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:58 PM PDT 24
Peak memory 206780 kb
Host smart-ebe72ad6-cdd7-47ba-af4e-431118307a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2191681894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2191681894
Directory /workspace/20.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2870684190
Short name T3209
Test name
Test status
Simulation time 73540217 ps
CPU time 0.69 seconds
Started Aug 05 04:58:12 PM PDT 24
Finished Aug 05 04:58:13 PM PDT 24
Peak memory 206788 kb
Host smart-48da6a52-9aff-4d0b-b98a-57beeff5b3b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2870684190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2870684190
Directory /workspace/21.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2525328200
Short name T3141
Test name
Test status
Simulation time 42546260 ps
CPU time 0.73 seconds
Started Aug 05 04:57:59 PM PDT 24
Finished Aug 05 04:57:59 PM PDT 24
Peak memory 206772 kb
Host smart-5a799e62-6e25-4347-be54-be021404f17a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2525328200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2525328200
Directory /workspace/22.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1172153914
Short name T3160
Test name
Test status
Simulation time 53169869 ps
CPU time 0.77 seconds
Started Aug 05 04:58:08 PM PDT 24
Finished Aug 05 04:58:09 PM PDT 24
Peak memory 206852 kb
Host smart-845e585b-1e33-47fa-aca5-94e79ed82bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1172153914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1172153914
Directory /workspace/23.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4065392141
Short name T3144
Test name
Test status
Simulation time 40911370 ps
CPU time 0.69 seconds
Started Aug 05 04:58:05 PM PDT 24
Finished Aug 05 04:58:06 PM PDT 24
Peak memory 206848 kb
Host smart-9c0f77a9-501c-4903-b741-883bbb15c9d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4065392141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.4065392141
Directory /workspace/24.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.958388900
Short name T3191
Test name
Test status
Simulation time 49412003 ps
CPU time 0.72 seconds
Started Aug 05 04:58:06 PM PDT 24
Finished Aug 05 04:58:07 PM PDT 24
Peak memory 206792 kb
Host smart-76003210-9e08-4316-850a-a22f471e376d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=958388900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.958388900
Directory /workspace/25.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4185131255
Short name T3200
Test name
Test status
Simulation time 42131466 ps
CPU time 0.74 seconds
Started Aug 05 04:58:02 PM PDT 24
Finished Aug 05 04:58:03 PM PDT 24
Peak memory 206784 kb
Host smart-e611c1e1-e83f-428b-b3e8-1a8ab00313cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4185131255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.4185131255
Directory /workspace/26.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.277727518
Short name T212
Test name
Test status
Simulation time 47020241 ps
CPU time 0.75 seconds
Started Aug 05 04:58:11 PM PDT 24
Finished Aug 05 04:58:12 PM PDT 24
Peak memory 206764 kb
Host smart-3aab50ee-604e-48e3-8290-052c5e6190c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=277727518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.277727518
Directory /workspace/27.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2278689117
Short name T3158
Test name
Test status
Simulation time 48751457 ps
CPU time 0.75 seconds
Started Aug 05 04:58:08 PM PDT 24
Finished Aug 05 04:58:09 PM PDT 24
Peak memory 206868 kb
Host smart-3a1b23d1-4c63-428a-bcee-f7df01ff0597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2278689117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2278689117
Directory /workspace/28.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3769676119
Short name T3196
Test name
Test status
Simulation time 62585968 ps
CPU time 0.75 seconds
Started Aug 05 04:57:58 PM PDT 24
Finished Aug 05 04:57:59 PM PDT 24
Peak memory 206780 kb
Host smart-33fc215f-d0cd-4558-b331-397cee8b8f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3769676119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3769676119
Directory /workspace/29.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.833621688
Short name T279
Test name
Test status
Simulation time 200869096 ps
CPU time 2.14 seconds
Started Aug 05 04:57:40 PM PDT 24
Finished Aug 05 04:57:43 PM PDT 24
Peak memory 207152 kb
Host smart-e0a3ce45-ccf1-4eef-9f75-8f54444fdcb6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=833621688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.833621688
Directory /workspace/3.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1615602377
Short name T3206
Test name
Test status
Simulation time 340083249 ps
CPU time 3.84 seconds
Started Aug 05 04:57:37 PM PDT 24
Finished Aug 05 04:57:41 PM PDT 24
Peak memory 207184 kb
Host smart-cb5e238b-8138-47b9-b116-eeadbae51f42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1615602377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1615602377
Directory /workspace/3.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2255371405
Short name T206
Test name
Test status
Simulation time 69599266 ps
CPU time 0.91 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:06 PM PDT 24
Peak memory 206924 kb
Host smart-93831375-3458-454a-be2f-2cdc42c226a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2255371405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2255371405
Directory /workspace/3.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.4214129866
Short name T3164
Test name
Test status
Simulation time 190300872 ps
CPU time 1.85 seconds
Started Aug 05 04:58:06 PM PDT 24
Finished Aug 05 04:58:08 PM PDT 24
Peak memory 219568 kb
Host smart-63b15528-996e-4431-a998-6870114cf56e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214129866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.4214129866
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.711624975
Short name T225
Test name
Test status
Simulation time 57292170 ps
CPU time 0.79 seconds
Started Aug 05 04:57:50 PM PDT 24
Finished Aug 05 04:57:51 PM PDT 24
Peak memory 206952 kb
Host smart-c1720ea1-be87-4a1a-9e46-065cf24a75a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=711624975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.711624975
Directory /workspace/3.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1267876280
Short name T3228
Test name
Test status
Simulation time 46410219 ps
CPU time 0.69 seconds
Started Aug 05 04:57:46 PM PDT 24
Finished Aug 05 04:57:47 PM PDT 24
Peak memory 206868 kb
Host smart-261f7f37-c68a-41e2-afb7-a0a28cb20a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1267876280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1267876280
Directory /workspace/3.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1867945708
Short name T268
Test name
Test status
Simulation time 92194568 ps
CPU time 2.17 seconds
Started Aug 05 04:57:52 PM PDT 24
Finished Aug 05 04:57:55 PM PDT 24
Peak memory 215304 kb
Host smart-af33a41d-529f-4383-8c49-1898a9cce294
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1867945708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1867945708
Directory /workspace/3.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2504407914
Short name T3155
Test name
Test status
Simulation time 185123044 ps
CPU time 4.03 seconds
Started Aug 05 04:58:02 PM PDT 24
Finished Aug 05 04:58:06 PM PDT 24
Peak memory 207008 kb
Host smart-0cfb39d7-c4c0-4b68-a1fc-a9d48a0ff63c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2504407914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2504407914
Directory /workspace/3.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.445581092
Short name T283
Test name
Test status
Simulation time 139639389 ps
CPU time 1.28 seconds
Started Aug 05 04:57:46 PM PDT 24
Finished Aug 05 04:57:47 PM PDT 24
Peak memory 207192 kb
Host smart-2271acc4-7330-4c39-a259-314b75081db1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=445581092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.445581092
Directory /workspace/3.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3931465548
Short name T316
Test name
Test status
Simulation time 385366633 ps
CPU time 2.68 seconds
Started Aug 05 04:57:41 PM PDT 24
Finished Aug 05 04:57:44 PM PDT 24
Peak memory 207224 kb
Host smart-08ca734c-536c-4fb4-a6bd-d3896a5bea2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3931465548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3931465548
Directory /workspace/3.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3689740118
Short name T3171
Test name
Test status
Simulation time 87048925 ps
CPU time 0.74 seconds
Started Aug 05 04:58:13 PM PDT 24
Finished Aug 05 04:58:14 PM PDT 24
Peak memory 206888 kb
Host smart-d9f96233-782c-4f24-bd10-6196391659e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3689740118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3689740118
Directory /workspace/31.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2415831766
Short name T3212
Test name
Test status
Simulation time 39257079 ps
CPU time 0.71 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:05 PM PDT 24
Peak memory 206864 kb
Host smart-d2d93a74-bf37-40bd-8774-e7753aa0c8c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2415831766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2415831766
Directory /workspace/32.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.793197819
Short name T282
Test name
Test status
Simulation time 40739154 ps
CPU time 0.75 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:58 PM PDT 24
Peak memory 206864 kb
Host smart-9bdf452a-2cba-413a-b327-daceff2bb0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=793197819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.793197819
Directory /workspace/33.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1604299257
Short name T301
Test name
Test status
Simulation time 39121450 ps
CPU time 0.76 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:05 PM PDT 24
Peak memory 206804 kb
Host smart-0f47ab4f-ee42-499c-ab00-20ebcbf20221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1604299257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1604299257
Directory /workspace/34.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2445169241
Short name T302
Test name
Test status
Simulation time 36175850 ps
CPU time 0.68 seconds
Started Aug 05 04:58:14 PM PDT 24
Finished Aug 05 04:58:14 PM PDT 24
Peak memory 206828 kb
Host smart-6c65e2a5-4f5b-4384-9335-a8afb0dc5513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2445169241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2445169241
Directory /workspace/35.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1759836798
Short name T3145
Test name
Test status
Simulation time 58223618 ps
CPU time 0.74 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:05 PM PDT 24
Peak memory 206764 kb
Host smart-6554becb-311b-4bb5-a624-951dadaf5e23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1759836798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1759836798
Directory /workspace/36.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3916660188
Short name T307
Test name
Test status
Simulation time 36371471 ps
CPU time 0.71 seconds
Started Aug 05 04:58:00 PM PDT 24
Finished Aug 05 04:58:01 PM PDT 24
Peak memory 206956 kb
Host smart-41575eee-c8d4-4ac8-8b4d-4958eb586e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3916660188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3916660188
Directory /workspace/38.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2811732162
Short name T3167
Test name
Test status
Simulation time 45602321 ps
CPU time 0.71 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:04 PM PDT 24
Peak memory 206744 kb
Host smart-09f4f48b-d4f1-42dd-86a1-07c094a8942d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2811732162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2811732162
Directory /workspace/39.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2191828380
Short name T266
Test name
Test status
Simulation time 121230379 ps
CPU time 3.31 seconds
Started Aug 05 04:57:40 PM PDT 24
Finished Aug 05 04:57:43 PM PDT 24
Peak memory 207112 kb
Host smart-6f0cfd3c-dc2d-4e21-bf5e-92ea5590c153
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2191828380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2191828380
Directory /workspace/4.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2754378952
Short name T252
Test name
Test status
Simulation time 338966256 ps
CPU time 3.82 seconds
Started Aug 05 04:58:00 PM PDT 24
Finished Aug 05 04:58:04 PM PDT 24
Peak memory 207200 kb
Host smart-0cf5f8a9-6a95-47de-9106-ebe8f4ce5014
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2754378952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2754378952
Directory /workspace/4.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3774959088
Short name T3176
Test name
Test status
Simulation time 85821805 ps
CPU time 0.83 seconds
Started Aug 05 04:57:54 PM PDT 24
Finished Aug 05 04:57:55 PM PDT 24
Peak memory 206916 kb
Host smart-d85623a1-0887-410d-97e9-5f0d7d5fcea9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3774959088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3774959088
Directory /workspace/4.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2042590515
Short name T205
Test name
Test status
Simulation time 57889506 ps
CPU time 1.66 seconds
Started Aug 05 04:57:48 PM PDT 24
Finished Aug 05 04:57:50 PM PDT 24
Peak memory 215332 kb
Host smart-a82a209a-05fd-4065-88a3-2cd90bafc894
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042590515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2042590515
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.510298017
Short name T264
Test name
Test status
Simulation time 120372607 ps
CPU time 0.87 seconds
Started Aug 05 04:57:59 PM PDT 24
Finished Aug 05 04:58:00 PM PDT 24
Peak memory 206948 kb
Host smart-c5ff47f2-ecee-4a6c-af3c-d73b013664f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=510298017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.510298017
Directory /workspace/4.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4151083929
Short name T3205
Test name
Test status
Simulation time 45635682 ps
CPU time 0.75 seconds
Started Aug 05 04:57:40 PM PDT 24
Finished Aug 05 04:57:41 PM PDT 24
Peak memory 206876 kb
Host smart-eead0a9e-b231-4157-8a37-217717629cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4151083929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.4151083929
Directory /workspace/4.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2589871322
Short name T267
Test name
Test status
Simulation time 122863850 ps
CPU time 1.52 seconds
Started Aug 05 04:57:50 PM PDT 24
Finished Aug 05 04:57:52 PM PDT 24
Peak memory 207108 kb
Host smart-879cf6cd-0b2f-4444-859e-f1151a7a1247
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2589871322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2589871322
Directory /workspace/4.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2561479767
Short name T3135
Test name
Test status
Simulation time 162697879 ps
CPU time 4.12 seconds
Started Aug 05 04:57:45 PM PDT 24
Finished Aug 05 04:57:50 PM PDT 24
Peak memory 207032 kb
Host smart-c892215d-6b87-4027-a88d-b762bf375ccc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2561479767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2561479767
Directory /workspace/4.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2410074237
Short name T3188
Test name
Test status
Simulation time 86429572 ps
CPU time 1.16 seconds
Started Aug 05 04:58:03 PM PDT 24
Finished Aug 05 04:58:05 PM PDT 24
Peak memory 207160 kb
Host smart-f52b55e9-2cba-4d65-8cfe-8de219687a2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2410074237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2410074237
Directory /workspace/4.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3730341934
Short name T3150
Test name
Test status
Simulation time 264800703 ps
CPU time 2.93 seconds
Started Aug 05 04:57:58 PM PDT 24
Finished Aug 05 04:58:01 PM PDT 24
Peak memory 223204 kb
Host smart-d938e825-9acf-47d2-800c-93a495e0fa16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3730341934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3730341934
Directory /workspace/4.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2398594282
Short name T3199
Test name
Test status
Simulation time 1481620849 ps
CPU time 4.89 seconds
Started Aug 05 04:58:05 PM PDT 24
Finished Aug 05 04:58:10 PM PDT 24
Peak memory 207108 kb
Host smart-1b35638c-29e3-43fc-9e75-2695078587b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2398594282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2398594282
Directory /workspace/4.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2647309205
Short name T3203
Test name
Test status
Simulation time 47975555 ps
CPU time 0.72 seconds
Started Aug 05 04:58:12 PM PDT 24
Finished Aug 05 04:58:13 PM PDT 24
Peak memory 206868 kb
Host smart-7c907b2c-59df-4ba9-97e7-ecfdb141765b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2647309205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2647309205
Directory /workspace/40.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1784446784
Short name T3172
Test name
Test status
Simulation time 44279336 ps
CPU time 0.76 seconds
Started Aug 05 04:58:05 PM PDT 24
Finished Aug 05 04:58:06 PM PDT 24
Peak memory 206892 kb
Host smart-3e7a27a2-ee6f-4523-a747-5374620a7154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1784446784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1784446784
Directory /workspace/41.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2252625718
Short name T306
Test name
Test status
Simulation time 81335005 ps
CPU time 0.82 seconds
Started Aug 05 04:58:03 PM PDT 24
Finished Aug 05 04:58:04 PM PDT 24
Peak memory 206864 kb
Host smart-677b4521-c5e1-4df6-9d71-4f7bb02a95fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2252625718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2252625718
Directory /workspace/42.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.68364153
Short name T3192
Test name
Test status
Simulation time 29311065 ps
CPU time 0.68 seconds
Started Aug 05 04:58:12 PM PDT 24
Finished Aug 05 04:58:12 PM PDT 24
Peak memory 206888 kb
Host smart-36abafc5-987f-414a-9eef-10dc6ab4a5bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=68364153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.68364153
Directory /workspace/43.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1964928584
Short name T280
Test name
Test status
Simulation time 40682653 ps
CPU time 0.73 seconds
Started Aug 05 04:58:13 PM PDT 24
Finished Aug 05 04:58:14 PM PDT 24
Peak memory 206852 kb
Host smart-6a638cab-8639-409d-bbfb-0147896ba419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1964928584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1964928584
Directory /workspace/44.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4220478448
Short name T3210
Test name
Test status
Simulation time 124367709 ps
CPU time 0.81 seconds
Started Aug 05 04:58:41 PM PDT 24
Finished Aug 05 04:58:42 PM PDT 24
Peak memory 206852 kb
Host smart-e040fe33-29a6-4c0a-979d-de8d4b2f4831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4220478448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.4220478448
Directory /workspace/45.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3816707321
Short name T3184
Test name
Test status
Simulation time 76318842 ps
CPU time 0.76 seconds
Started Aug 05 04:58:07 PM PDT 24
Finished Aug 05 04:58:08 PM PDT 24
Peak memory 206884 kb
Host smart-4f792ae3-95b6-46b1-a5a5-a64ffed12996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3816707321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3816707321
Directory /workspace/46.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3783944698
Short name T3163
Test name
Test status
Simulation time 74196260 ps
CPU time 0.74 seconds
Started Aug 05 04:58:08 PM PDT 24
Finished Aug 05 04:58:09 PM PDT 24
Peak memory 206888 kb
Host smart-dc70cf65-c427-4f02-b47f-6482335de1ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3783944698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3783944698
Directory /workspace/47.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3497741216
Short name T281
Test name
Test status
Simulation time 42696985 ps
CPU time 0.75 seconds
Started Aug 05 04:58:12 PM PDT 24
Finished Aug 05 04:58:13 PM PDT 24
Peak memory 206820 kb
Host smart-0f810d37-761d-4e89-bb4e-d3395afd3201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3497741216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3497741216
Directory /workspace/48.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4040549839
Short name T3216
Test name
Test status
Simulation time 42366199 ps
CPU time 0.71 seconds
Started Aug 05 04:58:09 PM PDT 24
Finished Aug 05 04:58:10 PM PDT 24
Peak memory 206732 kb
Host smart-6977125b-d9be-470d-b722-d34363962a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4040549839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.4040549839
Directory /workspace/49.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.665863895
Short name T234
Test name
Test status
Simulation time 135256188 ps
CPU time 1.71 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:06 PM PDT 24
Peak memory 217912 kb
Host smart-1b5b0f8b-3724-4a21-93e4-50d8f2e3d65b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665863895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.665863895
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3054574611
Short name T3204
Test name
Test status
Simulation time 88638318 ps
CPU time 0.9 seconds
Started Aug 05 04:58:07 PM PDT 24
Finished Aug 05 04:58:08 PM PDT 24
Peak memory 206932 kb
Host smart-55480745-6eb6-4883-9d0b-d694f9168304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3054574611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3054574611
Directory /workspace/5.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3430518105
Short name T3233
Test name
Test status
Simulation time 44907013 ps
CPU time 0.75 seconds
Started Aug 05 04:57:56 PM PDT 24
Finished Aug 05 04:57:57 PM PDT 24
Peak memory 206864 kb
Host smart-0b5e0ed4-2a86-4ccd-b84c-3440b2f8525e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3430518105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3430518105
Directory /workspace/5.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.380996205
Short name T3231
Test name
Test status
Simulation time 171431596 ps
CPU time 1.23 seconds
Started Aug 05 04:58:01 PM PDT 24
Finished Aug 05 04:58:02 PM PDT 24
Peak memory 206920 kb
Host smart-faab9b4b-bcfd-4bf2-bc88-a587e4e42e3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=380996205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.380996205
Directory /workspace/5.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2138567220
Short name T3230
Test name
Test status
Simulation time 256869019 ps
CPU time 2.93 seconds
Started Aug 05 04:57:49 PM PDT 24
Finished Aug 05 04:57:52 PM PDT 24
Peak memory 223372 kb
Host smart-570a5535-3042-4bbb-bf1f-674a84ebdcb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2138567220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2138567220
Directory /workspace/5.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3990217519
Short name T238
Test name
Test status
Simulation time 462954283 ps
CPU time 4 seconds
Started Aug 05 04:57:49 PM PDT 24
Finished Aug 05 04:57:53 PM PDT 24
Peak memory 207236 kb
Host smart-58ba2939-44a8-45af-9625-9616444d35c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3990217519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3990217519
Directory /workspace/5.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.816119617
Short name T3208
Test name
Test status
Simulation time 177304647 ps
CPU time 2.02 seconds
Started Aug 05 04:58:06 PM PDT 24
Finished Aug 05 04:58:08 PM PDT 24
Peak memory 215428 kb
Host smart-c004b769-6090-499f-8c60-d26967910e39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816119617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.816119617
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2523828062
Short name T3198
Test name
Test status
Simulation time 109072429 ps
CPU time 1.05 seconds
Started Aug 05 04:57:59 PM PDT 24
Finished Aug 05 04:58:00 PM PDT 24
Peak memory 206916 kb
Host smart-22e73fb3-ca82-4ae1-b008-624dca4c4e70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2523828062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2523828062
Directory /workspace/6.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.4129198788
Short name T211
Test name
Test status
Simulation time 42910592 ps
CPU time 0.72 seconds
Started Aug 05 04:57:56 PM PDT 24
Finished Aug 05 04:57:56 PM PDT 24
Peak memory 206748 kb
Host smart-dcbf4c03-1da2-4b55-8aa3-0097b53cfc27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4129198788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.4129198788
Directory /workspace/6.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1063423806
Short name T274
Test name
Test status
Simulation time 198809239 ps
CPU time 1.63 seconds
Started Aug 05 04:57:59 PM PDT 24
Finished Aug 05 04:58:01 PM PDT 24
Peak memory 207156 kb
Host smart-15e671cc-3bca-4aa8-8f9c-a26fa2692787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1063423806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1063423806
Directory /workspace/6.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3758309200
Short name T3159
Test name
Test status
Simulation time 61934171 ps
CPU time 1.45 seconds
Started Aug 05 04:58:01 PM PDT 24
Finished Aug 05 04:58:03 PM PDT 24
Peak memory 207224 kb
Host smart-bafbb4b3-9fa0-4112-82cb-a3267907f141
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3758309200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3758309200
Directory /workspace/6.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2007419147
Short name T3156
Test name
Test status
Simulation time 106649274 ps
CPU time 2.33 seconds
Started Aug 05 04:57:51 PM PDT 24
Finished Aug 05 04:57:53 PM PDT 24
Peak memory 215724 kb
Host smart-2052bd17-5cb7-47c3-aed9-3d453bc8110a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007419147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2007419147
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3934237237
Short name T255
Test name
Test status
Simulation time 59961482 ps
CPU time 0.81 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:58 PM PDT 24
Peak memory 207008 kb
Host smart-1679271f-77f6-4469-98e8-9b130ce931f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3934237237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3934237237
Directory /workspace/7.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2240315800
Short name T3214
Test name
Test status
Simulation time 44503726 ps
CPU time 0.76 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:58 PM PDT 24
Peak memory 206748 kb
Host smart-52a244c0-af86-4e3c-b77a-6206ec72e265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2240315800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2240315800
Directory /workspace/7.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1576140746
Short name T3194
Test name
Test status
Simulation time 210439542 ps
CPU time 1.77 seconds
Started Aug 05 04:57:56 PM PDT 24
Finished Aug 05 04:57:58 PM PDT 24
Peak memory 207136 kb
Host smart-e8464993-24d9-47e8-b9c3-1ec306eca45c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1576140746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1576140746
Directory /workspace/7.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2904211839
Short name T235
Test name
Test status
Simulation time 300554508 ps
CPU time 3.82 seconds
Started Aug 05 04:57:59 PM PDT 24
Finished Aug 05 04:58:03 PM PDT 24
Peak memory 221192 kb
Host smart-eaa7693d-5c3c-4744-b680-975d226a312e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2904211839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2904211839
Directory /workspace/7.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1518468016
Short name T243
Test name
Test status
Simulation time 112065301 ps
CPU time 1.3 seconds
Started Aug 05 04:58:07 PM PDT 24
Finished Aug 05 04:58:14 PM PDT 24
Peak memory 215436 kb
Host smart-db69bb73-0e89-4006-98b6-dfacf523a048
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518468016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1518468016
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.188133494
Short name T259
Test name
Test status
Simulation time 55136139 ps
CPU time 0.92 seconds
Started Aug 05 04:57:56 PM PDT 24
Finished Aug 05 04:57:57 PM PDT 24
Peak memory 206932 kb
Host smart-584a8f49-1964-4cb2-9413-fc24aa4def6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=188133494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.188133494
Directory /workspace/8.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4082869838
Short name T3183
Test name
Test status
Simulation time 61911896 ps
CPU time 0.74 seconds
Started Aug 05 04:58:04 PM PDT 24
Finished Aug 05 04:58:05 PM PDT 24
Peak memory 206784 kb
Host smart-dbd7f4c4-f630-450c-be7b-73d14b0b9c28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4082869838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.4082869838
Directory /workspace/8.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3371775673
Short name T270
Test name
Test status
Simulation time 465273953 ps
CPU time 1.91 seconds
Started Aug 05 04:57:57 PM PDT 24
Finished Aug 05 04:57:59 PM PDT 24
Peak memory 206980 kb
Host smart-9bdc1705-f27d-48e7-990f-59ff1157fb58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3371775673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3371775673
Directory /workspace/8.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3920780299
Short name T3180
Test name
Test status
Simulation time 59721385 ps
CPU time 1.86 seconds
Started Aug 05 04:58:00 PM PDT 24
Finished Aug 05 04:58:02 PM PDT 24
Peak memory 215392 kb
Host smart-344c815b-edcc-4468-ae02-65f72b702534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3920780299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3920780299
Directory /workspace/8.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2479813007
Short name T232
Test name
Test status
Simulation time 411811695 ps
CPU time 2.85 seconds
Started Aug 05 04:57:53 PM PDT 24
Finished Aug 05 04:57:56 PM PDT 24
Peak memory 207124 kb
Host smart-3b3551d6-5f7b-43a3-9f15-35f741e21a19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2479813007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2479813007
Directory /workspace/8.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1453011844
Short name T3186
Test name
Test status
Simulation time 106944984 ps
CPU time 1.3 seconds
Started Aug 05 04:57:52 PM PDT 24
Finished Aug 05 04:57:53 PM PDT 24
Peak memory 215504 kb
Host smart-bdcd645c-afb9-4e78-a6e5-710291ddac54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453011844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1453011844
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1867256930
Short name T3168
Test name
Test status
Simulation time 83260647 ps
CPU time 0.9 seconds
Started Aug 05 04:57:56 PM PDT 24
Finished Aug 05 04:57:57 PM PDT 24
Peak memory 206884 kb
Host smart-7a446716-14c3-4927-977b-f91018a1f5f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1867256930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1867256930
Directory /workspace/9.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.31273139
Short name T3149
Test name
Test status
Simulation time 91536794 ps
CPU time 0.8 seconds
Started Aug 05 04:57:58 PM PDT 24
Finished Aug 05 04:57:59 PM PDT 24
Peak memory 206796 kb
Host smart-a3941a12-c669-4471-88d3-24a96ad09f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=31273139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.31273139
Directory /workspace/9.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.580497349
Short name T226
Test name
Test status
Simulation time 163669997 ps
CPU time 1.63 seconds
Started Aug 05 04:57:55 PM PDT 24
Finished Aug 05 04:57:57 PM PDT 24
Peak memory 207252 kb
Host smart-875c3d22-4c1a-4edc-b42e-f4c7e6deefe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=580497349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.580497349
Directory /workspace/9.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.592899542
Short name T3147
Test name
Test status
Simulation time 230709403 ps
CPU time 2.57 seconds
Started Aug 05 04:58:03 PM PDT 24
Finished Aug 05 04:58:06 PM PDT 24
Peak memory 223308 kb
Host smart-17167327-a86f-4e3d-9c62-903da9f273c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=592899542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.592899542
Directory /workspace/9.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2909304609
Short name T230
Test name
Test status
Simulation time 792464286 ps
CPU time 3.33 seconds
Started Aug 05 04:57:55 PM PDT 24
Finished Aug 05 04:57:58 PM PDT 24
Peak memory 207104 kb
Host smart-f2916ac6-2efc-4fb4-8802-94246f1f1a31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2909304609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2909304609
Directory /workspace/9.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/0.usbdev_alert_test.129625474
Short name T3037
Test name
Test status
Simulation time 44113294 ps
CPU time 0.65 seconds
Started Aug 05 05:33:02 PM PDT 24
Finished Aug 05 05:33:03 PM PDT 24
Peak memory 207376 kb
Host smart-ab6d0c30-17b7-451a-8ac9-e9f98cf63d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=129625474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.129625474
Directory /workspace/0.usbdev_alert_test/latest


Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.726777642
Short name T1701
Test name
Test status
Simulation time 11311165780 ps
CPU time 13.76 seconds
Started Aug 05 05:32:44 PM PDT 24
Finished Aug 05 05:32:58 PM PDT 24
Peak memory 207532 kb
Host smart-94aa0874-d04a-4371-be1b-792081b18ead
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726777642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon
_wake_disconnect.726777642
Directory /workspace/0.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.753563961
Short name T2977
Test name
Test status
Simulation time 30266571374 ps
CPU time 38.77 seconds
Started Aug 05 05:32:45 PM PDT 24
Finished Aug 05 05:33:24 PM PDT 24
Peak memory 207716 kb
Host smart-7294c5f7-c101-4c57-8124-e37b01c245df
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753563961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon
_wake_resume.753563961
Directory /workspace/0.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/0.usbdev_av_buffer.1910510880
Short name T2003
Test name
Test status
Simulation time 188737884 ps
CPU time 0.94 seconds
Started Aug 05 05:32:48 PM PDT 24
Finished Aug 05 05:32:50 PM PDT 24
Peak memory 207368 kb
Host smart-f09d5dcc-c2d5-4945-8f5b-797778523732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105
10880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1910510880
Directory /workspace/0.usbdev_av_buffer/latest


Test location /workspace/coverage/default/0.usbdev_bitstuff_err.614556746
Short name T1479
Test name
Test status
Simulation time 141388541 ps
CPU time 0.85 seconds
Started Aug 05 05:32:43 PM PDT 24
Finished Aug 05 05:32:44 PM PDT 24
Peak memory 207316 kb
Host smart-80b3461a-7285-49e7-9c44-cd8f65beac6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61455
6746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.614556746
Directory /workspace/0.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.604867047
Short name T2533
Test name
Test status
Simulation time 427659709 ps
CPU time 1.54 seconds
Started Aug 05 05:32:47 PM PDT 24
Finished Aug 05 05:32:48 PM PDT 24
Peak memory 207604 kb
Host smart-9a6fa45d-4a22-48dc-aae1-0642ebfb69d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60486
7047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.604867047
Directory /workspace/0.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2997711581
Short name T2587
Test name
Test status
Simulation time 612851631 ps
CPU time 1.83 seconds
Started Aug 05 05:32:53 PM PDT 24
Finished Aug 05 05:32:55 PM PDT 24
Peak memory 207252 kb
Host smart-ea082b3c-15f7-4318-8ea0-e76990580273
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2997711581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2997711581
Directory /workspace/0.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/0.usbdev_device_address.3816263156
Short name T967
Test name
Test status
Simulation time 38162848503 ps
CPU time 58.13 seconds
Started Aug 05 05:32:43 PM PDT 24
Finished Aug 05 05:33:42 PM PDT 24
Peak memory 207652 kb
Host smart-42a6b269-e7b2-4a7c-8d0b-e3010934a290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38162
63156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3816263156
Directory /workspace/0.usbdev_device_address/latest


Test location /workspace/coverage/default/0.usbdev_device_timeout.1225741973
Short name T713
Test name
Test status
Simulation time 1021200570 ps
CPU time 22.16 seconds
Started Aug 05 05:32:54 PM PDT 24
Finished Aug 05 05:33:17 PM PDT 24
Peak memory 207468 kb
Host smart-d4d8dacf-d2f7-47be-a93b-257715fda692
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225741973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.1225741973
Directory /workspace/0.usbdev_device_timeout/latest


Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3331926468
Short name T2858
Test name
Test status
Simulation time 747165708 ps
CPU time 1.84 seconds
Started Aug 05 05:32:42 PM PDT 24
Finished Aug 05 05:32:44 PM PDT 24
Peak memory 207216 kb
Host smart-7d7441c4-5f5d-4280-b9fe-5ba55348480b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33319
26468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3331926468
Directory /workspace/0.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/0.usbdev_disconnected.1317049248
Short name T1634
Test name
Test status
Simulation time 136719092 ps
CPU time 0.82 seconds
Started Aug 05 05:32:45 PM PDT 24
Finished Aug 05 05:32:45 PM PDT 24
Peak memory 207344 kb
Host smart-d2da6ad9-6093-4190-8b90-fa7393b574c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13170
49248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1317049248
Directory /workspace/0.usbdev_disconnected/latest


Test location /workspace/coverage/default/0.usbdev_enable.1627649930
Short name T2798
Test name
Test status
Simulation time 38591518 ps
CPU time 0.7 seconds
Started Aug 05 05:32:44 PM PDT 24
Finished Aug 05 05:32:45 PM PDT 24
Peak memory 207316 kb
Host smart-45eb7d47-05a3-43cd-9377-b26648a60f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16276
49930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1627649930
Directory /workspace/0.usbdev_enable/latest


Test location /workspace/coverage/default/0.usbdev_endpoint_access.3643181927
Short name T2869
Test name
Test status
Simulation time 765152188 ps
CPU time 1.94 seconds
Started Aug 05 05:32:46 PM PDT 24
Finished Aug 05 05:32:48 PM PDT 24
Peak memory 207524 kb
Host smart-1c2bdd79-ef5e-4896-82fe-4144ce8396bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36431
81927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3643181927
Directory /workspace/0.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/0.usbdev_endpoint_types.2739853719
Short name T367
Test name
Test status
Simulation time 676188226 ps
CPU time 1.52 seconds
Started Aug 05 05:32:48 PM PDT 24
Finished Aug 05 05:32:50 PM PDT 24
Peak memory 207344 kb
Host smart-8d150243-0f6e-464e-9754-60d699dc67f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2739853719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.2739853719
Directory /workspace/0.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/0.usbdev_fifo_rst.946407261
Short name T3067
Test name
Test status
Simulation time 176999324 ps
CPU time 1.77 seconds
Started Aug 05 05:32:49 PM PDT 24
Finished Aug 05 05:32:51 PM PDT 24
Peak memory 207392 kb
Host smart-32bdccbe-9d34-4e83-837d-19d159293e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94640
7261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.946407261
Directory /workspace/0.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/0.usbdev_freq_hiclk.418101986
Short name T1237
Test name
Test status
Simulation time 101179161007 ps
CPU time 159.95 seconds
Started Aug 05 05:32:43 PM PDT 24
Finished Aug 05 05:35:23 PM PDT 24
Peak memory 207568 kb
Host smart-02a90e62-3501-4e0d-8445-85d98397677b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=418101986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.418101986
Directory /workspace/0.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2586669247
Short name T2851
Test name
Test status
Simulation time 96159841541 ps
CPU time 138.94 seconds
Started Aug 05 05:32:43 PM PDT 24
Finished Aug 05 05:35:02 PM PDT 24
Peak memory 207560 kb
Host smart-ea0b9896-1bf8-46c2-b870-56806ccc0c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586669247 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2586669247
Directory /workspace/0.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/0.usbdev_freq_loclk.586434718
Short name T1042
Test name
Test status
Simulation time 89100906444 ps
CPU time 151.05 seconds
Started Aug 05 05:32:46 PM PDT 24
Finished Aug 05 05:35:17 PM PDT 24
Peak memory 207696 kb
Host smart-8ba4dff1-6467-40d1-9cf5-fb44cc42dab8
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=586434718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.586434718
Directory /workspace/0.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.2804022392
Short name T1604
Test name
Test status
Simulation time 88129782974 ps
CPU time 140.02 seconds
Started Aug 05 05:32:47 PM PDT 24
Finished Aug 05 05:35:07 PM PDT 24
Peak memory 207664 kb
Host smart-6dcea52e-726b-489e-a91f-b562bd3ea77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804022392 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.2804022392
Directory /workspace/0.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/0.usbdev_freq_phase.1728468631
Short name T1738
Test name
Test status
Simulation time 103121158263 ps
CPU time 181.79 seconds
Started Aug 05 05:32:46 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 207708 kb
Host smart-2f8a0338-fcc8-4f86-8a60-41570f04e382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17284
68631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.1728468631
Directory /workspace/0.usbdev_freq_phase/latest


Test location /workspace/coverage/default/0.usbdev_in_iso.972005401
Short name T2144
Test name
Test status
Simulation time 244505402 ps
CPU time 1.2 seconds
Started Aug 05 05:32:46 PM PDT 24
Finished Aug 05 05:32:47 PM PDT 24
Peak memory 215776 kb
Host smart-9b84eebb-0311-429e-86d4-938e17a8b092
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=972005401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.972005401
Directory /workspace/0.usbdev_in_iso/latest


Test location /workspace/coverage/default/0.usbdev_in_stall.73271308
Short name T2624
Test name
Test status
Simulation time 165477096 ps
CPU time 0.81 seconds
Started Aug 05 05:32:43 PM PDT 24
Finished Aug 05 05:32:44 PM PDT 24
Peak memory 207336 kb
Host smart-195d2086-59d7-4ce2-b2c3-2b880c5c4d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73271
308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.73271308
Directory /workspace/0.usbdev_in_stall/latest


Test location /workspace/coverage/default/0.usbdev_in_trans.3552296143
Short name T1440
Test name
Test status
Simulation time 199740043 ps
CPU time 0.94 seconds
Started Aug 05 05:32:51 PM PDT 24
Finished Aug 05 05:32:52 PM PDT 24
Peak memory 207252 kb
Host smart-be52b70d-134e-4902-b6e0-6dd27f823f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35522
96143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3552296143
Directory /workspace/0.usbdev_in_trans/latest


Test location /workspace/coverage/default/0.usbdev_invalid_sync.1845794474
Short name T6
Test name
Test status
Simulation time 2613494335 ps
CPU time 26.09 seconds
Started Aug 05 05:32:47 PM PDT 24
Finished Aug 05 05:33:13 PM PDT 24
Peak memory 217660 kb
Host smart-9eb6c97e-30bd-40a3-aae8-511205739134
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1845794474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1845794474
Directory /workspace/0.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/0.usbdev_iso_retraction.999543978
Short name T2257
Test name
Test status
Simulation time 5760996339 ps
CPU time 37.45 seconds
Started Aug 05 05:32:45 PM PDT 24
Finished Aug 05 05:33:23 PM PDT 24
Peak memory 207620 kb
Host smart-e5d13978-f0b0-4a2f-bc95-f76d4660185e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=999543978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.999543978
Directory /workspace/0.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/0.usbdev_link_in_err.2888473034
Short name T2892
Test name
Test status
Simulation time 261961113 ps
CPU time 1.06 seconds
Started Aug 05 05:32:47 PM PDT 24
Finished Aug 05 05:32:48 PM PDT 24
Peak memory 207356 kb
Host smart-bf6657c5-8f57-4bd6-a5e4-197dafec8f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28884
73034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2888473034
Directory /workspace/0.usbdev_link_in_err/latest


Test location /workspace/coverage/default/0.usbdev_link_out_err.4122919790
Short name T77
Test name
Test status
Simulation time 427307167 ps
CPU time 1.52 seconds
Started Aug 05 05:32:45 PM PDT 24
Finished Aug 05 05:32:47 PM PDT 24
Peak memory 207396 kb
Host smart-5af35567-dd7b-4f21-aa83-947712730c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41229
19790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.4122919790
Directory /workspace/0.usbdev_link_out_err/latest


Test location /workspace/coverage/default/0.usbdev_link_resume.1366983067
Short name T1252
Test name
Test status
Simulation time 30993289031 ps
CPU time 47.89 seconds
Started Aug 05 05:32:49 PM PDT 24
Finished Aug 05 05:33:37 PM PDT 24
Peak memory 207712 kb
Host smart-b4633956-2d93-4f0d-adc1-fd161914f926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
83067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1366983067
Directory /workspace/0.usbdev_link_resume/latest


Test location /workspace/coverage/default/0.usbdev_link_suspend.1457077275
Short name T2271
Test name
Test status
Simulation time 3704817673 ps
CPU time 5.96 seconds
Started Aug 05 05:32:52 PM PDT 24
Finished Aug 05 05:32:58 PM PDT 24
Peak memory 215728 kb
Host smart-26e2657d-d9b2-4d79-9d6d-b82d85f11b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14570
77275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1457077275
Directory /workspace/0.usbdev_link_suspend/latest


Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.131896242
Short name T3126
Test name
Test status
Simulation time 2873960070 ps
CPU time 78.54 seconds
Started Aug 05 05:32:52 PM PDT 24
Finished Aug 05 05:34:10 PM PDT 24
Peak memory 218152 kb
Host smart-bbfebbbe-bcb9-4960-b209-4959c049f077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13189
6242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.131896242
Directory /workspace/0.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3144170240
Short name T1656
Test name
Test status
Simulation time 3039371605 ps
CPU time 34.03 seconds
Started Aug 05 05:32:52 PM PDT 24
Finished Aug 05 05:33:26 PM PDT 24
Peak memory 215884 kb
Host smart-00d3259e-4929-422e-92c1-322501de8ce0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3144170240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3144170240
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2534516525
Short name T3056
Test name
Test status
Simulation time 289722303 ps
CPU time 1.09 seconds
Started Aug 05 05:32:51 PM PDT 24
Finished Aug 05 05:32:52 PM PDT 24
Peak memory 207360 kb
Host smart-08bb4047-303a-4187-a7fa-3f29e0383a34
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2534516525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2534516525
Directory /workspace/0.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2906258511
Short name T623
Test name
Test status
Simulation time 183769794 ps
CPU time 0.9 seconds
Started Aug 05 05:32:52 PM PDT 24
Finished Aug 05 05:32:53 PM PDT 24
Peak memory 207368 kb
Host smart-060c6641-1557-474b-b26d-9dd83bbc41e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29062
58511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2906258511
Directory /workspace/0.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.3021278831
Short name T1991
Test name
Test status
Simulation time 2766081805 ps
CPU time 22.02 seconds
Started Aug 05 05:32:51 PM PDT 24
Finished Aug 05 05:33:13 PM PDT 24
Peak memory 217780 kb
Host smart-bc1b95f5-c7fa-4393-80e8-d60734f47c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30212
78831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.3021278831
Directory /workspace/0.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.1430540616
Short name T5
Test name
Test status
Simulation time 2443969697 ps
CPU time 24.43 seconds
Started Aug 05 05:32:54 PM PDT 24
Finished Aug 05 05:33:19 PM PDT 24
Peak memory 217536 kb
Host smart-b775069d-9116-471b-9660-f61a4e3d254d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1430540616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1430540616
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.704364038
Short name T803
Test name
Test status
Simulation time 165394577 ps
CPU time 0.83 seconds
Started Aug 05 05:32:49 PM PDT 24
Finished Aug 05 05:32:50 PM PDT 24
Peak memory 207364 kb
Host smart-02872158-f1b1-4905-867e-e5462aeff0fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=704364038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.704364038
Directory /workspace/0.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1376054917
Short name T1606
Test name
Test status
Simulation time 171398287 ps
CPU time 0.91 seconds
Started Aug 05 05:32:53 PM PDT 24
Finished Aug 05 05:32:54 PM PDT 24
Peak memory 207268 kb
Host smart-65adeaa7-5364-4633-aab6-f8e5c2abebb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13760
54917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1376054917
Directory /workspace/0.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2805546667
Short name T76
Test name
Test status
Simulation time 527817577 ps
CPU time 1.59 seconds
Started Aug 05 05:32:54 PM PDT 24
Finished Aug 05 05:32:55 PM PDT 24
Peak memory 207212 kb
Host smart-d8371121-e09b-4387-afd1-651c6c49bd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28055
46667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2805546667
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest


Test location /workspace/coverage/default/0.usbdev_out_iso.3288029789
Short name T1735
Test name
Test status
Simulation time 165570039 ps
CPU time 0.86 seconds
Started Aug 05 05:32:51 PM PDT 24
Finished Aug 05 05:32:52 PM PDT 24
Peak memory 207348 kb
Host smart-44991651-fde9-494e-9571-79d12af5c5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32880
29789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3288029789
Directory /workspace/0.usbdev_out_iso/latest


Test location /workspace/coverage/default/0.usbdev_out_stall.803173393
Short name T694
Test name
Test status
Simulation time 179568109 ps
CPU time 0.94 seconds
Started Aug 05 05:32:53 PM PDT 24
Finished Aug 05 05:32:54 PM PDT 24
Peak memory 207372 kb
Host smart-49a67fd8-6a85-439f-a341-6ebd0b16b8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80317
3393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.803173393
Directory /workspace/0.usbdev_out_stall/latest


Test location /workspace/coverage/default/0.usbdev_out_trans_nak.710462751
Short name T1351
Test name
Test status
Simulation time 159249493 ps
CPU time 0.9 seconds
Started Aug 05 05:32:51 PM PDT 24
Finished Aug 05 05:32:52 PM PDT 24
Peak memory 207228 kb
Host smart-5b332d52-e1f9-4036-87cb-6d06a4a2ff6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71046
2751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.710462751
Directory /workspace/0.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/0.usbdev_pending_in_trans.4117162118
Short name T2484
Test name
Test status
Simulation time 170049399 ps
CPU time 0.87 seconds
Started Aug 05 05:32:53 PM PDT 24
Finished Aug 05 05:32:54 PM PDT 24
Peak memory 207400 kb
Host smart-906bb21e-4549-4174-bab0-429de4d988de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41171
62118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.4117162118
Directory /workspace/0.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2001922923
Short name T1115
Test name
Test status
Simulation time 251017604 ps
CPU time 1.01 seconds
Started Aug 05 05:32:49 PM PDT 24
Finished Aug 05 05:32:50 PM PDT 24
Peak memory 207392 kb
Host smart-755f9612-24c2-4843-892e-1651246ceb38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20019
22923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2001922923
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.686127761
Short name T1119
Test name
Test status
Simulation time 236839663 ps
CPU time 1.1 seconds
Started Aug 05 05:32:53 PM PDT 24
Finished Aug 05 05:32:54 PM PDT 24
Peak memory 207396 kb
Host smart-26ecb91f-05a6-41cd-a649-1e97825ac8f4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=686127761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.686127761
Directory /workspace/0.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3311745960
Short name T2524
Test name
Test status
Simulation time 217354965 ps
CPU time 0.98 seconds
Started Aug 05 05:32:50 PM PDT 24
Finished Aug 05 05:32:51 PM PDT 24
Peak memory 207272 kb
Host smart-f559aea1-d7d9-4a95-bf64-b9b3b5962c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33117
45960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3311745960
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.591873679
Short name T2602
Test name
Test status
Simulation time 239194098 ps
CPU time 1.11 seconds
Started Aug 05 05:32:55 PM PDT 24
Finished Aug 05 05:32:56 PM PDT 24
Peak memory 207272 kb
Host smart-b6f74a71-ccaa-4604-9a4a-e530c851ee0a
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=591873679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.591873679
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.222636869
Short name T208
Test name
Test status
Simulation time 212885340 ps
CPU time 1.03 seconds
Started Aug 05 05:32:53 PM PDT 24
Finished Aug 05 05:32:54 PM PDT 24
Peak memory 207336 kb
Host smart-ed05c654-b40c-4dcd-bfe9-bec1d8394114
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=222636869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.222636869
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest


Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2448818256
Short name T2160
Test name
Test status
Simulation time 9486763115 ps
CPU time 24.36 seconds
Started Aug 05 05:32:51 PM PDT 24
Finished Aug 05 05:33:15 PM PDT 24
Peak memory 215860 kb
Host smart-78b95f26-7cb8-428c-bf80-a3745ccc2247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24488
18256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2448818256
Directory /workspace/0.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/0.usbdev_pkt_received.290102885
Short name T2720
Test name
Test status
Simulation time 156117076 ps
CPU time 0.86 seconds
Started Aug 05 05:32:53 PM PDT 24
Finished Aug 05 05:32:54 PM PDT 24
Peak memory 207308 kb
Host smart-1298bedc-96c8-4e50-896c-167f31a99130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29010
2885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.290102885
Directory /workspace/0.usbdev_pkt_received/latest


Test location /workspace/coverage/default/0.usbdev_pkt_sent.1739977363
Short name T2620
Test name
Test status
Simulation time 162322270 ps
CPU time 0.93 seconds
Started Aug 05 05:32:54 PM PDT 24
Finished Aug 05 05:32:55 PM PDT 24
Peak memory 207240 kb
Host smart-e31a2547-c102-43b0-a6e9-5a67483c3d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17399
77363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1739977363
Directory /workspace/0.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1578512298
Short name T1177
Test name
Test status
Simulation time 5280357076 ps
CPU time 18.72 seconds
Started Aug 05 05:32:55 PM PDT 24
Finished Aug 05 05:33:14 PM PDT 24
Peak memory 223936 kb
Host smart-600afa5f-4df3-4d7e-b54c-c9b334879697
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578512298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1578512298
Directory /workspace/0.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2381804394
Short name T2787
Test name
Test status
Simulation time 5310050141 ps
CPU time 22.07 seconds
Started Aug 05 05:32:55 PM PDT 24
Finished Aug 05 05:33:18 PM PDT 24
Peak memory 224040 kb
Host smart-5907961d-6e17-4512-ad65-8dc4ba008431
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2381804394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2381804394
Directory /workspace/0.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/0.usbdev_rand_suspends.3028741491
Short name T2321
Test name
Test status
Simulation time 14610916312 ps
CPU time 84.14 seconds
Started Aug 05 05:33:00 PM PDT 24
Finished Aug 05 05:34:24 PM PDT 24
Peak memory 223916 kb
Host smart-67ad4e6d-08c5-4582-ba83-e3f0f97ca08d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028741491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3028741491
Directory /workspace/0.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3952359668
Short name T2297
Test name
Test status
Simulation time 179970388 ps
CPU time 0.88 seconds
Started Aug 05 05:32:51 PM PDT 24
Finished Aug 05 05:32:52 PM PDT 24
Peak memory 207316 kb
Host smart-6b9a0a98-41a3-4d87-b52d-b88aba10afd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39523
59668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3952359668
Directory /workspace/0.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/0.usbdev_resume_link_active.63080011
Short name T2807
Test name
Test status
Simulation time 20191337536 ps
CPU time 30.75 seconds
Started Aug 05 05:32:55 PM PDT 24
Finished Aug 05 05:33:26 PM PDT 24
Peak memory 207420 kb
Host smart-4e74b5ad-0d2d-4a92-8dae-f571fe1ccb6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63080
011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.63080011
Directory /workspace/0.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/0.usbdev_rx_crc_err.3428977348
Short name T2184
Test name
Test status
Simulation time 172190635 ps
CPU time 0.92 seconds
Started Aug 05 05:32:57 PM PDT 24
Finished Aug 05 05:32:58 PM PDT 24
Peak memory 207468 kb
Host smart-1ab2c0f0-e812-49df-b427-db8221f132a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34289
77348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.3428977348
Directory /workspace/0.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/0.usbdev_rx_full.4172383939
Short name T3061
Test name
Test status
Simulation time 251891595 ps
CPU time 1.16 seconds
Started Aug 05 05:32:59 PM PDT 24
Finished Aug 05 05:33:00 PM PDT 24
Peak memory 207396 kb
Host smart-ab0122f0-0214-4fb9-b8af-9456094547f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41723
83939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.4172383939
Directory /workspace/0.usbdev_rx_full/latest


Test location /workspace/coverage/default/0.usbdev_sec_cm.1463860353
Short name T216
Test name
Test status
Simulation time 451607054 ps
CPU time 1.25 seconds
Started Aug 05 05:32:58 PM PDT 24
Finished Aug 05 05:33:00 PM PDT 24
Peak memory 224416 kb
Host smart-4c09fcbf-d65b-4619-9e1d-d97a09b77a6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1463860353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1463860353
Directory /workspace/0.usbdev_sec_cm/latest


Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.3035364331
Short name T1222
Test name
Test status
Simulation time 312231652 ps
CPU time 1.06 seconds
Started Aug 05 05:32:56 PM PDT 24
Finished Aug 05 05:32:57 PM PDT 24
Peak memory 207340 kb
Host smart-343f0578-d7c1-4926-baa7-f1dd76d400b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30353
64331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.3035364331
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/0.usbdev_setup_stage.1207230253
Short name T2645
Test name
Test status
Simulation time 149164378 ps
CPU time 0.85 seconds
Started Aug 05 05:33:01 PM PDT 24
Finished Aug 05 05:33:02 PM PDT 24
Peak memory 207316 kb
Host smart-a468beaa-596a-4d3e-9f72-8cffe787c1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12072
30253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1207230253
Directory /workspace/0.usbdev_setup_stage/latest


Test location /workspace/coverage/default/0.usbdev_smoke.2420443473
Short name T3043
Test name
Test status
Simulation time 238863231 ps
CPU time 1.09 seconds
Started Aug 05 05:32:56 PM PDT 24
Finished Aug 05 05:32:57 PM PDT 24
Peak memory 207268 kb
Host smart-d2067270-e33e-45ac-8c55-3ceaf32969f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24204
43473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2420443473
Directory /workspace/0.usbdev_smoke/latest


Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.2140857246
Short name T24
Test name
Test status
Simulation time 2950226368 ps
CPU time 30.25 seconds
Started Aug 05 05:32:58 PM PDT 24
Finished Aug 05 05:33:29 PM PDT 24
Peak memory 217696 kb
Host smart-b7a6cf12-bd76-4959-9229-92debffaf55b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2140857246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2140857246
Directory /workspace/0.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2985020869
Short name T1368
Test name
Test status
Simulation time 191472270 ps
CPU time 0.86 seconds
Started Aug 05 05:33:01 PM PDT 24
Finished Aug 05 05:33:02 PM PDT 24
Peak memory 207352 kb
Host smart-8ddba70c-9901-41a1-9f73-fe607b1a2997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29850
20869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2985020869
Directory /workspace/0.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/0.usbdev_stall_trans.2384382467
Short name T1486
Test name
Test status
Simulation time 186002097 ps
CPU time 0.87 seconds
Started Aug 05 05:32:56 PM PDT 24
Finished Aug 05 05:32:57 PM PDT 24
Peak memory 207268 kb
Host smart-29c20ee0-0f12-4a02-8742-58c64d8e49a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23843
82467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2384382467
Directory /workspace/0.usbdev_stall_trans/latest


Test location /workspace/coverage/default/0.usbdev_stream_len_max.2090384406
Short name T1506
Test name
Test status
Simulation time 1005115998 ps
CPU time 2.48 seconds
Started Aug 05 05:32:57 PM PDT 24
Finished Aug 05 05:33:00 PM PDT 24
Peak memory 207548 kb
Host smart-bd6418b4-6476-4d4c-9d50-0e9e187a3065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20903
84406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.2090384406
Directory /workspace/0.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/0.usbdev_streaming_out.649752209
Short name T1940
Test name
Test status
Simulation time 3719157928 ps
CPU time 108.02 seconds
Started Aug 05 05:33:00 PM PDT 24
Finished Aug 05 05:34:48 PM PDT 24
Peak memory 215928 kb
Host smart-a64c32ac-e8f4-4a40-b1e9-365aa41c5159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64975
2209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.649752209
Directory /workspace/0.usbdev_streaming_out/latest


Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3151090706
Short name T90
Test name
Test status
Simulation time 2704566172 ps
CPU time 68.08 seconds
Started Aug 05 05:32:57 PM PDT 24
Finished Aug 05 05:34:05 PM PDT 24
Peak memory 218212 kb
Host smart-c809f250-5de2-40e7-84f6-c46bc094b025
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151090706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3151090706
Directory /workspace/0.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.2333563012
Short name T3038
Test name
Test status
Simulation time 2912993139 ps
CPU time 20.27 seconds
Started Aug 05 05:32:48 PM PDT 24
Finished Aug 05 05:33:08 PM PDT 24
Peak memory 207900 kb
Host smart-aaa436a1-eb38-4ca4-97f8-ab9e9acda4bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333563012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.2333563012
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/1.usbdev_alert_test.1342799168
Short name T2914
Test name
Test status
Simulation time 72444779 ps
CPU time 0.7 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:12 PM PDT 24
Peak memory 207396 kb
Host smart-3abd81e9-85eb-4242-acea-895fc6f6bfef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1342799168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1342799168
Directory /workspace/1.usbdev_alert_test/latest


Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2768549745
Short name T695
Test name
Test status
Simulation time 6084768589 ps
CPU time 10.01 seconds
Started Aug 05 05:33:01 PM PDT 24
Finished Aug 05 05:33:12 PM PDT 24
Peak memory 215816 kb
Host smart-22e762c1-8bea-456f-a523-1099c20e1fb7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768549745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.2768549745
Directory /workspace/1.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.237170577
Short name T2238
Test name
Test status
Simulation time 29680593845 ps
CPU time 34.93 seconds
Started Aug 05 05:32:57 PM PDT 24
Finished Aug 05 05:33:32 PM PDT 24
Peak memory 207608 kb
Host smart-4cae0638-4902-4aac-81f2-32a6adbaee0e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237170577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon
_wake_resume.237170577
Directory /workspace/1.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/1.usbdev_av_buffer.606386272
Short name T721
Test name
Test status
Simulation time 172471008 ps
CPU time 0.88 seconds
Started Aug 05 05:32:59 PM PDT 24
Finished Aug 05 05:33:00 PM PDT 24
Peak memory 207388 kb
Host smart-09a76472-98c5-4c27-bd98-3b19f2e81878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60638
6272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.606386272
Directory /workspace/1.usbdev_av_buffer/latest


Test location /workspace/coverage/default/1.usbdev_av_empty.2716655956
Short name T52
Test name
Test status
Simulation time 141738956 ps
CPU time 0.85 seconds
Started Aug 05 05:32:57 PM PDT 24
Finished Aug 05 05:32:58 PM PDT 24
Peak memory 207256 kb
Host smart-9fdcc5e4-5bd4-45a0-a379-e2dce162be07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27166
55956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2716655956
Directory /workspace/1.usbdev_av_empty/latest


Test location /workspace/coverage/default/1.usbdev_bitstuff_err.3170872118
Short name T2898
Test name
Test status
Simulation time 146978958 ps
CPU time 0.9 seconds
Started Aug 05 05:32:59 PM PDT 24
Finished Aug 05 05:33:00 PM PDT 24
Peak memory 207316 kb
Host smart-2a8f8266-a662-45a7-9bc1-b84a20fb161f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31708
72118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.3170872118
Directory /workspace/1.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1338347535
Short name T2329
Test name
Test status
Simulation time 356855309 ps
CPU time 1.2 seconds
Started Aug 05 05:32:56 PM PDT 24
Finished Aug 05 05:32:57 PM PDT 24
Peak memory 207372 kb
Host smart-a40d38cc-16e4-491b-9e66-efd958620deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13383
47535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1338347535
Directory /workspace/1.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.4202287504
Short name T1912
Test name
Test status
Simulation time 934072946 ps
CPU time 2.47 seconds
Started Aug 05 05:32:57 PM PDT 24
Finished Aug 05 05:33:00 PM PDT 24
Peak memory 207568 kb
Host smart-7fe04b92-c5c6-4757-bd55-6c34f610553b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4202287504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.4202287504
Directory /workspace/1.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/1.usbdev_device_address.40926395
Short name T1562
Test name
Test status
Simulation time 19346123421 ps
CPU time 31.53 seconds
Started Aug 05 05:32:57 PM PDT 24
Finished Aug 05 05:33:29 PM PDT 24
Peak memory 207692 kb
Host smart-95694137-b672-4730-82ac-710c7e21303d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40926
395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.40926395
Directory /workspace/1.usbdev_device_address/latest


Test location /workspace/coverage/default/1.usbdev_device_timeout.249859043
Short name T1751
Test name
Test status
Simulation time 292561456 ps
CPU time 4.45 seconds
Started Aug 05 05:33:00 PM PDT 24
Finished Aug 05 05:33:04 PM PDT 24
Peak memory 207552 kb
Host smart-cd155ced-5e45-41f3-9c05-a9505ffa7d0a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249859043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.249859043
Directory /workspace/1.usbdev_device_timeout/latest


Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1569294294
Short name T2646
Test name
Test status
Simulation time 905157199 ps
CPU time 2.02 seconds
Started Aug 05 05:32:58 PM PDT 24
Finished Aug 05 05:33:00 PM PDT 24
Peak memory 207272 kb
Host smart-9ad5c2be-cebd-49f4-938e-7dc7ead24188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15692
94294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1569294294
Directory /workspace/1.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/1.usbdev_disconnected.309596685
Short name T2128
Test name
Test status
Simulation time 144343233 ps
CPU time 0.84 seconds
Started Aug 05 05:32:58 PM PDT 24
Finished Aug 05 05:32:58 PM PDT 24
Peak memory 207236 kb
Host smart-71f97f50-f562-4477-b290-62f007eb6e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30959
6685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.309596685
Directory /workspace/1.usbdev_disconnected/latest


Test location /workspace/coverage/default/1.usbdev_enable.3678242293
Short name T1608
Test name
Test status
Simulation time 57471566 ps
CPU time 0.77 seconds
Started Aug 05 05:32:58 PM PDT 24
Finished Aug 05 05:32:58 PM PDT 24
Peak memory 207328 kb
Host smart-c3b60f76-7b39-4f9a-9526-7ea0da934f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36782
42293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3678242293
Directory /workspace/1.usbdev_enable/latest


Test location /workspace/coverage/default/1.usbdev_endpoint_access.3648834916
Short name T2827
Test name
Test status
Simulation time 830856308 ps
CPU time 2.4 seconds
Started Aug 05 05:32:56 PM PDT 24
Finished Aug 05 05:32:58 PM PDT 24
Peak memory 207572 kb
Host smart-9a06e667-2ebe-41c1-a14b-42f650d08810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36488
34916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3648834916
Directory /workspace/1.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/1.usbdev_fifo_rst.1621646982
Short name T1029
Test name
Test status
Simulation time 392091936 ps
CPU time 2.53 seconds
Started Aug 05 05:33:04 PM PDT 24
Finished Aug 05 05:33:07 PM PDT 24
Peak memory 207480 kb
Host smart-ffb01ef1-b026-4e35-a762-70a459802afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16216
46982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1621646982
Directory /workspace/1.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.1996657800
Short name T480
Test name
Test status
Simulation time 119098508426 ps
CPU time 167.44 seconds
Started Aug 05 05:33:06 PM PDT 24
Finished Aug 05 05:35:53 PM PDT 24
Peak memory 207664 kb
Host smart-5bdfc688-665a-4901-be8c-fe792b219b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996657800 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.1996657800
Directory /workspace/1.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/1.usbdev_freq_loclk.1602821828
Short name T2502
Test name
Test status
Simulation time 116097292479 ps
CPU time 202.13 seconds
Started Aug 05 05:33:02 PM PDT 24
Finished Aug 05 05:36:24 PM PDT 24
Peak memory 207608 kb
Host smart-ea483bb6-917f-4b82-ad36-5fbaf6d3986f
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1602821828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.1602821828
Directory /workspace/1.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.1402609253
Short name T2112
Test name
Test status
Simulation time 106147613001 ps
CPU time 170.51 seconds
Started Aug 05 05:33:06 PM PDT 24
Finished Aug 05 05:35:57 PM PDT 24
Peak memory 207684 kb
Host smart-52c6baf1-8ed7-450c-ba2e-0e199efa0322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402609253 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.1402609253
Directory /workspace/1.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/1.usbdev_freq_phase.4152157878
Short name T1129
Test name
Test status
Simulation time 94135043049 ps
CPU time 163.1 seconds
Started Aug 05 05:33:06 PM PDT 24
Finished Aug 05 05:35:49 PM PDT 24
Peak memory 207504 kb
Host smart-ed7c9f71-383a-4b98-a735-9e04f9fb9792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41521
57878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.4152157878
Directory /workspace/1.usbdev_freq_phase/latest


Test location /workspace/coverage/default/1.usbdev_in_iso.657265461
Short name T2269
Test name
Test status
Simulation time 234288076 ps
CPU time 1.11 seconds
Started Aug 05 05:33:04 PM PDT 24
Finished Aug 05 05:33:05 PM PDT 24
Peak memory 215744 kb
Host smart-c1ff38dc-dd36-4b3c-a038-549c17529371
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=657265461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.657265461
Directory /workspace/1.usbdev_in_iso/latest


Test location /workspace/coverage/default/1.usbdev_in_stall.1134493411
Short name T1371
Test name
Test status
Simulation time 145904122 ps
CPU time 0.86 seconds
Started Aug 05 05:33:09 PM PDT 24
Finished Aug 05 05:33:10 PM PDT 24
Peak memory 207236 kb
Host smart-5a10daa7-1876-464b-aaa6-846dc3baf053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11344
93411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1134493411
Directory /workspace/1.usbdev_in_stall/latest


Test location /workspace/coverage/default/1.usbdev_in_trans.135026786
Short name T1246
Test name
Test status
Simulation time 248238072 ps
CPU time 1.02 seconds
Started Aug 05 05:33:09 PM PDT 24
Finished Aug 05 05:33:10 PM PDT 24
Peak memory 207264 kb
Host smart-b9c04be7-4805-4e8e-bdb3-4eae0134cf5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13502
6786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.135026786
Directory /workspace/1.usbdev_in_trans/latest


Test location /workspace/coverage/default/1.usbdev_invalid_sync.4022000251
Short name T972
Test name
Test status
Simulation time 5716339757 ps
CPU time 162.75 seconds
Started Aug 05 05:33:07 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 223800 kb
Host smart-2adb5bf7-d381-4ab2-8fc2-3f148e0f6dfc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4022000251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.4022000251
Directory /workspace/1.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/1.usbdev_iso_retraction.3761555370
Short name T3113
Test name
Test status
Simulation time 8535442793 ps
CPU time 59.82 seconds
Started Aug 05 05:33:05 PM PDT 24
Finished Aug 05 05:34:05 PM PDT 24
Peak memory 207500 kb
Host smart-5fd3de63-d389-4106-aec9-3142fe29b76a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3761555370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.3761555370
Directory /workspace/1.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/1.usbdev_link_in_err.3722930865
Short name T2546
Test name
Test status
Simulation time 221658756 ps
CPU time 0.95 seconds
Started Aug 05 05:33:02 PM PDT 24
Finished Aug 05 05:33:03 PM PDT 24
Peak memory 207404 kb
Host smart-3c17d6ec-a4ec-454b-bdfa-65de044707f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37229
30865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3722930865
Directory /workspace/1.usbdev_link_in_err/latest


Test location /workspace/coverage/default/1.usbdev_link_resume.2680187197
Short name T941
Test name
Test status
Simulation time 24403288505 ps
CPU time 40.71 seconds
Started Aug 05 05:33:07 PM PDT 24
Finished Aug 05 05:33:47 PM PDT 24
Peak memory 216084 kb
Host smart-c8ce79ee-855c-4b61-bb00-a0d48b326196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26801
87197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2680187197
Directory /workspace/1.usbdev_link_resume/latest


Test location /workspace/coverage/default/1.usbdev_link_suspend.181167353
Short name T2770
Test name
Test status
Simulation time 5481347249 ps
CPU time 8.24 seconds
Started Aug 05 05:33:06 PM PDT 24
Finished Aug 05 05:33:15 PM PDT 24
Peak memory 207600 kb
Host smart-8846cc0b-f7fe-415c-b2ba-9b5c1df24da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18116
7353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.181167353
Directory /workspace/1.usbdev_link_suspend/latest


Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.3611041392
Short name T163
Test name
Test status
Simulation time 3564721217 ps
CPU time 97.07 seconds
Started Aug 05 05:33:04 PM PDT 24
Finished Aug 05 05:34:41 PM PDT 24
Peak memory 218500 kb
Host smart-0d3b34cb-98f1-4a5f-a443-d4782694e95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36110
41392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.3611041392
Directory /workspace/1.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.3338174007
Short name T1792
Test name
Test status
Simulation time 4051347549 ps
CPU time 37.58 seconds
Started Aug 05 05:33:04 PM PDT 24
Finished Aug 05 05:33:41 PM PDT 24
Peak memory 215916 kb
Host smart-4789543a-a82c-4ab4-b4d1-7ebf4fea2e43
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3338174007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.3338174007
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3351087865
Short name T1492
Test name
Test status
Simulation time 241817391 ps
CPU time 1.02 seconds
Started Aug 05 05:33:05 PM PDT 24
Finished Aug 05 05:33:06 PM PDT 24
Peak memory 207388 kb
Host smart-5d096f99-be23-4e52-ab93-13e836d64ee3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3351087865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3351087865
Directory /workspace/1.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1559092791
Short name T547
Test name
Test status
Simulation time 242587844 ps
CPU time 1.03 seconds
Started Aug 05 05:33:02 PM PDT 24
Finished Aug 05 05:33:03 PM PDT 24
Peak memory 207424 kb
Host smart-4462c7bc-6693-448b-ac6d-985509a4b198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15590
92791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1559092791
Directory /workspace/1.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.3464117627
Short name T1326
Test name
Test status
Simulation time 2480323820 ps
CPU time 20.04 seconds
Started Aug 05 05:33:06 PM PDT 24
Finished Aug 05 05:33:26 PM PDT 24
Peak memory 215712 kb
Host smart-afaddbb5-4bba-4008-8e72-9793a37a52f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34641
17627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.3464117627
Directory /workspace/1.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3140615618
Short name T1550
Test name
Test status
Simulation time 4102036138 ps
CPU time 42.15 seconds
Started Aug 05 05:33:04 PM PDT 24
Finished Aug 05 05:33:46 PM PDT 24
Peak memory 223952 kb
Host smart-1583e38f-ed8e-4b88-af6a-5f3e51b9f581
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3140615618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3140615618
Directory /workspace/1.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2516553995
Short name T3106
Test name
Test status
Simulation time 2181051613 ps
CPU time 22.73 seconds
Started Aug 05 05:33:03 PM PDT 24
Finished Aug 05 05:33:26 PM PDT 24
Peak memory 215788 kb
Host smart-8a875e89-2391-408d-8437-c2c1a999f06f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2516553995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2516553995
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1983488249
Short name T2436
Test name
Test status
Simulation time 221094904 ps
CPU time 0.92 seconds
Started Aug 05 05:33:04 PM PDT 24
Finished Aug 05 05:33:05 PM PDT 24
Peak memory 207352 kb
Host smart-fdc2b873-3ff5-4243-815f-38fa7af2f9af
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1983488249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1983488249
Directory /workspace/1.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3994802490
Short name T2563
Test name
Test status
Simulation time 142777658 ps
CPU time 0.86 seconds
Started Aug 05 05:33:07 PM PDT 24
Finished Aug 05 05:33:08 PM PDT 24
Peak memory 207380 kb
Host smart-143bc993-1167-4985-88ff-15883277d1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39948
02490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3994802490
Directory /workspace/1.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/1.usbdev_out_iso.3613257231
Short name T2062
Test name
Test status
Simulation time 146304031 ps
CPU time 0.83 seconds
Started Aug 05 05:33:04 PM PDT 24
Finished Aug 05 05:33:05 PM PDT 24
Peak memory 207376 kb
Host smart-e526a751-f939-4241-a90c-f85a437dc4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36132
57231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3613257231
Directory /workspace/1.usbdev_out_iso/latest


Test location /workspace/coverage/default/1.usbdev_out_stall.2343087786
Short name T2684
Test name
Test status
Simulation time 210908721 ps
CPU time 0.94 seconds
Started Aug 05 05:33:09 PM PDT 24
Finished Aug 05 05:33:10 PM PDT 24
Peak memory 207268 kb
Host smart-b1cadfc0-8cc5-440d-ade2-bb28096e13fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
87786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2343087786
Directory /workspace/1.usbdev_out_stall/latest


Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2978483794
Short name T744
Test name
Test status
Simulation time 176124936 ps
CPU time 0.94 seconds
Started Aug 05 05:33:04 PM PDT 24
Finished Aug 05 05:33:05 PM PDT 24
Peak memory 207348 kb
Host smart-40327dce-bef6-4bfd-bf61-7bd771e770f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29784
83794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2978483794
Directory /workspace/1.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3412565898
Short name T2264
Test name
Test status
Simulation time 182622057 ps
CPU time 0.94 seconds
Started Aug 05 05:33:05 PM PDT 24
Finished Aug 05 05:33:06 PM PDT 24
Peak memory 207404 kb
Host smart-a97e056c-8b88-485f-92f6-fd2643cc79e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34125
65898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3412565898
Directory /workspace/1.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.855187378
Short name T1773
Test name
Test status
Simulation time 183312600 ps
CPU time 0.91 seconds
Started Aug 05 05:33:02 PM PDT 24
Finished Aug 05 05:33:03 PM PDT 24
Peak memory 207372 kb
Host smart-421390d1-d37b-4542-a0d7-25138938634e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=855187378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.855187378
Directory /workspace/1.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.2123206889
Short name T734
Test name
Test status
Simulation time 212505255 ps
CPU time 1.02 seconds
Started Aug 05 05:33:01 PM PDT 24
Finished Aug 05 05:33:02 PM PDT 24
Peak memory 207352 kb
Host smart-5920929c-974b-471b-b853-422222caed3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21232
06889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.2123206889
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3317136984
Short name T1389
Test name
Test status
Simulation time 164270921 ps
CPU time 0.83 seconds
Started Aug 05 05:33:02 PM PDT 24
Finished Aug 05 05:33:03 PM PDT 24
Peak memory 207392 kb
Host smart-bed6f90c-73d2-4cfc-bbc9-4ec9a8cf8c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33171
36984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3317136984
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2598994985
Short name T1482
Test name
Test status
Simulation time 37743036 ps
CPU time 0.72 seconds
Started Aug 05 05:33:03 PM PDT 24
Finished Aug 05 05:33:04 PM PDT 24
Peak memory 207316 kb
Host smart-f446fded-bb26-43fa-8136-0f0d2b3619ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25989
94985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2598994985
Directory /workspace/1.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/1.usbdev_pkt_received.4242398182
Short name T790
Test name
Test status
Simulation time 182675489 ps
CPU time 0.87 seconds
Started Aug 05 05:33:04 PM PDT 24
Finished Aug 05 05:33:05 PM PDT 24
Peak memory 207348 kb
Host smart-7fb4dea3-cde8-4931-9b1b-6468d9f5b9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42423
98182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.4242398182
Directory /workspace/1.usbdev_pkt_received/latest


Test location /workspace/coverage/default/1.usbdev_pkt_sent.3787081350
Short name T1892
Test name
Test status
Simulation time 213386390 ps
CPU time 1.09 seconds
Started Aug 05 05:33:09 PM PDT 24
Finished Aug 05 05:33:11 PM PDT 24
Peak memory 207268 kb
Host smart-93b6b9a2-4d5e-40b3-900e-715ed2c25453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37870
81350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3787081350
Directory /workspace/1.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1114786794
Short name T1297
Test name
Test status
Simulation time 6951582158 ps
CPU time 104 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:34:55 PM PDT 24
Peak memory 218920 kb
Host smart-da5fb732-0f96-4ce0-ad5e-ddf09fed4528
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114786794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1114786794
Directory /workspace/1.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.88451759
Short name T1513
Test name
Test status
Simulation time 10370478926 ps
CPU time 69.49 seconds
Started Aug 05 05:33:12 PM PDT 24
Finished Aug 05 05:34:21 PM PDT 24
Peak memory 223956 kb
Host smart-96f64fcf-ed54-45d7-8a63-524968434fff
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=88451759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.88451759
Directory /workspace/1.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/1.usbdev_rand_suspends.2143115838
Short name T2034
Test name
Test status
Simulation time 5642130062 ps
CPU time 64.02 seconds
Started Aug 05 05:33:09 PM PDT 24
Finished Aug 05 05:34:13 PM PDT 24
Peak memory 215820 kb
Host smart-f38af8f6-1bef-4ab6-aedb-fcff8b72a79e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143115838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.2143115838
Directory /workspace/1.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.4061742118
Short name T491
Test name
Test status
Simulation time 227139141 ps
CPU time 1.02 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:12 PM PDT 24
Peak memory 207352 kb
Host smart-242074a5-9033-4fb1-88b8-fb259774a23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40617
42118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.4061742118
Directory /workspace/1.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2894925127
Short name T2883
Test name
Test status
Simulation time 182292609 ps
CPU time 0.87 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:12 PM PDT 24
Peak memory 207396 kb
Host smart-9b8333a6-bf23-4605-b826-5c4f042fb513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28949
25127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2894925127
Directory /workspace/1.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/1.usbdev_resume_link_active.706342675
Short name T614
Test name
Test status
Simulation time 20183230798 ps
CPU time 31.11 seconds
Started Aug 05 05:33:13 PM PDT 24
Finished Aug 05 05:33:44 PM PDT 24
Peak memory 207396 kb
Host smart-3529ae29-03db-4d27-a785-7f041dd9b2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70634
2675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.706342675
Directory /workspace/1.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1240700219
Short name T2854
Test name
Test status
Simulation time 143857646 ps
CPU time 0.81 seconds
Started Aug 05 05:33:13 PM PDT 24
Finished Aug 05 05:33:14 PM PDT 24
Peak memory 207360 kb
Host smart-2253976d-47ee-4a04-8f9e-cf413b23ae5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12407
00219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1240700219
Directory /workspace/1.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/1.usbdev_rx_full.929455172
Short name T61
Test name
Test status
Simulation time 255794170 ps
CPU time 1.04 seconds
Started Aug 05 05:33:13 PM PDT 24
Finished Aug 05 05:33:14 PM PDT 24
Peak memory 207312 kb
Host smart-816fb686-c849-45d9-8f4c-b84ba45d7ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92945
5172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.929455172
Directory /workspace/1.usbdev_rx_full/latest


Test location /workspace/coverage/default/1.usbdev_rx_pid_err.448791157
Short name T86
Test name
Test status
Simulation time 203566064 ps
CPU time 0.96 seconds
Started Aug 05 05:33:12 PM PDT 24
Finished Aug 05 05:33:13 PM PDT 24
Peak memory 207364 kb
Host smart-1e874e1b-6d66-4bcf-b7fd-ea572c79347f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44879
1157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.448791157
Directory /workspace/1.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/1.usbdev_setup_priority.792475617
Short name T59
Test name
Test status
Simulation time 469310547 ps
CPU time 1.79 seconds
Started Aug 05 05:33:12 PM PDT 24
Finished Aug 05 05:33:13 PM PDT 24
Peak memory 207368 kb
Host smart-182d44a1-8859-431a-9004-0b4d3a01cc43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79247
5617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.792475617
Directory /workspace/1.usbdev_setup_priority/latest


Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.3522333170
Short name T1673
Test name
Test status
Simulation time 218661650 ps
CPU time 0.99 seconds
Started Aug 05 05:33:15 PM PDT 24
Finished Aug 05 05:33:16 PM PDT 24
Peak memory 207400 kb
Host smart-26abb1ee-6226-4ec9-9833-74ed85572459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35223
33170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3522333170
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/1.usbdev_setup_stage.214227074
Short name T2452
Test name
Test status
Simulation time 175888323 ps
CPU time 0.88 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:11 PM PDT 24
Peak memory 207308 kb
Host smart-8f4f7a30-5dc1-47b0-92d2-0f9bc93e86b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21422
7074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.214227074
Directory /workspace/1.usbdev_setup_stage/latest


Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3608327865
Short name T2649
Test name
Test status
Simulation time 182664435 ps
CPU time 0.93 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:12 PM PDT 24
Peak memory 207316 kb
Host smart-755db9fd-be03-4df6-97b7-55c5c1467ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36083
27865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3608327865
Directory /workspace/1.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/1.usbdev_smoke.1806605861
Short name T1400
Test name
Test status
Simulation time 199295791 ps
CPU time 0.96 seconds
Started Aug 05 05:33:12 PM PDT 24
Finished Aug 05 05:33:13 PM PDT 24
Peak memory 207396 kb
Host smart-1b1d74fb-cb6f-42d4-9a55-2cc21523fd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18066
05861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1806605861
Directory /workspace/1.usbdev_smoke/latest


Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.1447807886
Short name T2001
Test name
Test status
Simulation time 2437058764 ps
CPU time 24.08 seconds
Started Aug 05 05:33:09 PM PDT 24
Finished Aug 05 05:33:33 PM PDT 24
Peak memory 217504 kb
Host smart-7b95ef02-cd8b-40e0-bed1-3ac0f80fa492
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1447807886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.1447807886
Directory /workspace/1.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.743591808
Short name T1253
Test name
Test status
Simulation time 185573243 ps
CPU time 0.92 seconds
Started Aug 05 05:33:10 PM PDT 24
Finished Aug 05 05:33:11 PM PDT 24
Peak memory 207324 kb
Host smart-6d967681-6b95-46d8-b62c-37b3185cce37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74359
1808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.743591808
Directory /workspace/1.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/1.usbdev_stall_trans.1307289704
Short name T1178
Test name
Test status
Simulation time 156005254 ps
CPU time 0.9 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:12 PM PDT 24
Peak memory 207468 kb
Host smart-6212da9a-aafb-48e9-86cc-65fead519218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13072
89704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1307289704
Directory /workspace/1.usbdev_stall_trans/latest


Test location /workspace/coverage/default/1.usbdev_stream_len_max.1872651600
Short name T3110
Test name
Test status
Simulation time 725387948 ps
CPU time 1.98 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:13 PM PDT 24
Peak memory 207364 kb
Host smart-06a9daec-aa14-4ffa-8abc-f4062a114cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18726
51600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.1872651600
Directory /workspace/1.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/1.usbdev_streaming_out.334586328
Short name T1014
Test name
Test status
Simulation time 4142480306 ps
CPU time 47.44 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:59 PM PDT 24
Peak memory 217440 kb
Host smart-603f756d-ce3d-47dd-b2d0-3114ef9769a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33458
6328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.334586328
Directory /workspace/1.usbdev_streaming_out/latest


Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.4043026555
Short name T2491
Test name
Test status
Simulation time 492972570 ps
CPU time 8.39 seconds
Started Aug 05 05:33:00 PM PDT 24
Finished Aug 05 05:33:08 PM PDT 24
Peak memory 207616 kb
Host smart-8c1ceeab-e9e6-44fb-a591-b6c15f27a058
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043026555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.4043026555
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/10.usbdev_alert_test.2379987111
Short name T2037
Test name
Test status
Simulation time 50502824 ps
CPU time 0.69 seconds
Started Aug 05 05:35:01 PM PDT 24
Finished Aug 05 05:35:02 PM PDT 24
Peak memory 207460 kb
Host smart-812a0ce4-6935-4ccf-8694-f938f8b0aa5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2379987111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.2379987111
Directory /workspace/10.usbdev_alert_test/latest


Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.976022084
Short name T2538
Test name
Test status
Simulation time 13779716601 ps
CPU time 15.32 seconds
Started Aug 05 05:34:51 PM PDT 24
Finished Aug 05 05:35:07 PM PDT 24
Peak memory 215884 kb
Host smart-f947db87-e030-4e50-852f-a512b30ea51a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=976022084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.976022084
Directory /workspace/10.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.286664126
Short name T1295
Test name
Test status
Simulation time 28761917231 ps
CPU time 31.29 seconds
Started Aug 05 05:34:56 PM PDT 24
Finished Aug 05 05:35:28 PM PDT 24
Peak memory 207616 kb
Host smart-28e0cae0-2022-437d-88d1-f0ad4e52e69c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286664126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_ao
n_wake_resume.286664126
Directory /workspace/10.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/10.usbdev_av_buffer.2213816205
Short name T1911
Test name
Test status
Simulation time 154851507 ps
CPU time 0.84 seconds
Started Aug 05 05:34:52 PM PDT 24
Finished Aug 05 05:34:53 PM PDT 24
Peak memory 207288 kb
Host smart-6127cb0e-ef4f-4554-99a0-6ea2acf66e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22138
16205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2213816205
Directory /workspace/10.usbdev_av_buffer/latest


Test location /workspace/coverage/default/10.usbdev_bitstuff_err.473277190
Short name T1681
Test name
Test status
Simulation time 144595022 ps
CPU time 0.88 seconds
Started Aug 05 05:34:52 PM PDT 24
Finished Aug 05 05:34:53 PM PDT 24
Peak memory 207344 kb
Host smart-6c9d16bc-ae1a-4a4a-80a8-718c37a324a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47327
7190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.473277190
Directory /workspace/10.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.2040734462
Short name T568
Test name
Test status
Simulation time 388760905 ps
CPU time 1.34 seconds
Started Aug 05 05:34:52 PM PDT 24
Finished Aug 05 05:34:54 PM PDT 24
Peak memory 207376 kb
Host smart-3a1441cd-2375-49cb-8737-fb05118cedd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20407
34462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.2040734462
Directory /workspace/10.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2545759556
Short name T2901
Test name
Test status
Simulation time 374595231 ps
CPU time 1.21 seconds
Started Aug 05 05:34:56 PM PDT 24
Finished Aug 05 05:34:57 PM PDT 24
Peak memory 207356 kb
Host smart-29e3281e-b35b-40ed-ac68-79f2c3e95b0b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2545759556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2545759556
Directory /workspace/10.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/10.usbdev_device_address.1154778323
Short name T1028
Test name
Test status
Simulation time 33565369520 ps
CPU time 57.38 seconds
Started Aug 05 05:34:54 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207720 kb
Host smart-d9dab490-b738-46fb-88a1-c8407af4e981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11547
78323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1154778323
Directory /workspace/10.usbdev_device_address/latest


Test location /workspace/coverage/default/10.usbdev_device_timeout.4091949998
Short name T1248
Test name
Test status
Simulation time 2536800369 ps
CPU time 18.04 seconds
Started Aug 05 05:34:57 PM PDT 24
Finished Aug 05 05:35:16 PM PDT 24
Peak memory 207600 kb
Host smart-f8a52c22-5d6a-4a14-a06c-44f254afc5f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091949998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.4091949998
Directory /workspace/10.usbdev_device_timeout/latest


Test location /workspace/coverage/default/10.usbdev_disable_endpoint.3106424951
Short name T2476
Test name
Test status
Simulation time 848492016 ps
CPU time 2.28 seconds
Started Aug 05 05:34:53 PM PDT 24
Finished Aug 05 05:34:56 PM PDT 24
Peak memory 207352 kb
Host smart-0e788b58-f4f4-4c1e-b7e3-b4461ca7897d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31064
24951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3106424951
Directory /workspace/10.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/10.usbdev_disconnected.3193517415
Short name T1461
Test name
Test status
Simulation time 144834588 ps
CPU time 0.88 seconds
Started Aug 05 05:34:58 PM PDT 24
Finished Aug 05 05:34:59 PM PDT 24
Peak memory 207236 kb
Host smart-730e2f74-e179-4f4d-ac5d-e8b9f7a702b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31935
17415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3193517415
Directory /workspace/10.usbdev_disconnected/latest


Test location /workspace/coverage/default/10.usbdev_enable.1326042810
Short name T1074
Test name
Test status
Simulation time 55819894 ps
CPU time 0.7 seconds
Started Aug 05 05:34:52 PM PDT 24
Finished Aug 05 05:34:53 PM PDT 24
Peak memory 207316 kb
Host smart-45f034df-0cbd-4781-855b-b81878b215fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13260
42810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1326042810
Directory /workspace/10.usbdev_enable/latest


Test location /workspace/coverage/default/10.usbdev_endpoint_access.2020251177
Short name T648
Test name
Test status
Simulation time 888202112 ps
CPU time 2.56 seconds
Started Aug 05 05:34:56 PM PDT 24
Finished Aug 05 05:34:59 PM PDT 24
Peak memory 207532 kb
Host smart-dd5a23af-8595-422e-9057-55adf8f66df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20202
51177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2020251177
Directory /workspace/10.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/10.usbdev_fifo_rst.70723915
Short name T1446
Test name
Test status
Simulation time 164037296 ps
CPU time 1.72 seconds
Started Aug 05 05:34:53 PM PDT 24
Finished Aug 05 05:34:55 PM PDT 24
Peak memory 207468 kb
Host smart-ae7a4220-133c-4ac1-97a6-b199ef72bff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70723
915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.70723915
Directory /workspace/10.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/10.usbdev_in_iso.2799068159
Short name T1132
Test name
Test status
Simulation time 226862408 ps
CPU time 1.19 seconds
Started Aug 05 05:34:53 PM PDT 24
Finished Aug 05 05:34:54 PM PDT 24
Peak memory 207504 kb
Host smart-85846242-8f2c-454f-820c-8a5d600aff3e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2799068159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2799068159
Directory /workspace/10.usbdev_in_iso/latest


Test location /workspace/coverage/default/10.usbdev_in_stall.1858663177
Short name T906
Test name
Test status
Simulation time 165712182 ps
CPU time 0.82 seconds
Started Aug 05 05:34:57 PM PDT 24
Finished Aug 05 05:34:58 PM PDT 24
Peak memory 207256 kb
Host smart-eb5bb0ed-d4c7-4193-b4ca-11cae7cee6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18586
63177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1858663177
Directory /workspace/10.usbdev_in_stall/latest


Test location /workspace/coverage/default/10.usbdev_in_trans.3495589809
Short name T2879
Test name
Test status
Simulation time 264191376 ps
CPU time 1.07 seconds
Started Aug 05 05:34:55 PM PDT 24
Finished Aug 05 05:34:56 PM PDT 24
Peak memory 207324 kb
Host smart-4eb1afca-6002-4482-81ba-dd790e328567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34955
89809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3495589809
Directory /workspace/10.usbdev_in_trans/latest


Test location /workspace/coverage/default/10.usbdev_invalid_sync.2323848695
Short name T1959
Test name
Test status
Simulation time 4331304977 ps
CPU time 122.18 seconds
Started Aug 05 05:34:52 PM PDT 24
Finished Aug 05 05:36:54 PM PDT 24
Peak memory 218160 kb
Host smart-97f86f53-e95d-49f0-8905-4e4bc5c4cbea
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2323848695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.2323848695
Directory /workspace/10.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/10.usbdev_iso_retraction.3028544127
Short name T649
Test name
Test status
Simulation time 4724723539 ps
CPU time 58.87 seconds
Started Aug 05 05:34:53 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207512 kb
Host smart-e965861e-0d90-4af9-8f83-a8e9e6c26958
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3028544127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.3028544127
Directory /workspace/10.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/10.usbdev_link_in_err.3418487745
Short name T1879
Test name
Test status
Simulation time 182511771 ps
CPU time 0.91 seconds
Started Aug 05 05:34:55 PM PDT 24
Finished Aug 05 05:34:56 PM PDT 24
Peak memory 207348 kb
Host smart-edc41f5e-23b8-4b68-8b9a-25c355698f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34184
87745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3418487745
Directory /workspace/10.usbdev_link_in_err/latest


Test location /workspace/coverage/default/10.usbdev_link_resume.2219386298
Short name T789
Test name
Test status
Simulation time 6668989919 ps
CPU time 11.45 seconds
Started Aug 05 05:34:53 PM PDT 24
Finished Aug 05 05:35:05 PM PDT 24
Peak memory 215820 kb
Host smart-9128b81d-bbba-4c30-b6a7-1ec9d65a3f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22193
86298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2219386298
Directory /workspace/10.usbdev_link_resume/latest


Test location /workspace/coverage/default/10.usbdev_link_suspend.1572746072
Short name T1594
Test name
Test status
Simulation time 5076382169 ps
CPU time 6.46 seconds
Started Aug 05 05:34:53 PM PDT 24
Finished Aug 05 05:35:00 PM PDT 24
Peak memory 215744 kb
Host smart-1324dbce-8521-43e5-a99f-acca43fb4f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15727
46072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1572746072
Directory /workspace/10.usbdev_link_suspend/latest


Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.1590165229
Short name T2816
Test name
Test status
Simulation time 4554748515 ps
CPU time 135.24 seconds
Started Aug 05 05:34:58 PM PDT 24
Finished Aug 05 05:37:14 PM PDT 24
Peak memory 218352 kb
Host smart-7b89f72e-12d0-4d52-b8ef-d223d4cdb27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15901
65229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.1590165229
Directory /workspace/10.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.4039966201
Short name T710
Test name
Test status
Simulation time 2065898229 ps
CPU time 56.78 seconds
Started Aug 05 05:34:51 PM PDT 24
Finished Aug 05 05:35:48 PM PDT 24
Peak memory 215736 kb
Host smart-1a239842-b95f-46f0-9f64-e53efc4496f4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4039966201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.4039966201
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1261095168
Short name T1401
Test name
Test status
Simulation time 240364980 ps
CPU time 1.11 seconds
Started Aug 05 05:35:04 PM PDT 24
Finished Aug 05 05:35:05 PM PDT 24
Peak memory 207272 kb
Host smart-af7027dd-3fc0-4663-87c5-6fbb44dcfa89
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1261095168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1261095168
Directory /workspace/10.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.4246512822
Short name T2639
Test name
Test status
Simulation time 191473840 ps
CPU time 0.95 seconds
Started Aug 05 05:35:00 PM PDT 24
Finished Aug 05 05:35:01 PM PDT 24
Peak memory 207376 kb
Host smart-bf33fee9-8a63-4f45-8c5f-ec79919dfee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42465
12822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.4246512822
Directory /workspace/10.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.1003852578
Short name T1964
Test name
Test status
Simulation time 2110471679 ps
CPU time 16.38 seconds
Started Aug 05 05:35:01 PM PDT 24
Finished Aug 05 05:35:18 PM PDT 24
Peak memory 207468 kb
Host smart-da03aeb7-b554-4818-8485-596d94a58670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10038
52578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.1003852578
Directory /workspace/10.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.542110020
Short name T1489
Test name
Test status
Simulation time 2590833725 ps
CPU time 76.27 seconds
Started Aug 05 05:35:03 PM PDT 24
Finished Aug 05 05:36:20 PM PDT 24
Peak memory 224024 kb
Host smart-4ddb50aa-1b5d-44f5-b1ed-97fe29de065e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=542110020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.542110020
Directory /workspace/10.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.2678970991
Short name T503
Test name
Test status
Simulation time 2016459568 ps
CPU time 16.6 seconds
Started Aug 05 05:35:02 PM PDT 24
Finished Aug 05 05:35:19 PM PDT 24
Peak memory 207552 kb
Host smart-164e299d-7412-485d-91eb-16aa9d7cc986
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2678970991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.2678970991
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.2364458408
Short name T2852
Test name
Test status
Simulation time 178056857 ps
CPU time 0.92 seconds
Started Aug 05 05:35:03 PM PDT 24
Finished Aug 05 05:35:04 PM PDT 24
Peak memory 207368 kb
Host smart-af19ec56-a7cf-460f-a381-38ae079f16da
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2364458408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.2364458408
Directory /workspace/10.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.4009880996
Short name T557
Test name
Test status
Simulation time 149817056 ps
CPU time 0.83 seconds
Started Aug 05 05:35:06 PM PDT 24
Finished Aug 05 05:35:07 PM PDT 24
Peak memory 207400 kb
Host smart-4518f340-0b01-4509-8922-707a466658ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40098
80996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.4009880996
Directory /workspace/10.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/10.usbdev_out_iso.4198956730
Short name T119
Test name
Test status
Simulation time 179589763 ps
CPU time 0.9 seconds
Started Aug 05 05:35:00 PM PDT 24
Finished Aug 05 05:35:01 PM PDT 24
Peak memory 207308 kb
Host smart-30abbeaa-ab35-4677-9a30-919c161d65a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41989
56730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.4198956730
Directory /workspace/10.usbdev_out_iso/latest


Test location /workspace/coverage/default/10.usbdev_out_stall.3517054675
Short name T1491
Test name
Test status
Simulation time 196442939 ps
CPU time 0.88 seconds
Started Aug 05 05:35:06 PM PDT 24
Finished Aug 05 05:35:07 PM PDT 24
Peak memory 207392 kb
Host smart-43067628-daec-4c7c-9dc1-20b7ee093d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35170
54675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3517054675
Directory /workspace/10.usbdev_out_stall/latest


Test location /workspace/coverage/default/10.usbdev_out_trans_nak.632625423
Short name T2488
Test name
Test status
Simulation time 169434110 ps
CPU time 0.93 seconds
Started Aug 05 05:35:01 PM PDT 24
Finished Aug 05 05:35:02 PM PDT 24
Peak memory 207240 kb
Host smart-7ec534ff-bcf9-494e-bfd1-7ee8fe49071e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63262
5423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.632625423
Directory /workspace/10.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/10.usbdev_pending_in_trans.798455515
Short name T2406
Test name
Test status
Simulation time 167240115 ps
CPU time 0.93 seconds
Started Aug 05 05:35:04 PM PDT 24
Finished Aug 05 05:35:05 PM PDT 24
Peak memory 207400 kb
Host smart-70f17d6b-2e46-4e25-97e0-c7a4aa81a1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79845
5515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.798455515
Directory /workspace/10.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.791448368
Short name T2523
Test name
Test status
Simulation time 227640544 ps
CPU time 1 seconds
Started Aug 05 05:35:06 PM PDT 24
Finished Aug 05 05:35:07 PM PDT 24
Peak memory 207372 kb
Host smart-348ce514-63e4-4eb0-9b7f-8bb49c87d6f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=791448368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.791448368
Directory /workspace/10.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1208512088
Short name T1539
Test name
Test status
Simulation time 179733891 ps
CPU time 0.94 seconds
Started Aug 05 05:35:04 PM PDT 24
Finished Aug 05 05:35:05 PM PDT 24
Peak memory 207264 kb
Host smart-5167ccdb-53c1-42c1-aeaa-5762a84926c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12085
12088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1208512088
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/10.usbdev_pkt_buffer.447917507
Short name T3102
Test name
Test status
Simulation time 7012095068 ps
CPU time 18.57 seconds
Started Aug 05 05:35:00 PM PDT 24
Finished Aug 05 05:35:19 PM PDT 24
Peak memory 215840 kb
Host smart-f671dacb-18fa-43ce-9cd2-553f04f1bb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44791
7507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.447917507
Directory /workspace/10.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/10.usbdev_pkt_received.845099057
Short name T2499
Test name
Test status
Simulation time 184475062 ps
CPU time 0.91 seconds
Started Aug 05 05:35:01 PM PDT 24
Finished Aug 05 05:35:02 PM PDT 24
Peak memory 207388 kb
Host smart-e4efed85-fde7-4229-b6ab-e88efd0ee946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84509
9057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.845099057
Directory /workspace/10.usbdev_pkt_received/latest


Test location /workspace/coverage/default/10.usbdev_pkt_sent.2525911470
Short name T2789
Test name
Test status
Simulation time 242389751 ps
CPU time 1.04 seconds
Started Aug 05 05:35:01 PM PDT 24
Finished Aug 05 05:35:02 PM PDT 24
Peak memory 207328 kb
Host smart-3012cf69-6522-41b0-a979-7edad8b380ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25259
11470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2525911470
Directory /workspace/10.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.454287813
Short name T2872
Test name
Test status
Simulation time 206188725 ps
CPU time 1.01 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:35:08 PM PDT 24
Peak memory 207320 kb
Host smart-05cf7615-6dbb-4f3c-aa75-fa0099e426b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45428
7813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.454287813
Directory /workspace/10.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2271798672
Short name T1515
Test name
Test status
Simulation time 202597798 ps
CPU time 0.96 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:35:08 PM PDT 24
Peak memory 207320 kb
Host smart-88037675-cc62-4b25-a3f1-d17a02b4ecd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22717
98672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2271798672
Directory /workspace/10.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/10.usbdev_resume_link_active.3144127152
Short name T2998
Test name
Test status
Simulation time 20165705714 ps
CPU time 26.41 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:35:34 PM PDT 24
Peak memory 207404 kb
Host smart-c6cc7b5e-82ba-4894-a5f4-07e2bacff2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31441
27152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.3144127152
Directory /workspace/10.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/10.usbdev_setup_stage.2730998359
Short name T1363
Test name
Test status
Simulation time 192542789 ps
CPU time 0.95 seconds
Started Aug 05 05:35:03 PM PDT 24
Finished Aug 05 05:35:04 PM PDT 24
Peak memory 207336 kb
Host smart-8f55932f-4231-46ca-88f9-8b4a2e93825f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27309
98359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2730998359
Directory /workspace/10.usbdev_setup_stage/latest


Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3182565251
Short name T2171
Test name
Test status
Simulation time 164035346 ps
CPU time 1.01 seconds
Started Aug 05 05:35:02 PM PDT 24
Finished Aug 05 05:35:03 PM PDT 24
Peak memory 207380 kb
Host smart-c03657cb-75e3-4b50-ba78-cf94c24b08a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31825
65251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3182565251
Directory /workspace/10.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/10.usbdev_smoke.1923469754
Short name T2252
Test name
Test status
Simulation time 233612977 ps
CPU time 1.13 seconds
Started Aug 05 05:35:04 PM PDT 24
Finished Aug 05 05:35:06 PM PDT 24
Peak memory 207272 kb
Host smart-dc3203eb-7c71-42cf-89e9-51e9c0bbe66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19234
69754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1923469754
Directory /workspace/10.usbdev_smoke/latest


Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2308072804
Short name T1578
Test name
Test status
Simulation time 3208399323 ps
CPU time 26.27 seconds
Started Aug 05 05:35:06 PM PDT 24
Finished Aug 05 05:35:32 PM PDT 24
Peak memory 223940 kb
Host smart-3b055d4e-f4fc-4bbf-b1fa-ec12ab99c632
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2308072804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2308072804
Directory /workspace/10.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1022543751
Short name T2000
Test name
Test status
Simulation time 202460805 ps
CPU time 0.95 seconds
Started Aug 05 05:35:02 PM PDT 24
Finished Aug 05 05:35:04 PM PDT 24
Peak memory 207352 kb
Host smart-fe900346-e3bc-47fd-86ef-b40284219dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10225
43751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1022543751
Directory /workspace/10.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/10.usbdev_stall_trans.1180036293
Short name T1747
Test name
Test status
Simulation time 168750798 ps
CPU time 0.88 seconds
Started Aug 05 05:35:04 PM PDT 24
Finished Aug 05 05:35:05 PM PDT 24
Peak memory 207224 kb
Host smart-59f6a9a7-e254-4050-a723-a84920aeae0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11800
36293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1180036293
Directory /workspace/10.usbdev_stall_trans/latest


Test location /workspace/coverage/default/10.usbdev_stream_len_max.2291668129
Short name T679
Test name
Test status
Simulation time 503756543 ps
CPU time 1.58 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:35:08 PM PDT 24
Peak memory 207288 kb
Host smart-be07c36b-8063-4e9c-bb91-fad5a2288733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22916
68129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.2291668129
Directory /workspace/10.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/10.usbdev_streaming_out.2725450810
Short name T524
Test name
Test status
Simulation time 2995733735 ps
CPU time 22.89 seconds
Started Aug 05 05:35:02 PM PDT 24
Finished Aug 05 05:35:25 PM PDT 24
Peak memory 207664 kb
Host smart-f7391885-443b-49d2-bce7-a11b665eb301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27254
50810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2725450810
Directory /workspace/10.usbdev_streaming_out/latest


Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.638532084
Short name T1168
Test name
Test status
Simulation time 555867763 ps
CPU time 11.39 seconds
Started Aug 05 05:34:57 PM PDT 24
Finished Aug 05 05:35:08 PM PDT 24
Peak memory 207588 kb
Host smart-7489f5e3-bc6a-40f3-aabd-821a4bee0569
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638532084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_host
_handshake.638532084
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/102.usbdev_endpoint_types.1671701644
Short name T438
Test name
Test status
Simulation time 717641794 ps
CPU time 1.65 seconds
Started Aug 05 05:40:47 PM PDT 24
Finished Aug 05 05:40:48 PM PDT 24
Peak memory 207300 kb
Host smart-fdd463fd-a600-4be2-affe-d0a9c7b7bbf0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1671701644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.1671701644
Directory /workspace/102.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/105.usbdev_endpoint_types.2073136335
Short name T92
Test name
Test status
Simulation time 346875274 ps
CPU time 1.15 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207212 kb
Host smart-a5aabaac-77e6-40cd-afab-dbc9aeca192b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2073136335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.2073136335
Directory /workspace/105.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/106.usbdev_endpoint_types.1298932418
Short name T449
Test name
Test status
Simulation time 289168520 ps
CPU time 1.16 seconds
Started Aug 05 05:40:41 PM PDT 24
Finished Aug 05 05:40:42 PM PDT 24
Peak memory 207368 kb
Host smart-3a06f0f1-864c-4d6d-b7e8-7b4e68c3b465
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1298932418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.1298932418
Directory /workspace/106.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/107.usbdev_endpoint_types.2191905498
Short name T362
Test name
Test status
Simulation time 603596357 ps
CPU time 1.58 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:34 PM PDT 24
Peak memory 207296 kb
Host smart-59909ae4-73d7-4f02-b2c3-99ed462b6097
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2191905498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.2191905498
Directory /workspace/107.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/109.usbdev_endpoint_types.4194073142
Short name T378
Test name
Test status
Simulation time 277198271 ps
CPU time 1.07 seconds
Started Aug 05 05:41:04 PM PDT 24
Finished Aug 05 05:41:05 PM PDT 24
Peak memory 207368 kb
Host smart-209785b8-d460-41c7-834f-66a4b1947a1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4194073142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.4194073142
Directory /workspace/109.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/11.usbdev_alert_test.469741889
Short name T2818
Test name
Test status
Simulation time 55936302 ps
CPU time 0.69 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:23 PM PDT 24
Peak memory 207464 kb
Host smart-4f928380-1305-4a34-842f-14fede059ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=469741889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.469741889
Directory /workspace/11.usbdev_alert_test/latest


Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.2095134070
Short name T1566
Test name
Test status
Simulation time 4104878963 ps
CPU time 5.53 seconds
Started Aug 05 05:35:00 PM PDT 24
Finished Aug 05 05:35:06 PM PDT 24
Peak memory 215812 kb
Host smart-85ef72ef-31f3-4d7f-90a5-062133245394
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095134070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.2095134070
Directory /workspace/11.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.4022101812
Short name T2661
Test name
Test status
Simulation time 19389134648 ps
CPU time 24.65 seconds
Started Aug 05 05:35:04 PM PDT 24
Finished Aug 05 05:35:28 PM PDT 24
Peak memory 207672 kb
Host smart-6171f67d-449f-4092-90d5-f8d2ab9d7b50
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022101812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.4022101812
Directory /workspace/11.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.4026106735
Short name T2501
Test name
Test status
Simulation time 25520125490 ps
CPU time 30.21 seconds
Started Aug 05 05:35:03 PM PDT 24
Finished Aug 05 05:35:34 PM PDT 24
Peak memory 215800 kb
Host smart-d0a4d15b-c91d-49a6-9e62-8572ea8084bf
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026106735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.4026106735
Directory /workspace/11.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/11.usbdev_av_buffer.2157765259
Short name T2557
Test name
Test status
Simulation time 150180083 ps
CPU time 0.92 seconds
Started Aug 05 05:35:00 PM PDT 24
Finished Aug 05 05:35:01 PM PDT 24
Peak memory 207376 kb
Host smart-e7ab6f6e-a196-4645-9261-7aa07a4c1348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21577
65259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2157765259
Directory /workspace/11.usbdev_av_buffer/latest


Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1875858476
Short name T2477
Test name
Test status
Simulation time 241127303 ps
CPU time 1.01 seconds
Started Aug 05 05:35:01 PM PDT 24
Finished Aug 05 05:35:03 PM PDT 24
Peak memory 207232 kb
Host smart-24b08c92-f758-4034-b97e-d28513ec58ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18758
58476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1875858476
Directory /workspace/11.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.1742503675
Short name T2550
Test name
Test status
Simulation time 421280329 ps
CPU time 1.51 seconds
Started Aug 05 05:35:02 PM PDT 24
Finished Aug 05 05:35:03 PM PDT 24
Peak memory 207612 kb
Host smart-9218c554-1ec0-4777-99d0-41ee59da7eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17425
03675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.1742503675
Directory /workspace/11.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.896329166
Short name T505
Test name
Test status
Simulation time 736843310 ps
CPU time 1.98 seconds
Started Aug 05 05:35:01 PM PDT 24
Finished Aug 05 05:35:04 PM PDT 24
Peak memory 206904 kb
Host smart-f3b2ca37-28af-440c-bc59-908ea0c9376e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=896329166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.896329166
Directory /workspace/11.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/11.usbdev_device_address.2466966330
Short name T1034
Test name
Test status
Simulation time 40746777171 ps
CPU time 68.21 seconds
Started Aug 05 05:35:01 PM PDT 24
Finished Aug 05 05:36:09 PM PDT 24
Peak memory 207696 kb
Host smart-cbd65941-8ec5-4a79-b8d5-83e212ceb28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24669
66330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2466966330
Directory /workspace/11.usbdev_device_address/latest


Test location /workspace/coverage/default/11.usbdev_device_timeout.3885523832
Short name T2335
Test name
Test status
Simulation time 1266660771 ps
CPU time 29.01 seconds
Started Aug 05 05:35:03 PM PDT 24
Finished Aug 05 05:35:32 PM PDT 24
Peak memory 207520 kb
Host smart-04dd90cd-fec5-4833-bbf7-e6ed50dddfc7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885523832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.3885523832
Directory /workspace/11.usbdev_device_timeout/latest


Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2304222841
Short name T424
Test name
Test status
Simulation time 911770778 ps
CPU time 2.35 seconds
Started Aug 05 05:35:02 PM PDT 24
Finished Aug 05 05:35:04 PM PDT 24
Peak memory 206692 kb
Host smart-94cd3540-8bb3-44be-87c8-3db550efad2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23042
22841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2304222841
Directory /workspace/11.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/11.usbdev_disconnected.2645082405
Short name T1536
Test name
Test status
Simulation time 153731973 ps
CPU time 0.86 seconds
Started Aug 05 05:35:06 PM PDT 24
Finished Aug 05 05:35:07 PM PDT 24
Peak memory 207332 kb
Host smart-21c0816b-8a54-42c3-a46b-878f4dea98e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26450
82405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2645082405
Directory /workspace/11.usbdev_disconnected/latest


Test location /workspace/coverage/default/11.usbdev_enable.3659538561
Short name T706
Test name
Test status
Simulation time 49530544 ps
CPU time 0.73 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:35:08 PM PDT 24
Peak memory 207328 kb
Host smart-7509cf45-994f-4dea-998d-847b1d67dc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36595
38561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3659538561
Directory /workspace/11.usbdev_enable/latest


Test location /workspace/coverage/default/11.usbdev_endpoint_access.4157095294
Short name T1985
Test name
Test status
Simulation time 924532162 ps
CPU time 2.55 seconds
Started Aug 05 05:35:10 PM PDT 24
Finished Aug 05 05:35:13 PM PDT 24
Peak memory 207544 kb
Host smart-a41cf7b9-a38b-46c7-b43a-2f425e3c0ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41570
95294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.4157095294
Directory /workspace/11.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/11.usbdev_in_iso.285767797
Short name T1082
Test name
Test status
Simulation time 182372243 ps
CPU time 1.1 seconds
Started Aug 05 05:35:09 PM PDT 24
Finished Aug 05 05:35:11 PM PDT 24
Peak memory 207548 kb
Host smart-2ad5cdce-b81a-4a71-8542-0e5392d1f183
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=285767797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.285767797
Directory /workspace/11.usbdev_in_iso/latest


Test location /workspace/coverage/default/11.usbdev_in_stall.4016674670
Short name T2327
Test name
Test status
Simulation time 155955987 ps
CPU time 0.83 seconds
Started Aug 05 05:35:09 PM PDT 24
Finished Aug 05 05:35:10 PM PDT 24
Peak memory 207284 kb
Host smart-3f03640d-960c-4cea-95f2-863a34dc8a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40166
74670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.4016674670
Directory /workspace/11.usbdev_in_stall/latest


Test location /workspace/coverage/default/11.usbdev_in_trans.560375843
Short name T1035
Test name
Test status
Simulation time 208225979 ps
CPU time 1.02 seconds
Started Aug 05 05:35:05 PM PDT 24
Finished Aug 05 05:35:07 PM PDT 24
Peak memory 207396 kb
Host smart-48d08cc3-d8e5-41b6-b83e-4330c5e5fd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56037
5843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.560375843
Directory /workspace/11.usbdev_in_trans/latest


Test location /workspace/coverage/default/11.usbdev_invalid_sync.4088403583
Short name T4
Test name
Test status
Simulation time 4153650549 ps
CPU time 123.67 seconds
Started Aug 05 05:35:08 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 224060 kb
Host smart-5b3ff136-4813-481d-879a-95f4a0fa9a00
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4088403583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.4088403583
Directory /workspace/11.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/11.usbdev_iso_retraction.1718707907
Short name T2346
Test name
Test status
Simulation time 8327918369 ps
CPU time 53 seconds
Started Aug 05 05:35:11 PM PDT 24
Finished Aug 05 05:36:04 PM PDT 24
Peak memory 207540 kb
Host smart-7f61c1b6-0f49-4203-ba47-3ccbd60a50cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1718707907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.1718707907
Directory /workspace/11.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/11.usbdev_link_in_err.4030004387
Short name T1572
Test name
Test status
Simulation time 231309455 ps
CPU time 1.19 seconds
Started Aug 05 05:35:15 PM PDT 24
Finished Aug 05 05:35:16 PM PDT 24
Peak memory 207224 kb
Host smart-d3139f57-69b5-422b-8d9f-10c0ec65c92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40300
04387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.4030004387
Directory /workspace/11.usbdev_link_in_err/latest


Test location /workspace/coverage/default/11.usbdev_link_resume.2574683905
Short name T1561
Test name
Test status
Simulation time 28358406877 ps
CPU time 43.54 seconds
Started Aug 05 05:35:10 PM PDT 24
Finished Aug 05 05:35:53 PM PDT 24
Peak memory 207764 kb
Host smart-d5803339-5c21-4aec-adef-5bcf1aeb6812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25746
83905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.2574683905
Directory /workspace/11.usbdev_link_resume/latest


Test location /workspace/coverage/default/11.usbdev_link_suspend.1528133400
Short name T2755
Test name
Test status
Simulation time 5571286248 ps
CPU time 7.07 seconds
Started Aug 05 05:35:11 PM PDT 24
Finished Aug 05 05:35:18 PM PDT 24
Peak memory 215872 kb
Host smart-2d25c296-b31e-45e3-87fc-cdf8fe5f0fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15281
33400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1528133400
Directory /workspace/11.usbdev_link_suspend/latest


Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2729414749
Short name T1061
Test name
Test status
Simulation time 4035657252 ps
CPU time 41.5 seconds
Started Aug 05 05:35:08 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 217920 kb
Host smart-8845d6b0-4a02-424a-a6bb-65fa010f9d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27294
14749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2729414749
Directory /workspace/11.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3865269730
Short name T1556
Test name
Test status
Simulation time 1786293523 ps
CPU time 53.13 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:36:00 PM PDT 24
Peak memory 215792 kb
Host smart-230a5768-af42-4fdd-8d98-31be166e6f6f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3865269730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3865269730
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2934088774
Short name T2044
Test name
Test status
Simulation time 309444450 ps
CPU time 1.06 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:35:08 PM PDT 24
Peak memory 207360 kb
Host smart-9998527d-1314-4c15-a615-c0c4a79df60a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2934088774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2934088774
Directory /workspace/11.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.345791686
Short name T31
Test name
Test status
Simulation time 236825873 ps
CPU time 0.95 seconds
Started Aug 05 05:35:09 PM PDT 24
Finished Aug 05 05:35:10 PM PDT 24
Peak memory 207316 kb
Host smart-c903bfbf-e1ef-4a35-bda9-da2bd1c44a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34579
1686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.345791686
Directory /workspace/11.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.42590325
Short name T1188
Test name
Test status
Simulation time 3664013240 ps
CPU time 37.8 seconds
Started Aug 05 05:35:11 PM PDT 24
Finished Aug 05 05:35:49 PM PDT 24
Peak memory 224016 kb
Host smart-0c51c786-05cf-41f5-988b-1a206fb65631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42590
325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.42590325
Directory /workspace/11.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.320023928
Short name T3014
Test name
Test status
Simulation time 3433194503 ps
CPU time 35.83 seconds
Started Aug 05 05:35:11 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 215736 kb
Host smart-a82d2540-b9ed-47de-83e9-b1e6e98bccc5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=320023928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.320023928
Directory /workspace/11.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.32870039
Short name T2591
Test name
Test status
Simulation time 1833397153 ps
CPU time 53.13 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:36:10 PM PDT 24
Peak memory 216992 kb
Host smart-c9d75d0e-5aa9-4356-9afb-b2e30d3db3f0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=32870039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.32870039
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.4293392459
Short name T892
Test name
Test status
Simulation time 157307047 ps
CPU time 0.95 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:35:08 PM PDT 24
Peak memory 207400 kb
Host smart-42f1e110-1f35-4a4d-8193-17fca134e5fc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4293392459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.4293392459
Directory /workspace/11.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1602548110
Short name T2133
Test name
Test status
Simulation time 153717815 ps
CPU time 0.89 seconds
Started Aug 05 05:35:10 PM PDT 24
Finished Aug 05 05:35:11 PM PDT 24
Peak memory 207352 kb
Host smart-52df3a40-f872-4f34-ab88-936fa4e228e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16025
48110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1602548110
Directory /workspace/11.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/11.usbdev_nak_trans.2420380029
Short name T149
Test name
Test status
Simulation time 188893809 ps
CPU time 0.91 seconds
Started Aug 05 05:35:06 PM PDT 24
Finished Aug 05 05:35:07 PM PDT 24
Peak memory 207340 kb
Host smart-123d52fd-77ff-4fae-9156-6b70d15213bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24203
80029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2420380029
Directory /workspace/11.usbdev_nak_trans/latest


Test location /workspace/coverage/default/11.usbdev_out_iso.2526595798
Short name T2757
Test name
Test status
Simulation time 224023017 ps
CPU time 0.89 seconds
Started Aug 05 05:35:09 PM PDT 24
Finished Aug 05 05:35:10 PM PDT 24
Peak memory 207348 kb
Host smart-66775f1f-9702-4576-861f-b71f981b9929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25265
95798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2526595798
Directory /workspace/11.usbdev_out_iso/latest


Test location /workspace/coverage/default/11.usbdev_out_stall.2904658892
Short name T2693
Test name
Test status
Simulation time 182361741 ps
CPU time 0.98 seconds
Started Aug 05 05:35:08 PM PDT 24
Finished Aug 05 05:35:10 PM PDT 24
Peak memory 207392 kb
Host smart-690a4e31-9be6-4cc4-befc-229a8a75ac8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29046
58892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2904658892
Directory /workspace/11.usbdev_out_stall/latest


Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2964499674
Short name T1978
Test name
Test status
Simulation time 199340816 ps
CPU time 0.96 seconds
Started Aug 05 05:35:06 PM PDT 24
Finished Aug 05 05:35:07 PM PDT 24
Peak memory 207320 kb
Host smart-9f67218e-e9f4-45d7-8f0c-269d4262e9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29644
99674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2964499674
Directory /workspace/11.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3245446948
Short name T1921
Test name
Test status
Simulation time 161313160 ps
CPU time 0.86 seconds
Started Aug 05 05:35:09 PM PDT 24
Finished Aug 05 05:35:10 PM PDT 24
Peak memory 207396 kb
Host smart-b987208d-10fd-426e-9b4f-42b0d8e71c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32454
46948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3245446948
Directory /workspace/11.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1396087441
Short name T2043
Test name
Test status
Simulation time 213949953 ps
CPU time 0.99 seconds
Started Aug 05 05:35:09 PM PDT 24
Finished Aug 05 05:35:10 PM PDT 24
Peak memory 207372 kb
Host smart-c4e1a703-33e0-4b7a-a3c0-3831705b11e8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1396087441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1396087441
Directory /workspace/11.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.273885900
Short name T1875
Test name
Test status
Simulation time 199983085 ps
CPU time 0.98 seconds
Started Aug 05 05:35:14 PM PDT 24
Finished Aug 05 05:35:15 PM PDT 24
Peak memory 207196 kb
Host smart-6f6cf77e-58e1-48bf-9b8b-c8820f31e28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27388
5900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.273885900
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1968902714
Short name T2834
Test name
Test status
Simulation time 35531109 ps
CPU time 0.67 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:35:08 PM PDT 24
Peak memory 207216 kb
Host smart-cdf83fa5-c39c-43b8-a4c9-8a8f96d40e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19689
02714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1968902714
Directory /workspace/11.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2354945698
Short name T1100
Test name
Test status
Simulation time 22219058886 ps
CPU time 63.37 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:36:10 PM PDT 24
Peak memory 215804 kb
Host smart-005ea7ed-6061-4df7-b4d0-891791a08a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23549
45698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2354945698
Directory /workspace/11.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/11.usbdev_pkt_received.3230428338
Short name T617
Test name
Test status
Simulation time 194528221 ps
CPU time 0.97 seconds
Started Aug 05 05:35:15 PM PDT 24
Finished Aug 05 05:35:16 PM PDT 24
Peak memory 207224 kb
Host smart-9c69d17b-a3c0-4ce3-8262-015a43c7b9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32304
28338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3230428338
Directory /workspace/11.usbdev_pkt_received/latest


Test location /workspace/coverage/default/11.usbdev_pkt_sent.4039692871
Short name T1118
Test name
Test status
Simulation time 207497456 ps
CPU time 0.96 seconds
Started Aug 05 05:35:10 PM PDT 24
Finished Aug 05 05:35:11 PM PDT 24
Peak memory 207320 kb
Host smart-0449665f-bc19-40d5-9f90-fe7e45eb108e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
92871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.4039692871
Directory /workspace/11.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.3193740195
Short name T707
Test name
Test status
Simulation time 213294577 ps
CPU time 0.99 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:35:08 PM PDT 24
Peak memory 207236 kb
Host smart-ccc850a9-4b4b-42de-8ebf-22b3dcc1d5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31937
40195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.3193740195
Directory /workspace/11.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.140733010
Short name T2623
Test name
Test status
Simulation time 214893469 ps
CPU time 1 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:35:17 PM PDT 24
Peak memory 207228 kb
Host smart-008aeb05-fd9b-4463-a802-a09d06b66df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14073
3010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.140733010
Directory /workspace/11.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/11.usbdev_resume_link_active.468146934
Short name T2516
Test name
Test status
Simulation time 20197740931 ps
CPU time 21.58 seconds
Started Aug 05 05:35:06 PM PDT 24
Finished Aug 05 05:35:28 PM PDT 24
Peak memory 207456 kb
Host smart-ddef5a63-8f8a-48ab-b531-ed64e1177b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46814
6934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.468146934
Directory /workspace/11.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2850004694
Short name T2948
Test name
Test status
Simulation time 163018343 ps
CPU time 0.86 seconds
Started Aug 05 05:35:08 PM PDT 24
Finished Aug 05 05:35:09 PM PDT 24
Peak memory 207272 kb
Host smart-a215505e-b372-4444-a09c-348f072b41b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28500
04694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2850004694
Directory /workspace/11.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/11.usbdev_rx_full.3654910846
Short name T1410
Test name
Test status
Simulation time 348726307 ps
CPU time 1.29 seconds
Started Aug 05 05:35:09 PM PDT 24
Finished Aug 05 05:35:11 PM PDT 24
Peak memory 207324 kb
Host smart-146c44ae-b58e-4f85-a9cd-dc17211480c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36549
10846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.3654910846
Directory /workspace/11.usbdev_rx_full/latest


Test location /workspace/coverage/default/11.usbdev_setup_stage.256876216
Short name T1338
Test name
Test status
Simulation time 176890365 ps
CPU time 0.89 seconds
Started Aug 05 05:35:06 PM PDT 24
Finished Aug 05 05:35:07 PM PDT 24
Peak memory 207208 kb
Host smart-4f081b09-4826-4af5-b394-e17cd08edf1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25687
6216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.256876216
Directory /workspace/11.usbdev_setup_stage/latest


Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.652161223
Short name T1840
Test name
Test status
Simulation time 157616389 ps
CPU time 0.91 seconds
Started Aug 05 05:35:09 PM PDT 24
Finished Aug 05 05:35:10 PM PDT 24
Peak memory 207328 kb
Host smart-6e88e916-ac3b-42d1-8a66-b94fc9eb078a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65216
1223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.652161223
Directory /workspace/11.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/11.usbdev_smoke.1494877236
Short name T1148
Test name
Test status
Simulation time 227373648 ps
CPU time 1.03 seconds
Started Aug 05 05:35:07 PM PDT 24
Finished Aug 05 05:35:08 PM PDT 24
Peak memory 207368 kb
Host smart-c04e139f-4bd3-417e-8236-5db5202f4e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14948
77236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1494877236
Directory /workspace/11.usbdev_smoke/latest


Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.668731080
Short name T1335
Test name
Test status
Simulation time 2050809314 ps
CPU time 62.04 seconds
Started Aug 05 05:35:09 PM PDT 24
Finished Aug 05 05:36:12 PM PDT 24
Peak memory 215748 kb
Host smart-9e52b02a-8db8-4cfb-9c38-fc3a597c804a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=668731080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.668731080
Directory /workspace/11.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.924812106
Short name T1708
Test name
Test status
Simulation time 253686491 ps
CPU time 1.01 seconds
Started Aug 05 05:35:11 PM PDT 24
Finished Aug 05 05:35:12 PM PDT 24
Peak memory 207384 kb
Host smart-4a203cf4-67a7-4789-9433-6f64495a9ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92481
2106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.924812106
Directory /workspace/11.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/11.usbdev_stall_trans.76404862
Short name T3
Test name
Test status
Simulation time 229770949 ps
CPU time 0.94 seconds
Started Aug 05 05:35:09 PM PDT 24
Finished Aug 05 05:35:10 PM PDT 24
Peak memory 207324 kb
Host smart-deb31c47-8335-4a69-9511-f2d7616363f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76404
862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.76404862
Directory /workspace/11.usbdev_stall_trans/latest


Test location /workspace/coverage/default/11.usbdev_stream_len_max.3899591741
Short name T920
Test name
Test status
Simulation time 635759520 ps
CPU time 1.72 seconds
Started Aug 05 05:35:06 PM PDT 24
Finished Aug 05 05:35:08 PM PDT 24
Peak memory 207372 kb
Host smart-f7a39133-5326-4f60-a92e-a916c99127f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38995
91741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.3899591741
Directory /workspace/11.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/11.usbdev_streaming_out.2992276641
Short name T1155
Test name
Test status
Simulation time 3063876951 ps
CPU time 22.92 seconds
Started Aug 05 05:35:08 PM PDT 24
Finished Aug 05 05:35:31 PM PDT 24
Peak memory 215896 kb
Host smart-6dc64265-206d-4343-ace6-06b9d766df73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29922
76641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2992276641
Directory /workspace/11.usbdev_streaming_out/latest


Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.568428298
Short name T1672
Test name
Test status
Simulation time 154024762 ps
CPU time 0.84 seconds
Started Aug 05 05:35:08 PM PDT 24
Finished Aug 05 05:35:09 PM PDT 24
Peak memory 207316 kb
Host smart-15292067-5b8a-484f-bd87-38d08384b722
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568428298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_host
_handshake.568428298
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/110.usbdev_endpoint_types.1307637726
Short name T359
Test name
Test status
Simulation time 510964697 ps
CPU time 1.45 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207324 kb
Host smart-99085e79-1d8c-458b-93ab-f0437a7e39be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1307637726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.1307637726
Directory /workspace/110.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/111.usbdev_endpoint_types.3401360967
Short name T461
Test name
Test status
Simulation time 303578753 ps
CPU time 1.13 seconds
Started Aug 05 05:40:39 PM PDT 24
Finished Aug 05 05:40:40 PM PDT 24
Peak memory 207244 kb
Host smart-1c0f78a4-4858-4e38-8d07-f36ddf642562
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3401360967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.3401360967
Directory /workspace/111.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/113.usbdev_endpoint_types.2431201761
Short name T2882
Test name
Test status
Simulation time 247948356 ps
CPU time 0.97 seconds
Started Aug 05 05:40:36 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207312 kb
Host smart-e508375c-f22c-4c25-9dd0-c2e671f0cc92
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2431201761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.2431201761
Directory /workspace/113.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/114.usbdev_endpoint_types.3449395285
Short name T1426
Test name
Test status
Simulation time 238357364 ps
CPU time 1.01 seconds
Started Aug 05 05:40:37 PM PDT 24
Finished Aug 05 05:40:38 PM PDT 24
Peak memory 207240 kb
Host smart-a73d7ba7-815b-4771-9882-741a011f9817
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3449395285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.3449395285
Directory /workspace/114.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/115.usbdev_endpoint_types.3366463717
Short name T404
Test name
Test status
Simulation time 771007167 ps
CPU time 1.67 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:34 PM PDT 24
Peak memory 207324 kb
Host smart-521324fa-fd81-4f69-9444-d794f4c4ad15
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3366463717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.3366463717
Directory /workspace/115.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/118.usbdev_endpoint_types.786191475
Short name T1268
Test name
Test status
Simulation time 365707261 ps
CPU time 1.17 seconds
Started Aug 05 05:40:46 PM PDT 24
Finished Aug 05 05:40:47 PM PDT 24
Peak memory 207372 kb
Host smart-a559e9f3-6949-4e05-a2b1-d740798f82d8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=786191475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.786191475
Directory /workspace/118.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/119.usbdev_endpoint_types.1906903656
Short name T372
Test name
Test status
Simulation time 733083864 ps
CPU time 1.6 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:34 PM PDT 24
Peak memory 207272 kb
Host smart-f2305265-9625-42c8-84c5-27c589ac9e55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1906903656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.1906903656
Directory /workspace/119.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.2266504626
Short name T2891
Test name
Test status
Simulation time 11152435385 ps
CPU time 14.32 seconds
Started Aug 05 05:35:20 PM PDT 24
Finished Aug 05 05:35:35 PM PDT 24
Peak memory 207684 kb
Host smart-ecf7b1d4-9738-49bb-8f67-b301d5d96851
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266504626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.2266504626
Directory /workspace/12.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2687685152
Short name T2051
Test name
Test status
Simulation time 21408507365 ps
CPU time 24.76 seconds
Started Aug 05 05:35:15 PM PDT 24
Finished Aug 05 05:35:40 PM PDT 24
Peak memory 207624 kb
Host smart-cf9ef387-bc52-48ad-9b95-dd768e49cf13
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687685152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2687685152
Directory /workspace/12.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/12.usbdev_av_buffer.747334121
Short name T2552
Test name
Test status
Simulation time 195188270 ps
CPU time 0.85 seconds
Started Aug 05 05:35:15 PM PDT 24
Finished Aug 05 05:35:16 PM PDT 24
Peak memory 207416 kb
Host smart-266025da-73f6-4128-ac2f-4a8a79338005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74733
4121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.747334121
Directory /workspace/12.usbdev_av_buffer/latest


Test location /workspace/coverage/default/12.usbdev_bitstuff_err.2498384639
Short name T1664
Test name
Test status
Simulation time 147950376 ps
CPU time 0.82 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:23 PM PDT 24
Peak memory 207336 kb
Host smart-a9060f0e-6f09-4a4f-bb03-24ca789270f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24983
84639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.2498384639
Directory /workspace/12.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.1611406883
Short name T2521
Test name
Test status
Simulation time 283693094 ps
CPU time 1.21 seconds
Started Aug 05 05:35:17 PM PDT 24
Finished Aug 05 05:35:19 PM PDT 24
Peak memory 207404 kb
Host smart-1d87d727-f0c0-40b0-abde-f70df5c74537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16114
06883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.1611406883
Directory /workspace/12.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1403329740
Short name T800
Test name
Test status
Simulation time 817490763 ps
CPU time 2.4 seconds
Started Aug 05 05:35:14 PM PDT 24
Finished Aug 05 05:35:16 PM PDT 24
Peak memory 207504 kb
Host smart-48a87ce8-03f5-4387-8b02-741da751e8a4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1403329740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1403329740
Directory /workspace/12.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/12.usbdev_device_address.2040339363
Short name T2785
Test name
Test status
Simulation time 29196219749 ps
CPU time 43.83 seconds
Started Aug 05 05:35:15 PM PDT 24
Finished Aug 05 05:35:59 PM PDT 24
Peak memory 207740 kb
Host smart-6a56b9cc-4bed-4229-a66e-0b223c13a4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20403
39363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.2040339363
Directory /workspace/12.usbdev_device_address/latest


Test location /workspace/coverage/default/12.usbdev_device_timeout.1218581700
Short name T950
Test name
Test status
Simulation time 3839005338 ps
CPU time 35.79 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207648 kb
Host smart-211dce76-14fe-4b25-947e-56e1a3bcacf2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218581700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.1218581700
Directory /workspace/12.usbdev_device_timeout/latest


Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3496202764
Short name T2163
Test name
Test status
Simulation time 855700606 ps
CPU time 2.22 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:35:18 PM PDT 24
Peak memory 207336 kb
Host smart-9a19fa9e-4075-45b9-81ce-3d5938870209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34962
02764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3496202764
Directory /workspace/12.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/12.usbdev_disconnected.2656003801
Short name T1543
Test name
Test status
Simulation time 162208667 ps
CPU time 0.92 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:35:17 PM PDT 24
Peak memory 207344 kb
Host smart-aeda1497-d9d8-4c03-9ded-90d848dfe62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26560
03801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2656003801
Directory /workspace/12.usbdev_disconnected/latest


Test location /workspace/coverage/default/12.usbdev_enable.104440808
Short name T1737
Test name
Test status
Simulation time 44257611 ps
CPU time 0.74 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:35:17 PM PDT 24
Peak memory 207356 kb
Host smart-8e293047-63b6-4844-8b48-a4245d33b3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10444
0808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.104440808
Directory /workspace/12.usbdev_enable/latest


Test location /workspace/coverage/default/12.usbdev_endpoint_access.3301853485
Short name T1266
Test name
Test status
Simulation time 771674117 ps
CPU time 2.12 seconds
Started Aug 05 05:35:17 PM PDT 24
Finished Aug 05 05:35:19 PM PDT 24
Peak memory 207512 kb
Host smart-1b2c4a44-c179-4b21-a693-0ac5a5e034f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33018
53485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3301853485
Directory /workspace/12.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/12.usbdev_endpoint_types.762749985
Short name T2275
Test name
Test status
Simulation time 141210130 ps
CPU time 0.82 seconds
Started Aug 05 05:35:18 PM PDT 24
Finished Aug 05 05:35:19 PM PDT 24
Peak memory 207324 kb
Host smart-255504d1-8ea0-44ff-b05b-707eb0c28774
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=762749985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.762749985
Directory /workspace/12.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/12.usbdev_fifo_rst.2981415603
Short name T905
Test name
Test status
Simulation time 202328445 ps
CPU time 1.48 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:35:18 PM PDT 24
Peak memory 207744 kb
Host smart-02acdc07-9567-472e-8afb-3fea9a1c7e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29814
15603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2981415603
Directory /workspace/12.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/12.usbdev_in_iso.3272721719
Short name T2267
Test name
Test status
Simulation time 219043025 ps
CPU time 1.12 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:35:17 PM PDT 24
Peak memory 215740 kb
Host smart-08c93abc-50d6-40aa-88ae-9423b8721c1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3272721719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3272721719
Directory /workspace/12.usbdev_in_iso/latest


Test location /workspace/coverage/default/12.usbdev_in_stall.3384367338
Short name T1186
Test name
Test status
Simulation time 146848511 ps
CPU time 0.87 seconds
Started Aug 05 05:35:17 PM PDT 24
Finished Aug 05 05:35:18 PM PDT 24
Peak memory 207256 kb
Host smart-98fd0759-8caf-4c28-832b-5bc0b8c75ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33843
67338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3384367338
Directory /workspace/12.usbdev_in_stall/latest


Test location /workspace/coverage/default/12.usbdev_in_trans.2423350732
Short name T533
Test name
Test status
Simulation time 193562937 ps
CPU time 0.95 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:23 PM PDT 24
Peak memory 207384 kb
Host smart-62026d55-fdd7-4de4-8eb6-53cfae616771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24233
50732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2423350732
Directory /workspace/12.usbdev_in_trans/latest


Test location /workspace/coverage/default/12.usbdev_invalid_sync.4212858628
Short name T156
Test name
Test status
Simulation time 4422472890 ps
CPU time 44.92 seconds
Started Aug 05 05:35:17 PM PDT 24
Finished Aug 05 05:36:02 PM PDT 24
Peak memory 218144 kb
Host smart-7963481a-c6bd-4dfe-b2f9-fc7619110a98
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4212858628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.4212858628
Directory /workspace/12.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/12.usbdev_iso_retraction.1805651206
Short name T2978
Test name
Test status
Simulation time 9981274161 ps
CPU time 68.34 seconds
Started Aug 05 05:35:14 PM PDT 24
Finished Aug 05 05:36:23 PM PDT 24
Peak memory 207668 kb
Host smart-ba313b6a-5443-4fb1-a633-42d61ae0efed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1805651206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.1805651206
Directory /workspace/12.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/12.usbdev_link_in_err.808247498
Short name T1324
Test name
Test status
Simulation time 182496276 ps
CPU time 0.91 seconds
Started Aug 05 05:35:17 PM PDT 24
Finished Aug 05 05:35:18 PM PDT 24
Peak memory 207284 kb
Host smart-77c3e078-a903-4b75-a05b-450dd2dbcf00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80824
7498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.808247498
Directory /workspace/12.usbdev_link_in_err/latest


Test location /workspace/coverage/default/12.usbdev_link_resume.681578707
Short name T2210
Test name
Test status
Simulation time 10149870456 ps
CPU time 12.71 seconds
Started Aug 05 05:35:17 PM PDT 24
Finished Aug 05 05:35:29 PM PDT 24
Peak memory 207504 kb
Host smart-fd1e6d62-4a99-4dab-a486-9c29355a0c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68157
8707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.681578707
Directory /workspace/12.usbdev_link_resume/latest


Test location /workspace/coverage/default/12.usbdev_link_suspend.3652702736
Short name T1910
Test name
Test status
Simulation time 5583946440 ps
CPU time 6.72 seconds
Started Aug 05 05:35:15 PM PDT 24
Finished Aug 05 05:35:22 PM PDT 24
Peak memory 215808 kb
Host smart-a39be046-26c5-4764-b7c9-693bc10cec38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36527
02736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3652702736
Directory /workspace/12.usbdev_link_suspend/latest


Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2885920338
Short name T1313
Test name
Test status
Simulation time 3195475456 ps
CPU time 31.82 seconds
Started Aug 05 05:35:14 PM PDT 24
Finished Aug 05 05:35:46 PM PDT 24
Peak memory 224012 kb
Host smart-6d261988-6c6d-4b9f-81dd-848f02e1e920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28859
20338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2885920338
Directory /workspace/12.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3830156049
Short name T2447
Test name
Test status
Simulation time 3293130137 ps
CPU time 32.26 seconds
Started Aug 05 05:35:17 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 223840 kb
Host smart-c58a176f-2733-4307-82c7-826a46f66832
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3830156049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3830156049
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.2413900906
Short name T2115
Test name
Test status
Simulation time 242060599 ps
CPU time 1.01 seconds
Started Aug 05 05:35:20 PM PDT 24
Finished Aug 05 05:35:21 PM PDT 24
Peak memory 207400 kb
Host smart-b5e34bb8-852b-4f2f-9ec7-a3bc499e519d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2413900906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.2413900906
Directory /workspace/12.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.4060240864
Short name T551
Test name
Test status
Simulation time 206195615 ps
CPU time 0.9 seconds
Started Aug 05 05:35:20 PM PDT 24
Finished Aug 05 05:35:21 PM PDT 24
Peak memory 207424 kb
Host smart-872a808f-b2ee-4dbb-9a79-50d5a8f2f808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40602
40864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.4060240864
Directory /workspace/12.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.2326265827
Short name T2965
Test name
Test status
Simulation time 2881124032 ps
CPU time 28.25 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:35:44 PM PDT 24
Peak memory 217280 kb
Host smart-a2c98107-5bcb-4f8e-9adc-071f527eb22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23262
65827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.2326265827
Directory /workspace/12.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2733219826
Short name T1245
Test name
Test status
Simulation time 2052886074 ps
CPU time 63.56 seconds
Started Aug 05 05:35:15 PM PDT 24
Finished Aug 05 05:36:19 PM PDT 24
Peak memory 217540 kb
Host smart-5b1155cb-0a91-42ba-b263-81ed0d526d4e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2733219826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2733219826
Directory /workspace/12.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1561712000
Short name T2641
Test name
Test status
Simulation time 3826510723 ps
CPU time 39.92 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:35:56 PM PDT 24
Peak memory 215832 kb
Host smart-82c04254-5f86-4126-930a-220e9dcaf1b3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1561712000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1561712000
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.309936988
Short name T673
Test name
Test status
Simulation time 169408382 ps
CPU time 0.93 seconds
Started Aug 05 05:35:18 PM PDT 24
Finished Aug 05 05:35:19 PM PDT 24
Peak memory 207372 kb
Host smart-93b39861-9449-47c7-915e-12b505e0f06d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=309936988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.309936988
Directory /workspace/12.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2378724236
Short name T1828
Test name
Test status
Simulation time 155198745 ps
CPU time 0.88 seconds
Started Aug 05 05:35:18 PM PDT 24
Finished Aug 05 05:35:19 PM PDT 24
Peak memory 207404 kb
Host smart-c99128da-16b9-47f9-b879-849178c31785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23787
24236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2378724236
Directory /workspace/12.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/12.usbdev_out_iso.2186497497
Short name T1655
Test name
Test status
Simulation time 180198074 ps
CPU time 0.99 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:35:17 PM PDT 24
Peak memory 207268 kb
Host smart-c82e4751-658b-4f24-99f7-e3deb66421cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21864
97497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2186497497
Directory /workspace/12.usbdev_out_iso/latest


Test location /workspace/coverage/default/12.usbdev_out_stall.1433203259
Short name T2647
Test name
Test status
Simulation time 171461987 ps
CPU time 0.87 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:35:17 PM PDT 24
Peak memory 207408 kb
Host smart-6aa62252-2b02-4a28-9090-aa6e40639b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14332
03259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1433203259
Directory /workspace/12.usbdev_out_stall/latest


Test location /workspace/coverage/default/12.usbdev_out_trans_nak.721226345
Short name T1630
Test name
Test status
Simulation time 150269518 ps
CPU time 0.85 seconds
Started Aug 05 05:35:15 PM PDT 24
Finished Aug 05 05:35:16 PM PDT 24
Peak memory 207404 kb
Host smart-ef323d97-5ea8-4a83-aee3-492bb21a5663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72122
6345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.721226345
Directory /workspace/12.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3686084274
Short name T174
Test name
Test status
Simulation time 159598763 ps
CPU time 0.82 seconds
Started Aug 05 05:35:18 PM PDT 24
Finished Aug 05 05:35:19 PM PDT 24
Peak memory 207368 kb
Host smart-497afe67-3efd-40eb-a294-b62a6ba94468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36860
84274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3686084274
Directory /workspace/12.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.2367435777
Short name T743
Test name
Test status
Simulation time 194931183 ps
CPU time 0.97 seconds
Started Aug 05 05:35:15 PM PDT 24
Finished Aug 05 05:35:16 PM PDT 24
Peak memory 207412 kb
Host smart-01170957-c2b8-4368-b8e5-809a50943daa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2367435777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.2367435777
Directory /workspace/12.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2959647006
Short name T2627
Test name
Test status
Simulation time 139849474 ps
CPU time 0.82 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 207320 kb
Host smart-97059376-aa23-4423-8080-eb888d02b0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29596
47006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2959647006
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3433791370
Short name T3088
Test name
Test status
Simulation time 76731250 ps
CPU time 0.79 seconds
Started Aug 05 05:35:16 PM PDT 24
Finished Aug 05 05:35:17 PM PDT 24
Peak memory 207216 kb
Host smart-f777961a-e43f-4b5f-aeb4-2754ce097bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34337
91370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3433791370
Directory /workspace/12.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/12.usbdev_pkt_buffer.157596400
Short name T2633
Test name
Test status
Simulation time 11652266216 ps
CPU time 29.38 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:51 PM PDT 24
Peak memory 215924 kb
Host smart-cb11c853-60cb-421e-800b-a528f8624e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15759
6400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.157596400
Directory /workspace/12.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/12.usbdev_pkt_received.1610462000
Short name T2345
Test name
Test status
Simulation time 150681667 ps
CPU time 0.85 seconds
Started Aug 05 05:35:23 PM PDT 24
Finished Aug 05 05:35:24 PM PDT 24
Peak memory 207364 kb
Host smart-e1947044-2e7c-4718-bef8-f152805e6d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16104
62000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1610462000
Directory /workspace/12.usbdev_pkt_received/latest


Test location /workspace/coverage/default/12.usbdev_pkt_sent.1438948748
Short name T1668
Test name
Test status
Simulation time 182402384 ps
CPU time 1.19 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:23 PM PDT 24
Peak memory 207240 kb
Host smart-ef85c001-9890-47b5-a033-494df82784df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14389
48748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1438948748
Directory /workspace/12.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1392395647
Short name T2079
Test name
Test status
Simulation time 214316102 ps
CPU time 0.98 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:23 PM PDT 24
Peak memory 207316 kb
Host smart-220e36b8-104d-4461-ae02-4b01569efde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13923
95647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1392395647
Directory /workspace/12.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.1252536963
Short name T1434
Test name
Test status
Simulation time 216271453 ps
CPU time 1.05 seconds
Started Aug 05 05:35:25 PM PDT 24
Finished Aug 05 05:35:26 PM PDT 24
Peak memory 207348 kb
Host smart-de27f304-dc66-4476-9896-c970bb9dea17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12525
36963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.1252536963
Directory /workspace/12.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/12.usbdev_resume_link_active.211217196
Short name T3093
Test name
Test status
Simulation time 20159423504 ps
CPU time 23.89 seconds
Started Aug 05 05:35:21 PM PDT 24
Finished Aug 05 05:35:45 PM PDT 24
Peak memory 207432 kb
Host smart-c1423853-1856-471e-af85-eb7b712f0bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21121
7196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.211217196
Directory /workspace/12.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2392225365
Short name T987
Test name
Test status
Simulation time 148073974 ps
CPU time 0.8 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:23 PM PDT 24
Peak memory 207384 kb
Host smart-9b0ef164-e5bd-47ac-9018-6c69d6089697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23922
25365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2392225365
Directory /workspace/12.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/12.usbdev_rx_full.1314051171
Short name T2604
Test name
Test status
Simulation time 250028027 ps
CPU time 1.12 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:24 PM PDT 24
Peak memory 207396 kb
Host smart-6de490d1-06e9-4231-af13-b2d7fb5cc53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13140
51171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.1314051171
Directory /workspace/12.usbdev_rx_full/latest


Test location /workspace/coverage/default/12.usbdev_setup_stage.1458643941
Short name T556
Test name
Test status
Simulation time 176660779 ps
CPU time 0.93 seconds
Started Aug 05 05:35:25 PM PDT 24
Finished Aug 05 05:35:26 PM PDT 24
Peak memory 207292 kb
Host smart-fff8efd5-1c7b-448e-8970-c4d46f694732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14586
43941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.1458643941
Directory /workspace/12.usbdev_setup_stage/latest


Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1159966275
Short name T676
Test name
Test status
Simulation time 160009117 ps
CPU time 0.84 seconds
Started Aug 05 05:35:25 PM PDT 24
Finished Aug 05 05:35:26 PM PDT 24
Peak memory 207348 kb
Host smart-d04ce7ca-bcec-47ca-a163-567fb63ba799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11599
66275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1159966275
Directory /workspace/12.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/12.usbdev_smoke.613631950
Short name T1195
Test name
Test status
Simulation time 210114339 ps
CPU time 1.09 seconds
Started Aug 05 05:35:25 PM PDT 24
Finished Aug 05 05:35:26 PM PDT 24
Peak memory 207348 kb
Host smart-f21d26ab-9f0e-48b8-986b-3dc5a291cfb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61363
1950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.613631950
Directory /workspace/12.usbdev_smoke/latest


Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2727225140
Short name T1535
Test name
Test status
Simulation time 3105089913 ps
CPU time 24.79 seconds
Started Aug 05 05:35:25 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 224036 kb
Host smart-1f1a1271-b7f1-437a-a533-c6203a719203
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2727225140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2727225140
Directory /workspace/12.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1131388725
Short name T2575
Test name
Test status
Simulation time 197332113 ps
CPU time 0.94 seconds
Started Aug 05 05:35:28 PM PDT 24
Finished Aug 05 05:35:29 PM PDT 24
Peak memory 207228 kb
Host smart-077d7f5e-774d-4a9d-9309-6ec9e0b4903e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11313
88725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1131388725
Directory /workspace/12.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/12.usbdev_stall_trans.313299425
Short name T2593
Test name
Test status
Simulation time 157793206 ps
CPU time 0.85 seconds
Started Aug 05 05:35:29 PM PDT 24
Finished Aug 05 05:35:29 PM PDT 24
Peak memory 207224 kb
Host smart-ab98af08-a3d2-4379-a3e5-d69307cf88f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31329
9425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.313299425
Directory /workspace/12.usbdev_stall_trans/latest


Test location /workspace/coverage/default/12.usbdev_stream_len_max.1899306186
Short name T2953
Test name
Test status
Simulation time 851752122 ps
CPU time 2.23 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:24 PM PDT 24
Peak memory 207496 kb
Host smart-d063c356-6966-46be-b73b-c41e21c53442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18993
06186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.1899306186
Directory /workspace/12.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/12.usbdev_streaming_out.3770111655
Short name T3080
Test name
Test status
Simulation time 2352285493 ps
CPU time 19.36 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:41 PM PDT 24
Peak memory 207660 kb
Host smart-cbdd6e36-0ce3-440d-a868-f8a8e389c4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37701
11655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3770111655
Directory /workspace/12.usbdev_streaming_out/latest


Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.2022486109
Short name T2714
Test name
Test status
Simulation time 4388039523 ps
CPU time 36.7 seconds
Started Aug 05 05:35:17 PM PDT 24
Finished Aug 05 05:35:54 PM PDT 24
Peak memory 207608 kb
Host smart-5935cdbd-7a10-4461-9d89-ab2d35367d7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022486109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.2022486109
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/120.usbdev_endpoint_types.496134967
Short name T382
Test name
Test status
Simulation time 224888122 ps
CPU time 0.99 seconds
Started Aug 05 05:40:23 PM PDT 24
Finished Aug 05 05:40:24 PM PDT 24
Peak memory 207272 kb
Host smart-7446c170-42a2-4d40-8fde-89d17ec29587
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=496134967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.496134967
Directory /workspace/120.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/121.usbdev_endpoint_types.2583852657
Short name T2943
Test name
Test status
Simulation time 171951710 ps
CPU time 0.93 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:34 PM PDT 24
Peak memory 207232 kb
Host smart-d6fafd16-2cd3-4d5b-af30-47291789602b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2583852657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.2583852657
Directory /workspace/121.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/123.usbdev_endpoint_types.708310248
Short name T376
Test name
Test status
Simulation time 384978541 ps
CPU time 1.23 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:32 PM PDT 24
Peak memory 207324 kb
Host smart-baa63cec-72c8-40b7-8c88-10b11c1f40f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=708310248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.708310248
Directory /workspace/123.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/124.usbdev_endpoint_types.1458067662
Short name T397
Test name
Test status
Simulation time 489201723 ps
CPU time 1.35 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 207240 kb
Host smart-af498ea1-1922-4b12-b055-13023eebf6ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1458067662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.1458067662
Directory /workspace/124.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/125.usbdev_endpoint_types.1942976716
Short name T1663
Test name
Test status
Simulation time 199055293 ps
CPU time 0.93 seconds
Started Aug 05 05:40:37 PM PDT 24
Finished Aug 05 05:40:38 PM PDT 24
Peak memory 207324 kb
Host smart-e8492db1-23df-4ed7-9c76-3fa8b94ed313
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1942976716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.1942976716
Directory /workspace/125.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/126.usbdev_endpoint_types.1127312575
Short name T457
Test name
Test status
Simulation time 164713949 ps
CPU time 0.89 seconds
Started Aug 05 05:40:46 PM PDT 24
Finished Aug 05 05:40:47 PM PDT 24
Peak memory 207256 kb
Host smart-9a4ea0ab-f52a-4dbc-b5ee-afdf15c61b55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1127312575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.1127312575
Directory /workspace/126.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/127.usbdev_endpoint_types.459449617
Short name T441
Test name
Test status
Simulation time 357469009 ps
CPU time 1.18 seconds
Started Aug 05 05:40:40 PM PDT 24
Finished Aug 05 05:40:42 PM PDT 24
Peak memory 207320 kb
Host smart-2fb56af8-f17c-44a6-9cbe-8670cd859d9f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=459449617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.459449617
Directory /workspace/127.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/128.usbdev_endpoint_types.13727327
Short name T1182
Test name
Test status
Simulation time 174666218 ps
CPU time 0.87 seconds
Started Aug 05 05:40:47 PM PDT 24
Finished Aug 05 05:40:48 PM PDT 24
Peak memory 207368 kb
Host smart-575bab53-d904-4cfa-aa85-ef1b58519d81
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=13727327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.13727327
Directory /workspace/128.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/129.usbdev_endpoint_types.236946830
Short name T448
Test name
Test status
Simulation time 277555203 ps
CPU time 1.07 seconds
Started Aug 05 05:40:46 PM PDT 24
Finished Aug 05 05:40:48 PM PDT 24
Peak memory 207240 kb
Host smart-307ea175-aab4-4ef0-b90a-f3f8c7b21034
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=236946830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.236946830
Directory /workspace/129.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/13.usbdev_alert_test.601080677
Short name T2570
Test name
Test status
Simulation time 39574735 ps
CPU time 0.67 seconds
Started Aug 05 05:35:34 PM PDT 24
Finished Aug 05 05:35:35 PM PDT 24
Peak memory 207388 kb
Host smart-dda97fba-5396-4ad8-854c-ec60a1aa463d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=601080677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.601080677
Directory /workspace/13.usbdev_alert_test/latest


Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3065918090
Short name T779
Test name
Test status
Simulation time 9261389922 ps
CPU time 11.36 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:33 PM PDT 24
Peak memory 207596 kb
Host smart-6a5c6152-9d07-4064-9f49-f063a9fac895
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065918090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.3065918090
Directory /workspace/13.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3678857997
Short name T1000
Test name
Test status
Simulation time 18502220959 ps
CPU time 24.41 seconds
Started Aug 05 05:35:21 PM PDT 24
Finished Aug 05 05:35:45 PM PDT 24
Peak memory 207536 kb
Host smart-b7d437d1-efac-4967-b44d-e82432b478d2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678857997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3678857997
Directory /workspace/13.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.1979902970
Short name T669
Test name
Test status
Simulation time 25590093943 ps
CPU time 29.94 seconds
Started Aug 05 05:35:29 PM PDT 24
Finished Aug 05 05:35:59 PM PDT 24
Peak memory 215708 kb
Host smart-8d070f7c-4d98-4a53-a54e-cf83334f81ed
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979902970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.1979902970
Directory /workspace/13.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/13.usbdev_av_buffer.602796979
Short name T2966
Test name
Test status
Simulation time 208298206 ps
CPU time 0.98 seconds
Started Aug 05 05:35:23 PM PDT 24
Finished Aug 05 05:35:25 PM PDT 24
Peak memory 207460 kb
Host smart-dbdb7d48-9692-41cb-9e48-27d572ceeb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60279
6979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.602796979
Directory /workspace/13.usbdev_av_buffer/latest


Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2989045849
Short name T1038
Test name
Test status
Simulation time 173686807 ps
CPU time 0.85 seconds
Started Aug 05 05:35:25 PM PDT 24
Finished Aug 05 05:35:26 PM PDT 24
Peak memory 207344 kb
Host smart-527a4cf8-a87a-4c17-acae-399ce6da13b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29890
45849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2989045849
Directory /workspace/13.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3646197037
Short name T1436
Test name
Test status
Simulation time 456779669 ps
CPU time 1.56 seconds
Started Aug 05 05:35:21 PM PDT 24
Finished Aug 05 05:35:23 PM PDT 24
Peak memory 207404 kb
Host smart-833b1c64-6f4d-4189-b577-f3914b2a6ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36461
97037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3646197037
Directory /workspace/13.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2630731997
Short name T2428
Test name
Test status
Simulation time 312774659 ps
CPU time 1.12 seconds
Started Aug 05 05:35:25 PM PDT 24
Finished Aug 05 05:35:26 PM PDT 24
Peak memory 207236 kb
Host smart-532429bf-7cc0-46f0-8650-73767bb25903
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2630731997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2630731997
Directory /workspace/13.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/13.usbdev_device_address.424250148
Short name T175
Test name
Test status
Simulation time 50242185501 ps
CPU time 75.47 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:36:38 PM PDT 24
Peak memory 207628 kb
Host smart-f0155b35-17b4-422c-bfc8-e315582b8502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42425
0148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.424250148
Directory /workspace/13.usbdev_device_address/latest


Test location /workspace/coverage/default/13.usbdev_device_timeout.829522985
Short name T2316
Test name
Test status
Simulation time 1016531758 ps
CPU time 23.27 seconds
Started Aug 05 05:35:21 PM PDT 24
Finished Aug 05 05:35:44 PM PDT 24
Peak memory 207440 kb
Host smart-a8568b70-e089-4123-b89e-2ef1ee489ec9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829522985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.829522985
Directory /workspace/13.usbdev_device_timeout/latest


Test location /workspace/coverage/default/13.usbdev_disable_endpoint.698784071
Short name T322
Test name
Test status
Simulation time 727014005 ps
CPU time 1.8 seconds
Started Aug 05 05:35:23 PM PDT 24
Finished Aug 05 05:35:24 PM PDT 24
Peak memory 207276 kb
Host smart-ab45737f-40f9-4f67-bebf-8c28d2bee4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69878
4071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.698784071
Directory /workspace/13.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/13.usbdev_enable.2227530366
Short name T2463
Test name
Test status
Simulation time 108343781 ps
CPU time 0.81 seconds
Started Aug 05 05:35:21 PM PDT 24
Finished Aug 05 05:35:22 PM PDT 24
Peak memory 207304 kb
Host smart-157427af-538f-46fe-bd79-a1501960ac03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22275
30366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2227530366
Directory /workspace/13.usbdev_enable/latest


Test location /workspace/coverage/default/13.usbdev_endpoint_access.3910034427
Short name T1040
Test name
Test status
Simulation time 879409539 ps
CPU time 2.28 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:25 PM PDT 24
Peak memory 207520 kb
Host smart-7853b38d-0960-46b2-9421-abdbffaf501a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39100
34427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.3910034427
Directory /workspace/13.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/13.usbdev_endpoint_types.2684193362
Short name T2677
Test name
Test status
Simulation time 356760046 ps
CPU time 1.19 seconds
Started Aug 05 05:35:21 PM PDT 24
Finished Aug 05 05:35:22 PM PDT 24
Peak memory 207316 kb
Host smart-2dc927bc-c360-4095-93e8-136112417682
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2684193362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.2684193362
Directory /workspace/13.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/13.usbdev_fifo_rst.3118695980
Short name T1079
Test name
Test status
Simulation time 175723024 ps
CPU time 2.15 seconds
Started Aug 05 05:35:25 PM PDT 24
Finished Aug 05 05:35:27 PM PDT 24
Peak memory 207424 kb
Host smart-4353e4f8-4a1d-4fec-8f42-efb6190f333c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31186
95980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3118695980
Directory /workspace/13.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/13.usbdev_in_iso.1495706293
Short name T2835
Test name
Test status
Simulation time 220150474 ps
CPU time 1.06 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:35:24 PM PDT 24
Peak memory 207536 kb
Host smart-0a4f07d4-bb04-4677-a4a7-f2f942524bfe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1495706293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1495706293
Directory /workspace/13.usbdev_in_iso/latest


Test location /workspace/coverage/default/13.usbdev_in_stall.607971331
Short name T3010
Test name
Test status
Simulation time 177705057 ps
CPU time 0.9 seconds
Started Aug 05 05:35:23 PM PDT 24
Finished Aug 05 05:35:24 PM PDT 24
Peak memory 207440 kb
Host smart-4f7ae298-8dcd-4480-a099-0aa12801d102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60797
1331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.607971331
Directory /workspace/13.usbdev_in_stall/latest


Test location /workspace/coverage/default/13.usbdev_in_trans.2039061075
Short name T2866
Test name
Test status
Simulation time 195537192 ps
CPU time 0.92 seconds
Started Aug 05 05:35:21 PM PDT 24
Finished Aug 05 05:35:22 PM PDT 24
Peak memory 207396 kb
Host smart-554a9e89-4152-48c8-a811-cd97bbc60aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20390
61075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2039061075
Directory /workspace/13.usbdev_in_trans/latest


Test location /workspace/coverage/default/13.usbdev_invalid_sync.1731479727
Short name T2513
Test name
Test status
Simulation time 4328636004 ps
CPU time 123.52 seconds
Started Aug 05 05:35:22 PM PDT 24
Finished Aug 05 05:37:26 PM PDT 24
Peak memory 215780 kb
Host smart-55490b39-e5a0-4753-ab55-11a8fc3ee214
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1731479727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.1731479727
Directory /workspace/13.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/13.usbdev_iso_retraction.1669159551
Short name T2929
Test name
Test status
Simulation time 11380651286 ps
CPU time 70.72 seconds
Started Aug 05 05:35:21 PM PDT 24
Finished Aug 05 05:36:31 PM PDT 24
Peak memory 207668 kb
Host smart-370609b8-8b0a-4362-81df-f3aa25a46ff3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1669159551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.1669159551
Directory /workspace/13.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/13.usbdev_link_in_err.770557479
Short name T1341
Test name
Test status
Simulation time 230563818 ps
CPU time 0.95 seconds
Started Aug 05 05:35:23 PM PDT 24
Finished Aug 05 05:35:24 PM PDT 24
Peak memory 207348 kb
Host smart-4c8b23ec-3692-48dc-8912-4dd634197db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77055
7479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.770557479
Directory /workspace/13.usbdev_link_in_err/latest


Test location /workspace/coverage/default/13.usbdev_link_resume.3166466964
Short name T2027
Test name
Test status
Simulation time 9755878825 ps
CPU time 15.36 seconds
Started Aug 05 05:35:29 PM PDT 24
Finished Aug 05 05:35:44 PM PDT 24
Peak memory 207608 kb
Host smart-b925f5a8-427a-4e3b-ad71-2118173ce505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31664
66964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3166466964
Directory /workspace/13.usbdev_link_resume/latest


Test location /workspace/coverage/default/13.usbdev_link_suspend.3061128950
Short name T1919
Test name
Test status
Simulation time 3409805566 ps
CPU time 5.22 seconds
Started Aug 05 05:35:34 PM PDT 24
Finished Aug 05 05:35:40 PM PDT 24
Peak memory 215812 kb
Host smart-6627c814-3764-462b-9cb8-a2a337106b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30611
28950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3061128950
Directory /workspace/13.usbdev_link_suspend/latest


Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.294980222
Short name T1221
Test name
Test status
Simulation time 4133173666 ps
CPU time 30.01 seconds
Started Aug 05 05:35:32 PM PDT 24
Finished Aug 05 05:36:02 PM PDT 24
Peak memory 215852 kb
Host smart-9d28f0ba-360f-48c1-8f7b-213adf1e2cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29498
0222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.294980222
Directory /workspace/13.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1543999680
Short name T1544
Test name
Test status
Simulation time 3713274171 ps
CPU time 106.35 seconds
Started Aug 05 05:35:29 PM PDT 24
Finished Aug 05 05:37:16 PM PDT 24
Peak memory 217304 kb
Host smart-f452cfb4-188d-46fa-8623-8c267b278285
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1543999680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1543999680
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.444734152
Short name T1816
Test name
Test status
Simulation time 241809792 ps
CPU time 1 seconds
Started Aug 05 05:35:31 PM PDT 24
Finished Aug 05 05:35:32 PM PDT 24
Peak memory 207240 kb
Host smart-e08b4845-4de9-4c4d-b104-1e2c9ddaa05a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=444734152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.444734152
Directory /workspace/13.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1519405850
Short name T3090
Test name
Test status
Simulation time 226611608 ps
CPU time 1.01 seconds
Started Aug 05 05:35:30 PM PDT 24
Finished Aug 05 05:35:31 PM PDT 24
Peak memory 207276 kb
Host smart-25522386-6508-49fc-9d74-4b3588720687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194
05850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1519405850
Directory /workspace/13.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.3664035824
Short name T1950
Test name
Test status
Simulation time 2805999788 ps
CPU time 82.65 seconds
Started Aug 05 05:35:30 PM PDT 24
Finished Aug 05 05:36:53 PM PDT 24
Peak memory 223996 kb
Host smart-13a0a99a-2c6f-4f7c-b9c3-dddbfbc949fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36640
35824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.3664035824
Directory /workspace/13.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1824872632
Short name T116
Test name
Test status
Simulation time 2128039528 ps
CPU time 63.46 seconds
Started Aug 05 05:35:33 PM PDT 24
Finished Aug 05 05:36:37 PM PDT 24
Peak memory 217640 kb
Host smart-97ad4692-9408-49c1-9316-34f7c39fa994
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1824872632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1824872632
Directory /workspace/13.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3152520209
Short name T536
Test name
Test status
Simulation time 2091283219 ps
CPU time 60.05 seconds
Started Aug 05 05:35:33 PM PDT 24
Finished Aug 05 05:36:33 PM PDT 24
Peak memory 217092 kb
Host smart-792d1e8d-3a24-4507-a917-8a1bf491d9e4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3152520209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3152520209
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2875884043
Short name T2145
Test name
Test status
Simulation time 171467441 ps
CPU time 0.89 seconds
Started Aug 05 05:35:33 PM PDT 24
Finished Aug 05 05:35:34 PM PDT 24
Peak memory 207348 kb
Host smart-bd9e4945-45b6-4ed9-84db-87e2c4d6cc93
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2875884043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2875884043
Directory /workspace/13.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.567130027
Short name T1718
Test name
Test status
Simulation time 160234338 ps
CPU time 0.91 seconds
Started Aug 05 05:35:29 PM PDT 24
Finished Aug 05 05:35:30 PM PDT 24
Peak memory 207272 kb
Host smart-5617db1a-6527-463d-8667-6ff567a199ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56713
0027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.567130027
Directory /workspace/13.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/13.usbdev_out_iso.3523169815
Short name T2232
Test name
Test status
Simulation time 166875149 ps
CPU time 0.96 seconds
Started Aug 05 05:35:34 PM PDT 24
Finished Aug 05 05:35:35 PM PDT 24
Peak memory 207348 kb
Host smart-eb9a7800-fbb1-4874-aa20-e6b3d55cbffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35231
69815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3523169815
Directory /workspace/13.usbdev_out_iso/latest


Test location /workspace/coverage/default/13.usbdev_out_stall.3597065319
Short name T2446
Test name
Test status
Simulation time 217187288 ps
CPU time 0.97 seconds
Started Aug 05 05:35:30 PM PDT 24
Finished Aug 05 05:35:31 PM PDT 24
Peak memory 207240 kb
Host smart-3541989f-b603-4cf6-8aa7-9756d0ebfcd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35970
65319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3597065319
Directory /workspace/13.usbdev_out_stall/latest


Test location /workspace/coverage/default/13.usbdev_out_trans_nak.4076581948
Short name T2566
Test name
Test status
Simulation time 179656997 ps
CPU time 0.93 seconds
Started Aug 05 05:35:34 PM PDT 24
Finished Aug 05 05:35:35 PM PDT 24
Peak memory 207404 kb
Host smart-0dd316ae-ac32-4713-ae91-8b1418705c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40765
81948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.4076581948
Directory /workspace/13.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/13.usbdev_pending_in_trans.301912946
Short name T2162
Test name
Test status
Simulation time 162892327 ps
CPU time 0.89 seconds
Started Aug 05 05:35:32 PM PDT 24
Finished Aug 05 05:35:33 PM PDT 24
Peak memory 207384 kb
Host smart-7928a473-8ca1-4a3e-9060-e69f0675008f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30191
2946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.301912946
Directory /workspace/13.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.50037313
Short name T2884
Test name
Test status
Simulation time 224493942 ps
CPU time 0.97 seconds
Started Aug 05 05:35:33 PM PDT 24
Finished Aug 05 05:35:34 PM PDT 24
Peak memory 207304 kb
Host smart-5dc0c658-48df-46de-96bc-ab31f803e30b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=50037313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.50037313
Directory /workspace/13.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.2218138141
Short name T1620
Test name
Test status
Simulation time 172706373 ps
CPU time 0.87 seconds
Started Aug 05 05:35:28 PM PDT 24
Finished Aug 05 05:35:29 PM PDT 24
Peak memory 207240 kb
Host smart-b4523d1f-727c-411d-abb5-c11c83a20fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22181
38141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.2218138141
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3629288097
Short name T1800
Test name
Test status
Simulation time 13755471735 ps
CPU time 35.66 seconds
Started Aug 05 05:35:28 PM PDT 24
Finished Aug 05 05:36:04 PM PDT 24
Peak memory 215868 kb
Host smart-1ab022a8-735a-46ac-894e-b70ac25b3b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36292
88097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3629288097
Directory /workspace/13.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/13.usbdev_pkt_received.1444060324
Short name T2964
Test name
Test status
Simulation time 192592764 ps
CPU time 0.91 seconds
Started Aug 05 05:35:32 PM PDT 24
Finished Aug 05 05:35:33 PM PDT 24
Peak memory 207324 kb
Host smart-b49f87ca-3723-4f4a-88a5-126c29047e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14440
60324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1444060324
Directory /workspace/13.usbdev_pkt_received/latest


Test location /workspace/coverage/default/13.usbdev_pkt_sent.1656068483
Short name T1211
Test name
Test status
Simulation time 184877314 ps
CPU time 0.88 seconds
Started Aug 05 05:35:33 PM PDT 24
Finished Aug 05 05:35:34 PM PDT 24
Peak memory 207196 kb
Host smart-52bd832c-ef34-424a-aeec-df400dd86195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16560
68483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1656068483
Directory /workspace/13.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.3747851847
Short name T1612
Test name
Test status
Simulation time 200722050 ps
CPU time 0.89 seconds
Started Aug 05 05:35:29 PM PDT 24
Finished Aug 05 05:35:30 PM PDT 24
Peak memory 207396 kb
Host smart-f606000e-86f9-4ccb-af38-57f0553a7eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37478
51847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.3747851847
Directory /workspace/13.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.484855990
Short name T702
Test name
Test status
Simulation time 178062554 ps
CPU time 0.93 seconds
Started Aug 05 05:35:32 PM PDT 24
Finished Aug 05 05:35:33 PM PDT 24
Peak memory 207364 kb
Host smart-22085efe-54fa-44da-8ba9-6d33b8b37e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48485
5990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.484855990
Directory /workspace/13.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/13.usbdev_rx_crc_err.836105763
Short name T2371
Test name
Test status
Simulation time 174645751 ps
CPU time 0.86 seconds
Started Aug 05 05:35:32 PM PDT 24
Finished Aug 05 05:35:33 PM PDT 24
Peak memory 207364 kb
Host smart-f7d591f7-92c8-4f38-a7df-83cd7d7463c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83610
5763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.836105763
Directory /workspace/13.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/13.usbdev_rx_full.1671940922
Short name T1283
Test name
Test status
Simulation time 402420640 ps
CPU time 1.37 seconds
Started Aug 05 05:35:33 PM PDT 24
Finished Aug 05 05:35:35 PM PDT 24
Peak memory 207336 kb
Host smart-3188b58f-b0ba-4564-8260-bf46af7232a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16719
40922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.1671940922
Directory /workspace/13.usbdev_rx_full/latest


Test location /workspace/coverage/default/13.usbdev_setup_stage.1341859531
Short name T1993
Test name
Test status
Simulation time 168407183 ps
CPU time 0.91 seconds
Started Aug 05 05:35:31 PM PDT 24
Finished Aug 05 05:35:32 PM PDT 24
Peak memory 207344 kb
Host smart-ea44995d-f46a-49c7-ab92-c37e7a4f6a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13418
59531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1341859531
Directory /workspace/13.usbdev_setup_stage/latest


Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.391245929
Short name T1022
Test name
Test status
Simulation time 159734748 ps
CPU time 0.87 seconds
Started Aug 05 05:35:32 PM PDT 24
Finished Aug 05 05:35:33 PM PDT 24
Peak memory 207276 kb
Host smart-f1519a61-35b2-4168-9d3b-ccb0178a6792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39124
5929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.391245929
Directory /workspace/13.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/13.usbdev_smoke.1202336087
Short name T674
Test name
Test status
Simulation time 237847100 ps
CPU time 1.04 seconds
Started Aug 05 05:35:31 PM PDT 24
Finished Aug 05 05:35:32 PM PDT 24
Peak memory 207376 kb
Host smart-abcf994d-2ad1-4f34-9eaf-ce0076422d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12023
36087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1202336087
Directory /workspace/13.usbdev_smoke/latest


Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.1131020455
Short name T877
Test name
Test status
Simulation time 2362233411 ps
CPU time 20.52 seconds
Started Aug 05 05:35:31 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 217808 kb
Host smart-b8ebd8f0-4a48-4c73-9ecd-83273b9b7ff9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1131020455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.1131020455
Directory /workspace/13.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1382899332
Short name T2167
Test name
Test status
Simulation time 181964207 ps
CPU time 0.86 seconds
Started Aug 05 05:35:30 PM PDT 24
Finished Aug 05 05:35:31 PM PDT 24
Peak memory 207428 kb
Host smart-adaf733d-26f6-43c2-93d8-2eb4543cea24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13828
99332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1382899332
Directory /workspace/13.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/13.usbdev_stall_trans.297855994
Short name T1970
Test name
Test status
Simulation time 163798505 ps
CPU time 0.89 seconds
Started Aug 05 05:35:31 PM PDT 24
Finished Aug 05 05:35:32 PM PDT 24
Peak memory 207320 kb
Host smart-217ad8fb-5a34-487f-96d1-b729aa28bff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29785
5994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.297855994
Directory /workspace/13.usbdev_stall_trans/latest


Test location /workspace/coverage/default/13.usbdev_stream_len_max.252977610
Short name T861
Test name
Test status
Simulation time 429274581 ps
CPU time 1.36 seconds
Started Aug 05 05:35:32 PM PDT 24
Finished Aug 05 05:35:34 PM PDT 24
Peak memory 207368 kb
Host smart-1bfbdc86-4d13-430c-bdb0-7a1fddc17701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25297
7610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.252977610
Directory /workspace/13.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/13.usbdev_streaming_out.1051230756
Short name T1917
Test name
Test status
Simulation time 3405637536 ps
CPU time 35.58 seconds
Started Aug 05 05:35:31 PM PDT 24
Finished Aug 05 05:36:06 PM PDT 24
Peak memory 217348 kb
Host smart-a357b0c8-6487-49bb-8259-cad6249d7919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10512
30756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.1051230756
Directory /workspace/13.usbdev_streaming_out/latest


Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.820878659
Short name T2260
Test name
Test status
Simulation time 1450692239 ps
CPU time 34.72 seconds
Started Aug 05 05:35:20 PM PDT 24
Finished Aug 05 05:35:55 PM PDT 24
Peak memory 207580 kb
Host smart-945a5617-9892-4a89-af48-24af8561927e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820878659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_host
_handshake.820878659
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/131.usbdev_endpoint_types.3842254241
Short name T2068
Test name
Test status
Simulation time 153537877 ps
CPU time 0.87 seconds
Started Aug 05 05:40:45 PM PDT 24
Finished Aug 05 05:40:46 PM PDT 24
Peak memory 207444 kb
Host smart-61d383b9-9ddd-4bc1-bb54-64dfe50a0875
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3842254241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.3842254241
Directory /workspace/131.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/132.usbdev_endpoint_types.3418857561
Short name T440
Test name
Test status
Simulation time 245518714 ps
CPU time 1.09 seconds
Started Aug 05 05:40:45 PM PDT 24
Finished Aug 05 05:40:46 PM PDT 24
Peak memory 207556 kb
Host smart-8415f0f0-8da4-4597-b6ff-e328eb3f269d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3418857561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.3418857561
Directory /workspace/132.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/133.usbdev_endpoint_types.1588166636
Short name T347
Test name
Test status
Simulation time 413562472 ps
CPU time 1.3 seconds
Started Aug 05 05:40:52 PM PDT 24
Finished Aug 05 05:40:53 PM PDT 24
Peak memory 207372 kb
Host smart-19403445-93ad-4e2a-a929-6a8b10a8c16f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1588166636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.1588166636
Directory /workspace/133.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/134.usbdev_endpoint_types.3811815019
Short name T296
Test name
Test status
Simulation time 565328743 ps
CPU time 1.65 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:40:51 PM PDT 24
Peak memory 207320 kb
Host smart-0bdbf4ed-9bf8-4b32-a7db-a8d501ea1f49
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3811815019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.3811815019
Directory /workspace/134.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/135.usbdev_endpoint_types.3565905281
Short name T114
Test name
Test status
Simulation time 575340092 ps
CPU time 1.43 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:40:51 PM PDT 24
Peak memory 207344 kb
Host smart-60403ed5-954a-4d53-99d7-59d72957adb8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3565905281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.3565905281
Directory /workspace/135.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/136.usbdev_endpoint_types.1740300001
Short name T332
Test name
Test status
Simulation time 514678412 ps
CPU time 1.39 seconds
Started Aug 05 05:40:41 PM PDT 24
Finished Aug 05 05:40:43 PM PDT 24
Peak memory 207280 kb
Host smart-81fb460f-5f89-4907-9f1b-0710591d6fa9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1740300001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.1740300001
Directory /workspace/136.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/137.usbdev_endpoint_types.2057563949
Short name T389
Test name
Test status
Simulation time 490342027 ps
CPU time 1.35 seconds
Started Aug 05 05:40:47 PM PDT 24
Finished Aug 05 05:40:48 PM PDT 24
Peak memory 207312 kb
Host smart-8e61c181-cea4-4631-a4f0-4c9ccc1950e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2057563949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.2057563949
Directory /workspace/137.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/138.usbdev_endpoint_types.2814702472
Short name T425
Test name
Test status
Simulation time 504251606 ps
CPU time 1.33 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207324 kb
Host smart-2c7dca14-6caf-44ad-a183-3343cb155371
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2814702472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.2814702472
Directory /workspace/138.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/139.usbdev_endpoint_types.3839846705
Short name T1998
Test name
Test status
Simulation time 273202341 ps
CPU time 1.01 seconds
Started Aug 05 05:40:48 PM PDT 24
Finished Aug 05 05:40:49 PM PDT 24
Peak memory 207316 kb
Host smart-cd102a53-f2dd-4130-ad37-54cf533bca8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3839846705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.3839846705
Directory /workspace/139.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/14.usbdev_alert_test.1419691974
Short name T1546
Test name
Test status
Simulation time 37675979 ps
CPU time 0.68 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207432 kb
Host smart-8bd251d8-2b32-47cc-9f9b-49775f04fb4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1419691974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.1419691974
Directory /workspace/14.usbdev_alert_test/latest


Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1164259751
Short name T2322
Test name
Test status
Simulation time 5852283603 ps
CPU time 8.83 seconds
Started Aug 05 05:35:32 PM PDT 24
Finished Aug 05 05:35:41 PM PDT 24
Peak memory 215768 kb
Host smart-f201e649-79c8-40af-8c09-90cbcfd8f5ce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164259751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.1164259751
Directory /workspace/14.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.4062432942
Short name T999
Test name
Test status
Simulation time 13815672700 ps
CPU time 16.33 seconds
Started Aug 05 05:35:30 PM PDT 24
Finished Aug 05 05:35:46 PM PDT 24
Peak memory 215888 kb
Host smart-a6f1f9cc-47a6-4ed2-8d31-2cd6de3512be
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062432942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.4062432942
Directory /workspace/14.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1482009640
Short name T1690
Test name
Test status
Simulation time 24987281510 ps
CPU time 29.71 seconds
Started Aug 05 05:35:32 PM PDT 24
Finished Aug 05 05:36:02 PM PDT 24
Peak memory 215860 kb
Host smart-e10e10e0-e674-4951-b09f-0aaf7657491e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482009640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.1482009640
Directory /workspace/14.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/14.usbdev_av_buffer.698269055
Short name T1938
Test name
Test status
Simulation time 151790600 ps
CPU time 0.84 seconds
Started Aug 05 05:35:37 PM PDT 24
Finished Aug 05 05:35:38 PM PDT 24
Peak memory 207260 kb
Host smart-fc84dbb9-5a2f-4821-baad-8424de72aac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69826
9055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.698269055
Directory /workspace/14.usbdev_av_buffer/latest


Test location /workspace/coverage/default/14.usbdev_bitstuff_err.606169194
Short name T2127
Test name
Test status
Simulation time 174594249 ps
CPU time 0.85 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207308 kb
Host smart-0004b1b6-05e7-4247-982d-e6f50ed1ef65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60616
9194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.606169194
Directory /workspace/14.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.338347220
Short name T1853
Test name
Test status
Simulation time 292548722 ps
CPU time 1.12 seconds
Started Aug 05 05:35:58 PM PDT 24
Finished Aug 05 05:35:59 PM PDT 24
Peak memory 207248 kb
Host smart-287971da-684e-422e-af23-6266254ba21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33834
7220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.338347220
Directory /workspace/14.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3141366729
Short name T3057
Test name
Test status
Simulation time 270082636 ps
CPU time 1.08 seconds
Started Aug 05 05:35:42 PM PDT 24
Finished Aug 05 05:35:43 PM PDT 24
Peak memory 207356 kb
Host smart-7d83c2ed-dad1-47e6-af6c-271fb046923d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3141366729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3141366729
Directory /workspace/14.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/14.usbdev_device_address.278840350
Short name T909
Test name
Test status
Simulation time 35882667884 ps
CPU time 51.81 seconds
Started Aug 05 05:35:42 PM PDT 24
Finished Aug 05 05:36:34 PM PDT 24
Peak memory 207516 kb
Host smart-b44a3976-b9a4-4992-958e-bf641951ad38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27884
0350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.278840350
Directory /workspace/14.usbdev_device_address/latest


Test location /workspace/coverage/default/14.usbdev_device_timeout.1343015449
Short name T1260
Test name
Test status
Simulation time 191044049 ps
CPU time 0.92 seconds
Started Aug 05 05:35:39 PM PDT 24
Finished Aug 05 05:35:40 PM PDT 24
Peak memory 207308 kb
Host smart-a0cced5c-940c-45c2-ac3c-09a52a554dde
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343015449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.1343015449
Directory /workspace/14.usbdev_device_timeout/latest


Test location /workspace/coverage/default/14.usbdev_disable_endpoint.698955286
Short name T2632
Test name
Test status
Simulation time 697486900 ps
CPU time 1.65 seconds
Started Aug 05 05:35:37 PM PDT 24
Finished Aug 05 05:35:39 PM PDT 24
Peak memory 207388 kb
Host smart-2d033232-13f1-4d1e-972e-a0a36a811531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69895
5286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.698955286
Directory /workspace/14.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/14.usbdev_disconnected.185559693
Short name T2847
Test name
Test status
Simulation time 138706018 ps
CPU time 0.87 seconds
Started Aug 05 05:35:39 PM PDT 24
Finished Aug 05 05:35:40 PM PDT 24
Peak memory 207316 kb
Host smart-bc981f02-075f-45a2-b813-fce6ac29aa47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18555
9693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.185559693
Directory /workspace/14.usbdev_disconnected/latest


Test location /workspace/coverage/default/14.usbdev_enable.1390788227
Short name T897
Test name
Test status
Simulation time 82559655 ps
CPU time 0.72 seconds
Started Aug 05 05:35:42 PM PDT 24
Finished Aug 05 05:35:43 PM PDT 24
Peak memory 207216 kb
Host smart-330cb1c1-a0fa-4a0a-824e-2d04dcc2c69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13907
88227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1390788227
Directory /workspace/14.usbdev_enable/latest


Test location /workspace/coverage/default/14.usbdev_endpoint_access.1052914637
Short name T1202
Test name
Test status
Simulation time 964194302 ps
CPU time 2.61 seconds
Started Aug 05 05:35:38 PM PDT 24
Finished Aug 05 05:35:40 PM PDT 24
Peak memory 207860 kb
Host smart-1408b5ca-dc5e-44c2-8386-006a1a05ba1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10529
14637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1052914637
Directory /workspace/14.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/14.usbdev_endpoint_types.3346856594
Short name T1574
Test name
Test status
Simulation time 311474580 ps
CPU time 1.14 seconds
Started Aug 05 05:35:41 PM PDT 24
Finished Aug 05 05:35:42 PM PDT 24
Peak memory 207244 kb
Host smart-ed23b472-a4c6-44ff-8b2e-7596a8784ed8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3346856594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.3346856594
Directory /workspace/14.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/14.usbdev_fifo_rst.1269660953
Short name T2159
Test name
Test status
Simulation time 188463495 ps
CPU time 2.46 seconds
Started Aug 05 05:35:41 PM PDT 24
Finished Aug 05 05:35:43 PM PDT 24
Peak memory 207512 kb
Host smart-75384ef6-7f40-402d-83c6-db923eef1634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12696
60953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1269660953
Directory /workspace/14.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/14.usbdev_in_iso.2685148467
Short name T1015
Test name
Test status
Simulation time 261037508 ps
CPU time 1.17 seconds
Started Aug 05 05:35:39 PM PDT 24
Finished Aug 05 05:35:41 PM PDT 24
Peak memory 207488 kb
Host smart-fe1dbe0b-5679-405b-a20d-b88f320dc53a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2685148467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2685148467
Directory /workspace/14.usbdev_in_iso/latest


Test location /workspace/coverage/default/14.usbdev_in_stall.2950649935
Short name T2500
Test name
Test status
Simulation time 139521848 ps
CPU time 0.78 seconds
Started Aug 05 05:35:39 PM PDT 24
Finished Aug 05 05:35:40 PM PDT 24
Peak memory 207272 kb
Host smart-1a8ac41c-55ff-4079-a215-23ba43437a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29506
49935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2950649935
Directory /workspace/14.usbdev_in_stall/latest


Test location /workspace/coverage/default/14.usbdev_in_trans.1386430548
Short name T1062
Test name
Test status
Simulation time 239963086 ps
CPU time 1.04 seconds
Started Aug 05 05:35:38 PM PDT 24
Finished Aug 05 05:35:39 PM PDT 24
Peak memory 207368 kb
Host smart-054fb4ab-371d-4cef-b182-2e58044d64fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13864
30548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1386430548
Directory /workspace/14.usbdev_in_trans/latest


Test location /workspace/coverage/default/14.usbdev_invalid_sync.76291806
Short name T938
Test name
Test status
Simulation time 3599693915 ps
CPU time 37.02 seconds
Started Aug 05 05:35:43 PM PDT 24
Finished Aug 05 05:36:20 PM PDT 24
Peak memory 223916 kb
Host smart-6d7ff5df-ab1a-4b01-8e87-c109388388ed
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=76291806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.76291806
Directory /workspace/14.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/14.usbdev_link_in_err.472002775
Short name T1123
Test name
Test status
Simulation time 211206931 ps
CPU time 0.92 seconds
Started Aug 05 05:35:38 PM PDT 24
Finished Aug 05 05:35:39 PM PDT 24
Peak memory 207268 kb
Host smart-64834003-7de7-4138-ad43-8e454b268c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47200
2775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.472002775
Directory /workspace/14.usbdev_link_in_err/latest


Test location /workspace/coverage/default/14.usbdev_link_resume.2490135099
Short name T809
Test name
Test status
Simulation time 14280526562 ps
CPU time 19.2 seconds
Started Aug 05 05:35:39 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207584 kb
Host smart-8842bd52-f4c9-451b-8217-808af6644caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24901
35099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2490135099
Directory /workspace/14.usbdev_link_resume/latest


Test location /workspace/coverage/default/14.usbdev_link_suspend.2092095910
Short name T1815
Test name
Test status
Simulation time 4639699317 ps
CPU time 6.47 seconds
Started Aug 05 05:35:40 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 215732 kb
Host smart-286f781c-7938-4a73-a77d-735d413e1302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20920
95910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2092095910
Directory /workspace/14.usbdev_link_suspend/latest


Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.3826849801
Short name T1228
Test name
Test status
Simulation time 2652717072 ps
CPU time 71.22 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:37:03 PM PDT 24
Peak memory 224004 kb
Host smart-cd0d24f8-d913-46a7-ac08-a4938b82e4a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38268
49801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3826849801
Directory /workspace/14.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.324201674
Short name T1984
Test name
Test status
Simulation time 2848131948 ps
CPU time 29.52 seconds
Started Aug 05 05:35:39 PM PDT 24
Finished Aug 05 05:36:08 PM PDT 24
Peak memory 215900 kb
Host smart-88c5977e-4095-4f31-87b0-ed2fc14831e4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=324201674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.324201674
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.4106567524
Short name T691
Test name
Test status
Simulation time 244330940 ps
CPU time 0.98 seconds
Started Aug 05 05:35:37 PM PDT 24
Finished Aug 05 05:35:39 PM PDT 24
Peak memory 207276 kb
Host smart-bde43383-68c8-477a-b497-0f99f5c9f4d9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4106567524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.4106567524
Directory /workspace/14.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.4095264654
Short name T1164
Test name
Test status
Simulation time 194901786 ps
CPU time 0.97 seconds
Started Aug 05 05:35:58 PM PDT 24
Finished Aug 05 05:35:59 PM PDT 24
Peak memory 207260 kb
Host smart-e0071d52-1811-49a6-a324-3fcde87221fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40952
64654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.4095264654
Directory /workspace/14.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.849119406
Short name T1287
Test name
Test status
Simulation time 2143377108 ps
CPU time 61.89 seconds
Started Aug 05 05:35:37 PM PDT 24
Finished Aug 05 05:36:39 PM PDT 24
Peak memory 217328 kb
Host smart-9e34c6dc-f089-4737-a688-5135c5111d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84911
9406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.849119406
Directory /workspace/14.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.2030821724
Short name T2779
Test name
Test status
Simulation time 2570560510 ps
CPU time 28.81 seconds
Started Aug 05 05:35:38 PM PDT 24
Finished Aug 05 05:36:07 PM PDT 24
Peak memory 218560 kb
Host smart-9c3166f0-eb14-4012-8a7a-a110d698f41f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2030821724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.2030821724
Directory /workspace/14.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2563034312
Short name T1404
Test name
Test status
Simulation time 2877656762 ps
CPU time 82.45 seconds
Started Aug 05 05:35:39 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 217512 kb
Host smart-f9074a1e-9bd3-4cae-8f70-6c59cf231dd1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2563034312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2563034312
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.1672398580
Short name T1979
Test name
Test status
Simulation time 167552119 ps
CPU time 0.85 seconds
Started Aug 05 05:35:40 PM PDT 24
Finished Aug 05 05:35:41 PM PDT 24
Peak memory 207272 kb
Host smart-31434b04-31d3-4a6d-aefe-ed1ac6fbb268
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1672398580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.1672398580
Directory /workspace/14.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.239973708
Short name T2956
Test name
Test status
Simulation time 147840558 ps
CPU time 0.85 seconds
Started Aug 05 05:35:41 PM PDT 24
Finished Aug 05 05:35:42 PM PDT 24
Peak memory 207404 kb
Host smart-b7526b07-fe1a-4763-bf77-c96d8ec1d3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23997
3708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.239973708
Directory /workspace/14.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/14.usbdev_out_iso.3651656276
Short name T1332
Test name
Test status
Simulation time 150527326 ps
CPU time 0.84 seconds
Started Aug 05 05:35:39 PM PDT 24
Finished Aug 05 05:35:40 PM PDT 24
Peak memory 207396 kb
Host smart-d8efb898-2fb9-4082-852c-77ba635cc9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36516
56276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3651656276
Directory /workspace/14.usbdev_out_iso/latest


Test location /workspace/coverage/default/14.usbdev_out_stall.4206199537
Short name T1281
Test name
Test status
Simulation time 191853231 ps
CPU time 0.91 seconds
Started Aug 05 05:35:43 PM PDT 24
Finished Aug 05 05:35:44 PM PDT 24
Peak memory 207368 kb
Host smart-d7d30c6f-b5a0-4dcd-a9a7-e27adf7eff97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42061
99537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.4206199537
Directory /workspace/14.usbdev_out_stall/latest


Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2392295439
Short name T2772
Test name
Test status
Simulation time 172168372 ps
CPU time 0.92 seconds
Started Aug 05 05:35:39 PM PDT 24
Finished Aug 05 05:35:40 PM PDT 24
Peak memory 207284 kb
Host smart-74712af3-f306-47f1-b3a1-4e6671904157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23922
95439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2392295439
Directory /workspace/14.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2121565446
Short name T844
Test name
Test status
Simulation time 156471861 ps
CPU time 0.87 seconds
Started Aug 05 05:35:38 PM PDT 24
Finished Aug 05 05:35:39 PM PDT 24
Peak memory 207320 kb
Host smart-876d6e19-d190-437f-bad2-0beed57f7566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21215
65446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2121565446
Directory /workspace/14.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3465534341
Short name T2919
Test name
Test status
Simulation time 240805338 ps
CPU time 1.11 seconds
Started Aug 05 05:35:42 PM PDT 24
Finished Aug 05 05:35:43 PM PDT 24
Peak memory 207296 kb
Host smart-1fc61a7a-a5e3-461d-8f0a-7480e626c1cc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3465534341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3465534341
Directory /workspace/14.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1925627914
Short name T1049
Test name
Test status
Simulation time 152526892 ps
CPU time 0.86 seconds
Started Aug 05 05:35:38 PM PDT 24
Finished Aug 05 05:35:39 PM PDT 24
Peak memory 207308 kb
Host smart-eac7194f-f493-4de0-9fe2-78a5a7207830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19256
27914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1925627914
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2638052033
Short name T2954
Test name
Test status
Simulation time 66119123 ps
CPU time 0.73 seconds
Started Aug 05 05:35:40 PM PDT 24
Finished Aug 05 05:35:40 PM PDT 24
Peak memory 207236 kb
Host smart-3a3e85cd-2cd9-4440-b23d-cd0d6c87624b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26380
52033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2638052033
Directory /workspace/14.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3133937639
Short name T1766
Test name
Test status
Simulation time 8426768556 ps
CPU time 23.01 seconds
Started Aug 05 05:35:43 PM PDT 24
Finished Aug 05 05:36:06 PM PDT 24
Peak memory 215916 kb
Host smart-c638df24-55a6-4787-8e58-c414e12ae6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31339
37639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3133937639
Directory /workspace/14.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/14.usbdev_pkt_received.1611201932
Short name T2426
Test name
Test status
Simulation time 160448377 ps
CPU time 0.85 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207340 kb
Host smart-f406b7dd-1ba5-4bd2-aa52-85f1b334fa7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16112
01932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1611201932
Directory /workspace/14.usbdev_pkt_received/latest


Test location /workspace/coverage/default/14.usbdev_pkt_sent.3599050972
Short name T1523
Test name
Test status
Simulation time 243141415 ps
CPU time 1 seconds
Started Aug 05 05:35:52 PM PDT 24
Finished Aug 05 05:35:53 PM PDT 24
Peak memory 207344 kb
Host smart-9e8d73b4-4713-4519-a06f-21c740d1cf95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35990
50972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3599050972
Directory /workspace/14.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3438368914
Short name T2792
Test name
Test status
Simulation time 231970292 ps
CPU time 1.01 seconds
Started Aug 05 05:35:40 PM PDT 24
Finished Aug 05 05:35:41 PM PDT 24
Peak memory 207316 kb
Host smart-10d54f66-6d86-46e2-bb0e-fa7518e775b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34383
68914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3438368914
Directory /workspace/14.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1828423646
Short name T1580
Test name
Test status
Simulation time 181538031 ps
CPU time 0.89 seconds
Started Aug 05 05:35:38 PM PDT 24
Finished Aug 05 05:35:39 PM PDT 24
Peak memory 207352 kb
Host smart-c2621e71-d563-4c13-92f2-f2f77ef6b9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284
23646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1828423646
Directory /workspace/14.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/14.usbdev_resume_link_active.666014124
Short name T1888
Test name
Test status
Simulation time 20187156585 ps
CPU time 24.86 seconds
Started Aug 05 05:35:39 PM PDT 24
Finished Aug 05 05:36:04 PM PDT 24
Peak memory 207544 kb
Host smart-fc20fc60-4206-4a49-a201-4059aa0723e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66601
4124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.666014124
Directory /workspace/14.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/14.usbdev_rx_crc_err.810238598
Short name T2408
Test name
Test status
Simulation time 168554060 ps
CPU time 0.86 seconds
Started Aug 05 05:35:52 PM PDT 24
Finished Aug 05 05:35:53 PM PDT 24
Peak memory 207308 kb
Host smart-68788b3a-619c-4ed3-a1ed-b3bd7637de08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81023
8598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.810238598
Directory /workspace/14.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/14.usbdev_rx_full.74220326
Short name T54
Test name
Test status
Simulation time 247013352 ps
CPU time 1.16 seconds
Started Aug 05 05:35:42 PM PDT 24
Finished Aug 05 05:35:43 PM PDT 24
Peak memory 207280 kb
Host smart-98411b0c-23a6-49f1-9f0e-3cd6f1e08a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74220
326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.74220326
Directory /workspace/14.usbdev_rx_full/latest


Test location /workspace/coverage/default/14.usbdev_setup_stage.3239094710
Short name T637
Test name
Test status
Simulation time 217075650 ps
CPU time 0.89 seconds
Started Aug 05 05:35:38 PM PDT 24
Finished Aug 05 05:35:39 PM PDT 24
Peak memory 207344 kb
Host smart-6bb59be4-c77e-4946-ae01-a8cc7fe9708d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32390
94710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3239094710
Directory /workspace/14.usbdev_setup_stage/latest


Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2036820240
Short name T1292
Test name
Test status
Simulation time 172278628 ps
CPU time 0.86 seconds
Started Aug 05 05:35:42 PM PDT 24
Finished Aug 05 05:35:42 PM PDT 24
Peak memory 207348 kb
Host smart-b6c02bd9-7ed2-4020-9d9f-962d0ec5b814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20368
20240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2036820240
Directory /workspace/14.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/14.usbdev_smoke.254703726
Short name T445
Test name
Test status
Simulation time 244211094 ps
CPU time 1.06 seconds
Started Aug 05 05:35:42 PM PDT 24
Finished Aug 05 05:35:43 PM PDT 24
Peak memory 207352 kb
Host smart-8d4c3bd0-faec-4e9f-90e5-a8eabe2804d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25470
3726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.254703726
Directory /workspace/14.usbdev_smoke/latest


Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.1897305311
Short name T2435
Test name
Test status
Simulation time 3503012554 ps
CPU time 36.33 seconds
Started Aug 05 05:35:42 PM PDT 24
Finished Aug 05 05:36:19 PM PDT 24
Peak memory 217628 kb
Host smart-0bff48c8-5c91-4e3f-b053-3b357a04e516
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1897305311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.1897305311
Directory /workspace/14.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2594841786
Short name T564
Test name
Test status
Simulation time 171914534 ps
CPU time 0.88 seconds
Started Aug 05 05:35:43 PM PDT 24
Finished Aug 05 05:35:44 PM PDT 24
Peak memory 207300 kb
Host smart-7856e23a-ef66-4db5-8631-73198401a0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25948
41786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2594841786
Directory /workspace/14.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/14.usbdev_stall_trans.3080162747
Short name T2622
Test name
Test status
Simulation time 214036543 ps
CPU time 0.94 seconds
Started Aug 05 05:35:40 PM PDT 24
Finished Aug 05 05:35:41 PM PDT 24
Peak memory 207320 kb
Host smart-9828e64e-d0b9-4f68-a99f-fb6f2efbab72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30801
62747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3080162747
Directory /workspace/14.usbdev_stall_trans/latest


Test location /workspace/coverage/default/14.usbdev_stream_len_max.1028964645
Short name T2093
Test name
Test status
Simulation time 193671103 ps
CPU time 0.97 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207308 kb
Host smart-5a1b0b80-70bc-4633-992f-8b75995446ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10289
64645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.1028964645
Directory /workspace/14.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/14.usbdev_streaming_out.2934190807
Short name T486
Test name
Test status
Simulation time 3548106005 ps
CPU time 35.2 seconds
Started Aug 05 05:35:39 PM PDT 24
Finished Aug 05 05:36:15 PM PDT 24
Peak memory 215748 kb
Host smart-ed834e94-07ae-4aa4-9e84-1dd33c39f7df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29341
90807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2934190807
Directory /workspace/14.usbdev_streaming_out/latest


Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.2497608544
Short name T37
Test name
Test status
Simulation time 1319961819 ps
CPU time 29.75 seconds
Started Aug 05 05:35:38 PM PDT 24
Finished Aug 05 05:36:08 PM PDT 24
Peak memory 207536 kb
Host smart-5a0aba28-1fbb-4519-bb25-934c5f4d8d38
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497608544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.2497608544
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/140.usbdev_endpoint_types.3302980741
Short name T413
Test name
Test status
Simulation time 376433604 ps
CPU time 1.3 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207336 kb
Host smart-2509b322-6fde-4dd0-8b6b-adf0d508af12
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3302980741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.3302980741
Directory /workspace/140.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/141.usbdev_endpoint_types.648163560
Short name T299
Test name
Test status
Simulation time 424265085 ps
CPU time 1.19 seconds
Started Aug 05 05:40:57 PM PDT 24
Finished Aug 05 05:40:58 PM PDT 24
Peak memory 207324 kb
Host smart-fca5ad57-2e63-4e35-9216-a00aece9d243
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=648163560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.648163560
Directory /workspace/141.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/142.usbdev_endpoint_types.383753913
Short name T365
Test name
Test status
Simulation time 234896495 ps
CPU time 1 seconds
Started Aug 05 05:40:53 PM PDT 24
Finished Aug 05 05:40:54 PM PDT 24
Peak memory 207296 kb
Host smart-9d234db0-7416-40c3-8f87-e83104d10f57
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=383753913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.383753913
Directory /workspace/142.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/143.usbdev_endpoint_types.3488960308
Short name T357
Test name
Test status
Simulation time 644401783 ps
CPU time 1.58 seconds
Started Aug 05 05:40:48 PM PDT 24
Finished Aug 05 05:40:49 PM PDT 24
Peak memory 207320 kb
Host smart-f8cc82b9-1d8f-4c54-b14d-344e8f204ccf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3488960308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.3488960308
Directory /workspace/143.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/144.usbdev_endpoint_types.2091077354
Short name T353
Test name
Test status
Simulation time 839865480 ps
CPU time 1.79 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:40:51 PM PDT 24
Peak memory 207324 kb
Host smart-da5afdb9-b9b5-4f20-8164-5e3d1229ce7b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2091077354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.2091077354
Directory /workspace/144.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/145.usbdev_endpoint_types.3674148319
Short name T434
Test name
Test status
Simulation time 274176812 ps
CPU time 1.08 seconds
Started Aug 05 05:40:47 PM PDT 24
Finished Aug 05 05:40:48 PM PDT 24
Peak memory 207348 kb
Host smart-6523c76b-099c-4b30-9f65-3ef11a08169c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3674148319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.3674148319
Directory /workspace/145.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/146.usbdev_endpoint_types.2867749562
Short name T329
Test name
Test status
Simulation time 794866945 ps
CPU time 1.67 seconds
Started Aug 05 05:40:50 PM PDT 24
Finished Aug 05 05:40:52 PM PDT 24
Peak memory 207320 kb
Host smart-3a81c135-ed58-45ee-9a4e-d46357379c9d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2867749562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.2867749562
Directory /workspace/146.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/147.usbdev_endpoint_types.1258346889
Short name T377
Test name
Test status
Simulation time 357483334 ps
CPU time 1.1 seconds
Started Aug 05 05:40:53 PM PDT 24
Finished Aug 05 05:40:54 PM PDT 24
Peak memory 207336 kb
Host smart-b6a1d16c-3234-4a9c-9c26-28073ccaa413
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1258346889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.1258346889
Directory /workspace/147.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/148.usbdev_endpoint_types.1130077567
Short name T3097
Test name
Test status
Simulation time 488676806 ps
CPU time 1.45 seconds
Started Aug 05 05:40:57 PM PDT 24
Finished Aug 05 05:40:59 PM PDT 24
Peak memory 207316 kb
Host smart-adcc1414-68c3-4e8a-8fe7-fae39cf91b56
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1130077567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.1130077567
Directory /workspace/148.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/149.usbdev_endpoint_types.660693990
Short name T2980
Test name
Test status
Simulation time 674181908 ps
CPU time 1.52 seconds
Started Aug 05 05:40:57 PM PDT 24
Finished Aug 05 05:40:59 PM PDT 24
Peak memory 207316 kb
Host smart-9527b777-79e1-499a-b199-11b0a55f1aa9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=660693990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.660693990
Directory /workspace/149.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/15.usbdev_alert_test.3491833421
Short name T1545
Test name
Test status
Simulation time 46837368 ps
CPU time 0.68 seconds
Started Aug 05 05:35:48 PM PDT 24
Finished Aug 05 05:35:48 PM PDT 24
Peak memory 207452 kb
Host smart-1e35effa-6e36-4d23-b852-72cdc928e602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3491833421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3491833421
Directory /workspace/15.usbdev_alert_test/latest


Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3842280625
Short name T1008
Test name
Test status
Simulation time 8937716587 ps
CPU time 12.07 seconds
Started Aug 05 05:35:41 PM PDT 24
Finished Aug 05 05:35:53 PM PDT 24
Peak memory 207528 kb
Host smart-a6be09c1-1e56-446a-a58b-03b69fb663e6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842280625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.3842280625
Directory /workspace/15.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2872463914
Short name T2903
Test name
Test status
Simulation time 16231512213 ps
CPU time 19.79 seconds
Started Aug 05 05:35:41 PM PDT 24
Finished Aug 05 05:36:01 PM PDT 24
Peak memory 215736 kb
Host smart-fd19f16c-4195-4972-8663-c165ca83836d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872463914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2872463914
Directory /workspace/15.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2944437089
Short name T830
Test name
Test status
Simulation time 24027824317 ps
CPU time 29.23 seconds
Started Aug 05 05:35:40 PM PDT 24
Finished Aug 05 05:36:09 PM PDT 24
Peak memory 215880 kb
Host smart-8f0aeadc-4971-4a36-9274-f4772272ebe4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944437089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.2944437089
Directory /workspace/15.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/15.usbdev_av_buffer.80194264
Short name T1889
Test name
Test status
Simulation time 149020359 ps
CPU time 0.88 seconds
Started Aug 05 05:35:47 PM PDT 24
Finished Aug 05 05:35:48 PM PDT 24
Peak memory 207288 kb
Host smart-5080809e-704b-44ff-997d-7921021e123a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80194
264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.80194264
Directory /workspace/15.usbdev_av_buffer/latest


Test location /workspace/coverage/default/15.usbdev_bitstuff_err.1809780287
Short name T1169
Test name
Test status
Simulation time 173658866 ps
CPU time 0.9 seconds
Started Aug 05 05:35:46 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 207336 kb
Host smart-a613f4ed-5ef8-4e25-a7db-c4effaa4ed2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18097
80287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1809780287
Directory /workspace/15.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.2633742055
Short name T2240
Test name
Test status
Simulation time 400399683 ps
CPU time 1.42 seconds
Started Aug 05 05:35:54 PM PDT 24
Finished Aug 05 05:35:55 PM PDT 24
Peak memory 207368 kb
Host smart-fcec7c54-9586-4a59-acd6-43b2af728b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26337
42055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.2633742055
Directory /workspace/15.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.174360565
Short name T1105
Test name
Test status
Simulation time 1261819075 ps
CPU time 3.21 seconds
Started Aug 05 05:35:45 PM PDT 24
Finished Aug 05 05:35:49 PM PDT 24
Peak memory 207508 kb
Host smart-9f4841d7-e7ce-49c2-afb2-68b289ba0c40
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=174360565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.174360565
Directory /workspace/15.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/15.usbdev_device_address.1189167887
Short name T188
Test name
Test status
Simulation time 43124862397 ps
CPU time 67.35 seconds
Started Aug 05 05:35:48 PM PDT 24
Finished Aug 05 05:36:56 PM PDT 24
Peak memory 207552 kb
Host smart-518e787a-f214-4695-b1e7-7a09101b620c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11891
67887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.1189167887
Directory /workspace/15.usbdev_device_address/latest


Test location /workspace/coverage/default/15.usbdev_device_timeout.812226427
Short name T1137
Test name
Test status
Simulation time 2318006000 ps
CPU time 14.39 seconds
Started Aug 05 05:35:47 PM PDT 24
Finished Aug 05 05:36:02 PM PDT 24
Peak memory 207660 kb
Host smart-76825f8f-1294-4dc6-b311-3acb72018b23
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812226427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.812226427
Directory /workspace/15.usbdev_device_timeout/latest


Test location /workspace/coverage/default/15.usbdev_disable_endpoint.1728440117
Short name T1303
Test name
Test status
Simulation time 634817732 ps
CPU time 1.58 seconds
Started Aug 05 05:35:50 PM PDT 24
Finished Aug 05 05:35:51 PM PDT 24
Peak memory 207236 kb
Host smart-97b0accb-e8a9-4169-9530-b53bd5e7939e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17284
40117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.1728440117
Directory /workspace/15.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/15.usbdev_disconnected.2522334793
Short name T70
Test name
Test status
Simulation time 143749973 ps
CPU time 0.83 seconds
Started Aug 05 05:35:45 PM PDT 24
Finished Aug 05 05:35:46 PM PDT 24
Peak memory 207368 kb
Host smart-10c7072c-d794-4fa7-8393-41af4013daf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
34793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2522334793
Directory /workspace/15.usbdev_disconnected/latest


Test location /workspace/coverage/default/15.usbdev_enable.3839196565
Short name T1831
Test name
Test status
Simulation time 36432865 ps
CPU time 0.68 seconds
Started Aug 05 05:35:49 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 207288 kb
Host smart-5ed613e7-dc86-4292-9825-520c0b00156b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38391
96565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3839196565
Directory /workspace/15.usbdev_enable/latest


Test location /workspace/coverage/default/15.usbdev_endpoint_access.1515657476
Short name T1354
Test name
Test status
Simulation time 740174570 ps
CPU time 2.15 seconds
Started Aug 05 05:35:44 PM PDT 24
Finished Aug 05 05:35:46 PM PDT 24
Peak memory 207728 kb
Host smart-e2081dfd-7783-480f-8d6a-17513865dabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15156
57476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1515657476
Directory /workspace/15.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/15.usbdev_endpoint_types.3949198717
Short name T431
Test name
Test status
Simulation time 514423893 ps
CPU time 1.51 seconds
Started Aug 05 05:35:44 PM PDT 24
Finished Aug 05 05:35:46 PM PDT 24
Peak memory 207372 kb
Host smart-8c0d5977-b945-46e8-aeb0-d6b93edd12c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3949198717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.3949198717
Directory /workspace/15.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/15.usbdev_fifo_rst.1809662032
Short name T190
Test name
Test status
Simulation time 166551620 ps
CPU time 1.5 seconds
Started Aug 05 05:35:45 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 207492 kb
Host smart-185020be-5d58-4aea-9285-ca0a17948483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18096
62032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1809662032
Directory /workspace/15.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/15.usbdev_in_iso.107500438
Short name T1743
Test name
Test status
Simulation time 164897895 ps
CPU time 0.89 seconds
Started Aug 05 05:35:49 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 207276 kb
Host smart-e5a0098e-e4d4-48db-b2e3-3a1cf37bdaef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=107500438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.107500438
Directory /workspace/15.usbdev_in_iso/latest


Test location /workspace/coverage/default/15.usbdev_in_stall.382095869
Short name T1896
Test name
Test status
Simulation time 152870411 ps
CPU time 0.85 seconds
Started Aug 05 05:35:49 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 207312 kb
Host smart-9744ebea-39ad-43ae-9cbe-eeebdb611e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38209
5869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.382095869
Directory /workspace/15.usbdev_in_stall/latest


Test location /workspace/coverage/default/15.usbdev_in_trans.1406287775
Short name T1842
Test name
Test status
Simulation time 193991388 ps
CPU time 0.94 seconds
Started Aug 05 05:35:47 PM PDT 24
Finished Aug 05 05:35:48 PM PDT 24
Peak memory 207384 kb
Host smart-5ec4e266-3d12-4365-ac08-41369c4f0c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14062
87775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1406287775
Directory /workspace/15.usbdev_in_trans/latest


Test location /workspace/coverage/default/15.usbdev_invalid_sync.3445195479
Short name T1960
Test name
Test status
Simulation time 3482164423 ps
CPU time 29.84 seconds
Started Aug 05 05:35:45 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 223968 kb
Host smart-93733bdd-2eaa-4786-b5f9-af157a82a5bc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3445195479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3445195479
Directory /workspace/15.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/15.usbdev_iso_retraction.584404158
Short name T1678
Test name
Test status
Simulation time 11399415421 ps
CPU time 72.47 seconds
Started Aug 05 05:35:46 PM PDT 24
Finished Aug 05 05:36:59 PM PDT 24
Peak memory 207584 kb
Host smart-4db7f597-2703-4119-824e-7e8a611850e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=584404158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.584404158
Directory /workspace/15.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/15.usbdev_link_in_err.2525688021
Short name T3034
Test name
Test status
Simulation time 235095876 ps
CPU time 1.03 seconds
Started Aug 05 05:35:46 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 207268 kb
Host smart-78858560-171e-491d-8314-a735cf58d615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25256
88021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2525688021
Directory /workspace/15.usbdev_link_in_err/latest


Test location /workspace/coverage/default/15.usbdev_link_resume.829750715
Short name T606
Test name
Test status
Simulation time 12125598105 ps
CPU time 15.62 seconds
Started Aug 05 05:35:45 PM PDT 24
Finished Aug 05 05:36:01 PM PDT 24
Peak memory 207656 kb
Host smart-70f703e0-9846-4e88-a0a5-c490c14c1005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82975
0715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.829750715
Directory /workspace/15.usbdev_link_resume/latest


Test location /workspace/coverage/default/15.usbdev_link_suspend.889925124
Short name T1405
Test name
Test status
Simulation time 3856785751 ps
CPU time 5.01 seconds
Started Aug 05 05:35:45 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 215808 kb
Host smart-2e0d6c64-44c7-4022-b592-4d50b587ca73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88992
5124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.889925124
Directory /workspace/15.usbdev_link_suspend/latest


Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.116600445
Short name T2887
Test name
Test status
Simulation time 5130547194 ps
CPU time 37.86 seconds
Started Aug 05 05:35:45 PM PDT 24
Finished Aug 05 05:36:23 PM PDT 24
Peak memory 218452 kb
Host smart-2cd3b892-fc19-4901-a211-584ac338c3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11660
0445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.116600445
Directory /workspace/15.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3984962019
Short name T2609
Test name
Test status
Simulation time 3216026104 ps
CPU time 90.87 seconds
Started Aug 05 05:35:46 PM PDT 24
Finished Aug 05 05:37:17 PM PDT 24
Peak memory 217228 kb
Host smart-06f3bfe4-fdf2-4b0b-a94d-3a4d172c4aa7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3984962019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3984962019
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3438751104
Short name T2598
Test name
Test status
Simulation time 251399955 ps
CPU time 1.03 seconds
Started Aug 05 05:35:46 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 207392 kb
Host smart-a5ad7eb1-a5a8-4e3f-9ba3-33a48489eeb9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3438751104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3438751104
Directory /workspace/15.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2541093284
Short name T939
Test name
Test status
Simulation time 191265550 ps
CPU time 0.93 seconds
Started Aug 05 05:35:50 PM PDT 24
Finished Aug 05 05:35:51 PM PDT 24
Peak memory 207348 kb
Host smart-79f2d628-f686-4272-9488-38349920c3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410
93284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2541093284
Directory /workspace/15.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.1828028568
Short name T2483
Test name
Test status
Simulation time 2465436764 ps
CPU time 19.67 seconds
Started Aug 05 05:35:47 PM PDT 24
Finished Aug 05 05:36:06 PM PDT 24
Peak memory 207636 kb
Host smart-de7c3ff4-f2b6-41e9-9edc-7f822b6e69a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18280
28568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.1828028568
Directory /workspace/15.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2689280438
Short name T1394
Test name
Test status
Simulation time 1840289962 ps
CPU time 13.4 seconds
Started Aug 05 05:35:44 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 223944 kb
Host smart-e586bbd2-dfa8-4039-9d15-e1be2fa7883b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2689280438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2689280438
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3098856998
Short name T1399
Test name
Test status
Simulation time 157048902 ps
CPU time 0.9 seconds
Started Aug 05 05:35:44 PM PDT 24
Finished Aug 05 05:35:45 PM PDT 24
Peak memory 207380 kb
Host smart-b230a6b1-72db-46ff-b992-268e2128dfa6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3098856998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3098856998
Directory /workspace/15.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.378517261
Short name T2589
Test name
Test status
Simulation time 150596300 ps
CPU time 0.84 seconds
Started Aug 05 05:35:46 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 207260 kb
Host smart-38da43b9-b41b-4549-a1a7-090b759548cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37851
7261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.378517261
Directory /workspace/15.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/15.usbdev_nak_trans.2147293923
Short name T22
Test name
Test status
Simulation time 170017124 ps
CPU time 0.89 seconds
Started Aug 05 05:35:48 PM PDT 24
Finished Aug 05 05:35:49 PM PDT 24
Peak memory 207288 kb
Host smart-5dd724da-93f5-431c-bbaa-5bf0e7d8e709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21472
93923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2147293923
Directory /workspace/15.usbdev_nak_trans/latest


Test location /workspace/coverage/default/15.usbdev_out_iso.893086256
Short name T2712
Test name
Test status
Simulation time 215696448 ps
CPU time 0.98 seconds
Started Aug 05 05:35:50 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207324 kb
Host smart-bff6a50a-12fb-4393-bf7e-f03ed9ff5953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89308
6256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.893086256
Directory /workspace/15.usbdev_out_iso/latest


Test location /workspace/coverage/default/15.usbdev_out_stall.4151094676
Short name T2674
Test name
Test status
Simulation time 183789820 ps
CPU time 0.92 seconds
Started Aug 05 05:35:54 PM PDT 24
Finished Aug 05 05:35:55 PM PDT 24
Peak memory 207364 kb
Host smart-c4a3aec0-1d96-4e86-afd8-4fa89dfd58bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41510
94676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.4151094676
Directory /workspace/15.usbdev_out_stall/latest


Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1512222203
Short name T1275
Test name
Test status
Simulation time 186394356 ps
CPU time 0.89 seconds
Started Aug 05 05:35:47 PM PDT 24
Finished Aug 05 05:35:48 PM PDT 24
Peak memory 207356 kb
Host smart-fe941c9e-4cb1-4c19-9b75-1d29646be04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15122
22203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1512222203
Directory /workspace/15.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3409189514
Short name T2074
Test name
Test status
Simulation time 166924588 ps
CPU time 0.91 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207372 kb
Host smart-00f89913-567a-4939-befe-8f71054a6709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34091
89514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3409189514
Directory /workspace/15.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.53241929
Short name T531
Test name
Test status
Simulation time 200653756 ps
CPU time 1.04 seconds
Started Aug 05 05:35:43 PM PDT 24
Finished Aug 05 05:35:45 PM PDT 24
Peak memory 207372 kb
Host smart-5e9a1aab-cb3a-4824-ad87-d34cdc8a8566
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=53241929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.53241929
Directory /workspace/15.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.4233260853
Short name T2767
Test name
Test status
Simulation time 171870570 ps
CPU time 0.87 seconds
Started Aug 05 05:35:49 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 207368 kb
Host smart-63f11dd7-0ca7-47bc-884e-4eeac36519ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42332
60853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.4233260853
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2710464090
Short name T2391
Test name
Test status
Simulation time 47148271 ps
CPU time 0.7 seconds
Started Aug 05 05:35:43 PM PDT 24
Finished Aug 05 05:35:44 PM PDT 24
Peak memory 207204 kb
Host smart-6587aa40-dfd4-4c1a-ae9f-18fd652317fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27104
64090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2710464090
Directory /workspace/15.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3168683392
Short name T248
Test name
Test status
Simulation time 18009926056 ps
CPU time 44.96 seconds
Started Aug 05 05:35:46 PM PDT 24
Finished Aug 05 05:36:31 PM PDT 24
Peak memory 215840 kb
Host smart-8620a250-4dc0-4f1c-bb6c-7c4091aa4c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31686
83392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3168683392
Directory /workspace/15.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/15.usbdev_pkt_received.1069111347
Short name T1064
Test name
Test status
Simulation time 231909422 ps
CPU time 0.93 seconds
Started Aug 05 05:35:49 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 207320 kb
Host smart-2514f795-3f52-4d9f-adff-e93de2f9fb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10691
11347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1069111347
Directory /workspace/15.usbdev_pkt_received/latest


Test location /workspace/coverage/default/15.usbdev_pkt_sent.112675584
Short name T2366
Test name
Test status
Simulation time 170211239 ps
CPU time 0.9 seconds
Started Aug 05 05:35:48 PM PDT 24
Finished Aug 05 05:35:49 PM PDT 24
Peak memory 207232 kb
Host smart-76018a37-f6c3-4a46-b7d9-0cbd3ec5e5b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11267
5584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.112675584
Directory /workspace/15.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.596992222
Short name T699
Test name
Test status
Simulation time 197988749 ps
CPU time 0.92 seconds
Started Aug 05 05:35:52 PM PDT 24
Finished Aug 05 05:35:53 PM PDT 24
Peak memory 207340 kb
Host smart-3c158b5b-8f43-422d-a29c-e828a8cb0b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59699
2222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.596992222
Directory /workspace/15.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2257827025
Short name T1616
Test name
Test status
Simulation time 235327668 ps
CPU time 0.97 seconds
Started Aug 05 05:35:45 PM PDT 24
Finished Aug 05 05:35:46 PM PDT 24
Peak memory 207256 kb
Host smart-e21cccb7-d579-4ac3-beed-97938cbe361f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22578
27025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2257827025
Directory /workspace/15.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/15.usbdev_resume_link_active.3358145733
Short name T1977
Test name
Test status
Simulation time 20173132564 ps
CPU time 21.95 seconds
Started Aug 05 05:35:48 PM PDT 24
Finished Aug 05 05:36:10 PM PDT 24
Peak memory 207404 kb
Host smart-e399c780-bf8c-49e9-8478-627a26443541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33581
45733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.3358145733
Directory /workspace/15.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/15.usbdev_rx_crc_err.1333918441
Short name T1002
Test name
Test status
Simulation time 189611728 ps
CPU time 0.9 seconds
Started Aug 05 05:35:45 PM PDT 24
Finished Aug 05 05:35:46 PM PDT 24
Peak memory 207296 kb
Host smart-ea74cc61-add5-4c93-863c-02e6cc373bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13339
18441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1333918441
Directory /workspace/15.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/15.usbdev_rx_full.716433092
Short name T290
Test name
Test status
Simulation time 291440016 ps
CPU time 1.19 seconds
Started Aug 05 05:35:50 PM PDT 24
Finished Aug 05 05:35:51 PM PDT 24
Peak memory 207352 kb
Host smart-44639617-3f18-4d3f-9c4d-b93144ab785e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71643
3092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.716433092
Directory /workspace/15.usbdev_rx_full/latest


Test location /workspace/coverage/default/15.usbdev_setup_stage.1898645376
Short name T2695
Test name
Test status
Simulation time 217294249 ps
CPU time 0.92 seconds
Started Aug 05 05:35:48 PM PDT 24
Finished Aug 05 05:35:49 PM PDT 24
Peak memory 207316 kb
Host smart-cb2b7f2a-dad8-41a8-a496-d076c926d8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18986
45376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.1898645376
Directory /workspace/15.usbdev_setup_stage/latest


Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2944202142
Short name T796
Test name
Test status
Simulation time 149281847 ps
CPU time 0.81 seconds
Started Aug 05 05:35:58 PM PDT 24
Finished Aug 05 05:35:59 PM PDT 24
Peak memory 207340 kb
Host smart-63d0ffae-965d-4783-b4e1-89b950cb77a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29442
02142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2944202142
Directory /workspace/15.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/15.usbdev_smoke.1762902029
Short name T1560
Test name
Test status
Simulation time 213575562 ps
CPU time 1.05 seconds
Started Aug 05 05:35:52 PM PDT 24
Finished Aug 05 05:35:53 PM PDT 24
Peak memory 207332 kb
Host smart-70e41467-b9a3-447e-b98e-dc9e61ff9f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17629
02029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1762902029
Directory /workspace/15.usbdev_smoke/latest


Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.4149777195
Short name T1720
Test name
Test status
Simulation time 2485423528 ps
CPU time 71.34 seconds
Started Aug 05 05:35:45 PM PDT 24
Finished Aug 05 05:36:56 PM PDT 24
Peak memory 223892 kb
Host smart-12116e90-1cbc-4f42-a8ca-9c974b50ec94
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4149777195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.4149777195
Directory /workspace/15.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.967754445
Short name T589
Test name
Test status
Simulation time 171887063 ps
CPU time 0.9 seconds
Started Aug 05 05:35:48 PM PDT 24
Finished Aug 05 05:35:49 PM PDT 24
Peak memory 207352 kb
Host smart-d89d58d3-a52e-43b9-8b37-f80559613684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96775
4445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.967754445
Directory /workspace/15.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/15.usbdev_stall_trans.81342395
Short name T755
Test name
Test status
Simulation time 174168262 ps
CPU time 0.85 seconds
Started Aug 05 05:35:48 PM PDT 24
Finished Aug 05 05:35:49 PM PDT 24
Peak memory 207404 kb
Host smart-0e5c798c-5d9e-42c1-8853-59911fd8b2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81342
395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.81342395
Directory /workspace/15.usbdev_stall_trans/latest


Test location /workspace/coverage/default/15.usbdev_stream_len_max.2085802510
Short name T2592
Test name
Test status
Simulation time 539105160 ps
CPU time 1.6 seconds
Started Aug 05 05:35:48 PM PDT 24
Finished Aug 05 05:35:49 PM PDT 24
Peak memory 207336 kb
Host smart-7d06fdfc-1a91-457a-a7a0-8281b5bb6c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20858
02510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2085802510
Directory /workspace/15.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/15.usbdev_streaming_out.800969794
Short name T1810
Test name
Test status
Simulation time 2628618065 ps
CPU time 25.29 seconds
Started Aug 05 05:35:49 PM PDT 24
Finished Aug 05 05:36:15 PM PDT 24
Peak memory 215808 kb
Host smart-de22c23c-648d-458d-8073-4fffacd7d85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80096
9794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.800969794
Directory /workspace/15.usbdev_streaming_out/latest


Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.282201785
Short name T657
Test name
Test status
Simulation time 867505465 ps
CPU time 5.21 seconds
Started Aug 05 05:35:46 PM PDT 24
Finished Aug 05 05:35:51 PM PDT 24
Peak memory 207736 kb
Host smart-fd8cbefa-f8b2-42fe-b7f8-6187093f331e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282201785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_host
_handshake.282201785
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/150.usbdev_endpoint_types.3808205027
Short name T408
Test name
Test status
Simulation time 390613760 ps
CPU time 1.25 seconds
Started Aug 05 05:40:57 PM PDT 24
Finished Aug 05 05:40:58 PM PDT 24
Peak memory 207316 kb
Host smart-adf6baff-6a7b-4c89-8c8a-0f3e82c3dc6b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3808205027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.3808205027
Directory /workspace/150.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/151.usbdev_endpoint_types.789973727
Short name T219
Test name
Test status
Simulation time 190711653 ps
CPU time 0.89 seconds
Started Aug 05 05:40:28 PM PDT 24
Finished Aug 05 05:40:29 PM PDT 24
Peak memory 207240 kb
Host smart-35556543-95ce-4804-a848-80e01f0cf51f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=789973727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.789973727
Directory /workspace/151.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/152.usbdev_endpoint_types.158263232
Short name T374
Test name
Test status
Simulation time 323540953 ps
CPU time 1.07 seconds
Started Aug 05 05:40:39 PM PDT 24
Finished Aug 05 05:40:40 PM PDT 24
Peak memory 207296 kb
Host smart-b794b517-038a-41ed-8d83-77c646323b15
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=158263232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.158263232
Directory /workspace/152.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/153.usbdev_endpoint_types.4022143106
Short name T323
Test name
Test status
Simulation time 288693481 ps
CPU time 1.06 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:34 PM PDT 24
Peak memory 207324 kb
Host smart-8905e0f1-9b69-412f-90bc-cf2dd91d5f11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4022143106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.4022143106
Directory /workspace/153.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/154.usbdev_endpoint_types.1122589995
Short name T2046
Test name
Test status
Simulation time 272042645 ps
CPU time 0.99 seconds
Started Aug 05 05:40:36 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207200 kb
Host smart-3a6cf2db-5c05-4842-9bb2-e4dade97c21d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1122589995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.1122589995
Directory /workspace/154.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/156.usbdev_endpoint_types.1580461723
Short name T340
Test name
Test status
Simulation time 582718033 ps
CPU time 1.5 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207272 kb
Host smart-1ccb998d-e6bf-4cb0-8f32-7132970dba89
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1580461723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.1580461723
Directory /workspace/156.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/157.usbdev_endpoint_types.3420314586
Short name T89
Test name
Test status
Simulation time 388476995 ps
CPU time 1.19 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:40:50 PM PDT 24
Peak memory 207324 kb
Host smart-3623ba19-c826-4f28-bf26-77db1395b2b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3420314586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.3420314586
Directory /workspace/157.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/158.usbdev_endpoint_types.1610759413
Short name T349
Test name
Test status
Simulation time 364880637 ps
CPU time 1.2 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207216 kb
Host smart-4cc1ae3b-bdd8-4da5-bfec-6a64129f8b0b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1610759413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.1610759413
Directory /workspace/158.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/159.usbdev_endpoint_types.3050738913
Short name T471
Test name
Test status
Simulation time 623424948 ps
CPU time 1.61 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207444 kb
Host smart-4cee0611-0b6a-4a38-ad76-5711d26d8ea3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3050738913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.3050738913
Directory /workspace/159.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/16.usbdev_alert_test.3735192681
Short name T2733
Test name
Test status
Simulation time 33599276 ps
CPU time 0.67 seconds
Started Aug 05 05:35:58 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207508 kb
Host smart-8aa69253-84c1-480c-9363-c23c7bef189e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3735192681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.3735192681
Directory /workspace/16.usbdev_alert_test/latest


Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1962590411
Short name T1444
Test name
Test status
Simulation time 5223281523 ps
CPU time 7.02 seconds
Started Aug 05 05:35:50 PM PDT 24
Finished Aug 05 05:35:57 PM PDT 24
Peak memory 215776 kb
Host smart-1e09a902-3830-45e7-b3f1-e078a0d08494
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962590411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.1962590411
Directory /workspace/16.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2336006169
Short name T2694
Test name
Test status
Simulation time 14166616863 ps
CPU time 20.46 seconds
Started Aug 05 05:35:50 PM PDT 24
Finished Aug 05 05:36:11 PM PDT 24
Peak memory 215808 kb
Host smart-1550c080-e4e6-4651-a9ac-9a050abae2f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336006169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2336006169
Directory /workspace/16.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.1351717229
Short name T3085
Test name
Test status
Simulation time 29648451973 ps
CPU time 35.66 seconds
Started Aug 05 05:35:48 PM PDT 24
Finished Aug 05 05:36:23 PM PDT 24
Peak memory 207556 kb
Host smart-35fa3f3b-9375-48ee-a97f-4a2289035d54
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351717229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.1351717229
Directory /workspace/16.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/16.usbdev_av_buffer.3755219585
Short name T2932
Test name
Test status
Simulation time 163364535 ps
CPU time 0.89 seconds
Started Aug 05 05:35:47 PM PDT 24
Finished Aug 05 05:35:48 PM PDT 24
Peak memory 207416 kb
Host smart-7b21853f-33f5-4727-90a6-8cdf80aba014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37552
19585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3755219585
Directory /workspace/16.usbdev_av_buffer/latest


Test location /workspace/coverage/default/16.usbdev_bitstuff_err.445590876
Short name T788
Test name
Test status
Simulation time 157215880 ps
CPU time 0.85 seconds
Started Aug 05 05:35:46 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 207316 kb
Host smart-5036c4a5-96bb-4869-88a6-074bea63a1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44559
0876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.445590876
Directory /workspace/16.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.835707577
Short name T1524
Test name
Test status
Simulation time 450046617 ps
CPU time 1.62 seconds
Started Aug 05 05:35:46 PM PDT 24
Finished Aug 05 05:35:48 PM PDT 24
Peak memory 207372 kb
Host smart-34d31b97-6c4e-4141-a852-c0e75d530802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83570
7577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.835707577
Directory /workspace/16.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1526565850
Short name T980
Test name
Test status
Simulation time 634597050 ps
CPU time 1.67 seconds
Started Aug 05 05:35:56 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207320 kb
Host smart-a4dbcee0-efc0-4d48-bc73-6c83aaab0a74
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1526565850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1526565850
Directory /workspace/16.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/16.usbdev_device_address.1385130172
Short name T171
Test name
Test status
Simulation time 35923479986 ps
CPU time 61.36 seconds
Started Aug 05 05:35:54 PM PDT 24
Finished Aug 05 05:36:55 PM PDT 24
Peak memory 207692 kb
Host smart-bd2baedd-3a48-4123-95f7-1aa66053f31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13851
30172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.1385130172
Directory /workspace/16.usbdev_device_address/latest


Test location /workspace/coverage/default/16.usbdev_device_timeout.2004382170
Short name T1255
Test name
Test status
Simulation time 4770386597 ps
CPU time 42.17 seconds
Started Aug 05 05:35:52 PM PDT 24
Finished Aug 05 05:36:34 PM PDT 24
Peak memory 207632 kb
Host smart-3c00dc24-e189-4674-9d7b-f91753131972
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004382170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.2004382170
Directory /workspace/16.usbdev_device_timeout/latest


Test location /workspace/coverage/default/16.usbdev_disable_endpoint.2778145590
Short name T819
Test name
Test status
Simulation time 377781154 ps
CPU time 1.34 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207380 kb
Host smart-41175c57-ae5f-4319-97cb-8c6db465bc0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27781
45590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.2778145590
Directory /workspace/16.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/16.usbdev_disconnected.2208539700
Short name T45
Test name
Test status
Simulation time 159057734 ps
CPU time 0.89 seconds
Started Aug 05 05:35:50 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207348 kb
Host smart-d88bf806-4bd4-4958-928c-ea3c48e6a5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22085
39700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2208539700
Directory /workspace/16.usbdev_disconnected/latest


Test location /workspace/coverage/default/16.usbdev_enable.1502824732
Short name T740
Test name
Test status
Simulation time 46071211 ps
CPU time 0.72 seconds
Started Aug 05 05:35:53 PM PDT 24
Finished Aug 05 05:35:54 PM PDT 24
Peak memory 207360 kb
Host smart-3150c978-2460-4c74-94cb-bacda31d9229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15028
24732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1502824732
Directory /workspace/16.usbdev_enable/latest


Test location /workspace/coverage/default/16.usbdev_endpoint_access.1424193436
Short name T1475
Test name
Test status
Simulation time 913893455 ps
CPU time 2.47 seconds
Started Aug 05 05:35:56 PM PDT 24
Finished Aug 05 05:35:59 PM PDT 24
Peak memory 207540 kb
Host smart-ad42314d-69da-4bfd-8b0c-177ed1309257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14241
93436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1424193436
Directory /workspace/16.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/16.usbdev_endpoint_types.3795215454
Short name T423
Test name
Test status
Simulation time 194943565 ps
CPU time 0.9 seconds
Started Aug 05 05:35:49 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 207352 kb
Host smart-baab3c65-f773-44c2-9de5-868023de77f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3795215454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.3795215454
Directory /workspace/16.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/16.usbdev_fifo_rst.498199431
Short name T2313
Test name
Test status
Simulation time 279811187 ps
CPU time 2.39 seconds
Started Aug 05 05:35:53 PM PDT 24
Finished Aug 05 05:35:56 PM PDT 24
Peak memory 207468 kb
Host smart-b4280adc-f751-477b-82c5-8b87e839190d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49819
9431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.498199431
Directory /workspace/16.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/16.usbdev_in_iso.1025961527
Short name T2392
Test name
Test status
Simulation time 215641616 ps
CPU time 1.08 seconds
Started Aug 05 05:35:56 PM PDT 24
Finished Aug 05 05:35:57 PM PDT 24
Peak memory 207524 kb
Host smart-c1436578-91b9-49c9-aa7d-75701b344fe9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1025961527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1025961527
Directory /workspace/16.usbdev_in_iso/latest


Test location /workspace/coverage/default/16.usbdev_in_stall.3785178445
Short name T1481
Test name
Test status
Simulation time 162040358 ps
CPU time 0.86 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207316 kb
Host smart-fb86ef9e-4d4b-43d0-a317-a0d183099487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37851
78445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3785178445
Directory /workspace/16.usbdev_in_stall/latest


Test location /workspace/coverage/default/16.usbdev_in_trans.4255478339
Short name T2273
Test name
Test status
Simulation time 228591598 ps
CPU time 1.01 seconds
Started Aug 05 05:35:54 PM PDT 24
Finished Aug 05 05:35:55 PM PDT 24
Peak memory 207400 kb
Host smart-9cf50dc7-f2fd-4008-a87b-054bcc594d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42554
78339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4255478339
Directory /workspace/16.usbdev_in_trans/latest


Test location /workspace/coverage/default/16.usbdev_iso_retraction.1575286884
Short name T2547
Test name
Test status
Simulation time 3814948795 ps
CPU time 23.7 seconds
Started Aug 05 05:35:52 PM PDT 24
Finished Aug 05 05:36:16 PM PDT 24
Peak memory 207644 kb
Host smart-89751095-a082-456b-a74e-f9b405f51af8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1575286884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.1575286884
Directory /workspace/16.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/16.usbdev_link_in_err.4235248051
Short name T2799
Test name
Test status
Simulation time 172101861 ps
CPU time 0.9 seconds
Started Aug 05 05:35:52 PM PDT 24
Finished Aug 05 05:35:53 PM PDT 24
Peak memory 207396 kb
Host smart-5af86746-d7b5-42c5-90df-3610b47e683e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42352
48051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.4235248051
Directory /workspace/16.usbdev_link_in_err/latest


Test location /workspace/coverage/default/16.usbdev_link_resume.12144035
Short name T2004
Test name
Test status
Simulation time 31707567603 ps
CPU time 50.34 seconds
Started Aug 05 05:35:57 PM PDT 24
Finished Aug 05 05:36:47 PM PDT 24
Peak memory 207596 kb
Host smart-4e868b65-e7da-4568-ac86-cb4e4b9592f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12144
035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.12144035
Directory /workspace/16.usbdev_link_resume/latest


Test location /workspace/coverage/default/16.usbdev_link_suspend.2310335200
Short name T2383
Test name
Test status
Simulation time 11194961057 ps
CPU time 14.02 seconds
Started Aug 05 05:35:53 PM PDT 24
Finished Aug 05 05:36:08 PM PDT 24
Peak memory 207624 kb
Host smart-62315028-4714-4036-9d0c-8a765185814d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23103
35200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2310335200
Directory /workspace/16.usbdev_link_suspend/latest


Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.2255711578
Short name T1640
Test name
Test status
Simulation time 4858370759 ps
CPU time 35.82 seconds
Started Aug 05 05:35:53 PM PDT 24
Finished Aug 05 05:36:29 PM PDT 24
Peak memory 215848 kb
Host smart-bdea3aa6-289b-4a16-8c52-309339d7d5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22557
11578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2255711578
Directory /workspace/16.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1223454272
Short name T178
Test name
Test status
Simulation time 2237560790 ps
CPU time 21.73 seconds
Started Aug 05 05:35:49 PM PDT 24
Finished Aug 05 05:36:11 PM PDT 24
Peak memory 215828 kb
Host smart-a86c1918-6118-4745-b3db-a7b9b3c57728
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1223454272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1223454272
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.59407490
Short name T829
Test name
Test status
Simulation time 247498551 ps
CPU time 1.06 seconds
Started Aug 05 05:35:53 PM PDT 24
Finished Aug 05 05:35:54 PM PDT 24
Peak memory 207360 kb
Host smart-0519b6a4-96a0-432a-963e-e711a81919db
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=59407490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.59407490
Directory /workspace/16.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1237599487
Short name T668
Test name
Test status
Simulation time 224085252 ps
CPU time 0.98 seconds
Started Aug 05 05:35:54 PM PDT 24
Finished Aug 05 05:35:55 PM PDT 24
Peak memory 207320 kb
Host smart-8d7b06a1-9eb4-4a4a-ba9c-8513f06e0210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12375
99487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1237599487
Directory /workspace/16.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.2622763457
Short name T1286
Test name
Test status
Simulation time 2537802942 ps
CPU time 25.86 seconds
Started Aug 05 05:35:54 PM PDT 24
Finished Aug 05 05:36:20 PM PDT 24
Peak memory 215892 kb
Host smart-8e47531a-3628-4bac-8d2f-45eccce1b7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26227
63457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.2622763457
Directory /workspace/16.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3790844272
Short name T1470
Test name
Test status
Simulation time 2276397817 ps
CPU time 64.52 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:36:56 PM PDT 24
Peak memory 215264 kb
Host smart-19bdc1f1-846c-4a9c-b677-b5d1510d484a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3790844272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3790844272
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.1734033561
Short name T735
Test name
Test status
Simulation time 142079381 ps
CPU time 0.86 seconds
Started Aug 05 05:35:57 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207236 kb
Host smart-3d86dfa8-cb60-47a6-92cc-3e8b9e94121a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1734033561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1734033561
Directory /workspace/16.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.470381999
Short name T523
Test name
Test status
Simulation time 145027507 ps
CPU time 0.82 seconds
Started Aug 05 05:35:54 PM PDT 24
Finished Aug 05 05:35:55 PM PDT 24
Peak memory 207376 kb
Host smart-f9dfdb61-f7a9-4139-88f8-4d8d128a76bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47038
1999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.470381999
Directory /workspace/16.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/16.usbdev_out_iso.1467156212
Short name T120
Test name
Test status
Simulation time 150478256 ps
CPU time 0.85 seconds
Started Aug 05 05:35:55 PM PDT 24
Finished Aug 05 05:35:56 PM PDT 24
Peak memory 207316 kb
Host smart-e48a04b6-b428-4ff8-8a40-da926b5268ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14671
56212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1467156212
Directory /workspace/16.usbdev_out_iso/latest


Test location /workspace/coverage/default/16.usbdev_out_stall.2973865128
Short name T2997
Test name
Test status
Simulation time 190777895 ps
CPU time 0.91 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207416 kb
Host smart-8e19f3aa-fb4b-4314-873a-0726d4e474a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29738
65128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2973865128
Directory /workspace/16.usbdev_out_stall/latest


Test location /workspace/coverage/default/16.usbdev_out_trans_nak.4126934481
Short name T2284
Test name
Test status
Simulation time 181981454 ps
CPU time 0.91 seconds
Started Aug 05 05:35:56 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207324 kb
Host smart-8cf6bd66-3e8e-4b94-bc57-2b84c51c436e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41269
34481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.4126934481
Directory /workspace/16.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1018524883
Short name T177
Test name
Test status
Simulation time 169844517 ps
CPU time 0.89 seconds
Started Aug 05 05:35:53 PM PDT 24
Finished Aug 05 05:35:54 PM PDT 24
Peak memory 207396 kb
Host smart-5c159045-8a7e-4db6-8d27-54a73f75cde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10185
24883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1018524883
Directory /workspace/16.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.257187505
Short name T746
Test name
Test status
Simulation time 235577792 ps
CPU time 0.99 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207380 kb
Host smart-5a38421d-9863-442f-a846-84400689593b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=257187505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.257187505
Directory /workspace/16.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1533169223
Short name T2430
Test name
Test status
Simulation time 141009077 ps
CPU time 0.81 seconds
Started Aug 05 05:35:54 PM PDT 24
Finished Aug 05 05:35:55 PM PDT 24
Peak memory 206692 kb
Host smart-f1cd143c-7520-4173-857f-3a0a97469f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15331
69223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1533169223
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2169105843
Short name T2399
Test name
Test status
Simulation time 39110829 ps
CPU time 0.7 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 207304 kb
Host smart-cdfde77e-abd6-4073-8fb2-300d7ab46541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21691
05843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2169105843
Directory /workspace/16.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1644097206
Short name T2233
Test name
Test status
Simulation time 12059362097 ps
CPU time 31.49 seconds
Started Aug 05 05:35:50 PM PDT 24
Finished Aug 05 05:36:22 PM PDT 24
Peak memory 220504 kb
Host smart-34a1f23f-568d-435d-a271-ede30e6648dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16440
97206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1644097206
Directory /workspace/16.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/16.usbdev_pkt_received.1061202652
Short name T560
Test name
Test status
Simulation time 186254297 ps
CPU time 0.89 seconds
Started Aug 05 05:35:52 PM PDT 24
Finished Aug 05 05:35:53 PM PDT 24
Peak memory 207328 kb
Host smart-27724275-e421-4266-998b-c62e1f522a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10612
02652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1061202652
Directory /workspace/16.usbdev_pkt_received/latest


Test location /workspace/coverage/default/16.usbdev_pkt_sent.3338457594
Short name T2175
Test name
Test status
Simulation time 218259500 ps
CPU time 1 seconds
Started Aug 05 05:35:57 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207268 kb
Host smart-2c4c23c3-8e3e-488b-970e-b338420fe669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33384
57594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3338457594
Directory /workspace/16.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.4200633774
Short name T1811
Test name
Test status
Simulation time 288795169 ps
CPU time 1.05 seconds
Started Aug 05 05:35:58 PM PDT 24
Finished Aug 05 05:35:59 PM PDT 24
Peak memory 207320 kb
Host smart-abf0f870-2c4f-4668-b378-9e26295e11d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42006
33774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.4200633774
Directory /workspace/16.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.2102632666
Short name T1387
Test name
Test status
Simulation time 219776032 ps
CPU time 0.95 seconds
Started Aug 05 05:35:58 PM PDT 24
Finished Aug 05 05:35:59 PM PDT 24
Peak memory 207400 kb
Host smart-aab93af3-77b8-4545-826b-6e41bc554719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21026
32666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.2102632666
Directory /workspace/16.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/16.usbdev_resume_link_active.2414221777
Short name T858
Test name
Test status
Simulation time 20170105003 ps
CPU time 24.58 seconds
Started Aug 05 05:36:02 PM PDT 24
Finished Aug 05 05:36:27 PM PDT 24
Peak memory 207372 kb
Host smart-cb1f1f4d-135d-47c6-8c3f-55087a8657b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24142
21777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.2414221777
Directory /workspace/16.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/16.usbdev_rx_crc_err.4103691249
Short name T2355
Test name
Test status
Simulation time 190674250 ps
CPU time 0.9 seconds
Started Aug 05 05:35:57 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207348 kb
Host smart-6af4567a-8195-486b-86d3-81858f594864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41036
91249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.4103691249
Directory /workspace/16.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/16.usbdev_rx_full.2411233090
Short name T2495
Test name
Test status
Simulation time 251905814 ps
CPU time 1.06 seconds
Started Aug 05 05:36:01 PM PDT 24
Finished Aug 05 05:36:02 PM PDT 24
Peak memory 207372 kb
Host smart-1144b9fa-eb0b-4201-8e7f-94b434d88a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24112
33090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.2411233090
Directory /workspace/16.usbdev_rx_full/latest


Test location /workspace/coverage/default/16.usbdev_setup_stage.1261437247
Short name T2635
Test name
Test status
Simulation time 142308776 ps
CPU time 0.86 seconds
Started Aug 05 05:36:02 PM PDT 24
Finished Aug 05 05:36:03 PM PDT 24
Peak memory 207252 kb
Host smart-6855fd44-cb3b-43e9-8667-cd90a988ec1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12614
37247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1261437247
Directory /workspace/16.usbdev_setup_stage/latest


Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1271973813
Short name T1179
Test name
Test status
Simulation time 164215370 ps
CPU time 0.86 seconds
Started Aug 05 05:36:00 PM PDT 24
Finished Aug 05 05:36:01 PM PDT 24
Peak memory 207324 kb
Host smart-e28a3080-315d-4240-9c9d-fdd69df00156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12719
73813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1271973813
Directory /workspace/16.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/16.usbdev_smoke.2550186178
Short name T2301
Test name
Test status
Simulation time 213911316 ps
CPU time 1.05 seconds
Started Aug 05 05:35:57 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207348 kb
Host smart-01c0a2f6-f6bc-4354-afa7-58298a3f4fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25501
86178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2550186178
Directory /workspace/16.usbdev_smoke/latest


Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.1331904507
Short name T2228
Test name
Test status
Simulation time 2524053791 ps
CPU time 26.45 seconds
Started Aug 05 05:35:59 PM PDT 24
Finished Aug 05 05:36:26 PM PDT 24
Peak memory 223960 kb
Host smart-4be23952-ba53-4bcb-aab1-760fef0bcb03
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1331904507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.1331904507
Directory /workspace/16.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.4180197122
Short name T1153
Test name
Test status
Simulation time 186045911 ps
CPU time 0.91 seconds
Started Aug 05 05:35:58 PM PDT 24
Finished Aug 05 05:35:59 PM PDT 24
Peak memory 207608 kb
Host smart-bec3d1bb-5ce3-4f17-b4c6-608ad1924b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41801
97122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.4180197122
Directory /workspace/16.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/16.usbdev_stall_trans.1196497494
Short name T1866
Test name
Test status
Simulation time 185132473 ps
CPU time 0.92 seconds
Started Aug 05 05:35:57 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207248 kb
Host smart-4bb83ca0-a706-469b-8f5f-15b8b8c40388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11964
97494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1196497494
Directory /workspace/16.usbdev_stall_trans/latest


Test location /workspace/coverage/default/16.usbdev_stream_len_max.582723494
Short name T2412
Test name
Test status
Simulation time 201815228 ps
CPU time 0.9 seconds
Started Aug 05 05:36:01 PM PDT 24
Finished Aug 05 05:36:02 PM PDT 24
Peak memory 207360 kb
Host smart-8ce4252c-17dd-432c-b470-f464c04ade3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58272
3494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.582723494
Directory /workspace/16.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/16.usbdev_streaming_out.224019974
Short name T1120
Test name
Test status
Simulation time 1572039787 ps
CPU time 43.32 seconds
Started Aug 05 05:36:02 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 217252 kb
Host smart-a64176f8-9ec7-4e4f-9587-c18eed088707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22401
9974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.224019974
Directory /workspace/16.usbdev_streaming_out/latest


Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.813184062
Short name T558
Test name
Test status
Simulation time 1536987340 ps
CPU time 10.12 seconds
Started Aug 05 05:35:51 PM PDT 24
Finished Aug 05 05:36:01 PM PDT 24
Peak memory 207596 kb
Host smart-90ab94d5-7104-4603-a838-df74db7e6758
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813184062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_host
_handshake.813184062
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/160.usbdev_endpoint_types.759917744
Short name T1778
Test name
Test status
Simulation time 380038006 ps
CPU time 1.28 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207288 kb
Host smart-61b28626-475d-48b0-b6d3-a7ddb3b446f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=759917744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.759917744
Directory /workspace/160.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/161.usbdev_endpoint_types.309447428
Short name T2572
Test name
Test status
Simulation time 161851270 ps
CPU time 0.93 seconds
Started Aug 05 05:40:36 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207352 kb
Host smart-88bef99a-777f-4116-836c-b773bd32458f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=309447428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.309447428
Directory /workspace/161.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/162.usbdev_endpoint_types.2582266308
Short name T346
Test name
Test status
Simulation time 659813475 ps
CPU time 1.54 seconds
Started Aug 05 05:40:46 PM PDT 24
Finished Aug 05 05:40:47 PM PDT 24
Peak memory 207344 kb
Host smart-e51ff172-7dd0-404d-a226-0317ca07b90f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2582266308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.2582266308
Directory /workspace/162.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/163.usbdev_endpoint_types.3318802608
Short name T3064
Test name
Test status
Simulation time 269123162 ps
CPU time 0.97 seconds
Started Aug 05 05:40:47 PM PDT 24
Finished Aug 05 05:40:48 PM PDT 24
Peak memory 207240 kb
Host smart-17e2326f-a855-4b68-af87-c003b3b21724
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3318802608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.3318802608
Directory /workspace/163.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/164.usbdev_endpoint_types.1081344332
Short name T427
Test name
Test status
Simulation time 446783582 ps
CPU time 1.38 seconds
Started Aug 05 05:40:57 PM PDT 24
Finished Aug 05 05:40:58 PM PDT 24
Peak memory 207204 kb
Host smart-0da2631e-7791-430b-b4b9-73240d516e68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1081344332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.1081344332
Directory /workspace/164.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/166.usbdev_endpoint_types.4175575414
Short name T454
Test name
Test status
Simulation time 442679697 ps
CPU time 1.31 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207556 kb
Host smart-20966c57-4721-4c2b-8278-98476a856ba7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4175575414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.4175575414
Directory /workspace/166.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/167.usbdev_endpoint_types.54605273
Short name T1863
Test name
Test status
Simulation time 139526195 ps
CPU time 0.85 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:34 PM PDT 24
Peak memory 207316 kb
Host smart-1906caec-df93-4e54-91f5-a7182c5a6baf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=54605273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.54605273
Directory /workspace/167.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/168.usbdev_endpoint_types.3615781545
Short name T459
Test name
Test status
Simulation time 382091608 ps
CPU time 1.2 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207224 kb
Host smart-32f9dd67-992d-4543-9df2-79935bcbdd92
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3615781545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.3615781545
Directory /workspace/168.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/17.usbdev_alert_test.4274679337
Short name T1623
Test name
Test status
Simulation time 64117628 ps
CPU time 0.69 seconds
Started Aug 05 05:36:10 PM PDT 24
Finished Aug 05 05:36:10 PM PDT 24
Peak memory 207416 kb
Host smart-323070a8-398b-427b-986d-3b1adf5bd6a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4274679337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.4274679337
Directory /workspace/17.usbdev_alert_test/latest


Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1219318673
Short name T1725
Test name
Test status
Simulation time 9407434705 ps
CPU time 11.85 seconds
Started Aug 05 05:35:59 PM PDT 24
Finished Aug 05 05:36:11 PM PDT 24
Peak memory 207672 kb
Host smart-99da8d04-c8d7-4d52-ba76-33d34f1f43d9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219318673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.1219318673
Directory /workspace/17.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1239846873
Short name T1217
Test name
Test status
Simulation time 16091070289 ps
CPU time 18.01 seconds
Started Aug 05 05:36:02 PM PDT 24
Finished Aug 05 05:36:20 PM PDT 24
Peak memory 215820 kb
Host smart-159fc3e6-f496-4cbc-a8ec-da5e0ba34fbe
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239846873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1239846873
Directory /workspace/17.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2597983321
Short name T9
Test name
Test status
Simulation time 31216834280 ps
CPU time 39.9 seconds
Started Aug 05 05:36:00 PM PDT 24
Finished Aug 05 05:36:40 PM PDT 24
Peak memory 207604 kb
Host smart-43a8e2f3-1b47-4d7f-bd12-ef21cd342594
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597983321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.2597983321
Directory /workspace/17.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/17.usbdev_av_buffer.3818783927
Short name T1652
Test name
Test status
Simulation time 199687413 ps
CPU time 0.92 seconds
Started Aug 05 05:36:00 PM PDT 24
Finished Aug 05 05:36:01 PM PDT 24
Peak memory 207368 kb
Host smart-63c52deb-fc27-4911-a35f-56fb28a424d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38187
83927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3818783927
Directory /workspace/17.usbdev_av_buffer/latest


Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1039458995
Short name T2859
Test name
Test status
Simulation time 148566177 ps
CPU time 0.82 seconds
Started Aug 05 05:36:00 PM PDT 24
Finished Aug 05 05:36:01 PM PDT 24
Peak memory 207320 kb
Host smart-f2f6b867-f592-46d0-8069-54d04f35eadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10394
58995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1039458995
Directory /workspace/17.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2161865906
Short name T2315
Test name
Test status
Simulation time 212862517 ps
CPU time 1.1 seconds
Started Aug 05 05:35:56 PM PDT 24
Finished Aug 05 05:35:57 PM PDT 24
Peak memory 207244 kb
Host smart-414fcf9f-0252-4010-ad65-cb0c9f054c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21618
65906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2161865906
Directory /workspace/17.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.3335763724
Short name T2972
Test name
Test status
Simulation time 543569062 ps
CPU time 1.55 seconds
Started Aug 05 05:36:00 PM PDT 24
Finished Aug 05 05:36:02 PM PDT 24
Peak memory 207352 kb
Host smart-2c032e9a-e3a6-44d0-b8e9-c00d30e26d2c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3335763724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.3335763724
Directory /workspace/17.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/17.usbdev_device_timeout.1986967480
Short name T2936
Test name
Test status
Simulation time 198034697 ps
CPU time 0.92 seconds
Started Aug 05 05:35:59 PM PDT 24
Finished Aug 05 05:36:00 PM PDT 24
Peak memory 207368 kb
Host smart-62a0a551-559d-4928-a32d-175687fceee4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986967480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.1986967480
Directory /workspace/17.usbdev_device_timeout/latest


Test location /workspace/coverage/default/17.usbdev_disable_endpoint.467359108
Short name T741
Test name
Test status
Simulation time 502080107 ps
CPU time 1.53 seconds
Started Aug 05 05:35:58 PM PDT 24
Finished Aug 05 05:36:00 PM PDT 24
Peak memory 207340 kb
Host smart-988dae84-0d35-48d1-9392-f102696a0117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46735
9108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.467359108
Directory /workspace/17.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/17.usbdev_disconnected.1970747805
Short name T916
Test name
Test status
Simulation time 142828464 ps
CPU time 0.84 seconds
Started Aug 05 05:36:02 PM PDT 24
Finished Aug 05 05:36:03 PM PDT 24
Peak memory 207320 kb
Host smart-8279825c-8535-44ce-a8b4-3fe282ab756b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19707
47805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1970747805
Directory /workspace/17.usbdev_disconnected/latest


Test location /workspace/coverage/default/17.usbdev_enable.991434910
Short name T1873
Test name
Test status
Simulation time 38196629 ps
CPU time 0.73 seconds
Started Aug 05 05:35:59 PM PDT 24
Finished Aug 05 05:36:00 PM PDT 24
Peak memory 207232 kb
Host smart-c6ffddf9-3d3a-4042-b3b4-2dfd33332613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99143
4910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.991434910
Directory /workspace/17.usbdev_enable/latest


Test location /workspace/coverage/default/17.usbdev_endpoint_access.634775584
Short name T2487
Test name
Test status
Simulation time 875668758 ps
CPU time 2.65 seconds
Started Aug 05 05:36:02 PM PDT 24
Finished Aug 05 05:36:05 PM PDT 24
Peak memory 207512 kb
Host smart-c4d33349-273c-46eb-b92d-daeec389afca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63477
5584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.634775584
Directory /workspace/17.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/17.usbdev_endpoint_types.29558912
Short name T1772
Test name
Test status
Simulation time 577571201 ps
CPU time 1.46 seconds
Started Aug 05 05:35:59 PM PDT 24
Finished Aug 05 05:36:00 PM PDT 24
Peak memory 207352 kb
Host smart-3bf2833a-c0d0-469b-88a3-ab1b95a66d20
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=29558912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.29558912
Directory /workspace/17.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/17.usbdev_fifo_rst.4073164366
Short name T2813
Test name
Test status
Simulation time 191396165 ps
CPU time 1.84 seconds
Started Aug 05 05:35:56 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207556 kb
Host smart-bf0589ee-0fae-4060-a35e-cd1b963efe22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40731
64366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.4073164366
Directory /workspace/17.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/17.usbdev_in_iso.813045434
Short name T495
Test name
Test status
Simulation time 287895485 ps
CPU time 1.18 seconds
Started Aug 05 05:36:03 PM PDT 24
Finished Aug 05 05:36:04 PM PDT 24
Peak memory 215740 kb
Host smart-b831d098-dfbf-4fed-95f0-1078606ff1fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=813045434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.813045434
Directory /workspace/17.usbdev_in_iso/latest


Test location /workspace/coverage/default/17.usbdev_in_stall.3435437618
Short name T1187
Test name
Test status
Simulation time 151989299 ps
CPU time 0.87 seconds
Started Aug 05 05:35:59 PM PDT 24
Finished Aug 05 05:36:00 PM PDT 24
Peak memory 207364 kb
Host smart-4d54d207-a84d-46a7-bd08-09e0f7fba4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34354
37618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3435437618
Directory /workspace/17.usbdev_in_stall/latest


Test location /workspace/coverage/default/17.usbdev_in_trans.2669941767
Short name T799
Test name
Test status
Simulation time 196544871 ps
CPU time 0.96 seconds
Started Aug 05 05:36:01 PM PDT 24
Finished Aug 05 05:36:02 PM PDT 24
Peak memory 207328 kb
Host smart-9d719a61-8d3a-4f73-870d-b196a1d2cd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26699
41767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2669941767
Directory /workspace/17.usbdev_in_trans/latest


Test location /workspace/coverage/default/17.usbdev_invalid_sync.3134131565
Short name T652
Test name
Test status
Simulation time 5015406031 ps
CPU time 50.58 seconds
Started Aug 05 05:36:00 PM PDT 24
Finished Aug 05 05:36:51 PM PDT 24
Peak memory 217756 kb
Host smart-cbdf79da-5eb9-4332-a46d-941125d12ea4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3134131565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.3134131565
Directory /workspace/17.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/17.usbdev_iso_retraction.4223095764
Short name T2691
Test name
Test status
Simulation time 10178175841 ps
CPU time 138.56 seconds
Started Aug 05 05:35:58 PM PDT 24
Finished Aug 05 05:38:16 PM PDT 24
Peak memory 207620 kb
Host smart-f4ac3fd3-6c81-4e27-9494-e0d557da023c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4223095764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.4223095764
Directory /workspace/17.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/17.usbdev_link_in_err.1684938230
Short name T2055
Test name
Test status
Simulation time 195257281 ps
CPU time 0.89 seconds
Started Aug 05 05:35:58 PM PDT 24
Finished Aug 05 05:35:59 PM PDT 24
Peak memory 207268 kb
Host smart-63757655-029d-4e2a-8fa5-e8b2915f1bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16849
38230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.1684938230
Directory /workspace/17.usbdev_link_in_err/latest


Test location /workspace/coverage/default/17.usbdev_link_resume.2062810590
Short name T1966
Test name
Test status
Simulation time 26551161998 ps
CPU time 42.26 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:47 PM PDT 24
Peak memory 215892 kb
Host smart-7781e3ba-6934-4f5a-bbac-1057e20f1b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20628
10590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2062810590
Directory /workspace/17.usbdev_link_resume/latest


Test location /workspace/coverage/default/17.usbdev_link_suspend.2050118925
Short name T483
Test name
Test status
Simulation time 11337905024 ps
CPU time 13.72 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:19 PM PDT 24
Peak memory 207648 kb
Host smart-0c17bda2-e127-4c69-81d6-f96e5fd6ebbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20501
18925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2050118925
Directory /workspace/17.usbdev_link_suspend/latest


Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.2983849765
Short name T2545
Test name
Test status
Simulation time 5072604020 ps
CPU time 38.96 seconds
Started Aug 05 05:36:07 PM PDT 24
Finished Aug 05 05:36:46 PM PDT 24
Peak memory 218380 kb
Host smart-1dde2378-0973-4afa-a934-e6e9f81aee97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29838
49765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.2983849765
Directory /workspace/17.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.3629267320
Short name T726
Test name
Test status
Simulation time 2236341300 ps
CPU time 23.64 seconds
Started Aug 05 05:36:09 PM PDT 24
Finished Aug 05 05:36:33 PM PDT 24
Peak memory 217172 kb
Host smart-e12bcec9-fb42-4dde-8621-0821d2be08f0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3629267320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.3629267320
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.5645567
Short name T867
Test name
Test status
Simulation time 287854738 ps
CPU time 1.01 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:06 PM PDT 24
Peak memory 207376 kb
Host smart-7035e045-1cc9-42b6-845e-9ab2c97596e9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=5645567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.5645567
Directory /workspace/17.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2588165895
Short name T2357
Test name
Test status
Simulation time 191931882 ps
CPU time 0.97 seconds
Started Aug 05 05:36:06 PM PDT 24
Finished Aug 05 05:36:07 PM PDT 24
Peak memory 207288 kb
Host smart-fa54d1dd-d116-4b3f-a6ac-34eda7ce083e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25881
65895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2588165895
Directory /workspace/17.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.3587907148
Short name T187
Test name
Test status
Simulation time 2628582808 ps
CPU time 25.71 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:31 PM PDT 24
Peak memory 217940 kb
Host smart-a8c61c27-f370-4df4-8637-45e9354878f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35879
07148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.3587907148
Directory /workspace/17.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3160014418
Short name T515
Test name
Test status
Simulation time 2486845775 ps
CPU time 71.69 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:37:16 PM PDT 24
Peak memory 217120 kb
Host smart-c6016781-6123-4506-a924-3e4bd01b9bb3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3160014418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3160014418
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.3153968418
Short name T2768
Test name
Test status
Simulation time 151002781 ps
CPU time 0.9 seconds
Started Aug 05 05:36:08 PM PDT 24
Finished Aug 05 05:36:09 PM PDT 24
Peak memory 207360 kb
Host smart-0bcf9d32-6666-4be4-9b86-7306c3ea7ce4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3153968418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3153968418
Directory /workspace/17.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1088032640
Short name T2583
Test name
Test status
Simulation time 194859594 ps
CPU time 0.91 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:06 PM PDT 24
Peak memory 207376 kb
Host smart-bb825e22-53a5-4562-b8f3-9b54e450859e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10880
32640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1088032640
Directory /workspace/17.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/17.usbdev_out_iso.184978199
Short name T99
Test name
Test status
Simulation time 176389251 ps
CPU time 0.93 seconds
Started Aug 05 05:36:06 PM PDT 24
Finished Aug 05 05:36:07 PM PDT 24
Peak memory 207228 kb
Host smart-0220192a-50c9-43a8-812f-6a1bf5f28576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18497
8199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.184978199
Directory /workspace/17.usbdev_out_iso/latest


Test location /workspace/coverage/default/17.usbdev_out_stall.2450404700
Short name T1806
Test name
Test status
Simulation time 190444860 ps
CPU time 0.93 seconds
Started Aug 05 05:36:08 PM PDT 24
Finished Aug 05 05:36:09 PM PDT 24
Peak memory 207348 kb
Host smart-46e8586b-ab5f-4194-a56e-dfe15ac2a2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24504
04700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2450404700
Directory /workspace/17.usbdev_out_stall/latest


Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1983245526
Short name T640
Test name
Test status
Simulation time 175248053 ps
CPU time 0.88 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:06 PM PDT 24
Peak memory 207356 kb
Host smart-729562e0-3d8f-4313-a48e-e8bdf480a01a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19832
45526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1983245526
Directory /workspace/17.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2511894873
Short name T759
Test name
Test status
Simulation time 158933865 ps
CPU time 0.85 seconds
Started Aug 05 05:36:04 PM PDT 24
Finished Aug 05 05:36:05 PM PDT 24
Peak memory 207396 kb
Host smart-2f3c4acf-bd32-4e32-a3fb-8fdf4e18d2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25118
94873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2511894873
Directory /workspace/17.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.909076315
Short name T2375
Test name
Test status
Simulation time 235886445 ps
CPU time 1.09 seconds
Started Aug 05 05:36:04 PM PDT 24
Finished Aug 05 05:36:05 PM PDT 24
Peak memory 207276 kb
Host smart-b88dc385-faab-409c-a988-2ab5bccb3185
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=909076315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.909076315
Directory /workspace/17.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.897493650
Short name T1618
Test name
Test status
Simulation time 158077318 ps
CPU time 0.83 seconds
Started Aug 05 05:36:06 PM PDT 24
Finished Aug 05 05:36:07 PM PDT 24
Peak memory 207368 kb
Host smart-731b8675-3191-4089-b16f-536b6b5af5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89749
3650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.897493650
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3938572852
Short name T2697
Test name
Test status
Simulation time 33225208 ps
CPU time 0.72 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:06 PM PDT 24
Peak memory 207276 kb
Host smart-74bdd036-a759-4a8c-907f-6c732b9a6203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39385
72852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3938572852
Directory /workspace/17.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3066551149
Short name T242
Test name
Test status
Simulation time 15781635440 ps
CPU time 38.56 seconds
Started Aug 05 05:36:04 PM PDT 24
Finished Aug 05 05:36:43 PM PDT 24
Peak memory 215880 kb
Host smart-119f8e97-14bf-479b-88d1-956bd429b18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30665
51149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3066551149
Directory /workspace/17.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/17.usbdev_pkt_received.1780683748
Short name T3039
Test name
Test status
Simulation time 162813344 ps
CPU time 0.85 seconds
Started Aug 05 05:36:06 PM PDT 24
Finished Aug 05 05:36:07 PM PDT 24
Peak memory 207228 kb
Host smart-fda57759-8df3-424b-82c2-4fbed57978c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17806
83748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1780683748
Directory /workspace/17.usbdev_pkt_received/latest


Test location /workspace/coverage/default/17.usbdev_pkt_sent.2199149779
Short name T2290
Test name
Test status
Simulation time 206315010 ps
CPU time 0.96 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:06 PM PDT 24
Peak memory 207324 kb
Host smart-b1a3dd79-0a59-47e3-bfa2-032df89e39d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21991
49779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2199149779
Directory /workspace/17.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.3780675281
Short name T1846
Test name
Test status
Simulation time 228688791 ps
CPU time 1.02 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:06 PM PDT 24
Peak memory 207256 kb
Host smart-30ebbbc4-0e7d-4062-a46f-22dfed5ce835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37806
75281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.3780675281
Directory /workspace/17.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.2717290887
Short name T1467
Test name
Test status
Simulation time 165226232 ps
CPU time 0.96 seconds
Started Aug 05 05:36:09 PM PDT 24
Finished Aug 05 05:36:10 PM PDT 24
Peak memory 207340 kb
Host smart-a63ecb90-18f6-476a-b797-a27cd16331a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27172
90887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2717290887
Directory /workspace/17.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/17.usbdev_resume_link_active.1287762780
Short name T2069
Test name
Test status
Simulation time 20175184974 ps
CPU time 21.69 seconds
Started Aug 05 05:36:06 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207452 kb
Host smart-d97f1c4a-bcf7-403d-b68b-cafa986caf96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12877
62780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.1287762780
Directory /workspace/17.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1740276056
Short name T2704
Test name
Test status
Simulation time 153811890 ps
CPU time 0.91 seconds
Started Aug 05 05:36:09 PM PDT 24
Finished Aug 05 05:36:10 PM PDT 24
Peak memory 207468 kb
Host smart-f06c686b-743f-40d8-96f3-0ca4a498573f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17402
76056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1740276056
Directory /workspace/17.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/17.usbdev_rx_full.293636437
Short name T1826
Test name
Test status
Simulation time 343821190 ps
CPU time 1.17 seconds
Started Aug 05 05:36:06 PM PDT 24
Finished Aug 05 05:36:08 PM PDT 24
Peak memory 207368 kb
Host smart-a92db7dd-65f8-454a-8134-4e8596131b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29363
6437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.293636437
Directory /workspace/17.usbdev_rx_full/latest


Test location /workspace/coverage/default/17.usbdev_setup_stage.4256074259
Short name T1321
Test name
Test status
Simulation time 175773849 ps
CPU time 0.87 seconds
Started Aug 05 05:36:10 PM PDT 24
Finished Aug 05 05:36:11 PM PDT 24
Peak memory 207292 kb
Host smart-acb6150e-c4b7-4324-8117-d9ee5f40a8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42560
74259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.4256074259
Directory /workspace/17.usbdev_setup_stage/latest


Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1212091514
Short name T1765
Test name
Test status
Simulation time 150435910 ps
CPU time 0.83 seconds
Started Aug 05 05:36:04 PM PDT 24
Finished Aug 05 05:36:05 PM PDT 24
Peak memory 207320 kb
Host smart-436daab3-6837-4716-9ae8-f13b7b3b8f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12120
91514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1212091514
Directory /workspace/17.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/17.usbdev_smoke.1200266082
Short name T1770
Test name
Test status
Simulation time 186837520 ps
CPU time 1.02 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:06 PM PDT 24
Peak memory 207268 kb
Host smart-fcfbfc10-6175-48e9-95c6-533fd499caf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12002
66082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1200266082
Directory /workspace/17.usbdev_smoke/latest


Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2278392994
Short name T2155
Test name
Test status
Simulation time 2974798856 ps
CPU time 30.07 seconds
Started Aug 05 05:36:06 PM PDT 24
Finished Aug 05 05:36:37 PM PDT 24
Peak memory 224040 kb
Host smart-4f0ff81d-f30a-4ccc-b2fb-b69b07f8777f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2278392994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2278392994
Directory /workspace/17.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2400811859
Short name T1397
Test name
Test status
Simulation time 185537455 ps
CPU time 0.91 seconds
Started Aug 05 05:36:07 PM PDT 24
Finished Aug 05 05:36:08 PM PDT 24
Peak memory 207356 kb
Host smart-cf4f818c-17b6-4d51-8122-a60f2794f753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24008
11859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2400811859
Directory /workspace/17.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/17.usbdev_stall_trans.3531241912
Short name T2507
Test name
Test status
Simulation time 176214553 ps
CPU time 0.91 seconds
Started Aug 05 05:36:09 PM PDT 24
Finished Aug 05 05:36:10 PM PDT 24
Peak memory 207364 kb
Host smart-2428b3c6-7e03-4078-a04f-1fbb708603b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35312
41912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3531241912
Directory /workspace/17.usbdev_stall_trans/latest


Test location /workspace/coverage/default/17.usbdev_stream_len_max.4190361695
Short name T2258
Test name
Test status
Simulation time 231212241 ps
CPU time 1.07 seconds
Started Aug 05 05:36:06 PM PDT 24
Finished Aug 05 05:36:07 PM PDT 24
Peak memory 207368 kb
Host smart-18b673de-d567-4216-993b-e0d549936737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41903
61695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.4190361695
Directory /workspace/17.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/17.usbdev_streaming_out.3272041129
Short name T1617
Test name
Test status
Simulation time 4141992449 ps
CPU time 43.57 seconds
Started Aug 05 05:36:04 PM PDT 24
Finished Aug 05 05:36:47 PM PDT 24
Peak memory 217384 kb
Host smart-ef5fb281-ca81-4c07-8153-b520744cceed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32720
41129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.3272041129
Directory /workspace/17.usbdev_streaming_out/latest


Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.981026462
Short name T2588
Test name
Test status
Simulation time 2220513142 ps
CPU time 14.61 seconds
Started Aug 05 05:35:59 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 207684 kb
Host smart-03e4daac-c756-42fa-ba3a-c7d3a8e974a9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981026462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_host
_handshake.981026462
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/170.usbdev_endpoint_types.3381930289
Short name T456
Test name
Test status
Simulation time 601446803 ps
CPU time 1.47 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207372 kb
Host smart-d42467dd-2c4c-4e50-9a9e-70b499e0d2ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3381930289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.3381930289
Directory /workspace/170.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/171.usbdev_endpoint_types.855661579
Short name T3040
Test name
Test status
Simulation time 387981120 ps
CPU time 1.18 seconds
Started Aug 05 05:40:44 PM PDT 24
Finished Aug 05 05:40:45 PM PDT 24
Peak memory 207344 kb
Host smart-e1872cfd-be3e-443d-8183-8e307cb11640
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=855661579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.855661579
Directory /workspace/171.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/172.usbdev_endpoint_types.824745217
Short name T472
Test name
Test status
Simulation time 524805180 ps
CPU time 1.52 seconds
Started Aug 05 05:40:44 PM PDT 24
Finished Aug 05 05:40:45 PM PDT 24
Peak memory 207244 kb
Host smart-31a9654b-77dd-4864-94ff-63b1183931fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=824745217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.824745217
Directory /workspace/172.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/174.usbdev_endpoint_types.2578342277
Short name T470
Test name
Test status
Simulation time 1081101586 ps
CPU time 2.11 seconds
Started Aug 05 05:40:43 PM PDT 24
Finished Aug 05 05:40:45 PM PDT 24
Peak memory 207324 kb
Host smart-57ba8015-bd48-4223-92a6-103dbe55fe0e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2578342277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.2578342277
Directory /workspace/174.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/175.usbdev_endpoint_types.95242791
Short name T358
Test name
Test status
Simulation time 376225560 ps
CPU time 1.31 seconds
Started Aug 05 05:40:53 PM PDT 24
Finished Aug 05 05:40:54 PM PDT 24
Peak memory 207392 kb
Host smart-fe223d95-ad67-469f-90e4-9c3cb4d43061
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=95242791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.95242791
Directory /workspace/175.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/178.usbdev_endpoint_types.427178411
Short name T385
Test name
Test status
Simulation time 516781158 ps
CPU time 1.34 seconds
Started Aug 05 05:40:45 PM PDT 24
Finished Aug 05 05:40:47 PM PDT 24
Peak memory 207320 kb
Host smart-d6361acd-9632-4768-8751-3c0511b485b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=427178411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.427178411
Directory /workspace/178.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/179.usbdev_endpoint_types.1118410470
Short name T2625
Test name
Test status
Simulation time 307049957 ps
CPU time 1.12 seconds
Started Aug 05 05:41:02 PM PDT 24
Finished Aug 05 05:41:03 PM PDT 24
Peak memory 207352 kb
Host smart-6cda4811-81a3-402f-9e87-ca847dfe2c30
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1118410470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.1118410470
Directory /workspace/179.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/18.usbdev_alert_test.848852684
Short name T2177
Test name
Test status
Simulation time 30828183 ps
CPU time 0.67 seconds
Started Aug 05 05:36:19 PM PDT 24
Finished Aug 05 05:36:20 PM PDT 24
Peak memory 207380 kb
Host smart-b4583252-1995-4a2a-8be8-58f8341f28f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=848852684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.848852684
Directory /workspace/18.usbdev_alert_test/latest


Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.29829878
Short name T1086
Test name
Test status
Simulation time 9495296368 ps
CPU time 10.91 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:16 PM PDT 24
Peak memory 207668 kb
Host smart-c66d260a-ace8-4b3d-a98a-767a89ff2cce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29829878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon
_wake_disconnect.29829878
Directory /workspace/18.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2338064310
Short name T1296
Test name
Test status
Simulation time 19873618975 ps
CPU time 23.23 seconds
Started Aug 05 05:36:07 PM PDT 24
Finished Aug 05 05:36:30 PM PDT 24
Peak memory 207620 kb
Host smart-80d9c844-5a71-488d-ae91-82587998af5b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338064310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2338064310
Directory /workspace/18.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.4058005741
Short name T2617
Test name
Test status
Simulation time 25281637846 ps
CPU time 29.62 seconds
Started Aug 05 05:36:05 PM PDT 24
Finished Aug 05 05:36:34 PM PDT 24
Peak memory 215848 kb
Host smart-155452ae-9813-4088-a14c-f4f78196e9be
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058005741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.4058005741
Directory /workspace/18.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/18.usbdev_av_buffer.2931890914
Short name T2810
Test name
Test status
Simulation time 172740694 ps
CPU time 0.91 seconds
Started Aug 05 05:36:09 PM PDT 24
Finished Aug 05 05:36:10 PM PDT 24
Peak memory 207224 kb
Host smart-b5741814-b201-44fa-9a8d-26e3defb8e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
90914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2931890914
Directory /workspace/18.usbdev_av_buffer/latest


Test location /workspace/coverage/default/18.usbdev_bitstuff_err.2203673864
Short name T1782
Test name
Test status
Simulation time 150048896 ps
CPU time 0.86 seconds
Started Aug 05 05:36:07 PM PDT 24
Finished Aug 05 05:36:08 PM PDT 24
Peak memory 207316 kb
Host smart-9699f9c8-d387-43fa-9cc5-9cb6f1381577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22036
73864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.2203673864
Directory /workspace/18.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3141427735
Short name T685
Test name
Test status
Simulation time 448187055 ps
CPU time 1.47 seconds
Started Aug 05 05:36:06 PM PDT 24
Finished Aug 05 05:36:08 PM PDT 24
Peak memory 207232 kb
Host smart-449fe51e-abc4-4fbf-8df7-f898ee9f02ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31414
27735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3141427735
Directory /workspace/18.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3601303108
Short name T1676
Test name
Test status
Simulation time 815525697 ps
CPU time 2.38 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:15 PM PDT 24
Peak memory 207616 kb
Host smart-f1583f90-c1c2-4317-b40d-d1a1e6288d08
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3601303108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3601303108
Directory /workspace/18.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/18.usbdev_device_address.338039631
Short name T2292
Test name
Test status
Simulation time 31798039601 ps
CPU time 48.5 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207604 kb
Host smart-99c9d19b-77f1-4313-815f-23062d01c7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33803
9631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.338039631
Directory /workspace/18.usbdev_device_address/latest


Test location /workspace/coverage/default/18.usbdev_device_timeout.3591845443
Short name T2191
Test name
Test status
Simulation time 883462263 ps
CPU time 5.49 seconds
Started Aug 05 05:36:17 PM PDT 24
Finished Aug 05 05:36:23 PM PDT 24
Peak memory 207376 kb
Host smart-812f8e70-b9be-4eb7-94a4-c6c5278bad5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591845443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.3591845443
Directory /workspace/18.usbdev_device_timeout/latest


Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1027882203
Short name T1200
Test name
Test status
Simulation time 914944426 ps
CPU time 2.08 seconds
Started Aug 05 05:36:14 PM PDT 24
Finished Aug 05 05:36:16 PM PDT 24
Peak memory 207296 kb
Host smart-f00f1919-d151-4758-bfcc-9dae0cc8c793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10278
82203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1027882203
Directory /workspace/18.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/18.usbdev_disconnected.1984795745
Short name T1190
Test name
Test status
Simulation time 146056579 ps
CPU time 0.83 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 207336 kb
Host smart-0d140163-687e-49de-ab74-13db4e5712cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19847
95745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1984795745
Directory /workspace/18.usbdev_disconnected/latest


Test location /workspace/coverage/default/18.usbdev_enable.4080558189
Short name T519
Test name
Test status
Simulation time 45843338 ps
CPU time 0.73 seconds
Started Aug 05 05:36:17 PM PDT 24
Finished Aug 05 05:36:18 PM PDT 24
Peak memory 207356 kb
Host smart-4c24b287-74d9-4c6e-ba8a-936992e59c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40805
58189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.4080558189
Directory /workspace/18.usbdev_enable/latest


Test location /workspace/coverage/default/18.usbdev_endpoint_access.2138926322
Short name T622
Test name
Test status
Simulation time 852532630 ps
CPU time 2.32 seconds
Started Aug 05 05:36:12 PM PDT 24
Finished Aug 05 05:36:15 PM PDT 24
Peak memory 207532 kb
Host smart-82e27358-236b-4fb8-b1a1-d542c6f08dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21389
26322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2138926322
Directory /workspace/18.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/18.usbdev_endpoint_types.3038709676
Short name T396
Test name
Test status
Simulation time 505374830 ps
CPU time 1.42 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 207296 kb
Host smart-4a7a26d3-1cca-42d5-bcb4-01fc0b037127
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3038709676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.3038709676
Directory /workspace/18.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/18.usbdev_fifo_rst.461440866
Short name T191
Test name
Test status
Simulation time 362479722 ps
CPU time 2.36 seconds
Started Aug 05 05:36:12 PM PDT 24
Finished Aug 05 05:36:15 PM PDT 24
Peak memory 207444 kb
Host smart-ef864318-9002-41d3-bad8-a03ea8e1115d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46144
0866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.461440866
Directory /workspace/18.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/18.usbdev_in_iso.2594951258
Short name T1577
Test name
Test status
Simulation time 194695498 ps
CPU time 1.14 seconds
Started Aug 05 05:36:12 PM PDT 24
Finished Aug 05 05:36:13 PM PDT 24
Peak memory 207472 kb
Host smart-66f11717-c285-403a-90d8-67c968890710
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2594951258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2594951258
Directory /workspace/18.usbdev_in_iso/latest


Test location /workspace/coverage/default/18.usbdev_in_stall.386768029
Short name T1333
Test name
Test status
Simulation time 143901718 ps
CPU time 0.81 seconds
Started Aug 05 05:36:16 PM PDT 24
Finished Aug 05 05:36:17 PM PDT 24
Peak memory 207356 kb
Host smart-82a897ab-c3e1-4dd6-81ad-efb062d059cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38676
8029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.386768029
Directory /workspace/18.usbdev_in_stall/latest


Test location /workspace/coverage/default/18.usbdev_in_trans.1892783621
Short name T1223
Test name
Test status
Simulation time 191579922 ps
CPU time 0.99 seconds
Started Aug 05 05:36:16 PM PDT 24
Finished Aug 05 05:36:17 PM PDT 24
Peak memory 207340 kb
Host smart-ccb7dd8b-bd19-4417-9315-5f23de11e634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18927
83621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1892783621
Directory /workspace/18.usbdev_in_trans/latest


Test location /workspace/coverage/default/18.usbdev_invalid_sync.3917083570
Short name T2368
Test name
Test status
Simulation time 3714147742 ps
CPU time 109.22 seconds
Started Aug 05 05:36:17 PM PDT 24
Finished Aug 05 05:38:07 PM PDT 24
Peak memory 215740 kb
Host smart-7769eff8-c501-41cf-8213-d61ea480ddb4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3917083570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.3917083570
Directory /workspace/18.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/18.usbdev_iso_retraction.4272683981
Short name T890
Test name
Test status
Simulation time 4497801873 ps
CPU time 53.63 seconds
Started Aug 05 05:36:11 PM PDT 24
Finished Aug 05 05:37:05 PM PDT 24
Peak memory 207540 kb
Host smart-14a97d51-5368-4334-87d0-9bf249cfd68a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4272683981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.4272683981
Directory /workspace/18.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/18.usbdev_link_in_err.1125499166
Short name T2803
Test name
Test status
Simulation time 253022103 ps
CPU time 1.03 seconds
Started Aug 05 05:36:12 PM PDT 24
Finished Aug 05 05:36:13 PM PDT 24
Peak memory 207348 kb
Host smart-b8a33a32-666e-4ff3-9dfa-d301e126026c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11254
99166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.1125499166
Directory /workspace/18.usbdev_link_in_err/latest


Test location /workspace/coverage/default/18.usbdev_link_resume.1149171000
Short name T921
Test name
Test status
Simulation time 28623500398 ps
CPU time 51.37 seconds
Started Aug 05 05:36:17 PM PDT 24
Finished Aug 05 05:37:09 PM PDT 24
Peak memory 207500 kb
Host smart-2a2d1222-281b-4101-92d4-ec0b934a17ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11491
71000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1149171000
Directory /workspace/18.usbdev_link_resume/latest


Test location /workspace/coverage/default/18.usbdev_link_suspend.1472723453
Short name T1215
Test name
Test status
Simulation time 9023929371 ps
CPU time 13.27 seconds
Started Aug 05 05:36:17 PM PDT 24
Finished Aug 05 05:36:30 PM PDT 24
Peak memory 207672 kb
Host smart-bd042c8a-0365-4bac-8acb-4117edef3fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14727
23453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1472723453
Directory /workspace/18.usbdev_link_suspend/latest


Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.768673455
Short name T955
Test name
Test status
Simulation time 3211537181 ps
CPU time 23.73 seconds
Started Aug 05 05:36:12 PM PDT 24
Finished Aug 05 05:36:36 PM PDT 24
Peak memory 223916 kb
Host smart-d0d7106e-b740-4393-bccd-57f13aa99aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76867
3455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.768673455
Directory /workspace/18.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.756551411
Short name T164
Test name
Test status
Simulation time 2580545062 ps
CPU time 75.01 seconds
Started Aug 05 05:36:11 PM PDT 24
Finished Aug 05 05:37:26 PM PDT 24
Peak memory 215756 kb
Host smart-28fce9cc-9590-41cc-a10f-916b4b21cc27
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=756551411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.756551411
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3822969313
Short name T1803
Test name
Test status
Simulation time 305133699 ps
CPU time 1.04 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:15 PM PDT 24
Peak memory 207352 kb
Host smart-f94c7a00-edc1-4bbc-968b-290586350d62
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3822969313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3822969313
Directory /workspace/18.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3226587967
Short name T725
Test name
Test status
Simulation time 266571946 ps
CPU time 1.07 seconds
Started Aug 05 05:36:14 PM PDT 24
Finished Aug 05 05:36:15 PM PDT 24
Peak memory 207300 kb
Host smart-3f335b7d-805c-44ad-ab48-8d78ed4895dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32265
87967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3226587967
Directory /workspace/18.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.704416516
Short name T1314
Test name
Test status
Simulation time 1914765752 ps
CPU time 52.76 seconds
Started Aug 05 05:36:16 PM PDT 24
Finished Aug 05 05:37:09 PM PDT 24
Peak memory 215688 kb
Host smart-68550bc7-12c4-4adf-9d36-22a020d791e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70441
6516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.704416516
Directory /workspace/18.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.3841865245
Short name T747
Test name
Test status
Simulation time 2683639320 ps
CPU time 77.89 seconds
Started Aug 05 05:36:11 PM PDT 24
Finished Aug 05 05:37:29 PM PDT 24
Peak memory 215760 kb
Host smart-5cc9cd75-8c9c-46c6-846d-75115457b553
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3841865245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.3841865245
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.4201706919
Short name T2036
Test name
Test status
Simulation time 152110397 ps
CPU time 0.85 seconds
Started Aug 05 05:36:11 PM PDT 24
Finished Aug 05 05:36:12 PM PDT 24
Peak memory 207432 kb
Host smart-ff5275d2-ca17-4871-b440-62eaea918d03
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4201706919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.4201706919
Directory /workspace/18.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1117152334
Short name T2766
Test name
Test status
Simulation time 148548490 ps
CPU time 0.87 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 207256 kb
Host smart-e1bb66b2-c618-481c-97f5-e96bb6aeeda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11171
52334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1117152334
Directory /workspace/18.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/18.usbdev_nak_trans.4040673221
Short name T129
Test name
Test status
Simulation time 258644461 ps
CPU time 1.04 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 207340 kb
Host smart-8b2a01e8-3fa1-4ad1-8cb3-ebeaa09f0aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40406
73221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.4040673221
Directory /workspace/18.usbdev_nak_trans/latest


Test location /workspace/coverage/default/18.usbdev_out_iso.2767877652
Short name T2205
Test name
Test status
Simulation time 194298968 ps
CPU time 0.9 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 207348 kb
Host smart-0177d409-ff3d-4ad0-b176-ade1432abe0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27678
77652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2767877652
Directory /workspace/18.usbdev_out_iso/latest


Test location /workspace/coverage/default/18.usbdev_out_stall.919569826
Short name T597
Test name
Test status
Simulation time 199386634 ps
CPU time 0.9 seconds
Started Aug 05 05:36:16 PM PDT 24
Finished Aug 05 05:36:17 PM PDT 24
Peak memory 207380 kb
Host smart-e47a6fdb-7154-432b-aaed-5c6fbeb1e60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91956
9826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.919569826
Directory /workspace/18.usbdev_out_stall/latest


Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1435225123
Short name T2280
Test name
Test status
Simulation time 165096023 ps
CPU time 0.89 seconds
Started Aug 05 05:36:14 PM PDT 24
Finished Aug 05 05:36:15 PM PDT 24
Peak memory 207376 kb
Host smart-51d21ecf-d2a2-41ee-806f-814229746a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14352
25123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1435225123
Directory /workspace/18.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/18.usbdev_pending_in_trans.915507512
Short name T2161
Test name
Test status
Simulation time 167133280 ps
CPU time 0.85 seconds
Started Aug 05 05:36:16 PM PDT 24
Finished Aug 05 05:36:17 PM PDT 24
Peak memory 207344 kb
Host smart-b84ba06c-7a15-49da-89a1-69530fb23c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91550
7512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.915507512
Directory /workspace/18.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.2381689610
Short name T2158
Test name
Test status
Simulation time 194807465 ps
CPU time 1 seconds
Started Aug 05 05:36:12 PM PDT 24
Finished Aug 05 05:36:13 PM PDT 24
Peak memory 207380 kb
Host smart-b2ccf9fe-1677-4bb5-84c8-ab08462edcf9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2381689610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.2381689610
Directory /workspace/18.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1726581802
Short name T854
Test name
Test status
Simulation time 155259718 ps
CPU time 0.85 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 207344 kb
Host smart-fe63e893-d685-4cfe-b17e-c373aa3ddcc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17265
81802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1726581802
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3659978703
Short name T1305
Test name
Test status
Simulation time 43453349 ps
CPU time 0.73 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 207260 kb
Host smart-efd64eb4-df5e-4a53-a34b-74430574d423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36599
78703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3659978703
Directory /workspace/18.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2178139738
Short name T2239
Test name
Test status
Simulation time 15490851368 ps
CPU time 40.12 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:53 PM PDT 24
Peak memory 215816 kb
Host smart-28a2ef07-f2d3-42a0-bd19-4b5303b88279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21781
39738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2178139738
Directory /workspace/18.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/18.usbdev_pkt_received.2809907098
Short name T2277
Test name
Test status
Simulation time 250433879 ps
CPU time 1.09 seconds
Started Aug 05 05:36:11 PM PDT 24
Finished Aug 05 05:36:13 PM PDT 24
Peak memory 207264 kb
Host smart-5938be1f-ef89-42fc-9a7a-2ed0062386c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28099
07098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2809907098
Directory /workspace/18.usbdev_pkt_received/latest


Test location /workspace/coverage/default/18.usbdev_pkt_sent.1168362255
Short name T2236
Test name
Test status
Simulation time 173703756 ps
CPU time 0.91 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 207324 kb
Host smart-2f2f0d4d-48a5-41cd-8ea0-9287b7281e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11683
62255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1168362255
Directory /workspace/18.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.1286354286
Short name T2449
Test name
Test status
Simulation time 237056714 ps
CPU time 1.02 seconds
Started Aug 05 05:36:17 PM PDT 24
Finished Aug 05 05:36:18 PM PDT 24
Peak memory 207224 kb
Host smart-6d79f371-c81d-4377-8bd3-858b429bb678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12863
54286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.1286354286
Directory /workspace/18.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.4055639185
Short name T1517
Test name
Test status
Simulation time 193344195 ps
CPU time 0.93 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:36:27 PM PDT 24
Peak memory 207380 kb
Host smart-f536ae1f-904c-4aa6-bf77-ef3979290bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40556
39185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.4055639185
Directory /workspace/18.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/18.usbdev_resume_link_active.564254111
Short name T110
Test name
Test status
Simulation time 20170390517 ps
CPU time 25.03 seconds
Started Aug 05 05:36:11 PM PDT 24
Finished Aug 05 05:36:36 PM PDT 24
Peak memory 207432 kb
Host smart-268ea0cf-f4e0-420a-b76d-bedf58811199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56425
4111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_resume_link_active.564254111
Directory /workspace/18.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1509045350
Short name T2063
Test name
Test status
Simulation time 206444937 ps
CPU time 0.99 seconds
Started Aug 05 05:36:13 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 207416 kb
Host smart-0483d022-caf6-41d6-b889-7aae5ca269c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15090
45350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1509045350
Directory /workspace/18.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/18.usbdev_rx_full.3438812508
Short name T1173
Test name
Test status
Simulation time 395257923 ps
CPU time 1.31 seconds
Started Aug 05 05:36:18 PM PDT 24
Finished Aug 05 05:36:20 PM PDT 24
Peak memory 207224 kb
Host smart-07e45de4-9a05-4603-b49c-eeb72364d3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34388
12508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.3438812508
Directory /workspace/18.usbdev_rx_full/latest


Test location /workspace/coverage/default/18.usbdev_setup_stage.3192613151
Short name T1650
Test name
Test status
Simulation time 187783174 ps
CPU time 0.91 seconds
Started Aug 05 05:36:12 PM PDT 24
Finished Aug 05 05:36:13 PM PDT 24
Peak memory 207316 kb
Host smart-c531e685-b2f3-4f70-963a-8416b7ebad97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31926
13151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3192613151
Directory /workspace/18.usbdev_setup_stage/latest


Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.4250421102
Short name T1431
Test name
Test status
Simulation time 157503585 ps
CPU time 0.85 seconds
Started Aug 05 05:36:18 PM PDT 24
Finished Aug 05 05:36:19 PM PDT 24
Peak memory 207288 kb
Host smart-49a6f03a-e214-4243-8e18-3bd0fd83e380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42504
21102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.4250421102
Directory /workspace/18.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/18.usbdev_smoke.902602583
Short name T1558
Test name
Test status
Simulation time 251379142 ps
CPU time 1.07 seconds
Started Aug 05 05:36:17 PM PDT 24
Finished Aug 05 05:36:18 PM PDT 24
Peak memory 207348 kb
Host smart-a18db924-44ff-4819-a30b-46a08d158d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90260
2583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.902602583
Directory /workspace/18.usbdev_smoke/latest


Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.2078904819
Short name T2868
Test name
Test status
Simulation time 2579933198 ps
CPU time 74.98 seconds
Started Aug 05 05:36:18 PM PDT 24
Finished Aug 05 05:37:33 PM PDT 24
Peak memory 223940 kb
Host smart-b91bcbe4-d108-445a-a8ed-7421a846765b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2078904819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.2078904819
Directory /workspace/18.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3686760863
Short name T2092
Test name
Test status
Simulation time 195652860 ps
CPU time 0.95 seconds
Started Aug 05 05:36:19 PM PDT 24
Finished Aug 05 05:36:20 PM PDT 24
Peak memory 207328 kb
Host smart-d39da3e3-da3a-48e9-b4fb-efc3803f2934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36867
60863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3686760863
Directory /workspace/18.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/18.usbdev_stall_trans.207332340
Short name T513
Test name
Test status
Simulation time 153857306 ps
CPU time 0.85 seconds
Started Aug 05 05:36:20 PM PDT 24
Finished Aug 05 05:36:21 PM PDT 24
Peak memory 207416 kb
Host smart-9d74eaac-f2fc-4a64-b068-9dafde056b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20733
2340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.207332340
Directory /workspace/18.usbdev_stall_trans/latest


Test location /workspace/coverage/default/18.usbdev_stream_len_max.4169897724
Short name T1447
Test name
Test status
Simulation time 222334982 ps
CPU time 1.02 seconds
Started Aug 05 05:36:17 PM PDT 24
Finished Aug 05 05:36:19 PM PDT 24
Peak memory 207304 kb
Host smart-7e63a2d6-0964-4760-8c6f-f2b66a7c268c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41698
97724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.4169897724
Directory /workspace/18.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/18.usbdev_streaming_out.3937098314
Short name T1458
Test name
Test status
Simulation time 1862349637 ps
CPU time 54.45 seconds
Started Aug 05 05:36:19 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 217172 kb
Host smart-6f483050-2f83-4b77-ac6f-a2ca5abbc074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39370
98314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.3937098314
Directory /workspace/18.usbdev_streaming_out/latest


Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.2484823573
Short name T1661
Test name
Test status
Simulation time 596779695 ps
CPU time 11.7 seconds
Started Aug 05 05:36:12 PM PDT 24
Finished Aug 05 05:36:24 PM PDT 24
Peak memory 207420 kb
Host smart-b79a4cdf-4229-47a8-9738-d2581a6a9aab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484823573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_hos
t_handshake.2484823573
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/180.usbdev_endpoint_types.4004074130
Short name T337
Test name
Test status
Simulation time 661945609 ps
CPU time 1.61 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:41:02 PM PDT 24
Peak memory 207324 kb
Host smart-6e1d0ae6-af96-48d3-b866-49dad1d06af5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4004074130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.4004074130
Directory /workspace/180.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/182.usbdev_endpoint_types.3289791434
Short name T3078
Test name
Test status
Simulation time 732865991 ps
CPU time 1.68 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:40:50 PM PDT 24
Peak memory 207372 kb
Host smart-c318ca78-5c40-4754-b049-0e7ad537ec74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3289791434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.3289791434
Directory /workspace/182.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/183.usbdev_endpoint_types.3455115207
Short name T437
Test name
Test status
Simulation time 628219972 ps
CPU time 1.56 seconds
Started Aug 05 05:40:45 PM PDT 24
Finished Aug 05 05:40:47 PM PDT 24
Peak memory 207348 kb
Host smart-7c7ed929-51e0-4144-b7d8-a09a994eed2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3455115207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.3455115207
Directory /workspace/183.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/184.usbdev_endpoint_types.531650029
Short name T391
Test name
Test status
Simulation time 328521287 ps
CPU time 1.2 seconds
Started Aug 05 05:40:46 PM PDT 24
Finished Aug 05 05:40:47 PM PDT 24
Peak memory 207372 kb
Host smart-e6630b6a-2a13-45dc-bb89-550854ae7ada
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=531650029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.531650029
Directory /workspace/184.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/185.usbdev_endpoint_types.61539736
Short name T393
Test name
Test status
Simulation time 628374770 ps
CPU time 1.55 seconds
Started Aug 05 05:40:36 PM PDT 24
Finished Aug 05 05:40:38 PM PDT 24
Peak memory 207372 kb
Host smart-e8a83d3a-c4a7-4566-8955-04f8b85b5fc4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=61539736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.61539736
Directory /workspace/185.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/189.usbdev_endpoint_types.2477174080
Short name T450
Test name
Test status
Simulation time 194822556 ps
CPU time 0.9 seconds
Started Aug 05 05:40:58 PM PDT 24
Finished Aug 05 05:40:59 PM PDT 24
Peak memory 207240 kb
Host smart-08e80652-6919-4e0a-a55b-5cbb5df293c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2477174080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.2477174080
Directory /workspace/189.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/19.usbdev_alert_test.3655001799
Short name T719
Test name
Test status
Simulation time 70820297 ps
CPU time 0.7 seconds
Started Aug 05 05:36:28 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207360 kb
Host smart-f3d87208-3323-4bec-9286-b6cc8260ac81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3655001799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.3655001799
Directory /workspace/19.usbdev_alert_test/latest


Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.4243767506
Short name T2730
Test name
Test status
Simulation time 4664459250 ps
CPU time 6.3 seconds
Started Aug 05 05:36:16 PM PDT 24
Finished Aug 05 05:36:22 PM PDT 24
Peak memory 215764 kb
Host smart-c5985851-f29d-4ace-bb7f-e2e5695dec7e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243767506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.4243767506
Directory /workspace/19.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3919013768
Short name T2402
Test name
Test status
Simulation time 19986309780 ps
CPU time 25.09 seconds
Started Aug 05 05:36:17 PM PDT 24
Finished Aug 05 05:36:42 PM PDT 24
Peak memory 207540 kb
Host smart-4dc33230-3342-450b-9cd8-523cc1cd100b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919013768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3919013768
Directory /workspace/19.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/19.usbdev_av_buffer.1982632506
Short name T1667
Test name
Test status
Simulation time 156277622 ps
CPU time 0.91 seconds
Started Aug 05 05:36:18 PM PDT 24
Finished Aug 05 05:36:19 PM PDT 24
Peak memory 207304 kb
Host smart-e8759c7e-dcd2-4d28-8548-8c3c24d661ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19826
32506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1982632506
Directory /workspace/19.usbdev_av_buffer/latest


Test location /workspace/coverage/default/19.usbdev_bitstuff_err.2489409833
Short name T1907
Test name
Test status
Simulation time 144634726 ps
CPU time 0.84 seconds
Started Aug 05 05:36:21 PM PDT 24
Finished Aug 05 05:36:22 PM PDT 24
Peak memory 207280 kb
Host smart-267c2f52-b417-417f-9305-b49853a8d500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24894
09833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.2489409833
Directory /workspace/19.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1189959510
Short name T537
Test name
Test status
Simulation time 378323454 ps
CPU time 1.48 seconds
Started Aug 05 05:36:16 PM PDT 24
Finished Aug 05 05:36:18 PM PDT 24
Peak memory 207272 kb
Host smart-2b5388f2-6995-4045-85dd-e87a54ca9b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11899
59510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1189959510
Directory /workspace/19.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2643198492
Short name T91
Test name
Test status
Simulation time 1024233450 ps
CPU time 2.49 seconds
Started Aug 05 05:36:34 PM PDT 24
Finished Aug 05 05:36:36 PM PDT 24
Peak memory 207616 kb
Host smart-beffcaa9-5cf5-4fb0-bacf-0edc05d5e21c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2643198492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2643198492
Directory /workspace/19.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/19.usbdev_device_address.2012059992
Short name T182
Test name
Test status
Simulation time 31902582430 ps
CPU time 53.12 seconds
Started Aug 05 05:36:20 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 207612 kb
Host smart-eec35f7a-1f76-4906-b5b0-8467a4ffea26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20120
59992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2012059992
Directory /workspace/19.usbdev_device_address/latest


Test location /workspace/coverage/default/19.usbdev_device_timeout.4006474464
Short name T2156
Test name
Test status
Simulation time 889572558 ps
CPU time 18.75 seconds
Started Aug 05 05:36:18 PM PDT 24
Finished Aug 05 05:36:38 PM PDT 24
Peak memory 207428 kb
Host smart-e644beb0-f89d-461a-846a-af181e38ad8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006474464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.4006474464
Directory /workspace/19.usbdev_device_timeout/latest


Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3369339055
Short name T1121
Test name
Test status
Simulation time 622906752 ps
CPU time 1.94 seconds
Started Aug 05 05:36:18 PM PDT 24
Finished Aug 05 05:36:21 PM PDT 24
Peak memory 207288 kb
Host smart-6bd93768-8544-4e04-a3ee-b549370039b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33693
39055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3369339055
Directory /workspace/19.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/19.usbdev_disconnected.1643651131
Short name T1449
Test name
Test status
Simulation time 152318050 ps
CPU time 0.86 seconds
Started Aug 05 05:36:19 PM PDT 24
Finished Aug 05 05:36:20 PM PDT 24
Peak memory 207316 kb
Host smart-de633e02-ae63-4d1e-aa7d-c958e48570c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16436
51131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1643651131
Directory /workspace/19.usbdev_disconnected/latest


Test location /workspace/coverage/default/19.usbdev_enable.3150542636
Short name T1972
Test name
Test status
Simulation time 62522233 ps
CPU time 0.71 seconds
Started Aug 05 05:36:30 PM PDT 24
Finished Aug 05 05:36:31 PM PDT 24
Peak memory 207344 kb
Host smart-3ab10d28-a732-4ae3-aeec-85acc00f7444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31505
42636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3150542636
Directory /workspace/19.usbdev_enable/latest


Test location /workspace/coverage/default/19.usbdev_endpoint_access.96960687
Short name T1176
Test name
Test status
Simulation time 930401693 ps
CPU time 2.41 seconds
Started Aug 05 05:36:20 PM PDT 24
Finished Aug 05 05:36:23 PM PDT 24
Peak memory 207612 kb
Host smart-65e7350f-3c32-4a0b-a564-761cb6c2af07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96960
687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.96960687
Directory /workspace/19.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/19.usbdev_endpoint_types.1087558125
Short name T409
Test name
Test status
Simulation time 519658390 ps
CPU time 1.43 seconds
Started Aug 05 05:36:21 PM PDT 24
Finished Aug 05 05:36:22 PM PDT 24
Peak memory 207324 kb
Host smart-6096018f-9172-4548-abcf-6f13b09714a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1087558125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.1087558125
Directory /workspace/19.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/19.usbdev_fifo_rst.2059956503
Short name T2569
Test name
Test status
Simulation time 267150015 ps
CPU time 2.31 seconds
Started Aug 05 05:36:34 PM PDT 24
Finished Aug 05 05:36:37 PM PDT 24
Peak memory 207528 kb
Host smart-5ade84f1-6969-48c8-a003-f5a1b3d3f328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20599
56503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2059956503
Directory /workspace/19.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/19.usbdev_in_iso.2927598301
Short name T592
Test name
Test status
Simulation time 175915281 ps
CPU time 0.99 seconds
Started Aug 05 05:36:20 PM PDT 24
Finished Aug 05 05:36:21 PM PDT 24
Peak memory 215684 kb
Host smart-a309c5d2-6f3f-49f3-ad75-073478d6b51f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2927598301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2927598301
Directory /workspace/19.usbdev_in_iso/latest


Test location /workspace/coverage/default/19.usbdev_in_stall.3642317300
Short name T1626
Test name
Test status
Simulation time 161087855 ps
CPU time 0.84 seconds
Started Aug 05 05:36:19 PM PDT 24
Finished Aug 05 05:36:20 PM PDT 24
Peak memory 207348 kb
Host smart-4dce3d2c-0b33-41d6-b662-7443d3479e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36423
17300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3642317300
Directory /workspace/19.usbdev_in_stall/latest


Test location /workspace/coverage/default/19.usbdev_in_trans.1444473748
Short name T499
Test name
Test status
Simulation time 252006408 ps
CPU time 1 seconds
Started Aug 05 05:36:30 PM PDT 24
Finished Aug 05 05:36:31 PM PDT 24
Peak memory 207384 kb
Host smart-05eb7643-bc73-477d-95ec-2dae9ddf3713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14444
73748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1444473748
Directory /workspace/19.usbdev_in_trans/latest


Test location /workspace/coverage/default/19.usbdev_invalid_sync.3405315682
Short name T2896
Test name
Test status
Simulation time 4282056364 ps
CPU time 42.27 seconds
Started Aug 05 05:36:30 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 224064 kb
Host smart-0f314dd3-295d-4c35-b9c9-40ab49e12c7e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3405315682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.3405315682
Directory /workspace/19.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/19.usbdev_iso_retraction.3614318432
Short name T2130
Test name
Test status
Simulation time 7772074881 ps
CPU time 98.12 seconds
Started Aug 05 05:36:19 PM PDT 24
Finished Aug 05 05:37:57 PM PDT 24
Peak memory 207668 kb
Host smart-57ece870-0c9f-4bd2-801b-c3f8cecf3e0f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3614318432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.3614318432
Directory /workspace/19.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/19.usbdev_link_in_err.4083219091
Short name T1695
Test name
Test status
Simulation time 225203621 ps
CPU time 0.93 seconds
Started Aug 05 05:36:18 PM PDT 24
Finished Aug 05 05:36:19 PM PDT 24
Peak memory 207240 kb
Host smart-b8b577b4-3666-48f6-9045-97fb958682f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40832
19091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.4083219091
Directory /workspace/19.usbdev_link_in_err/latest


Test location /workspace/coverage/default/19.usbdev_link_suspend.1356597840
Short name T2466
Test name
Test status
Simulation time 5678271081 ps
CPU time 8.35 seconds
Started Aug 05 05:36:18 PM PDT 24
Finished Aug 05 05:36:27 PM PDT 24
Peak memory 216628 kb
Host smart-9306b1d2-f203-4c69-beb3-f5c31e754d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13565
97840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1356597840
Directory /workspace/19.usbdev_link_suspend/latest


Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.3855588928
Short name T968
Test name
Test status
Simulation time 3657489152 ps
CPU time 98.49 seconds
Started Aug 05 05:36:18 PM PDT 24
Finished Aug 05 05:37:57 PM PDT 24
Peak memory 224300 kb
Host smart-f08409a9-86b3-42da-a42c-f7ace633e881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38555
88928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.3855588928
Directory /workspace/19.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.1324635589
Short name T2109
Test name
Test status
Simulation time 4217831311 ps
CPU time 32.82 seconds
Started Aug 05 05:36:20 PM PDT 24
Finished Aug 05 05:36:53 PM PDT 24
Peak memory 215836 kb
Host smart-7d0fbed7-ca76-45c9-861a-bf0e3ace6060
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1324635589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1324635589
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.1216705883
Short name T1289
Test name
Test status
Simulation time 268080600 ps
CPU time 1.18 seconds
Started Aug 05 05:36:20 PM PDT 24
Finished Aug 05 05:36:21 PM PDT 24
Peak memory 207272 kb
Host smart-c8461021-eaee-4a6b-80ee-64d45fe6d1ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1216705883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.1216705883
Directory /workspace/19.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2159171368
Short name T2558
Test name
Test status
Simulation time 194127513 ps
CPU time 0.92 seconds
Started Aug 05 05:36:30 PM PDT 24
Finished Aug 05 05:36:31 PM PDT 24
Peak memory 207384 kb
Host smart-308ad2de-d6d7-4f29-ae86-032acf971ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21591
71368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2159171368
Directory /workspace/19.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.4247490199
Short name T1722
Test name
Test status
Simulation time 2492331210 ps
CPU time 70.99 seconds
Started Aug 05 05:36:30 PM PDT 24
Finished Aug 05 05:37:41 PM PDT 24
Peak memory 217460 kb
Host smart-ae3fc093-a466-4999-b296-96c91d891fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42474
90199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.4247490199
Directory /workspace/19.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.297349085
Short name T549
Test name
Test status
Simulation time 2985549358 ps
CPU time 89.1 seconds
Started Aug 05 05:36:20 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 217388 kb
Host smart-7b022ee0-e59c-4014-9dc9-3b2ef4381f45
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=297349085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.297349085
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.1933316984
Short name T603
Test name
Test status
Simulation time 180284836 ps
CPU time 0.86 seconds
Started Aug 05 05:36:18 PM PDT 24
Finished Aug 05 05:36:19 PM PDT 24
Peak memory 207352 kb
Host smart-dc2dfa89-02c1-41ee-a77f-51dc96a5752c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1933316984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1933316984
Directory /workspace/19.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.76226781
Short name T2555
Test name
Test status
Simulation time 154987441 ps
CPU time 0.86 seconds
Started Aug 05 05:36:21 PM PDT 24
Finished Aug 05 05:36:22 PM PDT 24
Peak memory 207352 kb
Host smart-2ff88207-efa9-46e7-aafa-3a36e25c96ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76226
781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.76226781
Directory /workspace/19.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/19.usbdev_nak_trans.2743462438
Short name T1615
Test name
Test status
Simulation time 189287206 ps
CPU time 0.93 seconds
Started Aug 05 05:36:20 PM PDT 24
Finished Aug 05 05:36:21 PM PDT 24
Peak memory 207416 kb
Host smart-9c582617-50dd-4e06-a10a-5090f6edc7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27434
62438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2743462438
Directory /workspace/19.usbdev_nak_trans/latest


Test location /workspace/coverage/default/19.usbdev_out_iso.285164792
Short name T1165
Test name
Test status
Simulation time 162625724 ps
CPU time 0.87 seconds
Started Aug 05 05:36:25 PM PDT 24
Finished Aug 05 05:36:26 PM PDT 24
Peak memory 207396 kb
Host smart-5510e53d-75b7-48bc-b3dc-ac63c46de273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28516
4792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.285164792
Directory /workspace/19.usbdev_out_iso/latest


Test location /workspace/coverage/default/19.usbdev_out_stall.4272858560
Short name T1096
Test name
Test status
Simulation time 188241590 ps
CPU time 0.87 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207320 kb
Host smart-05724abf-0cb1-4006-b3f1-d7e5cabe5051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42728
58560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.4272858560
Directory /workspace/19.usbdev_out_stall/latest


Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2664981554
Short name T690
Test name
Test status
Simulation time 166318354 ps
CPU time 0.87 seconds
Started Aug 05 05:36:36 PM PDT 24
Finished Aug 05 05:36:37 PM PDT 24
Peak memory 207348 kb
Host smart-c370ae2c-2669-4f4c-a762-5484a282692d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26649
81554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2664981554
Directory /workspace/19.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1944141354
Short name T179
Test name
Test status
Simulation time 152612835 ps
CPU time 0.91 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207276 kb
Host smart-2520cc49-a07b-48fc-87d0-d5af6d5ad625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19441
41354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1944141354
Directory /workspace/19.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3912301784
Short name T838
Test name
Test status
Simulation time 205606745 ps
CPU time 0.94 seconds
Started Aug 05 05:36:25 PM PDT 24
Finished Aug 05 05:36:26 PM PDT 24
Peak memory 207356 kb
Host smart-39010b52-1418-42ee-9a1f-209fab7bb395
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3912301784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3912301784
Directory /workspace/19.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1973365887
Short name T843
Test name
Test status
Simulation time 146896624 ps
CPU time 0.86 seconds
Started Aug 05 05:36:25 PM PDT 24
Finished Aug 05 05:36:25 PM PDT 24
Peak memory 207268 kb
Host smart-cfe76408-857b-4192-a450-61a2461a3b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19733
65887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1973365887
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1315942429
Short name T1837
Test name
Test status
Simulation time 47998539 ps
CPU time 0.74 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207312 kb
Host smart-069e9e61-7829-4131-a1ba-2ab2663c8f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13159
42429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1315942429
Directory /workspace/19.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3113661282
Short name T2212
Test name
Test status
Simulation time 14419120561 ps
CPU time 34.77 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 215884 kb
Host smart-95142d86-dda5-462d-8652-fef49846c80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31136
61282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3113661282
Directory /workspace/19.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/19.usbdev_pkt_received.1273537564
Short name T2042
Test name
Test status
Simulation time 149344997 ps
CPU time 0.83 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207272 kb
Host smart-d1274546-b926-464b-abfd-46472cb6763d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12735
37564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1273537564
Directory /workspace/19.usbdev_pkt_received/latest


Test location /workspace/coverage/default/19.usbdev_pkt_sent.2826757847
Short name T2192
Test name
Test status
Simulation time 216619166 ps
CPU time 0.92 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:36:27 PM PDT 24
Peak memory 207372 kb
Host smart-d4ee4c95-8256-4f2e-97db-fbe2663bdfdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28267
57847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2826757847
Directory /workspace/19.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3787576613
Short name T2358
Test name
Test status
Simulation time 158894880 ps
CPU time 0.87 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207276 kb
Host smart-f01b18a0-ad10-42c5-a682-f2fb9e8638a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37875
76613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3787576613
Directory /workspace/19.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2089369193
Short name T778
Test name
Test status
Simulation time 182345109 ps
CPU time 0.85 seconds
Started Aug 05 05:36:25 PM PDT 24
Finished Aug 05 05:36:26 PM PDT 24
Peak memory 207324 kb
Host smart-e1337d76-d912-47fe-a776-25b7ec6aa355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20893
69193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2089369193
Directory /workspace/19.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/19.usbdev_resume_link_active.2348333985
Short name T1823
Test name
Test status
Simulation time 20174282109 ps
CPU time 24.08 seconds
Started Aug 05 05:36:24 PM PDT 24
Finished Aug 05 05:36:49 PM PDT 24
Peak memory 207348 kb
Host smart-a08eef06-2fff-473c-be52-0ee8fb44395f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23483
33985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.2348333985
Directory /workspace/19.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1690092692
Short name T739
Test name
Test status
Simulation time 226377620 ps
CPU time 0.98 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:33 PM PDT 24
Peak memory 207368 kb
Host smart-024a9abd-de7b-4373-aa59-b14d561edfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16900
92692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1690092692
Directory /workspace/19.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/19.usbdev_setup_stage.3306986227
Short name T2626
Test name
Test status
Simulation time 155024976 ps
CPU time 0.87 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207316 kb
Host smart-da863c22-2e34-4673-bb63-5221b3581bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33069
86227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3306986227
Directory /workspace/19.usbdev_setup_stage/latest


Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2298781219
Short name T2981
Test name
Test status
Simulation time 156725981 ps
CPU time 0.81 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207364 kb
Host smart-97bd1147-b929-4fd8-a855-7c29d085e45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22987
81219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2298781219
Directory /workspace/19.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/19.usbdev_smoke.554405264
Short name T624
Test name
Test status
Simulation time 299996018 ps
CPU time 1.18 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207348 kb
Host smart-9e8c50f4-4b82-463c-9aad-4e8f35fb9f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55440
5264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.554405264
Directory /workspace/19.usbdev_smoke/latest


Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2837776473
Short name T559
Test name
Test status
Simulation time 2531566692 ps
CPU time 18.78 seconds
Started Aug 05 05:36:28 PM PDT 24
Finished Aug 05 05:36:47 PM PDT 24
Peak memory 223884 kb
Host smart-423a2de7-9ea4-4272-ae10-228781d9b3d7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2837776473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2837776473
Directory /workspace/19.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1592978582
Short name T34
Test name
Test status
Simulation time 184227206 ps
CPU time 0.9 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207356 kb
Host smart-937839cd-36cd-4632-aea1-3799fc3cce99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15929
78582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1592978582
Directory /workspace/19.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/19.usbdev_stall_trans.1634341003
Short name T1719
Test name
Test status
Simulation time 147655709 ps
CPU time 0.85 seconds
Started Aug 05 05:36:24 PM PDT 24
Finished Aug 05 05:36:25 PM PDT 24
Peak memory 207428 kb
Host smart-a6d3c36f-8c46-4396-a825-5fb7a087400b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16343
41003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1634341003
Directory /workspace/19.usbdev_stall_trans/latest


Test location /workspace/coverage/default/19.usbdev_stream_len_max.2608458190
Short name T1180
Test name
Test status
Simulation time 502663722 ps
CPU time 1.75 seconds
Started Aug 05 05:36:33 PM PDT 24
Finished Aug 05 05:36:35 PM PDT 24
Peak memory 207264 kb
Host smart-92c708e1-0840-46f1-a928-a2f7f374297f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26084
58190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.2608458190
Directory /workspace/19.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/19.usbdev_streaming_out.150198416
Short name T924
Test name
Test status
Simulation time 2596415068 ps
CPU time 74.06 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:37:40 PM PDT 24
Peak memory 217380 kb
Host smart-60fbadc1-8419-4a5b-822d-483907dac5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15019
8416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.150198416
Directory /workspace/19.usbdev_streaming_out/latest


Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.1018224921
Short name T1844
Test name
Test status
Simulation time 2204271614 ps
CPU time 14.27 seconds
Started Aug 05 05:36:30 PM PDT 24
Finished Aug 05 05:36:44 PM PDT 24
Peak memory 207720 kb
Host smart-f3a8eee8-fd79-465a-8076-7f40c4b43e33
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018224921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.1018224921
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/190.usbdev_endpoint_types.964236928
Short name T411
Test name
Test status
Simulation time 325045718 ps
CPU time 1.17 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:40:50 PM PDT 24
Peak memory 207324 kb
Host smart-ad3a4c73-ade8-4e68-9f97-2e85b08e957e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=964236928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.964236928
Directory /workspace/190.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/195.usbdev_endpoint_types.1840981540
Short name T2861
Test name
Test status
Simulation time 243414390 ps
CPU time 1.06 seconds
Started Aug 05 05:40:53 PM PDT 24
Finished Aug 05 05:40:54 PM PDT 24
Peak memory 207240 kb
Host smart-7862ef16-3178-407a-bc34-35d458cff35e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1840981540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.1840981540
Directory /workspace/195.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/197.usbdev_endpoint_types.3879732176
Short name T354
Test name
Test status
Simulation time 828337862 ps
CPU time 1.81 seconds
Started Aug 05 05:40:41 PM PDT 24
Finished Aug 05 05:40:43 PM PDT 24
Peak memory 207356 kb
Host smart-6adb1653-368a-46c4-9e62-be8a3efc8ea3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3879732176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.3879732176
Directory /workspace/197.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/199.usbdev_endpoint_types.4022889383
Short name T2349
Test name
Test status
Simulation time 321881687 ps
CPU time 1.14 seconds
Started Aug 05 05:41:05 PM PDT 24
Finished Aug 05 05:41:06 PM PDT 24
Peak memory 207272 kb
Host smart-cf0578f5-c515-4464-8b9a-b075aa368944
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4022889383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.4022889383
Directory /workspace/199.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/2.usbdev_alert_test.2688711604
Short name T658
Test name
Test status
Simulation time 36760990 ps
CPU time 0.65 seconds
Started Aug 05 05:33:32 PM PDT 24
Finished Aug 05 05:33:33 PM PDT 24
Peak memory 207460 kb
Host smart-f212ad2d-5e9a-4784-8733-c095ec95a65b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2688711604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.2688711604
Directory /workspace/2.usbdev_alert_test/latest


Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1666074206
Short name T111
Test name
Test status
Simulation time 4154608799 ps
CPU time 5.55 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:16 PM PDT 24
Peak memory 216836 kb
Host smart-a4903b9b-13cd-40aa-ad13-b7fcaea69573
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666074206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.1666074206
Directory /workspace/2.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1712232673
Short name T2385
Test name
Test status
Simulation time 13512804993 ps
CPU time 15.89 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:27 PM PDT 24
Peak memory 215864 kb
Host smart-7a88fdec-4ac6-4e94-a173-48305a27873d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712232673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1712232673
Directory /workspace/2.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.932206753
Short name T1836
Test name
Test status
Simulation time 28878233038 ps
CPU time 43.84 seconds
Started Aug 05 05:33:13 PM PDT 24
Finished Aug 05 05:33:57 PM PDT 24
Peak memory 207684 kb
Host smart-4435d4dd-a947-4eff-a72b-80209d1bf5ba
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932206753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon
_wake_resume.932206753
Directory /workspace/2.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/2.usbdev_av_buffer.2836460319
Short name T1089
Test name
Test status
Simulation time 184351257 ps
CPU time 0.89 seconds
Started Aug 05 05:33:15 PM PDT 24
Finished Aug 05 05:33:16 PM PDT 24
Peak memory 207308 kb
Host smart-93b67540-0438-4ff2-8199-aaf8bce0187e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28364
60319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2836460319
Directory /workspace/2.usbdev_av_buffer/latest


Test location /workspace/coverage/default/2.usbdev_av_overflow.2382106744
Short name T66
Test name
Test status
Simulation time 179660847 ps
CPU time 0.89 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:12 PM PDT 24
Peak memory 207232 kb
Host smart-402454a2-686a-4937-8c90-4feee64ed3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23821
06744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2382106744
Directory /workspace/2.usbdev_av_overflow/latest


Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1645619609
Short name T3005
Test name
Test status
Simulation time 162902605 ps
CPU time 0.82 seconds
Started Aug 05 05:33:10 PM PDT 24
Finished Aug 05 05:33:11 PM PDT 24
Peak memory 207252 kb
Host smart-47c5e265-6ca6-48d1-ad01-d4e6329dcc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16456
19609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1645619609
Directory /workspace/2.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.140944635
Short name T2470
Test name
Test status
Simulation time 584472959 ps
CPU time 1.95 seconds
Started Aug 05 05:33:12 PM PDT 24
Finished Aug 05 05:33:14 PM PDT 24
Peak memory 207580 kb
Host smart-6e866f92-c94c-4973-b7a7-cf8822498420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14094
4635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.140944635
Directory /workspace/2.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3753056555
Short name T1478
Test name
Test status
Simulation time 351716459 ps
CPU time 1.12 seconds
Started Aug 05 05:33:12 PM PDT 24
Finished Aug 05 05:33:13 PM PDT 24
Peak memory 207352 kb
Host smart-62d16d3a-75f0-4c32-bda1-3793548091f3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3753056555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3753056555
Directory /workspace/2.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/2.usbdev_device_address.1022940252
Short name T2170
Test name
Test status
Simulation time 31344365883 ps
CPU time 48.67 seconds
Started Aug 05 05:33:09 PM PDT 24
Finished Aug 05 05:33:57 PM PDT 24
Peak memory 207636 kb
Host smart-bf9788f7-6b6f-4ef0-abb5-4d5a41b79393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10229
40252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1022940252
Directory /workspace/2.usbdev_device_address/latest


Test location /workspace/coverage/default/2.usbdev_device_timeout.4274683059
Short name T1937
Test name
Test status
Simulation time 843365440 ps
CPU time 5.19 seconds
Started Aug 05 05:33:15 PM PDT 24
Finished Aug 05 05:33:21 PM PDT 24
Peak memory 207500 kb
Host smart-20acb7ed-2c37-4a42-8aab-9de77c35fb85
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274683059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.4274683059
Directory /workspace/2.usbdev_device_timeout/latest


Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2125919812
Short name T1590
Test name
Test status
Simulation time 648802873 ps
CPU time 1.69 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:13 PM PDT 24
Peak memory 207344 kb
Host smart-e87a6ec9-9aee-4a29-a0f7-44b907d2d575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21259
19812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2125919812
Directory /workspace/2.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/2.usbdev_disconnected.2441092592
Short name T2748
Test name
Test status
Simulation time 135640421 ps
CPU time 0.86 seconds
Started Aug 05 05:33:25 PM PDT 24
Finished Aug 05 05:33:26 PM PDT 24
Peak memory 207316 kb
Host smart-651269bd-79d1-4dca-846e-3044f8591ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24410
92592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2441092592
Directory /workspace/2.usbdev_disconnected/latest


Test location /workspace/coverage/default/2.usbdev_enable.4120785904
Short name T886
Test name
Test status
Simulation time 46636692 ps
CPU time 0.72 seconds
Started Aug 05 05:33:21 PM PDT 24
Finished Aug 05 05:33:22 PM PDT 24
Peak memory 207192 kb
Host smart-0f81ea45-1a59-4839-bdeb-cd1946c2f025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41207
85904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.4120785904
Directory /workspace/2.usbdev_enable/latest


Test location /workspace/coverage/default/2.usbdev_endpoint_access.2397169519
Short name T2014
Test name
Test status
Simulation time 894925494 ps
CPU time 2.23 seconds
Started Aug 05 05:33:22 PM PDT 24
Finished Aug 05 05:33:25 PM PDT 24
Peak memory 207452 kb
Host smart-83df501c-4221-4cd9-ac90-1ed6e1e7c0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23971
69519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2397169519
Directory /workspace/2.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/2.usbdev_endpoint_types.4150361675
Short name T466
Test name
Test status
Simulation time 252670175 ps
CPU time 1.03 seconds
Started Aug 05 05:33:19 PM PDT 24
Finished Aug 05 05:33:20 PM PDT 24
Peak memory 207392 kb
Host smart-088841e9-ddc3-4b7d-b556-57dd2aa6bb74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4150361675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.4150361675
Directory /workspace/2.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/2.usbdev_fifo_rst.2300498297
Short name T646
Test name
Test status
Simulation time 329865674 ps
CPU time 2.19 seconds
Started Aug 05 05:33:18 PM PDT 24
Finished Aug 05 05:33:21 PM PDT 24
Peak memory 207496 kb
Host smart-bee2a621-7cc6-4d00-baa0-0b477fbd1a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23004
98297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2300498297
Directory /workspace/2.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/2.usbdev_freq_hiclk.3131064210
Short name T1445
Test name
Test status
Simulation time 102185617028 ps
CPU time 156.29 seconds
Started Aug 05 05:33:22 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207600 kb
Host smart-42248ed3-f768-496f-9f16-9c6d975fa175
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3131064210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.3131064210
Directory /workspace/2.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.321692941
Short name T817
Test name
Test status
Simulation time 95249907261 ps
CPU time 153.88 seconds
Started Aug 05 05:33:19 PM PDT 24
Finished Aug 05 05:35:53 PM PDT 24
Peak memory 207588 kb
Host smart-62fc871e-8edf-4334-affa-81d32baa2028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321692941 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.321692941
Directory /workspace/2.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/2.usbdev_freq_loclk.2769143412
Short name T1628
Test name
Test status
Simulation time 96160045892 ps
CPU time 149.65 seconds
Started Aug 05 05:33:17 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 207640 kb
Host smart-a0a418d0-7895-4359-8a05-24dac81fd06f
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2769143412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.2769143412
Directory /workspace/2.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.105220955
Short name T1452
Test name
Test status
Simulation time 115033088145 ps
CPU time 161.95 seconds
Started Aug 05 05:33:18 PM PDT 24
Finished Aug 05 05:36:00 PM PDT 24
Peak memory 207712 kb
Host smart-d387c6fb-cb4a-4f51-b193-fcf5afb28948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105220955 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.105220955
Directory /workspace/2.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/2.usbdev_freq_phase.3658679621
Short name T1106
Test name
Test status
Simulation time 107177438075 ps
CPU time 172.01 seconds
Started Aug 05 05:33:22 PM PDT 24
Finished Aug 05 05:36:14 PM PDT 24
Peak memory 207588 kb
Host smart-6afb05d7-8db8-4220-a5c1-2e27b8001d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36586
79621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3658679621
Directory /workspace/2.usbdev_freq_phase/latest


Test location /workspace/coverage/default/2.usbdev_in_iso.4038817508
Short name T3000
Test name
Test status
Simulation time 201382092 ps
CPU time 1.04 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:33:22 PM PDT 24
Peak memory 215680 kb
Host smart-702ba1b2-2c2b-484a-a1d7-73d7a4cb8834
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4038817508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.4038817508
Directory /workspace/2.usbdev_in_iso/latest


Test location /workspace/coverage/default/2.usbdev_in_stall.1668157312
Short name T2658
Test name
Test status
Simulation time 173554358 ps
CPU time 0.9 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:33:21 PM PDT 24
Peak memory 207252 kb
Host smart-1849d23b-b108-4f3b-a518-59308103c77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16681
57312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1668157312
Directory /workspace/2.usbdev_in_stall/latest


Test location /workspace/coverage/default/2.usbdev_in_trans.2485525064
Short name T1154
Test name
Test status
Simulation time 227860740 ps
CPU time 0.99 seconds
Started Aug 05 05:33:21 PM PDT 24
Finished Aug 05 05:33:22 PM PDT 24
Peak memory 207460 kb
Host smart-dd41d9b0-1258-4a3a-9b0a-b62b304c204f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24855
25064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2485525064
Directory /workspace/2.usbdev_in_trans/latest


Test location /workspace/coverage/default/2.usbdev_invalid_sync.67570334
Short name T1209
Test name
Test status
Simulation time 2712078198 ps
CPU time 80.09 seconds
Started Aug 05 05:33:19 PM PDT 24
Finished Aug 05 05:34:39 PM PDT 24
Peak memory 223844 kb
Host smart-6b77c0a2-dd65-42dc-ab6d-7a1f3709bd54
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=67570334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.67570334
Directory /workspace/2.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/2.usbdev_iso_retraction.2197398042
Short name T96
Test name
Test status
Simulation time 9885899781 ps
CPU time 67.09 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:34:27 PM PDT 24
Peak memory 207560 kb
Host smart-e5dec591-4c2d-4cf4-b340-046529438f11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2197398042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.2197398042
Directory /workspace/2.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/2.usbdev_link_in_err.2519997507
Short name T3008
Test name
Test status
Simulation time 174073863 ps
CPU time 0.89 seconds
Started Aug 05 05:33:21 PM PDT 24
Finished Aug 05 05:33:22 PM PDT 24
Peak memory 207376 kb
Host smart-688498d9-50c7-4713-b155-181866dd892b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25199
97507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2519997507
Directory /workspace/2.usbdev_link_in_err/latest


Test location /workspace/coverage/default/2.usbdev_link_resume.3861871116
Short name T1346
Test name
Test status
Simulation time 24094804139 ps
CPU time 29.29 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:33:49 PM PDT 24
Peak memory 207548 kb
Host smart-df80d4d2-4fce-4716-9257-24d80ad37ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38618
71116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3861871116
Directory /workspace/2.usbdev_link_resume/latest


Test location /workspace/coverage/default/2.usbdev_link_suspend.3898712715
Short name T2560
Test name
Test status
Simulation time 4922294637 ps
CPU time 7.1 seconds
Started Aug 05 05:33:19 PM PDT 24
Finished Aug 05 05:33:26 PM PDT 24
Peak memory 215836 kb
Host smart-aacc8ac2-b4e7-49f6-bf4f-f93d02bbf75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38987
12715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3898712715
Directory /workspace/2.usbdev_link_suspend/latest


Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2874020208
Short name T3011
Test name
Test status
Simulation time 4606670856 ps
CPU time 126.04 seconds
Started Aug 05 05:33:22 PM PDT 24
Finished Aug 05 05:35:29 PM PDT 24
Peak memory 218368 kb
Host smart-e5e800f6-c093-494b-8165-91a003d237c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28740
20208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2874020208
Directory /workspace/2.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3601069044
Short name T528
Test name
Test status
Simulation time 2762963768 ps
CPU time 29.09 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:33:49 PM PDT 24
Peak memory 217516 kb
Host smart-563d2715-e57f-44ba-ba7e-bf18e50486c4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3601069044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3601069044
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.315538076
Short name T1001
Test name
Test status
Simulation time 249442671 ps
CPU time 1.02 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:33:21 PM PDT 24
Peak memory 207252 kb
Host smart-f4616faa-54dd-4a6d-acdd-a9cc897cd023
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=315538076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.315538076
Directory /workspace/2.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2331055312
Short name T23
Test name
Test status
Simulation time 204487303 ps
CPU time 0.93 seconds
Started Aug 05 05:33:19 PM PDT 24
Finished Aug 05 05:33:20 PM PDT 24
Peak memory 207368 kb
Host smart-61f41914-4737-4f49-85da-fff9e6dfc82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23310
55312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2331055312
Directory /workspace/2.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.3959751634
Short name T953
Test name
Test status
Simulation time 2979685636 ps
CPU time 30.8 seconds
Started Aug 05 05:33:23 PM PDT 24
Finished Aug 05 05:33:54 PM PDT 24
Peak memory 215784 kb
Host smart-ea64c9b1-5739-4ca7-9e54-35580d9c945d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39597
51634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.3959751634
Directory /workspace/2.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1642783152
Short name T1953
Test name
Test status
Simulation time 2929569439 ps
CPU time 23.41 seconds
Started Aug 05 05:33:21 PM PDT 24
Finished Aug 05 05:33:45 PM PDT 24
Peak memory 217760 kb
Host smart-2b2db469-d9b9-4cfd-b5ea-5a6d8f329120
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1642783152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1642783152
Directory /workspace/2.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.519839330
Short name T1819
Test name
Test status
Simulation time 2946626787 ps
CPU time 32.34 seconds
Started Aug 05 05:33:17 PM PDT 24
Finished Aug 05 05:33:50 PM PDT 24
Peak memory 216792 kb
Host smart-12f08a5c-a809-40e1-8902-6865543f27c3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=519839330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.519839330
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.2924247868
Short name T2480
Test name
Test status
Simulation time 211028001 ps
CPU time 0.93 seconds
Started Aug 05 05:33:21 PM PDT 24
Finished Aug 05 05:33:22 PM PDT 24
Peak memory 207240 kb
Host smart-0adca92a-7be1-43f8-9d29-5c281fce77e9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2924247868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.2924247868
Directory /workspace/2.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1711378832
Short name T1941
Test name
Test status
Simulation time 149806483 ps
CPU time 0.84 seconds
Started Aug 05 05:33:21 PM PDT 24
Finished Aug 05 05:33:22 PM PDT 24
Peak memory 207344 kb
Host smart-274a0f85-3e74-4965-a113-55f720184180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17113
78832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1711378832
Directory /workspace/2.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/2.usbdev_nak_trans.3329053148
Short name T147
Test name
Test status
Simulation time 227413830 ps
CPU time 1.04 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:33:21 PM PDT 24
Peak memory 207384 kb
Host smart-4eb3fab0-defe-4a7c-9b32-29360a89d79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33290
53148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3329053148
Directory /workspace/2.usbdev_nak_trans/latest


Test location /workspace/coverage/default/2.usbdev_out_iso.1267932994
Short name T2468
Test name
Test status
Simulation time 186670196 ps
CPU time 0.93 seconds
Started Aug 05 05:33:19 PM PDT 24
Finished Aug 05 05:33:20 PM PDT 24
Peak memory 207268 kb
Host smart-a9bbff7b-cd90-4e33-bf89-18b844db875c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12679
32994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1267932994
Directory /workspace/2.usbdev_out_iso/latest


Test location /workspace/coverage/default/2.usbdev_out_stall.2245382348
Short name T1065
Test name
Test status
Simulation time 163232017 ps
CPU time 0.93 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:33:21 PM PDT 24
Peak memory 207380 kb
Host smart-94afec58-b744-4e77-9f85-80b7b698a2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22453
82348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2245382348
Directory /workspace/2.usbdev_out_stall/latest


Test location /workspace/coverage/default/2.usbdev_out_trans_nak.4244912794
Short name T1267
Test name
Test status
Simulation time 203603758 ps
CPU time 0.88 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:33:21 PM PDT 24
Peak memory 207324 kb
Host smart-6048f81e-6fb3-4521-8812-e042711b2673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42449
12794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.4244912794
Directory /workspace/2.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2518981122
Short name T1825
Test name
Test status
Simulation time 170996217 ps
CPU time 0.89 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:33:21 PM PDT 24
Peak memory 207292 kb
Host smart-788ace2d-83d8-4185-8777-b927c13071c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25189
81122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2518981122
Directory /workspace/2.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3350350995
Short name T2433
Test name
Test status
Simulation time 216080354 ps
CPU time 0.96 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:33:21 PM PDT 24
Peak memory 207272 kb
Host smart-0b1a5d65-ffca-4dde-8ee0-30e613af4eb0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3350350995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3350350995
Directory /workspace/2.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1600841405
Short name T209
Test name
Test status
Simulation time 211285795 ps
CPU time 1.1 seconds
Started Aug 05 05:33:21 PM PDT 24
Finished Aug 05 05:33:23 PM PDT 24
Peak memory 207428 kb
Host smart-fc4f2fb7-4568-4b69-8252-a91b7723647a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16008
41405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1600841405
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.386036491
Short name T2381
Test name
Test status
Simulation time 149796023 ps
CPU time 0.89 seconds
Started Aug 05 05:33:21 PM PDT 24
Finished Aug 05 05:33:22 PM PDT 24
Peak memory 207320 kb
Host smart-2bc35fbf-c754-4de5-9f13-cf41e5e75c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38603
6491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.386036491
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3205666488
Short name T40
Test name
Test status
Simulation time 39995910 ps
CPU time 0.7 seconds
Started Aug 05 05:33:21 PM PDT 24
Finished Aug 05 05:33:22 PM PDT 24
Peak memory 207204 kb
Host smart-f2a9b14d-7f08-4c3a-a644-aff51afa3d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32056
66488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3205666488
Directory /workspace/2.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/2.usbdev_pkt_buffer.522238628
Short name T1793
Test name
Test status
Simulation time 16667956360 ps
CPU time 48.2 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:34:08 PM PDT 24
Peak memory 220812 kb
Host smart-9359e42f-2ee1-47c4-a1fe-16783a6f60bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52223
8628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.522238628
Directory /workspace/2.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/2.usbdev_pkt_received.4042336388
Short name T781
Test name
Test status
Simulation time 208910510 ps
CPU time 0.93 seconds
Started Aug 05 05:33:22 PM PDT 24
Finished Aug 05 05:33:24 PM PDT 24
Peak memory 207268 kb
Host smart-e1f3952d-a053-4f7b-8511-2f5ac0a1d65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40423
36388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.4042336388
Directory /workspace/2.usbdev_pkt_received/latest


Test location /workspace/coverage/default/2.usbdev_pkt_sent.896467494
Short name T1541
Test name
Test status
Simulation time 213124524 ps
CPU time 1 seconds
Started Aug 05 05:33:18 PM PDT 24
Finished Aug 05 05:33:20 PM PDT 24
Peak memory 207396 kb
Host smart-d7e36af5-d60d-4b57-97cf-82d3d5043876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89646
7494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.896467494
Directory /workspace/2.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.2481992310
Short name T1838
Test name
Test status
Simulation time 9482401590 ps
CPU time 161.53 seconds
Started Aug 05 05:33:34 PM PDT 24
Finished Aug 05 05:36:16 PM PDT 24
Peak memory 223964 kb
Host smart-055c1d5d-2248-49da-9ba4-807ef4594c95
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481992310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.2481992310
Directory /workspace/2.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1075856202
Short name T919
Test name
Test status
Simulation time 8535274072 ps
CPU time 226.33 seconds
Started Aug 05 05:33:30 PM PDT 24
Finished Aug 05 05:37:16 PM PDT 24
Peak memory 218436 kb
Host smart-e99f8313-e7c4-44d5-9bce-94dd6d41a9a3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1075856202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1075856202
Directory /workspace/2.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/2.usbdev_rand_suspends.1257714143
Short name T1686
Test name
Test status
Simulation time 9284529970 ps
CPU time 159.89 seconds
Started Aug 05 05:33:32 PM PDT 24
Finished Aug 05 05:36:12 PM PDT 24
Peak memory 224032 kb
Host smart-5d59b70c-6138-49b5-ae91-2a3a5c55dbf9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257714143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.1257714143
Directory /workspace/2.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1627566305
Short name T2485
Test name
Test status
Simulation time 184124859 ps
CPU time 0.89 seconds
Started Aug 05 05:33:20 PM PDT 24
Finished Aug 05 05:33:21 PM PDT 24
Peak memory 207300 kb
Host smart-57a28cda-c513-4c08-8ab9-7f9b6dacc3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16275
66305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1627566305
Directory /workspace/2.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.2144818415
Short name T2749
Test name
Test status
Simulation time 149724563 ps
CPU time 0.88 seconds
Started Aug 05 05:33:22 PM PDT 24
Finished Aug 05 05:33:23 PM PDT 24
Peak memory 207348 kb
Host smart-ea35713b-8728-4d4a-98ac-c0d5bdcd7a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21448
18415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.2144818415
Directory /workspace/2.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/2.usbdev_resume_link_active.533496329
Short name T2794
Test name
Test status
Simulation time 20222569411 ps
CPU time 26.87 seconds
Started Aug 05 05:33:28 PM PDT 24
Finished Aug 05 05:33:55 PM PDT 24
Peak memory 207480 kb
Host smart-8ded214b-8cde-4d4e-ad02-9b9826e4a963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53349
6329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.533496329
Directory /workspace/2.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/2.usbdev_rx_crc_err.4051520349
Short name T2234
Test name
Test status
Simulation time 163888151 ps
CPU time 0.83 seconds
Started Aug 05 05:33:29 PM PDT 24
Finished Aug 05 05:33:30 PM PDT 24
Peak memory 207348 kb
Host smart-b5ac66c0-f2e2-42fa-b0b8-f79c9acb589f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40515
20349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.4051520349
Directory /workspace/2.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/2.usbdev_rx_full.2479419396
Short name T287
Test name
Test status
Simulation time 292946045 ps
CPU time 1.12 seconds
Started Aug 05 05:33:31 PM PDT 24
Finished Aug 05 05:33:32 PM PDT 24
Peak memory 207348 kb
Host smart-b2d31285-7164-4f90-993f-ea917d276ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24794
19396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.2479419396
Directory /workspace/2.usbdev_rx_full/latest


Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1713175730
Short name T85
Test name
Test status
Simulation time 176142312 ps
CPU time 0.87 seconds
Started Aug 05 05:33:29 PM PDT 24
Finished Aug 05 05:33:30 PM PDT 24
Peak memory 207364 kb
Host smart-c55d8991-752e-421b-95b4-617cab8753ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131
75730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1713175730
Directory /workspace/2.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/2.usbdev_sec_cm.3708268509
Short name T215
Test name
Test status
Simulation time 997152114 ps
CPU time 1.74 seconds
Started Aug 05 05:33:28 PM PDT 24
Finished Aug 05 05:33:30 PM PDT 24
Peak memory 223420 kb
Host smart-26bf745f-9a8b-4519-af6d-6b98a78e7456
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3708268509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3708268509
Directory /workspace/2.usbdev_sec_cm/latest


Test location /workspace/coverage/default/2.usbdev_setup_priority.1429700495
Short name T60
Test name
Test status
Simulation time 482142840 ps
CPU time 1.64 seconds
Started Aug 05 05:33:32 PM PDT 24
Finished Aug 05 05:33:34 PM PDT 24
Peak memory 207328 kb
Host smart-ce665c39-69e3-498c-9786-2cd965e9a137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14297
00495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1429700495
Directory /workspace/2.usbdev_setup_priority/latest


Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.1457440575
Short name T2429
Test name
Test status
Simulation time 199057743 ps
CPU time 0.98 seconds
Started Aug 05 05:33:28 PM PDT 24
Finished Aug 05 05:33:29 PM PDT 24
Peak memory 207260 kb
Host smart-dbca40a9-caf4-4f91-a28a-183f795216d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14574
40575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.1457440575
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/2.usbdev_setup_stage.3937165452
Short name T1784
Test name
Test status
Simulation time 151177476 ps
CPU time 0.83 seconds
Started Aug 05 05:33:29 PM PDT 24
Finished Aug 05 05:33:30 PM PDT 24
Peak memory 207352 kb
Host smart-a7891f2f-5929-4590-8d0b-1efaf0b5b3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39371
65452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3937165452
Directory /workspace/2.usbdev_setup_stage/latest


Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.4273454052
Short name T2758
Test name
Test status
Simulation time 141035227 ps
CPU time 0.84 seconds
Started Aug 05 05:33:30 PM PDT 24
Finished Aug 05 05:33:31 PM PDT 24
Peak memory 207384 kb
Host smart-84e80179-3631-46a9-b9ac-dc7f5190ee7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42734
54052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.4273454052
Directory /workspace/2.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/2.usbdev_smoke.567534585
Short name T1609
Test name
Test status
Simulation time 219632375 ps
CPU time 1.02 seconds
Started Aug 05 05:33:31 PM PDT 24
Finished Aug 05 05:33:32 PM PDT 24
Peak memory 207344 kb
Host smart-ef107630-1cff-479e-8075-06555ef50b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56753
4585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.567534585
Directory /workspace/2.usbdev_smoke/latest


Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.3298981782
Short name T1509
Test name
Test status
Simulation time 2761560065 ps
CPU time 19.96 seconds
Started Aug 05 05:33:34 PM PDT 24
Finished Aug 05 05:33:54 PM PDT 24
Peak memory 223896 kb
Host smart-fc1953fb-40df-4f88-9b3a-7c53be6bdaac
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3298981782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.3298981782
Directory /workspace/2.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.965631932
Short name T1956
Test name
Test status
Simulation time 189561859 ps
CPU time 0.89 seconds
Started Aug 05 05:33:30 PM PDT 24
Finished Aug 05 05:33:31 PM PDT 24
Peak memory 207300 kb
Host smart-44ed7d94-5cb1-4a00-ae2d-521c5f84312b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96563
1932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.965631932
Directory /workspace/2.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/2.usbdev_stall_trans.3132608840
Short name T1968
Test name
Test status
Simulation time 160254595 ps
CPU time 0.87 seconds
Started Aug 05 05:33:29 PM PDT 24
Finished Aug 05 05:33:30 PM PDT 24
Peak memory 207256 kb
Host smart-31d33260-7741-42a6-a35d-29f039ef7501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31326
08840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3132608840
Directory /workspace/2.usbdev_stall_trans/latest


Test location /workspace/coverage/default/2.usbdev_stream_len_max.1825451368
Short name T3050
Test name
Test status
Simulation time 732038464 ps
CPU time 1.82 seconds
Started Aug 05 05:33:32 PM PDT 24
Finished Aug 05 05:33:34 PM PDT 24
Peak memory 207344 kb
Host smart-334246bd-4f5a-4107-af44-a4fa337bc8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18254
51368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.1825451368
Directory /workspace/2.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/2.usbdev_streaming_out.201715801
Short name T3022
Test name
Test status
Simulation time 2986796757 ps
CPU time 84.24 seconds
Started Aug 05 05:33:30 PM PDT 24
Finished Aug 05 05:34:54 PM PDT 24
Peak memory 217140 kb
Host smart-c724d106-7ed4-4058-b24b-ac54a8380876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20171
5801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.201715801
Directory /workspace/2.usbdev_streaming_out/latest


Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.3600568405
Short name T2890
Test name
Test status
Simulation time 1302470227 ps
CPU time 30.11 seconds
Started Aug 05 05:33:11 PM PDT 24
Finished Aug 05 05:33:41 PM PDT 24
Peak memory 207600 kb
Host smart-55af354a-5441-484b-8149-bfb86cfc5f86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600568405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.3600568405
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/20.usbdev_alert_test.2613044738
Short name T635
Test name
Test status
Simulation time 43697123 ps
CPU time 0.67 seconds
Started Aug 05 05:36:36 PM PDT 24
Finished Aug 05 05:36:37 PM PDT 24
Peak memory 207460 kb
Host smart-9a2344e5-fd0b-4d7d-8c83-5131119ef4fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2613044738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.2613044738
Directory /workspace/20.usbdev_alert_test/latest


Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.225153127
Short name T2616
Test name
Test status
Simulation time 11182878197 ps
CPU time 12.9 seconds
Started Aug 05 05:36:24 PM PDT 24
Finished Aug 05 05:36:37 PM PDT 24
Peak memory 207512 kb
Host smart-a00b04d0-abae-4427-9bbe-d34d8595daa6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225153127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_ao
n_wake_disconnect.225153127
Directory /workspace/20.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2157225730
Short name T2153
Test name
Test status
Simulation time 15538182598 ps
CPU time 18.3 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 215816 kb
Host smart-39f9b742-37d5-4cb2-b7c8-f84c19fa7724
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157225730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2157225730
Directory /workspace/20.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.2691307300
Short name T1046
Test name
Test status
Simulation time 24837869062 ps
CPU time 29.09 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:56 PM PDT 24
Peak memory 215740 kb
Host smart-66de977d-85d2-4743-a984-e238fcf55085
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691307300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.2691307300
Directory /workspace/20.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/20.usbdev_av_buffer.4131814779
Short name T1783
Test name
Test status
Simulation time 203857755 ps
CPU time 0.96 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207296 kb
Host smart-35725aa1-f2e4-4951-b372-050fab2d0400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41318
14779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.4131814779
Directory /workspace/20.usbdev_av_buffer/latest


Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1455330802
Short name T802
Test name
Test status
Simulation time 152759112 ps
CPU time 0.85 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:29 PM PDT 24
Peak memory 207236 kb
Host smart-f34cbf45-6249-49ec-a287-79b5fcf7c403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14553
30802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1455330802
Directory /workspace/20.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.4232935337
Short name T1699
Test name
Test status
Simulation time 345759173 ps
CPU time 1.35 seconds
Started Aug 05 05:36:28 PM PDT 24
Finished Aug 05 05:36:29 PM PDT 24
Peak memory 207376 kb
Host smart-81725d58-cad9-4c35-aab3-1a85e98884ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42329
35337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.4232935337
Directory /workspace/20.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2561823385
Short name T1193
Test name
Test status
Simulation time 831044313 ps
CPU time 2.18 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:36:29 PM PDT 24
Peak memory 207560 kb
Host smart-99e98c25-d724-4390-b18a-a758b2c51006
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2561823385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2561823385
Directory /workspace/20.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/20.usbdev_device_address.3767510188
Short name T169
Test name
Test status
Simulation time 43028344532 ps
CPU time 67 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:37:33 PM PDT 24
Peak memory 207552 kb
Host smart-edbeb3ae-2e20-4046-a6d7-7567bc8c9a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37675
10188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3767510188
Directory /workspace/20.usbdev_device_address/latest


Test location /workspace/coverage/default/20.usbdev_device_timeout.1736253397
Short name T2554
Test name
Test status
Simulation time 1522051513 ps
CPU time 13.49 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:36:40 PM PDT 24
Peak memory 207392 kb
Host smart-2783da75-7fe7-4cbd-96cb-5144cc910a62
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736253397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.1736253397
Directory /workspace/20.usbdev_device_timeout/latest


Test location /workspace/coverage/default/20.usbdev_disable_endpoint.2949007872
Short name T2652
Test name
Test status
Simulation time 1167121569 ps
CPU time 2.89 seconds
Started Aug 05 05:36:28 PM PDT 24
Finished Aug 05 05:36:31 PM PDT 24
Peak memory 207300 kb
Host smart-784294ca-4ed9-449c-bb43-50d3795238c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29490
07872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2949007872
Directory /workspace/20.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/20.usbdev_disconnected.2899577550
Short name T1370
Test name
Test status
Simulation time 146580443 ps
CPU time 0.84 seconds
Started Aug 05 05:36:25 PM PDT 24
Finished Aug 05 05:36:26 PM PDT 24
Peak memory 207220 kb
Host smart-dcfa713d-5207-4c0b-aa98-259bb0e81447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28995
77550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2899577550
Directory /workspace/20.usbdev_disconnected/latest


Test location /workspace/coverage/default/20.usbdev_enable.787337469
Short name T1997
Test name
Test status
Simulation time 33424022 ps
CPU time 0.7 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:36:27 PM PDT 24
Peak memory 207220 kb
Host smart-4f86a6df-33a0-4135-97e4-37953a86296a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78733
7469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.787337469
Directory /workspace/20.usbdev_enable/latest


Test location /workspace/coverage/default/20.usbdev_endpoint_access.3814348222
Short name T651
Test name
Test status
Simulation time 873444447 ps
CPU time 2.38 seconds
Started Aug 05 05:36:28 PM PDT 24
Finished Aug 05 05:36:30 PM PDT 24
Peak memory 207536 kb
Host smart-53a53c51-4e82-4ec0-8b60-efc180e69bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38143
48222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3814348222
Directory /workspace/20.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/20.usbdev_endpoint_types.704436498
Short name T380
Test name
Test status
Simulation time 649447927 ps
CPU time 1.47 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207324 kb
Host smart-fd03324e-fbe1-4d87-9365-7fd4b894f76d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=704436498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.704436498
Directory /workspace/20.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/20.usbdev_fifo_rst.2489630103
Short name T2823
Test name
Test status
Simulation time 326759184 ps
CPU time 2.01 seconds
Started Aug 05 05:36:25 PM PDT 24
Finished Aug 05 05:36:27 PM PDT 24
Peak memory 207476 kb
Host smart-66276e2f-ae5b-4567-8ebf-cac365a862f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24896
30103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2489630103
Directory /workspace/20.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/20.usbdev_in_iso.2285471539
Short name T1432
Test name
Test status
Simulation time 220346436 ps
CPU time 1.19 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:29 PM PDT 24
Peak memory 207548 kb
Host smart-236d1107-3e2f-46c4-b5f6-363402d946ad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2285471539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2285471539
Directory /workspace/20.usbdev_in_iso/latest


Test location /workspace/coverage/default/20.usbdev_in_stall.65877966
Short name T2687
Test name
Test status
Simulation time 163274526 ps
CPU time 0.89 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207360 kb
Host smart-378bf782-3701-4833-81d4-a09e0e812d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65877
966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.65877966
Directory /workspace/20.usbdev_in_stall/latest


Test location /workspace/coverage/default/20.usbdev_in_trans.1412564681
Short name T1900
Test name
Test status
Simulation time 243698549 ps
CPU time 1 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:28 PM PDT 24
Peak memory 207288 kb
Host smart-5a82aa5d-c469-4435-8126-8640bbbafad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14125
64681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1412564681
Directory /workspace/20.usbdev_in_trans/latest


Test location /workspace/coverage/default/20.usbdev_invalid_sync.2846049223
Short name T2363
Test name
Test status
Simulation time 2510353934 ps
CPU time 18.48 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 215912 kb
Host smart-bf95859d-8cde-4cac-85f8-ad06f438c610
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2846049223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2846049223
Directory /workspace/20.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/20.usbdev_link_in_err.1821656313
Short name T1263
Test name
Test status
Simulation time 192564594 ps
CPU time 0.9 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:36:27 PM PDT 24
Peak memory 207360 kb
Host smart-37ae096d-52f3-44ff-a94b-7331faaa8dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18216
56313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.1821656313
Directory /workspace/20.usbdev_link_in_err/latest


Test location /workspace/coverage/default/20.usbdev_link_resume.3127865403
Short name T1417
Test name
Test status
Simulation time 31236846861 ps
CPU time 56.4 seconds
Started Aug 05 05:36:26 PM PDT 24
Finished Aug 05 05:37:22 PM PDT 24
Peak memory 207760 kb
Host smart-af66436a-7b5c-43f8-883e-198b9442f4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31278
65403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.3127865403
Directory /workspace/20.usbdev_link_resume/latest


Test location /workspace/coverage/default/20.usbdev_link_suspend.2355771099
Short name T1063
Test name
Test status
Simulation time 9905892000 ps
CPU time 12.02 seconds
Started Aug 05 05:36:28 PM PDT 24
Finished Aug 05 05:36:40 PM PDT 24
Peak memory 207656 kb
Host smart-bca8bb6b-e569-4232-9139-54a528fca684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23557
71099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2355771099
Directory /workspace/20.usbdev_link_suspend/latest


Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.4181871880
Short name T2800
Test name
Test status
Simulation time 3564606729 ps
CPU time 32.91 seconds
Started Aug 05 05:36:29 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 218384 kb
Host smart-e309c0a2-508e-48a1-9f69-06b4ed3da01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41818
71880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.4181871880
Directory /workspace/20.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2439311661
Short name T2666
Test name
Test status
Simulation time 2937432369 ps
CPU time 22.03 seconds
Started Aug 05 05:36:27 PM PDT 24
Finished Aug 05 05:36:49 PM PDT 24
Peak memory 215800 kb
Host smart-0271da4e-435f-4d54-953f-d964610d12c0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2439311661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2439311661
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.57629930
Short name T1587
Test name
Test status
Simulation time 241988106 ps
CPU time 1.01 seconds
Started Aug 05 05:36:28 PM PDT 24
Finished Aug 05 05:36:29 PM PDT 24
Peak memory 207376 kb
Host smart-d99d7b58-6426-4362-abaa-3028ea48db02
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=57629930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.57629930
Directory /workspace/20.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1275281958
Short name T2219
Test name
Test status
Simulation time 231952314 ps
CPU time 1 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 207348 kb
Host smart-c679d28e-25fc-485f-b45e-eeeda1f940ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12752
81958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1275281958
Directory /workspace/20.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.2257809804
Short name T535
Test name
Test status
Simulation time 1953489955 ps
CPU time 14.94 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:36:57 PM PDT 24
Peak memory 207420 kb
Host smart-cf4d0786-6193-4e44-a36b-1347000041c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22578
09804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.2257809804
Directory /workspace/20.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2804549190
Short name T1448
Test name
Test status
Simulation time 3370285097 ps
CPU time 98.5 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 215856 kb
Host smart-bfb102cd-966f-4e80-83f6-232c38ef1555
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2804549190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2804549190
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1447444989
Short name T2690
Test name
Test status
Simulation time 198008471 ps
CPU time 0.87 seconds
Started Aug 05 05:36:35 PM PDT 24
Finished Aug 05 05:36:36 PM PDT 24
Peak memory 207252 kb
Host smart-82617b6a-56bb-4af2-b995-2dc40f7a83c3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1447444989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1447444989
Directory /workspace/20.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2342468930
Short name T2211
Test name
Test status
Simulation time 184683030 ps
CPU time 0.89 seconds
Started Aug 05 05:36:36 PM PDT 24
Finished Aug 05 05:36:37 PM PDT 24
Peak memory 207376 kb
Host smart-624c2334-1bbe-449e-9348-b6d98c4e69b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23424
68930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2342468930
Directory /workspace/20.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/20.usbdev_nak_trans.1003621755
Short name T138
Test name
Test status
Simulation time 230655080 ps
CPU time 0.94 seconds
Started Aug 05 05:36:32 PM PDT 24
Finished Aug 05 05:36:33 PM PDT 24
Peak memory 207604 kb
Host smart-45030c04-9929-44bb-ace1-886babd370c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10036
21755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1003621755
Directory /workspace/20.usbdev_nak_trans/latest


Test location /workspace/coverage/default/20.usbdev_out_iso.3911642136
Short name T1891
Test name
Test status
Simulation time 144505986 ps
CPU time 0.83 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 207376 kb
Host smart-a454516a-e145-43d8-b10c-9040fbda3183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39116
42136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3911642136
Directory /workspace/20.usbdev_out_iso/latest


Test location /workspace/coverage/default/20.usbdev_out_stall.1158785781
Short name T1962
Test name
Test status
Simulation time 186533745 ps
CPU time 0.89 seconds
Started Aug 05 05:36:33 PM PDT 24
Finished Aug 05 05:36:34 PM PDT 24
Peak memory 207368 kb
Host smart-e12bc0e0-629e-490c-a4db-cf0f201bad13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11587
85781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1158785781
Directory /workspace/20.usbdev_out_stall/latest


Test location /workspace/coverage/default/20.usbdev_out_trans_nak.387573089
Short name T2135
Test name
Test status
Simulation time 161116265 ps
CPU time 0.81 seconds
Started Aug 05 05:36:32 PM PDT 24
Finished Aug 05 05:36:38 PM PDT 24
Peak memory 207352 kb
Host smart-d77b2f16-d7a9-4401-9b4e-d7e16e0c2e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38757
3089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.387573089
Directory /workspace/20.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/20.usbdev_pending_in_trans.4134427812
Short name T170
Test name
Test status
Simulation time 167423007 ps
CPU time 0.83 seconds
Started Aug 05 05:36:45 PM PDT 24
Finished Aug 05 05:36:47 PM PDT 24
Peak memory 207340 kb
Host smart-71098e78-e2b5-45a4-9fff-369c3bab28a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41344
27812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.4134427812
Directory /workspace/20.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.1219836997
Short name T1728
Test name
Test status
Simulation time 244608968 ps
CPU time 1.06 seconds
Started Aug 05 05:36:40 PM PDT 24
Finished Aug 05 05:36:41 PM PDT 24
Peak memory 207412 kb
Host smart-de757607-926e-4d24-9a37-5b704a253936
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1219836997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1219836997
Directory /workspace/20.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.330239908
Short name T1591
Test name
Test status
Simulation time 176792814 ps
CPU time 0.88 seconds
Started Aug 05 05:36:38 PM PDT 24
Finished Aug 05 05:36:39 PM PDT 24
Peak memory 207316 kb
Host smart-d9d2e48f-270e-4e1a-acee-c4a00947da82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33023
9908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.330239908
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3040798355
Short name T1789
Test name
Test status
Simulation time 41678481 ps
CPU time 0.7 seconds
Started Aug 05 05:36:42 PM PDT 24
Finished Aug 05 05:36:43 PM PDT 24
Peak memory 207232 kb
Host smart-10ff1ac7-b295-4b47-b2bb-bfd9316fa43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30407
98355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3040798355
Directory /workspace/20.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/20.usbdev_pkt_buffer.873697372
Short name T1742
Test name
Test status
Simulation time 15364243685 ps
CPU time 40.81 seconds
Started Aug 05 05:36:39 PM PDT 24
Finished Aug 05 05:37:20 PM PDT 24
Peak memory 215832 kb
Host smart-1ff30b8a-2b51-4fdb-a7d5-7210afc254bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87369
7372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.873697372
Directory /workspace/20.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/20.usbdev_pkt_received.3432750994
Short name T2424
Test name
Test status
Simulation time 185872508 ps
CPU time 0.87 seconds
Started Aug 05 05:36:35 PM PDT 24
Finished Aug 05 05:36:36 PM PDT 24
Peak memory 207368 kb
Host smart-06cd15da-d366-442b-ba5d-aeeb538369ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34327
50994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3432750994
Directory /workspace/20.usbdev_pkt_received/latest


Test location /workspace/coverage/default/20.usbdev_pkt_sent.1734507998
Short name T929
Test name
Test status
Simulation time 162985357 ps
CPU time 0.94 seconds
Started Aug 05 05:36:32 PM PDT 24
Finished Aug 05 05:36:33 PM PDT 24
Peak memory 207240 kb
Host smart-f75df459-e77d-445b-b7da-43c38f6bf675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17345
07998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1734507998
Directory /workspace/20.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.727904398
Short name T611
Test name
Test status
Simulation time 187499193 ps
CPU time 0.93 seconds
Started Aug 05 05:36:31 PM PDT 24
Finished Aug 05 05:36:32 PM PDT 24
Peak memory 207400 kb
Host smart-04154859-973c-451c-947f-3700ff299015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72790
4398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.727904398
Directory /workspace/20.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.1051518153
Short name T2172
Test name
Test status
Simulation time 184159298 ps
CPU time 0.89 seconds
Started Aug 05 05:36:42 PM PDT 24
Finished Aug 05 05:36:43 PM PDT 24
Peak memory 207352 kb
Host smart-ef90a695-1490-48b5-b763-a7d40bd2c6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10515
18153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.1051518153
Directory /workspace/20.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3305485608
Short name T1380
Test name
Test status
Simulation time 167639530 ps
CPU time 0.88 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:36:42 PM PDT 24
Peak memory 207348 kb
Host smart-fd499825-0b44-403f-90dc-18eefadaca53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33054
85608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3305485608
Directory /workspace/20.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/20.usbdev_rx_full.3195299113
Short name T1020
Test name
Test status
Simulation time 411964278 ps
CPU time 1.37 seconds
Started Aug 05 05:36:32 PM PDT 24
Finished Aug 05 05:36:34 PM PDT 24
Peak memory 207268 kb
Host smart-684b279a-ddef-4448-b3e4-5abfb4c6b881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31952
99113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.3195299113
Directory /workspace/20.usbdev_rx_full/latest


Test location /workspace/coverage/default/20.usbdev_setup_stage.235103562
Short name T2388
Test name
Test status
Simulation time 186095928 ps
CPU time 0.87 seconds
Started Aug 05 05:36:31 PM PDT 24
Finished Aug 05 05:36:32 PM PDT 24
Peak memory 207256 kb
Host smart-6d53236e-fd12-4113-8a5b-4b4863024f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23510
3562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.235103562
Directory /workspace/20.usbdev_setup_stage/latest


Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3077601157
Short name T545
Test name
Test status
Simulation time 156969835 ps
CPU time 0.86 seconds
Started Aug 05 05:36:36 PM PDT 24
Finished Aug 05 05:36:37 PM PDT 24
Peak memory 207368 kb
Host smart-c8588a81-2381-4662-88cd-ed6093b4915f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30776
01157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3077601157
Directory /workspace/20.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/20.usbdev_smoke.3653992992
Short name T935
Test name
Test status
Simulation time 195647353 ps
CPU time 0.99 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:36:42 PM PDT 24
Peak memory 207320 kb
Host smart-9df8ed0c-426b-4d94-88dd-08ce4c238a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36539
92992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3653992992
Directory /workspace/20.usbdev_smoke/latest


Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1662775946
Short name T2421
Test name
Test status
Simulation time 2978100208 ps
CPU time 27.65 seconds
Started Aug 05 05:36:40 PM PDT 24
Finished Aug 05 05:37:07 PM PDT 24
Peak memory 217760 kb
Host smart-a17335a6-2f84-4542-bc0e-a1438b140e72
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1662775946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1662775946
Directory /workspace/20.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.716813077
Short name T2178
Test name
Test status
Simulation time 172892565 ps
CPU time 0.88 seconds
Started Aug 05 05:36:38 PM PDT 24
Finished Aug 05 05:36:39 PM PDT 24
Peak memory 207272 kb
Host smart-d1c23132-c97e-469b-9a7f-f7de29dafd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71681
3077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.716813077
Directory /workspace/20.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/20.usbdev_stall_trans.1459480305
Short name T1161
Test name
Test status
Simulation time 182823015 ps
CPU time 0.97 seconds
Started Aug 05 05:36:34 PM PDT 24
Finished Aug 05 05:36:35 PM PDT 24
Peak memory 207372 kb
Host smart-2156919a-ebb9-451a-b3ac-b9cb0101a7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14594
80305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1459480305
Directory /workspace/20.usbdev_stall_trans/latest


Test location /workspace/coverage/default/20.usbdev_stream_len_max.397385351
Short name T889
Test name
Test status
Simulation time 651689484 ps
CPU time 1.84 seconds
Started Aug 05 05:36:32 PM PDT 24
Finished Aug 05 05:36:34 PM PDT 24
Peak memory 207220 kb
Host smart-da5d0d00-2684-417c-8072-b5330fff21fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39738
5351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.397385351
Directory /workspace/20.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/20.usbdev_streaming_out.2179220444
Short name T3073
Test name
Test status
Simulation time 4009214051 ps
CPU time 30.77 seconds
Started Aug 05 05:36:37 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 215876 kb
Host smart-5c28b3fb-0780-4d3b-bb3b-b5d40fd4464c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21792
20444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2179220444
Directory /workspace/20.usbdev_streaming_out/latest


Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.1247206257
Short name T2672
Test name
Test status
Simulation time 2046826494 ps
CPU time 16.97 seconds
Started Aug 05 05:36:25 PM PDT 24
Finished Aug 05 05:36:42 PM PDT 24
Peak memory 207516 kb
Host smart-8bf92c3b-b9e3-4763-a473-dafa2d5252e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247206257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.1247206257
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/21.usbdev_alert_test.290688851
Short name T813
Test name
Test status
Simulation time 43411845 ps
CPU time 0.66 seconds
Started Aug 05 05:36:42 PM PDT 24
Finished Aug 05 05:36:43 PM PDT 24
Peak memory 207332 kb
Host smart-ed2c3b74-e153-443f-a84e-0b94ee002b1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=290688851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.290688851
Directory /workspace/21.usbdev_alert_test/latest


Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2738964794
Short name T1212
Test name
Test status
Simulation time 11300786680 ps
CPU time 14.2 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:36:55 PM PDT 24
Peak memory 207536 kb
Host smart-fe41ce80-fc8d-42a2-8f2c-238d4f6995c5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738964794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.2738964794
Directory /workspace/21.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.265880499
Short name T1103
Test name
Test status
Simulation time 14122488954 ps
CPU time 16.45 seconds
Started Aug 05 05:36:33 PM PDT 24
Finished Aug 05 05:36:50 PM PDT 24
Peak memory 215932 kb
Host smart-307efc08-0438-479f-82a9-e238fcf1896e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=265880499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.265880499
Directory /workspace/21.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.3532673743
Short name T1272
Test name
Test status
Simulation time 28490738717 ps
CPU time 31.16 seconds
Started Aug 05 05:36:38 PM PDT 24
Finished Aug 05 05:37:10 PM PDT 24
Peak memory 207516 kb
Host smart-bef96dd9-2445-4225-a4ef-ccde34134fbe
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532673743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.3532673743
Directory /workspace/21.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/21.usbdev_av_buffer.828936873
Short name T1801
Test name
Test status
Simulation time 169174429 ps
CPU time 0.92 seconds
Started Aug 05 05:36:32 PM PDT 24
Finished Aug 05 05:36:33 PM PDT 24
Peak memory 207288 kb
Host smart-fa583aab-46c5-49ba-a6b1-e055f4a5f4a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82893
6873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.828936873
Directory /workspace/21.usbdev_av_buffer/latest


Test location /workspace/coverage/default/21.usbdev_bitstuff_err.838885769
Short name T1216
Test name
Test status
Simulation time 151776737 ps
CPU time 0.88 seconds
Started Aug 05 05:36:35 PM PDT 24
Finished Aug 05 05:36:36 PM PDT 24
Peak memory 207340 kb
Host smart-bf1b8c13-3b55-4505-9f52-ffc1ec2ded25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83888
5769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.838885769
Directory /workspace/21.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.3563876351
Short name T1528
Test name
Test status
Simulation time 276434794 ps
CPU time 1.17 seconds
Started Aug 05 05:36:47 PM PDT 24
Finished Aug 05 05:36:49 PM PDT 24
Peak memory 207352 kb
Host smart-f133f2cf-18e5-4cbf-a0cd-0ed2ab3b639c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35638
76351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.3563876351
Directory /workspace/21.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.1835742210
Short name T3024
Test name
Test status
Simulation time 536902451 ps
CPU time 1.54 seconds
Started Aug 05 05:36:39 PM PDT 24
Finished Aug 05 05:36:40 PM PDT 24
Peak memory 207264 kb
Host smart-2245c54f-8db6-48ac-a28c-3e8d51ff4b13
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1835742210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.1835742210
Directory /workspace/21.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/21.usbdev_device_timeout.1651086753
Short name T1234
Test name
Test status
Simulation time 4956983826 ps
CPU time 36.11 seconds
Started Aug 05 05:36:32 PM PDT 24
Finished Aug 05 05:37:08 PM PDT 24
Peak memory 207632 kb
Host smart-e7f9c248-6dda-4eaf-ad11-b649cecaddcc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651086753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.1651086753
Directory /workspace/21.usbdev_device_timeout/latest


Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3503332574
Short name T1694
Test name
Test status
Simulation time 1028136697 ps
CPU time 1.95 seconds
Started Aug 05 05:40:09 PM PDT 24
Finished Aug 05 05:40:11 PM PDT 24
Peak memory 207316 kb
Host smart-0f52afb4-c704-4b01-afd9-2a6340b885e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35033
32574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3503332574
Directory /workspace/21.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/21.usbdev_disconnected.613369534
Short name T3009
Test name
Test status
Simulation time 183985294 ps
CPU time 0.82 seconds
Started Aug 05 05:36:49 PM PDT 24
Finished Aug 05 05:36:50 PM PDT 24
Peak memory 207316 kb
Host smart-c99b5531-14ee-4153-8e90-cb896a421993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61336
9534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.613369534
Directory /workspace/21.usbdev_disconnected/latest


Test location /workspace/coverage/default/21.usbdev_enable.1874897398
Short name T1006
Test name
Test status
Simulation time 30983177 ps
CPU time 0.71 seconds
Started Aug 05 05:36:42 PM PDT 24
Finished Aug 05 05:36:43 PM PDT 24
Peak memory 207312 kb
Host smart-8225f5b1-a3dd-4c9c-b91f-55455205ea87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18748
97398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1874897398
Directory /workspace/21.usbdev_enable/latest


Test location /workspace/coverage/default/21.usbdev_endpoint_access.2224540742
Short name T1611
Test name
Test status
Simulation time 787823263 ps
CPU time 2.23 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:36:44 PM PDT 24
Peak memory 207580 kb
Host smart-d640ff0e-3db3-4100-97d7-c653f8d312db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22245
40742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2224540742
Directory /workspace/21.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/21.usbdev_endpoint_types.3280383635
Short name T395
Test name
Test status
Simulation time 361053446 ps
CPU time 1.17 seconds
Started Aug 05 05:36:37 PM PDT 24
Finished Aug 05 05:36:38 PM PDT 24
Peak memory 207372 kb
Host smart-d9c32ca4-6596-4945-a1a1-70a76ca1dd12
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3280383635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.3280383635
Directory /workspace/21.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/21.usbdev_fifo_rst.31296861
Short name T1755
Test name
Test status
Simulation time 282255216 ps
CPU time 1.87 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 207540 kb
Host smart-7b67e5f7-eccc-41e8-9527-8b3884446670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31296
861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.31296861
Directory /workspace/21.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/21.usbdev_in_iso.512218491
Short name T2579
Test name
Test status
Simulation time 158045852 ps
CPU time 0.9 seconds
Started Aug 05 05:36:42 PM PDT 24
Finished Aug 05 05:36:43 PM PDT 24
Peak memory 207328 kb
Host smart-f5c367c6-6213-462f-a678-73f78558ad54
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=512218491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.512218491
Directory /workspace/21.usbdev_in_iso/latest


Test location /workspace/coverage/default/21.usbdev_in_stall.4043651432
Short name T777
Test name
Test status
Simulation time 142250590 ps
CPU time 0.84 seconds
Started Aug 05 05:36:38 PM PDT 24
Finished Aug 05 05:36:39 PM PDT 24
Peak memory 207376 kb
Host smart-cbf2dba9-03b0-40c1-aba6-275cd68a08ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40436
51432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.4043651432
Directory /workspace/21.usbdev_in_stall/latest


Test location /workspace/coverage/default/21.usbdev_in_trans.871836561
Short name T1592
Test name
Test status
Simulation time 158683445 ps
CPU time 0.87 seconds
Started Aug 05 05:36:40 PM PDT 24
Finished Aug 05 05:36:41 PM PDT 24
Peak memory 207352 kb
Host smart-16ce3c96-8730-4d93-92ee-5ff525ef6ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87183
6561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.871836561
Directory /workspace/21.usbdev_in_trans/latest


Test location /workspace/coverage/default/21.usbdev_invalid_sync.2671559904
Short name T583
Test name
Test status
Simulation time 5426522306 ps
CPU time 164.48 seconds
Started Aug 05 05:36:40 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 218180 kb
Host smart-e509cf41-bfd8-439f-bfc3-92d10f0f758d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2671559904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.2671559904
Directory /workspace/21.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/21.usbdev_iso_retraction.2600120129
Short name T869
Test name
Test status
Simulation time 3933461986 ps
CPU time 24.65 seconds
Started Aug 05 05:36:40 PM PDT 24
Finished Aug 05 05:37:05 PM PDT 24
Peak memory 207640 kb
Host smart-4afdf110-7973-4a49-b0c5-22d412a3591d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2600120129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.2600120129
Directory /workspace/21.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/21.usbdev_link_in_err.3859736480
Short name T98
Test name
Test status
Simulation time 164381868 ps
CPU time 0.87 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:36:44 PM PDT 24
Peak memory 207320 kb
Host smart-13f7955d-5ca3-40b2-86c5-04f99505d42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38597
36480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3859736480
Directory /workspace/21.usbdev_link_in_err/latest


Test location /workspace/coverage/default/21.usbdev_link_resume.1623862447
Short name T1973
Test name
Test status
Simulation time 30621619605 ps
CPU time 47.5 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:37:29 PM PDT 24
Peak memory 207644 kb
Host smart-b9bd29f7-d214-477a-a2ab-0da9de26054e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16238
62447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1623862447
Directory /workspace/21.usbdev_link_resume/latest


Test location /workspace/coverage/default/21.usbdev_link_suspend.1894336289
Short name T758
Test name
Test status
Simulation time 10686934660 ps
CPU time 13.27 seconds
Started Aug 05 05:36:42 PM PDT 24
Finished Aug 05 05:36:56 PM PDT 24
Peak memory 207596 kb
Host smart-89f62e9b-176d-4f34-bf0a-7887ea57d717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18943
36289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1894336289
Directory /workspace/21.usbdev_link_suspend/latest


Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2073416062
Short name T18
Test name
Test status
Simulation time 3707270263 ps
CPU time 29.31 seconds
Started Aug 05 05:36:42 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 215880 kb
Host smart-6055e0d5-d5a8-489d-bb3b-310803b37457
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2073416062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2073416062
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3924540928
Short name T1762
Test name
Test status
Simulation time 262928074 ps
CPU time 1.06 seconds
Started Aug 05 05:36:42 PM PDT 24
Finished Aug 05 05:36:43 PM PDT 24
Peak memory 207332 kb
Host smart-00094d7e-e943-4322-a3e5-6eff906f58f0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3924540928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3924540928
Directory /workspace/21.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2857159945
Short name T498
Test name
Test status
Simulation time 204751744 ps
CPU time 0.94 seconds
Started Aug 05 05:36:48 PM PDT 24
Finished Aug 05 05:36:49 PM PDT 24
Peak memory 207376 kb
Host smart-4fb602e9-0c8f-4a51-a779-d79f33601007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28571
59945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2857159945
Directory /workspace/21.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.2408696086
Short name T1551
Test name
Test status
Simulation time 1829403419 ps
CPU time 14.79 seconds
Started Aug 05 05:36:37 PM PDT 24
Finished Aug 05 05:36:52 PM PDT 24
Peak memory 217472 kb
Host smart-9d355ebc-821e-4079-83b5-91d06a4a1f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24086
96086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.2408696086
Directory /workspace/21.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.2366131061
Short name T1192
Test name
Test status
Simulation time 3841049489 ps
CPU time 106.43 seconds
Started Aug 05 05:36:36 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 215832 kb
Host smart-1c73118f-ca9b-4705-b4c4-96b432e0e81b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2366131061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2366131061
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1025146327
Short name T2237
Test name
Test status
Simulation time 157564661 ps
CPU time 0.87 seconds
Started Aug 05 05:36:35 PM PDT 24
Finished Aug 05 05:36:36 PM PDT 24
Peak memory 207380 kb
Host smart-43b90ce4-04b1-4b69-82e7-a7930c847893
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1025146327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1025146327
Directory /workspace/21.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3238029197
Short name T1696
Test name
Test status
Simulation time 156387138 ps
CPU time 0.83 seconds
Started Aug 05 05:36:38 PM PDT 24
Finished Aug 05 05:36:39 PM PDT 24
Peak memory 207316 kb
Host smart-5fae7f26-e9e1-4dc2-bd6b-2df8857b3305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32380
29197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3238029197
Directory /workspace/21.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/21.usbdev_out_iso.2273581424
Short name T2705
Test name
Test status
Simulation time 249980291 ps
CPU time 1.02 seconds
Started Aug 05 05:36:50 PM PDT 24
Finished Aug 05 05:36:51 PM PDT 24
Peak memory 207364 kb
Host smart-e6b6dc94-f86c-48c6-9d5e-170decb29931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22735
81424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2273581424
Directory /workspace/21.usbdev_out_iso/latest


Test location /workspace/coverage/default/21.usbdev_out_stall.2839489416
Short name T1054
Test name
Test status
Simulation time 177529330 ps
CPU time 0.9 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:36:42 PM PDT 24
Peak memory 207340 kb
Host smart-8aa1bb53-bb48-4a00-a5ea-7efcd15f1f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28394
89416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2839489416
Directory /workspace/21.usbdev_out_stall/latest


Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3098714547
Short name T1047
Test name
Test status
Simulation time 161711591 ps
CPU time 0.89 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:36:42 PM PDT 24
Peak memory 207380 kb
Host smart-0f4d4fef-690e-4fe0-84dd-2b2cf384b8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30987
14547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3098714547
Directory /workspace/21.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1522017455
Short name T184
Test name
Test status
Simulation time 152708485 ps
CPU time 0.89 seconds
Started Aug 05 05:36:46 PM PDT 24
Finished Aug 05 05:36:47 PM PDT 24
Peak memory 207288 kb
Host smart-a606514c-7d77-41ab-8d95-a39001878e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15220
17455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1522017455
Directory /workspace/21.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2666508302
Short name T1904
Test name
Test status
Simulation time 226788829 ps
CPU time 1.05 seconds
Started Aug 05 05:36:40 PM PDT 24
Finished Aug 05 05:36:42 PM PDT 24
Peak memory 207428 kb
Host smart-b8b33bbc-ff18-443b-b5fc-6ffaaba44db2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2666508302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2666508302
Directory /workspace/21.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1432903153
Short name T1621
Test name
Test status
Simulation time 156140506 ps
CPU time 0.84 seconds
Started Aug 05 05:36:51 PM PDT 24
Finished Aug 05 05:36:52 PM PDT 24
Peak memory 207268 kb
Host smart-654cbed2-4e1f-46a0-97c4-641c73c819e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14329
03153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1432903153
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3173421145
Short name T2041
Test name
Test status
Simulation time 50642944 ps
CPU time 0.7 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 207356 kb
Host smart-3dd422e5-cd24-4e7b-8e01-c7308007690d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31734
21145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3173421145
Directory /workspace/21.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2518247530
Short name T245
Test name
Test status
Simulation time 11417703392 ps
CPU time 27.56 seconds
Started Aug 05 05:36:51 PM PDT 24
Finished Aug 05 05:37:19 PM PDT 24
Peak memory 215800 kb
Host smart-fd1f0f54-0daa-4907-a1d6-e7e91edd6f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25182
47530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2518247530
Directory /workspace/21.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/21.usbdev_pkt_sent.3232061343
Short name T1706
Test name
Test status
Simulation time 176211127 ps
CPU time 0.92 seconds
Started Aug 05 05:36:54 PM PDT 24
Finished Aug 05 05:36:55 PM PDT 24
Peak memory 207340 kb
Host smart-221b050d-17fc-4b95-bbc9-1db293490c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32320
61343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3232061343
Directory /workspace/21.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.3413989417
Short name T1359
Test name
Test status
Simulation time 173456295 ps
CPU time 0.93 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:36:44 PM PDT 24
Peak memory 207324 kb
Host smart-8bcdcf36-7a0c-475c-a71c-b3494ef5e8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34139
89417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.3413989417
Directory /workspace/21.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.1307393420
Short name T1250
Test name
Test status
Simulation time 206548577 ps
CPU time 1.01 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 207380 kb
Host smart-c66bf5a4-82ae-4acc-846e-89fea557f923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13073
93420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.1307393420
Directory /workspace/21.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3897612465
Short name T82
Test name
Test status
Simulation time 177628118 ps
CPU time 0.96 seconds
Started Aug 05 05:36:40 PM PDT 24
Finished Aug 05 05:36:41 PM PDT 24
Peak memory 207268 kb
Host smart-a84cb262-0b93-4f91-8170-8bcd15d83a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38976
12465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3897612465
Directory /workspace/21.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/21.usbdev_rx_full.1549057274
Short name T1091
Test name
Test status
Simulation time 284815075 ps
CPU time 1.12 seconds
Started Aug 05 05:36:48 PM PDT 24
Finished Aug 05 05:36:49 PM PDT 24
Peak memory 207364 kb
Host smart-4918be2b-f16e-4499-8623-4a86a4574437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15490
57274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.1549057274
Directory /workspace/21.usbdev_rx_full/latest


Test location /workspace/coverage/default/21.usbdev_setup_stage.3485114505
Short name T2142
Test name
Test status
Simulation time 168133258 ps
CPU time 0.91 seconds
Started Aug 05 05:36:40 PM PDT 24
Finished Aug 05 05:36:41 PM PDT 24
Peak memory 207232 kb
Host smart-888732f6-d7bd-4491-885b-9d379ca2cbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34851
14505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3485114505
Directory /workspace/21.usbdev_setup_stage/latest


Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3785682090
Short name T1897
Test name
Test status
Simulation time 143553781 ps
CPU time 0.84 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:36:44 PM PDT 24
Peak memory 207320 kb
Host smart-1a0ad53c-7a52-4d32-8f77-71c788536975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37856
82090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3785682090
Directory /workspace/21.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/21.usbdev_smoke.854941095
Short name T2514
Test name
Test status
Simulation time 228685671 ps
CPU time 0.96 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:36:42 PM PDT 24
Peak memory 207224 kb
Host smart-a0860842-1810-4d13-80d5-74edb788b19c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85494
1095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.854941095
Directory /workspace/21.usbdev_smoke/latest


Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.4279267591
Short name T1422
Test name
Test status
Simulation time 2516023022 ps
CPU time 19.07 seconds
Started Aug 05 05:36:45 PM PDT 24
Finished Aug 05 05:37:04 PM PDT 24
Peak memory 207712 kb
Host smart-f5fbf633-08ee-482c-aa05-3f8dda93b344
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4279267591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.4279267591
Directory /workspace/21.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1512098877
Short name T1666
Test name
Test status
Simulation time 186747034 ps
CPU time 0.88 seconds
Started Aug 05 05:36:55 PM PDT 24
Finished Aug 05 05:36:56 PM PDT 24
Peak memory 207288 kb
Host smart-0f95154a-1eec-46ac-a646-3fc1d86d84ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15120
98877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1512098877
Directory /workspace/21.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/21.usbdev_stall_trans.2937529255
Short name T1957
Test name
Test status
Simulation time 181921535 ps
CPU time 0.88 seconds
Started Aug 05 05:36:42 PM PDT 24
Finished Aug 05 05:36:43 PM PDT 24
Peak memory 207404 kb
Host smart-ec7a2ed8-9d11-44ef-bacb-f250719145ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29375
29255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2937529255
Directory /workspace/21.usbdev_stall_trans/latest


Test location /workspace/coverage/default/21.usbdev_stream_len_max.3885917759
Short name T1265
Test name
Test status
Simulation time 662632572 ps
CPU time 1.72 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 207576 kb
Host smart-26a5fe1b-4d87-4a38-8e0b-1e0768655c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38859
17759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3885917759
Directory /workspace/21.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/21.usbdev_streaming_out.3956011562
Short name T2336
Test name
Test status
Simulation time 2606018478 ps
CPU time 25.47 seconds
Started Aug 05 05:36:46 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 217464 kb
Host smart-327fcbca-78e2-4378-acac-5ef65d54ea77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39560
11562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3956011562
Directory /workspace/21.usbdev_streaming_out/latest


Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.1281968704
Short name T17
Test name
Test status
Simulation time 2492959269 ps
CPU time 21.5 seconds
Started Aug 05 05:36:38 PM PDT 24
Finished Aug 05 05:37:00 PM PDT 24
Peak memory 207740 kb
Host smart-56576dc0-0fe9-4c20-be30-79edbe26e5ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281968704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.1281968704
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/22.usbdev_alert_test.2580180468
Short name T1003
Test name
Test status
Simulation time 37432004 ps
CPU time 0.69 seconds
Started Aug 05 05:36:47 PM PDT 24
Finished Aug 05 05:36:48 PM PDT 24
Peak memory 207420 kb
Host smart-bcf139ef-d4a7-4fb9-a0d0-7c707034d182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2580180468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2580180468
Directory /workspace/22.usbdev_alert_test/latest


Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2169751081
Short name T910
Test name
Test status
Simulation time 5632131428 ps
CPU time 7.8 seconds
Started Aug 05 05:36:51 PM PDT 24
Finished Aug 05 05:36:58 PM PDT 24
Peak memory 215852 kb
Host smart-0d824ca5-1d85-4dd2-848d-2df232fa0bf0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169751081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.2169751081
Directory /workspace/22.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1705403969
Short name T2065
Test name
Test status
Simulation time 21079795205 ps
CPU time 25.14 seconds
Started Aug 05 05:36:53 PM PDT 24
Finished Aug 05 05:37:18 PM PDT 24
Peak memory 207620 kb
Host smart-50bfd362-90b4-400b-afe5-79be396c2de0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705403969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1705403969
Directory /workspace/22.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.2046324600
Short name T1877
Test name
Test status
Simulation time 29491066666 ps
CPU time 37.71 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:37:21 PM PDT 24
Peak memory 207604 kb
Host smart-616c5af5-4d46-4467-a4d1-e31b9195041e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046324600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_resume.2046324600
Directory /workspace/22.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/22.usbdev_av_buffer.2262619219
Short name T587
Test name
Test status
Simulation time 151727337 ps
CPU time 0.81 seconds
Started Aug 05 05:36:47 PM PDT 24
Finished Aug 05 05:36:48 PM PDT 24
Peak memory 207416 kb
Host smart-c23068ac-b535-4b61-9cb4-655527cd8fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22626
19219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2262619219
Directory /workspace/22.usbdev_av_buffer/latest


Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3444661034
Short name T2342
Test name
Test status
Simulation time 143322864 ps
CPU time 0.84 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 207320 kb
Host smart-66ceae5e-0a93-42ff-982d-f0bfaa331878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34446
61034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3444661034
Directory /workspace/22.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.546475056
Short name T647
Test name
Test status
Simulation time 492769395 ps
CPU time 1.63 seconds
Started Aug 05 05:36:51 PM PDT 24
Finished Aug 05 05:36:53 PM PDT 24
Peak memory 207332 kb
Host smart-f367f178-9442-4383-b101-b60028af921b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54647
5056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.546475056
Directory /workspace/22.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3196224007
Short name T2871
Test name
Test status
Simulation time 1379837994 ps
CPU time 3.63 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:36:48 PM PDT 24
Peak memory 207568 kb
Host smart-d8af16a7-27cc-422d-baad-20c2ac35c2e8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3196224007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3196224007
Directory /workspace/22.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/22.usbdev_device_address.351766218
Short name T2105
Test name
Test status
Simulation time 41031514043 ps
CPU time 62.04 seconds
Started Aug 05 05:36:41 PM PDT 24
Finished Aug 05 05:37:44 PM PDT 24
Peak memory 207612 kb
Host smart-05582a66-3a48-41d8-8969-2989cef58c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35176
6218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.351766218
Directory /workspace/22.usbdev_device_address/latest


Test location /workspace/coverage/default/22.usbdev_device_timeout.2392451723
Short name T1754
Test name
Test status
Simulation time 1085519588 ps
CPU time 9.33 seconds
Started Aug 05 05:36:48 PM PDT 24
Finished Aug 05 05:36:57 PM PDT 24
Peak memory 207528 kb
Host smart-5fa288af-2178-4721-bea5-cc19dfe3a730
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392451723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.2392451723
Directory /workspace/22.usbdev_device_timeout/latest


Test location /workspace/coverage/default/22.usbdev_disable_endpoint.4112701766
Short name T824
Test name
Test status
Simulation time 654608082 ps
CPU time 1.69 seconds
Started Aug 05 05:36:46 PM PDT 24
Finished Aug 05 05:36:48 PM PDT 24
Peak memory 207336 kb
Host smart-9a9359b6-91e9-4d24-8503-5914afec6daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41127
01766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.4112701766
Directory /workspace/22.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/22.usbdev_disconnected.2929673973
Short name T1251
Test name
Test status
Simulation time 144718857 ps
CPU time 0.84 seconds
Started Aug 05 05:36:49 PM PDT 24
Finished Aug 05 05:36:50 PM PDT 24
Peak memory 207368 kb
Host smart-f11f1df9-3bde-4c40-b452-a9238feff5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29296
73973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2929673973
Directory /workspace/22.usbdev_disconnected/latest


Test location /workspace/coverage/default/22.usbdev_enable.1881743369
Short name T2842
Test name
Test status
Simulation time 45617062 ps
CPU time 0.7 seconds
Started Aug 05 05:36:42 PM PDT 24
Finished Aug 05 05:36:42 PM PDT 24
Peak memory 207364 kb
Host smart-32da9d0f-5c0b-4fd0-853c-29fa772f8afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18817
43369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1881743369
Directory /workspace/22.usbdev_enable/latest


Test location /workspace/coverage/default/22.usbdev_endpoint_access.1174006828
Short name T675
Test name
Test status
Simulation time 952179464 ps
CPU time 2.72 seconds
Started Aug 05 05:36:50 PM PDT 24
Finished Aug 05 05:36:53 PM PDT 24
Peak memory 207568 kb
Host smart-70bb6c1b-1b0b-4751-8a5e-3fb78020ebf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11740
06828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1174006828
Directory /workspace/22.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/22.usbdev_endpoint_types.3989854593
Short name T429
Test name
Test status
Simulation time 210672264 ps
CPU time 0.92 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:36:44 PM PDT 24
Peak memory 207324 kb
Host smart-93198362-765b-4660-b1b0-df555ef8e86e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3989854593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.3989854593
Directory /workspace/22.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/22.usbdev_fifo_rst.1896767992
Short name T785
Test name
Test status
Simulation time 203633734 ps
CPU time 1.39 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:36:44 PM PDT 24
Peak memory 207460 kb
Host smart-25623da2-60cc-4a11-a32b-8c99ec603a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18967
67992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1896767992
Directory /workspace/22.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/22.usbdev_in_iso.1607122316
Short name T827
Test name
Test status
Simulation time 190812555 ps
CPU time 1.02 seconds
Started Aug 05 05:36:40 PM PDT 24
Finished Aug 05 05:36:41 PM PDT 24
Peak memory 207428 kb
Host smart-40bedd13-da12-4b26-b4f8-e87481da652c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1607122316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1607122316
Directory /workspace/22.usbdev_in_iso/latest


Test location /workspace/coverage/default/22.usbdev_in_stall.2999532748
Short name T2481
Test name
Test status
Simulation time 145675974 ps
CPU time 0.84 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:36:44 PM PDT 24
Peak memory 207352 kb
Host smart-345f1d7e-2251-4e22-88c6-bda8ba89182e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29995
32748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2999532748
Directory /workspace/22.usbdev_in_stall/latest


Test location /workspace/coverage/default/22.usbdev_in_trans.180416391
Short name T585
Test name
Test status
Simulation time 235397957 ps
CPU time 1.01 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 207376 kb
Host smart-d2534ab7-7e93-4916-838a-5eea3f061a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18041
6391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.180416391
Directory /workspace/22.usbdev_in_trans/latest


Test location /workspace/coverage/default/22.usbdev_invalid_sync.3379269399
Short name T2702
Test name
Test status
Simulation time 4295656715 ps
CPU time 121.06 seconds
Started Aug 05 05:36:49 PM PDT 24
Finished Aug 05 05:38:50 PM PDT 24
Peak memory 218216 kb
Host smart-6d04b8ae-ce4d-4ad3-b57b-f982e36540df
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3379269399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.3379269399
Directory /workspace/22.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/22.usbdev_iso_retraction.3366304165
Short name T71
Test name
Test status
Simulation time 5408730758 ps
CPU time 33.65 seconds
Started Aug 05 05:36:51 PM PDT 24
Finished Aug 05 05:37:25 PM PDT 24
Peak memory 207572 kb
Host smart-fb9ae562-4320-4477-9334-d951018aacd5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3366304165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.3366304165
Directory /workspace/22.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/22.usbdev_link_in_err.1245653610
Short name T1529
Test name
Test status
Simulation time 180978291 ps
CPU time 0.94 seconds
Started Aug 05 05:36:46 PM PDT 24
Finished Aug 05 05:36:48 PM PDT 24
Peak memory 207248 kb
Host smart-b000ca81-7661-48df-93e5-9c6ff138fd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12456
53610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.1245653610
Directory /workspace/22.usbdev_link_in_err/latest


Test location /workspace/coverage/default/22.usbdev_link_resume.3326982358
Short name T2797
Test name
Test status
Simulation time 11395177807 ps
CPU time 14.26 seconds
Started Aug 05 05:36:46 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207620 kb
Host smart-b01d0606-8f59-4dca-bd00-c224430a06fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33269
82358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3326982358
Directory /workspace/22.usbdev_link_resume/latest


Test location /workspace/coverage/default/22.usbdev_link_suspend.2119128071
Short name T65
Test name
Test status
Simulation time 9567068956 ps
CPU time 12.1 seconds
Started Aug 05 05:36:51 PM PDT 24
Finished Aug 05 05:37:03 PM PDT 24
Peak memory 207700 kb
Host smart-d8190ebe-a1c6-4efb-9030-5275f60e1765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
28071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2119128071
Directory /workspace/22.usbdev_link_suspend/latest


Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.2922859445
Short name T324
Test name
Test status
Simulation time 5036881819 ps
CPU time 38.25 seconds
Started Aug 05 05:36:46 PM PDT 24
Finished Aug 05 05:37:25 PM PDT 24
Peak memory 224036 kb
Host smart-d1af9298-686a-4a44-b625-7ddf3fdd4420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29228
59445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.2922859445
Directory /workspace/22.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.3713962966
Short name T2837
Test name
Test status
Simulation time 2815654071 ps
CPU time 79.8 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:38:04 PM PDT 24
Peak memory 215764 kb
Host smart-b19a899c-9611-4336-b22f-885ece173131
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3713962966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.3713962966
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1041128011
Short name T601
Test name
Test status
Simulation time 246523291 ps
CPU time 1.07 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 207360 kb
Host smart-b0ca789a-bf18-4197-9d23-5bb11bee81d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1041128011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1041128011
Directory /workspace/22.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1189088384
Short name T1990
Test name
Test status
Simulation time 250293669 ps
CPU time 1.04 seconds
Started Aug 05 05:36:47 PM PDT 24
Finished Aug 05 05:36:48 PM PDT 24
Peak memory 207380 kb
Host smart-24f60a0a-fc15-4ba5-a162-d5e90f69b3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11890
88384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1189088384
Directory /workspace/22.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.4084834748
Short name T1915
Test name
Test status
Simulation time 2861820120 ps
CPU time 21.66 seconds
Started Aug 05 05:36:48 PM PDT 24
Finished Aug 05 05:37:10 PM PDT 24
Peak memory 224048 kb
Host smart-8b4583e7-f927-4152-b9a8-43447fe932ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40848
34748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.4084834748
Directory /workspace/22.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.2735820630
Short name T1794
Test name
Test status
Simulation time 2380772310 ps
CPU time 17.39 seconds
Started Aug 05 05:36:47 PM PDT 24
Finished Aug 05 05:37:04 PM PDT 24
Peak memory 215880 kb
Host smart-e944ca96-bafe-4f07-86be-d42e98866da5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2735820630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.2735820630
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2707958330
Short name T1379
Test name
Test status
Simulation time 157529576 ps
CPU time 0.84 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:36:44 PM PDT 24
Peak memory 207360 kb
Host smart-b2007e92-9dfd-407b-86fb-49cd73979a0e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2707958330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2707958330
Directory /workspace/22.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.4032340429
Short name T2173
Test name
Test status
Simulation time 135546861 ps
CPU time 0.83 seconds
Started Aug 05 05:36:45 PM PDT 24
Finished Aug 05 05:36:46 PM PDT 24
Peak memory 207404 kb
Host smart-ee0fc5d3-213c-4736-af08-51c590fe9007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40323
40429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.4032340429
Directory /workspace/22.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/22.usbdev_nak_trans.1915817559
Short name T151
Test name
Test status
Simulation time 216197516 ps
CPU time 0.99 seconds
Started Aug 05 05:36:51 PM PDT 24
Finished Aug 05 05:36:52 PM PDT 24
Peak memory 207416 kb
Host smart-890e8a33-bbc2-4cd7-b3f9-f26a2141dd2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19158
17559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1915817559
Directory /workspace/22.usbdev_nak_trans/latest


Test location /workspace/coverage/default/22.usbdev_out_iso.202942846
Short name T1412
Test name
Test status
Simulation time 180421936 ps
CPU time 0.97 seconds
Started Aug 05 05:36:46 PM PDT 24
Finished Aug 05 05:36:48 PM PDT 24
Peak memory 207272 kb
Host smart-227f991b-c236-4316-9389-67913e549c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20294
2846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.202942846
Directory /workspace/22.usbdev_out_iso/latest


Test location /workspace/coverage/default/22.usbdev_out_stall.350238594
Short name T501
Test name
Test status
Simulation time 172823576 ps
CPU time 0.9 seconds
Started Aug 05 05:36:55 PM PDT 24
Finished Aug 05 05:36:56 PM PDT 24
Peak memory 207260 kb
Host smart-633b61fa-e8de-400f-9e30-58fed684d219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35023
8594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.350238594
Directory /workspace/22.usbdev_out_stall/latest


Test location /workspace/coverage/default/22.usbdev_out_trans_nak.221974602
Short name T1031
Test name
Test status
Simulation time 146088092 ps
CPU time 0.8 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207268 kb
Host smart-d8b50ff8-938c-48a8-b7f8-9efef2262c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22197
4602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.221974602
Directory /workspace/22.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/22.usbdev_pending_in_trans.926710019
Short name T2444
Test name
Test status
Simulation time 161569909 ps
CPU time 0.84 seconds
Started Aug 05 05:36:48 PM PDT 24
Finished Aug 05 05:36:49 PM PDT 24
Peak memory 207468 kb
Host smart-5b907dd3-513d-492d-a275-1efa74de5978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92671
0019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.926710019
Directory /workspace/22.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.400176790
Short name T3046
Test name
Test status
Simulation time 213559862 ps
CPU time 1.02 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207356 kb
Host smart-5427c051-6398-48bb-b73d-90b8144dc40f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=400176790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.400176790
Directory /workspace/22.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1236052784
Short name T2032
Test name
Test status
Simulation time 159272020 ps
CPU time 0.87 seconds
Started Aug 05 05:36:56 PM PDT 24
Finished Aug 05 05:36:57 PM PDT 24
Peak memory 207212 kb
Host smart-f881ba15-166d-44dd-ad50-0ae754d319a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12360
52784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1236052784
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.711106641
Short name T1641
Test name
Test status
Simulation time 108225537 ps
CPU time 0.78 seconds
Started Aug 05 05:36:46 PM PDT 24
Finished Aug 05 05:36:47 PM PDT 24
Peak memory 207316 kb
Host smart-7579c035-4ec6-4420-9bfa-fcd7312a3b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71110
6641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.711106641
Directory /workspace/22.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1101641248
Short name T2296
Test name
Test status
Simulation time 14464654217 ps
CPU time 38.16 seconds
Started Aug 05 05:36:51 PM PDT 24
Finished Aug 05 05:37:29 PM PDT 24
Peak memory 215888 kb
Host smart-96dbbee2-2629-4637-b99b-b78c045f9bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11016
41248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1101641248
Directory /workspace/22.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/22.usbdev_pkt_received.4176622106
Short name T625
Test name
Test status
Simulation time 154950328 ps
CPU time 0.88 seconds
Started Aug 05 05:36:51 PM PDT 24
Finished Aug 05 05:36:52 PM PDT 24
Peak memory 207376 kb
Host smart-7060e420-321d-4550-919d-d20662b7af70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41766
22106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.4176622106
Directory /workspace/22.usbdev_pkt_received/latest


Test location /workspace/coverage/default/22.usbdev_pkt_sent.3993168482
Short name T1408
Test name
Test status
Simulation time 220687210 ps
CPU time 0.95 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207268 kb
Host smart-10f120e9-d7b1-4c32-bdef-709fa4a7bbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39931
68482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3993168482
Directory /workspace/22.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.600752161
Short name T2303
Test name
Test status
Simulation time 234368954 ps
CPU time 1 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 207348 kb
Host smart-b7067edf-e56d-44e7-bb48-5aba319604cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60075
2161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.600752161
Directory /workspace/22.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.2982800850
Short name T2008
Test name
Test status
Simulation time 192095525 ps
CPU time 0.94 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 207320 kb
Host smart-59e36c9c-c463-44db-8512-2be0e6b6b64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29828
00850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.2982800850
Directory /workspace/22.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/22.usbdev_rx_crc_err.825779430
Short name T956
Test name
Test status
Simulation time 193041212 ps
CPU time 0.91 seconds
Started Aug 05 05:36:49 PM PDT 24
Finished Aug 05 05:36:50 PM PDT 24
Peak memory 207392 kb
Host smart-f393d973-9d6c-4e4f-98bf-6fb7c23b3c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82577
9430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.825779430
Directory /workspace/22.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/22.usbdev_setup_stage.3608700437
Short name T2544
Test name
Test status
Simulation time 147013389 ps
CPU time 0.82 seconds
Started Aug 05 05:36:45 PM PDT 24
Finished Aug 05 05:36:46 PM PDT 24
Peak memory 207316 kb
Host smart-f5fa7b85-1e34-4465-b4d5-8a19b29df54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36087
00437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3608700437
Directory /workspace/22.usbdev_setup_stage/latest


Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.4131110436
Short name T1752
Test name
Test status
Simulation time 147439599 ps
CPU time 0.87 seconds
Started Aug 05 05:36:56 PM PDT 24
Finished Aug 05 05:36:57 PM PDT 24
Peak memory 207396 kb
Host smart-3e842740-6c68-4f3d-a62a-95a18b4f2009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41311
10436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.4131110436
Directory /workspace/22.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/22.usbdev_smoke.3320834065
Short name T1721
Test name
Test status
Simulation time 239883811 ps
CPU time 1.02 seconds
Started Aug 05 05:36:49 PM PDT 24
Finished Aug 05 05:36:50 PM PDT 24
Peak memory 207368 kb
Host smart-5563892d-36db-4ac3-8be1-736da1da5d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33208
34065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3320834065
Directory /workspace/22.usbdev_smoke/latest


Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.2823902335
Short name T2443
Test name
Test status
Simulation time 2823664979 ps
CPU time 28.49 seconds
Started Aug 05 05:36:54 PM PDT 24
Finished Aug 05 05:37:22 PM PDT 24
Peak memory 224000 kb
Host smart-2c665d5d-be51-4387-b287-f35f7655b703
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2823902335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.2823902335
Directory /workspace/22.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.747196059
Short name T1507
Test name
Test status
Simulation time 176739914 ps
CPU time 0.87 seconds
Started Aug 05 05:36:48 PM PDT 24
Finished Aug 05 05:36:49 PM PDT 24
Peak memory 207356 kb
Host smart-5ce8d622-0d69-4300-b549-2e2d296fe6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74719
6059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.747196059
Directory /workspace/22.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/22.usbdev_stall_trans.3515625976
Short name T1547
Test name
Test status
Simulation time 185673685 ps
CPU time 0.89 seconds
Started Aug 05 05:36:48 PM PDT 24
Finished Aug 05 05:36:49 PM PDT 24
Peak memory 207320 kb
Host smart-4855ec41-9e00-43f9-a2a1-279b9dcbc06c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35156
25976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3515625976
Directory /workspace/22.usbdev_stall_trans/latest


Test location /workspace/coverage/default/22.usbdev_stream_len_max.3244440461
Short name T1582
Test name
Test status
Simulation time 955713910 ps
CPU time 2.52 seconds
Started Aug 05 05:36:59 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 207440 kb
Host smart-bb0b7ede-ac7d-4ebd-a523-68d57208beec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32444
40461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3244440461
Directory /workspace/22.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/22.usbdev_streaming_out.2829120551
Short name T1624
Test name
Test status
Simulation time 2818888658 ps
CPU time 23.48 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:37:08 PM PDT 24
Peak memory 217528 kb
Host smart-66323a69-ba12-4ad9-807c-34ead2912d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28291
20551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2829120551
Directory /workspace/22.usbdev_streaming_out/latest


Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.3557053295
Short name T995
Test name
Test status
Simulation time 610515533 ps
CPU time 5.2 seconds
Started Aug 05 05:36:43 PM PDT 24
Finished Aug 05 05:36:49 PM PDT 24
Peak memory 207596 kb
Host smart-43cb1adb-8223-4527-a83b-01adb7895018
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557053295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.3557053295
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/23.usbdev_alert_test.1384418721
Short name T2663
Test name
Test status
Simulation time 37449866 ps
CPU time 0.67 seconds
Started Aug 05 05:37:06 PM PDT 24
Finished Aug 05 05:37:06 PM PDT 24
Peak memory 207508 kb
Host smart-28ad02b0-2c55-4cee-b18b-d500d53c0bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1384418721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.1384418721
Directory /workspace/23.usbdev_alert_test/latest


Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3101120109
Short name T1311
Test name
Test status
Simulation time 5986655647 ps
CPU time 8.97 seconds
Started Aug 05 05:36:47 PM PDT 24
Finished Aug 05 05:36:57 PM PDT 24
Peak memory 215756 kb
Host smart-2aa9a767-b4be-44c3-a08d-92ae7bf6a538
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101120109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.3101120109
Directory /workspace/23.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.949569003
Short name T1850
Test name
Test status
Simulation time 20756283447 ps
CPU time 24.96 seconds
Started Aug 05 05:36:54 PM PDT 24
Finished Aug 05 05:37:19 PM PDT 24
Peak memory 207652 kb
Host smart-c164b908-8f4a-4d65-998d-c1c3ea3dd6af
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=949569003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.949569003
Directory /workspace/23.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3461746419
Short name T2973
Test name
Test status
Simulation time 24726034131 ps
CPU time 29.65 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:30 PM PDT 24
Peak memory 215796 kb
Host smart-281c9b61-4adb-4ce9-9e8d-98a888ef5710
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461746419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.3461746419
Directory /workspace/23.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/23.usbdev_av_buffer.2953871355
Short name T1083
Test name
Test status
Simulation time 167158821 ps
CPU time 0.87 seconds
Started Aug 05 05:36:49 PM PDT 24
Finished Aug 05 05:36:50 PM PDT 24
Peak memory 207368 kb
Host smart-df6ce45b-d47f-4c7c-af49-b9bdb865354e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29538
71355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2953871355
Directory /workspace/23.usbdev_av_buffer/latest


Test location /workspace/coverage/default/23.usbdev_bitstuff_err.223530526
Short name T1384
Test name
Test status
Simulation time 142973499 ps
CPU time 0.81 seconds
Started Aug 05 05:36:52 PM PDT 24
Finished Aug 05 05:36:53 PM PDT 24
Peak memory 207316 kb
Host smart-72256c8b-e95c-49d6-906c-65391be7d67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22353
0526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.223530526
Directory /workspace/23.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.711775427
Short name T2343
Test name
Test status
Simulation time 438041823 ps
CPU time 1.59 seconds
Started Aug 05 05:36:55 PM PDT 24
Finished Aug 05 05:36:56 PM PDT 24
Peak memory 207276 kb
Host smart-c82bed27-7bc3-4557-9cd0-5130ac37f1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71177
5427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.711775427
Directory /workspace/23.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.327348543
Short name T2134
Test name
Test status
Simulation time 1046109701 ps
CPU time 2.67 seconds
Started Aug 05 05:36:45 PM PDT 24
Finished Aug 05 05:36:48 PM PDT 24
Peak memory 207552 kb
Host smart-0709c5d2-0de7-41e6-a8a8-970e858463a7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=327348543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.327348543
Directory /workspace/23.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/23.usbdev_device_address.1972339486
Short name T168
Test name
Test status
Simulation time 59680311664 ps
CPU time 95.6 seconds
Started Aug 05 05:36:44 PM PDT 24
Finished Aug 05 05:38:20 PM PDT 24
Peak memory 207680 kb
Host smart-be9804ab-0ecc-463c-a5c0-62ff41c6cba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19723
39486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.1972339486
Directory /workspace/23.usbdev_device_address/latest


Test location /workspace/coverage/default/23.usbdev_device_timeout.3153798756
Short name T2605
Test name
Test status
Simulation time 3112922982 ps
CPU time 21.35 seconds
Started Aug 05 05:36:48 PM PDT 24
Finished Aug 05 05:37:10 PM PDT 24
Peak memory 207708 kb
Host smart-bae25c24-0af9-4386-b41f-f7d74bb75a0c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153798756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.3153798756
Directory /workspace/23.usbdev_device_timeout/latest


Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3357593706
Short name T343
Test name
Test status
Simulation time 745496462 ps
CPU time 1.75 seconds
Started Aug 05 05:36:54 PM PDT 24
Finished Aug 05 05:36:56 PM PDT 24
Peak memory 207360 kb
Host smart-423d472e-1ac6-48f7-9556-0760fc43c393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33575
93706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3357593706
Directory /workspace/23.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/23.usbdev_disconnected.3059274059
Short name T1097
Test name
Test status
Simulation time 143955388 ps
CPU time 0.87 seconds
Started Aug 05 05:36:58 PM PDT 24
Finished Aug 05 05:36:59 PM PDT 24
Peak memory 207252 kb
Host smart-9cb1f566-6375-455c-8f4e-841fb8f2290c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30592
74059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.3059274059
Directory /workspace/23.usbdev_disconnected/latest


Test location /workspace/coverage/default/23.usbdev_enable.555602626
Short name T2193
Test name
Test status
Simulation time 70412411 ps
CPU time 0.71 seconds
Started Aug 05 05:36:58 PM PDT 24
Finished Aug 05 05:36:59 PM PDT 24
Peak memory 207312 kb
Host smart-2b819ff6-0903-4b80-a1f3-68a620174de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55560
2626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.555602626
Directory /workspace/23.usbdev_enable/latest


Test location /workspace/coverage/default/23.usbdev_endpoint_access.2572925599
Short name T1935
Test name
Test status
Simulation time 860203789 ps
CPU time 2.48 seconds
Started Aug 05 05:36:46 PM PDT 24
Finished Aug 05 05:36:48 PM PDT 24
Peak memory 207628 kb
Host smart-680948e1-4fd5-4f7e-a48e-72780a4c5a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25729
25599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2572925599
Directory /workspace/23.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/23.usbdev_endpoint_types.3338293655
Short name T3062
Test name
Test status
Simulation time 332606753 ps
CPU time 1.14 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207324 kb
Host smart-5e6f12d0-2c8b-4e11-849a-b1eb17999672
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3338293655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.3338293655
Directory /workspace/23.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/23.usbdev_fifo_rst.4059542152
Short name T2503
Test name
Test status
Simulation time 171262280 ps
CPU time 1.86 seconds
Started Aug 05 05:36:49 PM PDT 24
Finished Aug 05 05:36:51 PM PDT 24
Peak memory 207460 kb
Host smart-2564cf81-0f9e-420f-96ff-f94dbeb948d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40595
42152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.4059542152
Directory /workspace/23.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/23.usbdev_in_iso.3595751572
Short name T2938
Test name
Test status
Simulation time 196180551 ps
CPU time 1.02 seconds
Started Aug 05 05:36:46 PM PDT 24
Finished Aug 05 05:36:47 PM PDT 24
Peak memory 207356 kb
Host smart-49b9d54c-d94d-482f-a302-2411dbdad2da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3595751572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3595751572
Directory /workspace/23.usbdev_in_iso/latest


Test location /workspace/coverage/default/23.usbdev_in_stall.2975219454
Short name T1797
Test name
Test status
Simulation time 147029961 ps
CPU time 0.87 seconds
Started Aug 05 05:36:45 PM PDT 24
Finished Aug 05 05:36:46 PM PDT 24
Peak memory 207376 kb
Host smart-2cd6bfa6-295d-46e1-83f6-60a403dae927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29752
19454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2975219454
Directory /workspace/23.usbdev_in_stall/latest


Test location /workspace/coverage/default/23.usbdev_in_trans.1166460795
Short name T2537
Test name
Test status
Simulation time 245624244 ps
CPU time 1.01 seconds
Started Aug 05 05:36:45 PM PDT 24
Finished Aug 05 05:36:46 PM PDT 24
Peak memory 207416 kb
Host smart-d0c410d4-4699-47ea-86db-2f39c930e4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11664
60795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1166460795
Directory /workspace/23.usbdev_in_trans/latest


Test location /workspace/coverage/default/23.usbdev_invalid_sync.1983128810
Short name T698
Test name
Test status
Simulation time 4872750159 ps
CPU time 145.03 seconds
Started Aug 05 05:36:45 PM PDT 24
Finished Aug 05 05:39:10 PM PDT 24
Peak memory 218204 kb
Host smart-c23cc1b4-4507-4ee1-995f-de8fa1cbcf8f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1983128810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.1983128810
Directory /workspace/23.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/23.usbdev_iso_retraction.418539223
Short name T104
Test name
Test status
Simulation time 10996238752 ps
CPU time 85.33 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:38:26 PM PDT 24
Peak memory 207700 kb
Host smart-2048a0b6-bb8f-4cf1-b236-1bf63d0ac932
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=418539223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.418539223
Directory /workspace/23.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/23.usbdev_link_in_err.776481231
Short name T1713
Test name
Test status
Simulation time 197659921 ps
CPU time 0.98 seconds
Started Aug 05 05:36:50 PM PDT 24
Finished Aug 05 05:36:51 PM PDT 24
Peak memory 207368 kb
Host smart-328e67e2-5bfd-4696-a97f-4b8129a41275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77648
1231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.776481231
Directory /workspace/23.usbdev_link_in_err/latest


Test location /workspace/coverage/default/23.usbdev_link_resume.3228049439
Short name T74
Test name
Test status
Simulation time 26025069294 ps
CPU time 44.38 seconds
Started Aug 05 05:36:47 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 215936 kb
Host smart-a0b16a29-36ae-47e1-9e88-682bdf236721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32280
49439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.3228049439
Directory /workspace/23.usbdev_link_resume/latest


Test location /workspace/coverage/default/23.usbdev_link_suspend.4251210385
Short name T879
Test name
Test status
Simulation time 9641150254 ps
CPU time 12.06 seconds
Started Aug 05 05:36:59 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207668 kb
Host smart-ccfefe7e-b03d-4e8f-b392-9c2d5a8b15c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42512
10385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.4251210385
Directory /workspace/23.usbdev_link_suspend/latest


Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3851749052
Short name T3076
Test name
Test status
Simulation time 5032828102 ps
CPU time 148.58 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:39:30 PM PDT 24
Peak memory 218156 kb
Host smart-7d3d4f17-a6b3-4b9c-957c-d0779dcd9d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517
49052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3851749052
Directory /workspace/23.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1195529824
Short name T1152
Test name
Test status
Simulation time 2278597010 ps
CPU time 22.54 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:22 PM PDT 24
Peak memory 217504 kb
Host smart-1a6f65dc-f8c2-449c-b6cf-f7d4ecc08352
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1195529824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1195529824
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.1698074931
Short name T2784
Test name
Test status
Simulation time 251300193 ps
CPU time 1 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207324 kb
Host smart-1911d1d5-4aea-493f-84e0-5e652826eea5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1698074931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.1698074931
Directory /workspace/23.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.4169295823
Short name T1473
Test name
Test status
Simulation time 187502264 ps
CPU time 0.94 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207324 kb
Host smart-c3a20494-243f-4f6e-9b7f-4cab031db97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41692
95823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.4169295823
Directory /workspace/23.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.4279417530
Short name T2613
Test name
Test status
Simulation time 1842790766 ps
CPU time 49.63 seconds
Started Aug 05 05:36:59 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 223872 kb
Host smart-b2d0ba4f-aae4-47fd-9831-4270064fcbb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42794
17530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.4279417530
Directory /workspace/23.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2076856405
Short name T2374
Test name
Test status
Simulation time 2597093634 ps
CPU time 27.39 seconds
Started Aug 05 05:36:54 PM PDT 24
Finished Aug 05 05:37:21 PM PDT 24
Peak memory 224080 kb
Host smart-2e6c641e-7073-4f4f-9d86-40a41ea6ea2d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2076856405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2076856405
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1254716333
Short name T888
Test name
Test status
Simulation time 184010424 ps
CPU time 0.87 seconds
Started Aug 05 05:37:02 PM PDT 24
Finished Aug 05 05:37:03 PM PDT 24
Peak memory 207296 kb
Host smart-d0c8ab7f-f2ee-4d90-8b44-088efc9b9665
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1254716333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1254716333
Directory /workspace/23.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1580635163
Short name T720
Test name
Test status
Simulation time 172800170 ps
CPU time 0.89 seconds
Started Aug 05 05:37:02 PM PDT 24
Finished Aug 05 05:37:03 PM PDT 24
Peak memory 207340 kb
Host smart-701f11e8-7e77-49cf-a49f-3e348fe0dcae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
35163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1580635163
Directory /workspace/23.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/23.usbdev_nak_trans.3276895177
Short name T2081
Test name
Test status
Simulation time 188919404 ps
CPU time 0.9 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 207348 kb
Host smart-8c26f0b1-3960-47c2-b355-83da28b24542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32768
95177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3276895177
Directory /workspace/23.usbdev_nak_trans/latest


Test location /workspace/coverage/default/23.usbdev_out_iso.126188620
Short name T2947
Test name
Test status
Simulation time 164251323 ps
CPU time 0.91 seconds
Started Aug 05 05:37:08 PM PDT 24
Finished Aug 05 05:37:09 PM PDT 24
Peak memory 207400 kb
Host smart-32fd8e3e-1189-4532-9f5c-b4c0b470b84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12618
8620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.126188620
Directory /workspace/23.usbdev_out_iso/latest


Test location /workspace/coverage/default/23.usbdev_out_stall.4092423783
Short name T820
Test name
Test status
Simulation time 148335196 ps
CPU time 0.81 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:05 PM PDT 24
Peak memory 207416 kb
Host smart-5b67c665-ea40-4729-978e-165fb01e4686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40924
23783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.4092423783
Directory /workspace/23.usbdev_out_stall/latest


Test location /workspace/coverage/default/23.usbdev_out_trans_nak.672071825
Short name T737
Test name
Test status
Simulation time 182246445 ps
CPU time 0.92 seconds
Started Aug 05 05:36:59 PM PDT 24
Finished Aug 05 05:37:00 PM PDT 24
Peak memory 207264 kb
Host smart-a80fd15b-aaac-4c2d-8a1a-6dabd51f0027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67207
1825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.672071825
Directory /workspace/23.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1045504265
Short name T1197
Test name
Test status
Simulation time 206022310 ps
CPU time 1.01 seconds
Started Aug 05 05:36:55 PM PDT 24
Finished Aug 05 05:36:56 PM PDT 24
Peak memory 207368 kb
Host smart-968679ed-5357-4f93-9c6b-a3ae9bb1a956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10455
04265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1045504265
Directory /workspace/23.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.3494382912
Short name T795
Test name
Test status
Simulation time 236935805 ps
CPU time 1.08 seconds
Started Aug 05 05:37:13 PM PDT 24
Finished Aug 05 05:37:14 PM PDT 24
Peak memory 207352 kb
Host smart-a65d8281-324e-4588-90ee-0c289450c833
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3494382912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3494382912
Directory /workspace/23.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.344404904
Short name T1945
Test name
Test status
Simulation time 178856807 ps
CPU time 0.85 seconds
Started Aug 05 05:36:51 PM PDT 24
Finished Aug 05 05:36:52 PM PDT 24
Peak memory 207264 kb
Host smart-677af446-5646-48ce-a8f9-0aa2af8d7a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34440
4904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.344404904
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.4074010728
Short name T1530
Test name
Test status
Simulation time 43031703 ps
CPU time 0.7 seconds
Started Aug 05 05:37:07 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207316 kb
Host smart-3400911d-4831-47b6-a3b6-6506a32c7ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40740
10728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.4074010728
Directory /workspace/23.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3088421637
Short name T1740
Test name
Test status
Simulation time 9946963231 ps
CPU time 24.59 seconds
Started Aug 05 05:36:57 PM PDT 24
Finished Aug 05 05:37:22 PM PDT 24
Peak memory 215808 kb
Host smart-066848b6-0517-4dda-97c8-5a13da9ff068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30884
21637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3088421637
Directory /workspace/23.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/23.usbdev_pkt_received.3587820471
Short name T2445
Test name
Test status
Simulation time 210539361 ps
CPU time 0.94 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 207312 kb
Host smart-b1cb160b-0ff9-4a10-994e-ff57b49477c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35878
20471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3587820471
Directory /workspace/23.usbdev_pkt_received/latest


Test location /workspace/coverage/default/23.usbdev_pkt_sent.4135897885
Short name T3072
Test name
Test status
Simulation time 209036047 ps
CPU time 0.94 seconds
Started Aug 05 05:36:53 PM PDT 24
Finished Aug 05 05:36:54 PM PDT 24
Peak memory 207304 kb
Host smart-b5b276ed-efb6-4805-8c83-a49184403bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41358
97885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.4135897885
Directory /workspace/23.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.801316001
Short name T1199
Test name
Test status
Simulation time 210720849 ps
CPU time 0.95 seconds
Started Aug 05 05:37:03 PM PDT 24
Finished Aug 05 05:37:04 PM PDT 24
Peak memory 207224 kb
Host smart-31b37df0-6b34-4c19-85ef-98cd94b2ae93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80131
6001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.801316001
Directory /workspace/23.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3270302161
Short name T514
Test name
Test status
Simulation time 151153479 ps
CPU time 0.83 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 207364 kb
Host smart-1b1ae600-da7b-4146-8b5e-bb0a673e2c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32703
02161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3270302161
Directory /workspace/23.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2161962934
Short name T2190
Test name
Test status
Simulation time 190748224 ps
CPU time 0.85 seconds
Started Aug 05 05:37:03 PM PDT 24
Finished Aug 05 05:37:04 PM PDT 24
Peak memory 207308 kb
Host smart-13353d12-1741-434f-ad81-6e2018f6d13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21619
62934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2161962934
Directory /workspace/23.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/23.usbdev_rx_full.3944159944
Short name T289
Test name
Test status
Simulation time 266019934 ps
CPU time 1.17 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 207256 kb
Host smart-01477222-e7ce-4f23-9d3e-91df719dffcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39441
59944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.3944159944
Directory /workspace/23.usbdev_rx_full/latest


Test location /workspace/coverage/default/23.usbdev_setup_stage.1768297942
Short name T2512
Test name
Test status
Simulation time 161430094 ps
CPU time 0.85 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:05 PM PDT 24
Peak memory 207268 kb
Host smart-a282a849-05de-4b41-a7fd-1c13e8b6c99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17682
97942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1768297942
Directory /workspace/23.usbdev_setup_stage/latest


Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2504860505
Short name T2698
Test name
Test status
Simulation time 173505341 ps
CPU time 0.88 seconds
Started Aug 05 05:36:56 PM PDT 24
Finished Aug 05 05:36:57 PM PDT 24
Peak memory 207268 kb
Host smart-839add19-3c08-4fc2-8d20-6d0e9a8da909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25048
60505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2504860505
Directory /workspace/23.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/23.usbdev_smoke.1881778363
Short name T2719
Test name
Test status
Simulation time 280570732 ps
CPU time 1.11 seconds
Started Aug 05 05:36:49 PM PDT 24
Finished Aug 05 05:36:50 PM PDT 24
Peak memory 207272 kb
Host smart-39211159-c088-42a1-8ecf-6d53a8adf012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18817
78363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1881778363
Directory /workspace/23.usbdev_smoke/latest


Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1964547837
Short name T1345
Test name
Test status
Simulation time 2158561700 ps
CPU time 23 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:24 PM PDT 24
Peak memory 224048 kb
Host smart-86b719a7-5886-437a-95e9-0cce449b9581
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1964547837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1964547837
Directory /workspace/23.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.841049620
Short name T793
Test name
Test status
Simulation time 165700950 ps
CPU time 0.84 seconds
Started Aug 05 05:37:06 PM PDT 24
Finished Aug 05 05:37:07 PM PDT 24
Peak memory 207352 kb
Host smart-02afc0a1-a9ca-4669-a4e1-85a7916ec58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84104
9620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.841049620
Directory /workspace/23.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/23.usbdev_stall_trans.1666407451
Short name T511
Test name
Test status
Simulation time 159382110 ps
CPU time 0.94 seconds
Started Aug 05 05:36:58 PM PDT 24
Finished Aug 05 05:36:59 PM PDT 24
Peak memory 207396 kb
Host smart-a962d375-d869-41fa-ae4b-b5acfd620dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16664
07451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1666407451
Directory /workspace/23.usbdev_stall_trans/latest


Test location /workspace/coverage/default/23.usbdev_stream_len_max.2073030178
Short name T2735
Test name
Test status
Simulation time 1230241387 ps
CPU time 2.98 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:03 PM PDT 24
Peak memory 207472 kb
Host smart-562911c6-e762-40c8-858f-1c478411e38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20730
30178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2073030178
Directory /workspace/23.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/23.usbdev_streaming_out.1921933357
Short name T2559
Test name
Test status
Simulation time 3614320961 ps
CPU time 27.25 seconds
Started Aug 05 05:36:59 PM PDT 24
Finished Aug 05 05:37:26 PM PDT 24
Peak memory 215832 kb
Host smart-4a7cce5f-3195-45b0-a966-e20f2d4627b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19219
33357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.1921933357
Directory /workspace/23.usbdev_streaming_out/latest


Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.2573625039
Short name T2325
Test name
Test status
Simulation time 152168916 ps
CPU time 0.87 seconds
Started Aug 05 05:36:45 PM PDT 24
Finished Aug 05 05:36:46 PM PDT 24
Peak memory 207356 kb
Host smart-1a653b47-2a50-4370-8823-806f25dd64d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573625039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.2573625039
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/24.usbdev_alert_test.2022741720
Short name T3100
Test name
Test status
Simulation time 45158564 ps
CPU time 0.68 seconds
Started Aug 05 05:37:07 PM PDT 24
Finished Aug 05 05:37:08 PM PDT 24
Peak memory 207376 kb
Host smart-77b51a6f-7e3d-4ae3-ab0c-b06c614dd757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2022741720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2022741720
Directory /workspace/24.usbdev_alert_test/latest


Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.259773093
Short name T700
Test name
Test status
Simulation time 4614492158 ps
CPU time 7.62 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:20 PM PDT 24
Peak memory 215852 kb
Host smart-f7292923-381c-4f81-9391-64753816f059
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259773093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ao
n_wake_disconnect.259773093
Directory /workspace/24.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2097817388
Short name T15
Test name
Test status
Simulation time 13710884425 ps
CPU time 18.46 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:19 PM PDT 24
Peak memory 215692 kb
Host smart-9c49ae87-2993-4681-b30f-d90abe1a26c7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097817388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2097817388
Directory /workspace/24.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1065711920
Short name T1078
Test name
Test status
Simulation time 25564388167 ps
CPU time 27.88 seconds
Started Aug 05 05:36:57 PM PDT 24
Finished Aug 05 05:37:25 PM PDT 24
Peak memory 215800 kb
Host smart-6526a408-885d-434d-8198-7282dca71963
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065711920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.1065711920
Directory /workspace/24.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/24.usbdev_av_buffer.2978023369
Short name T1597
Test name
Test status
Simulation time 162652582 ps
CPU time 0.93 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207296 kb
Host smart-cd4183fd-6c65-4f80-990d-8a2e20d1011a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29780
23369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2978023369
Directory /workspace/24.usbdev_av_buffer/latest


Test location /workspace/coverage/default/24.usbdev_bitstuff_err.17505300
Short name T2532
Test name
Test status
Simulation time 174033369 ps
CPU time 0.85 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207316 kb
Host smart-d1d3990f-87fc-49d4-8b3c-f3139f4b115b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17505
300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.17505300
Directory /workspace/24.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.4161563155
Short name T994
Test name
Test status
Simulation time 188222869 ps
CPU time 0.95 seconds
Started Aug 05 05:37:19 PM PDT 24
Finished Aug 05 05:37:20 PM PDT 24
Peak memory 207424 kb
Host smart-7b8b2b9b-85b7-4768-8308-09e7f540db9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41615
63155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.4161563155
Directory /workspace/24.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3063399171
Short name T1936
Test name
Test status
Simulation time 645397090 ps
CPU time 1.68 seconds
Started Aug 05 05:36:51 PM PDT 24
Finished Aug 05 05:36:52 PM PDT 24
Peak memory 207476 kb
Host smart-0a8a0d0b-08c7-4557-bf8e-f41f2462577c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3063399171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3063399171
Directory /workspace/24.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/24.usbdev_device_address.2463508417
Short name T1402
Test name
Test status
Simulation time 46719495284 ps
CPU time 71.29 seconds
Started Aug 05 05:37:03 PM PDT 24
Finished Aug 05 05:38:14 PM PDT 24
Peak memory 207708 kb
Host smart-32b70c36-312c-43ab-aff6-4c0b267f73d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24635
08417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2463508417
Directory /workspace/24.usbdev_device_address/latest


Test location /workspace/coverage/default/24.usbdev_device_timeout.1514834593
Short name T1568
Test name
Test status
Simulation time 4931789182 ps
CPU time 34.76 seconds
Started Aug 05 05:36:58 PM PDT 24
Finished Aug 05 05:37:33 PM PDT 24
Peak memory 207632 kb
Host smart-7d7293bd-2262-4f2c-8026-b1f6b7fb938e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514834593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.1514834593
Directory /workspace/24.usbdev_device_timeout/latest


Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3822922180
Short name T2354
Test name
Test status
Simulation time 1297001839 ps
CPU time 2.75 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:03 PM PDT 24
Peak memory 207260 kb
Host smart-d37375d1-d40f-4bc7-8ed8-70ac8c234868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38229
22180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3822922180
Directory /workspace/24.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/24.usbdev_disconnected.4189709584
Short name T2817
Test name
Test status
Simulation time 182915979 ps
CPU time 0.83 seconds
Started Aug 05 05:37:08 PM PDT 24
Finished Aug 05 05:37:09 PM PDT 24
Peak memory 207368 kb
Host smart-8bd5fee7-e6c9-4c24-8b6a-06dbf9bc861d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41897
09584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.4189709584
Directory /workspace/24.usbdev_disconnected/latest


Test location /workspace/coverage/default/24.usbdev_enable.3259357952
Short name T1357
Test name
Test status
Simulation time 41482935 ps
CPU time 0.77 seconds
Started Aug 05 05:36:52 PM PDT 24
Finished Aug 05 05:36:53 PM PDT 24
Peak memory 207316 kb
Host smart-e609d1ca-e3f2-43c1-889e-070d61d5d2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32593
57952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3259357952
Directory /workspace/24.usbdev_enable/latest


Test location /workspace/coverage/default/24.usbdev_endpoint_access.4063924288
Short name T1996
Test name
Test status
Simulation time 711765632 ps
CPU time 2.02 seconds
Started Aug 05 05:36:58 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207544 kb
Host smart-2a9de3b3-b693-4ef8-8a0c-c1b226e45011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40639
24288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.4063924288
Directory /workspace/24.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/24.usbdev_endpoint_types.3994943009
Short name T356
Test name
Test status
Simulation time 655148791 ps
CPU time 1.74 seconds
Started Aug 05 05:37:19 PM PDT 24
Finished Aug 05 05:37:21 PM PDT 24
Peak memory 207368 kb
Host smart-268cb9c0-4ad2-49fb-9a0c-6dd30de2c9f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3994943009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.3994943009
Directory /workspace/24.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/24.usbdev_fifo_rst.1836490641
Short name T1809
Test name
Test status
Simulation time 167458277 ps
CPU time 1.28 seconds
Started Aug 05 05:37:05 PM PDT 24
Finished Aug 05 05:37:06 PM PDT 24
Peak memory 207528 kb
Host smart-3b5bc2c9-fe41-401b-8f12-8447fd105f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18364
90641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1836490641
Directory /workspace/24.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/24.usbdev_in_iso.479787425
Short name T1886
Test name
Test status
Simulation time 229949027 ps
CPU time 1.21 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 215724 kb
Host smart-dad71f51-22cb-4d5c-9ec4-90a4134808eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=479787425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.479787425
Directory /workspace/24.usbdev_in_iso/latest


Test location /workspace/coverage/default/24.usbdev_in_stall.3435158697
Short name T3023
Test name
Test status
Simulation time 142095656 ps
CPU time 0.81 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 207348 kb
Host smart-0de9649c-f53e-42da-abba-cc906025f216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34351
58697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3435158697
Directory /workspace/24.usbdev_in_stall/latest


Test location /workspace/coverage/default/24.usbdev_in_trans.3430722647
Short name T898
Test name
Test status
Simulation time 234955424 ps
CPU time 1.04 seconds
Started Aug 05 05:36:57 PM PDT 24
Finished Aug 05 05:36:58 PM PDT 24
Peak memory 207352 kb
Host smart-a056cbc4-ae22-49cd-9bce-cd637a06d7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34307
22647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3430722647
Directory /workspace/24.usbdev_in_trans/latest


Test location /workspace/coverage/default/24.usbdev_invalid_sync.3275415508
Short name T1085
Test name
Test status
Simulation time 4242767069 ps
CPU time 117.5 seconds
Started Aug 05 05:36:59 PM PDT 24
Finished Aug 05 05:38:57 PM PDT 24
Peak memory 215828 kb
Host smart-a59d4487-c8d6-4e89-bc7a-66fea21ce114
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3275415508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.3275415508
Directory /workspace/24.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/24.usbdev_iso_retraction.1358664786
Short name T1733
Test name
Test status
Simulation time 7594463885 ps
CPU time 53.35 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:57 PM PDT 24
Peak memory 207668 kb
Host smart-b39b1320-f426-4266-be49-f58f5c004732
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1358664786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.1358664786
Directory /workspace/24.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/24.usbdev_link_in_err.3530370137
Short name T1916
Test name
Test status
Simulation time 218963323 ps
CPU time 1.04 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207248 kb
Host smart-82075575-8f7d-4de8-a406-d7a36d372bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35303
70137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3530370137
Directory /workspace/24.usbdev_link_in_err/latest


Test location /workspace/coverage/default/24.usbdev_link_resume.1881797813
Short name T960
Test name
Test status
Simulation time 31090553332 ps
CPU time 50.44 seconds
Started Aug 05 05:37:07 PM PDT 24
Finished Aug 05 05:37:58 PM PDT 24
Peak memory 207660 kb
Host smart-6d4554cf-40ad-43b4-8a02-b9be53e78a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18817
97813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1881797813
Directory /workspace/24.usbdev_link_resume/latest


Test location /workspace/coverage/default/24.usbdev_link_suspend.1263139961
Short name T2058
Test name
Test status
Simulation time 9027596095 ps
CPU time 10.75 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:15 PM PDT 24
Peak memory 207588 kb
Host smart-5910f972-36e4-400c-8018-9a3fe25e1774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12631
39961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1263139961
Directory /workspace/24.usbdev_link_suspend/latest


Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.4072981413
Short name T159
Test name
Test status
Simulation time 2646975018 ps
CPU time 25.57 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:37:26 PM PDT 24
Peak memory 218304 kb
Host smart-594a2689-310f-4360-bd8c-5cfe556b07b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40729
81413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.4072981413
Directory /workspace/24.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1335810817
Short name T2011
Test name
Test status
Simulation time 2933237390 ps
CPU time 80.52 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:38:22 PM PDT 24
Peak memory 215908 kb
Host smart-01b2ba04-114f-4e1f-a4aa-5c691e207364
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1335810817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1335810817
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.3314793146
Short name T1902
Test name
Test status
Simulation time 258019579 ps
CPU time 1 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:05 PM PDT 24
Peak memory 207400 kb
Host smart-dbf489c2-201b-4789-871d-53c78ff59378
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3314793146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3314793146
Directory /workspace/24.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2488541891
Short name T2307
Test name
Test status
Simulation time 180571296 ps
CPU time 0.93 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:05 PM PDT 24
Peak memory 207404 kb
Host smart-4e5b5d49-428e-4c18-8466-1b41f9fbf3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24885
41891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2488541891
Directory /workspace/24.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.4017587796
Short name T3029
Test name
Test status
Simulation time 2317920807 ps
CPU time 63.9 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:38:05 PM PDT 24
Peak memory 217568 kb
Host smart-3f04876f-15b7-4114-be3f-179872951bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40175
87796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.4017587796
Directory /workspace/24.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.4049109293
Short name T841
Test name
Test status
Simulation time 2917001399 ps
CPU time 21.3 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:37:22 PM PDT 24
Peak memory 215908 kb
Host smart-a6ba94ab-2d8c-4da2-a8c2-8e4a67eb4fca
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4049109293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.4049109293
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.2989989619
Short name T1134
Test name
Test status
Simulation time 158568486 ps
CPU time 0.84 seconds
Started Aug 05 05:37:06 PM PDT 24
Finished Aug 05 05:37:07 PM PDT 24
Peak memory 207348 kb
Host smart-c020fdc8-04b3-4366-898f-ee09a4e2cdae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2989989619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.2989989619
Directory /workspace/24.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2401561907
Short name T2094
Test name
Test status
Simulation time 157428298 ps
CPU time 0.88 seconds
Started Aug 05 05:37:03 PM PDT 24
Finished Aug 05 05:37:04 PM PDT 24
Peak memory 207344 kb
Host smart-619e861b-36a7-4285-8b8d-886f3cf22b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24015
61907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2401561907
Directory /workspace/24.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/24.usbdev_nak_trans.1707510572
Short name T144
Test name
Test status
Simulation time 210629105 ps
CPU time 0.91 seconds
Started Aug 05 05:36:59 PM PDT 24
Finished Aug 05 05:37:06 PM PDT 24
Peak memory 207320 kb
Host smart-693c924c-1f8d-4cc0-a03b-f4d8c9c4e6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17075
10572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1707510572
Directory /workspace/24.usbdev_nak_trans/latest


Test location /workspace/coverage/default/24.usbdev_out_iso.862031056
Short name T2534
Test name
Test status
Simulation time 170460657 ps
CPU time 0.9 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207376 kb
Host smart-99311a21-71b0-4a9d-a238-e3132dba95a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86203
1056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.862031056
Directory /workspace/24.usbdev_out_iso/latest


Test location /workspace/coverage/default/24.usbdev_out_stall.2757030698
Short name T659
Test name
Test status
Simulation time 191009825 ps
CPU time 0.9 seconds
Started Aug 05 05:37:05 PM PDT 24
Finished Aug 05 05:37:06 PM PDT 24
Peak memory 207320 kb
Host smart-2718331e-a1fd-4e62-bdc2-e2ca98bebe85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27570
30698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2757030698
Directory /workspace/24.usbdev_out_stall/latest


Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2547623109
Short name T1288
Test name
Test status
Simulation time 161016152 ps
CPU time 0.84 seconds
Started Aug 05 05:37:10 PM PDT 24
Finished Aug 05 05:37:11 PM PDT 24
Peak memory 207356 kb
Host smart-5223777b-c353-40d6-a93d-a9bbdfd1d492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25476
23109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2547623109
Directory /workspace/24.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/24.usbdev_pending_in_trans.945693664
Short name T1954
Test name
Test status
Simulation time 143760024 ps
CPU time 0.91 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:01 PM PDT 24
Peak memory 207236 kb
Host smart-b003b973-1b55-42f3-a658-1789ba4d7c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94569
3664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.945693664
Directory /workspace/24.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1241687848
Short name T2638
Test name
Test status
Simulation time 251653885 ps
CPU time 1.05 seconds
Started Aug 05 05:37:06 PM PDT 24
Finished Aug 05 05:37:07 PM PDT 24
Peak memory 207356 kb
Host smart-766ec03c-04b0-4dd1-934f-0029956a5bf9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1241687848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1241687848
Directory /workspace/24.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2071937335
Short name T1298
Test name
Test status
Simulation time 165586848 ps
CPU time 0.84 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:05 PM PDT 24
Peak memory 207348 kb
Host smart-9c6b6cf2-0168-4237-8d8a-6eaacf0310bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20719
37335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2071937335
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1094525686
Short name T2243
Test name
Test status
Simulation time 50435881 ps
CPU time 0.69 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207236 kb
Host smart-b65e0a4c-187d-4594-a7e8-f762b937186c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10945
25686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1094525686
Directory /workspace/24.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1895003640
Short name T2137
Test name
Test status
Simulation time 18794329551 ps
CPU time 45.4 seconds
Started Aug 05 05:37:09 PM PDT 24
Finished Aug 05 05:37:54 PM PDT 24
Peak memory 215904 kb
Host smart-6da073f5-38bb-4e1f-8486-9546a84bc440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18950
03640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1895003640
Directory /workspace/24.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/24.usbdev_pkt_received.2669255484
Short name T1804
Test name
Test status
Simulation time 168095001 ps
CPU time 0.91 seconds
Started Aug 05 05:37:05 PM PDT 24
Finished Aug 05 05:37:06 PM PDT 24
Peak memory 207320 kb
Host smart-66c739cc-0c81-4c6c-9bc0-59203d3b1edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26692
55484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2669255484
Directory /workspace/24.usbdev_pkt_received/latest


Test location /workspace/coverage/default/24.usbdev_pkt_sent.178943306
Short name T2411
Test name
Test status
Simulation time 201941467 ps
CPU time 0.94 seconds
Started Aug 05 05:37:08 PM PDT 24
Finished Aug 05 05:37:09 PM PDT 24
Peak memory 207340 kb
Host smart-8d790385-4a14-42f5-92e1-9a2e328e591a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17894
3306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.178943306
Directory /workspace/24.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3549632396
Short name T1441
Test name
Test status
Simulation time 238288934 ps
CPU time 1 seconds
Started Aug 05 05:37:07 PM PDT 24
Finished Aug 05 05:37:08 PM PDT 24
Peak memory 207264 kb
Host smart-5ecb1f5e-0f6e-4623-878e-b95bdf15a8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35496
32396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3549632396
Directory /workspace/24.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.457335120
Short name T2746
Test name
Test status
Simulation time 191043907 ps
CPU time 1.01 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 207376 kb
Host smart-d0cfb6f8-c94a-4a41-adcb-f25e675e6914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45733
5120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.457335120
Directory /workspace/24.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3058554057
Short name T2098
Test name
Test status
Simulation time 162783805 ps
CPU time 0.85 seconds
Started Aug 05 05:37:06 PM PDT 24
Finished Aug 05 05:37:07 PM PDT 24
Peak memory 207368 kb
Host smart-04d7e51e-d8e3-488a-92b3-13f96398ce91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30585
54057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3058554057
Directory /workspace/24.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/24.usbdev_rx_full.2163468458
Short name T1472
Test name
Test status
Simulation time 242770733 ps
CPU time 1.07 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:06 PM PDT 24
Peak memory 207336 kb
Host smart-a31dea9b-3cc5-4799-9805-38c6a72216c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21634
68458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.2163468458
Directory /workspace/24.usbdev_rx_full/latest


Test location /workspace/coverage/default/24.usbdev_setup_stage.2934030947
Short name T1375
Test name
Test status
Simulation time 147328939 ps
CPU time 0.8 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:05 PM PDT 24
Peak memory 207344 kb
Host smart-86c0777d-6909-4e95-bd9f-20723d080b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29340
30947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2934030947
Directory /workspace/24.usbdev_setup_stage/latest


Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1713173113
Short name T1244
Test name
Test status
Simulation time 149380079 ps
CPU time 0.87 seconds
Started Aug 05 05:36:57 PM PDT 24
Finished Aug 05 05:36:58 PM PDT 24
Peak memory 207240 kb
Host smart-376ec330-b6d1-43a4-a927-bce861e6122b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131
73113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1713173113
Directory /workspace/24.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/24.usbdev_smoke.3655130195
Short name T2082
Test name
Test status
Simulation time 214381184 ps
CPU time 0.99 seconds
Started Aug 05 05:37:08 PM PDT 24
Finished Aug 05 05:37:09 PM PDT 24
Peak memory 207352 kb
Host smart-086a1a92-f38d-41a8-bd9e-844f9f8301aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36551
30195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3655130195
Directory /workspace/24.usbdev_smoke/latest


Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1217729309
Short name T1455
Test name
Test status
Simulation time 2232853142 ps
CPU time 21.03 seconds
Started Aug 05 05:37:07 PM PDT 24
Finished Aug 05 05:37:28 PM PDT 24
Peak memory 224040 kb
Host smart-d3377900-4f37-4341-98c0-91a6a581f7f6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1217729309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1217729309
Directory /workspace/24.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2631327137
Short name T1424
Test name
Test status
Simulation time 149678780 ps
CPU time 0.86 seconds
Started Aug 05 05:37:08 PM PDT 24
Finished Aug 05 05:37:09 PM PDT 24
Peak memory 207344 kb
Host smart-f03b9223-ddc2-44cc-b12b-ae5af4ff826d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26313
27137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2631327137
Directory /workspace/24.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/24.usbdev_stall_trans.1852871012
Short name T1586
Test name
Test status
Simulation time 152367365 ps
CPU time 0.85 seconds
Started Aug 05 05:37:05 PM PDT 24
Finished Aug 05 05:37:06 PM PDT 24
Peak memory 207340 kb
Host smart-544a0885-16d7-4f01-b8c3-9899eaed6810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18528
71012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1852871012
Directory /workspace/24.usbdev_stall_trans/latest


Test location /workspace/coverage/default/24.usbdev_stream_len_max.3728624197
Short name T2270
Test name
Test status
Simulation time 1318927477 ps
CPU time 3.01 seconds
Started Aug 05 05:37:13 PM PDT 24
Finished Aug 05 05:37:16 PM PDT 24
Peak memory 207516 kb
Host smart-260bb059-2264-43ee-8a02-20e6b02deb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37286
24197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.3728624197
Directory /workspace/24.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/24.usbdev_streaming_out.2023952688
Short name T1043
Test name
Test status
Simulation time 2772215296 ps
CPU time 77.26 seconds
Started Aug 05 05:37:09 PM PDT 24
Finished Aug 05 05:38:27 PM PDT 24
Peak memory 224008 kb
Host smart-35685fd8-b277-40ac-9553-a07a5286ace1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20239
52688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2023952688
Directory /workspace/24.usbdev_streaming_out/latest


Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.3590763569
Short name T621
Test name
Test status
Simulation time 4351546538 ps
CPU time 35.13 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:40 PM PDT 24
Peak memory 207672 kb
Host smart-86d39598-092c-4357-9690-efe89740b08d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590763569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_hos
t_handshake.3590763569
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/25.usbdev_alert_test.310926834
Short name T3059
Test name
Test status
Simulation time 33413716 ps
CPU time 0.69 seconds
Started Aug 05 05:37:24 PM PDT 24
Finished Aug 05 05:37:25 PM PDT 24
Peak memory 207412 kb
Host smart-8b72ffa0-7f6a-403f-82de-46917aa1e77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=310926834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.310926834
Directory /workspace/25.usbdev_alert_test/latest


Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.493935984
Short name T2370
Test name
Test status
Simulation time 5043816399 ps
CPU time 6.62 seconds
Started Aug 05 05:37:02 PM PDT 24
Finished Aug 05 05:37:09 PM PDT 24
Peak memory 215184 kb
Host smart-7abac6a2-70e1-4526-b9e5-4ee4b3155156
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493935984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_ao
n_wake_disconnect.493935984
Directory /workspace/25.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2578367391
Short name T16
Test name
Test status
Simulation time 18966535440 ps
CPU time 22.55 seconds
Started Aug 05 05:36:59 PM PDT 24
Finished Aug 05 05:37:21 PM PDT 24
Peak memory 207576 kb
Host smart-d5ef130a-152f-4167-a2d3-34e1f1e02176
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578367391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2578367391
Directory /workspace/25.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.499388882
Short name T1101
Test name
Test status
Simulation time 29233490053 ps
CPU time 33.51 seconds
Started Aug 05 05:37:05 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207652 kb
Host smart-a2a8db59-446c-406c-b723-88cf4a2a466a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499388882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_ao
n_wake_resume.499388882
Directory /workspace/25.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/25.usbdev_av_buffer.895439523
Short name T688
Test name
Test status
Simulation time 159909080 ps
CPU time 0.86 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:05 PM PDT 24
Peak memory 207340 kb
Host smart-86cdddd1-5b3e-435b-9bd5-d657249a403d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89543
9523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.895439523
Directory /workspace/25.usbdev_av_buffer/latest


Test location /workspace/coverage/default/25.usbdev_bitstuff_err.4031257353
Short name T928
Test name
Test status
Simulation time 161597242 ps
CPU time 0.86 seconds
Started Aug 05 05:37:01 PM PDT 24
Finished Aug 05 05:37:02 PM PDT 24
Peak memory 207240 kb
Host smart-2572678a-95f1-43f8-9cbf-47c3faa23df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40312
57353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.4031257353
Directory /workspace/25.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.2844782582
Short name T2461
Test name
Test status
Simulation time 348439912 ps
CPU time 1.35 seconds
Started Aug 05 05:37:06 PM PDT 24
Finished Aug 05 05:37:08 PM PDT 24
Peak memory 207324 kb
Host smart-2cf19eb2-f6ca-4164-9257-bdf4ff457762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28447
82582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.2844782582
Directory /workspace/25.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2369433588
Short name T798
Test name
Test status
Simulation time 1026163316 ps
CPU time 2.84 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:07 PM PDT 24
Peak memory 207604 kb
Host smart-5b5e3a07-12ac-4d61-984d-f067dfd6490f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2369433588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2369433588
Directory /workspace/25.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/25.usbdev_device_address.2710630882
Short name T1581
Test name
Test status
Simulation time 39978897718 ps
CPU time 56.24 seconds
Started Aug 05 05:37:00 PM PDT 24
Finished Aug 05 05:37:56 PM PDT 24
Peak memory 207540 kb
Host smart-c9a23fb9-14f1-477d-9fc2-e8e334abc417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27106
30882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.2710630882
Directory /workspace/25.usbdev_device_address/latest


Test location /workspace/coverage/default/25.usbdev_device_timeout.62514239
Short name T2189
Test name
Test status
Simulation time 1225938380 ps
CPU time 27.67 seconds
Started Aug 05 05:37:06 PM PDT 24
Finished Aug 05 05:37:33 PM PDT 24
Peak memory 207436 kb
Host smart-21f65ebe-b872-4173-8187-5868c28f8213
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62514239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.62514239
Directory /workspace/25.usbdev_device_timeout/latest


Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1529266360
Short name T656
Test name
Test status
Simulation time 465024800 ps
CPU time 1.37 seconds
Started Aug 05 05:37:13 PM PDT 24
Finished Aug 05 05:37:14 PM PDT 24
Peak memory 207384 kb
Host smart-34ae05a2-2d60-46a9-a452-f3fa8c4d0c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15292
66360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1529266360
Directory /workspace/25.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/25.usbdev_disconnected.689052595
Short name T2182
Test name
Test status
Simulation time 160412403 ps
CPU time 0.83 seconds
Started Aug 05 05:37:05 PM PDT 24
Finished Aug 05 05:37:06 PM PDT 24
Peak memory 207224 kb
Host smart-45c1c821-7b50-4648-bcd3-fbee0f15a734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68905
2595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.689052595
Directory /workspace/25.usbdev_disconnected/latest


Test location /workspace/coverage/default/25.usbdev_enable.533043591
Short name T2631
Test name
Test status
Simulation time 33184128 ps
CPU time 0.71 seconds
Started Aug 05 05:37:06 PM PDT 24
Finished Aug 05 05:37:07 PM PDT 24
Peak memory 207328 kb
Host smart-d3af05bb-22ec-4ca1-8612-230791429a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53304
3591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.533043591
Directory /workspace/25.usbdev_enable/latest


Test location /workspace/coverage/default/25.usbdev_endpoint_access.910690915
Short name T907
Test name
Test status
Simulation time 937315276 ps
CPU time 2.54 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:15 PM PDT 24
Peak memory 207480 kb
Host smart-78be369e-bd8e-45f4-90fc-f6c37db62d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91069
0915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.910690915
Directory /workspace/25.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/25.usbdev_endpoint_types.2267466820
Short name T410
Test name
Test status
Simulation time 499802527 ps
CPU time 1.27 seconds
Started Aug 05 05:37:10 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207324 kb
Host smart-44c896e4-000f-4918-a8bf-c9a16aecd047
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2267466820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.2267466820
Directory /workspace/25.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/25.usbdev_fifo_rst.3359643367
Short name T1748
Test name
Test status
Simulation time 199093444 ps
CPU time 2.5 seconds
Started Aug 05 05:37:10 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 207592 kb
Host smart-71faf76e-f7ef-4ba8-a5a7-a66282a67e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33596
43367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3359643367
Directory /workspace/25.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/25.usbdev_in_iso.2543751407
Short name T3092
Test name
Test status
Simulation time 255276961 ps
CPU time 1.18 seconds
Started Aug 05 05:37:02 PM PDT 24
Finished Aug 05 05:37:04 PM PDT 24
Peak memory 207564 kb
Host smart-e302b212-9ad7-4473-aaa5-d4a6cbe6121f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2543751407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2543751407
Directory /workspace/25.usbdev_in_iso/latest


Test location /workspace/coverage/default/25.usbdev_in_stall.686715004
Short name T1598
Test name
Test status
Simulation time 187259509 ps
CPU time 0.89 seconds
Started Aug 05 05:37:10 PM PDT 24
Finished Aug 05 05:37:11 PM PDT 24
Peak memory 207336 kb
Host smart-f3ce14fd-8290-4922-88e8-d72407619569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68671
5004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.686715004
Directory /workspace/25.usbdev_in_stall/latest


Test location /workspace/coverage/default/25.usbdev_in_trans.3674039983
Short name T1037
Test name
Test status
Simulation time 241266300 ps
CPU time 1.11 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207408 kb
Host smart-3c2bce46-36ce-42d0-8b82-aab48995495d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36740
39983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3674039983
Directory /workspace/25.usbdev_in_trans/latest


Test location /workspace/coverage/default/25.usbdev_invalid_sync.2391647737
Short name T2795
Test name
Test status
Simulation time 2977767490 ps
CPU time 83.92 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:38:35 PM PDT 24
Peak memory 217604 kb
Host smart-423f6087-453b-45f8-b367-204e905fbdc8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2391647737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2391647737
Directory /workspace/25.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/25.usbdev_iso_retraction.2966088917
Short name T1224
Test name
Test status
Simulation time 4990912421 ps
CPU time 36.37 seconds
Started Aug 05 05:37:07 PM PDT 24
Finished Aug 05 05:37:43 PM PDT 24
Peak memory 207620 kb
Host smart-d54dd7ba-3a34-4008-9d59-7025b7abdf3d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2966088917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.2966088917
Directory /workspace/25.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/25.usbdev_link_in_err.2892353004
Short name T1166
Test name
Test status
Simulation time 165708748 ps
CPU time 0.88 seconds
Started Aug 05 05:37:35 PM PDT 24
Finished Aug 05 05:37:36 PM PDT 24
Peak memory 207396 kb
Host smart-def61f81-00cd-47d9-976a-b437a84d474a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28923
53004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2892353004
Directory /workspace/25.usbdev_link_in_err/latest


Test location /workspace/coverage/default/25.usbdev_link_resume.3839529987
Short name T2308
Test name
Test status
Simulation time 12871912233 ps
CPU time 17.25 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:30 PM PDT 24
Peak memory 207492 kb
Host smart-db78d42b-6103-40d1-9122-b9425b60ba62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38395
29987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.3839529987
Directory /workspace/25.usbdev_link_resume/latest


Test location /workspace/coverage/default/25.usbdev_link_suspend.779042325
Short name T2183
Test name
Test status
Simulation time 11108988716 ps
CPU time 13.79 seconds
Started Aug 05 05:37:05 PM PDT 24
Finished Aug 05 05:37:19 PM PDT 24
Peak memory 207668 kb
Host smart-1b72a20c-d1f9-4f91-b581-8fdceaf2e341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77904
2325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.779042325
Directory /workspace/25.usbdev_link_suspend/latest


Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.2026162683
Short name T2983
Test name
Test status
Simulation time 1939013551 ps
CPU time 55.49 seconds
Started Aug 05 05:37:08 PM PDT 24
Finished Aug 05 05:38:03 PM PDT 24
Peak memory 218168 kb
Host smart-711f4f9b-71f7-440d-85b0-34c6b609b45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20261
62683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.2026162683
Directory /workspace/25.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.1699338316
Short name T3042
Test name
Test status
Simulation time 3411794943 ps
CPU time 24.99 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:36 PM PDT 24
Peak memory 215928 kb
Host smart-9045470c-576b-457b-abec-058fcbe32b3f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1699338316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.1699338316
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1585502234
Short name T492
Test name
Test status
Simulation time 264114106 ps
CPU time 0.97 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207408 kb
Host smart-901b30ed-90f9-46a5-9429-2e3ccdfd860a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1585502234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1585502234
Directory /workspace/25.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.4244980104
Short name T2995
Test name
Test status
Simulation time 233506060 ps
CPU time 1.03 seconds
Started Aug 05 05:37:03 PM PDT 24
Finished Aug 05 05:37:05 PM PDT 24
Peak memory 207296 kb
Host smart-7db0f6b9-059b-4310-ab50-83ef3a9d58c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42449
80104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.4244980104
Directory /workspace/25.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2107409997
Short name T837
Test name
Test status
Simulation time 2273224861 ps
CPU time 17.21 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:28 PM PDT 24
Peak memory 217232 kb
Host smart-f73aff9a-91ab-49ed-a164-5baf05b5582a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2107409997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2107409997
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.695586704
Short name T769
Test name
Test status
Simulation time 157638911 ps
CPU time 0.89 seconds
Started Aug 05 05:37:21 PM PDT 24
Finished Aug 05 05:37:22 PM PDT 24
Peak memory 207308 kb
Host smart-576e0833-1cb6-43ee-9f20-240bb2e2bfaf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=695586704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.695586704
Directory /workspace/25.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3887335231
Short name T3130
Test name
Test status
Simulation time 142189392 ps
CPU time 0.83 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 207424 kb
Host smart-02a15b26-83e8-4655-af9e-2bcd6ffc9342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38873
35231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3887335231
Directory /workspace/25.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/25.usbdev_out_iso.3323417143
Short name T2740
Test name
Test status
Simulation time 185903352 ps
CPU time 0.97 seconds
Started Aug 05 05:37:09 PM PDT 24
Finished Aug 05 05:37:10 PM PDT 24
Peak memory 207364 kb
Host smart-ee91faad-16fa-447b-a864-2f88d90ee25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33234
17143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3323417143
Directory /workspace/25.usbdev_out_iso/latest


Test location /workspace/coverage/default/25.usbdev_out_stall.3102922354
Short name T3107
Test name
Test status
Simulation time 162598150 ps
CPU time 0.86 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207348 kb
Host smart-2e21797f-f214-4f02-895b-ecd5b3492526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31029
22354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3102922354
Directory /workspace/25.usbdev_out_stall/latest


Test location /workspace/coverage/default/25.usbdev_out_trans_nak.513792257
Short name T594
Test name
Test status
Simulation time 151203085 ps
CPU time 0.85 seconds
Started Aug 05 05:37:08 PM PDT 24
Finished Aug 05 05:37:09 PM PDT 24
Peak memory 207284 kb
Host smart-f260550e-b828-4f4d-b8c5-15c7f678ce0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51379
2257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.513792257
Directory /workspace/25.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/25.usbdev_pending_in_trans.36496854
Short name T3114
Test name
Test status
Simulation time 174064508 ps
CPU time 0.88 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 207276 kb
Host smart-cba7329e-7cb5-4c77-80a0-d0143febafa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36496
854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.36496854
Directory /workspace/25.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.935746626
Short name T810
Test name
Test status
Simulation time 206731405 ps
CPU time 0.91 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:17 PM PDT 24
Peak memory 207304 kb
Host smart-ef22b8c4-4028-45f7-aa33-68af91bd7884
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=935746626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.935746626
Directory /workspace/25.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3415053333
Short name T3055
Test name
Test status
Simulation time 145219975 ps
CPU time 0.82 seconds
Started Aug 05 05:37:13 PM PDT 24
Finished Aug 05 05:37:14 PM PDT 24
Peak memory 207316 kb
Host smart-cd5e48fc-56fa-4c96-b97e-8c8cede39e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34150
53333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3415053333
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.4174377296
Short name T2143
Test name
Test status
Simulation time 36594435 ps
CPU time 0.7 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207300 kb
Host smart-41c0f0a9-6b04-4e67-b53c-d79a3ef970c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41743
77296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.4174377296
Directory /workspace/25.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2595062395
Short name T2933
Test name
Test status
Simulation time 13322367435 ps
CPU time 36.38 seconds
Started Aug 05 05:37:06 PM PDT 24
Finished Aug 05 05:37:43 PM PDT 24
Peak memory 220400 kb
Host smart-713d0844-9abb-4f98-8633-be6da3dac756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25950
62395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2595062395
Directory /workspace/25.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/25.usbdev_pkt_received.2260567932
Short name T732
Test name
Test status
Simulation time 177980793 ps
CPU time 0.9 seconds
Started Aug 05 05:37:16 PM PDT 24
Finished Aug 05 05:37:22 PM PDT 24
Peak memory 207288 kb
Host smart-707577f7-83d4-47b4-a344-a69633f3bddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22605
67932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2260567932
Directory /workspace/25.usbdev_pkt_received/latest


Test location /workspace/coverage/default/25.usbdev_pkt_sent.3689073237
Short name T1724
Test name
Test status
Simulation time 208741364 ps
CPU time 0.94 seconds
Started Aug 05 05:37:05 PM PDT 24
Finished Aug 05 05:37:06 PM PDT 24
Peak memory 207304 kb
Host smart-5e74ab50-b8e5-4229-b1a8-1f4b76e3049b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36890
73237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3689073237
Directory /workspace/25.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.725953492
Short name T1474
Test name
Test status
Simulation time 186615642 ps
CPU time 0.89 seconds
Started Aug 05 05:37:07 PM PDT 24
Finished Aug 05 05:37:08 PM PDT 24
Peak memory 207296 kb
Host smart-dc8fd96e-807f-4122-8bde-1ccce787742b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72595
3492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.725953492
Directory /workspace/25.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2386326598
Short name T494
Test name
Test status
Simulation time 206586166 ps
CPU time 0.88 seconds
Started Aug 05 05:37:18 PM PDT 24
Finished Aug 05 05:37:19 PM PDT 24
Peak memory 207272 kb
Host smart-b3c53b25-b10f-4d1f-9433-f57c97d6c102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23863
26598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2386326598
Directory /workspace/25.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/25.usbdev_rx_crc_err.2239579700
Short name T81
Test name
Test status
Simulation time 174223023 ps
CPU time 0.85 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 207268 kb
Host smart-965c6913-9bf9-4b81-a31a-a89de90ca5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22395
79700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.2239579700
Directory /workspace/25.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/25.usbdev_rx_full.2482991429
Short name T2152
Test name
Test status
Simulation time 299197314 ps
CPU time 1.25 seconds
Started Aug 05 05:37:08 PM PDT 24
Finished Aug 05 05:37:09 PM PDT 24
Peak memory 207268 kb
Host smart-4f740111-df20-495f-832a-965eb515f0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24829
91429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.2482991429
Directory /workspace/25.usbdev_rx_full/latest


Test location /workspace/coverage/default/25.usbdev_setup_stage.1119307412
Short name T2739
Test name
Test status
Simulation time 149800577 ps
CPU time 0.85 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 207192 kb
Host smart-f04ec9aa-8a4d-48a9-9eae-aa88938ef55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11193
07412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1119307412
Directory /workspace/25.usbdev_setup_stage/latest


Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2636613497
Short name T963
Test name
Test status
Simulation time 183944025 ps
CPU time 0.87 seconds
Started Aug 05 05:37:09 PM PDT 24
Finished Aug 05 05:37:10 PM PDT 24
Peak memory 207272 kb
Host smart-055288a0-65b3-4aa1-b048-378b92bab3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26366
13497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2636613497
Directory /workspace/25.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/25.usbdev_smoke.3472127475
Short name T1290
Test name
Test status
Simulation time 214872184 ps
CPU time 0.97 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:05 PM PDT 24
Peak memory 207336 kb
Host smart-e5d42e15-b029-400b-bbb5-1acd82568459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34721
27475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3472127475
Directory /workspace/25.usbdev_smoke/latest


Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.2673017021
Short name T1986
Test name
Test status
Simulation time 1748281409 ps
CPU time 13.08 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:25 PM PDT 24
Peak memory 223852 kb
Host smart-546943fd-b95b-4abb-b4c4-26a5005f87cd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2673017021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.2673017021
Directory /workspace/25.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2667911721
Short name T873
Test name
Test status
Simulation time 236325144 ps
CPU time 0.95 seconds
Started Aug 05 05:37:10 PM PDT 24
Finished Aug 05 05:37:11 PM PDT 24
Peak memory 207352 kb
Host smart-d438cca7-9b0e-4520-a1dc-09d41bee1f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26679
11721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2667911721
Directory /workspace/25.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/25.usbdev_stall_trans.3278169099
Short name T2040
Test name
Test status
Simulation time 229739299 ps
CPU time 0.98 seconds
Started Aug 05 05:37:22 PM PDT 24
Finished Aug 05 05:37:23 PM PDT 24
Peak memory 207364 kb
Host smart-704df28c-3c69-4884-882b-aff5e75c2b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32781
69099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3278169099
Directory /workspace/25.usbdev_stall_trans/latest


Test location /workspace/coverage/default/25.usbdev_stream_len_max.3926589177
Short name T1294
Test name
Test status
Simulation time 264943033 ps
CPU time 1.03 seconds
Started Aug 05 05:37:13 PM PDT 24
Finished Aug 05 05:37:14 PM PDT 24
Peak memory 207264 kb
Host smart-89c646a3-54a8-4c12-a0aa-cd1e0f190d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39265
89177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.3926589177
Directory /workspace/25.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/25.usbdev_streaming_out.1017482000
Short name T3079
Test name
Test status
Simulation time 3608908369 ps
CPU time 36.16 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 217336 kb
Host smart-16f5cfde-4762-4bd0-a15e-09582176b463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10174
82000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.1017482000
Directory /workspace/25.usbdev_streaming_out/latest


Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.297420398
Short name T1723
Test name
Test status
Simulation time 362918226 ps
CPU time 4.75 seconds
Started Aug 05 05:37:04 PM PDT 24
Finished Aug 05 05:37:09 PM PDT 24
Peak memory 207492 kb
Host smart-96557a47-8ea6-4e63-8d3b-eae842252304
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297420398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_host
_handshake.297420398
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/26.usbdev_alert_test.3012427257
Short name T1680
Test name
Test status
Simulation time 38423603 ps
CPU time 0.64 seconds
Started Aug 05 05:37:28 PM PDT 24
Finished Aug 05 05:37:28 PM PDT 24
Peak memory 207360 kb
Host smart-71846eb8-e730-4a7c-9a18-b2f159e3f6b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3012427257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.3012427257
Directory /workspace/26.usbdev_alert_test/latest


Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2617746701
Short name T2664
Test name
Test status
Simulation time 4304319291 ps
CPU time 5.58 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:17 PM PDT 24
Peak memory 215804 kb
Host smart-4797ebc7-68b3-4bc4-91e7-9ed79ce181f2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617746701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.2617746701
Directory /workspace/26.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.981450178
Short name T2706
Test name
Test status
Simulation time 14507893780 ps
CPU time 15.26 seconds
Started Aug 05 05:37:28 PM PDT 24
Finished Aug 05 05:37:43 PM PDT 24
Peak memory 215808 kb
Host smart-a9125983-dff4-480f-b335-4fcf29190194
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=981450178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.981450178
Directory /workspace/26.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1084848916
Short name T14
Test name
Test status
Simulation time 28936361363 ps
CPU time 33.56 seconds
Started Aug 05 05:37:25 PM PDT 24
Finished Aug 05 05:37:58 PM PDT 24
Peak memory 207648 kb
Host smart-3a53026b-44d1-4411-88b7-c88e4048664f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084848916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.1084848916
Directory /workspace/26.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/26.usbdev_av_buffer.1549830335
Short name T903
Test name
Test status
Simulation time 199267715 ps
CPU time 0.93 seconds
Started Aug 05 05:37:16 PM PDT 24
Finished Aug 05 05:37:17 PM PDT 24
Peak memory 207288 kb
Host smart-74590c6c-e059-43bb-b2ce-70a37d39ebb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15498
30335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1549830335
Directory /workspace/26.usbdev_av_buffer/latest


Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1527981921
Short name T1423
Test name
Test status
Simulation time 158366728 ps
CPU time 0.88 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207320 kb
Host smart-5c275baf-62e0-4113-b103-22e33d09a8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15279
81921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1527981921
Directory /workspace/26.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.538796921
Short name T1584
Test name
Test status
Simulation time 211140321 ps
CPU time 0.93 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 207272 kb
Host smart-849d5fde-15a3-4d9b-a8ec-a3ae78a15ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53879
6921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.538796921
Directory /workspace/26.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.519486068
Short name T709
Test name
Test status
Simulation time 1169917774 ps
CPU time 2.72 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:15 PM PDT 24
Peak memory 207556 kb
Host smart-40fc5130-f948-4c17-acd4-d6ab78ee2c53
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=519486068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.519486068
Directory /workspace/26.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/26.usbdev_device_address.3727018526
Short name T1963
Test name
Test status
Simulation time 27501466892 ps
CPU time 41.6 seconds
Started Aug 05 05:37:10 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207692 kb
Host smart-9ec7c867-9003-4751-bafd-e8293186d2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37270
18526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3727018526
Directory /workspace/26.usbdev_device_address/latest


Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1192798993
Short name T1457
Test name
Test status
Simulation time 770899758 ps
CPU time 2.13 seconds
Started Aug 05 05:37:18 PM PDT 24
Finished Aug 05 05:37:21 PM PDT 24
Peak memory 207256 kb
Host smart-38b44a60-434d-455b-80cf-9562317e0683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11927
98993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1192798993
Directory /workspace/26.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/26.usbdev_disconnected.3650511358
Short name T3020
Test name
Test status
Simulation time 143112900 ps
CPU time 0.88 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 207336 kb
Host smart-30921b70-f115-47ad-a0ec-3cfa9a75245c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36505
11358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3650511358
Directory /workspace/26.usbdev_disconnected/latest


Test location /workspace/coverage/default/26.usbdev_enable.2698867221
Short name T1498
Test name
Test status
Simulation time 35991261 ps
CPU time 0.72 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207260 kb
Host smart-35e37ba9-38c4-4ba3-928f-fdf63320139c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26988
67221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2698867221
Directory /workspace/26.usbdev_enable/latest


Test location /workspace/coverage/default/26.usbdev_endpoint_access.2106757543
Short name T2660
Test name
Test status
Simulation time 890468843 ps
CPU time 2.32 seconds
Started Aug 05 05:37:14 PM PDT 24
Finished Aug 05 05:37:17 PM PDT 24
Peak memory 207568 kb
Host smart-48da1b7a-8935-4525-ac47-a136517a581e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21067
57543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2106757543
Directory /workspace/26.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/26.usbdev_endpoint_types.1538546963
Short name T453
Test name
Test status
Simulation time 146906223 ps
CPU time 0.83 seconds
Started Aug 05 05:37:27 PM PDT 24
Finished Aug 05 05:37:28 PM PDT 24
Peak memory 207316 kb
Host smart-ca76712d-349e-4076-a6fb-0d25bf1360f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1538546963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.1538546963
Directory /workspace/26.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/26.usbdev_fifo_rst.2257461397
Short name T3002
Test name
Test status
Simulation time 292950042 ps
CPU time 1.98 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:14 PM PDT 24
Peak memory 207372 kb
Host smart-c08965e2-cfaa-4bf0-b308-0f6ed91e3b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22574
61397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2257461397
Directory /workspace/26.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/26.usbdev_in_iso.125069751
Short name T2788
Test name
Test status
Simulation time 198230747 ps
CPU time 1.02 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207604 kb
Host smart-8c34d1e6-ea44-4807-a645-399b51a70951
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=125069751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.125069751
Directory /workspace/26.usbdev_in_iso/latest


Test location /workspace/coverage/default/26.usbdev_in_stall.2369444837
Short name T2188
Test name
Test status
Simulation time 154399536 ps
CPU time 0.86 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 207312 kb
Host smart-f31135f5-b54c-43ed-887a-3cd4f96d6d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23694
44837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2369444837
Directory /workspace/26.usbdev_in_stall/latest


Test location /workspace/coverage/default/26.usbdev_in_trans.1006680308
Short name T1860
Test name
Test status
Simulation time 309713831 ps
CPU time 1.18 seconds
Started Aug 05 05:37:29 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 207268 kb
Host smart-79833489-bb71-409a-a479-ca4d0dc838ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10066
80308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1006680308
Directory /workspace/26.usbdev_in_trans/latest


Test location /workspace/coverage/default/26.usbdev_invalid_sync.2753921962
Short name T2821
Test name
Test status
Simulation time 5026242870 ps
CPU time 146.09 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 215780 kb
Host smart-a3f1584d-6f4e-4e24-8f54-e77665d74323
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2753921962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.2753921962
Directory /workspace/26.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/26.usbdev_iso_retraction.3213960757
Short name T1480
Test name
Test status
Simulation time 11113718667 ps
CPU time 134.38 seconds
Started Aug 05 05:37:13 PM PDT 24
Finished Aug 05 05:39:28 PM PDT 24
Peak memory 207652 kb
Host smart-61ebbe9f-dbea-47a1-ae0f-56ef22b3dcf2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3213960757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.3213960757
Directory /workspace/26.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/26.usbdev_link_in_err.408650843
Short name T2908
Test name
Test status
Simulation time 266156695 ps
CPU time 1.04 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207364 kb
Host smart-3c7b3278-2e29-4ec3-9b5e-dbbed5607f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40865
0843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.408650843
Directory /workspace/26.usbdev_link_in_err/latest


Test location /workspace/coverage/default/26.usbdev_link_resume.140205378
Short name T1514
Test name
Test status
Simulation time 10598612507 ps
CPU time 12.32 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:24 PM PDT 24
Peak memory 215780 kb
Host smart-c60416d9-cd9f-4429-9ec3-62941472a15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14020
5378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.140205378
Directory /workspace/26.usbdev_link_resume/latest


Test location /workspace/coverage/default/26.usbdev_link_suspend.2522359084
Short name T937
Test name
Test status
Simulation time 8583887693 ps
CPU time 10.69 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:22 PM PDT 24
Peak memory 207512 kb
Host smart-bc39f255-9aba-4395-b841-1c68b424a12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
59084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2522359084
Directory /workspace/26.usbdev_link_suspend/latest


Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.2311798484
Short name T1887
Test name
Test status
Simulation time 4025373338 ps
CPU time 31.07 seconds
Started Aug 05 05:37:34 PM PDT 24
Finished Aug 05 05:38:06 PM PDT 24
Peak memory 218248 kb
Host smart-effbcabf-0476-488a-9511-571fa53582a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23117
98484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.2311798484
Directory /workspace/26.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2750663751
Short name T1033
Test name
Test status
Simulation time 2714409843 ps
CPU time 19.98 seconds
Started Aug 05 05:37:27 PM PDT 24
Finished Aug 05 05:37:47 PM PDT 24
Peak memory 207692 kb
Host smart-2530879c-ff82-4b5f-81dc-344c4d4daa1f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2750663751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2750663751
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3926359096
Short name T2479
Test name
Test status
Simulation time 283315791 ps
CPU time 1.04 seconds
Started Aug 05 05:37:24 PM PDT 24
Finished Aug 05 05:37:25 PM PDT 24
Peak memory 207352 kb
Host smart-112f9439-d950-432a-9df9-b946fd577a78
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3926359096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3926359096
Directory /workspace/26.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3638322395
Short name T1767
Test name
Test status
Simulation time 262553109 ps
CPU time 1.11 seconds
Started Aug 05 05:37:27 PM PDT 24
Finished Aug 05 05:37:28 PM PDT 24
Peak memory 207296 kb
Host smart-51ec27e0-fd7a-4c2d-98e6-4ade405668d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36383
22395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3638322395
Directory /workspace/26.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.952345616
Short name T792
Test name
Test status
Simulation time 3658657027 ps
CPU time 37.42 seconds
Started Aug 05 05:37:31 PM PDT 24
Finished Aug 05 05:38:09 PM PDT 24
Peak memory 217452 kb
Host smart-dd5aba73-58fa-41d0-85a8-2150cc623634
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=952345616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.952345616
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.4118445807
Short name T1438
Test name
Test status
Simulation time 151336960 ps
CPU time 0.82 seconds
Started Aug 05 05:37:31 PM PDT 24
Finished Aug 05 05:37:32 PM PDT 24
Peak memory 207352 kb
Host smart-81767e7b-bc3f-4178-af33-68879fec9c13
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4118445807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.4118445807
Directory /workspace/26.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2918884529
Short name T1675
Test name
Test status
Simulation time 148666143 ps
CPU time 0.83 seconds
Started Aug 05 05:37:11 PM PDT 24
Finished Aug 05 05:37:12 PM PDT 24
Peak memory 207428 kb
Host smart-0f11daeb-5a8d-47bf-b667-fb5228e8cbff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29188
84529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2918884529
Directory /workspace/26.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/26.usbdev_nak_trans.2610109482
Short name T143
Test name
Test status
Simulation time 293153747 ps
CPU time 1.12 seconds
Started Aug 05 05:37:12 PM PDT 24
Finished Aug 05 05:37:13 PM PDT 24
Peak memory 207348 kb
Host smart-98fb455d-e807-44b0-a2e7-17b7f702196b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26101
09482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2610109482
Directory /workspace/26.usbdev_nak_trans/latest


Test location /workspace/coverage/default/26.usbdev_out_iso.3606470149
Short name T1259
Test name
Test status
Simulation time 179376949 ps
CPU time 0.9 seconds
Started Aug 05 05:37:33 PM PDT 24
Finished Aug 05 05:37:34 PM PDT 24
Peak memory 207348 kb
Host smart-6b429853-44e5-408d-b752-6bd87f58868d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36064
70149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3606470149
Directory /workspace/26.usbdev_out_iso/latest


Test location /workspace/coverage/default/26.usbdev_out_stall.2514684705
Short name T553
Test name
Test status
Simulation time 182475930 ps
CPU time 0.89 seconds
Started Aug 05 05:37:20 PM PDT 24
Finished Aug 05 05:37:21 PM PDT 24
Peak memory 207368 kb
Host smart-5e1cee8f-1858-4187-aa9e-1d8ae0e36796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25146
84705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2514684705
Directory /workspace/26.usbdev_out_stall/latest


Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2320635228
Short name T925
Test name
Test status
Simulation time 173579403 ps
CPU time 0.9 seconds
Started Aug 05 05:37:20 PM PDT 24
Finished Aug 05 05:37:22 PM PDT 24
Peak memory 207372 kb
Host smart-367ce547-ba48-4da8-bc0a-20693e4d3f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23206
35228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2320635228
Directory /workspace/26.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2824460711
Short name T2846
Test name
Test status
Simulation time 170564942 ps
CPU time 0.86 seconds
Started Aug 05 05:37:36 PM PDT 24
Finished Aug 05 05:37:37 PM PDT 24
Peak memory 207408 kb
Host smart-dbb8b9af-116b-4ac6-b6bc-2cfa276654db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28244
60711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2824460711
Directory /workspace/26.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.2740588835
Short name T1320
Test name
Test status
Simulation time 242770022 ps
CPU time 1.05 seconds
Started Aug 05 05:37:18 PM PDT 24
Finished Aug 05 05:37:19 PM PDT 24
Peak memory 207356 kb
Host smart-bae24a67-12b7-47fa-8eed-71675f478156
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2740588835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.2740588835
Directory /workspace/26.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2066132852
Short name T2166
Test name
Test status
Simulation time 239643917 ps
CPU time 0.98 seconds
Started Aug 05 05:37:28 PM PDT 24
Finished Aug 05 05:37:29 PM PDT 24
Peak memory 207320 kb
Host smart-93c034c6-0337-4cc6-a4de-83753f346d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20661
32852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2066132852
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.4117881357
Short name T26
Test name
Test status
Simulation time 31089439 ps
CPU time 0.73 seconds
Started Aug 05 05:37:27 PM PDT 24
Finished Aug 05 05:37:28 PM PDT 24
Peak memory 207236 kb
Host smart-cb36ac15-4bf2-4352-9380-96956cbba95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41178
81357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.4117881357
Directory /workspace/26.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3211758263
Short name T276
Test name
Test status
Simulation time 7419728383 ps
CPU time 20.95 seconds
Started Aug 05 05:37:32 PM PDT 24
Finished Aug 05 05:37:53 PM PDT 24
Peak memory 215860 kb
Host smart-0353df3f-3361-4533-a4de-5326c9fa7611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32117
58263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3211758263
Directory /workspace/26.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/26.usbdev_pkt_received.1713958101
Short name T2475
Test name
Test status
Simulation time 195928711 ps
CPU time 0.99 seconds
Started Aug 05 05:37:35 PM PDT 24
Finished Aug 05 05:37:36 PM PDT 24
Peak memory 207376 kb
Host smart-eed031f0-fcb4-48bb-9093-a60b0838b8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17139
58101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1713958101
Directory /workspace/26.usbdev_pkt_received/latest


Test location /workspace/coverage/default/26.usbdev_pkt_sent.1256627465
Short name T493
Test name
Test status
Simulation time 224301792 ps
CPU time 0.99 seconds
Started Aug 05 05:37:24 PM PDT 24
Finished Aug 05 05:37:25 PM PDT 24
Peak memory 207272 kb
Host smart-4b134105-243d-4248-a251-07ca85c812e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12566
27465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1256627465
Directory /workspace/26.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1046552368
Short name T2863
Test name
Test status
Simulation time 210633047 ps
CPU time 1.05 seconds
Started Aug 05 05:37:23 PM PDT 24
Finished Aug 05 05:37:24 PM PDT 24
Peak memory 207364 kb
Host smart-8d9ffa87-1d99-4181-af21-9600dce2841d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10465
52368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1046552368
Directory /workspace/26.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.643767009
Short name T2939
Test name
Test status
Simulation time 142974561 ps
CPU time 0.8 seconds
Started Aug 05 05:37:26 PM PDT 24
Finished Aug 05 05:37:27 PM PDT 24
Peak memory 207396 kb
Host smart-59c9bb3f-83a8-4863-ae28-572dd01667a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64376
7009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.643767009
Directory /workspace/26.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1821378602
Short name T1005
Test name
Test status
Simulation time 146481832 ps
CPU time 0.8 seconds
Started Aug 05 05:37:16 PM PDT 24
Finished Aug 05 05:37:17 PM PDT 24
Peak memory 207364 kb
Host smart-b524ad12-1ee6-4860-9095-76326c3c223b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18213
78602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1821378602
Directory /workspace/26.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/26.usbdev_rx_full.1418391736
Short name T1009
Test name
Test status
Simulation time 320449608 ps
CPU time 1.25 seconds
Started Aug 05 05:37:33 PM PDT 24
Finished Aug 05 05:37:34 PM PDT 24
Peak memory 207320 kb
Host smart-c42e2793-dc2d-4f06-a217-21d31c6b1b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14183
91736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.1418391736
Directory /workspace/26.usbdev_rx_full/latest


Test location /workspace/coverage/default/26.usbdev_setup_stage.1217362317
Short name T1162
Test name
Test status
Simulation time 176721856 ps
CPU time 0.84 seconds
Started Aug 05 05:37:15 PM PDT 24
Finished Aug 05 05:37:16 PM PDT 24
Peak memory 207224 kb
Host smart-78517fec-3f0c-4450-b2ec-d4c840442acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12173
62317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1217362317
Directory /workspace/26.usbdev_setup_stage/latest


Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2340688643
Short name T1487
Test name
Test status
Simulation time 176164291 ps
CPU time 0.86 seconds
Started Aug 05 05:37:26 PM PDT 24
Finished Aug 05 05:37:27 PM PDT 24
Peak memory 207404 kb
Host smart-77517d6e-38d4-4293-b56d-3e19e481d1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23406
88643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2340688643
Directory /workspace/26.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/26.usbdev_smoke.1200235597
Short name T808
Test name
Test status
Simulation time 200940391 ps
CPU time 0.97 seconds
Started Aug 05 05:37:22 PM PDT 24
Finished Aug 05 05:37:23 PM PDT 24
Peak memory 207336 kb
Host smart-076565fb-0efc-4b38-80e3-45bf4f0570fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12002
35597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1200235597
Directory /workspace/26.usbdev_smoke/latest


Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.4115846999
Short name T1679
Test name
Test status
Simulation time 3143943605 ps
CPU time 25.29 seconds
Started Aug 05 05:37:29 PM PDT 24
Finished Aug 05 05:37:55 PM PDT 24
Peak memory 217504 kb
Host smart-d18fc746-a64d-4aa7-b3ba-fa3edbefe1da
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4115846999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.4115846999
Directory /workspace/26.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1994508668
Short name T1280
Test name
Test status
Simulation time 187112937 ps
CPU time 0.92 seconds
Started Aug 05 05:37:29 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 207356 kb
Host smart-8864bc33-4f80-4f58-8799-d00f9fa85559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19945
08668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1994508668
Directory /workspace/26.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/26.usbdev_stall_trans.2393821623
Short name T2576
Test name
Test status
Simulation time 183215753 ps
CPU time 0.87 seconds
Started Aug 05 05:37:21 PM PDT 24
Finished Aug 05 05:37:22 PM PDT 24
Peak memory 207312 kb
Host smart-facaf9f7-696d-4d10-9029-7b399dccc77e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23938
21623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2393821623
Directory /workspace/26.usbdev_stall_trans/latest


Test location /workspace/coverage/default/26.usbdev_stream_len_max.788550852
Short name T627
Test name
Test status
Simulation time 1086656776 ps
CPU time 2.5 seconds
Started Aug 05 05:37:29 PM PDT 24
Finished Aug 05 05:37:32 PM PDT 24
Peak memory 207756 kb
Host smart-f7b34c33-305c-4c93-ba58-eaee6bfc9d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78855
0852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.788550852
Directory /workspace/26.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/26.usbdev_streaming_out.852542781
Short name T1520
Test name
Test status
Simulation time 1867185217 ps
CPU time 15.02 seconds
Started Aug 05 05:37:27 PM PDT 24
Finished Aug 05 05:37:43 PM PDT 24
Peak memory 223872 kb
Host smart-662ecb97-9b75-49a2-9c76-3ae8a81eb070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85254
2781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.852542781
Directory /workspace/26.usbdev_streaming_out/latest


Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.3275996749
Short name T3071
Test name
Test status
Simulation time 7695157934 ps
CPU time 52.67 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 207712 kb
Host smart-2aeb4916-27bf-420e-a1e7-430f260f45b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275996749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.3275996749
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/27.usbdev_alert_test.2057238408
Short name T2295
Test name
Test status
Simulation time 68328092 ps
CPU time 0.69 seconds
Started Aug 05 05:37:35 PM PDT 24
Finished Aug 05 05:37:36 PM PDT 24
Peak memory 207500 kb
Host smart-496b44bc-2f9b-44e4-86be-d1691c40c05c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2057238408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2057238408
Directory /workspace/27.usbdev_alert_test/latest


Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.2500989487
Short name T1548
Test name
Test status
Simulation time 6339209714 ps
CPU time 9.47 seconds
Started Aug 05 05:37:22 PM PDT 24
Finished Aug 05 05:37:32 PM PDT 24
Peak memory 215924 kb
Host smart-68a81735-fc62-4b02-bee2-59968b8b8d56
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500989487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.2500989487
Directory /workspace/27.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.3766229825
Short name T3017
Test name
Test status
Simulation time 15836946686 ps
CPU time 18.47 seconds
Started Aug 05 05:37:25 PM PDT 24
Finished Aug 05 05:37:43 PM PDT 24
Peak memory 215860 kb
Host smart-2e9bf1c0-2f62-4f25-b8c3-d8413fd355db
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766229825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.3766229825
Directory /workspace/27.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3891307025
Short name T595
Test name
Test status
Simulation time 28820417989 ps
CPU time 33.83 seconds
Started Aug 05 05:37:34 PM PDT 24
Finished Aug 05 05:38:08 PM PDT 24
Peak memory 207652 kb
Host smart-51acd832-4503-4c30-96ac-2ae963397ee7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891307025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.3891307025
Directory /workspace/27.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/27.usbdev_av_buffer.1969771487
Short name T1881
Test name
Test status
Simulation time 157666990 ps
CPU time 0.85 seconds
Started Aug 05 05:37:32 PM PDT 24
Finished Aug 05 05:37:33 PM PDT 24
Peak memory 207340 kb
Host smart-6e161a7f-ee2e-452b-a6cb-9052c0c9fd08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19697
71487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1969771487
Directory /workspace/27.usbdev_av_buffer/latest


Test location /workspace/coverage/default/27.usbdev_bitstuff_err.761191736
Short name T1439
Test name
Test status
Simulation time 147157204 ps
CPU time 0.86 seconds
Started Aug 05 05:37:33 PM PDT 24
Finished Aug 05 05:37:34 PM PDT 24
Peak memory 207332 kb
Host smart-6e1c54b3-11ad-4d71-85f8-11afd2dac0ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76119
1736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.761191736
Directory /workspace/27.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2677165147
Short name T1388
Test name
Test status
Simulation time 201169848 ps
CPU time 0.96 seconds
Started Aug 05 05:37:27 PM PDT 24
Finished Aug 05 05:37:28 PM PDT 24
Peak memory 207296 kb
Host smart-68763dc6-c68a-4b56-97f8-416944f9d9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26771
65147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2677165147
Directory /workspace/27.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.838266673
Short name T981
Test name
Test status
Simulation time 1136079997 ps
CPU time 2.85 seconds
Started Aug 05 05:37:18 PM PDT 24
Finished Aug 05 05:37:21 PM PDT 24
Peak memory 207580 kb
Host smart-33b4dfd9-2da2-44df-87a0-6aa382584118
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=838266673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.838266673
Directory /workspace/27.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/27.usbdev_device_address.2570370664
Short name T2571
Test name
Test status
Simulation time 55442457686 ps
CPU time 88.32 seconds
Started Aug 05 05:37:24 PM PDT 24
Finished Aug 05 05:38:53 PM PDT 24
Peak memory 206936 kb
Host smart-b81da993-855f-44d2-a750-5ff8efac3245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25703
70664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2570370664
Directory /workspace/27.usbdev_device_address/latest


Test location /workspace/coverage/default/27.usbdev_device_timeout.3088687515
Short name T973
Test name
Test status
Simulation time 1269551836 ps
CPU time 31.13 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:38:02 PM PDT 24
Peak memory 207568 kb
Host smart-8c518b4b-ed3b-46b0-8190-3bc4ab0ff16d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088687515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.3088687515
Directory /workspace/27.usbdev_device_timeout/latest


Test location /workspace/coverage/default/27.usbdev_disable_endpoint.528525578
Short name T1135
Test name
Test status
Simulation time 808219116 ps
CPU time 1.99 seconds
Started Aug 05 05:37:26 PM PDT 24
Finished Aug 05 05:37:29 PM PDT 24
Peak memory 207352 kb
Host smart-f099eeb2-bd3b-445f-970a-b548e9c1b506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52852
5578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.528525578
Directory /workspace/27.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/27.usbdev_disconnected.643367398
Short name T1361
Test name
Test status
Simulation time 148546936 ps
CPU time 0.84 seconds
Started Aug 05 05:37:29 PM PDT 24
Finished Aug 05 05:37:30 PM PDT 24
Peak memory 207316 kb
Host smart-c4c1ddfb-58f1-4544-bf1d-56f0086815ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64336
7398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.643367398
Directory /workspace/27.usbdev_disconnected/latest


Test location /workspace/coverage/default/27.usbdev_enable.602543047
Short name T712
Test name
Test status
Simulation time 78445261 ps
CPU time 0.69 seconds
Started Aug 05 05:37:24 PM PDT 24
Finished Aug 05 05:37:25 PM PDT 24
Peak memory 207288 kb
Host smart-6585401e-7646-4e77-a48b-73158bb6ac54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60254
3047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.602543047
Directory /workspace/27.usbdev_enable/latest


Test location /workspace/coverage/default/27.usbdev_endpoint_access.3130252543
Short name T961
Test name
Test status
Simulation time 1004725250 ps
CPU time 2.59 seconds
Started Aug 05 05:37:32 PM PDT 24
Finished Aug 05 05:37:34 PM PDT 24
Peak memory 207632 kb
Host smart-ec1dd7fa-8de7-4f21-9435-0bd9b938c277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31302
52543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3130252543
Directory /workspace/27.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/27.usbdev_endpoint_types.2295399258
Short name T421
Test name
Test status
Simulation time 278289690 ps
CPU time 1.14 seconds
Started Aug 05 05:37:21 PM PDT 24
Finished Aug 05 05:37:22 PM PDT 24
Peak memory 207352 kb
Host smart-13c910e1-33dd-4713-b559-21fb94d2856f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2295399258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.2295399258
Directory /workspace/27.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/27.usbdev_fifo_rst.859071751
Short name T2025
Test name
Test status
Simulation time 166623784 ps
CPU time 1.7 seconds
Started Aug 05 05:37:36 PM PDT 24
Finished Aug 05 05:37:38 PM PDT 24
Peak memory 207508 kb
Host smart-7fd76bcd-c6e3-40ce-8b45-d0390ae8a14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85907
1751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.859071751
Directory /workspace/27.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/27.usbdev_in_iso.2397788372
Short name T2931
Test name
Test status
Simulation time 220785683 ps
CPU time 1.17 seconds
Started Aug 05 05:37:16 PM PDT 24
Finished Aug 05 05:37:17 PM PDT 24
Peak memory 215640 kb
Host smart-0f3a3dc8-1a1a-430e-bcdc-88ee87625fb7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2397788372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2397788372
Directory /workspace/27.usbdev_in_iso/latest


Test location /workspace/coverage/default/27.usbdev_in_stall.851508662
Short name T1382
Test name
Test status
Simulation time 151547868 ps
CPU time 0.83 seconds
Started Aug 05 05:37:20 PM PDT 24
Finished Aug 05 05:37:21 PM PDT 24
Peak memory 207352 kb
Host smart-f74c7ace-e777-4e57-a6d5-42572b9c9573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85150
8662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.851508662
Directory /workspace/27.usbdev_in_stall/latest


Test location /workspace/coverage/default/27.usbdev_in_trans.2446114421
Short name T1151
Test name
Test status
Simulation time 179366974 ps
CPU time 0.92 seconds
Started Aug 05 05:37:34 PM PDT 24
Finished Aug 05 05:37:36 PM PDT 24
Peak memory 207368 kb
Host smart-c284e950-8387-4652-9d2b-80d7c7aa89b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24461
14421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2446114421
Directory /workspace/27.usbdev_in_trans/latest


Test location /workspace/coverage/default/27.usbdev_invalid_sync.3788250593
Short name T2010
Test name
Test status
Simulation time 4699902192 ps
CPU time 37.83 seconds
Started Aug 05 05:37:26 PM PDT 24
Finished Aug 05 05:38:04 PM PDT 24
Peak memory 224012 kb
Host smart-f3e4ad91-9438-420d-adf5-f9a2bb0112ca
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3788250593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3788250593
Directory /workspace/27.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/27.usbdev_iso_retraction.100218219
Short name T833
Test name
Test status
Simulation time 12260268602 ps
CPU time 144.92 seconds
Started Aug 05 05:37:32 PM PDT 24
Finished Aug 05 05:39:57 PM PDT 24
Peak memory 207612 kb
Host smart-c9140870-f107-48aa-a5c3-8aab95be2bd1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=100218219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.100218219
Directory /workspace/27.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/27.usbdev_link_in_err.3129295983
Short name T3012
Test name
Test status
Simulation time 178641946 ps
CPU time 0.94 seconds
Started Aug 05 05:37:28 PM PDT 24
Finished Aug 05 05:37:29 PM PDT 24
Peak memory 207388 kb
Host smart-5521b87e-6e8f-46aa-8c45-381ecb2b4a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31292
95983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3129295983
Directory /workspace/27.usbdev_link_in_err/latest


Test location /workspace/coverage/default/27.usbdev_link_resume.2394658212
Short name T2245
Test name
Test status
Simulation time 32584787610 ps
CPU time 51.58 seconds
Started Aug 05 05:37:33 PM PDT 24
Finished Aug 05 05:38:25 PM PDT 24
Peak memory 207688 kb
Host smart-a0a17639-99ff-4819-8be1-f20845332976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23946
58212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2394658212
Directory /workspace/27.usbdev_link_resume/latest


Test location /workspace/coverage/default/27.usbdev_link_suspend.1959031216
Short name T1508
Test name
Test status
Simulation time 5727493192 ps
CPU time 8.98 seconds
Started Aug 05 05:37:24 PM PDT 24
Finished Aug 05 05:37:33 PM PDT 24
Peak memory 215840 kb
Host smart-88fe7808-445a-4881-b0dc-0631d0a9a7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19590
31216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1959031216
Directory /workspace/27.usbdev_link_suspend/latest


Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.1538594977
Short name T2504
Test name
Test status
Simulation time 3385751425 ps
CPU time 92.56 seconds
Started Aug 05 05:37:24 PM PDT 24
Finished Aug 05 05:38:57 PM PDT 24
Peak memory 223460 kb
Host smart-7320fdac-a6d2-4234-ab86-e6d91e8806a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15385
94977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.1538594977
Directory /workspace/27.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.1788600694
Short name T542
Test name
Test status
Simulation time 2579330492 ps
CPU time 74.93 seconds
Started Aug 05 05:37:20 PM PDT 24
Finished Aug 05 05:38:35 PM PDT 24
Peak memory 217388 kb
Host smart-47bcf3a9-6204-41a3-9b48-27f327cb45f2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1788600694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.1788600694
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.3913429212
Short name T1369
Test name
Test status
Simulation time 233131463 ps
CPU time 0.99 seconds
Started Aug 05 05:37:17 PM PDT 24
Finished Aug 05 05:37:18 PM PDT 24
Peak memory 207256 kb
Host smart-f8737549-6643-4937-9cdb-a80b6e4ee12c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3913429212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.3913429212
Directory /workspace/27.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.972926985
Short name T814
Test name
Test status
Simulation time 218938082 ps
CPU time 1.04 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 207320 kb
Host smart-23a4fbfa-344d-4681-bb82-8b2cd1352772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97292
6985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.972926985
Directory /workspace/27.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.555622529
Short name T510
Test name
Test status
Simulation time 1733744147 ps
CPU time 13.45 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:37:43 PM PDT 24
Peak memory 217192 kb
Host smart-01fcaf72-ab8f-4a22-858d-26901c73c2d4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=555622529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.555622529
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.560717121
Short name T3070
Test name
Test status
Simulation time 153682307 ps
CPU time 0.82 seconds
Started Aug 05 05:37:33 PM PDT 24
Finished Aug 05 05:37:34 PM PDT 24
Peak memory 207332 kb
Host smart-986a08da-dfb0-467b-b4c1-859e15618a2a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=560717121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.560717121
Directory /workspace/27.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.297969761
Short name T806
Test name
Test status
Simulation time 145282213 ps
CPU time 0.86 seconds
Started Aug 05 05:37:28 PM PDT 24
Finished Aug 05 05:37:29 PM PDT 24
Peak memory 207352 kb
Host smart-e6f3891d-1e5d-4b2c-a30b-2ef5ea9f263f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29796
9761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.297969761
Directory /workspace/27.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/27.usbdev_nak_trans.2752621928
Short name T1493
Test name
Test status
Simulation time 193691939 ps
CPU time 0.99 seconds
Started Aug 05 05:37:36 PM PDT 24
Finished Aug 05 05:37:37 PM PDT 24
Peak memory 207368 kb
Host smart-5ef1629e-cc17-41ec-88da-056ceb5dd4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27526
21928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2752621928
Directory /workspace/27.usbdev_nak_trans/latest


Test location /workspace/coverage/default/27.usbdev_out_iso.1909552531
Short name T2064
Test name
Test status
Simulation time 162451195 ps
CPU time 0.92 seconds
Started Aug 05 05:37:29 PM PDT 24
Finished Aug 05 05:37:30 PM PDT 24
Peak memory 207240 kb
Host smart-d38fe4f5-f12c-471d-84be-a031e2957bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19095
52531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1909552531
Directory /workspace/27.usbdev_out_iso/latest


Test location /workspace/coverage/default/27.usbdev_out_stall.909940153
Short name T1943
Test name
Test status
Simulation time 173323164 ps
CPU time 0.85 seconds
Started Aug 05 05:37:35 PM PDT 24
Finished Aug 05 05:37:36 PM PDT 24
Peak memory 207368 kb
Host smart-433f69eb-7484-45e7-a9cb-43713365cf6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90994
0153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.909940153
Directory /workspace/27.usbdev_out_stall/latest


Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3257198166
Short name T1220
Test name
Test status
Simulation time 175008944 ps
CPU time 0.94 seconds
Started Aug 05 05:37:35 PM PDT 24
Finished Aug 05 05:37:36 PM PDT 24
Peak memory 207380 kb
Host smart-b896be51-df25-4fbf-a7e8-013408a18684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32571
98166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3257198166
Directory /workspace/27.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3602922752
Short name T2215
Test name
Test status
Simulation time 145732749 ps
CPU time 0.85 seconds
Started Aug 05 05:37:29 PM PDT 24
Finished Aug 05 05:37:30 PM PDT 24
Peak memory 207356 kb
Host smart-2b5478c3-bd46-4100-94df-803ed9d7d2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36029
22752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3602922752
Directory /workspace/27.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3521512705
Short name T1072
Test name
Test status
Simulation time 200864728 ps
CPU time 1.02 seconds
Started Aug 05 05:37:31 PM PDT 24
Finished Aug 05 05:37:33 PM PDT 24
Peak memory 207368 kb
Host smart-598422bd-dbe6-4a6e-b434-d4e72804d5b9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3521512705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3521512705
Directory /workspace/27.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2697647213
Short name T199
Test name
Test status
Simulation time 147240044 ps
CPU time 0.89 seconds
Started Aug 05 05:37:34 PM PDT 24
Finished Aug 05 05:37:35 PM PDT 24
Peak memory 207348 kb
Host smart-a23c2083-ca63-4a4b-ba92-736c4c14fa1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26976
47213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2697647213
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3642556145
Short name T28
Test name
Test status
Simulation time 53656892 ps
CPU time 0.72 seconds
Started Aug 05 05:37:32 PM PDT 24
Finished Aug 05 05:37:33 PM PDT 24
Peak memory 207328 kb
Host smart-30d2d7f5-7d58-4051-9f35-b6d18259df49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36425
56145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3642556145
Directory /workspace/27.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3936213015
Short name T2047
Test name
Test status
Simulation time 9760571653 ps
CPU time 25.09 seconds
Started Aug 05 05:37:32 PM PDT 24
Finished Aug 05 05:37:58 PM PDT 24
Peak memory 224076 kb
Host smart-c39cfc13-d3e0-44e1-b8fd-e2832a6ad5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39362
13015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3936213015
Directory /workspace/27.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/27.usbdev_pkt_received.3324879525
Short name T3117
Test name
Test status
Simulation time 151596975 ps
CPU time 0.84 seconds
Started Aug 05 05:37:36 PM PDT 24
Finished Aug 05 05:37:37 PM PDT 24
Peak memory 207252 kb
Host smart-3faea9a6-1c81-47de-95eb-d430a407ed81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33248
79525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3324879525
Directory /workspace/27.usbdev_pkt_received/latest


Test location /workspace/coverage/default/27.usbdev_pkt_sent.3255666078
Short name T544
Test name
Test status
Simulation time 253118365 ps
CPU time 1.03 seconds
Started Aug 05 05:37:29 PM PDT 24
Finished Aug 05 05:37:30 PM PDT 24
Peak memory 207272 kb
Host smart-5a7403f0-1eb1-4b48-9e9d-7fb5a1ef8230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32556
66078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3255666078
Directory /workspace/27.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.94980902
Short name T2756
Test name
Test status
Simulation time 209989634 ps
CPU time 0.94 seconds
Started Aug 05 05:37:38 PM PDT 24
Finished Aug 05 05:37:39 PM PDT 24
Peak memory 207368 kb
Host smart-6d1574b7-1223-4977-9ce2-da0fb56d1cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94980
902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.94980902
Directory /workspace/27.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.2748537396
Short name T1729
Test name
Test status
Simulation time 215798460 ps
CPU time 0.96 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 207268 kb
Host smart-2271def2-eba2-4081-a40b-d10e764dd314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27485
37396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.2748537396
Directory /workspace/27.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1786093541
Short name T2007
Test name
Test status
Simulation time 189630136 ps
CPU time 0.86 seconds
Started Aug 05 05:37:31 PM PDT 24
Finished Aug 05 05:37:32 PM PDT 24
Peak memory 207368 kb
Host smart-311f8729-7c3a-4a8a-8301-5ba0de1fddfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17860
93541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1786093541
Directory /workspace/27.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/27.usbdev_rx_full.3683676399
Short name T2120
Test name
Test status
Simulation time 260910172 ps
CPU time 1.11 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 207296 kb
Host smart-bda67f3c-3493-4016-ade7-207a622b2570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36836
76399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.3683676399
Directory /workspace/27.usbdev_rx_full/latest


Test location /workspace/coverage/default/27.usbdev_setup_stage.3884915914
Short name T2263
Test name
Test status
Simulation time 208543072 ps
CPU time 0.9 seconds
Started Aug 05 05:37:34 PM PDT 24
Finished Aug 05 05:37:35 PM PDT 24
Peak memory 207308 kb
Host smart-8ebbdf52-a16e-4d3b-9e75-91a98cae18f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38849
15914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3884915914
Directory /workspace/27.usbdev_setup_stage/latest


Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.916025743
Short name T1983
Test name
Test status
Simulation time 156350858 ps
CPU time 0.87 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 207324 kb
Host smart-178028fb-5ff1-485a-a363-eaf6fb4dab17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91602
5743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.916025743
Directory /workspace/27.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/27.usbdev_smoke.855191786
Short name T2618
Test name
Test status
Simulation time 230302203 ps
CPU time 1.07 seconds
Started Aug 05 05:37:35 PM PDT 24
Finished Aug 05 05:37:36 PM PDT 24
Peak memory 207248 kb
Host smart-3e262861-7594-4b85-8f70-32ee3961b719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85519
1786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.855191786
Directory /workspace/27.usbdev_smoke/latest


Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.1051077113
Short name T2317
Test name
Test status
Simulation time 1782466035 ps
CPU time 14.48 seconds
Started Aug 05 05:37:28 PM PDT 24
Finished Aug 05 05:37:43 PM PDT 24
Peak memory 215760 kb
Host smart-2a9afbca-f800-4a43-aafe-60952ca71c2d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1051077113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.1051077113
Directory /workspace/27.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3935970932
Short name T2300
Test name
Test status
Simulation time 185552156 ps
CPU time 0.89 seconds
Started Aug 05 05:37:39 PM PDT 24
Finished Aug 05 05:37:40 PM PDT 24
Peak memory 207356 kb
Host smart-ac9a5966-4adf-4b29-a9f2-83a793e474af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39359
70932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3935970932
Directory /workspace/27.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/27.usbdev_stall_trans.102765590
Short name T3111
Test name
Test status
Simulation time 176808114 ps
CPU time 0.93 seconds
Started Aug 05 05:37:37 PM PDT 24
Finished Aug 05 05:37:38 PM PDT 24
Peak memory 207396 kb
Host smart-9365f455-77d8-46af-a8ed-041f5f1be7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10276
5590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.102765590
Directory /workspace/27.usbdev_stall_trans/latest


Test location /workspace/coverage/default/27.usbdev_stream_len_max.2230843410
Short name T2511
Test name
Test status
Simulation time 578341539 ps
CPU time 1.57 seconds
Started Aug 05 05:37:40 PM PDT 24
Finished Aug 05 05:37:42 PM PDT 24
Peak memory 207292 kb
Host smart-5e767ff0-37a4-477e-bd0d-09d035d0d656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22308
43410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.2230843410
Directory /workspace/27.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/27.usbdev_streaming_out.3672670265
Short name T1340
Test name
Test status
Simulation time 2530272745 ps
CPU time 19.89 seconds
Started Aug 05 05:37:35 PM PDT 24
Finished Aug 05 05:37:55 PM PDT 24
Peak memory 217468 kb
Host smart-1c2df423-227b-4bb4-b39c-a768228439eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36726
70265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.3672670265
Directory /workspace/27.usbdev_streaming_out/latest


Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.67713677
Short name T2054
Test name
Test status
Simulation time 1128782438 ps
CPU time 24.5 seconds
Started Aug 05 05:37:35 PM PDT 24
Finished Aug 05 05:37:59 PM PDT 24
Peak memory 207616 kb
Host smart-28fc2b44-b570-47b0-b27b-25460a159010
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67713677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_host_
handshake.67713677
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/28.usbdev_alert_test.3725867124
Short name T1756
Test name
Test status
Simulation time 54560331 ps
CPU time 0.69 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207572 kb
Host smart-9099e24f-2f36-41a9-b28d-e1a436ada54e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3725867124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.3725867124
Directory /workspace/28.usbdev_alert_test/latest


Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3722167639
Short name T1653
Test name
Test status
Simulation time 10050112884 ps
CPU time 13.31 seconds
Started Aug 05 05:37:26 PM PDT 24
Finished Aug 05 05:37:40 PM PDT 24
Peak memory 207604 kb
Host smart-abd70f32-26ef-4da8-b226-972d66686062
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722167639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.3722167639
Directory /workspace/28.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.3254386974
Short name T687
Test name
Test status
Simulation time 14675654351 ps
CPU time 17.14 seconds
Started Aug 05 05:37:36 PM PDT 24
Finished Aug 05 05:37:53 PM PDT 24
Peak memory 215808 kb
Host smart-0f426f23-281a-45e4-b5c4-f63613e2fb3d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254386974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3254386974
Directory /workspace/28.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.2126790919
Short name T2422
Test name
Test status
Simulation time 25262483307 ps
CPU time 26.99 seconds
Started Aug 05 05:37:29 PM PDT 24
Finished Aug 05 05:37:56 PM PDT 24
Peak memory 215832 kb
Host smart-a944a623-43df-4dae-85a4-dc9a12e000b3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126790919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.2126790919
Directory /workspace/28.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/28.usbdev_av_buffer.1599980695
Short name T1495
Test name
Test status
Simulation time 190512511 ps
CPU time 0.92 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 207416 kb
Host smart-f4da871b-906a-45ba-8f47-abdf0acb0d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15999
80695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1599980695
Directory /workspace/28.usbdev_av_buffer/latest


Test location /workspace/coverage/default/28.usbdev_bitstuff_err.2574595467
Short name T2945
Test name
Test status
Simulation time 158024690 ps
CPU time 0.91 seconds
Started Aug 05 05:37:35 PM PDT 24
Finished Aug 05 05:37:36 PM PDT 24
Peak memory 207280 kb
Host smart-72b17f35-3a4e-4661-b019-a29b70689429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25745
95467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.2574595467
Directory /workspace/28.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2811237997
Short name T2876
Test name
Test status
Simulation time 346563779 ps
CPU time 1.26 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:37:31 PM PDT 24
Peak memory 207380 kb
Host smart-6133b0eb-7e10-4185-b18e-aad74fbfceb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28112
37997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2811237997
Directory /workspace/28.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1552773776
Short name T1525
Test name
Test status
Simulation time 866625031 ps
CPU time 2.21 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:37:32 PM PDT 24
Peak memory 207616 kb
Host smart-15649fa2-5737-4a26-a941-01fc26e25e5b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1552773776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1552773776
Directory /workspace/28.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/28.usbdev_device_address.74474796
Short name T366
Test name
Test status
Simulation time 33640462815 ps
CPU time 61.06 seconds
Started Aug 05 05:37:40 PM PDT 24
Finished Aug 05 05:38:41 PM PDT 24
Peak memory 207616 kb
Host smart-69305ed6-2469-4c42-abd9-f141be9d14b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74474
796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.74474796
Directory /workspace/28.usbdev_device_address/latest


Test location /workspace/coverage/default/28.usbdev_device_timeout.1847282427
Short name T600
Test name
Test status
Simulation time 883245531 ps
CPU time 18.24 seconds
Started Aug 05 05:37:35 PM PDT 24
Finished Aug 05 05:37:54 PM PDT 24
Peak memory 207716 kb
Host smart-59678c24-e69b-4bc9-bc1a-a80c22215913
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847282427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.1847282427
Directory /workspace/28.usbdev_device_timeout/latest


Test location /workspace/coverage/default/28.usbdev_disable_endpoint.1034606059
Short name T2765
Test name
Test status
Simulation time 1419546960 ps
CPU time 2.54 seconds
Started Aug 05 05:37:30 PM PDT 24
Finished Aug 05 05:37:32 PM PDT 24
Peak memory 207216 kb
Host smart-f2689bee-4edb-41d9-b45a-113c3aac7a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10346
06059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.1034606059
Directory /workspace/28.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/28.usbdev_disconnected.1123720935
Short name T2781
Test name
Test status
Simulation time 145847088 ps
CPU time 0.87 seconds
Started Aug 05 05:37:41 PM PDT 24
Finished Aug 05 05:37:42 PM PDT 24
Peak memory 207272 kb
Host smart-074cb528-c374-4df5-8619-1a6855b6a598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11237
20935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1123720935
Directory /workspace/28.usbdev_disconnected/latest


Test location /workspace/coverage/default/28.usbdev_enable.39105885
Short name T2338
Test name
Test status
Simulation time 48270833 ps
CPU time 0.71 seconds
Started Aug 05 05:37:34 PM PDT 24
Finished Aug 05 05:37:34 PM PDT 24
Peak memory 207232 kb
Host smart-83a4cfb0-3c01-48ed-92df-4e9e8bef8f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39105
885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.39105885
Directory /workspace/28.usbdev_enable/latest


Test location /workspace/coverage/default/28.usbdev_endpoint_access.4114003508
Short name T1646
Test name
Test status
Simulation time 910447236 ps
CPU time 2.53 seconds
Started Aug 05 05:37:33 PM PDT 24
Finished Aug 05 05:37:36 PM PDT 24
Peak memory 207600 kb
Host smart-21a7d2ce-6f51-448f-9ac7-60470b5e87a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41140
03508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.4114003508
Directory /workspace/28.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/28.usbdev_endpoint_types.688296874
Short name T1376
Test name
Test status
Simulation time 280898014 ps
CPU time 1.1 seconds
Started Aug 05 05:37:37 PM PDT 24
Finished Aug 05 05:37:38 PM PDT 24
Peak memory 207316 kb
Host smart-7441e9aa-4d59-467e-b3be-931bb37abe2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=688296874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.688296874
Directory /workspace/28.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/28.usbdev_fifo_rst.667280376
Short name T1143
Test name
Test status
Simulation time 209867105 ps
CPU time 1.36 seconds
Started Aug 05 05:37:37 PM PDT 24
Finished Aug 05 05:37:38 PM PDT 24
Peak memory 207520 kb
Host smart-f27396a2-d56a-4b01-9e94-4ec912acd7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66728
0376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.667280376
Directory /workspace/28.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/28.usbdev_in_iso.156205546
Short name T880
Test name
Test status
Simulation time 220146727 ps
CPU time 1.12 seconds
Started Aug 05 05:37:31 PM PDT 24
Finished Aug 05 05:37:33 PM PDT 24
Peak memory 215804 kb
Host smart-1b726fcb-a362-459c-af6f-5e149e36d638
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=156205546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.156205546
Directory /workspace/28.usbdev_in_iso/latest


Test location /workspace/coverage/default/28.usbdev_in_stall.2649850564
Short name T930
Test name
Test status
Simulation time 201402549 ps
CPU time 0.89 seconds
Started Aug 05 05:37:31 PM PDT 24
Finished Aug 05 05:37:32 PM PDT 24
Peak memory 207348 kb
Host smart-205a5a37-5211-4398-8e10-dcf6ad15bda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26498
50564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2649850564
Directory /workspace/28.usbdev_in_stall/latest


Test location /workspace/coverage/default/28.usbdev_in_trans.2279803370
Short name T2490
Test name
Test status
Simulation time 204378711 ps
CPU time 0.96 seconds
Started Aug 05 05:37:25 PM PDT 24
Finished Aug 05 05:37:26 PM PDT 24
Peak memory 207288 kb
Host smart-67ea2061-00c1-49d9-bf01-25e54a57b472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22798
03370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2279803370
Directory /workspace/28.usbdev_in_trans/latest


Test location /workspace/coverage/default/28.usbdev_invalid_sync.383851617
Short name T1242
Test name
Test status
Simulation time 3107644437 ps
CPU time 31.55 seconds
Started Aug 05 05:37:26 PM PDT 24
Finished Aug 05 05:37:58 PM PDT 24
Peak memory 224080 kb
Host smart-cdb999e4-2d22-4aec-b04b-023f952ae2ed
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=383851617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.383851617
Directory /workspace/28.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/28.usbdev_iso_retraction.1320536353
Short name T2822
Test name
Test status
Simulation time 11874006094 ps
CPU time 76.73 seconds
Started Aug 05 05:37:36 PM PDT 24
Finished Aug 05 05:38:53 PM PDT 24
Peak memory 207520 kb
Host smart-c4988d8b-a9c3-4665-abc6-7d19ca43abad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1320536353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.1320536353
Directory /workspace/28.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/28.usbdev_link_in_err.4238889642
Short name T2124
Test name
Test status
Simulation time 155756563 ps
CPU time 0.84 seconds
Started Aug 05 05:37:29 PM PDT 24
Finished Aug 05 05:37:30 PM PDT 24
Peak memory 207228 kb
Host smart-c12aecd4-cd00-453c-bfed-f97fae8bbf99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42388
89642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.4238889642
Directory /workspace/28.usbdev_link_in_err/latest


Test location /workspace/coverage/default/28.usbdev_link_resume.1360519951
Short name T991
Test name
Test status
Simulation time 12218105579 ps
CPU time 16.24 seconds
Started Aug 05 05:37:35 PM PDT 24
Finished Aug 05 05:37:51 PM PDT 24
Peak memory 207644 kb
Host smart-9dd70607-89fa-42ca-b397-d4f405889bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13605
19951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1360519951
Directory /workspace/28.usbdev_link_resume/latest


Test location /workspace/coverage/default/28.usbdev_link_suspend.2010363722
Short name T575
Test name
Test status
Simulation time 9866345089 ps
CPU time 12.83 seconds
Started Aug 05 05:37:43 PM PDT 24
Finished Aug 05 05:37:56 PM PDT 24
Peak memory 207628 kb
Host smart-71160c69-949b-45ee-b163-f2294280ccf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20103
63722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2010363722
Directory /workspace/28.usbdev_link_suspend/latest


Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.3367356545
Short name T2441
Test name
Test status
Simulation time 3500742612 ps
CPU time 100.23 seconds
Started Aug 05 05:37:41 PM PDT 24
Finished Aug 05 05:39:21 PM PDT 24
Peak memory 218396 kb
Host smart-fa2e6ac5-68bd-4214-a61b-d8f00c6dc487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33673
56545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.3367356545
Directory /workspace/28.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.573571921
Short name T570
Test name
Test status
Simulation time 2708553037 ps
CPU time 26.52 seconds
Started Aug 05 05:37:34 PM PDT 24
Finished Aug 05 05:38:01 PM PDT 24
Peak memory 217596 kb
Host smart-240df610-522c-4acb-957d-5dc33bebfc5f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=573571921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.573571921
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1896311853
Short name T1104
Test name
Test status
Simulation time 239969002 ps
CPU time 1.01 seconds
Started Aug 05 05:37:34 PM PDT 24
Finished Aug 05 05:37:35 PM PDT 24
Peak memory 207360 kb
Host smart-f5641447-fac5-42d9-b8f6-e937817e8c62
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1896311853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1896311853
Directory /workspace/28.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1959850529
Short name T500
Test name
Test status
Simulation time 194141514 ps
CPU time 0.97 seconds
Started Aug 05 05:37:37 PM PDT 24
Finished Aug 05 05:37:38 PM PDT 24
Peak memory 207404 kb
Host smart-e8330508-ac59-4d08-a17f-3a2839e0aa88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19598
50529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1959850529
Directory /workspace/28.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.2223087435
Short name T847
Test name
Test status
Simulation time 2092554704 ps
CPU time 20.98 seconds
Started Aug 05 05:37:29 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 215704 kb
Host smart-9a8a6328-1d76-4efc-8d63-eaee8b31da9e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2223087435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.2223087435
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1924672244
Short name T1203
Test name
Test status
Simulation time 167274667 ps
CPU time 0.88 seconds
Started Aug 05 05:37:36 PM PDT 24
Finished Aug 05 05:37:37 PM PDT 24
Peak memory 207380 kb
Host smart-192b3bba-41a2-4707-99ed-8639c4ee8b27
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1924672244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1924672244
Directory /workspace/28.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.498962167
Short name T1521
Test name
Test status
Simulation time 153714733 ps
CPU time 0.8 seconds
Started Aug 05 05:37:27 PM PDT 24
Finished Aug 05 05:37:28 PM PDT 24
Peak memory 207380 kb
Host smart-4f39cadc-30af-459f-b037-c824cc2ad694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49896
2167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.498962167
Directory /workspace/28.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/28.usbdev_nak_trans.607989139
Short name T1862
Test name
Test status
Simulation time 181262756 ps
CPU time 0.89 seconds
Started Aug 05 05:37:34 PM PDT 24
Finished Aug 05 05:37:35 PM PDT 24
Peak memory 207396 kb
Host smart-64425b12-bc53-4f3b-b4ec-d44856e4fff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60798
9139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.607989139
Directory /workspace/28.usbdev_nak_trans/latest


Test location /workspace/coverage/default/28.usbdev_out_iso.1672632682
Short name T1821
Test name
Test status
Simulation time 204100866 ps
CPU time 0.93 seconds
Started Aug 05 05:37:26 PM PDT 24
Finished Aug 05 05:37:28 PM PDT 24
Peak memory 207348 kb
Host smart-d64cdc5f-7722-4abe-8228-2fd69661ab08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16726
32682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1672632682
Directory /workspace/28.usbdev_out_iso/latest


Test location /workspace/coverage/default/28.usbdev_out_stall.3869870407
Short name T2913
Test name
Test status
Simulation time 181150967 ps
CPU time 0.92 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:37:47 PM PDT 24
Peak memory 207416 kb
Host smart-76140cdf-a564-4cab-9503-f227e8bc045b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38698
70407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3869870407
Directory /workspace/28.usbdev_out_stall/latest


Test location /workspace/coverage/default/28.usbdev_out_trans_nak.295018971
Short name T2580
Test name
Test status
Simulation time 151758202 ps
CPU time 0.88 seconds
Started Aug 05 05:37:51 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207376 kb
Host smart-0b10bc5f-0ee4-4d13-aaec-d8c9f7341a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29501
8971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.295018971
Directory /workspace/28.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3530811859
Short name T2359
Test name
Test status
Simulation time 169959343 ps
CPU time 0.87 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207244 kb
Host smart-5d625081-a794-48f9-90fb-c0ec09fe3e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35308
11859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3530811859
Directory /workspace/28.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1521412129
Short name T2395
Test name
Test status
Simulation time 226261887 ps
CPU time 1.03 seconds
Started Aug 05 05:37:49 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 207352 kb
Host smart-0d6bf43a-a256-4ca8-aadf-b3736e77e622
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1521412129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1521412129
Directory /workspace/28.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1562571937
Short name T2874
Test name
Test status
Simulation time 150509574 ps
CPU time 0.9 seconds
Started Aug 05 05:37:51 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207256 kb
Host smart-27e375dc-9d62-4989-b67c-3427c74d1edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15625
71937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1562571937
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2264823193
Short name T1068
Test name
Test status
Simulation time 81131778 ps
CPU time 0.71 seconds
Started Aug 05 05:37:44 PM PDT 24
Finished Aug 05 05:37:45 PM PDT 24
Peak memory 207260 kb
Host smart-354fea6c-4627-4869-a4db-b036a65321a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22648
23193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2264823193
Directory /workspace/28.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/28.usbdev_pkt_buffer.729362463
Short name T3123
Test name
Test status
Simulation time 20061143483 ps
CPU time 47.62 seconds
Started Aug 05 05:37:49 PM PDT 24
Finished Aug 05 05:38:36 PM PDT 24
Peak memory 220212 kb
Host smart-ed220841-03b0-4fa9-9bd3-cc4bd166d1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72936
2463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.729362463
Directory /workspace/28.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/28.usbdev_pkt_received.1196178356
Short name T1310
Test name
Test status
Simulation time 193187989 ps
CPU time 0.91 seconds
Started Aug 05 05:37:44 PM PDT 24
Finished Aug 05 05:37:45 PM PDT 24
Peak memory 207400 kb
Host smart-d442e493-554d-4666-a3d7-f2f05f9fd903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11961
78356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1196178356
Directory /workspace/28.usbdev_pkt_received/latest


Test location /workspace/coverage/default/28.usbdev_pkt_sent.2247259864
Short name T2541
Test name
Test status
Simulation time 185640351 ps
CPU time 0.92 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:37:54 PM PDT 24
Peak memory 207352 kb
Host smart-024b6b92-de2e-4409-83b7-6c8c597515b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22472
59864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2247259864
Directory /workspace/28.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.4121583806
Short name T2493
Test name
Test status
Simulation time 196866049 ps
CPU time 0.93 seconds
Started Aug 05 05:37:50 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207336 kb
Host smart-af9e24f6-f215-49ee-b87d-1f4b9d4b2eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41215
83806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.4121583806
Directory /workspace/28.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.2473409918
Short name T2465
Test name
Test status
Simulation time 217969676 ps
CPU time 0.97 seconds
Started Aug 05 05:37:49 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 207604 kb
Host smart-3baff443-808c-4f24-abc8-1261dbaa44a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24734
09918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.2473409918
Directory /workspace/28.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2326735438
Short name T2204
Test name
Test status
Simulation time 176845957 ps
CPU time 0.9 seconds
Started Aug 05 05:37:39 PM PDT 24
Finished Aug 05 05:37:40 PM PDT 24
Peak memory 207368 kb
Host smart-8a7ef48b-3ce4-46cb-b7da-ba3c62c8b269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23267
35438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2326735438
Directory /workspace/28.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/28.usbdev_rx_full.271370723
Short name T1704
Test name
Test status
Simulation time 275548275 ps
CPU time 1.23 seconds
Started Aug 05 05:37:42 PM PDT 24
Finished Aug 05 05:37:44 PM PDT 24
Peak memory 207284 kb
Host smart-4b3cbb23-a683-4913-ad02-9a1acb957e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27137
0723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.271370723
Directory /workspace/28.usbdev_rx_full/latest


Test location /workspace/coverage/default/28.usbdev_setup_stage.2690685331
Short name T2116
Test name
Test status
Simulation time 163050904 ps
CPU time 0.88 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207316 kb
Host smart-ac77cb95-3c27-4469-941b-f6cf3a23bf51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26906
85331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2690685331
Directory /workspace/28.usbdev_setup_stage/latest


Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3705485587
Short name T2117
Test name
Test status
Simulation time 145912868 ps
CPU time 0.87 seconds
Started Aug 05 05:37:50 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207356 kb
Host smart-fbe1d5e9-cb0d-4b8a-901f-e18267aaec85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37054
85587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3705485587
Directory /workspace/28.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/28.usbdev_smoke.1268018782
Short name T2904
Test name
Test status
Simulation time 202345900 ps
CPU time 0.99 seconds
Started Aug 05 05:37:43 PM PDT 24
Finished Aug 05 05:37:44 PM PDT 24
Peak memory 207324 kb
Host smart-7abfdc43-9ad9-4039-9492-181c5dfe113f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12680
18782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1268018782
Directory /workspace/28.usbdev_smoke/latest


Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.612000632
Short name T663
Test name
Test status
Simulation time 2779117937 ps
CPU time 80.68 seconds
Started Aug 05 05:37:43 PM PDT 24
Finished Aug 05 05:39:04 PM PDT 24
Peak memory 217484 kb
Host smart-1438cf89-9397-4b38-8427-0221ce60df31
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=612000632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.612000632
Directory /workspace/28.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.4194027647
Short name T2584
Test name
Test status
Simulation time 169719084 ps
CPU time 0.87 seconds
Started Aug 05 05:37:56 PM PDT 24
Finished Aug 05 05:37:57 PM PDT 24
Peak memory 207384 kb
Host smart-98e401cf-0033-4b13-a73e-09d96c46a1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41940
27647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.4194027647
Directory /workspace/28.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/28.usbdev_stall_trans.2729871235
Short name T2590
Test name
Test status
Simulation time 174457812 ps
CPU time 0.88 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:37:54 PM PDT 24
Peak memory 207296 kb
Host smart-69c5677d-3307-4c05-83e7-e130280f5a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27298
71235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2729871235
Directory /workspace/28.usbdev_stall_trans/latest


Test location /workspace/coverage/default/28.usbdev_stream_len_max.1571171177
Short name T2420
Test name
Test status
Simulation time 855453058 ps
CPU time 2.28 seconds
Started Aug 05 05:37:41 PM PDT 24
Finished Aug 05 05:37:43 PM PDT 24
Peak memory 207548 kb
Host smart-99fe96e4-060d-4596-84cb-ec37ef4d0e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15711
71177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.1571171177
Directory /workspace/28.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/28.usbdev_streaming_out.2432933524
Short name T2253
Test name
Test status
Simulation time 2356196983 ps
CPU time 19.07 seconds
Started Aug 05 05:37:44 PM PDT 24
Finished Aug 05 05:38:03 PM PDT 24
Peak memory 215908 kb
Host smart-c7755165-7075-47e3-83c3-b2071a1822f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24329
33524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2432933524
Directory /workspace/28.usbdev_streaming_out/latest


Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.2049837497
Short name T2053
Test name
Test status
Simulation time 2066572870 ps
CPU time 18.27 seconds
Started Aug 05 05:37:34 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207576 kb
Host smart-9dd01a4a-9c7d-4129-b327-ad132a6d0de9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049837497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.2049837497
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/29.usbdev_alert_test.3988789741
Short name T1516
Test name
Test status
Simulation time 47809879 ps
CPU time 0.71 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207380 kb
Host smart-58f3126c-a6f0-47f0-a292-ae900d4e2b58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3988789741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3988789741
Directory /workspace/29.usbdev_alert_test/latest


Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.3075020545
Short name T227
Test name
Test status
Simulation time 4625947563 ps
CPU time 6.01 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:53 PM PDT 24
Peak memory 215736 kb
Host smart-e886f4d3-13eb-46d1-946a-22b311a9e86b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075020545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.3075020545
Directory /workspace/29.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3501362756
Short name T1603
Test name
Test status
Simulation time 21080245445 ps
CPU time 22.24 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:38:09 PM PDT 24
Peak memory 207672 kb
Host smart-e8ca888f-5b5f-4ea6-9e2d-5ebec19aef88
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501362756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3501362756
Directory /workspace/29.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2430437955
Short name T2100
Test name
Test status
Simulation time 28516851763 ps
CPU time 35.11 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 207556 kb
Host smart-d634eded-e8ee-462b-8e27-56601926850d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430437955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.2430437955
Directory /workspace/29.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/29.usbdev_av_buffer.2699209899
Short name T1633
Test name
Test status
Simulation time 229345609 ps
CPU time 0.95 seconds
Started Aug 05 05:37:49 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 207224 kb
Host smart-cab950d7-7642-4f4c-8e74-4bee50c79bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26992
09899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2699209899
Directory /workspace/29.usbdev_av_buffer/latest


Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2278804357
Short name T1894
Test name
Test status
Simulation time 147293248 ps
CPU time 0.82 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:37:47 PM PDT 24
Peak memory 207356 kb
Host smart-69b9c8a8-3484-43d5-8c05-ad8194568ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22788
04357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2278804357
Directory /workspace/29.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.50183789
Short name T1227
Test name
Test status
Simulation time 341490568 ps
CPU time 1.33 seconds
Started Aug 05 05:37:50 PM PDT 24
Finished Aug 05 05:37:51 PM PDT 24
Peak memory 207304 kb
Host smart-abb3e59e-6774-47a0-82e9-123c7bffb18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50183
789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.50183789
Directory /workspace/29.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2546219397
Short name T974
Test name
Test status
Simulation time 631087560 ps
CPU time 1.79 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207276 kb
Host smart-836b9532-cb31-434f-9f88-760e2e09ee5f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2546219397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2546219397
Directory /workspace/29.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/29.usbdev_device_address.2349464233
Short name T1645
Test name
Test status
Simulation time 35807552600 ps
CPU time 61.96 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:38:50 PM PDT 24
Peak memory 207568 kb
Host smart-efcf2f7a-a1b2-4354-82e7-4eec70099176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23494
64233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.2349464233
Directory /workspace/29.usbdev_device_address/latest


Test location /workspace/coverage/default/29.usbdev_device_timeout.361118742
Short name T2255
Test name
Test status
Simulation time 2549627537 ps
CPU time 21.84 seconds
Started Aug 05 05:37:59 PM PDT 24
Finished Aug 05 05:38:21 PM PDT 24
Peak memory 207760 kb
Host smart-a7ad491b-6056-42d8-aeed-6a0249ef2812
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361118742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.361118742
Directory /workspace/29.usbdev_device_timeout/latest


Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1130454466
Short name T1689
Test name
Test status
Simulation time 644018072 ps
CPU time 1.59 seconds
Started Aug 05 05:37:43 PM PDT 24
Finished Aug 05 05:37:45 PM PDT 24
Peak memory 207256 kb
Host smart-e6996453-f733-4d48-81dd-ddb3f9d185ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11304
54466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1130454466
Directory /workspace/29.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/29.usbdev_disconnected.408162084
Short name T1822
Test name
Test status
Simulation time 163920992 ps
CPU time 0.85 seconds
Started Aug 05 05:37:52 PM PDT 24
Finished Aug 05 05:37:53 PM PDT 24
Peak memory 207348 kb
Host smart-63c29207-9a1a-48cb-9f40-145410b9614e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40816
2084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.408162084
Directory /workspace/29.usbdev_disconnected/latest


Test location /workspace/coverage/default/29.usbdev_enable.3883925469
Short name T3087
Test name
Test status
Simulation time 35525597 ps
CPU time 0.73 seconds
Started Aug 05 05:37:50 PM PDT 24
Finished Aug 05 05:37:51 PM PDT 24
Peak memory 207312 kb
Host smart-732986c4-7c82-462a-9362-d6b5ba208b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38839
25469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3883925469
Directory /workspace/29.usbdev_enable/latest


Test location /workspace/coverage/default/29.usbdev_endpoint_access.3311979895
Short name T1692
Test name
Test status
Simulation time 865345668 ps
CPU time 2.34 seconds
Started Aug 05 05:37:52 PM PDT 24
Finished Aug 05 05:37:54 PM PDT 24
Peak memory 207460 kb
Host smart-4d368dd5-74b7-4d13-8c86-28cb958320d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33119
79895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3311979895
Directory /workspace/29.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/29.usbdev_endpoint_types.3290690596
Short name T476
Test name
Test status
Simulation time 285754250 ps
CPU time 1.18 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:37:47 PM PDT 24
Peak memory 207324 kb
Host smart-d3f49d51-14b2-47b7-8108-c56732fd1ee5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3290690596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.3290690596
Directory /workspace/29.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/29.usbdev_fifo_rst.464596865
Short name T1350
Test name
Test status
Simulation time 359516550 ps
CPU time 2.49 seconds
Started Aug 05 05:37:45 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207388 kb
Host smart-0dd29870-8398-4d5e-af91-4d672566927c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46459
6865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.464596865
Directory /workspace/29.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/29.usbdev_in_iso.1334161033
Short name T901
Test name
Test status
Simulation time 188159401 ps
CPU time 1 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207432 kb
Host smart-f9dd7de8-6dc3-4318-a934-6bc45a8a4624
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1334161033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1334161033
Directory /workspace/29.usbdev_in_iso/latest


Test location /workspace/coverage/default/29.usbdev_in_stall.777373523
Short name T2607
Test name
Test status
Simulation time 147798732 ps
CPU time 0.85 seconds
Started Aug 05 05:37:44 PM PDT 24
Finished Aug 05 05:37:45 PM PDT 24
Peak memory 207312 kb
Host smart-cb4a8cc2-2e9b-45de-89d9-c676d2e70fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77737
3523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.777373523
Directory /workspace/29.usbdev_in_stall/latest


Test location /workspace/coverage/default/29.usbdev_in_trans.510336911
Short name T1971
Test name
Test status
Simulation time 232969704 ps
CPU time 0.99 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207240 kb
Host smart-2c070fba-374c-4a21-9b0e-32ce467602e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51033
6911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.510336911
Directory /workspace/29.usbdev_in_trans/latest


Test location /workspace/coverage/default/29.usbdev_invalid_sync.527787647
Short name T1700
Test name
Test status
Simulation time 5936382229 ps
CPU time 44.62 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:38:31 PM PDT 24
Peak memory 216076 kb
Host smart-7ceac7ba-1da7-462c-9170-58b0a25cb7b9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=527787647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.527787647
Directory /workspace/29.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/29.usbdev_iso_retraction.4091363763
Short name T93
Test name
Test status
Simulation time 7625852359 ps
CPU time 88.08 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:39:21 PM PDT 24
Peak memory 207620 kb
Host smart-32db5c0f-cef6-44b1-886e-c25937cb8892
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4091363763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.4091363763
Directory /workspace/29.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/29.usbdev_link_in_err.3952142068
Short name T1707
Test name
Test status
Simulation time 247394020 ps
CPU time 1.05 seconds
Started Aug 05 05:37:45 PM PDT 24
Finished Aug 05 05:37:46 PM PDT 24
Peak memory 207396 kb
Host smart-7652b7fa-da18-4f84-830d-9b2c29d50cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39521
42068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3952142068
Directory /workspace/29.usbdev_link_in_err/latest


Test location /workspace/coverage/default/29.usbdev_link_resume.125534301
Short name T2126
Test name
Test status
Simulation time 28364991025 ps
CPU time 43.9 seconds
Started Aug 05 05:37:45 PM PDT 24
Finished Aug 05 05:38:29 PM PDT 24
Peak memory 207700 kb
Host smart-9efe7155-5e40-483d-942b-efdbea589330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12553
4301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.125534301
Directory /workspace/29.usbdev_link_resume/latest


Test location /workspace/coverage/default/29.usbdev_link_suspend.1619418097
Short name T2351
Test name
Test status
Simulation time 3564388447 ps
CPU time 5.41 seconds
Started Aug 05 05:37:45 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 215812 kb
Host smart-b3c10700-2b4d-4966-a2b9-0cb5f2a066f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16194
18097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1619418097
Directory /workspace/29.usbdev_link_suspend/latest


Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2858564822
Short name T1589
Test name
Test status
Simulation time 3443906915 ps
CPU time 35.1 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 215832 kb
Host smart-6bbc28a8-963b-4f5f-a501-68254632e948
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2858564822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2858564822
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.4180181310
Short name T487
Test name
Test status
Simulation time 267275038 ps
CPU time 1.14 seconds
Started Aug 05 05:37:51 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207352 kb
Host smart-a9282b50-9f2b-469b-b061-c46a21c76fd7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4180181310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.4180181310
Directory /workspace/29.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2187679050
Short name T1048
Test name
Test status
Simulation time 244078295 ps
CPU time 0.98 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207608 kb
Host smart-56f104e2-b917-4e14-8949-845dbe24d079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21876
79050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2187679050
Directory /workspace/29.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2945399875
Short name T1477
Test name
Test status
Simulation time 2955869676 ps
CPU time 22.59 seconds
Started Aug 05 05:37:44 PM PDT 24
Finished Aug 05 05:38:07 PM PDT 24
Peak memory 223960 kb
Host smart-26e65f50-51e4-4f23-a779-0a6d3f683cb2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2945399875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2945399875
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1172715767
Short name T2708
Test name
Test status
Simulation time 157331002 ps
CPU time 0.84 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207272 kb
Host smart-79f7fcf8-9d89-4b19-8142-4288b29d1703
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1172715767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1172715767
Directory /workspace/29.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.147166958
Short name T2419
Test name
Test status
Simulation time 153956016 ps
CPU time 0.89 seconds
Started Aug 05 05:37:57 PM PDT 24
Finished Aug 05 05:37:58 PM PDT 24
Peak memory 207232 kb
Host smart-415d88c1-5101-4452-97eb-9e422c7302e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14716
6958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.147166958
Directory /workspace/29.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/29.usbdev_nak_trans.3424704798
Short name T1999
Test name
Test status
Simulation time 218405999 ps
CPU time 0.97 seconds
Started Aug 05 05:37:51 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207348 kb
Host smart-8bd86930-ca50-45ad-b8c5-0878391298f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34247
04798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3424704798
Directory /workspace/29.usbdev_nak_trans/latest


Test location /workspace/coverage/default/29.usbdev_out_iso.1337069693
Short name T2654
Test name
Test status
Simulation time 150223223 ps
CPU time 0.84 seconds
Started Aug 05 05:37:45 PM PDT 24
Finished Aug 05 05:37:46 PM PDT 24
Peak memory 207348 kb
Host smart-59d6c01d-88b1-4787-be11-e7e4e2ae31bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13370
69693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1337069693
Directory /workspace/29.usbdev_out_iso/latest


Test location /workspace/coverage/default/29.usbdev_out_stall.2188381699
Short name T865
Test name
Test status
Simulation time 182322112 ps
CPU time 0.89 seconds
Started Aug 05 05:37:55 PM PDT 24
Finished Aug 05 05:37:56 PM PDT 24
Peak memory 207284 kb
Host smart-f270859b-fc59-4266-9843-7de7d0cb1818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21883
81699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2188381699
Directory /workspace/29.usbdev_out_stall/latest


Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1235333267
Short name T2085
Test name
Test status
Simulation time 184768401 ps
CPU time 0.91 seconds
Started Aug 05 05:37:45 PM PDT 24
Finished Aug 05 05:37:46 PM PDT 24
Peak memory 207404 kb
Host smart-4219672a-ac3e-4c39-a31d-f2b9b9674723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12353
33267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1235333267
Directory /workspace/29.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3434657366
Short name T2409
Test name
Test status
Simulation time 218988542 ps
CPU time 0.91 seconds
Started Aug 05 05:37:41 PM PDT 24
Finished Aug 05 05:37:42 PM PDT 24
Peak memory 207288 kb
Host smart-e73e6389-94e2-47a0-af00-af5f64a896d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34346
57366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3434657366
Directory /workspace/29.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2262914943
Short name T2231
Test name
Test status
Simulation time 281917350 ps
CPU time 1.02 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207356 kb
Host smart-9143d308-6e70-4a54-a9d9-ee8b761998dc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2262914943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2262914943
Directory /workspace/29.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.705300982
Short name T1583
Test name
Test status
Simulation time 144399998 ps
CPU time 0.89 seconds
Started Aug 05 05:37:39 PM PDT 24
Finished Aug 05 05:37:40 PM PDT 24
Peak memory 207244 kb
Host smart-5c545a17-cb92-4e6b-8f49-4d77c37c7ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70530
0982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.705300982
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2541273904
Short name T43
Test name
Test status
Simulation time 34777159 ps
CPU time 0.67 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207288 kb
Host smart-43436927-fa1a-4a5a-b4ac-18f02a469b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25412
73904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2541273904
Directory /workspace/29.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1753789065
Short name T2312
Test name
Test status
Simulation time 11459074735 ps
CPU time 30.81 seconds
Started Aug 05 05:37:52 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 215812 kb
Host smart-79f60fde-8b55-4134-926c-e0d266880eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17537
89065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1753789065
Directory /workspace/29.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/29.usbdev_pkt_received.1227241212
Short name T2528
Test name
Test status
Simulation time 156498432 ps
CPU time 0.87 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:37:47 PM PDT 24
Peak memory 207380 kb
Host smart-4e2e5ab7-b07d-41b8-89a8-163f0e047a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12272
41212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1227241212
Directory /workspace/29.usbdev_pkt_received/latest


Test location /workspace/coverage/default/29.usbdev_pkt_sent.73905855
Short name T2886
Test name
Test status
Simulation time 239686437 ps
CPU time 1 seconds
Started Aug 05 05:37:44 PM PDT 24
Finished Aug 05 05:37:45 PM PDT 24
Peak memory 207268 kb
Host smart-8dbc1371-c75e-4d72-9db7-528b55b33cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73905
855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.73905855
Directory /workspace/29.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.3183826116
Short name T3069
Test name
Test status
Simulation time 237499955 ps
CPU time 0.99 seconds
Started Aug 05 05:37:45 PM PDT 24
Finished Aug 05 05:37:46 PM PDT 24
Peak memory 207348 kb
Host smart-95fd8cbc-c7e3-41f9-a794-b0f9e2b1812b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31838
26116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.3183826116
Directory /workspace/29.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.2568428452
Short name T3025
Test name
Test status
Simulation time 152511531 ps
CPU time 0.93 seconds
Started Aug 05 05:37:50 PM PDT 24
Finished Aug 05 05:37:51 PM PDT 24
Peak memory 207400 kb
Host smart-e4e39ade-be83-49a0-b68d-8bfeaf0bc452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25684
28452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.2568428452
Directory /workspace/29.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2701691621
Short name T1812
Test name
Test status
Simulation time 144029620 ps
CPU time 0.84 seconds
Started Aug 05 05:37:51 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207316 kb
Host smart-5f80e79d-aa03-4a99-9ede-82cf0ee0031d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27016
91621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2701691621
Directory /workspace/29.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/29.usbdev_rx_full.2449037526
Short name T2440
Test name
Test status
Simulation time 399294644 ps
CPU time 1.54 seconds
Started Aug 05 05:37:52 PM PDT 24
Finished Aug 05 05:37:53 PM PDT 24
Peak memory 207320 kb
Host smart-33d6ffe2-f8b8-4bcf-8b49-35b8bc76f55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24490
37526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.2449037526
Directory /workspace/29.usbdev_rx_full/latest


Test location /workspace/coverage/default/29.usbdev_setup_stage.2811834094
Short name T722
Test name
Test status
Simulation time 192401872 ps
CPU time 0.96 seconds
Started Aug 05 05:37:50 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207288 kb
Host smart-dff78ff7-6914-450e-9b05-f61ecbff16db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28118
34094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2811834094
Directory /workspace/29.usbdev_setup_stage/latest


Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3993726669
Short name T2984
Test name
Test status
Simulation time 158250138 ps
CPU time 0.87 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:37:54 PM PDT 24
Peak memory 207348 kb
Host smart-f6341c76-1ebc-4276-b619-4d2627bd5337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39937
26669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3993726669
Directory /workspace/29.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/29.usbdev_smoke.982729134
Short name T2373
Test name
Test status
Simulation time 210612027 ps
CPU time 0.93 seconds
Started Aug 05 05:37:45 PM PDT 24
Finished Aug 05 05:37:46 PM PDT 24
Peak memory 207376 kb
Host smart-9427b806-4648-4a2e-a2f6-efa2a163c03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98272
9134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.982729134
Directory /workspace/29.usbdev_smoke/latest


Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.510351002
Short name T966
Test name
Test status
Simulation time 2266589834 ps
CPU time 66.01 seconds
Started Aug 05 05:37:44 PM PDT 24
Finished Aug 05 05:38:51 PM PDT 24
Peak memory 217312 kb
Host smart-a2d55f8b-1ea9-4766-97f8-34a85beace97
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=510351002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.510351002
Directory /workspace/29.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.251135644
Short name T979
Test name
Test status
Simulation time 162192085 ps
CPU time 0.86 seconds
Started Aug 05 05:37:54 PM PDT 24
Finished Aug 05 05:37:55 PM PDT 24
Peak memory 207232 kb
Host smart-f6a7951d-30f3-461b-a0c8-bade6c18e605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25113
5644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.251135644
Directory /workspace/29.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/29.usbdev_stall_trans.2334736008
Short name T2123
Test name
Test status
Simulation time 214125839 ps
CPU time 0.86 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207348 kb
Host smart-70b29b45-f4c6-47ed-b901-d7c756e14e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23347
36008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2334736008
Directory /workspace/29.usbdev_stall_trans/latest


Test location /workspace/coverage/default/29.usbdev_stream_len_max.3948558666
Short name T2864
Test name
Test status
Simulation time 1260790082 ps
CPU time 2.8 seconds
Started Aug 05 05:37:54 PM PDT 24
Finished Aug 05 05:37:56 PM PDT 24
Peak memory 207584 kb
Host smart-7954069f-7457-446c-87dc-64f7873a7c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39485
58666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.3948558666
Directory /workspace/29.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/29.usbdev_streaming_out.254974104
Short name T1839
Test name
Test status
Simulation time 2112007364 ps
CPU time 15.69 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:38:04 PM PDT 24
Peak memory 223872 kb
Host smart-aeefb995-f3b5-470e-b1ca-489d9b200632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25497
4104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.254974104
Directory /workspace/29.usbdev_streaming_out/latest


Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.2383528150
Short name T2637
Test name
Test status
Simulation time 986305129 ps
CPU time 22.27 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:38:09 PM PDT 24
Peak memory 207436 kb
Host smart-b5f35721-a0fd-4f0f-afff-4b54e0a9385a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383528150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_hos
t_handshake.2383528150
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/3.usbdev_alert_test.2271894315
Short name T2314
Test name
Test status
Simulation time 36783744 ps
CPU time 0.67 seconds
Started Aug 05 05:33:37 PM PDT 24
Finished Aug 05 05:33:38 PM PDT 24
Peak memory 207412 kb
Host smart-1c6e182a-abe8-4cf3-aad3-c8a742721acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2271894315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2271894315
Directory /workspace/3.usbdev_alert_test/latest


Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.58921538
Short name T3104
Test name
Test status
Simulation time 5981196458 ps
CPU time 8.5 seconds
Started Aug 05 05:33:32 PM PDT 24
Finished Aug 05 05:33:41 PM PDT 24
Peak memory 215816 kb
Host smart-d50231f6-307d-4f5d-a8e5-1e27b868dfcd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58921538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_
wake_disconnect.58921538
Directory /workspace/3.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2098699425
Short name T2293
Test name
Test status
Simulation time 20688651570 ps
CPU time 26.09 seconds
Started Aug 05 05:33:31 PM PDT 24
Finished Aug 05 05:33:57 PM PDT 24
Peak memory 207860 kb
Host smart-8867bb75-1e26-4c6a-a88d-c20212b5fa21
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098699425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2098699425
Directory /workspace/3.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.974195380
Short name T1552
Test name
Test status
Simulation time 31252258140 ps
CPU time 39.64 seconds
Started Aug 05 05:33:30 PM PDT 24
Finished Aug 05 05:34:10 PM PDT 24
Peak memory 207668 kb
Host smart-d547e74b-dadc-445b-9b48-9155aced4d53
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974195380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon
_wake_resume.974195380
Directory /workspace/3.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/3.usbdev_av_buffer.1420066571
Short name T2568
Test name
Test status
Simulation time 151430043 ps
CPU time 0.87 seconds
Started Aug 05 05:33:30 PM PDT 24
Finished Aug 05 05:33:31 PM PDT 24
Peak memory 207340 kb
Host smart-c16c53b8-8344-4051-b7ac-19c7928e19c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14200
66571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1420066571
Directory /workspace/3.usbdev_av_buffer/latest


Test location /workspace/coverage/default/3.usbdev_av_empty.1179724227
Short name T51
Test name
Test status
Simulation time 222219077 ps
CPU time 0.96 seconds
Started Aug 05 05:33:34 PM PDT 24
Finished Aug 05 05:33:35 PM PDT 24
Peak memory 207168 kb
Host smart-4c55acdd-9cb4-44be-b018-c5ad59b40d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11797
24227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1179724227
Directory /workspace/3.usbdev_av_empty/latest


Test location /workspace/coverage/default/3.usbdev_av_overflow.1318222575
Short name T101
Test name
Test status
Simulation time 137366059 ps
CPU time 0.81 seconds
Started Aug 05 05:33:31 PM PDT 24
Finished Aug 05 05:33:31 PM PDT 24
Peak memory 207284 kb
Host smart-dd11769c-b267-4305-bf14-650fa2b87784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13182
22575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.1318222575
Directory /workspace/3.usbdev_av_overflow/latest


Test location /workspace/coverage/default/3.usbdev_bitstuff_err.1349392795
Short name T3131
Test name
Test status
Simulation time 169823042 ps
CPU time 0.92 seconds
Started Aug 05 05:33:30 PM PDT 24
Finished Aug 05 05:33:31 PM PDT 24
Peak memory 207316 kb
Host smart-40a63182-d8a5-465e-9a7d-753c4234ebf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13493
92795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.1349392795
Directory /workspace/3.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.4151169859
Short name T1435
Test name
Test status
Simulation time 368754014 ps
CPU time 1.35 seconds
Started Aug 05 05:33:31 PM PDT 24
Finished Aug 05 05:33:32 PM PDT 24
Peak memory 207348 kb
Host smart-2015716b-acc8-49c9-89d9-5259d6445d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41511
69859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.4151169859
Directory /workspace/3.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3826864912
Short name T1462
Test name
Test status
Simulation time 975382249 ps
CPU time 2.54 seconds
Started Aug 05 05:33:31 PM PDT 24
Finished Aug 05 05:33:34 PM PDT 24
Peak memory 207656 kb
Host smart-3db7d760-6d0b-490a-906c-ec2750de7481
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3826864912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3826864912
Directory /workspace/3.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/3.usbdev_device_address.362644722
Short name T1160
Test name
Test status
Simulation time 57807746161 ps
CPU time 89.18 seconds
Started Aug 05 05:33:29 PM PDT 24
Finished Aug 05 05:34:59 PM PDT 24
Peak memory 207664 kb
Host smart-9ad679e8-3a96-4035-8ce0-cf1d6f57ae76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36264
4722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.362644722
Directory /workspace/3.usbdev_device_address/latest


Test location /workspace/coverage/default/3.usbdev_device_timeout.3537160951
Short name T1004
Test name
Test status
Simulation time 3770275732 ps
CPU time 25.31 seconds
Started Aug 05 05:33:33 PM PDT 24
Finished Aug 05 05:33:59 PM PDT 24
Peak memory 207576 kb
Host smart-a9f66d48-e33e-409d-a2e8-96f38d41685d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537160951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.3537160951
Directory /workspace/3.usbdev_device_timeout/latest


Test location /workspace/coverage/default/3.usbdev_disable_endpoint.512659259
Short name T1136
Test name
Test status
Simulation time 703904008 ps
CPU time 1.79 seconds
Started Aug 05 05:33:33 PM PDT 24
Finished Aug 05 05:33:35 PM PDT 24
Peak memory 207336 kb
Host smart-538d54ab-df51-4ffa-8520-c2796e8eca2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51265
9259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.512659259
Directory /workspace/3.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/3.usbdev_disconnected.420903514
Short name T1322
Test name
Test status
Simulation time 161079341 ps
CPU time 0.87 seconds
Started Aug 05 05:33:28 PM PDT 24
Finished Aug 05 05:33:29 PM PDT 24
Peak memory 207364 kb
Host smart-5707475b-d777-4b9c-b475-559c30da3b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42090
3514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.420903514
Directory /workspace/3.usbdev_disconnected/latest


Test location /workspace/coverage/default/3.usbdev_enable.4260751349
Short name T754
Test name
Test status
Simulation time 37021645 ps
CPU time 0.69 seconds
Started Aug 05 05:33:29 PM PDT 24
Finished Aug 05 05:33:29 PM PDT 24
Peak memory 207364 kb
Host smart-a1b80c5f-7a1a-4dcd-8184-20064b6510f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42607
51349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.4260751349
Directory /workspace/3.usbdev_enable/latest


Test location /workspace/coverage/default/3.usbdev_endpoint_access.1152389539
Short name T2970
Test name
Test status
Simulation time 838951677 ps
CPU time 2.14 seconds
Started Aug 05 05:33:27 PM PDT 24
Finished Aug 05 05:33:30 PM PDT 24
Peak memory 207548 kb
Host smart-f053bc62-1dd1-4ce1-9a43-b359af684f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11523
89539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.1152389539
Directory /workspace/3.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/3.usbdev_endpoint_types.3392417999
Short name T336
Test name
Test status
Simulation time 622868661 ps
CPU time 1.68 seconds
Started Aug 05 05:33:37 PM PDT 24
Finished Aug 05 05:33:39 PM PDT 24
Peak memory 207240 kb
Host smart-a0579858-b00d-49b8-aa32-02cacdc7501c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3392417999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.3392417999
Directory /workspace/3.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/3.usbdev_fifo_rst.822051337
Short name T189
Test name
Test status
Simulation time 292334258 ps
CPU time 2.18 seconds
Started Aug 05 05:33:34 PM PDT 24
Finished Aug 05 05:33:36 PM PDT 24
Peak memory 207548 kb
Host smart-47019cde-54f4-4458-b241-9ef231155022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82205
1337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.822051337
Directory /workspace/3.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3873988747
Short name T1080
Test name
Test status
Simulation time 110259660361 ps
CPU time 154.4 seconds
Started Aug 05 05:33:31 PM PDT 24
Finished Aug 05 05:36:05 PM PDT 24
Peak memory 207724 kb
Host smart-3d4540b0-b3d3-4c4c-b813-c483dd927557
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3873988747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3873988747
Directory /workspace/3.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.2607454312
Short name T478
Test name
Test status
Simulation time 109404456197 ps
CPU time 187.02 seconds
Started Aug 05 05:33:31 PM PDT 24
Finished Aug 05 05:36:38 PM PDT 24
Peak memory 207592 kb
Host smart-e714021f-d47b-4fdb-92f4-5e0245d855a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607454312 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.2607454312
Directory /workspace/3.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/3.usbdev_freq_loclk.3719134655
Short name T485
Test name
Test status
Simulation time 119100279560 ps
CPU time 177.16 seconds
Started Aug 05 05:33:30 PM PDT 24
Finished Aug 05 05:36:27 PM PDT 24
Peak memory 207620 kb
Host smart-b4f601d8-6b5d-4b55-b25d-c026a81db625
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3719134655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.3719134655
Directory /workspace/3.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.606579974
Short name T1393
Test name
Test status
Simulation time 103998031304 ps
CPU time 187.82 seconds
Started Aug 05 05:33:32 PM PDT 24
Finished Aug 05 05:36:40 PM PDT 24
Peak memory 207916 kb
Host smart-1be72dd4-7679-4906-a45f-6f055010cee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606579974 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.606579974
Directory /workspace/3.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/3.usbdev_freq_phase.3406394812
Short name T1531
Test name
Test status
Simulation time 82146226990 ps
CPU time 140.84 seconds
Started Aug 05 05:33:37 PM PDT 24
Finished Aug 05 05:35:58 PM PDT 24
Peak memory 207668 kb
Host smart-555cc1df-a115-4997-a4fc-54cecced0665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34063
94812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.3406394812
Directory /workspace/3.usbdev_freq_phase/latest


Test location /workspace/coverage/default/3.usbdev_in_iso.1903546985
Short name T2711
Test name
Test status
Simulation time 175744986 ps
CPU time 0.92 seconds
Started Aug 05 05:33:33 PM PDT 24
Finished Aug 05 05:33:34 PM PDT 24
Peak memory 207384 kb
Host smart-66d78fe5-129e-488d-be6c-5ba87c3c8e46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1903546985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1903546985
Directory /workspace/3.usbdev_in_iso/latest


Test location /workspace/coverage/default/3.usbdev_in_stall.3843308780
Short name T2968
Test name
Test status
Simulation time 148756258 ps
CPU time 0.84 seconds
Started Aug 05 05:33:38 PM PDT 24
Finished Aug 05 05:33:39 PM PDT 24
Peak memory 207288 kb
Host smart-fef778cf-6cd8-4688-90bf-8c446a5d8b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38433
08780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3843308780
Directory /workspace/3.usbdev_in_stall/latest


Test location /workspace/coverage/default/3.usbdev_in_trans.3459885990
Short name T506
Test name
Test status
Simulation time 245197728 ps
CPU time 1.11 seconds
Started Aug 05 05:33:40 PM PDT 24
Finished Aug 05 05:33:42 PM PDT 24
Peak memory 207352 kb
Host smart-222d142f-bf5c-4dd8-8f7f-0803de0ba071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34598
85990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3459885990
Directory /workspace/3.usbdev_in_trans/latest


Test location /workspace/coverage/default/3.usbdev_invalid_sync.3291640420
Short name T2464
Test name
Test status
Simulation time 3841233784 ps
CPU time 111.98 seconds
Started Aug 05 05:33:33 PM PDT 24
Finished Aug 05 05:35:26 PM PDT 24
Peak memory 215880 kb
Host smart-099369e7-7a27-449b-b73a-1d865cdffe59
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3291640420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3291640420
Directory /workspace/3.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/3.usbdev_iso_retraction.1218088903
Short name T3074
Test name
Test status
Simulation time 6833815462 ps
CPU time 78.05 seconds
Started Aug 05 05:33:38 PM PDT 24
Finished Aug 05 05:34:57 PM PDT 24
Peak memory 207656 kb
Host smart-dfbfbfdd-026b-4d68-894f-b754b90bc880
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1218088903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.1218088903
Directory /workspace/3.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/3.usbdev_link_in_err.4228372965
Short name T1542
Test name
Test status
Simulation time 215106877 ps
CPU time 1 seconds
Started Aug 05 05:33:35 PM PDT 24
Finished Aug 05 05:33:36 PM PDT 24
Peak memory 207324 kb
Host smart-5afb2353-1887-4109-bd6b-ea2ddfdcd125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42283
72965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.4228372965
Directory /workspace/3.usbdev_link_in_err/latest


Test location /workspace/coverage/default/3.usbdev_link_resume.1604834470
Short name T2867
Test name
Test status
Simulation time 30305133900 ps
CPU time 45.29 seconds
Started Aug 05 05:33:33 PM PDT 24
Finished Aug 05 05:34:18 PM PDT 24
Peak memory 207572 kb
Host smart-bddb22d9-bd8b-4d62-afc9-5bb74cd6c6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16048
34470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1604834470
Directory /workspace/3.usbdev_link_resume/latest


Test location /workspace/coverage/default/3.usbdev_link_suspend.147959688
Short name T525
Test name
Test status
Simulation time 5985377799 ps
CPU time 7.81 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:33:47 PM PDT 24
Peak memory 207624 kb
Host smart-e89c4dd4-491a-41f9-977a-ebe34f4e00b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14795
9688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.147959688
Directory /workspace/3.usbdev_link_suspend/latest


Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.842697349
Short name T2067
Test name
Test status
Simulation time 4943286913 ps
CPU time 50.99 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:34:30 PM PDT 24
Peak memory 224020 kb
Host smart-278a25dd-fdef-4894-8628-a497a0787bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84269
7349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.842697349
Directory /workspace/3.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.163466846
Short name T2492
Test name
Test status
Simulation time 2353814421 ps
CPU time 17.13 seconds
Started Aug 05 05:33:42 PM PDT 24
Finished Aug 05 05:34:00 PM PDT 24
Peak memory 223796 kb
Host smart-63c82dfd-5529-4c18-89c6-217c8f269495
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=163466846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.163466846
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.1963679941
Short name T1348
Test name
Test status
Simulation time 263931792 ps
CPU time 1.07 seconds
Started Aug 05 05:33:38 PM PDT 24
Finished Aug 05 05:33:40 PM PDT 24
Peak memory 207372 kb
Host smart-b93e66e6-634f-4d24-a37c-54c4eb0c6b99
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1963679941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.1963679941
Directory /workspace/3.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2663500174
Short name T3084
Test name
Test status
Simulation time 221822564 ps
CPU time 1.03 seconds
Started Aug 05 05:33:38 PM PDT 24
Finished Aug 05 05:33:39 PM PDT 24
Peak memory 207392 kb
Host smart-0f20df89-6cc4-45bd-b413-8f1388660ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26635
00174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2663500174
Directory /workspace/3.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.846537280
Short name T670
Test name
Test status
Simulation time 3584043878 ps
CPU time 26.75 seconds
Started Aug 05 05:33:36 PM PDT 24
Finished Aug 05 05:34:03 PM PDT 24
Peak memory 217588 kb
Host smart-6a63b92a-7c8d-4a07-bc49-7364bda409cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84653
7280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.846537280
Directory /workspace/3.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2436715666
Short name T2676
Test name
Test status
Simulation time 3060306273 ps
CPU time 34.81 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:34:14 PM PDT 24
Peak memory 223728 kb
Host smart-48972af7-23cc-47fc-9183-f1646ea40a43
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2436715666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2436715666
Directory /workspace/3.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.4005936073
Short name T327
Test name
Test status
Simulation time 4243457199 ps
CPU time 116.11 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:35:35 PM PDT 24
Peak memory 215896 kb
Host smart-4d2cceab-46bd-4186-8af5-f2afd4342a1c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4005936073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.4005936073
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3993403974
Short name T1302
Test name
Test status
Simulation time 187782840 ps
CPU time 1.01 seconds
Started Aug 05 05:33:41 PM PDT 24
Finished Aug 05 05:33:42 PM PDT 24
Peak memory 207348 kb
Host smart-8990a62a-8f4e-4397-8c26-b42ece236c3b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3993403974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3993403974
Directory /workspace/3.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1054842474
Short name T2330
Test name
Test status
Simulation time 167621808 ps
CPU time 0.89 seconds
Started Aug 05 05:33:38 PM PDT 24
Finished Aug 05 05:33:39 PM PDT 24
Peak memory 207340 kb
Host smart-50ca7bc8-e898-4bb4-b4b0-d7c6db2d0b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10548
42474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1054842474
Directory /workspace/3.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/3.usbdev_out_iso.2912349531
Short name T1385
Test name
Test status
Simulation time 188538717 ps
CPU time 0.94 seconds
Started Aug 05 05:33:47 PM PDT 24
Finished Aug 05 05:33:48 PM PDT 24
Peak memory 207296 kb
Host smart-560fbc21-f470-44ec-b712-1b88fabbbb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29123
49531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2912349531
Directory /workspace/3.usbdev_out_iso/latest


Test location /workspace/coverage/default/3.usbdev_out_stall.2596052241
Short name T2989
Test name
Test status
Simulation time 178377416 ps
CPU time 0.92 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:33:40 PM PDT 24
Peak memory 207384 kb
Host smart-2ed1ebda-c58e-4af8-a67f-de835969c237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25960
52241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2596052241
Directory /workspace/3.usbdev_out_stall/latest


Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1488714458
Short name T2413
Test name
Test status
Simulation time 184510340 ps
CPU time 0.89 seconds
Started Aug 05 05:33:36 PM PDT 24
Finished Aug 05 05:33:37 PM PDT 24
Peak memory 207372 kb
Host smart-bd56d9cd-0e0b-4471-a51f-54f9bdb2be14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14887
14458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1488714458
Directory /workspace/3.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1210376569
Short name T2056
Test name
Test status
Simulation time 146762129 ps
CPU time 0.84 seconds
Started Aug 05 05:33:33 PM PDT 24
Finished Aug 05 05:33:34 PM PDT 24
Peak memory 207296 kb
Host smart-b82dac40-6916-4d21-a0bb-534ae1b3f23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12103
76569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1210376569
Directory /workspace/3.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.1811960283
Short name T229
Test name
Test status
Simulation time 202963544 ps
CPU time 1 seconds
Started Aug 05 05:33:35 PM PDT 24
Finished Aug 05 05:33:36 PM PDT 24
Peak memory 207384 kb
Host smart-4a79630a-94d9-4366-83d6-ea11b1d8a600
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1811960283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.1811960283
Directory /workspace/3.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3997267174
Short name T207
Test name
Test status
Simulation time 314730754 ps
CPU time 1.17 seconds
Started Aug 05 05:33:36 PM PDT 24
Finished Aug 05 05:33:38 PM PDT 24
Peak memory 207324 kb
Host smart-89f6399e-abf6-4694-8b57-c2bc8e99e262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39972
67174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3997267174
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1430647734
Short name T1381
Test name
Test status
Simulation time 142408389 ps
CPU time 0.87 seconds
Started Aug 05 05:33:41 PM PDT 24
Finished Aug 05 05:33:42 PM PDT 24
Peak memory 207244 kb
Host smart-a4bdf436-b6c7-4b25-9722-fe4fab569d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14306
47734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1430647734
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3313370161
Short name T915
Test name
Test status
Simulation time 49134552 ps
CPU time 0.71 seconds
Started Aug 05 05:33:47 PM PDT 24
Finished Aug 05 05:33:48 PM PDT 24
Peak memory 207260 kb
Host smart-fd059629-af57-4eb4-8816-63c25bc495a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33133
70161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3313370161
Directory /workspace/3.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3589965390
Short name T328
Test name
Test status
Simulation time 19430283672 ps
CPU time 47.75 seconds
Started Aug 05 05:33:38 PM PDT 24
Finished Aug 05 05:34:26 PM PDT 24
Peak memory 215860 kb
Host smart-1a6c18ed-61e1-4b8f-b5fa-0b9b35716aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35899
65390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3589965390
Directory /workspace/3.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/3.usbdev_pkt_received.1083722791
Short name T848
Test name
Test status
Simulation time 164487682 ps
CPU time 0.88 seconds
Started Aug 05 05:33:37 PM PDT 24
Finished Aug 05 05:33:38 PM PDT 24
Peak memory 207336 kb
Host smart-b193fb08-40ca-4b6e-9e8a-f938b0151bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10837
22791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1083722791
Directory /workspace/3.usbdev_pkt_received/latest


Test location /workspace/coverage/default/3.usbdev_pkt_sent.2832763943
Short name T932
Test name
Test status
Simulation time 168958950 ps
CPU time 0.9 seconds
Started Aug 05 05:33:37 PM PDT 24
Finished Aug 05 05:33:38 PM PDT 24
Peak memory 207340 kb
Host smart-e575a844-8815-4981-b006-1ab1ab2eab60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28327
63943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2832763943
Directory /workspace/3.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.1467101885
Short name T1610
Test name
Test status
Simulation time 2787047215 ps
CPU time 22.66 seconds
Started Aug 05 05:33:47 PM PDT 24
Finished Aug 05 05:34:10 PM PDT 24
Peak memory 223924 kb
Host smart-900ee61d-9c44-435f-935e-b285fc329147
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467101885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.1467101885
Directory /workspace/3.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.562562807
Short name T166
Test name
Test status
Simulation time 3050062981 ps
CPU time 20.3 seconds
Started Aug 05 05:33:37 PM PDT 24
Finished Aug 05 05:33:58 PM PDT 24
Peak memory 223996 kb
Host smart-c19f03c0-81a6-4048-a408-71af34b0ca43
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=562562807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.562562807
Directory /workspace/3.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/3.usbdev_rand_suspends.4167930512
Short name T1893
Test name
Test status
Simulation time 8708468963 ps
CPU time 46.17 seconds
Started Aug 05 05:33:34 PM PDT 24
Finished Aug 05 05:34:20 PM PDT 24
Peak memory 224072 kb
Host smart-dbe741e7-3385-4ceb-9126-db8a6d923244
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167930512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.4167930512
Directory /workspace/3.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.4091695675
Short name T2786
Test name
Test status
Simulation time 269895014 ps
CPU time 1.04 seconds
Started Aug 05 05:33:35 PM PDT 24
Finished Aug 05 05:33:37 PM PDT 24
Peak memory 207364 kb
Host smart-1d371f02-047d-4756-ba3d-bcdc147dc47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40916
95675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.4091695675
Directory /workspace/3.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3735989044
Short name T2084
Test name
Test status
Simulation time 170443770 ps
CPU time 0.88 seconds
Started Aug 05 05:33:35 PM PDT 24
Finished Aug 05 05:33:36 PM PDT 24
Peak memory 207308 kb
Host smart-1009c8bd-cc8e-44d9-b710-4401b6c788b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37359
89044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3735989044
Directory /workspace/3.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/3.usbdev_resume_link_active.3097714465
Short name T1685
Test name
Test status
Simulation time 20238569445 ps
CPU time 23.96 seconds
Started Aug 05 05:33:36 PM PDT 24
Finished Aug 05 05:34:00 PM PDT 24
Peak memory 207312 kb
Host smart-f931269c-28ff-4eea-9be3-73069aacec8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30977
14465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.3097714465
Directory /workspace/3.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1450175386
Short name T2180
Test name
Test status
Simulation time 191130417 ps
CPU time 0.94 seconds
Started Aug 05 05:33:40 PM PDT 24
Finished Aug 05 05:33:41 PM PDT 24
Peak memory 207268 kb
Host smart-29c9a742-9c37-499c-9ea3-d67319f9a89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14501
75386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1450175386
Directory /workspace/3.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/3.usbdev_rx_full.2655921404
Short name T1316
Test name
Test status
Simulation time 252349272 ps
CPU time 1.09 seconds
Started Aug 05 05:33:36 PM PDT 24
Finished Aug 05 05:33:37 PM PDT 24
Peak memory 207228 kb
Host smart-9cd29669-d560-42ec-83f6-6b9fc034d8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26559
21404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.2655921404
Directory /workspace/3.usbdev_rx_full/latest


Test location /workspace/coverage/default/3.usbdev_rx_pid_err.1333373672
Short name T1914
Test name
Test status
Simulation time 150750377 ps
CPU time 0.89 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:33:40 PM PDT 24
Peak memory 207372 kb
Host smart-956eeeab-8aac-431f-97a1-a4b114e69522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13333
73672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.1333373672
Directory /workspace/3.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/3.usbdev_sec_cm.2256492203
Short name T202
Test name
Test status
Simulation time 762509714 ps
CPU time 1.71 seconds
Started Aug 05 05:33:41 PM PDT 24
Finished Aug 05 05:33:43 PM PDT 24
Peak memory 223316 kb
Host smart-c11db800-3c70-4b88-b4fc-6a52fe2701fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2256492203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2256492203
Directory /workspace/3.usbdev_sec_cm/latest


Test location /workspace/coverage/default/3.usbdev_setup_priority.733330477
Short name T2442
Test name
Test status
Simulation time 436379939 ps
CPU time 1.56 seconds
Started Aug 05 05:33:47 PM PDT 24
Finished Aug 05 05:33:49 PM PDT 24
Peak memory 207280 kb
Host smart-1acf9946-6eee-422e-90fa-704c1d47436e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73333
0477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.733330477
Directory /workspace/3.usbdev_setup_priority/latest


Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2185432502
Short name T183
Test name
Test status
Simulation time 173382268 ps
CPU time 0.94 seconds
Started Aug 05 05:33:40 PM PDT 24
Finished Aug 05 05:33:41 PM PDT 24
Peak memory 207352 kb
Host smart-8e364d95-5f0d-4785-872d-23c9710f0578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21854
32502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2185432502
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/3.usbdev_setup_stage.2173843807
Short name T522
Test name
Test status
Simulation time 150078459 ps
CPU time 0.88 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:33:40 PM PDT 24
Peak memory 207336 kb
Host smart-29a2106e-ac89-485f-8fa3-5310c102494e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21738
43807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2173843807
Directory /workspace/3.usbdev_setup_stage/latest


Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2014583455
Short name T2878
Test name
Test status
Simulation time 147941509 ps
CPU time 0.89 seconds
Started Aug 05 05:33:47 PM PDT 24
Finished Aug 05 05:33:48 PM PDT 24
Peak memory 207300 kb
Host smart-b167f3b8-34b3-4bf8-8e36-4ec708655c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20145
83455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2014583455
Directory /workspace/3.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/3.usbdev_smoke.828900045
Short name T2777
Test name
Test status
Simulation time 201792880 ps
CPU time 0.97 seconds
Started Aug 05 05:33:38 PM PDT 24
Finished Aug 05 05:33:39 PM PDT 24
Peak memory 207348 kb
Host smart-c1452186-e3cd-483e-b4ae-391143416370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82890
0045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.828900045
Directory /workspace/3.usbdev_smoke/latest


Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.2059480863
Short name T1895
Test name
Test status
Simulation time 1846097523 ps
CPU time 18.98 seconds
Started Aug 05 05:33:32 PM PDT 24
Finished Aug 05 05:33:51 PM PDT 24
Peak memory 216664 kb
Host smart-ca1dee2b-5722-44ca-9957-0ed13ba2abf3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2059480863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.2059480863
Directory /workspace/3.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.278510690
Short name T469
Test name
Test status
Simulation time 193344655 ps
CPU time 0.9 seconds
Started Aug 05 05:33:36 PM PDT 24
Finished Aug 05 05:33:37 PM PDT 24
Peak memory 207308 kb
Host smart-a0107611-1cac-4d65-a523-c76a54a13a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27851
0690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.278510690
Directory /workspace/3.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/3.usbdev_stall_trans.3365297727
Short name T815
Test name
Test status
Simulation time 195320629 ps
CPU time 0.9 seconds
Started Aug 05 05:33:40 PM PDT 24
Finished Aug 05 05:33:41 PM PDT 24
Peak memory 207268 kb
Host smart-fb449e16-6fff-4076-a47b-8330be13b6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33652
97727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3365297727
Directory /workspace/3.usbdev_stall_trans/latest


Test location /workspace/coverage/default/3.usbdev_stream_len_max.3229861339
Short name T1093
Test name
Test status
Simulation time 653726396 ps
CPU time 1.85 seconds
Started Aug 05 05:33:38 PM PDT 24
Finished Aug 05 05:33:40 PM PDT 24
Peak memory 207292 kb
Host smart-aa23c82f-03e9-4715-a0fe-bb83518f9419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32298
61339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3229861339
Directory /workspace/3.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/3.usbdev_streaming_out.158556297
Short name T951
Test name
Test status
Simulation time 2013348471 ps
CPU time 59.3 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:34:38 PM PDT 24
Peak memory 217020 kb
Host smart-bb3a1b43-df59-4c52-aec3-4e9624575e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15855
6297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.158556297
Directory /workspace/3.usbdev_streaming_out/latest


Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.3333446718
Short name T1648
Test name
Test status
Simulation time 193935331 ps
CPU time 0.96 seconds
Started Aug 05 05:33:28 PM PDT 24
Finished Aug 05 05:33:29 PM PDT 24
Peak memory 207400 kb
Host smart-77d1b3f9-8ad5-4678-a48a-6f75c3210079
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333446718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.3333446718
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/30.usbdev_alert_test.3083502190
Short name T1588
Test name
Test status
Simulation time 47909247 ps
CPU time 0.66 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:37:53 PM PDT 24
Peak memory 207380 kb
Host smart-3ffebea2-2abc-4a4e-abfb-3b8509d797fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3083502190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3083502190
Directory /workspace/30.usbdev_alert_test/latest


Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3134666621
Short name T1946
Test name
Test status
Simulation time 6905162735 ps
CPU time 9.7 seconds
Started Aug 05 05:37:52 PM PDT 24
Finished Aug 05 05:38:02 PM PDT 24
Peak memory 215852 kb
Host smart-bbfb3502-f44f-482f-a6fd-15c2c86026a7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134666621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.3134666621
Directory /workspace/30.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.4003354707
Short name T2223
Test name
Test status
Simulation time 20585443635 ps
CPU time 23.53 seconds
Started Aug 05 05:37:55 PM PDT 24
Finished Aug 05 05:38:19 PM PDT 24
Peak memory 207496 kb
Host smart-93e969cb-14ad-44d8-a3c7-7f1119f975cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003354707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.4003354707
Directory /workspace/30.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2834716508
Short name T1677
Test name
Test status
Simulation time 24655443059 ps
CPU time 31.12 seconds
Started Aug 05 05:37:44 PM PDT 24
Finished Aug 05 05:38:16 PM PDT 24
Peak memory 215816 kb
Host smart-4fde4782-4766-4f13-8512-23fba302f044
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834716508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.2834716508
Directory /workspace/30.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/30.usbdev_av_buffer.2198967451
Short name T2287
Test name
Test status
Simulation time 155109811 ps
CPU time 0.87 seconds
Started Aug 05 05:37:44 PM PDT 24
Finished Aug 05 05:37:45 PM PDT 24
Peak memory 207372 kb
Host smart-947561c1-b3e1-4da2-bc25-47904a211f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21989
67451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2198967451
Directory /workspace/30.usbdev_av_buffer/latest


Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2197302053
Short name T1114
Test name
Test status
Simulation time 185045181 ps
CPU time 0.9 seconds
Started Aug 05 05:37:50 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207236 kb
Host smart-180cdf49-3989-4c52-ba52-9d7b96c8358a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21973
02053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2197302053
Directory /workspace/30.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3888771362
Short name T1306
Test name
Test status
Simulation time 513941888 ps
CPU time 1.61 seconds
Started Aug 05 05:37:45 PM PDT 24
Finished Aug 05 05:37:46 PM PDT 24
Peak memory 207376 kb
Host smart-530d74a6-7d59-4083-9d26-d5cbd2df3bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38887
71362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3888771362
Directory /workspace/30.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.234947594
Short name T891
Test name
Test status
Simulation time 655159645 ps
CPU time 1.93 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:37:55 PM PDT 24
Peak memory 207524 kb
Host smart-0d4b1e2e-66c4-471d-b0ad-627b12e59ea8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=234947594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.234947594
Directory /workspace/30.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/30.usbdev_device_address.2638748463
Short name T172
Test name
Test status
Simulation time 37302774828 ps
CPU time 62.73 seconds
Started Aug 05 05:37:44 PM PDT 24
Finished Aug 05 05:38:47 PM PDT 24
Peak memory 207712 kb
Host smart-9a1b40ca-db94-42a4-b652-0600edb985af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26387
48463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.2638748463
Directory /workspace/30.usbdev_device_address/latest


Test location /workspace/coverage/default/30.usbdev_device_timeout.4021825157
Short name T1827
Test name
Test status
Simulation time 1847204015 ps
CPU time 44.4 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:38:31 PM PDT 24
Peak memory 207456 kb
Host smart-ee55b7db-a1da-46a2-84d2-ac79ed116e17
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021825157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.4021825157
Directory /workspace/30.usbdev_device_timeout/latest


Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3077408624
Short name T2423
Test name
Test status
Simulation time 950072935 ps
CPU time 2.13 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207288 kb
Host smart-63129ffb-5465-4d80-b6ad-2d909ddaa030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30774
08624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3077408624
Directory /workspace/30.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/30.usbdev_disconnected.3757956858
Short name T1465
Test name
Test status
Simulation time 141877453 ps
CPU time 0.83 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207372 kb
Host smart-000d737a-137d-46a6-a0b3-b692eeba92cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37579
56858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3757956858
Directory /workspace/30.usbdev_disconnected/latest


Test location /workspace/coverage/default/30.usbdev_enable.1260016333
Short name T2543
Test name
Test status
Simulation time 68324442 ps
CPU time 0.78 seconds
Started Aug 05 05:37:49 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 207228 kb
Host smart-9c2753ef-a6c0-4429-a7cf-e3af338ec332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12600
16333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1260016333
Directory /workspace/30.usbdev_enable/latest


Test location /workspace/coverage/default/30.usbdev_endpoint_access.1320571378
Short name T807
Test name
Test status
Simulation time 937463554 ps
CPU time 2.28 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:54 PM PDT 24
Peak memory 207600 kb
Host smart-520715dd-30a0-4ca2-9952-ed9f55061dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13205
71378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1320571378
Directory /workspace/30.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/30.usbdev_endpoint_types.878925490
Short name T405
Test name
Test status
Simulation time 428145047 ps
CPU time 1.41 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207264 kb
Host smart-03418273-1c3c-4708-b6ed-23c2c3b572da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=878925490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.878925490
Directory /workspace/30.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/30.usbdev_fifo_rst.238375929
Short name T805
Test name
Test status
Simulation time 218540065 ps
CPU time 1.69 seconds
Started Aug 05 05:37:55 PM PDT 24
Finished Aug 05 05:37:56 PM PDT 24
Peak memory 207532 kb
Host smart-406f285e-20a4-4684-82a5-aedcd409a626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23837
5929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.238375929
Directory /workspace/30.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/30.usbdev_in_iso.2419905094
Short name T1463
Test name
Test status
Simulation time 211671447 ps
CPU time 1.07 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207580 kb
Host smart-825a4df3-16e0-4c9f-b7e4-08bbd15eaa93
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2419905094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2419905094
Directory /workspace/30.usbdev_in_iso/latest


Test location /workspace/coverage/default/30.usbdev_in_stall.2647141556
Short name T3120
Test name
Test status
Simulation time 166054642 ps
CPU time 0.9 seconds
Started Aug 05 05:37:45 PM PDT 24
Finished Aug 05 05:37:46 PM PDT 24
Peak memory 207196 kb
Host smart-cce04432-7baf-47f0-a6e1-f144aa3cf784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26471
41556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2647141556
Directory /workspace/30.usbdev_in_stall/latest


Test location /workspace/coverage/default/30.usbdev_in_trans.2982215298
Short name T760
Test name
Test status
Simulation time 256813743 ps
CPU time 1.08 seconds
Started Aug 05 05:37:49 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 207392 kb
Host smart-2f06550c-476d-4e23-89dc-4f117471aa4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29822
15298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2982215298
Directory /workspace/30.usbdev_in_trans/latest


Test location /workspace/coverage/default/30.usbdev_invalid_sync.3305956743
Short name T969
Test name
Test status
Simulation time 3338136521 ps
CPU time 35.32 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:38:21 PM PDT 24
Peak memory 218292 kb
Host smart-f42161e4-1b20-4ec3-90ff-40b37bef4af2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3305956743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.3305956743
Directory /workspace/30.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/30.usbdev_iso_retraction.1739252233
Short name T2387
Test name
Test status
Simulation time 5755031224 ps
CPU time 41.4 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 207648 kb
Host smart-c8e99e76-42c3-4e2b-aa01-261c2586077a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1739252233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.1739252233
Directory /workspace/30.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/30.usbdev_link_in_err.952109838
Short name T767
Test name
Test status
Simulation time 205069055 ps
CPU time 0.92 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207368 kb
Host smart-28141175-72d7-4ab2-8473-80343dd37f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95210
9838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.952109838
Directory /workspace/30.usbdev_link_in_err/latest


Test location /workspace/coverage/default/30.usbdev_link_resume.1173668525
Short name T107
Test name
Test status
Simulation time 29043623979 ps
CPU time 33.1 seconds
Started Aug 05 05:37:59 PM PDT 24
Finished Aug 05 05:38:32 PM PDT 24
Peak memory 215780 kb
Host smart-7579f469-fb7b-4077-8038-74c7609ffeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11736
68525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.1173668525
Directory /workspace/30.usbdev_link_resume/latest


Test location /workspace/coverage/default/30.usbdev_link_suspend.969970628
Short name T745
Test name
Test status
Simulation time 10444576333 ps
CPU time 13.39 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:38:00 PM PDT 24
Peak memory 207564 kb
Host smart-44278084-64c3-49a4-b8a7-5eaddee14ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96997
0628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.969970628
Directory /workspace/30.usbdev_link_suspend/latest


Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1372471320
Short name T2462
Test name
Test status
Simulation time 4406745758 ps
CPU time 131.07 seconds
Started Aug 05 05:37:56 PM PDT 24
Finished Aug 05 05:40:07 PM PDT 24
Peak memory 218268 kb
Host smart-07a063c5-d70a-4cb9-948f-d5dfdc5961b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13724
71320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1372471320
Directory /workspace/30.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.3343998269
Short name T2285
Test name
Test status
Simulation time 1902558703 ps
CPU time 19.29 seconds
Started Aug 05 05:37:51 PM PDT 24
Finished Aug 05 05:38:10 PM PDT 24
Peak memory 223820 kb
Host smart-342782ca-4bc1-438d-9b30-3fc5ea5bbbdb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3343998269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.3343998269
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.3341683524
Short name T569
Test name
Test status
Simulation time 247249129 ps
CPU time 1.04 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 207348 kb
Host smart-86b9a924-1244-47a5-8dd4-e6ce8274f8a1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3341683524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.3341683524
Directory /workspace/30.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.4179932075
Short name T1527
Test name
Test status
Simulation time 229392225 ps
CPU time 0.99 seconds
Started Aug 05 05:37:54 PM PDT 24
Finished Aug 05 05:37:55 PM PDT 24
Peak memory 207352 kb
Host smart-d9da3ba9-542f-4544-ac7c-42bbf83304c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41799
32075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.4179932075
Directory /workspace/30.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.4167473942
Short name T1392
Test name
Test status
Simulation time 3046605770 ps
CPU time 91.7 seconds
Started Aug 05 05:37:57 PM PDT 24
Finished Aug 05 05:39:29 PM PDT 24
Peak memory 217360 kb
Host smart-eddc4d7e-7c95-4f19-ad8d-4044150581dc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4167473942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.4167473942
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3162191823
Short name T496
Test name
Test status
Simulation time 172741665 ps
CPU time 0.89 seconds
Started Aug 05 05:37:50 PM PDT 24
Finished Aug 05 05:37:51 PM PDT 24
Peak memory 207352 kb
Host smart-2863255b-129c-4905-983c-01e7f6a6756c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3162191823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3162191823
Directory /workspace/30.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.311309246
Short name T1113
Test name
Test status
Simulation time 153362966 ps
CPU time 0.88 seconds
Started Aug 05 05:37:51 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207316 kb
Host smart-058d17dc-f27f-4593-a919-e4d9a985f25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31130
9246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.311309246
Directory /workspace/30.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/30.usbdev_nak_trans.4204761167
Short name T2005
Test name
Test status
Simulation time 212686246 ps
CPU time 0.96 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207364 kb
Host smart-e013d364-dcc8-47dd-93de-3f8e4ed80f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42047
61167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.4204761167
Directory /workspace/30.usbdev_nak_trans/latest


Test location /workspace/coverage/default/30.usbdev_out_iso.4293218989
Short name T2819
Test name
Test status
Simulation time 162870922 ps
CPU time 0.85 seconds
Started Aug 05 05:38:19 PM PDT 24
Finished Aug 05 05:38:20 PM PDT 24
Peak memory 207372 kb
Host smart-5c02082b-1a0d-4259-b378-76d30658dd74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42932
18989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.4293218989
Directory /workspace/30.usbdev_out_iso/latest


Test location /workspace/coverage/default/30.usbdev_out_stall.1738046604
Short name T1301
Test name
Test status
Simulation time 159079610 ps
CPU time 0.86 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207416 kb
Host smart-d6ed62a6-a013-4bb0-acf8-03c91ba650c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17380
46604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1738046604
Directory /workspace/30.usbdev_out_stall/latest


Test location /workspace/coverage/default/30.usbdev_out_trans_nak.785196818
Short name T1647
Test name
Test status
Simulation time 162097999 ps
CPU time 0.86 seconds
Started Aug 05 05:37:50 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207268 kb
Host smart-e862e87b-f8be-4578-b2ef-1e8bd73d761a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78519
6818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.785196818
Directory /workspace/30.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3426375081
Short name T839
Test name
Test status
Simulation time 198199726 ps
CPU time 0.91 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 207324 kb
Host smart-36066c73-aacb-4eff-8aeb-b731c13e60a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34263
75081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3426375081
Directory /workspace/30.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.3537952885
Short name T106
Test name
Test status
Simulation time 277265657 ps
CPU time 1.07 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207352 kb
Host smart-e0b745cf-7cc6-4fe6-86fc-37691b3a2a76
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3537952885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.3537952885
Directory /workspace/30.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3131126185
Short name T1928
Test name
Test status
Simulation time 153727462 ps
CPU time 0.85 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:37:54 PM PDT 24
Peak memory 207320 kb
Host smart-e335e897-0afc-4149-8fe5-f32d1451f782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31311
26185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3131126185
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2391383925
Short name T1791
Test name
Test status
Simulation time 80637047 ps
CPU time 0.77 seconds
Started Aug 05 05:37:54 PM PDT 24
Finished Aug 05 05:37:55 PM PDT 24
Peak memory 207276 kb
Host smart-d362d56b-81a6-4a49-8c88-6c39bdbc81b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23913
83925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2391383925
Directory /workspace/30.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1313994591
Short name T275
Test name
Test status
Simulation time 17889493735 ps
CPU time 48.31 seconds
Started Aug 05 05:37:49 PM PDT 24
Finished Aug 05 05:38:38 PM PDT 24
Peak memory 215840 kb
Host smart-ff97d16b-22fe-4b68-9678-778825e0eb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13139
94591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1313994591
Directory /workspace/30.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/30.usbdev_pkt_received.2518003887
Short name T308
Test name
Test status
Simulation time 193468223 ps
CPU time 0.96 seconds
Started Aug 05 05:37:54 PM PDT 24
Finished Aug 05 05:37:55 PM PDT 24
Peak memory 207284 kb
Host smart-54b9d374-cbbd-4d0e-a806-ba7887c2d753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25180
03887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2518003887
Directory /workspace/30.usbdev_pkt_received/latest


Test location /workspace/coverage/default/30.usbdev_pkt_sent.3599902111
Short name T2597
Test name
Test status
Simulation time 182796079 ps
CPU time 0.87 seconds
Started Aug 05 05:37:52 PM PDT 24
Finished Aug 05 05:37:53 PM PDT 24
Peak memory 207244 kb
Host smart-fac9430e-9e50-4b83-b347-1b23f4b16b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35999
02111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3599902111
Directory /workspace/30.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3099005182
Short name T1411
Test name
Test status
Simulation time 179242964 ps
CPU time 0.9 seconds
Started Aug 05 05:37:50 PM PDT 24
Finished Aug 05 05:37:51 PM PDT 24
Peak memory 207340 kb
Host smart-ca9ec1ef-23a2-47cd-ab8e-f66ecd74ea84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30990
05182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3099005182
Directory /workspace/30.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.1233616930
Short name T3077
Test name
Test status
Simulation time 162375438 ps
CPU time 0.91 seconds
Started Aug 05 05:37:51 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207348 kb
Host smart-7120ed26-3670-43b2-8b59-56f18df7d323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12336
16930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1233616930
Directory /workspace/30.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1881067402
Short name T842
Test name
Test status
Simulation time 137716969 ps
CPU time 0.8 seconds
Started Aug 05 05:37:57 PM PDT 24
Finished Aug 05 05:37:58 PM PDT 24
Peak memory 207332 kb
Host smart-ecffd989-897d-45a4-9904-91d12ccc716a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18810
67402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1881067402
Directory /workspace/30.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/30.usbdev_rx_full.599402199
Short name T1565
Test name
Test status
Simulation time 347493241 ps
CPU time 1.2 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207376 kb
Host smart-44e61f40-b7aa-48a1-9539-c82a9fcc0531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59940
2199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.599402199
Directory /workspace/30.usbdev_rx_full/latest


Test location /workspace/coverage/default/30.usbdev_setup_stage.3636223728
Short name T990
Test name
Test status
Simulation time 154993793 ps
CPU time 0.81 seconds
Started Aug 05 05:37:52 PM PDT 24
Finished Aug 05 05:37:53 PM PDT 24
Peak memory 207304 kb
Host smart-beaf6719-ad1f-4bbf-b86a-dedd2e921315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36362
23728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3636223728
Directory /workspace/30.usbdev_setup_stage/latest


Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1759577168
Short name T1632
Test name
Test status
Simulation time 158388422 ps
CPU time 0.86 seconds
Started Aug 05 05:38:08 PM PDT 24
Finished Aug 05 05:38:09 PM PDT 24
Peak memory 207312 kb
Host smart-48e90780-a06b-4cd5-8444-e10d88c16a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17595
77168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1759577168
Directory /workspace/30.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/30.usbdev_smoke.2105688673
Short name T2026
Test name
Test status
Simulation time 239600957 ps
CPU time 1.1 seconds
Started Aug 05 05:37:47 PM PDT 24
Finished Aug 05 05:37:48 PM PDT 24
Peak memory 207400 kb
Host smart-772909fc-6880-4045-ba3b-e1a76cf24a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21056
88673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2105688673
Directory /workspace/30.usbdev_smoke/latest


Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.739508265
Short name T2769
Test name
Test status
Simulation time 1954502432 ps
CPU time 59.24 seconds
Started Aug 05 05:38:16 PM PDT 24
Finished Aug 05 05:39:16 PM PDT 24
Peak memory 217156 kb
Host smart-f61b135b-df89-480f-b375-4174e313f051
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=739508265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.739508265
Directory /workspace/30.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3033180134
Short name T727
Test name
Test status
Simulation time 203020522 ps
CPU time 0.97 seconds
Started Aug 05 05:37:49 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 207380 kb
Host smart-6ae09b9a-f010-4621-877e-8820b7bc3a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30331
80134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3033180134
Directory /workspace/30.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/30.usbdev_stall_trans.346622479
Short name T2186
Test name
Test status
Simulation time 176519744 ps
CPU time 0.9 seconds
Started Aug 05 05:37:48 PM PDT 24
Finished Aug 05 05:37:49 PM PDT 24
Peak memory 207352 kb
Host smart-d6751b81-c863-44fa-b67c-fce4cf81fbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34662
2479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.346622479
Directory /workspace/30.usbdev_stall_trans/latest


Test location /workspace/coverage/default/30.usbdev_stream_len_max.3809712783
Short name T1909
Test name
Test status
Simulation time 989159357 ps
CPU time 2.47 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:37:55 PM PDT 24
Peak memory 207568 kb
Host smart-d46c185d-eaff-4ef2-b41e-039e2c076fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38097
12783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3809712783
Directory /workspace/30.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/30.usbdev_streaming_out.42957405
Short name T100
Test name
Test status
Simulation time 2656502848 ps
CPU time 27.59 seconds
Started Aug 05 05:37:51 PM PDT 24
Finished Aug 05 05:38:19 PM PDT 24
Peak memory 215808 kb
Host smart-d28b743f-3093-4d5c-9c98-43eba55e2072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42957
405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.42957405
Directory /workspace/30.usbdev_streaming_out/latest


Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.1818031296
Short name T2347
Test name
Test status
Simulation time 3417061756 ps
CPU time 28.48 seconds
Started Aug 05 05:37:46 PM PDT 24
Finished Aug 05 05:38:15 PM PDT 24
Peak memory 207684 kb
Host smart-09ec64d5-23b8-4b5b-9ed2-567486c35588
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818031296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.1818031296
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/31.usbdev_alert_test.3319507482
Short name T1184
Test name
Test status
Simulation time 50346017 ps
CPU time 0.7 seconds
Started Aug 05 05:38:22 PM PDT 24
Finished Aug 05 05:38:22 PM PDT 24
Peak memory 207360 kb
Host smart-96b00c15-8161-4519-9395-9ca47235fbc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3319507482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.3319507482
Directory /workspace/31.usbdev_alert_test/latest


Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.27492726
Short name T2224
Test name
Test status
Simulation time 10298243517 ps
CPU time 11.98 seconds
Started Aug 05 05:37:52 PM PDT 24
Finished Aug 05 05:38:04 PM PDT 24
Peak memory 207612 kb
Host smart-618b0775-7dc1-46f8-bb66-fdddbc30d2db
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27492726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon
_wake_disconnect.27492726
Directory /workspace/31.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3490697746
Short name T1468
Test name
Test status
Simulation time 15189059945 ps
CPU time 19.23 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:38:13 PM PDT 24
Peak memory 215792 kb
Host smart-a22a0fa8-5f78-4ecb-9cdb-be07b8ce06e6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490697746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3490697746
Directory /workspace/31.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.4066594927
Short name T1926
Test name
Test status
Simulation time 29457049977 ps
CPU time 37 seconds
Started Aug 05 05:37:51 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 207648 kb
Host smart-7aa9a094-1d1f-44ed-9b7e-cbcc88375a44
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066594927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.4066594927
Directory /workspace/31.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/31.usbdev_av_buffer.1529344795
Short name T2796
Test name
Test status
Simulation time 190953477 ps
CPU time 0.95 seconds
Started Aug 05 05:38:02 PM PDT 24
Finished Aug 05 05:38:03 PM PDT 24
Peak memory 207320 kb
Host smart-daf09338-919c-43a7-b259-a0a7f2fb8e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15293
44795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1529344795
Directory /workspace/31.usbdev_av_buffer/latest


Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3592178936
Short name T1657
Test name
Test status
Simulation time 141399162 ps
CPU time 0.91 seconds
Started Aug 05 05:37:49 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 207244 kb
Host smart-fc3bbe5e-3695-472a-ad65-ff7b9b92cf51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35921
78936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3592178936
Directory /workspace/31.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3209450131
Short name T871
Test name
Test status
Simulation time 274287414 ps
CPU time 1.11 seconds
Started Aug 05 05:38:05 PM PDT 24
Finished Aug 05 05:38:06 PM PDT 24
Peak memory 207376 kb
Host smart-4bb61990-ee64-4f15-adcb-6a018f06922d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32094
50131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3209450131
Directory /workspace/31.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.4263166464
Short name T2754
Test name
Test status
Simulation time 769783302 ps
CPU time 2.19 seconds
Started Aug 05 05:38:05 PM PDT 24
Finished Aug 05 05:38:07 PM PDT 24
Peak memory 207536 kb
Host smart-30a4a572-ca46-4d5c-b011-e8b962b07a83
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4263166464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.4263166464
Directory /workspace/31.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/31.usbdev_device_timeout.2464463853
Short name T2218
Test name
Test status
Simulation time 2020767902 ps
CPU time 18.5 seconds
Started Aug 05 05:37:55 PM PDT 24
Finished Aug 05 05:38:13 PM PDT 24
Peak memory 207576 kb
Host smart-f87d614d-0666-4e05-b41f-71fe61a82b11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464463853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.2464463853
Directory /workspace/31.usbdev_device_timeout/latest


Test location /workspace/coverage/default/31.usbdev_disable_endpoint.27692070
Short name T2018
Test name
Test status
Simulation time 638214465 ps
CPU time 1.84 seconds
Started Aug 05 05:37:54 PM PDT 24
Finished Aug 05 05:37:56 PM PDT 24
Peak memory 207372 kb
Host smart-7c17869a-3745-47d3-bb0c-3bfb7a927e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27692
070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.27692070
Directory /workspace/31.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/31.usbdev_disconnected.4185684921
Short name T1798
Test name
Test status
Simulation time 153917245 ps
CPU time 0.82 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:08 PM PDT 24
Peak memory 207320 kb
Host smart-947c0e70-c3aa-4094-ae81-f17787372918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41856
84921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.4185684921
Directory /workspace/31.usbdev_disconnected/latest


Test location /workspace/coverage/default/31.usbdev_enable.3574586690
Short name T2080
Test name
Test status
Simulation time 35866225 ps
CPU time 0.75 seconds
Started Aug 05 05:37:51 PM PDT 24
Finished Aug 05 05:37:52 PM PDT 24
Peak memory 207276 kb
Host smart-c89faf42-023e-4e2f-8689-3619e5b3db31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35745
86690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3574586690
Directory /workspace/31.usbdev_enable/latest


Test location /workspace/coverage/default/31.usbdev_endpoint_access.1151865326
Short name T2585
Test name
Test status
Simulation time 826972024 ps
CPU time 2.33 seconds
Started Aug 05 05:37:58 PM PDT 24
Finished Aug 05 05:38:00 PM PDT 24
Peak memory 207656 kb
Host smart-c56a2a3c-41ce-4959-824e-afc886a64c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11518
65326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1151865326
Directory /workspace/31.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/31.usbdev_endpoint_types.1972003706
Short name T1386
Test name
Test status
Simulation time 176377661 ps
CPU time 0.92 seconds
Started Aug 05 05:37:57 PM PDT 24
Finished Aug 05 05:37:58 PM PDT 24
Peak memory 207292 kb
Host smart-4832f1f5-a5d2-4725-905d-59b1b787287b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1972003706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.1972003706
Directory /workspace/31.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/31.usbdev_fifo_rst.2524595395
Short name T2174
Test name
Test status
Simulation time 171011008 ps
CPU time 1.52 seconds
Started Aug 05 05:37:57 PM PDT 24
Finished Aug 05 05:37:58 PM PDT 24
Peak memory 207452 kb
Host smart-f8c308eb-b86b-4362-a469-4c518c5774e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245
95395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2524595395
Directory /workspace/31.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/31.usbdev_in_iso.2550896941
Short name T1519
Test name
Test status
Simulation time 230808524 ps
CPU time 1.24 seconds
Started Aug 05 05:37:52 PM PDT 24
Finished Aug 05 05:37:53 PM PDT 24
Peak memory 215740 kb
Host smart-6527b4e3-2bd6-46ce-88a6-6b674b6252eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2550896941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2550896941
Directory /workspace/31.usbdev_in_iso/latest


Test location /workspace/coverage/default/31.usbdev_in_stall.1842922860
Short name T2340
Test name
Test status
Simulation time 135605308 ps
CPU time 0.8 seconds
Started Aug 05 05:37:50 PM PDT 24
Finished Aug 05 05:37:50 PM PDT 24
Peak memory 207384 kb
Host smart-0937f558-ecf7-4911-be7e-f89b761caaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18429
22860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1842922860
Directory /workspace/31.usbdev_in_stall/latest


Test location /workspace/coverage/default/31.usbdev_in_trans.2468731826
Short name T2902
Test name
Test status
Simulation time 220083265 ps
CPU time 0.94 seconds
Started Aug 05 05:38:06 PM PDT 24
Finished Aug 05 05:38:07 PM PDT 24
Peak memory 207348 kb
Host smart-f054a4fa-2c6c-4b07-ad8d-4996b2a45136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24687
31826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2468731826
Directory /workspace/31.usbdev_in_trans/latest


Test location /workspace/coverage/default/31.usbdev_invalid_sync.4292761664
Short name T1813
Test name
Test status
Simulation time 3248754502 ps
CPU time 92.55 seconds
Started Aug 05 05:37:57 PM PDT 24
Finished Aug 05 05:39:30 PM PDT 24
Peak memory 218232 kb
Host smart-dbd6019c-d8fa-44bd-810d-fa0981fdf5b2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4292761664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.4292761664
Directory /workspace/31.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/31.usbdev_iso_retraction.2000299092
Short name T2181
Test name
Test status
Simulation time 4600939076 ps
CPU time 33.74 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:38:27 PM PDT 24
Peak memory 207568 kb
Host smart-195e1250-2559-4b68-a091-ff0c3120560d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2000299092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.2000299092
Directory /workspace/31.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/31.usbdev_link_in_err.3992013150
Short name T1277
Test name
Test status
Simulation time 266803757 ps
CPU time 1.01 seconds
Started Aug 05 05:38:05 PM PDT 24
Finished Aug 05 05:38:06 PM PDT 24
Peak memory 207364 kb
Host smart-f8d964f2-55f8-4b9c-bb1a-fc607bd404fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39920
13150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3992013150
Directory /workspace/31.usbdev_link_in_err/latest


Test location /workspace/coverage/default/31.usbdev_link_resume.890880710
Short name T970
Test name
Test status
Simulation time 31743599000 ps
CPU time 43.91 seconds
Started Aug 05 05:38:09 PM PDT 24
Finished Aug 05 05:38:53 PM PDT 24
Peak memory 207528 kb
Host smart-babb89a5-9e87-4935-b45c-fe683767134c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89088
0710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.890880710
Directory /workspace/31.usbdev_link_resume/latest


Test location /workspace/coverage/default/31.usbdev_link_suspend.1791818826
Short name T2976
Test name
Test status
Simulation time 9835984731 ps
CPU time 12.01 seconds
Started Aug 05 05:38:11 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 207612 kb
Host smart-44ac6c21-3941-4079-85d1-b4d46f9f5635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17918
18826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1791818826
Directory /workspace/31.usbdev_link_suspend/latest


Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.206186127
Short name T787
Test name
Test status
Simulation time 2376273324 ps
CPU time 66.91 seconds
Started Aug 05 05:38:09 PM PDT 24
Finished Aug 05 05:39:16 PM PDT 24
Peak memory 215864 kb
Host smart-93c73767-2f7c-466d-be4e-f46be71c8d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20618
6127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.206186127
Directory /workspace/31.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1167304279
Short name T1832
Test name
Test status
Simulation time 1617846987 ps
CPU time 15.61 seconds
Started Aug 05 05:37:54 PM PDT 24
Finished Aug 05 05:38:10 PM PDT 24
Peak memory 216968 kb
Host smart-67a6f6ad-129f-4052-afe4-7474f9e19a22
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1167304279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1167304279
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2863416410
Short name T885
Test name
Test status
Simulation time 239819725 ps
CPU time 1.01 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:38:11 PM PDT 24
Peak memory 207296 kb
Host smart-8a578d97-3cc5-4f3f-9064-3d1205ca314f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2863416410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2863416410
Directory /workspace/31.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2245494101
Short name T571
Test name
Test status
Simulation time 215800144 ps
CPU time 0.98 seconds
Started Aug 05 05:38:11 PM PDT 24
Finished Aug 05 05:38:12 PM PDT 24
Peak memory 207344 kb
Host smart-f07db08e-dc50-419f-9efe-fafe10fb3025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22454
94101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2245494101
Directory /workspace/31.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3762318493
Short name T757
Test name
Test status
Simulation time 2509786269 ps
CPU time 18.91 seconds
Started Aug 05 05:37:54 PM PDT 24
Finished Aug 05 05:38:13 PM PDT 24
Peak memory 217432 kb
Host smart-99b5927e-4441-4153-b9bd-50169c61d78c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3762318493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3762318493
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.4220900330
Short name T588
Test name
Test status
Simulation time 150987230 ps
CPU time 0.87 seconds
Started Aug 05 05:38:06 PM PDT 24
Finished Aug 05 05:38:07 PM PDT 24
Peak memory 207380 kb
Host smart-099b860c-ebc5-4269-a3c0-f3b9fad6a864
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4220900330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.4220900330
Directory /workspace/31.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1425199642
Short name T604
Test name
Test status
Simulation time 207134699 ps
CPU time 0.9 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:38:11 PM PDT 24
Peak memory 207368 kb
Host smart-c24a99ff-be8e-450f-a4e8-6140e81da721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14251
99642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1425199642
Directory /workspace/31.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/31.usbdev_nak_trans.2161263320
Short name T917
Test name
Test status
Simulation time 187748954 ps
CPU time 0.9 seconds
Started Aug 05 05:38:06 PM PDT 24
Finished Aug 05 05:38:07 PM PDT 24
Peak memory 207368 kb
Host smart-d79686cb-a8cb-47e4-91fc-bb622bcf7079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21612
63320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2161263320
Directory /workspace/31.usbdev_nak_trans/latest


Test location /workspace/coverage/default/31.usbdev_out_iso.3046394666
Short name T2416
Test name
Test status
Simulation time 193414690 ps
CPU time 0.96 seconds
Started Aug 05 05:38:06 PM PDT 24
Finished Aug 05 05:38:07 PM PDT 24
Peak memory 207348 kb
Host smart-91f52c39-16bf-4dc5-82ce-5568b3f1106f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30463
94666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3046394666
Directory /workspace/31.usbdev_out_iso/latest


Test location /workspace/coverage/default/31.usbdev_out_stall.470698273
Short name T2474
Test name
Test status
Simulation time 167441985 ps
CPU time 0.86 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:08 PM PDT 24
Peak memory 207428 kb
Host smart-a637baac-d7c9-40f8-8a01-864462382b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47069
8273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.470698273
Directory /workspace/31.usbdev_out_stall/latest


Test location /workspace/coverage/default/31.usbdev_out_trans_nak.4003909327
Short name T936
Test name
Test status
Simulation time 152841598 ps
CPU time 0.79 seconds
Started Aug 05 05:37:57 PM PDT 24
Finished Aug 05 05:37:58 PM PDT 24
Peak memory 207292 kb
Host smart-eb19cee7-6138-423d-bbd7-a102351d86c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40039
09327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.4003909327
Directory /workspace/31.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2693245403
Short name T1867
Test name
Test status
Simulation time 155284034 ps
CPU time 0.86 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:38:11 PM PDT 24
Peak memory 207292 kb
Host smart-0e989a3e-4c6f-451e-b520-ba06f8a1d180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26932
45403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2693245403
Directory /workspace/31.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.2188622101
Short name T1429
Test name
Test status
Simulation time 237128936 ps
CPU time 1.02 seconds
Started Aug 05 05:38:03 PM PDT 24
Finished Aug 05 05:38:04 PM PDT 24
Peak memory 207324 kb
Host smart-4de54c7c-ee55-4758-8c82-881b54d9bde3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2188622101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.2188622101
Directory /workspace/31.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.921580466
Short name T612
Test name
Test status
Simulation time 168763788 ps
CPU time 0.88 seconds
Started Aug 05 05:38:01 PM PDT 24
Finished Aug 05 05:38:02 PM PDT 24
Peak memory 207372 kb
Host smart-ccf21e75-3800-4734-8030-688e73bd7ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92158
0466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.921580466
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3205340213
Short name T893
Test name
Test status
Simulation time 42669598 ps
CPU time 0.75 seconds
Started Aug 05 05:38:06 PM PDT 24
Finished Aug 05 05:38:07 PM PDT 24
Peak memory 207304 kb
Host smart-767a4329-1005-42d1-ada3-17410daddb49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32053
40213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3205340213
Directory /workspace/31.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2385608681
Short name T247
Test name
Test status
Simulation time 12804014156 ps
CPU time 32.57 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:40 PM PDT 24
Peak memory 215840 kb
Host smart-fb3eebda-de2f-4f41-a2e4-aa512b51a652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23856
08681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2385608681
Directory /workspace/31.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/31.usbdev_pkt_received.3460791460
Short name T2862
Test name
Test status
Simulation time 181217527 ps
CPU time 0.94 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:38:11 PM PDT 24
Peak memory 207400 kb
Host smart-9523b869-0ff8-498e-bc8b-781c3d05b16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34607
91460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3460791460
Directory /workspace/31.usbdev_pkt_received/latest


Test location /workspace/coverage/default/31.usbdev_pkt_sent.1832300124
Short name T671
Test name
Test status
Simulation time 172921165 ps
CPU time 0.88 seconds
Started Aug 05 05:38:05 PM PDT 24
Finished Aug 05 05:38:06 PM PDT 24
Peak memory 207332 kb
Host smart-1e64e8c2-3bb0-4924-8c47-4b8451ee44ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18323
00124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1832300124
Directory /workspace/31.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2347767833
Short name T1576
Test name
Test status
Simulation time 253590428 ps
CPU time 0.99 seconds
Started Aug 05 05:38:06 PM PDT 24
Finished Aug 05 05:38:07 PM PDT 24
Peak memory 207432 kb
Host smart-61a7e583-cf13-4a11-971a-1e7925064482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23477
67833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2347767833
Directory /workspace/31.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.1790599644
Short name T2194
Test name
Test status
Simulation time 161258908 ps
CPU time 0.87 seconds
Started Aug 05 05:38:02 PM PDT 24
Finished Aug 05 05:38:03 PM PDT 24
Peak memory 207324 kb
Host smart-581656c8-e834-446e-9a05-e733ea7d98ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17905
99644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1790599644
Directory /workspace/31.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2627851053
Short name T2431
Test name
Test status
Simulation time 206597797 ps
CPU time 0.88 seconds
Started Aug 05 05:38:12 PM PDT 24
Finished Aug 05 05:38:13 PM PDT 24
Peak memory 207368 kb
Host smart-e5864977-fd56-43d1-9247-ed81c3db6e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26278
51053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2627851053
Directory /workspace/31.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/31.usbdev_rx_full.2313682368
Short name T56
Test name
Test status
Simulation time 352512329 ps
CPU time 1.33 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:38:11 PM PDT 24
Peak memory 207336 kb
Host smart-27bb4b61-f11e-4427-857b-0144315223af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23136
82368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.2313682368
Directory /workspace/31.usbdev_rx_full/latest


Test location /workspace/coverage/default/31.usbdev_setup_stage.3693003147
Short name T616
Test name
Test status
Simulation time 164884959 ps
CPU time 0.84 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:38:11 PM PDT 24
Peak memory 207332 kb
Host smart-5aa4d9bd-96f8-4e49-837d-84a34c108b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36930
03147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.3693003147
Directory /workspace/31.usbdev_setup_stage/latest


Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3356634511
Short name T1109
Test name
Test status
Simulation time 159707403 ps
CPU time 0.84 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:08 PM PDT 24
Peak memory 207320 kb
Host smart-8176d365-c52c-488f-898a-6ebf86bd8a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33566
34511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3356634511
Directory /workspace/31.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/31.usbdev_smoke.2931800244
Short name T1969
Test name
Test status
Simulation time 244678108 ps
CPU time 0.99 seconds
Started Aug 05 05:38:05 PM PDT 24
Finished Aug 05 05:38:06 PM PDT 24
Peak memory 207324 kb
Host smart-5cccd00e-3e33-45c5-90ec-30449dc53864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
00244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2931800244
Directory /workspace/31.usbdev_smoke/latest


Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1077755595
Short name T2304
Test name
Test status
Simulation time 2516409432 ps
CPU time 76.57 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 217548 kb
Host smart-4075fd7c-d331-4f04-ba38-d5b9c81bd33a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1077755595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1077755595
Directory /workspace/31.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3686415363
Short name T2361
Test name
Test status
Simulation time 147500106 ps
CPU time 0.85 seconds
Started Aug 05 05:38:08 PM PDT 24
Finished Aug 05 05:38:09 PM PDT 24
Peak memory 207380 kb
Host smart-411e89ad-d2c0-45bc-8272-21a232075499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36864
15363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3686415363
Directory /workspace/31.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/31.usbdev_stall_trans.2490293177
Short name T666
Test name
Test status
Simulation time 161018805 ps
CPU time 0.87 seconds
Started Aug 05 05:38:08 PM PDT 24
Finished Aug 05 05:38:09 PM PDT 24
Peak memory 207320 kb
Host smart-d1d49a1c-dab5-4821-a853-4ec3e66d2ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24902
93177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2490293177
Directory /workspace/31.usbdev_stall_trans/latest


Test location /workspace/coverage/default/31.usbdev_stream_len_max.3615676910
Short name T628
Test name
Test status
Simulation time 1151414158 ps
CPU time 2.7 seconds
Started Aug 05 05:37:53 PM PDT 24
Finished Aug 05 05:37:56 PM PDT 24
Peak memory 207524 kb
Host smart-9f9b556c-3e15-45d7-9429-3f214d6a51d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36156
76910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.3615676910
Directory /workspace/31.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/31.usbdev_streaming_out.159260199
Short name T1503
Test name
Test status
Simulation time 1796115768 ps
CPU time 17.71 seconds
Started Aug 05 05:38:09 PM PDT 24
Finished Aug 05 05:38:27 PM PDT 24
Peak memory 215736 kb
Host smart-e998eb3d-c6e7-4269-a642-b6109086678b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15926
0199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.159260199
Directory /workspace/31.usbdev_streaming_out/latest


Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.3032187670
Short name T2727
Test name
Test status
Simulation time 1570194509 ps
CPU time 13.14 seconds
Started Aug 05 05:38:00 PM PDT 24
Finished Aug 05 05:38:13 PM PDT 24
Peak memory 207596 kb
Host smart-294f7273-4bf2-400d-a475-1c19cbb60a79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032187670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.3032187670
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/32.usbdev_alert_test.1740781638
Short name T1124
Test name
Test status
Simulation time 37339940 ps
CPU time 0.65 seconds
Started Aug 05 05:38:27 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 207476 kb
Host smart-562d46e1-f4b9-4bae-8328-2abe67ff036b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1740781638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.1740781638
Directory /workspace/32.usbdev_alert_test/latest


Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3404914819
Short name T2634
Test name
Test status
Simulation time 11297374189 ps
CPU time 13.84 seconds
Started Aug 05 05:38:08 PM PDT 24
Finished Aug 05 05:38:22 PM PDT 24
Peak memory 207612 kb
Host smart-60998c58-c602-441e-b47f-acb01b5333d6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404914819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.3404914819
Directory /workspace/32.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2354072893
Short name T2728
Test name
Test status
Simulation time 15190357342 ps
CPU time 17.06 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:24 PM PDT 24
Peak memory 215780 kb
Host smart-f4f29394-e1fd-4f4a-a1b1-16b3fa3f5e43
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354072893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2354072893
Directory /workspace/32.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.2645230277
Short name T811
Test name
Test status
Simulation time 23683569512 ps
CPU time 32.46 seconds
Started Aug 05 05:38:17 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 215860 kb
Host smart-decee9c4-d1a0-4ba9-bdc0-5a5e84c1fab7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645230277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.2645230277
Directory /workspace/32.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/32.usbdev_av_buffer.3931818616
Short name T773
Test name
Test status
Simulation time 215503580 ps
CPU time 0.9 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:08 PM PDT 24
Peak memory 207364 kb
Host smart-b0396ea1-aeb0-4c9c-8153-13cb52eba063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39318
18616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3931818616
Directory /workspace/32.usbdev_av_buffer/latest


Test location /workspace/coverage/default/32.usbdev_bitstuff_err.201494022
Short name T1518
Test name
Test status
Simulation time 181545399 ps
CPU time 0.89 seconds
Started Aug 05 05:38:06 PM PDT 24
Finished Aug 05 05:38:07 PM PDT 24
Peak memory 207316 kb
Host smart-173f18db-1ce0-4d4c-a151-8ab989c8dc45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20149
4022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.201494022
Directory /workspace/32.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.131528651
Short name T1570
Test name
Test status
Simulation time 299174618 ps
CPU time 1.17 seconds
Started Aug 05 05:38:05 PM PDT 24
Finished Aug 05 05:38:06 PM PDT 24
Peak memory 207372 kb
Host smart-073602f6-c6f0-4e46-9252-09b60e086520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13152
8651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.131528651
Directory /workspace/32.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2112466426
Short name T634
Test name
Test status
Simulation time 888797889 ps
CPU time 2.46 seconds
Started Aug 05 05:38:08 PM PDT 24
Finished Aug 05 05:38:11 PM PDT 24
Peak memory 207564 kb
Host smart-f20b5847-372f-44e2-b394-67b72e843d28
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2112466426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2112466426
Directory /workspace/32.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/32.usbdev_device_address.3122048129
Short name T1373
Test name
Test status
Simulation time 23184853140 ps
CPU time 36.32 seconds
Started Aug 05 05:38:04 PM PDT 24
Finished Aug 05 05:38:40 PM PDT 24
Peak memory 207704 kb
Host smart-a2d1f83b-23cc-4a81-94f6-aedc6bb6f27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31220
48129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3122048129
Directory /workspace/32.usbdev_device_address/latest


Test location /workspace/coverage/default/32.usbdev_device_timeout.3624347820
Short name T1454
Test name
Test status
Simulation time 888344807 ps
CPU time 18.05 seconds
Started Aug 05 05:38:14 PM PDT 24
Finished Aug 05 05:38:32 PM PDT 24
Peak memory 207552 kb
Host smart-16484b69-4b69-4010-bc80-950f0edb609f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624347820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.3624347820
Directory /workspace/32.usbdev_device_timeout/latest


Test location /workspace/coverage/default/32.usbdev_disable_endpoint.289519341
Short name T1254
Test name
Test status
Simulation time 819059556 ps
CPU time 1.91 seconds
Started Aug 05 05:38:25 PM PDT 24
Finished Aug 05 05:38:27 PM PDT 24
Peak memory 207340 kb
Host smart-41fa3ec8-ed1d-40e1-b59b-dbc7925003f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28951
9341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.289519341
Directory /workspace/32.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/32.usbdev_disconnected.1384760668
Short name T1117
Test name
Test status
Simulation time 143054966 ps
CPU time 0.84 seconds
Started Aug 05 05:38:06 PM PDT 24
Finished Aug 05 05:38:12 PM PDT 24
Peak memory 207196 kb
Host smart-3c5cf3b9-9140-408e-b3fd-77a856f17011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13847
60668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1384760668
Directory /workspace/32.usbdev_disconnected/latest


Test location /workspace/coverage/default/32.usbdev_enable.3739440164
Short name T1066
Test name
Test status
Simulation time 38438485 ps
CPU time 0.72 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:08 PM PDT 24
Peak memory 207364 kb
Host smart-b66fd11f-fbbe-45f7-9b95-4857e31145c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37394
40164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3739440164
Directory /workspace/32.usbdev_enable/latest


Test location /workspace/coverage/default/32.usbdev_endpoint_access.4151479894
Short name T567
Test name
Test status
Simulation time 903179362 ps
CPU time 2.54 seconds
Started Aug 05 05:38:06 PM PDT 24
Finished Aug 05 05:38:09 PM PDT 24
Peak memory 207548 kb
Host smart-56bc4286-ac70-43f5-b026-9d57fdac66c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41514
79894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.4151479894
Directory /workspace/32.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/32.usbdev_endpoint_types.2466876538
Short name T455
Test name
Test status
Simulation time 418808526 ps
CPU time 1.37 seconds
Started Aug 05 05:38:08 PM PDT 24
Finished Aug 05 05:38:10 PM PDT 24
Peak memory 207352 kb
Host smart-e7e93d03-5ccd-498d-873f-68eda5eeb8e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2466876538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.2466876538
Directory /workspace/32.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/32.usbdev_fifo_rst.909884407
Short name T1013
Test name
Test status
Simulation time 313125514 ps
CPU time 2.12 seconds
Started Aug 05 05:38:13 PM PDT 24
Finished Aug 05 05:38:15 PM PDT 24
Peak memory 207420 kb
Host smart-4683bc09-a8b4-4385-b621-5d21a073fd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90988
4407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.909884407
Directory /workspace/32.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/32.usbdev_in_iso.2506661332
Short name T2274
Test name
Test status
Simulation time 217314748 ps
CPU time 1 seconds
Started Aug 05 05:38:28 PM PDT 24
Finished Aug 05 05:38:29 PM PDT 24
Peak memory 207292 kb
Host smart-0f88c1bd-5650-4870-ae9c-eb2c31810dbb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2506661332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2506661332
Directory /workspace/32.usbdev_in_iso/latest


Test location /workspace/coverage/default/32.usbdev_in_stall.1951821610
Short name T1207
Test name
Test status
Simulation time 157824650 ps
CPU time 0.82 seconds
Started Aug 05 05:38:09 PM PDT 24
Finished Aug 05 05:38:10 PM PDT 24
Peak memory 207256 kb
Host smart-1a532cb6-7d24-4cec-8e7c-b3ba14cb187b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19518
21610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1951821610
Directory /workspace/32.usbdev_in_stall/latest


Test location /workspace/coverage/default/32.usbdev_in_trans.3744501562
Short name T36
Test name
Test status
Simulation time 174847788 ps
CPU time 0.84 seconds
Started Aug 05 05:38:19 PM PDT 24
Finished Aug 05 05:38:19 PM PDT 24
Peak memory 207400 kb
Host smart-4c40b356-ed75-4cb8-9d1a-31431ea00ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37445
01562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3744501562
Directory /workspace/32.usbdev_in_trans/latest


Test location /workspace/coverage/default/32.usbdev_invalid_sync.136588158
Short name T2814
Test name
Test status
Simulation time 4890485163 ps
CPU time 35.53 seconds
Started Aug 05 05:38:09 PM PDT 24
Finished Aug 05 05:38:45 PM PDT 24
Peak memory 223936 kb
Host smart-6b73031a-0535-4251-9418-05eb2df57507
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=136588158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.136588158
Directory /workspace/32.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/32.usbdev_iso_retraction.1735376111
Short name T2940
Test name
Test status
Simulation time 10624231524 ps
CPU time 122.57 seconds
Started Aug 05 05:38:08 PM PDT 24
Finished Aug 05 05:40:11 PM PDT 24
Peak memory 207620 kb
Host smart-4a66fb10-603f-4e1e-a8c4-2c64cd0c7ce3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1735376111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.1735376111
Directory /workspace/32.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/32.usbdev_link_in_err.2411428139
Short name T546
Test name
Test status
Simulation time 180428987 ps
CPU time 0.88 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:08 PM PDT 24
Peak memory 207348 kb
Host smart-7e019b45-8450-4099-9c39-7bf095043976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24114
28139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2411428139
Directory /workspace/32.usbdev_link_in_err/latest


Test location /workspace/coverage/default/32.usbdev_link_resume.2832208493
Short name T2119
Test name
Test status
Simulation time 12849177682 ps
CPU time 17.09 seconds
Started Aug 05 05:37:58 PM PDT 24
Finished Aug 05 05:38:15 PM PDT 24
Peak memory 207632 kb
Host smart-c44ee3a6-336f-44ce-ad70-c5c9114f099f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28322
08493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2832208493
Directory /workspace/32.usbdev_link_resume/latest


Test location /workspace/coverage/default/32.usbdev_link_suspend.1246725893
Short name T1965
Test name
Test status
Simulation time 10587306815 ps
CPU time 13.01 seconds
Started Aug 05 05:38:17 PM PDT 24
Finished Aug 05 05:38:30 PM PDT 24
Peak memory 207544 kb
Host smart-7b80c347-afc9-4c0c-8d95-b1cc35d855a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467
25893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1246725893
Directory /workspace/32.usbdev_link_suspend/latest


Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.1013208548
Short name T2564
Test name
Test status
Simulation time 2532113755 ps
CPU time 23.87 seconds
Started Aug 05 05:38:15 PM PDT 24
Finished Aug 05 05:38:39 PM PDT 24
Peak memory 224020 kb
Host smart-a24ebe1a-53ce-4715-b4e0-dd3f7b5e7e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10132
08548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1013208548
Directory /workspace/32.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.2917758523
Short name T1334
Test name
Test status
Simulation time 2493040526 ps
CPU time 20.94 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 217392 kb
Host smart-777ede14-6fb7-4cf8-9475-2052234925f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2917758523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.2917758523
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.2333600126
Short name T1045
Test name
Test status
Simulation time 269465861 ps
CPU time 0.98 seconds
Started Aug 05 05:38:15 PM PDT 24
Finished Aug 05 05:38:16 PM PDT 24
Peak memory 207376 kb
Host smart-135bccf0-ce98-4dab-baea-9060afc7730a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2333600126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.2333600126
Directory /workspace/32.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2006431460
Short name T3019
Test name
Test status
Simulation time 208475184 ps
CPU time 0.97 seconds
Started Aug 05 05:38:20 PM PDT 24
Finished Aug 05 05:38:21 PM PDT 24
Peak memory 207272 kb
Host smart-942123e9-3ad8-4317-9aef-3717cda31bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20064
31460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2006431460
Directory /workspace/32.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.3664448580
Short name T2341
Test name
Test status
Simulation time 2448909692 ps
CPU time 18.83 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:38:29 PM PDT 24
Peak memory 215788 kb
Host smart-373b6baa-3a49-4fb4-aaad-7fa396f38ab2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3664448580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3664448580
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.335290930
Short name T490
Test name
Test status
Simulation time 152194233 ps
CPU time 0.91 seconds
Started Aug 05 05:38:09 PM PDT 24
Finished Aug 05 05:38:10 PM PDT 24
Peak memory 207388 kb
Host smart-3aa00943-cb51-4fb0-a89b-ee8a5a7bc183
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=335290930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.335290930
Directory /workspace/32.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2951117801
Short name T1327
Test name
Test status
Simulation time 179393566 ps
CPU time 0.84 seconds
Started Aug 05 05:38:20 PM PDT 24
Finished Aug 05 05:38:21 PM PDT 24
Peak memory 207400 kb
Host smart-022e40e9-fd54-400a-b449-f81fb04ec907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29511
17801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2951117801
Directory /workspace/32.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/32.usbdev_nak_trans.2404795537
Short name T126
Test name
Test status
Simulation time 253451228 ps
CPU time 1 seconds
Started Aug 05 05:38:13 PM PDT 24
Finished Aug 05 05:38:14 PM PDT 24
Peak memory 207328 kb
Host smart-d9b4b8a8-9a4f-4bf2-a9ce-cb498d1cf251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24047
95537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2404795537
Directory /workspace/32.usbdev_nak_trans/latest


Test location /workspace/coverage/default/32.usbdev_out_iso.1865260110
Short name T2132
Test name
Test status
Simulation time 180908362 ps
CPU time 0.88 seconds
Started Aug 05 05:38:19 PM PDT 24
Finished Aug 05 05:38:20 PM PDT 24
Peak memory 207404 kb
Host smart-84491c94-75ca-48d7-adcd-2ef8f8eb99a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18652
60110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1865260110
Directory /workspace/32.usbdev_out_iso/latest


Test location /workspace/coverage/default/32.usbdev_out_stall.230928218
Short name T2729
Test name
Test status
Simulation time 156204512 ps
CPU time 0.86 seconds
Started Aug 05 05:38:11 PM PDT 24
Finished Aug 05 05:38:12 PM PDT 24
Peak memory 207344 kb
Host smart-aa145b0b-a14b-437b-8dae-d5deb109a2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23092
8218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.230928218
Directory /workspace/32.usbdev_out_stall/latest


Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1596795298
Short name T3013
Test name
Test status
Simulation time 157204573 ps
CPU time 0.85 seconds
Started Aug 05 05:38:17 PM PDT 24
Finished Aug 05 05:38:18 PM PDT 24
Peak memory 207336 kb
Host smart-e676868b-8472-47e1-b35a-74fc4895f3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15967
95298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1596795298
Directory /workspace/32.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2622324956
Short name T1488
Test name
Test status
Simulation time 150631759 ps
CPU time 0.83 seconds
Started Aug 05 05:38:20 PM PDT 24
Finished Aug 05 05:38:21 PM PDT 24
Peak memory 207268 kb
Host smart-13b3d31f-8271-4477-a3b2-5407a2c70b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26223
24956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2622324956
Directory /workspace/32.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.1052106667
Short name T2017
Test name
Test status
Simulation time 315926381 ps
CPU time 1.06 seconds
Started Aug 05 05:38:28 PM PDT 24
Finished Aug 05 05:38:29 PM PDT 24
Peak memory 207380 kb
Host smart-c6267361-5223-4230-bde6-3a5182e4e0ae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1052106667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.1052106667
Directory /workspace/32.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3834001401
Short name T2328
Test name
Test status
Simulation time 159091114 ps
CPU time 0.88 seconds
Started Aug 05 05:38:13 PM PDT 24
Finished Aug 05 05:38:14 PM PDT 24
Peak memory 206748 kb
Host smart-c1c369a2-b46d-4536-8960-267fcdcdeb4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38340
01401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3834001401
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.70018748
Short name T1727
Test name
Test status
Simulation time 63881574 ps
CPU time 0.7 seconds
Started Aug 05 05:38:18 PM PDT 24
Finished Aug 05 05:38:19 PM PDT 24
Peak memory 207232 kb
Host smart-a2f13341-0293-4601-9d6c-6b704e34084d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70018
748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.70018748
Directory /workspace/32.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2990632938
Short name T1343
Test name
Test status
Simulation time 12967260120 ps
CPU time 32.53 seconds
Started Aug 05 05:38:16 PM PDT 24
Finished Aug 05 05:38:48 PM PDT 24
Peak memory 215824 kb
Host smart-8d5984c8-a216-4f50-8df8-cbf622171177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29906
32938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2990632938
Directory /workspace/32.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/32.usbdev_pkt_received.2869814858
Short name T2414
Test name
Test status
Simulation time 207048632 ps
CPU time 0.92 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:38:11 PM PDT 24
Peak memory 207340 kb
Host smart-9610c908-0400-4c7b-a27b-3c04a2554838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28698
14858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2869814858
Directory /workspace/32.usbdev_pkt_received/latest


Test location /workspace/coverage/default/32.usbdev_pkt_sent.3333025787
Short name T3081
Test name
Test status
Simulation time 247790231 ps
CPU time 1.05 seconds
Started Aug 05 05:38:19 PM PDT 24
Finished Aug 05 05:38:20 PM PDT 24
Peak memory 207356 kb
Host smart-406ee40a-a597-44ea-8afc-c1c9a5b74555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33330
25787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3333025787
Directory /workspace/32.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.3087700532
Short name T2530
Test name
Test status
Simulation time 204988264 ps
CPU time 0.9 seconds
Started Aug 05 05:38:17 PM PDT 24
Finished Aug 05 05:38:18 PM PDT 24
Peak memory 207268 kb
Host smart-ba88aec6-2d9f-4a9e-a782-3332282c2cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30877
00532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3087700532
Directory /workspace/32.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2375294516
Short name T2857
Test name
Test status
Simulation time 186647567 ps
CPU time 0.96 seconds
Started Aug 05 05:38:29 PM PDT 24
Finished Aug 05 05:38:30 PM PDT 24
Peak memory 207272 kb
Host smart-52e1d94e-3d5e-4594-b6db-ac1d50880a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23752
94516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2375294516
Directory /workspace/32.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2266563277
Short name T2078
Test name
Test status
Simulation time 171588867 ps
CPU time 0.85 seconds
Started Aug 05 05:38:28 PM PDT 24
Finished Aug 05 05:38:29 PM PDT 24
Peak memory 207396 kb
Host smart-e5b70845-4f93-4eec-97ae-c204e729f63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22665
63277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2266563277
Directory /workspace/32.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/32.usbdev_rx_full.2205374631
Short name T2246
Test name
Test status
Simulation time 356853493 ps
CPU time 1.24 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:38:12 PM PDT 24
Peak memory 207320 kb
Host smart-5ffad3a2-c799-406e-9333-993e2fb09092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22053
74631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.2205374631
Directory /workspace/32.usbdev_rx_full/latest


Test location /workspace/coverage/default/32.usbdev_setup_stage.3535782805
Short name T2961
Test name
Test status
Simulation time 154287716 ps
CPU time 0.82 seconds
Started Aug 05 05:38:14 PM PDT 24
Finished Aug 05 05:38:15 PM PDT 24
Peak memory 207236 kb
Host smart-da7591a6-00d6-4b9a-b9c5-aea0d88d01be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35357
82805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3535782805
Directory /workspace/32.usbdev_setup_stage/latest


Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2803221191
Short name T2460
Test name
Test status
Simulation time 198694490 ps
CPU time 0.89 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:08 PM PDT 24
Peak memory 207428 kb
Host smart-99d59a8a-1925-4d8b-ba58-f0fdbb41bb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28032
21191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2803221191
Directory /workspace/32.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/32.usbdev_smoke.3636718067
Short name T638
Test name
Test status
Simulation time 212792455 ps
CPU time 1.04 seconds
Started Aug 05 05:38:15 PM PDT 24
Finished Aug 05 05:38:16 PM PDT 24
Peak memory 207392 kb
Host smart-792c340e-ab8b-4b9a-a5ac-d3479a8db7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36367
18067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3636718067
Directory /workspace/32.usbdev_smoke/latest


Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2014395404
Short name T1988
Test name
Test status
Simulation time 3835086414 ps
CPU time 37.56 seconds
Started Aug 05 05:38:13 PM PDT 24
Finished Aug 05 05:38:51 PM PDT 24
Peak memory 216660 kb
Host smart-98eec822-2eda-40fd-a41e-07ac3adadc56
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2014395404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2014395404
Directory /workspace/32.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1225631275
Short name T2581
Test name
Test status
Simulation time 163695349 ps
CPU time 0.9 seconds
Started Aug 05 05:38:15 PM PDT 24
Finished Aug 05 05:38:16 PM PDT 24
Peak memory 207496 kb
Host smart-915daf62-a5f4-458e-a9ef-447af12361c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12256
31275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1225631275
Directory /workspace/32.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/32.usbdev_stall_trans.2909605828
Short name T2722
Test name
Test status
Simulation time 176910845 ps
CPU time 1.05 seconds
Started Aug 05 05:38:25 PM PDT 24
Finished Aug 05 05:38:26 PM PDT 24
Peak memory 207300 kb
Host smart-64faa93b-a801-4001-8004-dee6f9443650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29096
05828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2909605828
Directory /workspace/32.usbdev_stall_trans/latest


Test location /workspace/coverage/default/32.usbdev_stream_len_max.2199493068
Short name T984
Test name
Test status
Simulation time 318788882 ps
CPU time 1.17 seconds
Started Aug 05 05:38:08 PM PDT 24
Finished Aug 05 05:38:09 PM PDT 24
Peak memory 207240 kb
Host smart-81585e7e-8402-4444-9f0a-6b104790803b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21994
93068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.2199493068
Directory /workspace/32.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/32.usbdev_streaming_out.2593680990
Short name T516
Test name
Test status
Simulation time 2462882915 ps
CPU time 69.53 seconds
Started Aug 05 05:38:16 PM PDT 24
Finished Aug 05 05:39:26 PM PDT 24
Peak memory 215804 kb
Host smart-ed3e2f83-b78d-4d38-bb6e-ebddb44ed67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25936
80990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2593680990
Directory /workspace/32.usbdev_streaming_out/latest


Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.440060769
Short name T857
Test name
Test status
Simulation time 1303489209 ps
CPU time 30.32 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:37 PM PDT 24
Peak memory 207504 kb
Host smart-5745290f-5d6a-4626-8f40-eabf6c873205
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440060769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_host
_handshake.440060769
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/33.usbdev_alert_test.1928972944
Short name T2164
Test name
Test status
Simulation time 40535381 ps
CPU time 0.66 seconds
Started Aug 05 05:38:23 PM PDT 24
Finished Aug 05 05:38:24 PM PDT 24
Peak memory 207404 kb
Host smart-0f4a4136-8fc4-45e1-b847-1b2e55587a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1928972944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.1928972944
Directory /workspace/33.usbdev_alert_test/latest


Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2598698311
Short name T947
Test name
Test status
Simulation time 10170927855 ps
CPU time 13.11 seconds
Started Aug 05 05:38:13 PM PDT 24
Finished Aug 05 05:38:27 PM PDT 24
Peak memory 207532 kb
Host smart-36f82a4e-c64f-4380-8f1b-cb2cf6fd6f10
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598698311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.2598698311
Directory /workspace/33.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3868764719
Short name T1442
Test name
Test status
Simulation time 13978420743 ps
CPU time 17 seconds
Started Aug 05 05:38:06 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 215836 kb
Host smart-36cb9cd6-9ea8-4584-b9d8-8c6f3b94de71
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868764719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3868764719
Directory /workspace/33.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.3437993955
Short name T959
Test name
Test status
Simulation time 29296516895 ps
CPU time 34.82 seconds
Started Aug 05 05:38:35 PM PDT 24
Finished Aug 05 05:39:10 PM PDT 24
Peak memory 207668 kb
Host smart-669a1844-e7f7-4266-95a4-a2b778b6fb6c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437993955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.3437993955
Directory /workspace/33.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/33.usbdev_av_buffer.3061613458
Short name T2404
Test name
Test status
Simulation time 204754856 ps
CPU time 1.01 seconds
Started Aug 05 05:38:07 PM PDT 24
Finished Aug 05 05:38:08 PM PDT 24
Peak memory 207348 kb
Host smart-4165c83d-e5a2-4d4a-9164-0cfb7b681fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30616
13458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3061613458
Directory /workspace/33.usbdev_av_buffer/latest


Test location /workspace/coverage/default/33.usbdev_bitstuff_err.1150956019
Short name T776
Test name
Test status
Simulation time 167840158 ps
CPU time 0.85 seconds
Started Aug 05 05:38:04 PM PDT 24
Finished Aug 05 05:38:05 PM PDT 24
Peak memory 207256 kb
Host smart-984b2788-fefe-4794-8aa4-16c3299ec1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11509
56019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.1150956019
Directory /workspace/33.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.1364563541
Short name T2809
Test name
Test status
Simulation time 312956624 ps
CPU time 1.29 seconds
Started Aug 05 05:38:15 PM PDT 24
Finished Aug 05 05:38:16 PM PDT 24
Peak memory 207384 kb
Host smart-1617d617-ac7f-4cc5-848b-262bf0fe14f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13645
63541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.1364563541
Directory /workspace/33.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3515069733
Short name T1476
Test name
Test status
Simulation time 1163638256 ps
CPU time 2.84 seconds
Started Aug 05 05:38:28 PM PDT 24
Finished Aug 05 05:38:31 PM PDT 24
Peak memory 207644 kb
Host smart-77d8e823-eb11-40d9-9b57-4bc0d1c0de63
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3515069733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3515069733
Directory /workspace/33.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/33.usbdev_device_address.3788925703
Short name T2606
Test name
Test status
Simulation time 60080553002 ps
CPU time 92.65 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:39:42 PM PDT 24
Peak memory 207680 kb
Host smart-6cb6a4d0-923d-4026-a51d-506c147df9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37889
25703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.3788925703
Directory /workspace/33.usbdev_device_address/latest


Test location /workspace/coverage/default/33.usbdev_device_timeout.4055128102
Short name T540
Test name
Test status
Simulation time 921506253 ps
CPU time 19.16 seconds
Started Aug 05 05:38:13 PM PDT 24
Finished Aug 05 05:38:33 PM PDT 24
Peak memory 206136 kb
Host smart-7497a62e-a124-4526-a06b-0cddddb32ccb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055128102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.4055128102
Directory /workspace/33.usbdev_device_timeout/latest


Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3430920193
Short name T1010
Test name
Test status
Simulation time 1001369924 ps
CPU time 2.06 seconds
Started Aug 05 05:38:08 PM PDT 24
Finished Aug 05 05:38:10 PM PDT 24
Peak memory 207256 kb
Host smart-b1c7fe2f-b645-4d04-8031-69b6dc34988f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34309
20193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3430920193
Directory /workspace/33.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/33.usbdev_disconnected.3144208163
Short name T1601
Test name
Test status
Simulation time 145189948 ps
CPU time 0.79 seconds
Started Aug 05 05:38:13 PM PDT 24
Finished Aug 05 05:38:14 PM PDT 24
Peak memory 207368 kb
Host smart-e00d1d93-5c42-44bf-b0d8-74e41f65c12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31442
08163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.3144208163
Directory /workspace/33.usbdev_disconnected/latest


Test location /workspace/coverage/default/33.usbdev_enable.3612569202
Short name T756
Test name
Test status
Simulation time 30162750 ps
CPU time 0.68 seconds
Started Aug 05 05:38:27 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 207220 kb
Host smart-90e1df48-62fd-4c1f-9404-29e8d6958ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36125
69202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3612569202
Directory /workspace/33.usbdev_enable/latest


Test location /workspace/coverage/default/33.usbdev_endpoint_access.2150391032
Short name T1025
Test name
Test status
Simulation time 956879123 ps
CPU time 2.57 seconds
Started Aug 05 05:38:15 PM PDT 24
Finished Aug 05 05:38:17 PM PDT 24
Peak memory 207556 kb
Host smart-325a849a-341f-46df-985f-cc498bafd6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21503
91032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2150391032
Directory /workspace/33.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/33.usbdev_endpoint_types.1360617736
Short name T334
Test name
Test status
Simulation time 580267821 ps
CPU time 1.52 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:38:11 PM PDT 24
Peak memory 207220 kb
Host smart-ea517b0f-e948-41f6-980f-11e3f9e268f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1360617736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.1360617736
Directory /workspace/33.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/33.usbdev_fifo_rst.2779946749
Short name T2265
Test name
Test status
Simulation time 300796842 ps
CPU time 1.96 seconds
Started Aug 05 05:38:19 PM PDT 24
Finished Aug 05 05:38:21 PM PDT 24
Peak memory 207544 kb
Host smart-ac8b1b09-fb4d-4909-b8e1-fae106af222d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27799
46749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2779946749
Directory /workspace/33.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/33.usbdev_in_iso.2295858567
Short name T518
Test name
Test status
Simulation time 223511291 ps
CPU time 0.97 seconds
Started Aug 05 05:38:30 PM PDT 24
Finished Aug 05 05:38:31 PM PDT 24
Peak memory 207280 kb
Host smart-e5f5c6eb-99aa-4b8a-8440-09c1f538c3f9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2295858567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2295858567
Directory /workspace/33.usbdev_in_iso/latest


Test location /workspace/coverage/default/33.usbdev_in_stall.438036282
Short name T2149
Test name
Test status
Simulation time 153353403 ps
CPU time 0.81 seconds
Started Aug 05 05:38:22 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 207292 kb
Host smart-275efdf7-5822-428b-95be-01387704d023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43803
6282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.438036282
Directory /workspace/33.usbdev_in_stall/latest


Test location /workspace/coverage/default/33.usbdev_in_trans.1737263192
Short name T579
Test name
Test status
Simulation time 181369107 ps
CPU time 0.91 seconds
Started Aug 05 05:38:21 PM PDT 24
Finished Aug 05 05:38:22 PM PDT 24
Peak memory 207408 kb
Host smart-07847d98-f30b-4eac-a3db-feafe2bda347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17372
63192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1737263192
Directory /workspace/33.usbdev_in_trans/latest


Test location /workspace/coverage/default/33.usbdev_invalid_sync.161629870
Short name T2035
Test name
Test status
Simulation time 3125915599 ps
CPU time 24.7 seconds
Started Aug 05 05:38:12 PM PDT 24
Finished Aug 05 05:38:37 PM PDT 24
Peak memory 223952 kb
Host smart-373bd641-1b53-401e-a65c-a5994e74e69b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=161629870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.161629870
Directory /workspace/33.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/33.usbdev_link_in_err.4048601041
Short name T1235
Test name
Test status
Simulation time 216326567 ps
CPU time 0.99 seconds
Started Aug 05 05:38:19 PM PDT 24
Finished Aug 05 05:38:20 PM PDT 24
Peak memory 207404 kb
Host smart-1d5e0176-2f7a-4658-90c5-97a76e2163c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40486
01041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.4048601041
Directory /workspace/33.usbdev_link_in_err/latest


Test location /workspace/coverage/default/33.usbdev_link_resume.1936315583
Short name T108
Test name
Test status
Simulation time 23480230960 ps
CPU time 28.05 seconds
Started Aug 05 05:38:22 PM PDT 24
Finished Aug 05 05:38:50 PM PDT 24
Peak memory 207608 kb
Host smart-a5073d71-3af9-4462-8886-41f96dbecd6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19363
15583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1936315583
Directory /workspace/33.usbdev_link_resume/latest


Test location /workspace/coverage/default/33.usbdev_link_suspend.543566252
Short name T1055
Test name
Test status
Simulation time 9269627216 ps
CPU time 13.31 seconds
Started Aug 05 05:38:18 PM PDT 24
Finished Aug 05 05:38:32 PM PDT 24
Peak memory 207672 kb
Host smart-e117a7f2-91de-4cb1-96b0-936ea58d28fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54356
6252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.543566252
Directory /workspace/33.usbdev_link_suspend/latest


Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.3876555305
Short name T1205
Test name
Test status
Simulation time 5275291503 ps
CPU time 56.29 seconds
Started Aug 05 05:38:19 PM PDT 24
Finished Aug 05 05:39:15 PM PDT 24
Peak memory 223964 kb
Host smart-c3bbbe2b-4605-4b61-9468-604621c67e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38765
55305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.3876555305
Directory /workspace/33.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.3910884227
Short name T1053
Test name
Test status
Simulation time 2504600493 ps
CPU time 72.88 seconds
Started Aug 05 05:38:17 PM PDT 24
Finished Aug 05 05:39:30 PM PDT 24
Peak memory 217208 kb
Host smart-fb5e8b84-8462-4a34-ac30-42d0ad4e0df8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3910884227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.3910884227
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.3367498664
Short name T1088
Test name
Test status
Simulation time 242657852 ps
CPU time 0.99 seconds
Started Aug 05 05:38:24 PM PDT 24
Finished Aug 05 05:38:25 PM PDT 24
Peak memory 207356 kb
Host smart-b0efd668-42ec-4bd1-bde9-97eeefd018c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3367498664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.3367498664
Directory /workspace/33.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.223006446
Short name T1269
Test name
Test status
Simulation time 250181363 ps
CPU time 1.07 seconds
Started Aug 05 05:38:16 PM PDT 24
Finished Aug 05 05:38:17 PM PDT 24
Peak memory 207296 kb
Host smart-5d9d3ff5-1b10-42eb-abb3-7c1fd68fbca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22300
6446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.223006446
Directory /workspace/33.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.2094529320
Short name T1428
Test name
Test status
Simulation time 3075614176 ps
CPU time 32.36 seconds
Started Aug 05 05:38:20 PM PDT 24
Finished Aug 05 05:38:52 PM PDT 24
Peak memory 217508 kb
Host smart-c495dce4-2494-41aa-908a-693bf05a877a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2094529320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2094529320
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3909082479
Short name T1021
Test name
Test status
Simulation time 149886495 ps
CPU time 0.86 seconds
Started Aug 05 05:38:10 PM PDT 24
Finished Aug 05 05:38:11 PM PDT 24
Peak memory 207352 kb
Host smart-7129fb9a-acd2-4311-9f98-f192095168dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3909082479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3909082479
Directory /workspace/33.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1946053900
Short name T1365
Test name
Test status
Simulation time 137617237 ps
CPU time 0.83 seconds
Started Aug 05 05:38:31 PM PDT 24
Finished Aug 05 05:38:32 PM PDT 24
Peak memory 207420 kb
Host smart-022ea469-43cf-4464-ac5a-e4a1db161f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19460
53900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1946053900
Directory /workspace/33.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/33.usbdev_nak_trans.3884695834
Short name T154
Test name
Test status
Simulation time 204649779 ps
CPU time 0.95 seconds
Started Aug 05 05:38:16 PM PDT 24
Finished Aug 05 05:38:17 PM PDT 24
Peak memory 207304 kb
Host smart-5c5079e0-55eb-4feb-a500-edba8486c492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38846
95834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3884695834
Directory /workspace/33.usbdev_nak_trans/latest


Test location /workspace/coverage/default/33.usbdev_out_iso.380726644
Short name T2825
Test name
Test status
Simulation time 203134098 ps
CPU time 0.94 seconds
Started Aug 05 05:38:08 PM PDT 24
Finished Aug 05 05:38:09 PM PDT 24
Peak memory 207312 kb
Host smart-557e4e4e-f806-43c2-a324-7aadc89b0800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38072
6644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.380726644
Directory /workspace/33.usbdev_out_iso/latest


Test location /workspace/coverage/default/33.usbdev_out_stall.1793212388
Short name T866
Test name
Test status
Simulation time 166162226 ps
CPU time 0.86 seconds
Started Aug 05 05:38:24 PM PDT 24
Finished Aug 05 05:38:25 PM PDT 24
Peak memory 207416 kb
Host smart-e37182e6-2cd9-4a0c-9452-744f19bdbfd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17932
12388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1793212388
Directory /workspace/33.usbdev_out_stall/latest


Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3087168477
Short name T1282
Test name
Test status
Simulation time 253249891 ps
CPU time 0.96 seconds
Started Aug 05 05:38:23 PM PDT 24
Finished Aug 05 05:38:25 PM PDT 24
Peak memory 207348 kb
Host smart-6a9d8207-a554-4293-80fb-39494ac23404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30871
68477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3087168477
Directory /workspace/33.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/33.usbdev_pending_in_trans.4053273720
Short name T2450
Test name
Test status
Simulation time 205704080 ps
CPU time 0.89 seconds
Started Aug 05 05:38:29 PM PDT 24
Finished Aug 05 05:38:30 PM PDT 24
Peak memory 207396 kb
Host smart-fdc0131b-f527-4247-a2c7-0182bc764942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40532
73720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.4053273720
Directory /workspace/33.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.1044204260
Short name T2889
Test name
Test status
Simulation time 229550385 ps
CPU time 0.99 seconds
Started Aug 05 05:38:13 PM PDT 24
Finished Aug 05 05:38:14 PM PDT 24
Peak memory 207384 kb
Host smart-9e6c6c2b-b539-4e8b-96ab-f5f9048bda44
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1044204260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.1044204260
Directory /workspace/33.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1747232614
Short name T1
Test name
Test status
Simulation time 132641675 ps
CPU time 0.86 seconds
Started Aug 05 05:38:27 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 207360 kb
Host smart-a39af409-9653-4888-b54e-d026d064bac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17472
32614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1747232614
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.92791579
Short name T2518
Test name
Test status
Simulation time 77908347 ps
CPU time 0.74 seconds
Started Aug 05 05:38:09 PM PDT 24
Finished Aug 05 05:38:10 PM PDT 24
Peak memory 207284 kb
Host smart-027e7fa9-7e57-4868-ad66-5c836d6b5154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92791
579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.92791579
Directory /workspace/33.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2964362754
Short name T249
Test name
Test status
Simulation time 10391819334 ps
CPU time 24.4 seconds
Started Aug 05 05:38:27 PM PDT 24
Finished Aug 05 05:38:51 PM PDT 24
Peak memory 215860 kb
Host smart-94ec63bb-3366-4206-944e-098276d1c60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29643
62754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2964362754
Directory /workspace/33.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/33.usbdev_pkt_received.1375322490
Short name T1705
Test name
Test status
Simulation time 188595727 ps
CPU time 0.9 seconds
Started Aug 05 05:38:28 PM PDT 24
Finished Aug 05 05:38:29 PM PDT 24
Peak memory 207400 kb
Host smart-6eca6a95-3b2b-4d24-8a47-194197f72f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13753
22490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1375322490
Directory /workspace/33.usbdev_pkt_received/latest


Test location /workspace/coverage/default/33.usbdev_pkt_sent.907273033
Short name T2952
Test name
Test status
Simulation time 296917133 ps
CPU time 1.02 seconds
Started Aug 05 05:38:14 PM PDT 24
Finished Aug 05 05:38:15 PM PDT 24
Peak memory 207392 kb
Host smart-609b07e4-841a-4dc6-b6c5-12b7dca3b9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90727
3033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.907273033
Directory /workspace/33.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.615243882
Short name T2671
Test name
Test status
Simulation time 248235865 ps
CPU time 0.98 seconds
Started Aug 05 05:38:11 PM PDT 24
Finished Aug 05 05:38:12 PM PDT 24
Peak memory 207240 kb
Host smart-ed4502cb-f0e6-4835-863f-f403f86a5240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61524
3882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.615243882
Directory /workspace/33.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.1756482553
Short name T1931
Test name
Test status
Simulation time 238003645 ps
CPU time 0.97 seconds
Started Aug 05 05:38:31 PM PDT 24
Finished Aug 05 05:38:32 PM PDT 24
Peak memory 207256 kb
Host smart-45f375cc-0033-425c-bd00-bc2f4176143e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17564
82553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.1756482553
Directory /workspace/33.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1811566359
Short name T2725
Test name
Test status
Simulation time 191855963 ps
CPU time 0.84 seconds
Started Aug 05 05:38:19 PM PDT 24
Finished Aug 05 05:38:20 PM PDT 24
Peak memory 207316 kb
Host smart-179ff342-4d73-46fa-a916-a3f54ce0762e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18115
66359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1811566359
Directory /workspace/33.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/33.usbdev_rx_full.2972822739
Short name T285
Test name
Test status
Simulation time 243914922 ps
CPU time 1.09 seconds
Started Aug 05 05:38:13 PM PDT 24
Finished Aug 05 05:38:15 PM PDT 24
Peak memory 207348 kb
Host smart-3ed03424-35f9-411f-98b2-3713bd919c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29728
22739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.2972822739
Directory /workspace/33.usbdev_rx_full/latest


Test location /workspace/coverage/default/33.usbdev_setup_stage.1126713936
Short name T581
Test name
Test status
Simulation time 147880174 ps
CPU time 0.83 seconds
Started Aug 05 05:38:11 PM PDT 24
Finished Aug 05 05:38:12 PM PDT 24
Peak memory 207208 kb
Host smart-9c44a094-efe6-4b3b-83a5-1deaf9ce8c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11267
13936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1126713936
Directory /workspace/33.usbdev_setup_stage/latest


Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2487906904
Short name T1557
Test name
Test status
Simulation time 169667763 ps
CPU time 0.84 seconds
Started Aug 05 05:38:27 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 207320 kb
Host smart-066baac9-7e30-44d1-b51f-723db020b1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24879
06904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2487906904
Directory /workspace/33.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/33.usbdev_smoke.2283371227
Short name T911
Test name
Test status
Simulation time 254505569 ps
CPU time 1.1 seconds
Started Aug 05 05:38:25 PM PDT 24
Finished Aug 05 05:38:26 PM PDT 24
Peak memory 207368 kb
Host smart-a6cb5090-c85b-407d-b5c4-9ce64c9f84bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22833
71227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2283371227
Directory /workspace/33.usbdev_smoke/latest


Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.99267549
Short name T1391
Test name
Test status
Simulation time 1888340121 ps
CPU time 14.9 seconds
Started Aug 05 05:38:24 PM PDT 24
Finished Aug 05 05:38:39 PM PDT 24
Peak memory 223832 kb
Host smart-13d23567-bae0-46fc-8798-7a8465b425b1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=99267549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.99267549
Directory /workspace/33.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.902739664
Short name T1451
Test name
Test status
Simulation time 185101762 ps
CPU time 0.92 seconds
Started Aug 05 05:38:25 PM PDT 24
Finished Aug 05 05:38:26 PM PDT 24
Peak memory 207256 kb
Host smart-db37be2a-d8fa-416b-a611-f394aa3cf371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90273
9664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.902739664
Directory /workspace/33.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/33.usbdev_stall_trans.2422800401
Short name T971
Test name
Test status
Simulation time 177400254 ps
CPU time 0.87 seconds
Started Aug 05 05:38:23 PM PDT 24
Finished Aug 05 05:38:24 PM PDT 24
Peak memory 207396 kb
Host smart-6ecee5da-1fae-4145-8fc6-3885b544f43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24228
00401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2422800401
Directory /workspace/33.usbdev_stall_trans/latest


Test location /workspace/coverage/default/33.usbdev_stream_len_max.1959131337
Short name T1415
Test name
Test status
Simulation time 912459126 ps
CPU time 2.19 seconds
Started Aug 05 05:38:13 PM PDT 24
Finished Aug 05 05:38:16 PM PDT 24
Peak memory 207600 kb
Host smart-f6e142a0-a3a4-49c2-8d11-cbd196963d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19591
31337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1959131337
Directory /workspace/33.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/33.usbdev_streaming_out.3503073325
Short name T3125
Test name
Test status
Simulation time 2228153128 ps
CPU time 17.24 seconds
Started Aug 05 05:38:22 PM PDT 24
Finished Aug 05 05:38:40 PM PDT 24
Peak memory 215880 kb
Host smart-eee0f026-9fd1-4352-9769-63c4927de9fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35030
73325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3503073325
Directory /workspace/33.usbdev_streaming_out/latest


Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.1810452953
Short name T552
Test name
Test status
Simulation time 584418385 ps
CPU time 11.17 seconds
Started Aug 05 05:38:09 PM PDT 24
Finished Aug 05 05:38:20 PM PDT 24
Peak memory 207520 kb
Host smart-25cb2c45-2799-4cfa-8270-05f72e9030d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810452953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.1810452953
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/34.usbdev_alert_test.1723444146
Short name T2061
Test name
Test status
Simulation time 35078109 ps
CPU time 0.67 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:38:46 PM PDT 24
Peak memory 207384 kb
Host smart-a60655a8-6b8d-4de2-b709-f85d286c1f00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1723444146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.1723444146
Directory /workspace/34.usbdev_alert_test/latest


Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2773268605
Short name T210
Test name
Test status
Simulation time 5826804107 ps
CPU time 7.9 seconds
Started Aug 05 05:38:20 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 215820 kb
Host smart-75ef3d80-75da-414f-afdf-443a0ca0795b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773268605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.2773268605
Directory /workspace/34.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.1211408667
Short name T2855
Test name
Test status
Simulation time 14680982267 ps
CPU time 15.69 seconds
Started Aug 05 05:38:28 PM PDT 24
Finished Aug 05 05:38:43 PM PDT 24
Peak memory 215884 kb
Host smart-059c0ddf-309d-4bd6-8eaa-dfb10f6e605a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211408667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.1211408667
Directory /workspace/34.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1598894849
Short name T2369
Test name
Test status
Simulation time 29129832544 ps
CPU time 38.9 seconds
Started Aug 05 05:38:17 PM PDT 24
Finished Aug 05 05:38:56 PM PDT 24
Peak memory 207652 kb
Host smart-3986dbf9-3a10-4467-b573-d1a3133ec684
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598894849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.1598894849
Directory /workspace/34.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/34.usbdev_av_buffer.958582886
Short name T615
Test name
Test status
Simulation time 147353547 ps
CPU time 0.82 seconds
Started Aug 05 05:38:11 PM PDT 24
Finished Aug 05 05:38:17 PM PDT 24
Peak memory 207244 kb
Host smart-414d533a-1476-4012-9aee-7207791deecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95858
2886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.958582886
Directory /workspace/34.usbdev_av_buffer/latest


Test location /workspace/coverage/default/34.usbdev_bitstuff_err.705792940
Short name T1056
Test name
Test status
Simulation time 213950039 ps
CPU time 0.91 seconds
Started Aug 05 05:38:14 PM PDT 24
Finished Aug 05 05:38:20 PM PDT 24
Peak memory 207224 kb
Host smart-1ef3049e-a9eb-401c-8ab2-0209591f654f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70579
2940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.705792940
Directory /workspace/34.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.1569427757
Short name T1505
Test name
Test status
Simulation time 504723372 ps
CPU time 1.71 seconds
Started Aug 05 05:38:17 PM PDT 24
Finished Aug 05 05:38:19 PM PDT 24
Peak memory 207324 kb
Host smart-467a62dc-f74d-4e20-8306-3708d7672eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15694
27757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.1569427757
Directory /workspace/34.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2569532197
Short name T763
Test name
Test status
Simulation time 887756645 ps
CPU time 2.36 seconds
Started Aug 05 05:38:22 PM PDT 24
Finished Aug 05 05:38:25 PM PDT 24
Peak memory 207504 kb
Host smart-e8f089ac-6734-4fec-9d35-b696c8aed581
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2569532197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2569532197
Directory /workspace/34.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/34.usbdev_device_address.2546020289
Short name T2350
Test name
Test status
Simulation time 21496014658 ps
CPU time 40.81 seconds
Started Aug 05 05:38:14 PM PDT 24
Finished Aug 05 05:38:55 PM PDT 24
Peak memory 207584 kb
Host smart-53926193-5717-4e64-9bfb-e50ee6aee61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25460
20289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2546020289
Directory /workspace/34.usbdev_device_address/latest


Test location /workspace/coverage/default/34.usbdev_device_timeout.1985479595
Short name T1427
Test name
Test status
Simulation time 571384639 ps
CPU time 11.77 seconds
Started Aug 05 05:38:28 PM PDT 24
Finished Aug 05 05:38:40 PM PDT 24
Peak memory 207568 kb
Host smart-b989282b-2663-4a9d-853a-512a7d5e79c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985479595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.1985479595
Directory /workspace/34.usbdev_device_timeout/latest


Test location /workspace/coverage/default/34.usbdev_disable_endpoint.1508498246
Short name T1824
Test name
Test status
Simulation time 544445123 ps
CPU time 1.45 seconds
Started Aug 05 05:38:29 PM PDT 24
Finished Aug 05 05:38:31 PM PDT 24
Peak memory 207380 kb
Host smart-8d01a92f-269f-4e95-8ddd-753ed18308f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15084
98246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.1508498246
Directory /workspace/34.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/34.usbdev_disconnected.2874726471
Short name T3001
Test name
Test status
Simulation time 137170324 ps
CPU time 0.87 seconds
Started Aug 05 05:38:30 PM PDT 24
Finished Aug 05 05:38:31 PM PDT 24
Peak memory 207360 kb
Host smart-c1f461ea-8cac-4fdc-8c11-0028c3720d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28747
26471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2874726471
Directory /workspace/34.usbdev_disconnected/latest


Test location /workspace/coverage/default/34.usbdev_enable.774609197
Short name T2384
Test name
Test status
Simulation time 76598616 ps
CPU time 0.76 seconds
Started Aug 05 05:38:15 PM PDT 24
Finished Aug 05 05:38:16 PM PDT 24
Peak memory 207228 kb
Host smart-21feab7f-7888-4666-ba02-837a9272f305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77460
9197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.774609197
Directory /workspace/34.usbdev_enable/latest


Test location /workspace/coverage/default/34.usbdev_endpoint_access.1219551586
Short name T2456
Test name
Test status
Simulation time 1012197794 ps
CPU time 2.57 seconds
Started Aug 05 05:38:32 PM PDT 24
Finished Aug 05 05:38:35 PM PDT 24
Peak memory 207600 kb
Host smart-9db1aa6b-925d-4582-90b8-8f7854ec75d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12195
51586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1219551586
Directory /workspace/34.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/34.usbdev_endpoint_types.3600521858
Short name T370
Test name
Test status
Simulation time 389005145 ps
CPU time 1.23 seconds
Started Aug 05 05:38:25 PM PDT 24
Finished Aug 05 05:38:26 PM PDT 24
Peak memory 207324 kb
Host smart-08455481-c341-43a0-8873-4a7c1cf8b67b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3600521858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.3600521858
Directory /workspace/34.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/34.usbdev_fifo_rst.4282226515
Short name T1741
Test name
Test status
Simulation time 161988886 ps
CPU time 1.76 seconds
Started Aug 05 05:38:25 PM PDT 24
Finished Aug 05 05:38:27 PM PDT 24
Peak memory 207556 kb
Host smart-a8eb14e9-11ee-44fa-a750-ac195e186e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42822
26515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.4282226515
Directory /workspace/34.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/34.usbdev_in_iso.313971335
Short name T945
Test name
Test status
Simulation time 236389392 ps
CPU time 1.18 seconds
Started Aug 05 05:38:24 PM PDT 24
Finished Aug 05 05:38:25 PM PDT 24
Peak memory 215748 kb
Host smart-e1ca16da-6d72-4b97-aca8-fa8019e29e95
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=313971335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.313971335
Directory /workspace/34.usbdev_in_iso/latest


Test location /workspace/coverage/default/34.usbdev_in_stall.2387853544
Short name T2771
Test name
Test status
Simulation time 167971601 ps
CPU time 0.86 seconds
Started Aug 05 05:38:30 PM PDT 24
Finished Aug 05 05:38:31 PM PDT 24
Peak memory 207336 kb
Host smart-f1e4b9e5-eb73-4fb8-85da-f5cefd7b8335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23878
53544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2387853544
Directory /workspace/34.usbdev_in_stall/latest


Test location /workspace/coverage/default/34.usbdev_in_trans.3005312595
Short name T2643
Test name
Test status
Simulation time 271048041 ps
CPU time 1.04 seconds
Started Aug 05 05:38:28 PM PDT 24
Finished Aug 05 05:38:29 PM PDT 24
Peak memory 207368 kb
Host smart-d5e40968-7c71-4342-9e3f-34b8a82c3118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30053
12595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3005312595
Directory /workspace/34.usbdev_in_trans/latest


Test location /workspace/coverage/default/34.usbdev_invalid_sync.2753970560
Short name T2680
Test name
Test status
Simulation time 4045742891 ps
CPU time 31.8 seconds
Started Aug 05 05:38:23 PM PDT 24
Finished Aug 05 05:38:55 PM PDT 24
Peak memory 217908 kb
Host smart-03018b5a-e56b-4866-be3d-690b7307d69f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2753970560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2753970560
Directory /workspace/34.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/34.usbdev_iso_retraction.1507204846
Short name T2999
Test name
Test status
Simulation time 9654384138 ps
CPU time 105.55 seconds
Started Aug 05 05:38:28 PM PDT 24
Finished Aug 05 05:40:14 PM PDT 24
Peak memory 207592 kb
Host smart-50378270-a50b-4711-9aeb-565e98724259
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1507204846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.1507204846
Directory /workspace/34.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/34.usbdev_link_in_err.3908948678
Short name T1133
Test name
Test status
Simulation time 221046731 ps
CPU time 0.95 seconds
Started Aug 05 05:38:22 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 207340 kb
Host smart-37019281-754b-4f37-bbf0-e7939137436e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39089
48678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3908948678
Directory /workspace/34.usbdev_link_in_err/latest


Test location /workspace/coverage/default/34.usbdev_link_resume.3111758806
Short name T2168
Test name
Test status
Simulation time 32200688270 ps
CPU time 48.55 seconds
Started Aug 05 05:38:14 PM PDT 24
Finished Aug 05 05:39:03 PM PDT 24
Peak memory 207604 kb
Host smart-6709793d-10b6-42d0-ae86-a7e66083b802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31117
58806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3111758806
Directory /workspace/34.usbdev_link_resume/latest


Test location /workspace/coverage/default/34.usbdev_link_suspend.2832772037
Short name T3109
Test name
Test status
Simulation time 9869256168 ps
CPU time 11.82 seconds
Started Aug 05 05:38:22 PM PDT 24
Finished Aug 05 05:38:33 PM PDT 24
Peak memory 207648 kb
Host smart-c694dcc9-f8ee-4d21-8ad0-9455913fb058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28327
72037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2832772037
Directory /workspace/34.usbdev_link_suspend/latest


Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.3116704935
Short name T1094
Test name
Test status
Simulation time 3535112620 ps
CPU time 27.37 seconds
Started Aug 05 05:38:28 PM PDT 24
Finished Aug 05 05:38:55 PM PDT 24
Peak memory 218464 kb
Host smart-69dbd25b-a4da-4778-9726-bb683a40775b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31167
04935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3116704935
Directory /workspace/34.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3071875982
Short name T975
Test name
Test status
Simulation time 3710352350 ps
CPU time 107.46 seconds
Started Aug 05 05:38:23 PM PDT 24
Finished Aug 05 05:40:10 PM PDT 24
Peak memory 217284 kb
Host smart-14d2d554-2344-411d-ab04-b6c9774eb944
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3071875982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3071875982
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1287177369
Short name T1903
Test name
Test status
Simulation time 241607199 ps
CPU time 1.01 seconds
Started Aug 05 05:38:28 PM PDT 24
Finished Aug 05 05:38:29 PM PDT 24
Peak memory 207352 kb
Host smart-c036bfc1-7b5b-4473-a467-357a9d8beab9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1287177369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1287177369
Directory /workspace/34.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2508227053
Short name T2899
Test name
Test status
Simulation time 268223359 ps
CPU time 1.09 seconds
Started Aug 05 05:38:39 PM PDT 24
Finished Aug 05 05:38:40 PM PDT 24
Peak memory 207376 kb
Host smart-cbc01261-8ccf-4e3e-af2c-823e9b154ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25082
27053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2508227053
Directory /workspace/34.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3410274169
Short name T2244
Test name
Test status
Simulation time 3303829891 ps
CPU time 94.66 seconds
Started Aug 05 05:38:26 PM PDT 24
Finished Aug 05 05:40:01 PM PDT 24
Peak memory 217296 kb
Host smart-784d4d76-d426-4ffd-9049-7ab422757ae9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3410274169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3410274169
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2272140208
Short name T1684
Test name
Test status
Simulation time 157467953 ps
CPU time 0.85 seconds
Started Aug 05 05:38:26 PM PDT 24
Finished Aug 05 05:38:27 PM PDT 24
Peak memory 207252 kb
Host smart-e72a0097-e42e-4816-9ec4-6ed9387b93cf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2272140208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2272140208
Directory /workspace/34.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.4264024627
Short name T1315
Test name
Test status
Simulation time 154007384 ps
CPU time 0.82 seconds
Started Aug 05 05:38:14 PM PDT 24
Finished Aug 05 05:38:14 PM PDT 24
Peak memory 207228 kb
Host smart-d02e43ba-619c-4005-9733-60f18c22f3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42640
24627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.4264024627
Directory /workspace/34.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/34.usbdev_nak_trans.957917074
Short name T135
Test name
Test status
Simulation time 185618011 ps
CPU time 0.98 seconds
Started Aug 05 05:38:35 PM PDT 24
Finished Aug 05 05:38:36 PM PDT 24
Peak memory 207380 kb
Host smart-ea61dd8e-ef9c-4afc-a089-3661a0521e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95791
7074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.957917074
Directory /workspace/34.usbdev_nak_trans/latest


Test location /workspace/coverage/default/34.usbdev_out_iso.3478180833
Short name T2229
Test name
Test status
Simulation time 160613584 ps
CPU time 0.85 seconds
Started Aug 05 05:38:23 PM PDT 24
Finished Aug 05 05:38:24 PM PDT 24
Peak memory 207396 kb
Host smart-bb3df57b-5edc-46d3-8974-e5251149cf6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34781
80833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3478180833
Directory /workspace/34.usbdev_out_iso/latest


Test location /workspace/coverage/default/34.usbdev_out_stall.2927307502
Short name T2601
Test name
Test status
Simulation time 194600958 ps
CPU time 0.92 seconds
Started Aug 05 05:38:24 PM PDT 24
Finished Aug 05 05:38:25 PM PDT 24
Peak memory 207604 kb
Host smart-9755170d-1229-4b38-aa61-37e2086e36dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29273
07502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2927307502
Directory /workspace/34.usbdev_out_stall/latest


Test location /workspace/coverage/default/34.usbdev_out_trans_nak.4008994878
Short name T3003
Test name
Test status
Simulation time 195720914 ps
CPU time 0.95 seconds
Started Aug 05 05:38:14 PM PDT 24
Finished Aug 05 05:38:15 PM PDT 24
Peak memory 207268 kb
Host smart-bed62c37-adbc-41e0-91eb-2168af5e75c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40089
94878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.4008994878
Directory /workspace/34.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/34.usbdev_pending_in_trans.454437165
Short name T2655
Test name
Test status
Simulation time 161651130 ps
CPU time 0.84 seconds
Started Aug 05 05:38:32 PM PDT 24
Finished Aug 05 05:38:33 PM PDT 24
Peak memory 207276 kb
Host smart-f4d91b63-d5e1-4cc3-bff5-ec1125c7970a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45443
7165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.454437165
Directory /workspace/34.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.4249196635
Short name T2881
Test name
Test status
Simulation time 293957738 ps
CPU time 1.08 seconds
Started Aug 05 05:38:17 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 207384 kb
Host smart-f61b141b-a3a1-4339-934a-3969cc200384
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4249196635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.4249196635
Directory /workspace/34.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3636665975
Short name T1325
Test name
Test status
Simulation time 142463573 ps
CPU time 0.83 seconds
Started Aug 05 05:38:20 PM PDT 24
Finished Aug 05 05:38:21 PM PDT 24
Peak memory 207320 kb
Host smart-0509accc-8a5a-4f16-8705-f3c05e9b9ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36366
65975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3636665975
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.4179092670
Short name T1194
Test name
Test status
Simulation time 39523190 ps
CPU time 0.69 seconds
Started Aug 05 05:38:22 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 207364 kb
Host smart-b1b8c3e9-bb5a-4d96-bf9f-0f2422354cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41790
92670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.4179092670
Directory /workspace/34.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1809103298
Short name T3015
Test name
Test status
Simulation time 22700478710 ps
CPU time 56.56 seconds
Started Aug 05 05:38:42 PM PDT 24
Finished Aug 05 05:39:39 PM PDT 24
Peak memory 215880 kb
Host smart-0f57b2b3-987b-459c-bfac-32ff7246be4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18091
03298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1809103298
Directory /workspace/34.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/34.usbdev_pkt_received.994802757
Short name T2621
Test name
Test status
Simulation time 183529152 ps
CPU time 0.94 seconds
Started Aug 05 05:38:24 PM PDT 24
Finished Aug 05 05:38:25 PM PDT 24
Peak memory 207372 kb
Host smart-9946d360-ccba-4007-9525-41bcce678b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99480
2757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.994802757
Directory /workspace/34.usbdev_pkt_received/latest


Test location /workspace/coverage/default/34.usbdev_pkt_sent.3763659625
Short name T3047
Test name
Test status
Simulation time 241563479 ps
CPU time 1 seconds
Started Aug 05 05:38:21 PM PDT 24
Finished Aug 05 05:38:25 PM PDT 24
Peak memory 207340 kb
Host smart-247bd8d0-2e53-4616-896d-a322bad06995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37636
59625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3763659625
Directory /workspace/34.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2708354659
Short name T2918
Test name
Test status
Simulation time 227072693 ps
CPU time 0.93 seconds
Started Aug 05 05:38:27 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 207356 kb
Host smart-e2552f16-fb12-492b-88ee-09bb27c0e0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27083
54659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2708354659
Directory /workspace/34.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.1870828073
Short name T952
Test name
Test status
Simulation time 175640134 ps
CPU time 0.88 seconds
Started Aug 05 05:38:27 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 207268 kb
Host smart-f9859bdd-ff4b-48a8-86b2-a1aad6e62710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18708
28073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.1870828073
Directory /workspace/34.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1359695512
Short name T1579
Test name
Test status
Simulation time 180649768 ps
CPU time 0.91 seconds
Started Aug 05 05:38:32 PM PDT 24
Finished Aug 05 05:38:33 PM PDT 24
Peak memory 207308 kb
Host smart-2e2a08e2-ef94-49de-8fe1-0a0264f38866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13596
95512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1359695512
Directory /workspace/34.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/34.usbdev_rx_full.1090815614
Short name T982
Test name
Test status
Simulation time 394607361 ps
CPU time 1.22 seconds
Started Aug 05 05:38:22 PM PDT 24
Finished Aug 05 05:38:23 PM PDT 24
Peak memory 207348 kb
Host smart-10cb6ff2-25e5-428f-a795-49331a5ba519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10908
15614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.1090815614
Directory /workspace/34.usbdev_rx_full/latest


Test location /workspace/coverage/default/34.usbdev_setup_stage.1328416429
Short name T2895
Test name
Test status
Simulation time 200474832 ps
CPU time 0.85 seconds
Started Aug 05 05:38:20 PM PDT 24
Finished Aug 05 05:38:21 PM PDT 24
Peak memory 207344 kb
Host smart-09bd518b-0c41-4edc-b320-816a837102d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13284
16429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1328416429
Directory /workspace/34.usbdev_setup_stage/latest


Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.866730077
Short name T1032
Test name
Test status
Simulation time 161043099 ps
CPU time 0.84 seconds
Started Aug 05 05:38:26 PM PDT 24
Finished Aug 05 05:38:27 PM PDT 24
Peak memory 207352 kb
Host smart-66413059-74f7-489a-8183-23713e53d7e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86673
0077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.866730077
Directory /workspace/34.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/34.usbdev_smoke.1655435112
Short name T1204
Test name
Test status
Simulation time 226250000 ps
CPU time 1.01 seconds
Started Aug 05 05:38:32 PM PDT 24
Finished Aug 05 05:38:34 PM PDT 24
Peak memory 207352 kb
Host smart-34e6dc08-d126-4be9-95fc-2a96cb87a1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16554
35112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1655435112
Directory /workspace/34.usbdev_smoke/latest


Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1685668766
Short name T1563
Test name
Test status
Simulation time 3250860027 ps
CPU time 33.42 seconds
Started Aug 05 05:38:31 PM PDT 24
Finished Aug 05 05:39:04 PM PDT 24
Peak memory 223980 kb
Host smart-60cc9916-674c-4748-95a6-1f782ae888e2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1685668766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1685668766
Directory /workspace/34.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.467956189
Short name T711
Test name
Test status
Simulation time 189977115 ps
CPU time 0.9 seconds
Started Aug 05 05:38:30 PM PDT 24
Finished Aug 05 05:38:31 PM PDT 24
Peak memory 207256 kb
Host smart-e9063c22-88f3-46b9-a83e-fa4b66a1a1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46795
6189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.467956189
Directory /workspace/34.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/34.usbdev_stall_trans.3448744051
Short name T2802
Test name
Test status
Simulation time 199156518 ps
CPU time 1.02 seconds
Started Aug 05 05:38:44 PM PDT 24
Finished Aug 05 05:38:45 PM PDT 24
Peak memory 207340 kb
Host smart-beaa8159-da5a-438f-8ea5-ddb4ec29f33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34487
44051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3448744051
Directory /workspace/34.usbdev_stall_trans/latest


Test location /workspace/coverage/default/34.usbdev_stream_len_max.959002667
Short name T2131
Test name
Test status
Simulation time 1326198769 ps
CPU time 3.26 seconds
Started Aug 05 05:38:44 PM PDT 24
Finished Aug 05 05:38:47 PM PDT 24
Peak memory 207480 kb
Host smart-8f2f1d9c-0ce8-43f1-9f0b-e87ab158c182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95900
2667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.959002667
Directory /workspace/34.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/34.usbdev_streaming_out.2523671686
Short name T2636
Test name
Test status
Simulation time 1924571890 ps
CPU time 52.82 seconds
Started Aug 05 05:38:42 PM PDT 24
Finished Aug 05 05:39:36 PM PDT 24
Peak memory 223780 kb
Host smart-28704b70-00ac-4e83-874f-eb2adcecaaec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25236
71686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2523671686
Directory /workspace/34.usbdev_streaming_out/latest


Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.1026847613
Short name T2611
Test name
Test status
Simulation time 622083414 ps
CPU time 4.93 seconds
Started Aug 05 05:38:23 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 207628 kb
Host smart-cdf23b45-d137-4b64-a9c6-1407d756ba85
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026847613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.1026847613
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/35.usbdev_alert_test.3312992191
Short name T677
Test name
Test status
Simulation time 46812737 ps
CPU time 0.65 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207416 kb
Host smart-29efb3cf-2ae2-49d3-af4c-1a891cb19d0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3312992191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.3312992191
Directory /workspace/35.usbdev_alert_test/latest


Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2967333621
Short name T2783
Test name
Test status
Simulation time 9989146875 ps
CPU time 11.38 seconds
Started Aug 05 05:38:24 PM PDT 24
Finished Aug 05 05:38:36 PM PDT 24
Peak memory 207656 kb
Host smart-325ae3f0-b378-4764-9af0-d4f83a8693bf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967333621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.2967333621
Directory /workspace/35.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3142184061
Short name T1533
Test name
Test status
Simulation time 13899946529 ps
CPU time 15.63 seconds
Started Aug 05 05:38:40 PM PDT 24
Finished Aug 05 05:38:56 PM PDT 24
Peak memory 215816 kb
Host smart-744e6b11-ba51-4b61-89c2-e5b8fca1c74a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142184061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3142184061
Directory /workspace/35.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.4294630149
Short name T1416
Test name
Test status
Simulation time 24786427427 ps
CPU time 30.43 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:39:15 PM PDT 24
Peak memory 215724 kb
Host smart-0718eec8-2bec-4f40-bc4a-60d18b07c94a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294630149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.4294630149
Directory /workspace/35.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/35.usbdev_av_buffer.3754730314
Short name T162
Test name
Test status
Simulation time 163884334 ps
CPU time 0.84 seconds
Started Aug 05 05:38:26 PM PDT 24
Finished Aug 05 05:38:27 PM PDT 24
Peak memory 207368 kb
Host smart-e3f2eda2-4772-4a61-b632-8b330bf7b571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37547
30314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3754730314
Directory /workspace/35.usbdev_av_buffer/latest


Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2637441360
Short name T2678
Test name
Test status
Simulation time 157753049 ps
CPU time 0.92 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:38:46 PM PDT 24
Peak memory 207208 kb
Host smart-0da03c5b-c71d-4605-bfa6-1de259f533bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26374
41360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2637441360
Directory /workspace/35.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.1856792191
Short name T1665
Test name
Test status
Simulation time 397460128 ps
CPU time 1.41 seconds
Started Aug 05 05:38:35 PM PDT 24
Finished Aug 05 05:38:36 PM PDT 24
Peak memory 207244 kb
Host smart-f9d676d9-ab5d-4c21-8f79-7d880494e933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18567
92191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1856792191
Directory /workspace/35.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.596917118
Short name T783
Test name
Test status
Simulation time 723616626 ps
CPU time 2.03 seconds
Started Aug 05 05:38:32 PM PDT 24
Finished Aug 05 05:38:34 PM PDT 24
Peak memory 207516 kb
Host smart-c5d59b7e-08df-4690-92e4-39537ae5cff3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=596917118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.596917118
Directory /workspace/35.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/35.usbdev_device_address.2131365086
Short name T181
Test name
Test status
Simulation time 54493760793 ps
CPU time 77.22 seconds
Started Aug 05 05:38:30 PM PDT 24
Finished Aug 05 05:39:47 PM PDT 24
Peak memory 207920 kb
Host smart-2ba06037-37f6-46d9-8795-f94b70c0eae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21313
65086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.2131365086
Directory /workspace/35.usbdev_device_address/latest


Test location /workspace/coverage/default/35.usbdev_device_timeout.644231277
Short name T2386
Test name
Test status
Simulation time 5596713392 ps
CPU time 37.34 seconds
Started Aug 05 05:38:22 PM PDT 24
Finished Aug 05 05:39:00 PM PDT 24
Peak memory 207616 kb
Host smart-5e4bd0b6-5ed4-48b8-aa42-42d1d219877e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644231277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.644231277
Directory /workspace/35.usbdev_device_timeout/latest


Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1715342751
Short name T1726
Test name
Test status
Simulation time 432861100 ps
CPU time 1.37 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:38:46 PM PDT 24
Peak memory 207272 kb
Host smart-b787b8de-0123-42f9-9945-f7bd1b8fbe98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17153
42751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1715342751
Directory /workspace/35.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/35.usbdev_disconnected.2984526203
Short name T1771
Test name
Test status
Simulation time 148796260 ps
CPU time 0.81 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207344 kb
Host smart-8c6c8e44-239a-4096-8e62-fd4f01e3f02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29845
26203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.2984526203
Directory /workspace/35.usbdev_disconnected/latest


Test location /workspace/coverage/default/35.usbdev_enable.3350702078
Short name T2379
Test name
Test status
Simulation time 49632501 ps
CPU time 0.76 seconds
Started Aug 05 05:38:35 PM PDT 24
Finished Aug 05 05:38:36 PM PDT 24
Peak memory 207204 kb
Host smart-3272f685-c8c7-459a-87bf-8c418e17095d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33507
02078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3350702078
Directory /workspace/35.usbdev_enable/latest


Test location /workspace/coverage/default/35.usbdev_endpoint_access.4187367802
Short name T976
Test name
Test status
Simulation time 899907700 ps
CPU time 2.46 seconds
Started Aug 05 05:38:33 PM PDT 24
Finished Aug 05 05:38:36 PM PDT 24
Peak memory 207584 kb
Host smart-405d0895-bc2f-43dd-bd96-8573ba657afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41873
67802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.4187367802
Directory /workspace/35.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/35.usbdev_endpoint_types.3559128760
Short name T414
Test name
Test status
Simulation time 449276030 ps
CPU time 1.3 seconds
Started Aug 05 05:38:38 PM PDT 24
Finished Aug 05 05:38:40 PM PDT 24
Peak memory 207324 kb
Host smart-773c08ab-149e-4657-88e7-b7151328aa05
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3559128760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.3559128760
Directory /workspace/35.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/35.usbdev_fifo_rst.1381526773
Short name T832
Test name
Test status
Simulation time 194098123 ps
CPU time 2.14 seconds
Started Aug 05 05:38:30 PM PDT 24
Finished Aug 05 05:38:33 PM PDT 24
Peak memory 207512 kb
Host smart-4b779497-b20e-4f0f-b35d-283b5a754af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13815
26773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1381526773
Directory /workspace/35.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/35.usbdev_in_iso.3659337357
Short name T1494
Test name
Test status
Simulation time 229854173 ps
CPU time 1.09 seconds
Started Aug 05 05:38:43 PM PDT 24
Finished Aug 05 05:38:44 PM PDT 24
Peak memory 215760 kb
Host smart-eb560e46-3a49-4e11-8bf0-61de7076230e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3659337357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3659337357
Directory /workspace/35.usbdev_in_iso/latest


Test location /workspace/coverage/default/35.usbdev_in_stall.1789496765
Short name T2683
Test name
Test status
Simulation time 147344588 ps
CPU time 0.84 seconds
Started Aug 05 05:38:40 PM PDT 24
Finished Aug 05 05:38:41 PM PDT 24
Peak memory 206692 kb
Host smart-344dfd08-7666-4629-abb8-67f2fe351150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17894
96765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1789496765
Directory /workspace/35.usbdev_in_stall/latest


Test location /workspace/coverage/default/35.usbdev_in_trans.1722638027
Short name T2793
Test name
Test status
Simulation time 235159156 ps
CPU time 0.92 seconds
Started Aug 05 05:38:32 PM PDT 24
Finished Aug 05 05:38:33 PM PDT 24
Peak memory 207368 kb
Host smart-b73e7109-d0c8-4d91-af46-2ed0fad8ed41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17226
38027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1722638027
Directory /workspace/35.usbdev_in_trans/latest


Test location /workspace/coverage/default/35.usbdev_invalid_sync.48365018
Short name T576
Test name
Test status
Simulation time 4322715076 ps
CPU time 44.41 seconds
Started Aug 05 05:38:30 PM PDT 24
Finished Aug 05 05:39:14 PM PDT 24
Peak memory 223892 kb
Host smart-ff96519f-3aba-4ca1-a274-390843a8a881
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=48365018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.48365018
Directory /workspace/35.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/35.usbdev_iso_retraction.2563537297
Short name T1023
Test name
Test status
Simulation time 8611904365 ps
CPU time 59.27 seconds
Started Aug 05 05:38:32 PM PDT 24
Finished Aug 05 05:39:31 PM PDT 24
Peak memory 207592 kb
Host smart-a97a2dce-6af9-4b64-ae1d-13b81f53287a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2563537297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.2563537297
Directory /workspace/35.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/35.usbdev_link_in_err.349604293
Short name T762
Test name
Test status
Simulation time 245738641 ps
CPU time 0.96 seconds
Started Aug 05 05:38:33 PM PDT 24
Finished Aug 05 05:38:34 PM PDT 24
Peak memory 207396 kb
Host smart-bdefb7e7-5008-43be-bf25-67e0829067fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34960
4293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.349604293
Directory /workspace/35.usbdev_link_in_err/latest


Test location /workspace/coverage/default/35.usbdev_link_resume.1936500769
Short name T2309
Test name
Test status
Simulation time 15478640419 ps
CPU time 21.7 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:39:07 PM PDT 24
Peak memory 207580 kb
Host smart-b5c3f28e-576d-4963-982b-3bc1f60c6df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19365
00769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1936500769
Directory /workspace/35.usbdev_link_resume/latest


Test location /workspace/coverage/default/35.usbdev_link_suspend.3589303399
Short name T1122
Test name
Test status
Simulation time 11056974328 ps
CPU time 13.21 seconds
Started Aug 05 05:38:32 PM PDT 24
Finished Aug 05 05:38:45 PM PDT 24
Peak memory 207624 kb
Host smart-71a70f46-8638-4ca0-8907-4821f2e9f5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35893
03399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3589303399
Directory /workspace/35.usbdev_link_suspend/latest


Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1434568776
Short name T2139
Test name
Test status
Simulation time 3536878529 ps
CPU time 97.52 seconds
Started Aug 05 05:38:38 PM PDT 24
Finished Aug 05 05:40:16 PM PDT 24
Peak memory 215884 kb
Host smart-253e5c7b-0317-497d-851e-6fb44370cadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14345
68776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1434568776
Directory /workspace/35.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3146892729
Short name T1872
Test name
Test status
Simulation time 1738279226 ps
CPU time 17.41 seconds
Started Aug 05 05:38:46 PM PDT 24
Finished Aug 05 05:39:04 PM PDT 24
Peak memory 223868 kb
Host smart-c51c87d6-4bdf-4dd4-9bae-4f60a6c7892d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3146892729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3146892729
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1410538775
Short name T926
Test name
Test status
Simulation time 241728244 ps
CPU time 1.04 seconds
Started Aug 05 05:38:33 PM PDT 24
Finished Aug 05 05:38:34 PM PDT 24
Peak memory 207272 kb
Host smart-b9ed2cd9-c537-4c17-a602-7c83f289d6a1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1410538775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1410538775
Directory /workspace/35.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.441063507
Short name T3128
Test name
Test status
Simulation time 218803636 ps
CPU time 1.02 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207368 kb
Host smart-d5a1d238-6cef-4a68-8608-1fd1d85088a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44106
3507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.441063507
Directory /workspace/35.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2830885410
Short name T2002
Test name
Test status
Simulation time 3071296053 ps
CPU time 31.79 seconds
Started Aug 05 05:38:37 PM PDT 24
Finished Aug 05 05:39:09 PM PDT 24
Peak memory 215788 kb
Host smart-0bcdc4e9-686e-42c5-8780-3e8e04d17b44
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2830885410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2830885410
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.1915129232
Short name T2836
Test name
Test status
Simulation time 148133071 ps
CPU time 0.87 seconds
Started Aug 05 05:38:41 PM PDT 24
Finished Aug 05 05:38:42 PM PDT 24
Peak memory 207360 kb
Host smart-6dd464a1-9536-45d5-9a5d-e87aade9584d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1915129232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.1915129232
Directory /workspace/35.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1665653345
Short name T1703
Test name
Test status
Simulation time 192818160 ps
CPU time 0.89 seconds
Started Aug 05 05:38:43 PM PDT 24
Finished Aug 05 05:38:44 PM PDT 24
Peak memory 207344 kb
Host smart-49a54b90-1750-44db-a7ad-418611551ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16656
53345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1665653345
Directory /workspace/35.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/35.usbdev_nak_trans.758321782
Short name T133
Test name
Test status
Simulation time 210786152 ps
CPU time 0.93 seconds
Started Aug 05 05:38:27 PM PDT 24
Finished Aug 05 05:38:28 PM PDT 24
Peak memory 207368 kb
Host smart-3b1ab485-ad67-47f4-b72a-4c3cd3c9d0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75832
1782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.758321782
Directory /workspace/35.usbdev_nak_trans/latest


Test location /workspace/coverage/default/35.usbdev_out_iso.3611087940
Short name T2957
Test name
Test status
Simulation time 166095625 ps
CPU time 0.85 seconds
Started Aug 05 05:38:47 PM PDT 24
Finished Aug 05 05:38:54 PM PDT 24
Peak memory 207296 kb
Host smart-1f0d397a-65a0-4429-b3c1-1668ca804433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36110
87940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3611087940
Directory /workspace/35.usbdev_out_iso/latest


Test location /workspace/coverage/default/35.usbdev_out_stall.670255964
Short name T2154
Test name
Test status
Simulation time 150100678 ps
CPU time 0.87 seconds
Started Aug 05 05:38:31 PM PDT 24
Finished Aug 05 05:38:32 PM PDT 24
Peak memory 207368 kb
Host smart-eab2e77f-2d49-4424-9909-cee8525d44b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67025
5964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.670255964
Directory /workspace/35.usbdev_out_stall/latest


Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3966333486
Short name T2718
Test name
Test status
Simulation time 157559660 ps
CPU time 0.85 seconds
Started Aug 05 05:38:50 PM PDT 24
Finished Aug 05 05:38:51 PM PDT 24
Peak memory 207268 kb
Host smart-43bed2b4-7fd9-4541-8b5a-fe8bbac569c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39663
33486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3966333486
Directory /workspace/35.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/35.usbdev_pending_in_trans.187530853
Short name T1112
Test name
Test status
Simulation time 190745788 ps
CPU time 0.92 seconds
Started Aug 05 05:38:33 PM PDT 24
Finished Aug 05 05:38:34 PM PDT 24
Peak memory 207288 kb
Host smart-7cfe3ae2-6696-484a-8f33-bff3084c6c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18753
0853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.187530853
Directory /workspace/35.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.1112069091
Short name T881
Test name
Test status
Simulation time 238569884 ps
CPU time 1.14 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207320 kb
Host smart-ec173e42-82aa-4b0b-9f23-1f7b1c296a5c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1112069091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.1112069091
Directory /workspace/35.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.4236785051
Short name T2761
Test name
Test status
Simulation time 135565036 ps
CPU time 0.79 seconds
Started Aug 05 05:38:35 PM PDT 24
Finished Aug 05 05:38:36 PM PDT 24
Peak memory 207392 kb
Host smart-de5bb60f-36ec-4c89-839d-ebce1c544479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42367
85051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.4236785051
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2371631761
Short name T29
Test name
Test status
Simulation time 32339045 ps
CPU time 0.73 seconds
Started Aug 05 05:38:30 PM PDT 24
Finished Aug 05 05:38:30 PM PDT 24
Peak memory 207572 kb
Host smart-11df9c76-4c64-47c3-a97f-74d99b40af15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23716
31761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2371631761
Directory /workspace/35.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/35.usbdev_pkt_buffer.98213463
Short name T1395
Test name
Test status
Simulation time 19570591311 ps
CPU time 47.04 seconds
Started Aug 05 05:38:29 PM PDT 24
Finished Aug 05 05:39:16 PM PDT 24
Peak memory 215760 kb
Host smart-bbb16a72-d7de-4a84-ad72-164707c3ab00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98213
463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.98213463
Directory /workspace/35.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/35.usbdev_pkt_received.2016281432
Short name T1443
Test name
Test status
Simulation time 178814120 ps
CPU time 0.92 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:38:46 PM PDT 24
Peak memory 207376 kb
Host smart-ace01209-e1e1-46b3-ad49-be04760fdc04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20162
81432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2016281432
Directory /workspace/35.usbdev_pkt_received/latest


Test location /workspace/coverage/default/35.usbdev_pkt_sent.3558198470
Short name T2612
Test name
Test status
Simulation time 225201927 ps
CPU time 0.97 seconds
Started Aug 05 05:38:34 PM PDT 24
Finished Aug 05 05:38:36 PM PDT 24
Peak memory 207380 kb
Host smart-614b87ca-000d-44c5-8a29-c4f925a05a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35581
98470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3558198470
Directory /workspace/35.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.4090749591
Short name T1372
Test name
Test status
Simulation time 261078780 ps
CPU time 1.03 seconds
Started Aug 05 05:38:47 PM PDT 24
Finished Aug 05 05:38:48 PM PDT 24
Peak memory 207296 kb
Host smart-0cc5ba6c-e45d-456f-8f08-e7439cca5194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40907
49591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.4090749591
Directory /workspace/35.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2650341461
Short name T2220
Test name
Test status
Simulation time 168564069 ps
CPU time 0.83 seconds
Started Aug 05 05:38:49 PM PDT 24
Finished Aug 05 05:38:50 PM PDT 24
Peak memory 207348 kb
Host smart-97b4f619-cd53-48d3-808b-4e8718fb2565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26503
41461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2650341461
Directory /workspace/35.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2233704630
Short name T1147
Test name
Test status
Simulation time 187294773 ps
CPU time 0.88 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207348 kb
Host smart-9d807331-f248-467f-8b44-bb11d405f735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22337
04630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2233704630
Directory /workspace/35.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/35.usbdev_rx_full.2911942969
Short name T58
Test name
Test status
Simulation time 417908080 ps
CPU time 1.48 seconds
Started Aug 05 05:38:44 PM PDT 24
Finished Aug 05 05:38:45 PM PDT 24
Peak memory 207348 kb
Host smart-3e275ae9-c30b-4bb1-bf37-5ad2ac8a2b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29119
42969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.2911942969
Directory /workspace/35.usbdev_rx_full/latest


Test location /workspace/coverage/default/35.usbdev_setup_stage.2265430712
Short name T1362
Test name
Test status
Simulation time 146522652 ps
CPU time 0.86 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207264 kb
Host smart-b1fee3fb-d6fb-4a64-b423-776f50a331e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22654
30712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2265430712
Directory /workspace/35.usbdev_setup_stage/latest


Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3355197547
Short name T294
Test name
Test status
Simulation time 151538294 ps
CPU time 0.84 seconds
Started Aug 05 05:38:32 PM PDT 24
Finished Aug 05 05:38:33 PM PDT 24
Peak memory 207400 kb
Host smart-a55dc788-e465-4142-85a1-167e915c37a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33551
97547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3355197547
Directory /workspace/35.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/35.usbdev_smoke.2056503718
Short name T2009
Test name
Test status
Simulation time 261029834 ps
CPU time 1.11 seconds
Started Aug 05 05:38:39 PM PDT 24
Finished Aug 05 05:38:40 PM PDT 24
Peak memory 207476 kb
Host smart-94d94a0a-6678-47b3-83ab-d7472ed4cabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20565
03718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2056503718
Directory /workspace/35.usbdev_smoke/latest


Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.38862796
Short name T733
Test name
Test status
Simulation time 2733358347 ps
CPU time 78.08 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:40:03 PM PDT 24
Peak memory 217700 kb
Host smart-27d96c8c-a39c-41dd-a402-655637462b58
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=38862796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.38862796
Directory /workspace/35.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.246198735
Short name T896
Test name
Test status
Simulation time 167277781 ps
CPU time 0.92 seconds
Started Aug 05 05:38:41 PM PDT 24
Finished Aug 05 05:38:42 PM PDT 24
Peak memory 207344 kb
Host smart-0d51527c-80f8-4132-ab0d-8f7fc77b3716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24619
8735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.246198735
Directory /workspace/35.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/35.usbdev_stall_trans.3112739710
Short name T2505
Test name
Test status
Simulation time 152972938 ps
CPU time 0.87 seconds
Started Aug 05 05:38:47 PM PDT 24
Finished Aug 05 05:38:48 PM PDT 24
Peak memory 207296 kb
Host smart-20476ed2-0696-4b9d-96e1-ff15e784ac69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31127
39710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3112739710
Directory /workspace/35.usbdev_stall_trans/latest


Test location /workspace/coverage/default/35.usbdev_stream_len_max.1973198152
Short name T2298
Test name
Test status
Simulation time 1140135735 ps
CPU time 2.53 seconds
Started Aug 05 05:38:34 PM PDT 24
Finished Aug 05 05:38:37 PM PDT 24
Peak memory 207544 kb
Host smart-c73a24e2-67e7-442e-85d0-86c8f4157cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19731
98152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.1973198152
Directory /workspace/35.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/35.usbdev_streaming_out.1979437567
Short name T619
Test name
Test status
Simulation time 2575396828 ps
CPU time 71.12 seconds
Started Aug 05 05:38:30 PM PDT 24
Finished Aug 05 05:39:41 PM PDT 24
Peak memory 215880 kb
Host smart-070f8598-a11b-4294-a28e-9bfe71e43d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794
37567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1979437567
Directory /workspace/35.usbdev_streaming_out/latest


Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.3110256244
Short name T95
Test name
Test status
Simulation time 1020284784 ps
CPU time 22.01 seconds
Started Aug 05 05:38:44 PM PDT 24
Finished Aug 05 05:39:06 PM PDT 24
Peak memory 207560 kb
Host smart-44afabe2-2274-4a63-9a05-80422327c80f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110256244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.3110256244
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/36.usbdev_alert_test.571515443
Short name T2567
Test name
Test status
Simulation time 41608666 ps
CPU time 0.69 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207340 kb
Host smart-aca9509d-31c8-4e50-8ddc-517324fde33d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=571515443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.571515443
Directory /workspace/36.usbdev_alert_test/latest


Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3860070470
Short name T3115
Test name
Test status
Simulation time 6219239921 ps
CPU time 8.46 seconds
Started Aug 05 05:38:32 PM PDT 24
Finished Aug 05 05:38:40 PM PDT 24
Peak memory 215832 kb
Host smart-7e586bc8-8a5e-40b8-97fe-f8887677e9bc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860070470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.3860070470
Directory /workspace/36.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3080053883
Short name T2013
Test name
Test status
Simulation time 18401719930 ps
CPU time 21.43 seconds
Started Aug 05 05:38:30 PM PDT 24
Finished Aug 05 05:38:51 PM PDT 24
Peak memory 207640 kb
Host smart-57c80cc4-a9a1-4e57-8385-6addd3134e1d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080053883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3080053883
Directory /workspace/36.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1713989050
Short name T2090
Test name
Test status
Simulation time 24215881108 ps
CPU time 36.6 seconds
Started Aug 05 05:38:43 PM PDT 24
Finished Aug 05 05:39:20 PM PDT 24
Peak memory 215864 kb
Host smart-6e4c84b0-e381-40c1-8bcd-3888e2fe4d18
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713989050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.1713989050
Directory /workspace/36.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/36.usbdev_av_buffer.4288997158
Short name T1069
Test name
Test status
Simulation time 166555126 ps
CPU time 0.89 seconds
Started Aug 05 05:38:34 PM PDT 24
Finished Aug 05 05:38:36 PM PDT 24
Peak memory 207416 kb
Host smart-cca86a24-a64c-4a03-96f1-e19f6b2bbe01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42889
97158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.4288997158
Directory /workspace/36.usbdev_av_buffer/latest


Test location /workspace/coverage/default/36.usbdev_bitstuff_err.2267547573
Short name T87
Test name
Test status
Simulation time 218069772 ps
CPU time 0.95 seconds
Started Aug 05 05:38:49 PM PDT 24
Finished Aug 05 05:38:50 PM PDT 24
Peak memory 207232 kb
Host smart-563c7cb5-ca29-4146-aba5-d74adc51a52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22675
47573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.2267547573
Directory /workspace/36.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.2810013396
Short name T1674
Test name
Test status
Simulation time 225254262 ps
CPU time 1.05 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:38:46 PM PDT 24
Peak memory 207344 kb
Host smart-285c249e-92c3-422c-99a7-1e02a0656e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28100
13396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2810013396
Directory /workspace/36.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1221245123
Short name T2640
Test name
Test status
Simulation time 837300435 ps
CPU time 2.24 seconds
Started Aug 05 05:38:47 PM PDT 24
Finished Aug 05 05:38:50 PM PDT 24
Peak memory 207556 kb
Host smart-07be5def-1b05-4773-b8e6-edd12832dcd9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1221245123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1221245123
Directory /workspace/36.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/36.usbdev_device_address.520509110
Short name T2390
Test name
Test status
Simulation time 60417246359 ps
CPU time 95.94 seconds
Started Aug 05 05:38:37 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207696 kb
Host smart-e2a18af7-9916-42bc-9050-66eae59b802f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52050
9110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.520509110
Directory /workspace/36.usbdev_device_address/latest


Test location /workspace/coverage/default/36.usbdev_device_timeout.895688802
Short name T2353
Test name
Test status
Simulation time 408624701 ps
CPU time 7.8 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:38:53 PM PDT 24
Peak memory 207496 kb
Host smart-6dd0a50b-08d6-4d7f-9183-f845c9291053
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895688802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.895688802
Directory /workspace/36.usbdev_device_timeout/latest


Test location /workspace/coverage/default/36.usbdev_disable_endpoint.561353258
Short name T342
Test name
Test status
Simulation time 715846908 ps
CPU time 1.83 seconds
Started Aug 05 05:38:44 PM PDT 24
Finished Aug 05 05:38:46 PM PDT 24
Peak memory 207320 kb
Host smart-3213305f-f22c-4eeb-82c8-7398cf53d384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56135
3258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.561353258
Directory /workspace/36.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/36.usbdev_disconnected.44463237
Short name T1274
Test name
Test status
Simulation time 152338100 ps
CPU time 0.83 seconds
Started Aug 05 05:38:37 PM PDT 24
Finished Aug 05 05:38:38 PM PDT 24
Peak memory 207236 kb
Host smart-c9bbec35-f8d7-4e3f-84c5-46b3a4b71986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44463
237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.44463237
Directory /workspace/36.usbdev_disconnected/latest


Test location /workspace/coverage/default/36.usbdev_enable.3109509237
Short name T899
Test name
Test status
Simulation time 39579327 ps
CPU time 0.68 seconds
Started Aug 05 05:38:32 PM PDT 24
Finished Aug 05 05:38:33 PM PDT 24
Peak memory 207316 kb
Host smart-c67e9746-a16d-426c-ae48-2c6a1c6d01ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31095
09237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3109509237
Directory /workspace/36.usbdev_enable/latest


Test location /workspace/coverage/default/36.usbdev_endpoint_access.3599535193
Short name T2250
Test name
Test status
Simulation time 884817647 ps
CPU time 2.47 seconds
Started Aug 05 05:38:38 PM PDT 24
Finished Aug 05 05:38:40 PM PDT 24
Peak memory 207500 kb
Host smart-af19d1b0-2f9b-4dc3-8968-36ed00d2115c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35995
35193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3599535193
Directory /workspace/36.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/36.usbdev_endpoint_types.2469181198
Short name T381
Test name
Test status
Simulation time 857675547 ps
CPU time 1.91 seconds
Started Aug 05 05:38:40 PM PDT 24
Finished Aug 05 05:38:42 PM PDT 24
Peak memory 207336 kb
Host smart-5b148e09-9dac-4dd4-a30d-67bbd652b82f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2469181198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.2469181198
Directory /workspace/36.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/36.usbdev_fifo_rst.3336365553
Short name T3048
Test name
Test status
Simulation time 169290010 ps
CPU time 1.54 seconds
Started Aug 05 05:38:34 PM PDT 24
Finished Aug 05 05:38:35 PM PDT 24
Peak memory 207428 kb
Host smart-f7fe87f1-56cf-4644-8a92-39eaa29e9726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33363
65553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3336365553
Directory /workspace/36.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/36.usbdev_in_iso.882303377
Short name T2875
Test name
Test status
Simulation time 240293302 ps
CPU time 1.24 seconds
Started Aug 05 05:38:33 PM PDT 24
Finished Aug 05 05:38:34 PM PDT 24
Peak memory 215780 kb
Host smart-bd2be11f-8b8f-44bc-9a98-62424a5ad307
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=882303377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.882303377
Directory /workspace/36.usbdev_in_iso/latest


Test location /workspace/coverage/default/36.usbdev_in_stall.2881471785
Short name T2125
Test name
Test status
Simulation time 136951564 ps
CPU time 0.79 seconds
Started Aug 05 05:38:46 PM PDT 24
Finished Aug 05 05:38:47 PM PDT 24
Peak memory 207320 kb
Host smart-0f2c6059-2ccb-48da-9fb9-cd322d275509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28814
71785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2881471785
Directory /workspace/36.usbdev_in_stall/latest


Test location /workspace/coverage/default/36.usbdev_in_trans.98415180
Short name T626
Test name
Test status
Simulation time 224474954 ps
CPU time 0.96 seconds
Started Aug 05 05:38:43 PM PDT 24
Finished Aug 05 05:38:44 PM PDT 24
Peak memory 207268 kb
Host smart-1ec2e2ae-577d-4b0e-8dc1-8ab78dcd9817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98415
180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.98415180
Directory /workspace/36.usbdev_in_trans/latest


Test location /workspace/coverage/default/36.usbdev_invalid_sync.2570303994
Short name T2915
Test name
Test status
Simulation time 4209116599 ps
CPU time 118.98 seconds
Started Aug 05 05:38:46 PM PDT 24
Finished Aug 05 05:40:45 PM PDT 24
Peak memory 215868 kb
Host smart-08af087d-7957-4d1c-a237-40a5fb907093
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2570303994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.2570303994
Directory /workspace/36.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/36.usbdev_iso_retraction.3807195422
Short name T2096
Test name
Test status
Simulation time 9587440449 ps
CPU time 107.23 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207616 kb
Host smart-5f356b55-685b-49c2-b324-299f836a7c9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3807195422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.3807195422
Directory /workspace/36.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/36.usbdev_link_in_err.936030875
Short name T1716
Test name
Test status
Simulation time 239145363 ps
CPU time 1.03 seconds
Started Aug 05 05:38:39 PM PDT 24
Finished Aug 05 05:38:41 PM PDT 24
Peak memory 207404 kb
Host smart-ce7e443f-d2b2-4776-943a-4a3531ad8698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93603
0875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.936030875
Directory /workspace/36.usbdev_link_in_err/latest


Test location /workspace/coverage/default/36.usbdev_link_resume.2443111342
Short name T1172
Test name
Test status
Simulation time 23957341388 ps
CPU time 41.57 seconds
Started Aug 05 05:38:43 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 215724 kb
Host smart-10a261b6-de38-42c1-a893-ab77098660ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24431
11342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.2443111342
Directory /workspace/36.usbdev_link_resume/latest


Test location /workspace/coverage/default/36.usbdev_link_suspend.1497474692
Short name T1569
Test name
Test status
Simulation time 9748961463 ps
CPU time 11.91 seconds
Started Aug 05 05:38:43 PM PDT 24
Finished Aug 05 05:38:55 PM PDT 24
Peak memory 207612 kb
Host smart-b731d022-d768-432c-9fc3-f6cd670e667f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14974
74692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1497474692
Directory /workspace/36.usbdev_link_suspend/latest


Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2201149792
Short name T933
Test name
Test status
Simulation time 3691334339 ps
CPU time 36.5 seconds
Started Aug 05 05:38:49 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 215756 kb
Host smart-36de97cf-ff8e-4b51-9b08-d64b42b69f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22011
49792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2201149792
Directory /workspace/36.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.2787495043
Short name T2497
Test name
Test status
Simulation time 3671896594 ps
CPU time 109.97 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:40:40 PM PDT 24
Peak memory 217132 kb
Host smart-82a1ad18-2c78-4443-806f-2ef825ffee72
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2787495043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.2787495043
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2515939115
Short name T1456
Test name
Test status
Simulation time 242332435 ps
CPU time 1.01 seconds
Started Aug 05 05:38:50 PM PDT 24
Finished Aug 05 05:38:51 PM PDT 24
Peak memory 207236 kb
Host smart-3db1da9a-561b-4aae-a244-9ce9aed2b4a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2515939115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2515939115
Directory /workspace/36.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.3805004323
Short name T1497
Test name
Test status
Simulation time 202388882 ps
CPU time 0.95 seconds
Started Aug 05 05:38:37 PM PDT 24
Finished Aug 05 05:38:38 PM PDT 24
Peak memory 207608 kb
Host smart-c79e0628-7a0f-40ea-83da-cea2493a37c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38050
04323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3805004323
Directory /workspace/36.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1136266601
Short name T2578
Test name
Test status
Simulation time 1612953703 ps
CPU time 15.51 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:39:04 PM PDT 24
Peak memory 215652 kb
Host smart-af95c359-0cb2-4259-9192-630602055646
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1136266601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1136266601
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2135848287
Short name T801
Test name
Test status
Simulation time 163618478 ps
CPU time 0.86 seconds
Started Aug 05 05:38:37 PM PDT 24
Finished Aug 05 05:38:39 PM PDT 24
Peak memory 207272 kb
Host smart-90a10222-bca8-46d7-93a9-6a9c98f91254
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2135848287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2135848287
Directory /workspace/36.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3605281851
Short name T2199
Test name
Test status
Simulation time 137802795 ps
CPU time 0.85 seconds
Started Aug 05 05:38:46 PM PDT 24
Finished Aug 05 05:38:47 PM PDT 24
Peak memory 207328 kb
Host smart-99a01cad-1cfd-45c2-b7a6-8129411dfd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36052
81851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3605281851
Directory /workspace/36.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/36.usbdev_nak_trans.443332330
Short name T2917
Test name
Test status
Simulation time 202724898 ps
CPU time 0.97 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207300 kb
Host smart-cb53851d-3704-4490-8fc3-0f4c597edcbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44333
2330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.443332330
Directory /workspace/36.usbdev_nak_trans/latest


Test location /workspace/coverage/default/36.usbdev_out_iso.4088950600
Short name T2829
Test name
Test status
Simulation time 207911330 ps
CPU time 0.9 seconds
Started Aug 05 05:38:37 PM PDT 24
Finished Aug 05 05:38:39 PM PDT 24
Peak memory 207268 kb
Host smart-fb7786e0-5192-4663-9e43-b22850d65c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40889
50600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.4088950600
Directory /workspace/36.usbdev_out_iso/latest


Test location /workspace/coverage/default/36.usbdev_out_stall.8289566
Short name T2394
Test name
Test status
Simulation time 156983887 ps
CPU time 0.86 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207300 kb
Host smart-76e63f10-085f-4fab-8aa8-7a268cceabf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82895
66 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.8289566
Directory /workspace/36.usbdev_out_stall/latest


Test location /workspace/coverage/default/36.usbdev_out_trans_nak.338600565
Short name T1717
Test name
Test status
Simulation time 179737685 ps
CPU time 0.94 seconds
Started Aug 05 05:38:38 PM PDT 24
Finished Aug 05 05:38:39 PM PDT 24
Peak memory 207316 kb
Host smart-e10f2dd3-c6bd-4bda-b2d6-5e839903c8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33860
0565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.338600565
Directory /workspace/36.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3360904062
Short name T2405
Test name
Test status
Simulation time 163103701 ps
CPU time 0.91 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:50 PM PDT 24
Peak memory 207324 kb
Host smart-2f59de6f-153a-4d13-ab54-da38e631e408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33609
04062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3360904062
Directory /workspace/36.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3707089357
Short name T1992
Test name
Test status
Simulation time 195429601 ps
CPU time 1.08 seconds
Started Aug 05 05:38:39 PM PDT 24
Finished Aug 05 05:38:40 PM PDT 24
Peak memory 207252 kb
Host smart-7c0d8479-ef72-49e6-8b82-80918009c4e4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3707089357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3707089357
Directory /workspace/36.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1013480516
Short name T1226
Test name
Test status
Simulation time 154291629 ps
CPU time 0.84 seconds
Started Aug 05 05:38:39 PM PDT 24
Finished Aug 05 05:38:40 PM PDT 24
Peak memory 207368 kb
Host smart-cda85216-29af-4f51-8d47-290cbaf742cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10134
80516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1013480516
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.416678746
Short name T41
Test name
Test status
Simulation time 34154168 ps
CPU time 0.71 seconds
Started Aug 05 05:38:47 PM PDT 24
Finished Aug 05 05:38:48 PM PDT 24
Peak memory 207364 kb
Host smart-39449138-d191-4a09-9e0d-64716cafb49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41667
8746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.416678746
Directory /workspace/36.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/36.usbdev_pkt_buffer.440808126
Short name T2619
Test name
Test status
Simulation time 22119801466 ps
CPU time 53.49 seconds
Started Aug 05 05:38:42 PM PDT 24
Finished Aug 05 05:39:36 PM PDT 24
Peak memory 215880 kb
Host smart-c01559a9-c0f0-4ad1-9b55-6654b0458f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44080
8126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.440808126
Directory /workspace/36.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/36.usbdev_pkt_received.3568276754
Short name T2870
Test name
Test status
Simulation time 246692753 ps
CPU time 0.98 seconds
Started Aug 05 05:38:34 PM PDT 24
Finished Aug 05 05:38:35 PM PDT 24
Peak memory 207324 kb
Host smart-44182436-8cbb-43ca-8d19-9a5f94f85c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35682
76754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3568276754
Directory /workspace/36.usbdev_pkt_received/latest


Test location /workspace/coverage/default/36.usbdev_pkt_sent.380671467
Short name T1075
Test name
Test status
Simulation time 217167092 ps
CPU time 0.96 seconds
Started Aug 05 05:38:46 PM PDT 24
Finished Aug 05 05:38:47 PM PDT 24
Peak memory 207328 kb
Host smart-7873b9d9-2804-4c51-b215-8eaef5d2398b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38067
1467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.380671467
Directory /workspace/36.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.788765133
Short name T1070
Test name
Test status
Simulation time 298688353 ps
CPU time 1.03 seconds
Started Aug 05 05:38:49 PM PDT 24
Finished Aug 05 05:38:50 PM PDT 24
Peak memory 207348 kb
Host smart-089b5644-cd99-4a46-bf72-e19f84047f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78876
5133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.788765133
Directory /workspace/36.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2371123708
Short name T2207
Test name
Test status
Simulation time 224271463 ps
CPU time 0.98 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207340 kb
Host smart-aa1e5f04-80a0-4fb9-8691-8f8d5772aec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23711
23708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2371123708
Directory /workspace/36.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/36.usbdev_rx_crc_err.4252225601
Short name T1635
Test name
Test status
Simulation time 170590773 ps
CPU time 0.85 seconds
Started Aug 05 05:38:37 PM PDT 24
Finished Aug 05 05:38:38 PM PDT 24
Peak memory 207396 kb
Host smart-ee1fb71f-cd04-4852-9b39-de511ab9028e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42522
25601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.4252225601
Directory /workspace/36.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/36.usbdev_rx_full.3872809518
Short name T2716
Test name
Test status
Simulation time 341163642 ps
CPU time 1.3 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:38:47 PM PDT 24
Peak memory 207352 kb
Host smart-1589c231-0f8f-4b14-8da7-95b00eec590c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38728
09518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.3872809518
Directory /workspace/36.usbdev_rx_full/latest


Test location /workspace/coverage/default/36.usbdev_setup_stage.1119662265
Short name T1433
Test name
Test status
Simulation time 150900505 ps
CPU time 0.84 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207336 kb
Host smart-bb7f5cbb-d26f-43b6-8265-3636c2d31e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11196
62265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1119662265
Directory /workspace/36.usbdev_setup_stage/latest


Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2255974880
Short name T2880
Test name
Test status
Simulation time 164898595 ps
CPU time 0.88 seconds
Started Aug 05 05:38:46 PM PDT 24
Finished Aug 05 05:38:47 PM PDT 24
Peak memory 207224 kb
Host smart-0396f414-dbc5-4a00-9d65-383bf0d76ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22559
74880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2255974880
Directory /workspace/36.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/36.usbdev_smoke.2811081128
Short name T856
Test name
Test status
Simulation time 214945047 ps
CPU time 1.02 seconds
Started Aug 05 05:38:39 PM PDT 24
Finished Aug 05 05:38:41 PM PDT 24
Peak memory 207376 kb
Host smart-83463050-6ca8-4737-9949-6b5903a406c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28110
81128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2811081128
Directory /workspace/36.usbdev_smoke/latest


Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.495600275
Short name T1247
Test name
Test status
Simulation time 2107810638 ps
CPU time 61.87 seconds
Started Aug 05 05:38:37 PM PDT 24
Finished Aug 05 05:39:39 PM PDT 24
Peak memory 217460 kb
Host smart-0eb13cb1-8d30-441d-88cd-7c58b7fbf2d4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=495600275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.495600275
Directory /workspace/36.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.382006925
Short name T731
Test name
Test status
Simulation time 169681481 ps
CPU time 0.92 seconds
Started Aug 05 05:38:38 PM PDT 24
Finished Aug 05 05:38:39 PM PDT 24
Peak memory 207468 kb
Host smart-45bb8a73-2d09-4414-be27-f8caac6ccb6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38200
6925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.382006925
Directory /workspace/36.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/36.usbdev_stall_trans.3229050615
Short name T2121
Test name
Test status
Simulation time 211241957 ps
CPU time 0.96 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207368 kb
Host smart-c0887ef9-6cb6-4e26-8a0d-9a30b5a884c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32290
50615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3229050615
Directory /workspace/36.usbdev_stall_trans/latest


Test location /workspace/coverage/default/36.usbdev_stream_len_max.3385478697
Short name T1016
Test name
Test status
Simulation time 235953025 ps
CPU time 0.96 seconds
Started Aug 05 05:38:43 PM PDT 24
Finished Aug 05 05:38:44 PM PDT 24
Peak memory 207220 kb
Host smart-66136da3-0ed1-4cfd-afb3-0a2e1ffd9024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33854
78697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.3385478697
Directory /workspace/36.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/36.usbdev_streaming_out.873759162
Short name T2206
Test name
Test status
Simulation time 2889822032 ps
CPU time 85.17 seconds
Started Aug 05 05:38:49 PM PDT 24
Finished Aug 05 05:40:15 PM PDT 24
Peak memory 223912 kb
Host smart-dc46858a-4f5d-4ddd-85d7-2a9d42c0b7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87375
9162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.873759162
Directory /workspace/36.usbdev_streaming_out/latest


Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.2675088258
Short name T1599
Test name
Test status
Simulation time 182012148 ps
CPU time 0.94 seconds
Started Aug 05 05:38:29 PM PDT 24
Finished Aug 05 05:38:30 PM PDT 24
Peak memory 207340 kb
Host smart-d3ccaf52-ea85-4c68-a95a-c6bf19689822
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675088258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.2675088258
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/37.usbdev_alert_test.1279137608
Short name T849
Test name
Test status
Simulation time 61527651 ps
CPU time 0.68 seconds
Started Aug 05 05:38:38 PM PDT 24
Finished Aug 05 05:38:39 PM PDT 24
Peak memory 207360 kb
Host smart-bc1594bd-fc58-4a3e-a63b-09a1b20dc3b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1279137608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.1279137608
Directory /workspace/37.usbdev_alert_test/latest


Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.515071694
Short name T2197
Test name
Test status
Simulation time 10493767422 ps
CPU time 12.7 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:39:00 PM PDT 24
Peak memory 207496 kb
Host smart-c29452c0-6b01-4f39-b47d-64079acf1a22
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515071694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ao
n_wake_disconnect.515071694
Directory /workspace/37.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2401175741
Short name T613
Test name
Test status
Simulation time 13402302333 ps
CPU time 18.18 seconds
Started Aug 05 05:38:37 PM PDT 24
Finished Aug 05 05:38:56 PM PDT 24
Peak memory 215836 kb
Host smart-4f1dfc6d-73c0-4cfe-adde-9a6a1ecacaff
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401175741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2401175741
Directory /workspace/37.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2511614342
Short name T1459
Test name
Test status
Simulation time 30113233134 ps
CPU time 34.34 seconds
Started Aug 05 05:38:46 PM PDT 24
Finished Aug 05 05:39:20 PM PDT 24
Peak memory 207580 kb
Host smart-dd3edaf0-5dc1-4e72-b843-cc07dab5fbf4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511614342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_resume.2511614342
Directory /workspace/37.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/37.usbdev_av_buffer.3537690469
Short name T2195
Test name
Test status
Simulation time 179729695 ps
CPU time 0.87 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:50 PM PDT 24
Peak memory 207356 kb
Host smart-a1a39ffb-8d18-47cd-8fd2-406ae823936d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35376
90469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3537690469
Directory /workspace/37.usbdev_av_buffer/latest


Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3778515458
Short name T1955
Test name
Test status
Simulation time 151845931 ps
CPU time 0.89 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:38:46 PM PDT 24
Peak memory 207236 kb
Host smart-c4a47628-e046-4e76-9101-2b1e0e0d92b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37785
15458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3778515458
Directory /workspace/37.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.671197632
Short name T2311
Test name
Test status
Simulation time 364530556 ps
CPU time 1.37 seconds
Started Aug 05 05:38:39 PM PDT 24
Finished Aug 05 05:38:41 PM PDT 24
Peak memory 207292 kb
Host smart-037cd184-246b-471c-95c8-8bd676243bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67119
7632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.671197632
Directory /workspace/37.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2654860265
Short name T1149
Test name
Test status
Simulation time 546720772 ps
CPU time 1.53 seconds
Started Aug 05 05:38:46 PM PDT 24
Finished Aug 05 05:38:48 PM PDT 24
Peak memory 207344 kb
Host smart-7dcc6e51-eb5f-412b-b6ed-9fa9114e35f7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2654860265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2654860265
Directory /workspace/37.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/37.usbdev_device_timeout.2675057300
Short name T2029
Test name
Test status
Simulation time 2495642876 ps
CPU time 21.28 seconds
Started Aug 05 05:38:53 PM PDT 24
Finished Aug 05 05:39:14 PM PDT 24
Peak memory 207624 kb
Host smart-11d1edeb-7e93-485a-865a-16bc0c2f6306
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675057300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.2675057300
Directory /workspace/37.usbdev_device_timeout/latest


Test location /workspace/coverage/default/37.usbdev_disable_endpoint.3710832432
Short name T2599
Test name
Test status
Simulation time 729427679 ps
CPU time 1.85 seconds
Started Aug 05 05:38:47 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207288 kb
Host smart-09f4e0cb-b991-435d-8f9c-5d2a25441275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37108
32432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.3710832432
Directory /workspace/37.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/37.usbdev_disconnected.2898963927
Short name T1712
Test name
Test status
Simulation time 153966520 ps
CPU time 0.8 seconds
Started Aug 05 05:38:55 PM PDT 24
Finished Aug 05 05:38:56 PM PDT 24
Peak memory 207364 kb
Host smart-0780934b-b050-4fba-96d6-1414c71d2b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28989
63927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2898963927
Directory /workspace/37.usbdev_disconnected/latest


Test location /workspace/coverage/default/37.usbdev_enable.909808734
Short name T509
Test name
Test status
Simulation time 41914654 ps
CPU time 0.67 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207304 kb
Host smart-d2418805-73a7-4b8a-8db8-b93f9d8593cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90980
8734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.909808734
Directory /workspace/37.usbdev_enable/latest


Test location /workspace/coverage/default/37.usbdev_endpoint_access.228609662
Short name T320
Test name
Test status
Simulation time 842104555 ps
CPU time 2.24 seconds
Started Aug 05 05:38:46 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207620 kb
Host smart-cf405f4d-4fab-4e34-b85a-7cb05a84293c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22860
9662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.228609662
Directory /workspace/37.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/37.usbdev_endpoint_types.3804914692
Short name T335
Test name
Test status
Simulation time 458038791 ps
CPU time 1.25 seconds
Started Aug 05 05:38:38 PM PDT 24
Finished Aug 05 05:38:39 PM PDT 24
Peak memory 207372 kb
Host smart-40a620ee-bdc1-41dc-a3b2-d52e069d5f03
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3804914692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.3804914692
Directory /workspace/37.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/37.usbdev_fifo_rst.1698413028
Short name T766
Test name
Test status
Simulation time 185444699 ps
CPU time 1.44 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:50 PM PDT 24
Peak memory 207408 kb
Host smart-11b94893-560c-48e9-8434-22244fc9273e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16984
13028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1698413028
Directory /workspace/37.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/37.usbdev_in_iso.1195434094
Short name T2334
Test name
Test status
Simulation time 162430170 ps
CPU time 0.86 seconds
Started Aug 05 05:38:41 PM PDT 24
Finished Aug 05 05:38:42 PM PDT 24
Peak memory 207328 kb
Host smart-76c2df6e-ecc1-461d-af4b-58bdb58a75b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1195434094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1195434094
Directory /workspace/37.usbdev_in_iso/latest


Test location /workspace/coverage/default/37.usbdev_in_stall.3726613466
Short name T2921
Test name
Test status
Simulation time 140980698 ps
CPU time 0.79 seconds
Started Aug 05 05:38:38 PM PDT 24
Finished Aug 05 05:38:39 PM PDT 24
Peak memory 207308 kb
Host smart-d6ff4327-29ff-4350-a811-ef5af5f3a9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37266
13466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3726613466
Directory /workspace/37.usbdev_in_stall/latest


Test location /workspace/coverage/default/37.usbdev_in_trans.1982967888
Short name T2283
Test name
Test status
Simulation time 174603512 ps
CPU time 0.94 seconds
Started Aug 05 05:38:39 PM PDT 24
Finished Aug 05 05:38:41 PM PDT 24
Peak memory 207468 kb
Host smart-5fef4f92-355c-4dbd-9197-bb88fdd7f004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19829
67888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1982967888
Directory /workspace/37.usbdev_in_trans/latest


Test location /workspace/coverage/default/37.usbdev_invalid_sync.3380090120
Short name T1057
Test name
Test status
Simulation time 4724525178 ps
CPU time 137.25 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:41:02 PM PDT 24
Peak memory 224056 kb
Host smart-f37729ca-3d15-48b4-94a1-d6281e53e907
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3380090120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.3380090120
Directory /workspace/37.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/37.usbdev_iso_retraction.3549355696
Short name T943
Test name
Test status
Simulation time 14282498154 ps
CPU time 94.44 seconds
Started Aug 05 05:38:34 PM PDT 24
Finished Aug 05 05:40:08 PM PDT 24
Peak memory 207636 kb
Host smart-615d08ea-a3c2-489c-a3da-801d7efc0661
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3549355696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.3549355696
Directory /workspace/37.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/37.usbdev_link_in_err.998674847
Short name T1994
Test name
Test status
Simulation time 207790631 ps
CPU time 0.96 seconds
Started Aug 05 05:38:40 PM PDT 24
Finished Aug 05 05:38:41 PM PDT 24
Peak memory 207416 kb
Host smart-19ddbc0c-bc6d-4930-a6ce-5bbf2b64381c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99867
4847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.998674847
Directory /workspace/37.usbdev_link_in_err/latest


Test location /workspace/coverage/default/37.usbdev_link_resume.1788590054
Short name T1880
Test name
Test status
Simulation time 25504699877 ps
CPU time 40.59 seconds
Started Aug 05 05:38:34 PM PDT 24
Finished Aug 05 05:39:15 PM PDT 24
Peak memory 215808 kb
Host smart-7428af7d-b931-4b1d-bcfa-437a08330f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17885
90054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1788590054
Directory /workspace/37.usbdev_link_resume/latest


Test location /workspace/coverage/default/37.usbdev_link_suspend.3931252524
Short name T1567
Test name
Test status
Simulation time 8748549190 ps
CPU time 11.46 seconds
Started Aug 05 05:38:52 PM PDT 24
Finished Aug 05 05:39:03 PM PDT 24
Peak memory 207640 kb
Host smart-b35805cf-d6ec-4270-8330-a5f6393cb947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39312
52524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3931252524
Directory /workspace/37.usbdev_link_suspend/latest


Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.3207851983
Short name T577
Test name
Test status
Simulation time 4516535120 ps
CPU time 130.93 seconds
Started Aug 05 05:38:45 PM PDT 24
Finished Aug 05 05:40:56 PM PDT 24
Peak memory 218224 kb
Host smart-cf9d29c6-ae94-44c7-9e34-d4d7e96b2d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32078
51983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.3207851983
Directory /workspace/37.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.2176280754
Short name T2496
Test name
Test status
Simulation time 3692125420 ps
CPU time 106.86 seconds
Started Aug 05 05:38:43 PM PDT 24
Finished Aug 05 05:40:30 PM PDT 24
Peak memory 217128 kb
Host smart-28b7cbab-4ee9-479a-b08e-21d32490e760
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2176280754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.2176280754
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1008353300
Short name T3051
Test name
Test status
Simulation time 272829160 ps
CPU time 1.02 seconds
Started Aug 05 05:38:33 PM PDT 24
Finished Aug 05 05:38:34 PM PDT 24
Peak memory 207368 kb
Host smart-95adea94-3c05-48a1-be55-4a4792593f58
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1008353300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1008353300
Directory /workspace/37.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.312881144
Short name T705
Test name
Test status
Simulation time 188449029 ps
CPU time 0.96 seconds
Started Aug 05 05:38:44 PM PDT 24
Finished Aug 05 05:38:45 PM PDT 24
Peak memory 207272 kb
Host smart-376cce9b-b511-49e6-8fac-b395e89874f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31288
1144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.312881144
Directory /workspace/37.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.3144265393
Short name T2951
Test name
Test status
Simulation time 2835027480 ps
CPU time 21.16 seconds
Started Aug 05 05:38:46 PM PDT 24
Finished Aug 05 05:39:08 PM PDT 24
Peak memory 215868 kb
Host smart-dd9bf1d7-4711-4ac8-be07-badb46046ad6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3144265393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.3144265393
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1178158859
Short name T748
Test name
Test status
Simulation time 157756665 ps
CPU time 0.84 seconds
Started Aug 05 05:38:36 PM PDT 24
Finished Aug 05 05:38:37 PM PDT 24
Peak memory 207312 kb
Host smart-9ae50bc5-a102-44ed-a58c-17874d1a3f37
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1178158859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1178158859
Directory /workspace/37.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2478097042
Short name T1885
Test name
Test status
Simulation time 175418784 ps
CPU time 0.86 seconds
Started Aug 05 05:38:52 PM PDT 24
Finished Aug 05 05:38:53 PM PDT 24
Peak memory 207376 kb
Host smart-e9e8cd35-841d-4788-869b-ba3cae05cbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24780
97042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2478097042
Directory /workspace/37.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/37.usbdev_nak_trans.3601925172
Short name T132
Test name
Test status
Simulation time 281998995 ps
CPU time 1 seconds
Started Aug 05 05:38:34 PM PDT 24
Finished Aug 05 05:38:36 PM PDT 24
Peak memory 207368 kb
Host smart-6ca7a0c0-ce7a-419f-9aa7-d7349f026330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36019
25172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3601925172
Directory /workspace/37.usbdev_nak_trans/latest


Test location /workspace/coverage/default/37.usbdev_out_iso.729430986
Short name T860
Test name
Test status
Simulation time 238868693 ps
CPU time 1.03 seconds
Started Aug 05 05:38:39 PM PDT 24
Finished Aug 05 05:38:41 PM PDT 24
Peak memory 207272 kb
Host smart-7f170eca-384d-4637-8794-cd9b3e462723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72943
0986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.729430986
Directory /workspace/37.usbdev_out_iso/latest


Test location /workspace/coverage/default/37.usbdev_out_stall.3310268027
Short name T1878
Test name
Test status
Simulation time 213675611 ps
CPU time 0.91 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207228 kb
Host smart-ccd7adb3-929c-495f-b5ae-15c2a6d181de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33102
68027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3310268027
Directory /workspace/37.usbdev_out_stall/latest


Test location /workspace/coverage/default/37.usbdev_out_trans_nak.580031726
Short name T2944
Test name
Test status
Simulation time 156799254 ps
CPU time 0.92 seconds
Started Aug 05 05:38:38 PM PDT 24
Finished Aug 05 05:38:39 PM PDT 24
Peak memory 207276 kb
Host smart-42c6cfbd-f962-4bf4-8dfd-223f6879bc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58003
1726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.580031726
Directory /workspace/37.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3783970210
Short name T1868
Test name
Test status
Simulation time 236914041 ps
CPU time 0.99 seconds
Started Aug 05 05:38:40 PM PDT 24
Finished Aug 05 05:38:41 PM PDT 24
Peak memory 207468 kb
Host smart-87fc9985-97b0-45e1-9369-d3e5d0f9eecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37839
70210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3783970210
Directory /workspace/37.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.2210484527
Short name T1913
Test name
Test status
Simulation time 196932638 ps
CPU time 0.9 seconds
Started Aug 05 05:38:42 PM PDT 24
Finished Aug 05 05:38:43 PM PDT 24
Peak memory 207400 kb
Host smart-6eb3411b-34f3-4fb4-b549-1cbf32ab0bb3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2210484527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.2210484527
Directory /workspace/37.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2382678594
Short name T1243
Test name
Test status
Simulation time 174778190 ps
CPU time 0.88 seconds
Started Aug 05 05:38:54 PM PDT 24
Finished Aug 05 05:38:55 PM PDT 24
Peak memory 207264 kb
Host smart-b03d8844-6ce7-4672-9358-3e65992b398c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23826
78594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2382678594
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1051093017
Short name T2517
Test name
Test status
Simulation time 40011237 ps
CPU time 0.71 seconds
Started Aug 05 05:38:48 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207316 kb
Host smart-72ee74b0-56a0-4852-900e-51b54e25a010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10510
93017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1051093017
Directory /workspace/37.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1691127607
Short name T1522
Test name
Test status
Simulation time 18161769212 ps
CPU time 44.27 seconds
Started Aug 05 05:38:55 PM PDT 24
Finished Aug 05 05:39:39 PM PDT 24
Peak memory 215840 kb
Host smart-26603287-f7bf-4949-815c-3b00a1fb4362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16911
27607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1691127607
Directory /workspace/37.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/37.usbdev_pkt_received.759217744
Short name T1682
Test name
Test status
Simulation time 156352753 ps
CPU time 0.87 seconds
Started Aug 05 05:38:41 PM PDT 24
Finished Aug 05 05:38:42 PM PDT 24
Peak memory 207376 kb
Host smart-5b201405-7e00-436b-b32c-bae1823af06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75921
7744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.759217744
Directory /workspace/37.usbdev_pkt_received/latest


Test location /workspace/coverage/default/37.usbdev_pkt_sent.2674713683
Short name T1059
Test name
Test status
Simulation time 160612636 ps
CPU time 0.91 seconds
Started Aug 05 05:38:53 PM PDT 24
Finished Aug 05 05:38:54 PM PDT 24
Peak memory 207260 kb
Host smart-b1321109-ac64-4431-bc78-b91b76a26c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26747
13683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2674713683
Directory /workspace/37.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1251966061
Short name T1627
Test name
Test status
Simulation time 228379879 ps
CPU time 1.01 seconds
Started Aug 05 05:38:52 PM PDT 24
Finished Aug 05 05:38:54 PM PDT 24
Peak memory 207284 kb
Host smart-9f5a9654-9b0f-4814-b0ed-117dc3e77915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12519
66061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1251966061
Directory /workspace/37.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3007961367
Short name T1662
Test name
Test status
Simulation time 177081978 ps
CPU time 1.09 seconds
Started Aug 05 05:38:51 PM PDT 24
Finished Aug 05 05:38:52 PM PDT 24
Peak memory 207284 kb
Host smart-c92c81ee-8083-48b1-94a8-d567b8f1c0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30079
61367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3007961367
Directory /workspace/37.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3568119837
Short name T2744
Test name
Test status
Simulation time 168239412 ps
CPU time 0.89 seconds
Started Aug 05 05:38:47 PM PDT 24
Finished Aug 05 05:38:49 PM PDT 24
Peak memory 207284 kb
Host smart-4912fabd-aba7-4cfc-854d-826496ec45bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35681
19837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3568119837
Directory /workspace/37.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/37.usbdev_rx_full.3033201943
Short name T1358
Test name
Test status
Simulation time 356197996 ps
CPU time 1.16 seconds
Started Aug 05 05:38:53 PM PDT 24
Finished Aug 05 05:39:00 PM PDT 24
Peak memory 207224 kb
Host smart-2ec53608-bc6c-462d-9ff9-d8599a2b886a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30332
01943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.3033201943
Directory /workspace/37.usbdev_rx_full/latest


Test location /workspace/coverage/default/37.usbdev_setup_stage.2571578371
Short name T2950
Test name
Test status
Simulation time 149223621 ps
CPU time 0.84 seconds
Started Aug 05 05:38:52 PM PDT 24
Finished Aug 05 05:38:53 PM PDT 24
Peak memory 207264 kb
Host smart-6898324a-aa46-4b25-a3a9-3f454043c910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25715
78371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2571578371
Directory /workspace/37.usbdev_setup_stage/latest


Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2551065381
Short name T2527
Test name
Test status
Simulation time 203065784 ps
CPU time 0.95 seconds
Started Aug 05 05:39:10 PM PDT 24
Finished Aug 05 05:39:11 PM PDT 24
Peak memory 207336 kb
Host smart-78a9dbed-f132-4a31-8d8e-5f619c996402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25510
65381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2551065381
Directory /workspace/37.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/37.usbdev_smoke.999065747
Short name T1276
Test name
Test status
Simulation time 204035838 ps
CPU time 0.97 seconds
Started Aug 05 05:38:53 PM PDT 24
Finished Aug 05 05:38:55 PM PDT 24
Peak memory 207324 kb
Host smart-8fa6ba5e-e51b-443a-bd0d-382620f554a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99906
5747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.999065747
Directory /workspace/37.usbdev_smoke/latest


Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.1654825692
Short name T1017
Test name
Test status
Simulation time 2071515121 ps
CPU time 20.66 seconds
Started Aug 05 05:38:49 PM PDT 24
Finished Aug 05 05:39:10 PM PDT 24
Peak memory 217264 kb
Host smart-2dbb6118-1e5f-4987-a96b-f219ad7d150d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1654825692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.1654825692
Directory /workspace/37.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3957212499
Short name T868
Test name
Test status
Simulation time 203245321 ps
CPU time 0.94 seconds
Started Aug 05 05:38:55 PM PDT 24
Finished Aug 05 05:38:56 PM PDT 24
Peak memory 207400 kb
Host smart-1c71798e-d476-47d8-8692-b2babec2ffda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39572
12499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3957212499
Directory /workspace/37.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/37.usbdev_stall_trans.4034535188
Short name T2251
Test name
Test status
Simulation time 148598068 ps
CPU time 0.81 seconds
Started Aug 05 05:38:50 PM PDT 24
Finished Aug 05 05:38:51 PM PDT 24
Peak memory 207228 kb
Host smart-d7450c02-0149-4d39-8a2b-3faf58775f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40345
35188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.4034535188
Directory /workspace/37.usbdev_stall_trans/latest


Test location /workspace/coverage/default/37.usbdev_stream_len_max.399443019
Short name T534
Test name
Test status
Simulation time 1028934784 ps
CPU time 2.54 seconds
Started Aug 05 05:38:53 PM PDT 24
Finished Aug 05 05:38:55 PM PDT 24
Peak memory 207496 kb
Host smart-9c2de784-e25b-4ffc-bc67-755045bfa191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39944
3019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.399443019
Directory /workspace/37.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/37.usbdev_streaming_out.2826386287
Short name T502
Test name
Test status
Simulation time 3196263849 ps
CPU time 27.37 seconds
Started Aug 05 05:38:47 PM PDT 24
Finished Aug 05 05:39:15 PM PDT 24
Peak memory 217492 kb
Host smart-af2535d0-c66b-4167-9be3-879357921467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28263
86287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2826386287
Directory /workspace/37.usbdev_streaming_out/latest


Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.750323480
Short name T1932
Test name
Test status
Simulation time 2598810591 ps
CPU time 17.4 seconds
Started Aug 05 05:38:49 PM PDT 24
Finished Aug 05 05:39:06 PM PDT 24
Peak memory 207660 kb
Host smart-002310b6-eae6-4c1d-9207-b94b9c3abf9c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750323480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_host
_handshake.750323480
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/38.usbdev_alert_test.2767185795
Short name T1356
Test name
Test status
Simulation time 36260238 ps
CPU time 0.69 seconds
Started Aug 05 05:38:53 PM PDT 24
Finished Aug 05 05:38:53 PM PDT 24
Peak memory 207412 kb
Host smart-1f202c6f-5854-42e2-aedd-e9e83c64e9c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2767185795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.2767185795
Directory /workspace/38.usbdev_alert_test/latest


Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2444718874
Short name T2941
Test name
Test status
Simulation time 5662521918 ps
CPU time 7.82 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:07 PM PDT 24
Peak memory 215820 kb
Host smart-b38c9877-21bc-4d73-9853-25b6af846719
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444718874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.2444718874
Directory /workspace/38.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.4245445542
Short name T2949
Test name
Test status
Simulation time 14916896765 ps
CPU time 18.12 seconds
Started Aug 05 05:38:58 PM PDT 24
Finished Aug 05 05:39:16 PM PDT 24
Peak memory 215768 kb
Host smart-920a0aa1-e40c-4133-a060-b5f1186f6d09
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245445542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.4245445542
Directory /workspace/38.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1583260124
Short name T2150
Test name
Test status
Simulation time 31255106587 ps
CPU time 41.28 seconds
Started Aug 05 05:38:51 PM PDT 24
Finished Aug 05 05:39:33 PM PDT 24
Peak memory 207672 kb
Host smart-ade8be77-f030-41d1-a608-8f078ce6b846
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583260124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_resume.1583260124
Directory /workspace/38.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/38.usbdev_av_buffer.689331710
Short name T3089
Test name
Test status
Simulation time 190193127 ps
CPU time 0.84 seconds
Started Aug 05 05:38:58 PM PDT 24
Finished Aug 05 05:38:59 PM PDT 24
Peak memory 207368 kb
Host smart-b2b374c6-8e99-4a25-b612-b651a9aa729d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68933
1710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.689331710
Directory /workspace/38.usbdev_av_buffer/latest


Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1375747734
Short name T2670
Test name
Test status
Simulation time 141863261 ps
CPU time 0.85 seconds
Started Aug 05 05:38:58 PM PDT 24
Finished Aug 05 05:38:59 PM PDT 24
Peak memory 207296 kb
Host smart-42ab10dd-f522-45e9-b9f6-6be874077aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13757
47734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1375747734
Directory /workspace/38.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.1517224486
Short name T2023
Test name
Test status
Simulation time 245980289 ps
CPU time 1.06 seconds
Started Aug 05 05:38:53 PM PDT 24
Finished Aug 05 05:38:55 PM PDT 24
Peak memory 207612 kb
Host smart-4abd45e3-ca24-409f-95cb-04fa8efe73f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15172
24486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.1517224486
Directory /workspace/38.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3118917816
Short name T2776
Test name
Test status
Simulation time 394956825 ps
CPU time 1.45 seconds
Started Aug 05 05:38:53 PM PDT 24
Finished Aug 05 05:38:54 PM PDT 24
Peak memory 207232 kb
Host smart-96f5e6d8-8bac-4be8-b9ef-9d1b930d28f5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3118917816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3118917816
Directory /workspace/38.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/38.usbdev_device_address.2354973022
Short name T1642
Test name
Test status
Simulation time 56620125432 ps
CPU time 96.69 seconds
Started Aug 05 05:38:56 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207588 kb
Host smart-67a2c3fb-44e0-445c-ab27-bc5564274ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23549
73022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.2354973022
Directory /workspace/38.usbdev_device_address/latest


Test location /workspace/coverage/default/38.usbdev_device_timeout.708469059
Short name T887
Test name
Test status
Simulation time 2453527418 ps
CPU time 20.94 seconds
Started Aug 05 05:39:01 PM PDT 24
Finished Aug 05 05:39:22 PM PDT 24
Peak memory 207712 kb
Host smart-f96286f9-2e3b-463f-aea2-86cf85305991
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708469059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.708469059
Directory /workspace/38.usbdev_device_timeout/latest


Test location /workspace/coverage/default/38.usbdev_disable_endpoint.3659836586
Short name T2101
Test name
Test status
Simulation time 752428852 ps
CPU time 1.75 seconds
Started Aug 05 05:38:56 PM PDT 24
Finished Aug 05 05:38:58 PM PDT 24
Peak memory 207396 kb
Host smart-3723a94d-30af-4607-8f73-e95b06707839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36598
36586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.3659836586
Directory /workspace/38.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/38.usbdev_disconnected.1234374086
Short name T2838
Test name
Test status
Simulation time 147230932 ps
CPU time 0.78 seconds
Started Aug 05 05:38:57 PM PDT 24
Finished Aug 05 05:38:58 PM PDT 24
Peak memory 207360 kb
Host smart-5eadf9d6-c36e-4c68-9fb4-bf1998b37fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12343
74086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.1234374086
Directory /workspace/38.usbdev_disconnected/latest


Test location /workspace/coverage/default/38.usbdev_enable.1648008174
Short name T1261
Test name
Test status
Simulation time 41215370 ps
CPU time 0.68 seconds
Started Aug 05 05:39:20 PM PDT 24
Finished Aug 05 05:39:21 PM PDT 24
Peak memory 207256 kb
Host smart-ab33338c-05f6-4fde-8f06-b4ee6c74cd03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16480
08174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1648008174
Directory /workspace/38.usbdev_enable/latest


Test location /workspace/coverage/default/38.usbdev_endpoint_access.395777241
Short name T2927
Test name
Test status
Simulation time 934935473 ps
CPU time 2.43 seconds
Started Aug 05 05:38:53 PM PDT 24
Finished Aug 05 05:38:56 PM PDT 24
Peak memory 207500 kb
Host smart-bbe43c1f-6ada-4711-94a7-89606ab7c7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39577
7241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.395777241
Directory /workspace/38.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/38.usbdev_endpoint_types.1452502313
Short name T2030
Test name
Test status
Simulation time 228039632 ps
CPU time 1.12 seconds
Started Aug 05 05:38:49 PM PDT 24
Finished Aug 05 05:38:50 PM PDT 24
Peak memory 207404 kb
Host smart-d4c22f83-4ce1-4321-be41-29de92486071
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1452502313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.1452502313
Directory /workspace/38.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/38.usbdev_fifo_rst.3981742460
Short name T1532
Test name
Test status
Simulation time 205882913 ps
CPU time 1.99 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:01 PM PDT 24
Peak memory 207612 kb
Host smart-da60ea7e-377d-498c-9c90-31c72b99aaed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39817
42460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3981742460
Directory /workspace/38.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/38.usbdev_in_iso.1642274192
Short name T1898
Test name
Test status
Simulation time 233533663 ps
CPU time 1.1 seconds
Started Aug 05 05:39:00 PM PDT 24
Finished Aug 05 05:39:01 PM PDT 24
Peak memory 207488 kb
Host smart-2517f3d3-3228-4d31-89cc-b733a22db17c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1642274192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.1642274192
Directory /workspace/38.usbdev_in_iso/latest


Test location /workspace/coverage/default/38.usbdev_in_stall.3300541225
Short name T1430
Test name
Test status
Simulation time 167299397 ps
CPU time 0.84 seconds
Started Aug 05 05:39:13 PM PDT 24
Finished Aug 05 05:39:14 PM PDT 24
Peak memory 207320 kb
Host smart-b4f039f5-3310-4dd0-b767-ff904f9d1703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33005
41225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3300541225
Directory /workspace/38.usbdev_in_stall/latest


Test location /workspace/coverage/default/38.usbdev_in_trans.1367122043
Short name T2885
Test name
Test status
Simulation time 205274662 ps
CPU time 0.95 seconds
Started Aug 05 05:39:04 PM PDT 24
Finished Aug 05 05:39:05 PM PDT 24
Peak memory 207396 kb
Host smart-a21fc7ea-4817-4522-8ab1-d80d9c218dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13671
22043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1367122043
Directory /workspace/38.usbdev_in_trans/latest


Test location /workspace/coverage/default/38.usbdev_invalid_sync.765262831
Short name T2478
Test name
Test status
Simulation time 4227726278 ps
CPU time 31.58 seconds
Started Aug 05 05:38:58 PM PDT 24
Finished Aug 05 05:39:30 PM PDT 24
Peak memory 215912 kb
Host smart-f4c58ee7-68b5-40c7-b9f2-fb050dcb2f7f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=765262831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.765262831
Directory /workspace/38.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/38.usbdev_iso_retraction.2929524892
Short name T2486
Test name
Test status
Simulation time 8960442507 ps
CPU time 110.1 seconds
Started Aug 05 05:38:55 PM PDT 24
Finished Aug 05 05:40:46 PM PDT 24
Peak memory 207668 kb
Host smart-457d427f-0d44-4d60-9d94-0f5068f89386
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2929524892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.2929524892
Directory /workspace/38.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/38.usbdev_link_in_err.4288550812
Short name T1808
Test name
Test status
Simulation time 260937289 ps
CPU time 1.04 seconds
Started Aug 05 05:39:03 PM PDT 24
Finished Aug 05 05:39:04 PM PDT 24
Peak memory 207376 kb
Host smart-d3a436b2-2f43-4cba-ad60-987e049b24ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42885
50812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.4288550812
Directory /workspace/38.usbdev_link_in_err/latest


Test location /workspace/coverage/default/38.usbdev_link_resume.389123809
Short name T852
Test name
Test status
Simulation time 8811126357 ps
CPU time 15.45 seconds
Started Aug 05 05:38:54 PM PDT 24
Finished Aug 05 05:39:09 PM PDT 24
Peak memory 215812 kb
Host smart-b664f201-2671-4708-930b-17f06b117822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38912
3809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.389123809
Directory /workspace/38.usbdev_link_resume/latest


Test location /workspace/coverage/default/38.usbdev_link_suspend.906293136
Short name T2242
Test name
Test status
Simulation time 9311033082 ps
CPU time 11.91 seconds
Started Aug 05 05:38:52 PM PDT 24
Finished Aug 05 05:39:04 PM PDT 24
Peak memory 207624 kb
Host smart-08e689ea-53dd-4e8d-9688-e9baf69d19b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90629
3136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.906293136
Directory /workspace/38.usbdev_link_suspend/latest


Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.3333909077
Short name T582
Test name
Test status
Simulation time 2648631210 ps
CPU time 18.56 seconds
Started Aug 05 05:39:21 PM PDT 24
Finished Aug 05 05:39:40 PM PDT 24
Peak memory 223980 kb
Host smart-c6ed0e03-1d9e-450a-acdc-6f3b002af74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33339
09077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.3333909077
Directory /workspace/38.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.796316381
Short name T2360
Test name
Test status
Simulation time 2314770456 ps
CPU time 25.98 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 224016 kb
Host smart-db44d98e-425d-454d-8341-222945c9ac9c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=796316381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.796316381
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3962909997
Short name T742
Test name
Test status
Simulation time 314364423 ps
CPU time 1.04 seconds
Started Aug 05 05:39:18 PM PDT 24
Finished Aug 05 05:39:19 PM PDT 24
Peak memory 207300 kb
Host smart-08a95d76-b824-43c7-afd0-e5de67b97973
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3962909997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3962909997
Directory /workspace/38.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1550573728
Short name T2339
Test name
Test status
Simulation time 252978697 ps
CPU time 1.11 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:00 PM PDT 24
Peak memory 207400 kb
Host smart-2868f7a1-6e94-48aa-a3c4-729964bfdf16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15505
73728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1550573728
Directory /workspace/38.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1073889821
Short name T2278
Test name
Test status
Simulation time 3264064760 ps
CPU time 24.59 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 215928 kb
Host smart-63e9d98c-a0b9-4011-8db4-bbc0ac067d17
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1073889821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1073889821
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.2410167923
Short name T2049
Test name
Test status
Simulation time 189534990 ps
CPU time 0.91 seconds
Started Aug 05 05:38:50 PM PDT 24
Finished Aug 05 05:38:52 PM PDT 24
Peak memory 207416 kb
Host smart-6b4d82de-0573-4520-8319-69999cb9a77f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2410167923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.2410167923
Directory /workspace/38.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.719616377
Short name T526
Test name
Test status
Simulation time 138965410 ps
CPU time 0.84 seconds
Started Aug 05 05:39:02 PM PDT 24
Finished Aug 05 05:39:03 PM PDT 24
Peak memory 207348 kb
Host smart-2881a1d7-e55c-4f56-975e-be50f1246294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71961
6377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.719616377
Directory /workspace/38.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/38.usbdev_nak_trans.344883127
Short name T136
Test name
Test status
Simulation time 223354126 ps
CPU time 0.95 seconds
Started Aug 05 05:39:18 PM PDT 24
Finished Aug 05 05:39:19 PM PDT 24
Peak memory 207296 kb
Host smart-d8f4a218-8d44-4be1-be0a-5df766315b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34488
3127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.344883127
Directory /workspace/38.usbdev_nak_trans/latest


Test location /workspace/coverage/default/38.usbdev_out_iso.1247365805
Short name T2922
Test name
Test status
Simulation time 200326943 ps
CPU time 0.92 seconds
Started Aug 05 05:38:56 PM PDT 24
Finished Aug 05 05:38:57 PM PDT 24
Peak memory 207268 kb
Host smart-c2e244f3-78a9-44e3-b4ae-627ed9e146bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12473
65805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1247365805
Directory /workspace/38.usbdev_out_iso/latest


Test location /workspace/coverage/default/38.usbdev_out_stall.1527177121
Short name T1060
Test name
Test status
Simulation time 251174060 ps
CPU time 0.95 seconds
Started Aug 05 05:38:57 PM PDT 24
Finished Aug 05 05:38:58 PM PDT 24
Peak memory 207396 kb
Host smart-1e5a3c55-d64d-46ae-a0de-33d338f5f7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15271
77121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1527177121
Directory /workspace/38.usbdev_out_stall/latest


Test location /workspace/coverage/default/38.usbdev_out_trans_nak.4094720051
Short name T2805
Test name
Test status
Simulation time 230048921 ps
CPU time 0.97 seconds
Started Aug 05 05:38:56 PM PDT 24
Finished Aug 05 05:38:57 PM PDT 24
Peak memory 207340 kb
Host smart-c856f8dc-7ec3-4f95-9472-36356861296f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40947
20051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.4094720051
Directory /workspace/38.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/38.usbdev_pending_in_trans.218549945
Short name T2681
Test name
Test status
Simulation time 187750049 ps
CPU time 0.9 seconds
Started Aug 05 05:38:54 PM PDT 24
Finished Aug 05 05:38:55 PM PDT 24
Peak memory 207276 kb
Host smart-ab5c1c5e-a9e2-446b-818b-335e505f23a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21854
9945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.218549945
Directory /workspace/38.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2164530703
Short name T3054
Test name
Test status
Simulation time 221360339 ps
CPU time 1.01 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:00 PM PDT 24
Peak memory 207324 kb
Host smart-c540859a-027b-4e1e-9921-54deca7ac7ac
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2164530703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2164530703
Directory /workspace/38.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3490978565
Short name T2451
Test name
Test status
Simulation time 154750946 ps
CPU time 0.87 seconds
Started Aug 05 05:39:09 PM PDT 24
Finished Aug 05 05:39:10 PM PDT 24
Peak memory 207296 kb
Host smart-bd3027bb-25b9-45c9-aa08-3f7b1695b654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34909
78565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3490978565
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.938322321
Short name T2850
Test name
Test status
Simulation time 96406479 ps
CPU time 0.78 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:00 PM PDT 24
Peak memory 207236 kb
Host smart-dae34fb3-d805-49e4-9a3b-c57b2a4956f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93832
2321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.938322321
Directory /workspace/38.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/38.usbdev_pkt_buffer.980534316
Short name T1934
Test name
Test status
Simulation time 8503696582 ps
CPU time 26.23 seconds
Started Aug 05 05:38:57 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 215948 kb
Host smart-e3ccaa0e-1933-48a2-b277-349cd5398360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98053
4316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.980534316
Directory /workspace/38.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/38.usbdev_pkt_received.2788324367
Short name T2256
Test name
Test status
Simulation time 148085497 ps
CPU time 0.85 seconds
Started Aug 05 05:39:01 PM PDT 24
Finished Aug 05 05:39:02 PM PDT 24
Peak memory 207352 kb
Host smart-ff7112b1-1c7e-40c1-b145-92d5421255de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27883
24367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2788324367
Directory /workspace/38.usbdev_pkt_received/latest


Test location /workspace/coverage/default/38.usbdev_pkt_sent.2279235207
Short name T3099
Test name
Test status
Simulation time 227902228 ps
CPU time 0.91 seconds
Started Aug 05 05:38:58 PM PDT 24
Finished Aug 05 05:38:59 PM PDT 24
Peak memory 207284 kb
Host smart-56a4aa48-6cee-40fb-bb6d-d52f33d44a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22792
35207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2279235207
Directory /workspace/38.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.37351686
Short name T629
Test name
Test status
Simulation time 194759549 ps
CPU time 0.93 seconds
Started Aug 05 05:39:11 PM PDT 24
Finished Aug 05 05:39:12 PM PDT 24
Peak memory 207296 kb
Host smart-c59dc4c4-133b-4404-9e54-7f4febe428ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37351
686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.37351686
Directory /workspace/38.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3641936417
Short name T862
Test name
Test status
Simulation time 175523292 ps
CPU time 0.88 seconds
Started Aug 05 05:39:08 PM PDT 24
Finished Aug 05 05:39:09 PM PDT 24
Peak memory 207340 kb
Host smart-23dc9fbe-7bb5-4e34-952d-3cb2f004a927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36419
36417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3641936417
Directory /workspace/38.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3992394248
Short name T681
Test name
Test status
Simulation time 141894968 ps
CPU time 0.82 seconds
Started Aug 05 05:38:53 PM PDT 24
Finished Aug 05 05:38:54 PM PDT 24
Peak memory 207272 kb
Host smart-d5ba383f-1ef6-40d4-9c2c-1fd1929f62aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39923
94248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3992394248
Directory /workspace/38.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/38.usbdev_rx_full.1897907620
Short name T1923
Test name
Test status
Simulation time 358892057 ps
CPU time 1.29 seconds
Started Aug 05 05:39:25 PM PDT 24
Finished Aug 05 05:39:26 PM PDT 24
Peak memory 207292 kb
Host smart-9c16f202-06f3-42a9-a491-e9d632749a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18979
07620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.1897907620
Directory /workspace/38.usbdev_rx_full/latest


Test location /workspace/coverage/default/38.usbdev_setup_stage.1615787302
Short name T2320
Test name
Test status
Simulation time 178095206 ps
CPU time 0.86 seconds
Started Aug 05 05:38:56 PM PDT 24
Finished Aug 05 05:38:57 PM PDT 24
Peak memory 207348 kb
Host smart-a9a6ed2c-c97a-4447-99ce-9c4a48c8d49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16157
87302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1615787302
Directory /workspace/38.usbdev_setup_stage/latest


Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1130120585
Short name T2057
Test name
Test status
Simulation time 158340782 ps
CPU time 0.86 seconds
Started Aug 05 05:39:00 PM PDT 24
Finished Aug 05 05:39:01 PM PDT 24
Peak memory 207380 kb
Host smart-33ae112c-c1bd-4515-8bc2-3c81183bfefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11301
20585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1130120585
Directory /workspace/38.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/38.usbdev_smoke.972549609
Short name T49
Test name
Test status
Simulation time 241190541 ps
CPU time 1.07 seconds
Started Aug 05 05:38:55 PM PDT 24
Finished Aug 05 05:38:57 PM PDT 24
Peak memory 207348 kb
Host smart-604eb34e-07f3-4508-912f-e2f36d8850a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97254
9609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.972549609
Directory /workspace/38.usbdev_smoke/latest


Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.504201066
Short name T642
Test name
Test status
Simulation time 2195815415 ps
CPU time 17.08 seconds
Started Aug 05 05:39:10 PM PDT 24
Finished Aug 05 05:39:32 PM PDT 24
Peak memory 223952 kb
Host smart-5991e201-86a4-4767-b367-fdef7a52f584
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=504201066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.504201066
Directory /workspace/38.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.245453479
Short name T2176
Test name
Test status
Simulation time 209279244 ps
CPU time 0.94 seconds
Started Aug 05 05:38:54 PM PDT 24
Finished Aug 05 05:39:05 PM PDT 24
Peak memory 207324 kb
Host smart-194e4f68-3d9a-45fc-b180-1c3f91e7c1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24545
3479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.245453479
Directory /workspace/38.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/38.usbdev_stall_trans.3154252153
Short name T942
Test name
Test status
Simulation time 171015607 ps
CPU time 0.87 seconds
Started Aug 05 05:38:51 PM PDT 24
Finished Aug 05 05:38:52 PM PDT 24
Peak memory 207348 kb
Host smart-356a6485-258d-494d-9125-e99dea5310a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31542
52153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3154252153
Directory /workspace/38.usbdev_stall_trans/latest


Test location /workspace/coverage/default/38.usbdev_stream_len_max.2752242230
Short name T1317
Test name
Test status
Simulation time 607041497 ps
CPU time 1.73 seconds
Started Aug 05 05:38:55 PM PDT 24
Finished Aug 05 05:38:57 PM PDT 24
Peak memory 207308 kb
Host smart-ab2030a1-8a46-4c28-888f-d183972980ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27522
42230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2752242230
Directory /workspace/38.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/38.usbdev_streaming_out.2835148933
Short name T1830
Test name
Test status
Simulation time 2862538331 ps
CPU time 81.44 seconds
Started Aug 05 05:38:57 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 215928 kb
Host smart-6623c598-0459-4238-a441-2fca0cbb7a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28351
48933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2835148933
Directory /workspace/38.usbdev_streaming_out/latest


Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.2379812186
Short name T2811
Test name
Test status
Simulation time 430154052 ps
CPU time 7.6 seconds
Started Aug 05 05:39:05 PM PDT 24
Finished Aug 05 05:39:13 PM PDT 24
Peak memory 207500 kb
Host smart-0522d5dd-4110-4295-9327-d3e756390c72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379812186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.2379812186
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/39.usbdev_alert_test.3614625323
Short name T1549
Test name
Test status
Simulation time 47388415 ps
CPU time 0.64 seconds
Started Aug 05 05:39:16 PM PDT 24
Finished Aug 05 05:39:17 PM PDT 24
Peak memory 207476 kb
Host smart-69b5e410-a959-4641-a930-68d47170fda7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3614625323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.3614625323
Directory /workspace/39.usbdev_alert_test/latest


Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.4268893365
Short name T874
Test name
Test status
Simulation time 4070716720 ps
CPU time 5.72 seconds
Started Aug 05 05:38:55 PM PDT 24
Finished Aug 05 05:39:01 PM PDT 24
Peak memory 215812 kb
Host smart-a7ed79dd-ab10-43e7-8872-6dcf01ae4996
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268893365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.4268893365
Directory /workspace/39.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.629619857
Short name T11
Test name
Test status
Simulation time 19331804590 ps
CPU time 22.31 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:46 PM PDT 24
Peak memory 207564 kb
Host smart-ae1b3fb9-6572-47c4-a287-08822c57d3f0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=629619857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.629619857
Directory /workspace/39.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.4080558816
Short name T197
Test name
Test status
Simulation time 23417910507 ps
CPU time 29.56 seconds
Started Aug 05 05:39:04 PM PDT 24
Finished Aug 05 05:39:34 PM PDT 24
Peak memory 216044 kb
Host smart-d85950b6-15ac-4c03-bf77-13c3408d5418
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080558816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.4080558816
Directory /workspace/39.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/39.usbdev_av_buffer.3395872484
Short name T667
Test name
Test status
Simulation time 149703632 ps
CPU time 0.86 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:01 PM PDT 24
Peak memory 207416 kb
Host smart-32be4fd6-23b6-4fab-bc38-46a5afb925f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33958
72484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3395872484
Directory /workspace/39.usbdev_av_buffer/latest


Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2075079422
Short name T3127
Test name
Test status
Simulation time 134651390 ps
CPU time 0.78 seconds
Started Aug 05 05:39:04 PM PDT 24
Finished Aug 05 05:39:05 PM PDT 24
Peak memory 207280 kb
Host smart-ee441eb8-1000-40fb-84b2-e8c4c19474b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20750
79422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2075079422
Directory /workspace/39.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1025658360
Short name T2016
Test name
Test status
Simulation time 416447476 ps
CPU time 1.35 seconds
Started Aug 05 05:39:08 PM PDT 24
Finished Aug 05 05:39:09 PM PDT 24
Peak memory 207344 kb
Host smart-5deaaf76-dfa6-4fce-9cf0-b25738be40d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10256
58360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1025658360
Directory /workspace/39.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1346295081
Short name T797
Test name
Test status
Simulation time 944447484 ps
CPU time 2.65 seconds
Started Aug 05 05:39:04 PM PDT 24
Finished Aug 05 05:39:07 PM PDT 24
Peak memory 207444 kb
Host smart-7ed2dade-4e16-4299-a3bb-f2c87a2a10bc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1346295081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1346295081
Directory /workspace/39.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/39.usbdev_device_address.2759659824
Short name T1141
Test name
Test status
Simulation time 18059954035 ps
CPU time 29.44 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:53 PM PDT 24
Peak memory 207576 kb
Host smart-50fc9a1e-58e9-4d98-ba0e-d272ae2e2624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27596
59824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2759659824
Directory /workspace/39.usbdev_device_address/latest


Test location /workspace/coverage/default/39.usbdev_device_timeout.3891216035
Short name T593
Test name
Test status
Simulation time 1036439333 ps
CPU time 23.85 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 207420 kb
Host smart-bf551159-745e-45cb-8a94-7d6ca74da451
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891216035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.3891216035
Directory /workspace/39.usbdev_device_timeout/latest


Test location /workspace/coverage/default/39.usbdev_disable_endpoint.3880361789
Short name T1870
Test name
Test status
Simulation time 642459176 ps
CPU time 1.64 seconds
Started Aug 05 05:39:03 PM PDT 24
Finished Aug 05 05:39:04 PM PDT 24
Peak memory 207244 kb
Host smart-baaf6d0a-43d1-4bf0-8348-7a159c0751e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38803
61789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.3880361789
Directory /workspace/39.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/39.usbdev_disconnected.1846451999
Short name T1918
Test name
Test status
Simulation time 140713688 ps
CPU time 0.84 seconds
Started Aug 05 05:39:06 PM PDT 24
Finished Aug 05 05:39:07 PM PDT 24
Peak memory 207252 kb
Host smart-332fc692-e7a6-46c9-b5bf-5f0d0f1d3c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18464
51999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1846451999
Directory /workspace/39.usbdev_disconnected/latest


Test location /workspace/coverage/default/39.usbdev_enable.3143189560
Short name T1504
Test name
Test status
Simulation time 63435353 ps
CPU time 0.71 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:00 PM PDT 24
Peak memory 207364 kb
Host smart-aa5a5a71-adfe-460a-8f5d-94bc1acce5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31431
89560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3143189560
Directory /workspace/39.usbdev_enable/latest


Test location /workspace/coverage/default/39.usbdev_endpoint_access.2774142172
Short name T1746
Test name
Test status
Simulation time 960300663 ps
CPU time 2.58 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:02 PM PDT 24
Peak memory 207488 kb
Host smart-be4afdb6-3463-4e10-87d8-91f318201e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27741
42172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2774142172
Directory /workspace/39.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/39.usbdev_endpoint_types.1157615781
Short name T406
Test name
Test status
Simulation time 644197898 ps
CPU time 1.53 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:01 PM PDT 24
Peak memory 207244 kb
Host smart-25eb81fd-0ac0-425b-a6c9-3289cc0a23a9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1157615781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.1157615781
Directory /workspace/39.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/39.usbdev_fifo_rst.2535824369
Short name T996
Test name
Test status
Simulation time 388043767 ps
CPU time 2.75 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:02 PM PDT 24
Peak memory 207528 kb
Host smart-1aad934d-03a7-4c88-8d91-78ee543459b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25358
24369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2535824369
Directory /workspace/39.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/39.usbdev_in_iso.2327698306
Short name T1238
Test name
Test status
Simulation time 171584542 ps
CPU time 0.94 seconds
Started Aug 05 05:38:56 PM PDT 24
Finished Aug 05 05:38:57 PM PDT 24
Peak memory 207404 kb
Host smart-01265973-a763-49c5-b078-6cd398d25653
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2327698306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2327698306
Directory /workspace/39.usbdev_in_iso/latest


Test location /workspace/coverage/default/39.usbdev_in_stall.4068184400
Short name T1098
Test name
Test status
Simulation time 148874099 ps
CPU time 0.81 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:00 PM PDT 24
Peak memory 207436 kb
Host smart-282044a7-4e6b-48a3-ac80-4f61225c60b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40681
84400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.4068184400
Directory /workspace/39.usbdev_in_stall/latest


Test location /workspace/coverage/default/39.usbdev_in_trans.1789559137
Short name T730
Test name
Test status
Simulation time 209593920 ps
CPU time 0.98 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 207232 kb
Host smart-14c8eb31-9024-47e2-847b-985f0a34048c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17895
59137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1789559137
Directory /workspace/39.usbdev_in_trans/latest


Test location /workspace/coverage/default/39.usbdev_invalid_sync.1521403538
Short name T1138
Test name
Test status
Simulation time 2373690706 ps
CPU time 24.54 seconds
Started Aug 05 05:39:03 PM PDT 24
Finished Aug 05 05:39:27 PM PDT 24
Peak memory 217760 kb
Host smart-ea8d4a5c-25b5-4273-8ca1-ad3f4f8ebdee
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1521403538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.1521403538
Directory /workspace/39.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/39.usbdev_iso_retraction.1416022323
Short name T977
Test name
Test status
Simulation time 12711005586 ps
CPU time 89.53 seconds
Started Aug 05 05:38:57 PM PDT 24
Finished Aug 05 05:40:27 PM PDT 24
Peak memory 207660 kb
Host smart-4f07dc3c-5a7a-41f8-9055-9f6cdf793ec5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1416022323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.1416022323
Directory /workspace/39.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/39.usbdev_link_in_err.954223657
Short name T2535
Test name
Test status
Simulation time 211755872 ps
CPU time 0.99 seconds
Started Aug 05 05:38:57 PM PDT 24
Finished Aug 05 05:38:58 PM PDT 24
Peak memory 207376 kb
Host smart-4bd066b7-1fb8-4dac-989a-9a73ed95d5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95422
3657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.954223657
Directory /workspace/39.usbdev_link_in_err/latest


Test location /workspace/coverage/default/39.usbdev_link_resume.3285391627
Short name T2396
Test name
Test status
Simulation time 14277223427 ps
CPU time 19.57 seconds
Started Aug 05 05:39:19 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 207592 kb
Host smart-43e476ad-0e51-40d6-860f-4277140d84a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32853
91627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.3285391627
Directory /workspace/39.usbdev_link_resume/latest


Test location /workspace/coverage/default/39.usbdev_link_suspend.1098591336
Short name T2099
Test name
Test status
Simulation time 9943769399 ps
CPU time 11.45 seconds
Started Aug 05 05:38:56 PM PDT 24
Finished Aug 05 05:39:08 PM PDT 24
Peak memory 207628 kb
Host smart-237550e4-d295-43ba-833c-1037acfc10bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10985
91336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1098591336
Directory /workspace/39.usbdev_link_suspend/latest


Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.611730169
Short name T1781
Test name
Test status
Simulation time 3667779927 ps
CPU time 110.93 seconds
Started Aug 05 05:38:58 PM PDT 24
Finished Aug 05 05:40:49 PM PDT 24
Peak memory 218564 kb
Host smart-d5abc38f-07e2-4cea-89be-4dda1ffa11fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61173
0169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.611730169
Directory /workspace/39.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.1743213356
Short name T1425
Test name
Test status
Simulation time 3551718898 ps
CPU time 107.99 seconds
Started Aug 05 05:39:03 PM PDT 24
Finished Aug 05 05:40:51 PM PDT 24
Peak memory 217256 kb
Host smart-689ab0b1-25f7-4ced-98f9-13f7fe897af0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1743213356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.1743213356
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.3589932746
Short name T753
Test name
Test status
Simulation time 312015721 ps
CPU time 1.14 seconds
Started Aug 05 05:38:55 PM PDT 24
Finished Aug 05 05:38:56 PM PDT 24
Peak memory 207384 kb
Host smart-8024c5c3-9061-4149-9898-de0e2a8b866e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3589932746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3589932746
Directory /workspace/39.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3243670185
Short name T521
Test name
Test status
Simulation time 209626303 ps
CPU time 0.92 seconds
Started Aug 05 05:38:55 PM PDT 24
Finished Aug 05 05:38:56 PM PDT 24
Peak memory 207368 kb
Host smart-d961b5b5-91c7-4069-805e-301afee1ba43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32436
70185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3243670185
Directory /workspace/39.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.2071982556
Short name T2877
Test name
Test status
Simulation time 2253460354 ps
CPU time 22.87 seconds
Started Aug 05 05:38:57 PM PDT 24
Finished Aug 05 05:39:20 PM PDT 24
Peak memory 217116 kb
Host smart-8f782a45-9b3f-4a22-a7d5-818e580db4d4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2071982556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.2071982556
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.705072351
Short name T1337
Test name
Test status
Simulation time 150849763 ps
CPU time 0.83 seconds
Started Aug 05 05:39:10 PM PDT 24
Finished Aug 05 05:39:11 PM PDT 24
Peak memory 207304 kb
Host smart-8083f48e-5980-4e11-8ea1-793aaf0c2c5a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=705072351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.705072351
Directory /workspace/39.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3039385861
Short name T2216
Test name
Test status
Simulation time 149709244 ps
CPU time 0.83 seconds
Started Aug 05 05:39:27 PM PDT 24
Finished Aug 05 05:39:28 PM PDT 24
Peak memory 207328 kb
Host smart-cdc5c574-fc88-4877-af35-e5e961c09a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30393
85861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3039385861
Directory /workspace/39.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/39.usbdev_nak_trans.2011892245
Short name T142
Test name
Test status
Simulation time 206374786 ps
CPU time 0.96 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:01 PM PDT 24
Peak memory 207376 kb
Host smart-bb43459e-871f-4cee-a875-90e4f969f752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20118
92245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2011892245
Directory /workspace/39.usbdev_nak_trans/latest


Test location /workspace/coverage/default/39.usbdev_out_iso.648342881
Short name T826
Test name
Test status
Simulation time 188980709 ps
CPU time 0.88 seconds
Started Aug 05 05:39:11 PM PDT 24
Finished Aug 05 05:39:12 PM PDT 24
Peak memory 207292 kb
Host smart-d5114e06-f043-496b-b2f6-17c8e14ad4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64834
2881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.648342881
Directory /workspace/39.usbdev_out_iso/latest


Test location /workspace/coverage/default/39.usbdev_out_stall.1639868128
Short name T1908
Test name
Test status
Simulation time 183230371 ps
CPU time 0.89 seconds
Started Aug 05 05:39:19 PM PDT 24
Finished Aug 05 05:39:20 PM PDT 24
Peak memory 207324 kb
Host smart-11dd56ba-04ff-4207-a1ac-0b96d8d8fd5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16398
68128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1639868128
Directory /workspace/39.usbdev_out_stall/latest


Test location /workspace/coverage/default/39.usbdev_out_trans_nak.4136135354
Short name T1834
Test name
Test status
Simulation time 178329851 ps
CPU time 0.88 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:00 PM PDT 24
Peak memory 207356 kb
Host smart-1bac4398-9359-497c-b5e6-a1b1c8cc51f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41361
35354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.4136135354
Directory /workspace/39.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1587939929
Short name T2860
Test name
Test status
Simulation time 157953239 ps
CPU time 0.89 seconds
Started Aug 05 05:39:09 PM PDT 24
Finished Aug 05 05:39:10 PM PDT 24
Peak memory 207372 kb
Host smart-f1b0e447-1570-4b02-b0f0-6948358faa08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15879
39929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1587939929
Directory /workspace/39.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.1491720861
Short name T782
Test name
Test status
Simulation time 202015324 ps
CPU time 0.94 seconds
Started Aug 05 05:38:57 PM PDT 24
Finished Aug 05 05:38:58 PM PDT 24
Peak memory 207348 kb
Host smart-9e1be0b7-e8cd-4670-bb63-5e180ecadc55
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1491720861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.1491720861
Directory /workspace/39.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.641057084
Short name T3105
Test name
Test status
Simulation time 160224034 ps
CPU time 0.84 seconds
Started Aug 05 05:38:59 PM PDT 24
Finished Aug 05 05:39:00 PM PDT 24
Peak memory 207360 kb
Host smart-893fdf78-4f19-443b-a55b-23405c17fee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64105
7084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.641057084
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2427965380
Short name T2364
Test name
Test status
Simulation time 61155568 ps
CPU time 0.72 seconds
Started Aug 05 05:39:02 PM PDT 24
Finished Aug 05 05:39:03 PM PDT 24
Peak memory 207236 kb
Host smart-379663a4-cffd-407c-9923-038b16f28e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24279
65380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2427965380
Directory /workspace/39.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/39.usbdev_pkt_buffer.496165886
Short name T1403
Test name
Test status
Simulation time 8735852663 ps
CPU time 20.12 seconds
Started Aug 05 05:39:21 PM PDT 24
Finished Aug 05 05:39:41 PM PDT 24
Peak memory 215784 kb
Host smart-e8ce42a9-383b-49bf-a49f-75d610b4723c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49616
5886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.496165886
Directory /workspace/39.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/39.usbdev_pkt_received.2520537490
Short name T1949
Test name
Test status
Simulation time 185527891 ps
CPU time 0.88 seconds
Started Aug 05 05:39:15 PM PDT 24
Finished Aug 05 05:39:16 PM PDT 24
Peak memory 207324 kb
Host smart-5166b954-480e-4009-b3c0-af08387ea0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25205
37490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2520537490
Directory /workspace/39.usbdev_pkt_received/latest


Test location /workspace/coverage/default/39.usbdev_pkt_sent.3120803040
Short name T1336
Test name
Test status
Simulation time 224586396 ps
CPU time 0.95 seconds
Started Aug 05 05:39:08 PM PDT 24
Finished Aug 05 05:39:09 PM PDT 24
Peak memory 207300 kb
Host smart-5dde5266-34a5-4477-94e2-17c6e71583f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31208
03040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3120803040
Directory /workspace/39.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.1682463328
Short name T692
Test name
Test status
Simulation time 221618442 ps
CPU time 0.97 seconds
Started Aug 05 05:39:15 PM PDT 24
Finished Aug 05 05:39:16 PM PDT 24
Peak memory 207356 kb
Host smart-e5100639-0481-4479-a8fb-d2ba5d265869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16824
63328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.1682463328
Directory /workspace/39.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2780109228
Short name T2398
Test name
Test status
Simulation time 192926049 ps
CPU time 0.95 seconds
Started Aug 05 05:39:10 PM PDT 24
Finished Aug 05 05:39:11 PM PDT 24
Peak memory 207352 kb
Host smart-409b5977-db9b-4efb-b4e5-a293957545a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27801
09228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2780109228
Directory /workspace/39.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3169670757
Short name T2225
Test name
Test status
Simulation time 136910574 ps
CPU time 0.82 seconds
Started Aug 05 05:39:07 PM PDT 24
Finished Aug 05 05:39:08 PM PDT 24
Peak memory 207196 kb
Host smart-2ba3f48b-cba9-4f5c-a3d3-3834b6c914ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31696
70757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3169670757
Directory /workspace/39.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/39.usbdev_rx_full.2285026683
Short name T1318
Test name
Test status
Simulation time 386626651 ps
CPU time 1.33 seconds
Started Aug 05 05:39:31 PM PDT 24
Finished Aug 05 05:39:32 PM PDT 24
Peak memory 207364 kb
Host smart-6f6db9c0-f730-48ac-ac75-3168b6e74c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22850
26683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.2285026683
Directory /workspace/39.usbdev_rx_full/latest


Test location /workspace/coverage/default/39.usbdev_setup_stage.4259261197
Short name T3052
Test name
Test status
Simulation time 157765195 ps
CPU time 0.83 seconds
Started Aug 05 05:39:18 PM PDT 24
Finished Aug 05 05:39:19 PM PDT 24
Peak memory 207280 kb
Host smart-6c7834ae-192b-4ab8-a8bf-7c88834c9f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42592
61197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.4259261197
Directory /workspace/39.usbdev_setup_stage/latest


Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.431703506
Short name T2565
Test name
Test status
Simulation time 153020562 ps
CPU time 0.84 seconds
Started Aug 05 05:39:12 PM PDT 24
Finished Aug 05 05:39:13 PM PDT 24
Peak memory 207384 kb
Host smart-802efdff-fe12-4a94-9e30-ea0c12fb5ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43170
3506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.431703506
Directory /workspace/39.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/39.usbdev_smoke.3732397906
Short name T2102
Test name
Test status
Simulation time 215007768 ps
CPU time 1.04 seconds
Started Aug 05 05:39:13 PM PDT 24
Finished Aug 05 05:39:14 PM PDT 24
Peak memory 207400 kb
Host smart-0063043b-b114-405b-9433-64de3de9c9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37323
97906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3732397906
Directory /workspace/39.usbdev_smoke/latest


Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.938374602
Short name T1874
Test name
Test status
Simulation time 3539635662 ps
CPU time 99.45 seconds
Started Aug 05 05:39:00 PM PDT 24
Finished Aug 05 05:40:39 PM PDT 24
Peak memory 217668 kb
Host smart-69736165-d38e-4699-ba21-2f4d2b0c711b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=938374602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.938374602
Directory /workspace/39.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1225109860
Short name T1780
Test name
Test status
Simulation time 155991120 ps
CPU time 0.85 seconds
Started Aug 05 05:39:13 PM PDT 24
Finished Aug 05 05:39:14 PM PDT 24
Peak memory 207260 kb
Host smart-e462655b-55be-4f31-81b4-b9328225e6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12251
09860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1225109860
Directory /workspace/39.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/39.usbdev_stall_trans.999498084
Short name T2974
Test name
Test status
Simulation time 160626730 ps
CPU time 0.88 seconds
Started Aug 05 05:39:02 PM PDT 24
Finished Aug 05 05:39:03 PM PDT 24
Peak memory 207368 kb
Host smart-964f0e6a-3787-41d8-9be0-e0debce3d0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99949
8084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.999498084
Directory /workspace/39.usbdev_stall_trans/latest


Test location /workspace/coverage/default/39.usbdev_stream_len_max.3484264780
Short name T875
Test name
Test status
Simulation time 1316773562 ps
CPU time 2.93 seconds
Started Aug 05 05:39:03 PM PDT 24
Finished Aug 05 05:39:06 PM PDT 24
Peak memory 207564 kb
Host smart-2e27c7d1-0d1c-41bc-b755-8e6c7c087e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34842
64780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3484264780
Directory /workspace/39.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/39.usbdev_streaming_out.66368002
Short name T2724
Test name
Test status
Simulation time 2213854136 ps
CPU time 61.6 seconds
Started Aug 05 05:39:17 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 216988 kb
Host smart-fee2b485-03d3-4caa-aad8-c65028d4bf89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66368
002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.66368002
Directory /workspace/39.usbdev_streaming_out/latest


Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.2879623101
Short name T2688
Test name
Test status
Simulation time 2266173452 ps
CPU time 14.67 seconds
Started Aug 05 05:39:00 PM PDT 24
Finished Aug 05 05:39:15 PM PDT 24
Peak memory 207656 kb
Host smart-a9f0064b-7b9b-4c92-b961-7b004fddff64
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879623101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.2879623101
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/4.usbdev_alert_test.1868230454
Short name T2824
Test name
Test status
Simulation time 41418852 ps
CPU time 0.66 seconds
Started Aug 05 05:33:54 PM PDT 24
Finished Aug 05 05:33:55 PM PDT 24
Peak memory 207508 kb
Host smart-a62d08ba-2462-47d1-a985-13fcd5b1b7a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1868230454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1868230454
Directory /workspace/4.usbdev_alert_test/latest


Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2519862323
Short name T1453
Test name
Test status
Simulation time 11209518278 ps
CPU time 13.72 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:33:53 PM PDT 24
Peak memory 207684 kb
Host smart-eaea6462-53c0-4143-a097-86ccbf659e42
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519862323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.2519862323
Directory /workspace/4.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.68658121
Short name T2208
Test name
Test status
Simulation time 15047531998 ps
CPU time 16.75 seconds
Started Aug 05 05:33:42 PM PDT 24
Finished Aug 05 05:33:59 PM PDT 24
Peak memory 215952 kb
Host smart-a97cdbfd-eec4-43ff-a189-996e16508145
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=68658121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.68658121
Directory /workspace/4.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.2985420450
Short name T1829
Test name
Test status
Simulation time 24822142152 ps
CPU time 29.63 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:34:09 PM PDT 24
Peak memory 215828 kb
Host smart-db84200d-9276-4b4e-ae21-9905aff5ff4b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985420450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.2985420450
Directory /workspace/4.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/4.usbdev_av_buffer.2061513095
Short name T1355
Test name
Test status
Simulation time 149647561 ps
CPU time 0.87 seconds
Started Aug 05 05:33:42 PM PDT 24
Finished Aug 05 05:33:43 PM PDT 24
Peak memory 207368 kb
Host smart-afa75b4d-eaee-4d08-ba7e-146541ac3cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20615
13095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2061513095
Directory /workspace/4.usbdev_av_buffer/latest


Test location /workspace/coverage/default/4.usbdev_av_empty.218829673
Short name T63
Test name
Test status
Simulation time 155355042 ps
CPU time 0.9 seconds
Started Aug 05 05:33:42 PM PDT 24
Finished Aug 05 05:33:43 PM PDT 24
Peak memory 207404 kb
Host smart-ccc190dd-e4aa-4a0e-9613-14346378f013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21882
9673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.218829673
Directory /workspace/4.usbdev_av_empty/latest


Test location /workspace/coverage/default/4.usbdev_av_overflow.2962072139
Short name T68
Test name
Test status
Simulation time 135753945 ps
CPU time 0.81 seconds
Started Aug 05 05:33:41 PM PDT 24
Finished Aug 05 05:33:42 PM PDT 24
Peak memory 207312 kb
Host smart-c4b99c10-eee3-4456-8173-615a77e3e04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29620
72139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2962072139
Directory /workspace/4.usbdev_av_overflow/latest


Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2890225801
Short name T2549
Test name
Test status
Simulation time 165613352 ps
CPU time 0.84 seconds
Started Aug 05 05:33:42 PM PDT 24
Finished Aug 05 05:33:43 PM PDT 24
Peak memory 207292 kb
Host smart-d820a513-cfaf-4f26-9c90-e2972c90cdf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28902
25801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2890225801
Directory /workspace/4.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2024101672
Short name T35
Test name
Test status
Simulation time 505386149 ps
CPU time 1.7 seconds
Started Aug 05 05:33:37 PM PDT 24
Finished Aug 05 05:33:39 PM PDT 24
Peak memory 207400 kb
Host smart-eeed2038-7ce9-4ee2-b985-136f18ae95de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20241
01672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2024101672
Directory /workspace/4.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.4049927569
Short name T2324
Test name
Test status
Simulation time 944007975 ps
CPU time 2.6 seconds
Started Aug 05 05:33:44 PM PDT 24
Finished Aug 05 05:33:47 PM PDT 24
Peak memory 207532 kb
Host smart-00ca3105-7a6a-4132-a484-207c570990d5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4049927569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.4049927569
Directory /workspace/4.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/4.usbdev_device_address.2765779082
Short name T161
Test name
Test status
Simulation time 43343888902 ps
CPU time 65.41 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:34:45 PM PDT 24
Peak memory 207632 kb
Host smart-702342f9-18c3-4fdd-9d3e-c43dfacabf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27657
79082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2765779082
Directory /workspace/4.usbdev_device_address/latest


Test location /workspace/coverage/default/4.usbdev_device_timeout.1653756378
Short name T2905
Test name
Test status
Simulation time 2965930315 ps
CPU time 26.56 seconds
Started Aug 05 05:33:40 PM PDT 24
Finished Aug 05 05:34:07 PM PDT 24
Peak memory 207684 kb
Host smart-1f34df2e-816d-443f-a2b9-8db7147a3bf9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653756378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.1653756378
Directory /workspace/4.usbdev_device_timeout/latest


Test location /workspace/coverage/default/4.usbdev_disable_endpoint.3817427490
Short name T321
Test name
Test status
Simulation time 927389109 ps
CPU time 1.92 seconds
Started Aug 05 05:33:43 PM PDT 24
Finished Aug 05 05:33:45 PM PDT 24
Peak memory 207380 kb
Host smart-bc9a1629-91a5-44ce-b4ac-4bf80552eb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38174
27490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.3817427490
Directory /workspace/4.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/4.usbdev_disconnected.2276027195
Short name T1835
Test name
Test status
Simulation time 153299324 ps
CPU time 0.86 seconds
Started Aug 05 05:33:41 PM PDT 24
Finished Aug 05 05:33:42 PM PDT 24
Peak memory 207320 kb
Host smart-2ef77458-4fb0-4d77-9fc4-cf1becb5cc49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22760
27195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2276027195
Directory /workspace/4.usbdev_disconnected/latest


Test location /workspace/coverage/default/4.usbdev_enable.2026731850
Short name T1538
Test name
Test status
Simulation time 34585727 ps
CPU time 0.7 seconds
Started Aug 05 05:33:41 PM PDT 24
Finished Aug 05 05:33:42 PM PDT 24
Peak memory 207332 kb
Host smart-d6e3d96b-a6c2-4a5b-b898-97aa023f14dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20267
31850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2026731850
Directory /workspace/4.usbdev_enable/latest


Test location /workspace/coverage/default/4.usbdev_endpoint_access.1548600298
Short name T2235
Test name
Test status
Simulation time 893428688 ps
CPU time 2.39 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:33:42 PM PDT 24
Peak memory 207556 kb
Host smart-569717f2-7fa6-4412-b31f-a075f7b76dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15486
00298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.1548600298
Directory /workspace/4.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/4.usbdev_endpoint_types.4221762516
Short name T398
Test name
Test status
Simulation time 279071947 ps
CPU time 1.11 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:33:41 PM PDT 24
Peak memory 207324 kb
Host smart-5028efc3-3252-434b-9aeb-b46259d06ad3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4221762516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.4221762516
Directory /workspace/4.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/4.usbdev_fifo_rst.1893235124
Short name T1901
Test name
Test status
Simulation time 190962739 ps
CPU time 2.48 seconds
Started Aug 05 05:33:41 PM PDT 24
Finished Aug 05 05:33:44 PM PDT 24
Peak memory 207496 kb
Host smart-731e7f6f-2f5f-4dd0-9ad7-0e9a302a16ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18932
35124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1893235124
Directory /workspace/4.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/4.usbdev_freq_hiclk.1111231775
Short name T882
Test name
Test status
Simulation time 89184177130 ps
CPU time 174.98 seconds
Started Aug 05 05:33:41 PM PDT 24
Finished Aug 05 05:36:36 PM PDT 24
Peak memory 207720 kb
Host smart-c89877f9-0d18-4f1c-a077-db457abfb0c1
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1111231775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.1111231775
Directory /workspace/4.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.94633283
Short name T1593
Test name
Test status
Simulation time 83149156341 ps
CPU time 151.4 seconds
Started Aug 05 05:33:48 PM PDT 24
Finished Aug 05 05:36:19 PM PDT 24
Peak memory 207616 kb
Host smart-a1bd0989-8f93-468a-b979-fe4d715ed593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94633283 -assert nop
ostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.94633283
Directory /workspace/4.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/4.usbdev_freq_loclk.3398612417
Short name T481
Test name
Test status
Simulation time 112100650061 ps
CPU time 206.47 seconds
Started Aug 05 05:33:44 PM PDT 24
Finished Aug 05 05:37:11 PM PDT 24
Peak memory 207656 kb
Host smart-27efd8ce-ca7f-4777-822e-0d8d69de8c40
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3398612417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.3398612417
Directory /workspace/4.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.514237412
Short name T1158
Test name
Test status
Simulation time 99905486426 ps
CPU time 151.58 seconds
Started Aug 05 05:33:40 PM PDT 24
Finished Aug 05 05:36:12 PM PDT 24
Peak memory 207584 kb
Host smart-4fa08c50-4377-4a77-b813-6442535e938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514237412 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.514237412
Directory /workspace/4.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/4.usbdev_freq_phase.4243350207
Short name T2458
Test name
Test status
Simulation time 113169995636 ps
CPU time 176.09 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:36:35 PM PDT 24
Peak memory 207656 kb
Host smart-5d8e4c5c-b502-41b3-86c5-560f03049aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42433
50207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.4243350207
Directory /workspace/4.usbdev_freq_phase/latest


Test location /workspace/coverage/default/4.usbdev_in_iso.3372220984
Short name T565
Test name
Test status
Simulation time 228534511 ps
CPU time 1.14 seconds
Started Aug 05 05:33:43 PM PDT 24
Finished Aug 05 05:33:44 PM PDT 24
Peak memory 215732 kb
Host smart-8ccfc3a3-3638-48c5-859c-ed894c9f4963
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3372220984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3372220984
Directory /workspace/4.usbdev_in_iso/latest


Test location /workspace/coverage/default/4.usbdev_in_stall.699265048
Short name T1349
Test name
Test status
Simulation time 141045703 ps
CPU time 0.81 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:33:40 PM PDT 24
Peak memory 207264 kb
Host smart-b1e4db93-c9ee-4541-ad3a-976422d21f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69926
5048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.699265048
Directory /workspace/4.usbdev_in_stall/latest


Test location /workspace/coverage/default/4.usbdev_in_trans.1206366493
Short name T1564
Test name
Test status
Simulation time 237411873 ps
CPU time 0.98 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:33:40 PM PDT 24
Peak memory 207272 kb
Host smart-9e9c22b1-088f-40dc-826d-bfab74e8b079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12063
66493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1206366493
Directory /workspace/4.usbdev_in_trans/latest


Test location /workspace/coverage/default/4.usbdev_invalid_sync.3491216308
Short name T2227
Test name
Test status
Simulation time 4279434734 ps
CPU time 43.32 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:34:22 PM PDT 24
Peak memory 217864 kb
Host smart-6c2984bf-cf7a-40be-9219-80dd42808ae8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3491216308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3491216308
Directory /workspace/4.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/4.usbdev_iso_retraction.360098602
Short name T251
Test name
Test status
Simulation time 8425994865 ps
CPU time 62.18 seconds
Started Aug 05 05:33:41 PM PDT 24
Finished Aug 05 05:34:44 PM PDT 24
Peak memory 207620 kb
Host smart-580b885f-403a-4d73-8072-81988c270f94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=360098602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.360098602
Directory /workspace/4.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/4.usbdev_link_in_err.1091482888
Short name T708
Test name
Test status
Simulation time 223587907 ps
CPU time 0.94 seconds
Started Aug 05 05:33:39 PM PDT 24
Finished Aug 05 05:33:40 PM PDT 24
Peak memory 207344 kb
Host smart-9c2578b6-7e1f-42c0-a883-c37aba7f5697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10914
82888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1091482888
Directory /workspace/4.usbdev_link_in_err/latest


Test location /workspace/coverage/default/4.usbdev_link_resume.2486866059
Short name T1922
Test name
Test status
Simulation time 29505076375 ps
CPU time 40.22 seconds
Started Aug 05 05:33:40 PM PDT 24
Finished Aug 05 05:34:20 PM PDT 24
Peak memory 207644 kb
Host smart-6e40f3e2-5dff-4e2c-b206-02dbe6f0a7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24868
66059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.2486866059
Directory /workspace/4.usbdev_link_resume/latest


Test location /workspace/coverage/default/4.usbdev_link_suspend.2582992841
Short name T112
Test name
Test status
Simulation time 5363147036 ps
CPU time 6.87 seconds
Started Aug 05 05:33:48 PM PDT 24
Finished Aug 05 05:33:55 PM PDT 24
Peak memory 215744 kb
Host smart-03f6326f-90e8-4ef7-b551-c9de4e363bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25829
92841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2582992841
Directory /workspace/4.usbdev_link_suspend/latest


Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.2647248273
Short name T2089
Test name
Test status
Simulation time 3931900538 ps
CPU time 39.92 seconds
Started Aug 05 05:33:46 PM PDT 24
Finished Aug 05 05:34:26 PM PDT 24
Peak memory 224056 kb
Host smart-5c2ac651-2daf-48e4-9f4b-85ad1195fb66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26472
48273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.2647248273
Directory /workspace/4.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.3124142120
Short name T2843
Test name
Test status
Simulation time 2985682930 ps
CPU time 86.78 seconds
Started Aug 05 05:33:49 PM PDT 24
Finished Aug 05 05:35:16 PM PDT 24
Peak memory 217560 kb
Host smart-5a9c1f21-35cd-4b4a-a701-1555fd3c08d6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3124142120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.3124142120
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2795947967
Short name T1036
Test name
Test status
Simulation time 243771692 ps
CPU time 1.05 seconds
Started Aug 05 05:33:49 PM PDT 24
Finished Aug 05 05:33:50 PM PDT 24
Peak memory 207352 kb
Host smart-a48a3365-602c-4066-a479-fb83cad8d045
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2795947967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2795947967
Directory /workspace/4.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2751690912
Short name T2848
Test name
Test status
Simulation time 183229835 ps
CPU time 0.93 seconds
Started Aug 05 05:33:54 PM PDT 24
Finished Aug 05 05:33:55 PM PDT 24
Peak memory 207352 kb
Host smart-6f9dc64d-b7d4-4491-80ae-8c0afaa08038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27516
90912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2751690912
Directory /workspace/4.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.1623797600
Short name T2060
Test name
Test status
Simulation time 3590894889 ps
CPU time 101.24 seconds
Started Aug 05 05:33:53 PM PDT 24
Finished Aug 05 05:35:35 PM PDT 24
Peak memory 217632 kb
Host smart-21cbe050-c33f-42ff-94fd-d8d0308c89c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16237
97600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.1623797600
Directory /workspace/4.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3027749728
Short name T2650
Test name
Test status
Simulation time 3292624464 ps
CPU time 28.08 seconds
Started Aug 05 05:33:54 PM PDT 24
Finished Aug 05 05:34:22 PM PDT 24
Peak memory 207664 kb
Host smart-1f3b6c49-ec5b-499f-a11c-4846a17f4ea1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3027749728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3027749728
Directory /workspace/4.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2231992403
Short name T2382
Test name
Test status
Simulation time 2899484837 ps
CPU time 87 seconds
Started Aug 05 05:33:47 PM PDT 24
Finished Aug 05 05:35:14 PM PDT 24
Peak memory 217368 kb
Host smart-cf2458c2-c278-443d-a38b-038211b4a8fd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2231992403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2231992403
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.2001063311
Short name T2185
Test name
Test status
Simulation time 163636979 ps
CPU time 0.85 seconds
Started Aug 05 05:33:53 PM PDT 24
Finished Aug 05 05:33:54 PM PDT 24
Peak memory 207360 kb
Host smart-15b489db-826d-4b3f-9f05-930da4fec9b1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2001063311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.2001063311
Directory /workspace/4.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.4130712585
Short name T3044
Test name
Test status
Simulation time 171221653 ps
CPU time 0.87 seconds
Started Aug 05 05:33:47 PM PDT 24
Finished Aug 05 05:33:48 PM PDT 24
Peak memory 207348 kb
Host smart-e4075374-420a-4677-a6a1-ddeae24ff3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41307
12585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.4130712585
Directory /workspace/4.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/4.usbdev_nak_trans.551778190
Short name T141
Test name
Test status
Simulation time 240968117 ps
CPU time 1.09 seconds
Started Aug 05 05:33:50 PM PDT 24
Finished Aug 05 05:33:52 PM PDT 24
Peak memory 207332 kb
Host smart-e52994b5-e36d-4b8e-a801-9cb790119507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55177
8190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.551778190
Directory /workspace/4.usbdev_nak_trans/latest


Test location /workspace/coverage/default/4.usbdev_out_iso.1980047458
Short name T682
Test name
Test status
Simulation time 167935350 ps
CPU time 0.93 seconds
Started Aug 05 05:33:47 PM PDT 24
Finished Aug 05 05:33:48 PM PDT 24
Peak memory 207268 kb
Host smart-eaed7f8c-fab8-40e6-928f-2107f8b599d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19800
47458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1980047458
Directory /workspace/4.usbdev_out_iso/latest


Test location /workspace/coverage/default/4.usbdev_out_stall.3606231181
Short name T1231
Test name
Test status
Simulation time 159977095 ps
CPU time 0.87 seconds
Started Aug 05 05:33:49 PM PDT 24
Finished Aug 05 05:33:50 PM PDT 24
Peak memory 207408 kb
Host smart-2951cd96-7f14-4630-9be6-d1525575125e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36062
31181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3606231181
Directory /workspace/4.usbdev_out_stall/latest


Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3695491314
Short name T1437
Test name
Test status
Simulation time 142131979 ps
CPU time 0.85 seconds
Started Aug 05 05:33:48 PM PDT 24
Finished Aug 05 05:33:49 PM PDT 24
Peak memory 207312 kb
Host smart-e3fd31da-f229-426e-85b8-a7faf34030ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36954
91314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3695491314
Directory /workspace/4.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3308401820
Short name T1858
Test name
Test status
Simulation time 163052670 ps
CPU time 0.92 seconds
Started Aug 05 05:33:47 PM PDT 24
Finished Aug 05 05:33:48 PM PDT 24
Peak memory 207248 kb
Host smart-0fd4bc61-119a-4720-a1ef-24054c9d104e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33084
01820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3308401820
Directory /workspace/4.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.3050878584
Short name T1185
Test name
Test status
Simulation time 233960161 ps
CPU time 1.05 seconds
Started Aug 05 05:33:49 PM PDT 24
Finished Aug 05 05:33:50 PM PDT 24
Peak memory 207392 kb
Host smart-b2fed2a5-cd00-4bb5-b8bf-519bbfd994eb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3050878584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.3050878584
Directory /workspace/4.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2801026766
Short name T2510
Test name
Test status
Simulation time 211380967 ps
CPU time 1.01 seconds
Started Aug 05 05:33:46 PM PDT 24
Finished Aug 05 05:33:47 PM PDT 24
Peak memory 207328 kb
Host smart-879591fa-053d-4aeb-8496-39ba9c36f4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28010
26766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2801026766
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2190985062
Short name T2992
Test name
Test status
Simulation time 146145237 ps
CPU time 0.9 seconds
Started Aug 05 05:33:49 PM PDT 24
Finished Aug 05 05:33:50 PM PDT 24
Peak memory 207256 kb
Host smart-c7b9080a-7c78-4b2b-9f6e-1224090f23ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21909
85062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2190985062
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1029956527
Short name T1383
Test name
Test status
Simulation time 82240506 ps
CPU time 0.73 seconds
Started Aug 05 05:33:44 PM PDT 24
Finished Aug 05 05:33:45 PM PDT 24
Peak memory 207364 kb
Host smart-e80965b6-8f5b-4474-a6c7-77f64cacefa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10299
56527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1029956527
Directory /workspace/4.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/4.usbdev_pkt_buffer.2719328577
Short name T2920
Test name
Test status
Simulation time 12151377763 ps
CPU time 35.29 seconds
Started Aug 05 05:33:50 PM PDT 24
Finished Aug 05 05:34:25 PM PDT 24
Peak memory 215952 kb
Host smart-e1dc88c0-49bb-4637-a389-0be41ce1013c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27193
28577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.2719328577
Directory /workspace/4.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/4.usbdev_pkt_received.82979318
Short name T2157
Test name
Test status
Simulation time 163614216 ps
CPU time 0.88 seconds
Started Aug 05 05:33:50 PM PDT 24
Finished Aug 05 05:33:51 PM PDT 24
Peak memory 207264 kb
Host smart-be0e206f-a795-4242-852e-9dcb35c42714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82979
318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.82979318
Directory /workspace/4.usbdev_pkt_received/latest


Test location /workspace/coverage/default/4.usbdev_pkt_sent.2924480457
Short name T1131
Test name
Test status
Simulation time 175263255 ps
CPU time 0.86 seconds
Started Aug 05 05:33:48 PM PDT 24
Finished Aug 05 05:33:49 PM PDT 24
Peak memory 207604 kb
Host smart-5a95be0b-adee-4040-8bde-03b926ffc827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29244
80457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2924480457
Directory /workspace/4.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2488238237
Short name T167
Test name
Test status
Simulation time 3633193422 ps
CPU time 28.16 seconds
Started Aug 05 05:33:47 PM PDT 24
Finished Aug 05 05:34:16 PM PDT 24
Peak memory 224060 kb
Host smart-41baae50-f958-46d2-bad2-950168e8c5c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2488238237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2488238237
Directory /workspace/4.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/4.usbdev_rand_suspends.750141716
Short name T1229
Test name
Test status
Simulation time 9843932139 ps
CPU time 52.78 seconds
Started Aug 05 05:33:49 PM PDT 24
Finished Aug 05 05:34:42 PM PDT 24
Peak memory 223952 kb
Host smart-3a8ab350-7068-4d5b-a987-ade6c811bc94
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=750141716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.750141716
Directory /workspace/4.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.513482826
Short name T1761
Test name
Test status
Simulation time 296360085 ps
CPU time 1.07 seconds
Started Aug 05 05:33:48 PM PDT 24
Finished Aug 05 05:33:50 PM PDT 24
Peak memory 207372 kb
Host smart-998f0f1a-e195-476e-92f4-fb11fb68b741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51348
2826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.513482826
Directory /workspace/4.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.347494037
Short name T1929
Test name
Test status
Simulation time 177259401 ps
CPU time 0.9 seconds
Started Aug 05 05:33:54 PM PDT 24
Finished Aug 05 05:33:55 PM PDT 24
Peak memory 207352 kb
Host smart-62407a35-5fa9-4ac5-872b-f10f2353dd9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34749
4037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.347494037
Directory /workspace/4.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/4.usbdev_resume_link_active.2496061032
Short name T641
Test name
Test status
Simulation time 20211575634 ps
CPU time 27.99 seconds
Started Aug 05 05:33:47 PM PDT 24
Finished Aug 05 05:34:15 PM PDT 24
Peak memory 207460 kb
Host smart-81d33f7d-a6b5-49de-be36-df643a764d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24960
61032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.2496061032
Directory /workspace/4.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2933782629
Short name T1691
Test name
Test status
Simulation time 137736795 ps
CPU time 0.79 seconds
Started Aug 05 05:33:50 PM PDT 24
Finished Aug 05 05:33:51 PM PDT 24
Peak memory 207232 kb
Host smart-730e95cc-ef45-4fbf-90fa-69b5af1280d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29337
82629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2933782629
Directory /workspace/4.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/4.usbdev_rx_full.3205410867
Short name T2141
Test name
Test status
Simulation time 260614944 ps
CPU time 1.11 seconds
Started Aug 05 05:33:46 PM PDT 24
Finished Aug 05 05:33:47 PM PDT 24
Peak memory 207268 kb
Host smart-d5f373da-f47d-4530-a2a9-ddb4028cde73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32054
10867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.3205410867
Directory /workspace/4.usbdev_rx_full/latest


Test location /workspace/coverage/default/4.usbdev_rx_pid_err.3951323753
Short name T84
Test name
Test status
Simulation time 179394459 ps
CPU time 0.88 seconds
Started Aug 05 05:33:54 PM PDT 24
Finished Aug 05 05:33:55 PM PDT 24
Peak memory 207268 kb
Host smart-d383d9ef-d479-4d5f-92e3-f35fb24dce0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39513
23753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.3951323753
Directory /workspace/4.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/4.usbdev_sec_cm.3758625334
Short name T201
Test name
Test status
Simulation time 245876145 ps
CPU time 1.05 seconds
Started Aug 05 05:33:59 PM PDT 24
Finished Aug 05 05:34:01 PM PDT 24
Peak memory 223288 kb
Host smart-c195a8a6-1504-45d5-892a-37fb14389d5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3758625334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3758625334
Directory /workspace/4.usbdev_sec_cm/latest


Test location /workspace/coverage/default/4.usbdev_setup_priority.3177694920
Short name T2990
Test name
Test status
Simulation time 370678497 ps
CPU time 1.28 seconds
Started Aug 05 05:33:56 PM PDT 24
Finished Aug 05 05:33:57 PM PDT 24
Peak memory 207400 kb
Host smart-59d1a4db-2b20-4df8-91b0-aff44de80fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31776
94920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.3177694920
Directory /workspace/4.usbdev_setup_priority/latest


Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.1339859165
Short name T1095
Test name
Test status
Simulation time 170283651 ps
CPU time 0.95 seconds
Started Aug 05 05:33:55 PM PDT 24
Finished Aug 05 05:33:56 PM PDT 24
Peak memory 207328 kb
Host smart-750e70b4-8290-461f-baea-6f4e656811a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13398
59165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.1339859165
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/4.usbdev_setup_stage.1885183071
Short name T599
Test name
Test status
Simulation time 155777744 ps
CPU time 0.87 seconds
Started Aug 05 05:34:02 PM PDT 24
Finished Aug 05 05:34:03 PM PDT 24
Peak memory 207264 kb
Host smart-222161e5-0696-4acc-bf7e-cb66334e3d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18851
83071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1885183071
Directory /workspace/4.usbdev_setup_stage/latest


Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1447284398
Short name T1607
Test name
Test status
Simulation time 165738121 ps
CPU time 0.86 seconds
Started Aug 05 05:33:54 PM PDT 24
Finished Aug 05 05:33:55 PM PDT 24
Peak memory 207288 kb
Host smart-e07cc1f2-6a43-42e0-ac6c-455464821de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14472
84398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1447284398
Directory /workspace/4.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/4.usbdev_smoke.2271970213
Short name T834
Test name
Test status
Simulation time 199190491 ps
CPU time 0.99 seconds
Started Aug 05 05:33:55 PM PDT 24
Finished Aug 05 05:33:56 PM PDT 24
Peak memory 207376 kb
Host smart-07c719e8-3c1a-4abe-abcb-0256649e8201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22719
70213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2271970213
Directory /workspace/4.usbdev_smoke/latest


Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.2305895234
Short name T1278
Test name
Test status
Simulation time 2385145945 ps
CPU time 65.65 seconds
Started Aug 05 05:33:55 PM PDT 24
Finished Aug 05 05:35:01 PM PDT 24
Peak memory 223968 kb
Host smart-d95901e3-8c69-4fd0-bfe0-ec5551ef9c7e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2305895234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.2305895234
Directory /workspace/4.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3821640007
Short name T596
Test name
Test status
Simulation time 179568163 ps
CPU time 0.92 seconds
Started Aug 05 05:33:57 PM PDT 24
Finished Aug 05 05:33:58 PM PDT 24
Peak memory 207404 kb
Host smart-17ea888b-5241-45d7-9602-c8d93e478867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38216
40007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3821640007
Directory /workspace/4.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/4.usbdev_stall_trans.1660668081
Short name T940
Test name
Test status
Simulation time 192755400 ps
CPU time 0.87 seconds
Started Aug 05 05:33:56 PM PDT 24
Finished Aug 05 05:33:57 PM PDT 24
Peak memory 207328 kb
Host smart-6be7df9b-12a2-4089-9d7c-e16a944f2133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16606
68081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1660668081
Directory /workspace/4.usbdev_stall_trans/latest


Test location /workspace/coverage/default/4.usbdev_stream_len_max.1285687237
Short name T1367
Test name
Test status
Simulation time 205473276 ps
CPU time 1.01 seconds
Started Aug 05 05:33:57 PM PDT 24
Finished Aug 05 05:33:58 PM PDT 24
Peak memory 207332 kb
Host smart-4df67c55-3d7a-45b4-832c-26cb3dbaf094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12856
87237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.1285687237
Directory /workspace/4.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/4.usbdev_streaming_out.849154331
Short name T2410
Test name
Test status
Simulation time 2778265585 ps
CPU time 84.97 seconds
Started Aug 05 05:33:55 PM PDT 24
Finished Aug 05 05:35:20 PM PDT 24
Peak memory 217252 kb
Host smart-96b2d3ab-6b12-4dc5-b8cd-91283664a689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84915
4331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.849154331
Directory /workspace/4.usbdev_streaming_out/latest


Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3940451607
Short name T79
Test name
Test status
Simulation time 4638848295 ps
CPU time 126.68 seconds
Started Aug 05 05:33:57 PM PDT 24
Finished Aug 05 05:36:04 PM PDT 24
Peak memory 223984 kb
Host smart-0c9eac87-68ea-4cf2-9e5c-ed4313649142
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940451607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3940451607
Directory /workspace/4.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.1998196319
Short name T1749
Test name
Test status
Simulation time 858645566 ps
CPU time 19 seconds
Started Aug 05 05:33:48 PM PDT 24
Finished Aug 05 05:34:07 PM PDT 24
Peak memory 207496 kb
Host smart-0d30c9da-4ba5-4f0e-83ea-37e75cca8881
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998196319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.1998196319
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/40.usbdev_alert_test.3647925462
Short name T2196
Test name
Test status
Simulation time 44807399 ps
CPU time 0.67 seconds
Started Aug 05 05:39:35 PM PDT 24
Finished Aug 05 05:39:35 PM PDT 24
Peak memory 207412 kb
Host smart-315a1898-dea5-4b17-966a-4202f6bb8725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3647925462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3647925462
Directory /workspace/40.usbdev_alert_test/latest


Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3664706928
Short name T1843
Test name
Test status
Simulation time 10237197764 ps
CPU time 14.95 seconds
Started Aug 05 05:39:00 PM PDT 24
Finished Aug 05 05:39:15 PM PDT 24
Peak memory 207620 kb
Host smart-acbc13c0-c044-45e3-8f96-4dec6f49fb42
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664706928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.3664706928
Directory /workspace/40.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.979000388
Short name T1944
Test name
Test status
Simulation time 15037229359 ps
CPU time 17.32 seconds
Started Aug 05 05:39:02 PM PDT 24
Finished Aug 05 05:39:19 PM PDT 24
Peak memory 215756 kb
Host smart-a5a946e6-84e2-4cef-82ff-d1f4fcb0f28f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=979000388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.979000388
Directory /workspace/40.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2499780171
Short name T2377
Test name
Test status
Simulation time 28946107540 ps
CPU time 34.17 seconds
Started Aug 05 05:39:03 PM PDT 24
Finished Aug 05 05:39:37 PM PDT 24
Peak memory 207516 kb
Host smart-c1b74a17-781b-4f6f-8c81-0c56894f5b53
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499780171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.2499780171
Directory /workspace/40.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/40.usbdev_av_buffer.637904715
Short name T2380
Test name
Test status
Simulation time 168611890 ps
CPU time 0.87 seconds
Started Aug 05 05:39:06 PM PDT 24
Finished Aug 05 05:39:07 PM PDT 24
Peak memory 207352 kb
Host smart-a30b60e5-2897-43a8-b851-66c20d6cabf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63790
4715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.637904715
Directory /workspace/40.usbdev_av_buffer/latest


Test location /workspace/coverage/default/40.usbdev_bitstuff_err.766853926
Short name T2764
Test name
Test status
Simulation time 150842376 ps
CPU time 0.82 seconds
Started Aug 05 05:39:09 PM PDT 24
Finished Aug 05 05:39:10 PM PDT 24
Peak memory 207372 kb
Host smart-fe5b4332-2f2a-4bfb-8835-1e9ba0bf8b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76685
3926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.766853926
Directory /workspace/40.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.832810491
Short name T2261
Test name
Test status
Simulation time 580489304 ps
CPU time 1.75 seconds
Started Aug 05 05:39:15 PM PDT 24
Finished Aug 05 05:39:17 PM PDT 24
Peak memory 207356 kb
Host smart-ef75856d-fd2a-49d9-bca5-35d5fa41eb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83281
0491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.832810491
Directory /workspace/40.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/40.usbdev_device_address.1263587731
Short name T2306
Test name
Test status
Simulation time 44556457737 ps
CPU time 77.88 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:40:42 PM PDT 24
Peak memory 207664 kb
Host smart-27d99fb4-e5a0-4f0e-b33d-7d0f3682441c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12635
87731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1263587731
Directory /workspace/40.usbdev_device_address/latest


Test location /workspace/coverage/default/40.usbdev_device_timeout.1273512673
Short name T539
Test name
Test status
Simulation time 322029940 ps
CPU time 4.7 seconds
Started Aug 05 05:39:04 PM PDT 24
Finished Aug 05 05:39:09 PM PDT 24
Peak memory 207596 kb
Host smart-1a4a9c24-d4ee-40e3-8212-42dbb8dce374
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273512673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.1273512673
Directory /workspace/40.usbdev_device_timeout/latest


Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2055760671
Short name T1189
Test name
Test status
Simulation time 1016968191 ps
CPU time 2.4 seconds
Started Aug 05 05:39:29 PM PDT 24
Finished Aug 05 05:39:31 PM PDT 24
Peak memory 207200 kb
Host smart-e6fab61f-43bc-444a-8dfc-3c9aa3ed08a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20557
60671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2055760671
Directory /workspace/40.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/40.usbdev_disconnected.630571725
Short name T69
Test name
Test status
Simulation time 141246143 ps
CPU time 0.85 seconds
Started Aug 05 05:39:12 PM PDT 24
Finished Aug 05 05:39:13 PM PDT 24
Peak memory 207344 kb
Host smart-af622943-2c6b-4611-b59a-d4777b5df557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63057
1725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.630571725
Directory /workspace/40.usbdev_disconnected/latest


Test location /workspace/coverage/default/40.usbdev_enable.2328242260
Short name T2286
Test name
Test status
Simulation time 33593965 ps
CPU time 0.7 seconds
Started Aug 05 05:39:10 PM PDT 24
Finished Aug 05 05:39:10 PM PDT 24
Peak memory 207340 kb
Host smart-0ab7ee9b-adea-48d0-83fc-bad5e0a76803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23282
42260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2328242260
Directory /workspace/40.usbdev_enable/latest


Test location /workspace/coverage/default/40.usbdev_endpoint_access.28877690
Short name T2400
Test name
Test status
Simulation time 836073974 ps
CPU time 2.22 seconds
Started Aug 05 05:39:14 PM PDT 24
Finished Aug 05 05:39:16 PM PDT 24
Peak memory 207632 kb
Host smart-1fe34c07-d57c-4170-af04-32552065312b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28877
690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.28877690
Directory /workspace/40.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/40.usbdev_fifo_rst.1564147055
Short name T2472
Test name
Test status
Simulation time 286900598 ps
CPU time 1.95 seconds
Started Aug 05 05:39:21 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 207576 kb
Host smart-6edd74f6-855b-4ff1-aba4-36365790238d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15641
47055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1564147055
Directory /workspace/40.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/40.usbdev_in_iso.1481510395
Short name T1625
Test name
Test status
Simulation time 200557095 ps
CPU time 1.02 seconds
Started Aug 05 05:39:12 PM PDT 24
Finished Aug 05 05:39:13 PM PDT 24
Peak memory 207440 kb
Host smart-da134cbd-bb4b-42f1-af43-5c9976193739
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1481510395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1481510395
Directory /workspace/40.usbdev_in_iso/latest


Test location /workspace/coverage/default/40.usbdev_in_stall.2655762051
Short name T2076
Test name
Test status
Simulation time 170783857 ps
CPU time 0.9 seconds
Started Aug 05 05:39:11 PM PDT 24
Finished Aug 05 05:39:12 PM PDT 24
Peak memory 207320 kb
Host smart-40f2ed2c-afa7-406d-a223-a7b00815b63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26557
62051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2655762051
Directory /workspace/40.usbdev_in_stall/latest


Test location /workspace/coverage/default/40.usbdev_in_trans.3632045498
Short name T33
Test name
Test status
Simulation time 249648387 ps
CPU time 1.09 seconds
Started Aug 05 05:39:13 PM PDT 24
Finished Aug 05 05:39:14 PM PDT 24
Peak memory 207400 kb
Host smart-b518e302-9af2-4b2f-b28c-69656be9e655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36320
45498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3632045498
Directory /workspace/40.usbdev_in_trans/latest


Test location /workspace/coverage/default/40.usbdev_invalid_sync.3120719429
Short name T25
Test name
Test status
Simulation time 3001655987 ps
CPU time 85.84 seconds
Started Aug 05 05:39:21 PM PDT 24
Finished Aug 05 05:40:47 PM PDT 24
Peak memory 218164 kb
Host smart-70b39fce-0b15-4a29-b3b8-f438c1da62cb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3120719429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.3120719429
Directory /workspace/40.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/40.usbdev_iso_retraction.253822860
Short name T1144
Test name
Test status
Simulation time 8043502317 ps
CPU time 97.81 seconds
Started Aug 05 05:39:00 PM PDT 24
Finished Aug 05 05:40:38 PM PDT 24
Peak memory 207688 kb
Host smart-d2df1674-2dce-4e6b-8189-fbec2ff79721
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=253822860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.253822860
Directory /workspace/40.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/40.usbdev_link_in_err.1297361202
Short name T923
Test name
Test status
Simulation time 217786630 ps
CPU time 0.93 seconds
Started Aug 05 05:39:20 PM PDT 24
Finished Aug 05 05:39:21 PM PDT 24
Peak memory 207320 kb
Host smart-51791f40-10a7-4bae-9a50-565a0abe71d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12973
61202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1297361202
Directory /workspace/40.usbdev_link_in_err/latest


Test location /workspace/coverage/default/40.usbdev_link_resume.3635228772
Short name T2865
Test name
Test status
Simulation time 7379189203 ps
CPU time 12.51 seconds
Started Aug 05 05:39:06 PM PDT 24
Finished Aug 05 05:39:19 PM PDT 24
Peak memory 215808 kb
Host smart-f0c0b411-9f8f-43b9-8554-0e07f6baedae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36352
28772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3635228772
Directory /workspace/40.usbdev_link_resume/latest


Test location /workspace/coverage/default/40.usbdev_link_suspend.4194345627
Short name T1249
Test name
Test status
Simulation time 5834752461 ps
CPU time 8.35 seconds
Started Aug 05 05:39:11 PM PDT 24
Finished Aug 05 05:39:19 PM PDT 24
Peak memory 207620 kb
Host smart-5faf36d3-6303-400e-9481-936fe73e74ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41943
45627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.4194345627
Directory /workspace/40.usbdev_link_suspend/latest


Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.736564462
Short name T578
Test name
Test status
Simulation time 3016013180 ps
CPU time 29.58 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:51 PM PDT 24
Peak memory 215908 kb
Host smart-38d58bc1-dccf-4f8c-b567-f4f082f6ebd2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=736564462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.736564462
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.1671951988
Short name T1409
Test name
Test status
Simulation time 240499250 ps
CPU time 1.05 seconds
Started Aug 05 05:39:02 PM PDT 24
Finished Aug 05 05:39:03 PM PDT 24
Peak memory 207400 kb
Host smart-2a7c255b-a9a4-422e-af17-64dde94673e3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1671951988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.1671951988
Directory /workspace/40.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2932590536
Short name T2985
Test name
Test status
Simulation time 185664420 ps
CPU time 0.93 seconds
Started Aug 05 05:39:15 PM PDT 24
Finished Aug 05 05:39:16 PM PDT 24
Peak memory 207424 kb
Host smart-aaf4a5fa-2d82-41f1-b4e2-98005d13f244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29325
90536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2932590536
Directory /workspace/40.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1562202196
Short name T2840
Test name
Test status
Simulation time 3484539658 ps
CPU time 35.31 seconds
Started Aug 05 05:39:10 PM PDT 24
Finished Aug 05 05:39:45 PM PDT 24
Peak memory 215932 kb
Host smart-68f24df2-7c1c-4b3c-8926-af245260297a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1562202196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1562202196
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3281129038
Short name T2305
Test name
Test status
Simulation time 155758086 ps
CPU time 0.92 seconds
Started Aug 05 05:39:04 PM PDT 24
Finished Aug 05 05:39:05 PM PDT 24
Peak memory 207352 kb
Host smart-c871c5f7-7bea-4f80-bcb5-007327daea62
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3281129038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3281129038
Directory /workspace/40.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2215169823
Short name T2070
Test name
Test status
Simulation time 172260254 ps
CPU time 0.9 seconds
Started Aug 05 05:39:08 PM PDT 24
Finished Aug 05 05:39:09 PM PDT 24
Peak memory 207240 kb
Host smart-c1feda79-b3bb-4b54-8195-ebcab79e4683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22151
69823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2215169823
Directory /workspace/40.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/40.usbdev_nak_trans.1774098145
Short name T2930
Test name
Test status
Simulation time 240890531 ps
CPU time 0.95 seconds
Started Aug 05 05:39:17 PM PDT 24
Finished Aug 05 05:39:18 PM PDT 24
Peak memory 207376 kb
Host smart-2105ca73-2901-48da-8fee-2f59ac912ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17740
98145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1774098145
Directory /workspace/40.usbdev_nak_trans/latest


Test location /workspace/coverage/default/40.usbdev_out_iso.1563730373
Short name T2574
Test name
Test status
Simulation time 174726590 ps
CPU time 0.93 seconds
Started Aug 05 05:39:01 PM PDT 24
Finished Aug 05 05:39:02 PM PDT 24
Peak memory 207248 kb
Host smart-ace56181-2277-404a-ae1e-c532979f837b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15637
30373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1563730373
Directory /workspace/40.usbdev_out_iso/latest


Test location /workspace/coverage/default/40.usbdev_out_stall.1169059466
Short name T2331
Test name
Test status
Simulation time 240605756 ps
CPU time 0.96 seconds
Started Aug 05 05:39:08 PM PDT 24
Finished Aug 05 05:39:09 PM PDT 24
Peak memory 207348 kb
Host smart-6e1247d7-52f4-47a4-9d83-dfb0451bc0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11690
59466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1169059466
Directory /workspace/40.usbdev_out_stall/latest


Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3570896378
Short name T864
Test name
Test status
Simulation time 210245739 ps
CPU time 0.91 seconds
Started Aug 05 05:39:12 PM PDT 24
Finished Aug 05 05:39:13 PM PDT 24
Peak memory 207352 kb
Host smart-f0511947-e658-4983-a2ed-c75d7e810bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35708
96378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3570896378
Directory /workspace/40.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1142011056
Short name T2806
Test name
Test status
Simulation time 159124168 ps
CPU time 0.89 seconds
Started Aug 05 05:39:16 PM PDT 24
Finished Aug 05 05:39:17 PM PDT 24
Peak memory 207404 kb
Host smart-c4c6b147-81ae-4fff-a145-f76b9b342654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11420
11056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1142011056
Directory /workspace/40.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.431134653
Short name T2743
Test name
Test status
Simulation time 198417092 ps
CPU time 0.95 seconds
Started Aug 05 05:39:15 PM PDT 24
Finished Aug 05 05:39:17 PM PDT 24
Peak memory 207276 kb
Host smart-cab5d975-0aae-47b4-90b9-fd94e34473b6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=431134653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.431134653
Directory /workspace/40.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2093848179
Short name T2169
Test name
Test status
Simulation time 194613222 ps
CPU time 0.86 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207344 kb
Host smart-0fffab87-4729-446a-85ab-5be63421bd64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20938
48179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2093848179
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2694273185
Short name T3118
Test name
Test status
Simulation time 34851728 ps
CPU time 0.71 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 207364 kb
Host smart-588453f3-d877-44cd-b25e-8139dd458757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26942
73185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2694273185
Directory /workspace/40.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/40.usbdev_pkt_buffer.922720564
Short name T2397
Test name
Test status
Simulation time 17257193378 ps
CPU time 42.96 seconds
Started Aug 05 05:39:13 PM PDT 24
Finished Aug 05 05:39:56 PM PDT 24
Peak memory 215860 kb
Host smart-a8aa02a3-6a38-4e7b-8a22-fbc3fa71b507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92272
0564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.922720564
Directory /workspace/40.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/40.usbdev_pkt_received.3649539103
Short name T1739
Test name
Test status
Simulation time 185368938 ps
CPU time 0.88 seconds
Started Aug 05 05:39:19 PM PDT 24
Finished Aug 05 05:39:20 PM PDT 24
Peak memory 207348 kb
Host smart-e21a0f73-45c1-4018-97c7-b63f0805fe67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36495
39103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3649539103
Directory /workspace/40.usbdev_pkt_received/latest


Test location /workspace/coverage/default/40.usbdev_pkt_sent.1290968125
Short name T1213
Test name
Test status
Simulation time 297587734 ps
CPU time 1.07 seconds
Started Aug 05 05:39:12 PM PDT 24
Finished Aug 05 05:39:14 PM PDT 24
Peak memory 207256 kb
Host smart-d85af3e7-490a-42ba-81e3-0eab6a4b9ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12909
68125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1290968125
Directory /workspace/40.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.655608862
Short name T1364
Test name
Test status
Simulation time 234872667 ps
CPU time 0.99 seconds
Started Aug 05 05:39:25 PM PDT 24
Finished Aug 05 05:39:26 PM PDT 24
Peak memory 207240 kb
Host smart-6227337c-d374-403f-aeb0-7867f84b95ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65560
8862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.655608862
Directory /workspace/40.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.3606263348
Short name T1052
Test name
Test status
Simulation time 176450104 ps
CPU time 0.92 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207320 kb
Host smart-dad57a72-e938-432f-b7f2-c43bad3759f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36062
63348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.3606263348
Directory /workspace/40.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/40.usbdev_rx_crc_err.1477926365
Short name T2083
Test name
Test status
Simulation time 152069454 ps
CPU time 0.8 seconds
Started Aug 05 05:39:27 PM PDT 24
Finished Aug 05 05:39:28 PM PDT 24
Peak memory 207252 kb
Host smart-f68777ce-cb0a-41be-9c52-b576f9978672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14779
26365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.1477926365
Directory /workspace/40.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/40.usbdev_setup_stage.4057713570
Short name T3129
Test name
Test status
Simulation time 144420488 ps
CPU time 0.83 seconds
Started Aug 05 05:39:14 PM PDT 24
Finished Aug 05 05:39:15 PM PDT 24
Peak memory 207348 kb
Host smart-43b1269e-7a6a-40a0-8534-b36ea42f41f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40577
13570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.4057713570
Directory /workspace/40.usbdev_setup_stage/latest


Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.585191122
Short name T1833
Test name
Test status
Simulation time 153956054 ps
CPU time 0.82 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 207612 kb
Host smart-5fafd771-f245-48c1-8d36-42d050c084d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58519
1122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.585191122
Directory /workspace/40.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/40.usbdev_smoke.1358457883
Short name T1702
Test name
Test status
Simulation time 194938182 ps
CPU time 1.06 seconds
Started Aug 05 05:39:18 PM PDT 24
Finished Aug 05 05:39:19 PM PDT 24
Peak memory 207400 kb
Host smart-6ffa46be-c903-43d9-ae34-35c4c0eb9992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13584
57883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1358457883
Directory /workspace/40.usbdev_smoke/latest


Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.3735948429
Short name T1483
Test name
Test status
Simulation time 2782391905 ps
CPU time 22.27 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:46 PM PDT 24
Peak memory 224020 kb
Host smart-4dd94aa7-3e52-49aa-888c-98c1ba275782
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3735948429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.3735948429
Directory /workspace/40.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.437491765
Short name T1631
Test name
Test status
Simulation time 168736403 ps
CPU time 0.96 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207328 kb
Host smart-e3f82f91-1cc6-4c8f-935a-66b3c5f5774e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43749
1765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.437491765
Directory /workspace/40.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/40.usbdev_stall_trans.2131541899
Short name T1861
Test name
Test status
Simulation time 201617119 ps
CPU time 0.85 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 207348 kb
Host smart-fe3eb039-312a-4fb8-bd2d-84937c10b28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21315
41899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2131541899
Directory /workspace/40.usbdev_stall_trans/latest


Test location /workspace/coverage/default/40.usbdev_stream_len_max.3648829074
Short name T812
Test name
Test status
Simulation time 1083380560 ps
CPU time 2.57 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207492 kb
Host smart-04a1f0b2-4dab-4f4a-afcf-0294bbb17611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36488
29074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3648829074
Directory /workspace/40.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/40.usbdev_streaming_out.603405061
Short name T723
Test name
Test status
Simulation time 2097730997 ps
CPU time 57.79 seconds
Started Aug 05 05:39:13 PM PDT 24
Finished Aug 05 05:40:11 PM PDT 24
Peak memory 223920 kb
Host smart-de632a50-bc45-4399-90d3-89d1e7c575a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60340
5061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.603405061
Directory /workspace/40.usbdev_streaming_out/latest


Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.1239553152
Short name T2348
Test name
Test status
Simulation time 3899840397 ps
CPU time 37.25 seconds
Started Aug 05 05:39:15 PM PDT 24
Finished Aug 05 05:39:52 PM PDT 24
Peak memory 207736 kb
Host smart-663f7a1f-6dab-4bfe-b930-62e8d4dca271
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239553152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.1239553152
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/41.usbdev_alert_test.1458621383
Short name T1319
Test name
Test status
Simulation time 40345175 ps
CPU time 0.69 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 207412 kb
Host smart-167f3224-2229-42fe-b02c-5af397a1d106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1458621383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1458621383
Directory /workspace/41.usbdev_alert_test/latest


Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3851963750
Short name T2247
Test name
Test status
Simulation time 5498461068 ps
CPU time 7.41 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:31 PM PDT 24
Peak memory 215852 kb
Host smart-77ee0bdf-df95-4c30-9e99-6761f851ccd6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851963750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.3851963750
Directory /workspace/41.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.2476438749
Short name T196
Test name
Test status
Simulation time 15705463388 ps
CPU time 17.89 seconds
Started Aug 05 05:39:19 PM PDT 24
Finished Aug 05 05:39:36 PM PDT 24
Peak memory 215824 kb
Host smart-c8d94134-d36e-49fc-ac73-70118df2b379
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476438749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.2476438749
Directory /workspace/41.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.1800577073
Short name T1142
Test name
Test status
Simulation time 29991135799 ps
CPU time 34.78 seconds
Started Aug 05 05:39:20 PM PDT 24
Finished Aug 05 05:39:54 PM PDT 24
Peak memory 207512 kb
Host smart-bf5baa5b-dce1-4869-a140-082df97716b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800577073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.1800577073
Directory /workspace/41.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/41.usbdev_av_buffer.3589110640
Short name T1559
Test name
Test status
Simulation time 159862976 ps
CPU time 0.86 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207240 kb
Host smart-d63ecd69-d945-4334-bd35-3eb8fd4f6fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35891
10640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3589110640
Directory /workspace/41.usbdev_av_buffer/latest


Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1367156083
Short name T2415
Test name
Test status
Simulation time 184087264 ps
CPU time 0.89 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 207320 kb
Host smart-8953c87d-b002-4139-a0e1-7aaded36af6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13671
56083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1367156083
Directory /workspace/41.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.1414713528
Short name T2114
Test name
Test status
Simulation time 505424276 ps
CPU time 1.71 seconds
Started Aug 05 05:39:16 PM PDT 24
Finished Aug 05 05:39:18 PM PDT 24
Peak memory 207296 kb
Host smart-4c33ca00-3833-4e1a-8425-d0ca793abce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14147
13528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.1414713528
Directory /workspace/41.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1689682517
Short name T831
Test name
Test status
Simulation time 884428794 ps
CPU time 2.54 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207612 kb
Host smart-7c71b61c-a35a-4442-b1b1-c86697087b6c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1689682517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1689682517
Directory /workspace/41.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/41.usbdev_device_address.4075518030
Short name T1924
Test name
Test status
Simulation time 38090921300 ps
CPU time 59.36 seconds
Started Aug 05 05:39:16 PM PDT 24
Finished Aug 05 05:40:16 PM PDT 24
Peak memory 207652 kb
Host smart-fc7b2a86-123b-403d-a641-bf68332fca76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40755
18030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.4075518030
Directory /workspace/41.usbdev_device_address/latest


Test location /workspace/coverage/default/41.usbdev_device_timeout.3451837038
Short name T749
Test name
Test status
Simulation time 564015038 ps
CPU time 11.76 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:36 PM PDT 24
Peak memory 207456 kb
Host smart-b6fc6c06-c67a-491e-aaa6-c9bb4190fdf6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451837038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.3451837038
Directory /workspace/41.usbdev_device_timeout/latest


Test location /workspace/coverage/default/41.usbdev_disable_endpoint.1391860347
Short name T1744
Test name
Test status
Simulation time 950072304 ps
CPU time 2.02 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207376 kb
Host smart-05a7bf6a-ca9a-4436-84ce-2ca6cfea8292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13918
60347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.1391860347
Directory /workspace/41.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/41.usbdev_disconnected.412904818
Short name T2849
Test name
Test status
Simulation time 135824990 ps
CPU time 0.85 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 207396 kb
Host smart-eebdb913-56d5-4fef-a23e-b155350c4b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41290
4818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.412904818
Directory /workspace/41.usbdev_disconnected/latest


Test location /workspace/coverage/default/41.usbdev_enable.2753260961
Short name T2086
Test name
Test status
Simulation time 29695754 ps
CPU time 0.7 seconds
Started Aug 05 05:39:15 PM PDT 24
Finished Aug 05 05:39:16 PM PDT 24
Peak memory 207248 kb
Host smart-dc0be630-8dad-4119-abfc-0cc944d518e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27532
60961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2753260961
Directory /workspace/41.usbdev_enable/latest


Test location /workspace/coverage/default/41.usbdev_endpoint_access.1349876255
Short name T1736
Test name
Test status
Simulation time 1127311561 ps
CPU time 2.77 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:27 PM PDT 24
Peak memory 207548 kb
Host smart-d70e7c62-8bfb-46ed-ab18-e765ffcdd54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13498
76255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.1349876255
Directory /workspace/41.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/41.usbdev_endpoint_types.2100637264
Short name T2266
Test name
Test status
Simulation time 376953088 ps
CPU time 1.2 seconds
Started Aug 05 05:39:17 PM PDT 24
Finished Aug 05 05:39:18 PM PDT 24
Peak memory 207216 kb
Host smart-e3109cc2-96dc-46a3-9380-6d13457c2a68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2100637264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.2100637264
Directory /workspace/41.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/41.usbdev_fifo_rst.3379402377
Short name T3066
Test name
Test status
Simulation time 200589518 ps
CPU time 1.59 seconds
Started Aug 05 05:39:16 PM PDT 24
Finished Aug 05 05:39:18 PM PDT 24
Peak memory 207544 kb
Host smart-589ba241-b68f-414e-9d1a-6bcd4bbc8af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33794
02377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3379402377
Directory /workspace/41.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/41.usbdev_in_iso.2959741905
Short name T1464
Test name
Test status
Simulation time 210244934 ps
CPU time 1.04 seconds
Started Aug 05 05:39:19 PM PDT 24
Finished Aug 05 05:39:21 PM PDT 24
Peak memory 207768 kb
Host smart-ab6e8b14-9918-4479-a828-cbe8a4654516
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2959741905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2959741905
Directory /workspace/41.usbdev_in_iso/latest


Test location /workspace/coverage/default/41.usbdev_in_stall.3731503904
Short name T1081
Test name
Test status
Simulation time 144568864 ps
CPU time 0.98 seconds
Started Aug 05 05:39:20 PM PDT 24
Finished Aug 05 05:39:26 PM PDT 24
Peak memory 207368 kb
Host smart-6166c4d4-8882-4e47-b67b-462a3e084865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37315
03904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3731503904
Directory /workspace/41.usbdev_in_stall/latest


Test location /workspace/coverage/default/41.usbdev_in_trans.840191461
Short name T1976
Test name
Test status
Simulation time 185522400 ps
CPU time 0.91 seconds
Started Aug 05 05:39:21 PM PDT 24
Finished Aug 05 05:39:22 PM PDT 24
Peak memory 207396 kb
Host smart-6f17561f-c492-48bd-8650-86b35a473af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84019
1461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.840191461
Directory /workspace/41.usbdev_in_trans/latest


Test location /workspace/coverage/default/41.usbdev_invalid_sync.3767846719
Short name T846
Test name
Test status
Simulation time 3287044846 ps
CPU time 92.41 seconds
Started Aug 05 05:39:35 PM PDT 24
Finished Aug 05 05:41:07 PM PDT 24
Peak memory 218416 kb
Host smart-20595031-30cb-49fc-b4c4-bfb1aa256bda
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3767846719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.3767846719
Directory /workspace/41.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/41.usbdev_iso_retraction.1157609605
Short name T1191
Test name
Test status
Simulation time 4294128261 ps
CPU time 52.65 seconds
Started Aug 05 05:39:13 PM PDT 24
Finished Aug 05 05:40:06 PM PDT 24
Peak memory 207632 kb
Host smart-a4c29947-ae8d-4060-9d6e-b075ebaee60e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1157609605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.1157609605
Directory /workspace/41.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/41.usbdev_link_in_err.827971685
Short name T2262
Test name
Test status
Simulation time 184360305 ps
CPU time 0.87 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 207368 kb
Host smart-e39b03d4-c0b8-4be9-a4f0-2299e8c383ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82797
1685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.827971685
Directory /workspace/41.usbdev_link_in_err/latest


Test location /workspace/coverage/default/41.usbdev_link_resume.3088948198
Short name T1555
Test name
Test status
Simulation time 9780470228 ps
CPU time 12.08 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:34 PM PDT 24
Peak memory 207632 kb
Host smart-36c2e33b-4b6f-46bf-ad70-67bde48aae08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30889
48198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3088948198
Directory /workspace/41.usbdev_link_resume/latest


Test location /workspace/coverage/default/41.usbdev_link_suspend.3832253759
Short name T1636
Test name
Test status
Simulation time 11326780565 ps
CPU time 14.27 seconds
Started Aug 05 05:39:25 PM PDT 24
Finished Aug 05 05:39:39 PM PDT 24
Peak memory 207668 kb
Host smart-ffc6ff89-5108-4217-b866-868e7ed65e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38322
53759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.3832253759
Directory /workspace/41.usbdev_link_suspend/latest


Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.3653808546
Short name T1270
Test name
Test status
Simulation time 4625625978 ps
CPU time 34.13 seconds
Started Aug 05 05:39:17 PM PDT 24
Finished Aug 05 05:39:52 PM PDT 24
Peak memory 215840 kb
Host smart-3d52be4a-ed78-48dd-a923-80d4660116b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36538
08546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.3653808546
Directory /workspace/41.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3921199349
Short name T1750
Test name
Test status
Simulation time 2951392477 ps
CPU time 29.64 seconds
Started Aug 05 05:39:17 PM PDT 24
Finished Aug 05 05:39:47 PM PDT 24
Peak memory 217516 kb
Host smart-d4feb4e0-5bd3-431d-ab37-5687e94f5f5e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3921199349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3921199349
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3178418988
Short name T855
Test name
Test status
Simulation time 240596117 ps
CPU time 0.97 seconds
Started Aug 05 05:39:18 PM PDT 24
Finished Aug 05 05:39:19 PM PDT 24
Peak memory 207368 kb
Host smart-f5810fa4-a3bf-47a2-9f7a-f1b42a5338d5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3178418988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3178418988
Directory /workspace/41.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3805993217
Short name T821
Test name
Test status
Simulation time 195220265 ps
CPU time 0.92 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207400 kb
Host smart-0eaac037-9ca2-4573-be0f-7803bf29c8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38059
93217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3805993217
Directory /workspace/41.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.1304354899
Short name T1099
Test name
Test status
Simulation time 2095617283 ps
CPU time 19.96 seconds
Started Aug 05 05:39:19 PM PDT 24
Finished Aug 05 05:39:39 PM PDT 24
Peak memory 215664 kb
Host smart-d894133a-2058-43c4-8237-e26347345be3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1304354899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.1304354899
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.3262273772
Short name T2745
Test name
Test status
Simulation time 185053324 ps
CPU time 0.9 seconds
Started Aug 05 05:39:18 PM PDT 24
Finished Aug 05 05:39:19 PM PDT 24
Peak memory 207352 kb
Host smart-584b1615-71e7-4de9-8b06-c6ebab139918
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3262273772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.3262273772
Directory /workspace/41.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2464897959
Short name T2059
Test name
Test status
Simulation time 204128294 ps
CPU time 0.89 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207400 kb
Host smart-f8bff695-d031-4b19-81b0-997beeb6e0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24648
97959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2464897959
Directory /workspace/41.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/41.usbdev_nak_trans.337693355
Short name T2713
Test name
Test status
Simulation time 208864623 ps
CPU time 1.01 seconds
Started Aug 05 05:39:20 PM PDT 24
Finished Aug 05 05:39:22 PM PDT 24
Peak memory 207228 kb
Host smart-a496303d-d766-4e64-a891-5b6e53435d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33769
3355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.337693355
Directory /workspace/41.usbdev_nak_trans/latest


Test location /workspace/coverage/default/41.usbdev_out_iso.2678475802
Short name T693
Test name
Test status
Simulation time 244820499 ps
CPU time 0.96 seconds
Started Aug 05 05:39:19 PM PDT 24
Finished Aug 05 05:39:20 PM PDT 24
Peak memory 207396 kb
Host smart-8464f762-1968-480f-86e0-d59173563f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26784
75802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2678475802
Directory /workspace/41.usbdev_out_iso/latest


Test location /workspace/coverage/default/41.usbdev_out_stall.2367589255
Short name T561
Test name
Test status
Simulation time 148361462 ps
CPU time 0.88 seconds
Started Aug 05 05:39:33 PM PDT 24
Finished Aug 05 05:39:34 PM PDT 24
Peak memory 207364 kb
Host smart-05b8b306-79e4-4ed3-a529-cec06a85b6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
89255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2367589255
Directory /workspace/41.usbdev_out_stall/latest


Test location /workspace/coverage/default/41.usbdev_out_trans_nak.4287119134
Short name T794
Test name
Test status
Simulation time 193173515 ps
CPU time 0.91 seconds
Started Aug 05 05:39:15 PM PDT 24
Finished Aug 05 05:39:16 PM PDT 24
Peak memory 207352 kb
Host smart-2a71965d-621d-4e49-b46d-157ca9600870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42871
19134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.4287119134
Directory /workspace/41.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1877303289
Short name T2448
Test name
Test status
Simulation time 176365010 ps
CPU time 0.91 seconds
Started Aug 05 05:39:14 PM PDT 24
Finished Aug 05 05:39:15 PM PDT 24
Peak memory 207384 kb
Host smart-4d425f7d-e804-43fc-aad4-7f2e9a91026c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18773
03289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1877303289
Directory /workspace/41.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.3537831456
Short name T2506
Test name
Test status
Simulation time 225216036 ps
CPU time 1.01 seconds
Started Aug 05 05:39:17 PM PDT 24
Finished Aug 05 05:39:18 PM PDT 24
Peak memory 207304 kb
Host smart-9f75c834-c255-4882-bb23-af9194961a36
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3537831456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.3537831456
Directory /workspace/41.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.54574296
Short name T198
Test name
Test status
Simulation time 145238091 ps
CPU time 0.83 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 207348 kb
Host smart-f8824c5b-4256-48fd-ba33-a6299b4f3f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54574
296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.54574296
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.368767393
Short name T1629
Test name
Test status
Simulation time 39391227 ps
CPU time 0.74 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 207288 kb
Host smart-9eb60be5-79b6-42d2-9f27-52b18d5ef3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36876
7393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.368767393
Directory /workspace/41.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1022580573
Short name T2147
Test name
Test status
Simulation time 17499222971 ps
CPU time 48.78 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:40:27 PM PDT 24
Peak memory 215716 kb
Host smart-4ddeb0fe-c7df-4d75-b866-8c5e92dea56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10225
80573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1022580573
Directory /workspace/41.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/41.usbdev_pkt_received.1334273498
Short name T2808
Test name
Test status
Simulation time 159461981 ps
CPU time 0.85 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:39:39 PM PDT 24
Peak memory 207336 kb
Host smart-4cf40f5e-c74e-4ea0-ada9-f725882b4bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13342
73498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1334273498
Directory /workspace/41.usbdev_pkt_received/latest


Test location /workspace/coverage/default/41.usbdev_pkt_sent.1437932071
Short name T2667
Test name
Test status
Simulation time 267771470 ps
CPU time 0.99 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:39:40 PM PDT 24
Peak memory 207328 kb
Host smart-3975ec28-a6a8-40f1-996d-a96921140e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14379
32071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1437932071
Directory /workspace/41.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3559445931
Short name T618
Test name
Test status
Simulation time 231591435 ps
CPU time 0.91 seconds
Started Aug 05 05:39:31 PM PDT 24
Finished Aug 05 05:39:32 PM PDT 24
Peak memory 207380 kb
Host smart-053a4527-2c06-4b8b-9758-4685f5fbc8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35594
45931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3559445931
Directory /workspace/41.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.2725818629
Short name T2319
Test name
Test status
Simulation time 245528653 ps
CPU time 0.99 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207604 kb
Host smart-3e7ef015-32ac-4edb-9bd5-5c1f1c10cd4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27258
18629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.2725818629
Directory /workspace/41.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/41.usbdev_rx_crc_err.809427556
Short name T701
Test name
Test status
Simulation time 157026601 ps
CPU time 0.86 seconds
Started Aug 05 05:39:25 PM PDT 24
Finished Aug 05 05:39:26 PM PDT 24
Peak memory 207256 kb
Host smart-88103fff-97de-4cc7-9626-aaaeba3ef141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80942
7556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.809427556
Directory /workspace/41.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/41.usbdev_rx_full.2914969239
Short name T284
Test name
Test status
Simulation time 258498698 ps
CPU time 1.13 seconds
Started Aug 05 05:39:30 PM PDT 24
Finished Aug 05 05:39:31 PM PDT 24
Peak memory 207320 kb
Host smart-018c1140-52f7-49a8-bb4f-15cb8fc9c0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29149
69239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.2914969239
Directory /workspace/41.usbdev_rx_full/latest


Test location /workspace/coverage/default/41.usbdev_setup_stage.3668206080
Short name T643
Test name
Test status
Simulation time 145342195 ps
CPU time 0.85 seconds
Started Aug 05 05:39:20 PM PDT 24
Finished Aug 05 05:39:21 PM PDT 24
Peak memory 207236 kb
Host smart-78b4b7bd-6c6b-4c98-a8bc-46903429e180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36682
06080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3668206080
Directory /workspace/41.usbdev_setup_stage/latest


Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2242341988
Short name T2987
Test name
Test status
Simulation time 157099780 ps
CPU time 0.86 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:42 PM PDT 24
Peak memory 207240 kb
Host smart-48c657f3-ef93-4ad6-add5-8383b7a938eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22423
41988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2242341988
Directory /workspace/41.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/41.usbdev_smoke.308163507
Short name T816
Test name
Test status
Simulation time 242211140 ps
CPU time 1.06 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 207348 kb
Host smart-ee21a390-8c64-46fe-ab23-da596934efeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30816
3507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.308163507
Directory /workspace/41.usbdev_smoke/latest


Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.4128346430
Short name T563
Test name
Test status
Simulation time 3878012759 ps
CPU time 110.17 seconds
Started Aug 05 05:39:21 PM PDT 24
Finished Aug 05 05:41:11 PM PDT 24
Peak memory 224056 kb
Host smart-1bf6ab4a-3c5a-4584-a9b0-d6a1bf2ab003
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4128346430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.4128346430
Directory /workspace/41.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.422762309
Short name T683
Test name
Test status
Simulation time 215693850 ps
CPU time 0.92 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 207324 kb
Host smart-d42477d8-26b1-401b-910e-ad729b08bfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42276
2309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.422762309
Directory /workspace/41.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/41.usbdev_stall_trans.2237376846
Short name T2427
Test name
Test status
Simulation time 201042272 ps
CPU time 0.97 seconds
Started Aug 05 05:39:34 PM PDT 24
Finished Aug 05 05:39:35 PM PDT 24
Peak memory 207364 kb
Host smart-11823727-c494-45d4-bbd5-ae1b2261a13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22373
76846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2237376846
Directory /workspace/41.usbdev_stall_trans/latest


Test location /workspace/coverage/default/41.usbdev_stream_len_max.2072829674
Short name T1876
Test name
Test status
Simulation time 827850384 ps
CPU time 2.21 seconds
Started Aug 05 05:39:30 PM PDT 24
Finished Aug 05 05:39:33 PM PDT 24
Peak memory 207576 kb
Host smart-620ce41c-153f-495b-a30b-a90f4c3f83d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20728
29674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.2072829674
Directory /workspace/41.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/41.usbdev_streaming_out.1249109413
Short name T3063
Test name
Test status
Simulation time 2692950892 ps
CPU time 26.91 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:40:04 PM PDT 24
Peak memory 215800 kb
Host smart-6e2e90f5-ee4e-4596-8ca3-f9808687711c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12491
09413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.1249109413
Directory /workspace/41.usbdev_streaming_out/latest


Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.3308155770
Short name T1852
Test name
Test status
Simulation time 9064724607 ps
CPU time 60.8 seconds
Started Aug 05 05:39:19 PM PDT 24
Finished Aug 05 05:40:20 PM PDT 24
Peak memory 207704 kb
Host smart-2eff4c3d-85bb-4d37-9c04-38874d1f3aa8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308155770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.3308155770
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/42.usbdev_alert_test.1272188151
Short name T1210
Test name
Test status
Simulation time 65985698 ps
CPU time 0.7 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207360 kb
Host smart-5ae7b628-a6c9-4ead-83c2-6e53ef2c0c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1272188151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1272188151
Directory /workspace/42.usbdev_alert_test/latest


Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3517486531
Short name T1948
Test name
Test status
Simulation time 9764709709 ps
CPU time 12.66 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:37 PM PDT 24
Peak memory 207608 kb
Host smart-7d903cad-8b4f-4f37-adaa-6f65a05de7bb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517486531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.3517486531
Directory /workspace/42.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.4209579193
Short name T12
Test name
Test status
Simulation time 19537011414 ps
CPU time 21.6 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:45 PM PDT 24
Peak memory 207688 kb
Host smart-033c22fc-4119-43de-9a34-7b50906e4926
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209579193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.4209579193
Directory /workspace/42.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1014964284
Short name T1775
Test name
Test status
Simulation time 28515546997 ps
CPU time 39.19 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207636 kb
Host smart-bd863508-0535-49e3-afb9-7a99ca1bb300
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014964284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.1014964284
Directory /workspace/42.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/42.usbdev_av_buffer.1384741969
Short name T1150
Test name
Test status
Simulation time 166922010 ps
CPU time 0.86 seconds
Started Aug 05 05:39:26 PM PDT 24
Finished Aug 05 05:39:27 PM PDT 24
Peak memory 207368 kb
Host smart-57387f34-c57d-405a-b317-de5cec2cc1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13847
41969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1384741969
Directory /workspace/42.usbdev_av_buffer/latest


Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3100884774
Short name T1414
Test name
Test status
Simulation time 164511378 ps
CPU time 0.84 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207292 kb
Host smart-f3338faa-424b-4029-b1dc-0e81378b3908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31008
84774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3100884774
Directory /workspace/42.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.174345584
Short name T3096
Test name
Test status
Simulation time 548838003 ps
CPU time 1.65 seconds
Started Aug 05 05:39:20 PM PDT 24
Finished Aug 05 05:39:21 PM PDT 24
Peak memory 207420 kb
Host smart-b7ec01f4-9cdc-4453-b18b-c3149b461759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17434
5584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.174345584
Directory /workspace/42.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3441888829
Short name T1145
Test name
Test status
Simulation time 620770583 ps
CPU time 1.64 seconds
Started Aug 05 05:39:20 PM PDT 24
Finished Aug 05 05:39:22 PM PDT 24
Peak memory 207256 kb
Host smart-b4dc286b-c03d-413a-af47-5f6a73ab91c6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3441888829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3441888829
Directory /workspace/42.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/42.usbdev_device_address.3323168131
Short name T2986
Test name
Test status
Simulation time 59868173233 ps
CPU time 98.05 seconds
Started Aug 05 05:39:25 PM PDT 24
Finished Aug 05 05:41:03 PM PDT 24
Peak memory 207604 kb
Host smart-ae9d26fb-c3a7-4656-9357-bde054fbd46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33231
68131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.3323168131
Directory /workspace/42.usbdev_device_address/latest


Test location /workspace/coverage/default/42.usbdev_device_timeout.3273220459
Short name T548
Test name
Test status
Simulation time 1373970841 ps
CPU time 33.36 seconds
Started Aug 05 05:39:35 PM PDT 24
Finished Aug 05 05:40:08 PM PDT 24
Peak memory 207604 kb
Host smart-1391a534-0ec6-4d1b-aea9-d85a724fda62
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273220459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.3273220459
Directory /workspace/42.usbdev_device_timeout/latest


Test location /workspace/coverage/default/42.usbdev_disable_endpoint.841655959
Short name T3030
Test name
Test status
Simulation time 493406849 ps
CPU time 1.34 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:39:39 PM PDT 24
Peak memory 207380 kb
Host smart-b27a4ab1-e3a5-423f-a931-ffb791c158ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84165
5959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.841655959
Directory /workspace/42.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/42.usbdev_disconnected.1232451823
Short name T1619
Test name
Test status
Simulation time 150970867 ps
CPU time 0.84 seconds
Started Aug 05 05:39:40 PM PDT 24
Finished Aug 05 05:39:41 PM PDT 24
Peak memory 207288 kb
Host smart-89c14bc8-5c83-444f-9c6a-1de3beb11d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12324
51823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1232451823
Directory /workspace/42.usbdev_disconnected/latest


Test location /workspace/coverage/default/42.usbdev_enable.2505026420
Short name T2856
Test name
Test status
Simulation time 52295447 ps
CPU time 0.7 seconds
Started Aug 05 05:39:21 PM PDT 24
Finished Aug 05 05:39:22 PM PDT 24
Peak memory 207332 kb
Host smart-9dd1db90-405b-4ba1-889c-3bfe02ce161e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25050
26420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2505026420
Directory /workspace/42.usbdev_enable/latest


Test location /workspace/coverage/default/42.usbdev_endpoint_access.784574637
Short name T2629
Test name
Test status
Simulation time 867033253 ps
CPU time 2.61 seconds
Started Aug 05 05:39:20 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 207580 kb
Host smart-270d28bd-7704-4b02-bd9a-8800934d2631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78457
4637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.784574637
Directory /workspace/42.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/42.usbdev_endpoint_types.2255474543
Short name T415
Test name
Test status
Simulation time 498566234 ps
CPU time 1.36 seconds
Started Aug 05 05:39:30 PM PDT 24
Finished Aug 05 05:39:31 PM PDT 24
Peak memory 207324 kb
Host smart-7fc65dd6-c915-4066-bdf6-f15ce1318517
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2255474543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.2255474543
Directory /workspace/42.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/42.usbdev_fifo_rst.4027560687
Short name T1687
Test name
Test status
Simulation time 214464457 ps
CPU time 1.59 seconds
Started Aug 05 05:39:21 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 207428 kb
Host smart-68641976-2714-45bf-8522-19b545a65e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40275
60687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.4027560687
Directory /workspace/42.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/42.usbdev_in_iso.1845986262
Short name T1420
Test name
Test status
Simulation time 166684121 ps
CPU time 0.89 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:39:44 PM PDT 24
Peak memory 207264 kb
Host smart-2b9834b6-d45e-4505-9deb-fb108e26de54
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1845986262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1845986262
Directory /workspace/42.usbdev_in_iso/latest


Test location /workspace/coverage/default/42.usbdev_in_stall.114518403
Short name T2577
Test name
Test status
Simulation time 164483790 ps
CPU time 0.89 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 207332 kb
Host smart-9161e7d4-7402-4101-85e2-1203f376614f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11451
8403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.114518403
Directory /workspace/42.usbdev_in_stall/latest


Test location /workspace/coverage/default/42.usbdev_in_trans.1986178122
Short name T3049
Test name
Test status
Simulation time 209457712 ps
CPU time 0.86 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 207396 kb
Host smart-9198a023-e6d7-4f49-8aec-16f2bce3edcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19861
78122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1986178122
Directory /workspace/42.usbdev_in_trans/latest


Test location /workspace/coverage/default/42.usbdev_invalid_sync.3640975969
Short name T1413
Test name
Test status
Simulation time 4993471781 ps
CPU time 38.32 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:40:15 PM PDT 24
Peak memory 224000 kb
Host smart-135def89-aa89-41a9-b93d-99d1f5944338
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3640975969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.3640975969
Directory /workspace/42.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/42.usbdev_iso_retraction.3203164470
Short name T2791
Test name
Test status
Simulation time 8309124612 ps
CPU time 101.32 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:41:05 PM PDT 24
Peak memory 207620 kb
Host smart-adcc98bd-c4e5-4333-a798-d94ebaed5799
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3203164470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.3203164470
Directory /workspace/42.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/42.usbdev_link_in_err.2696034022
Short name T2701
Test name
Test status
Simulation time 188940129 ps
CPU time 0.88 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207348 kb
Host smart-3db94389-e936-49fe-9454-349a87475e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26960
34022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2696034022
Directory /workspace/42.usbdev_link_in_err/latest


Test location /workspace/coverage/default/42.usbdev_link_suspend.2057033902
Short name T1688
Test name
Test status
Simulation time 3783753834 ps
CPU time 5.88 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:39:45 PM PDT 24
Peak memory 215808 kb
Host smart-0140dec6-aa59-4214-b9e5-3aebe8f63a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20570
33902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2057033902
Directory /workspace/42.usbdev_link_suspend/latest


Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.238852000
Short name T1050
Test name
Test status
Simulation time 5166029552 ps
CPU time 49.81 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:40:14 PM PDT 24
Peak memory 218640 kb
Host smart-a3877759-5a42-4caf-b085-3d5236558c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23885
2000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.238852000
Directory /workspace/42.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3142522297
Short name T1293
Test name
Test status
Simulation time 3359339660 ps
CPU time 34.92 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:58 PM PDT 24
Peak memory 215828 kb
Host smart-c6b7e267-6c85-49f0-aa50-ad742fc7f8b6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3142522297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3142522297
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.312351586
Short name T876
Test name
Test status
Simulation time 238793685 ps
CPU time 0.98 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207352 kb
Host smart-693064e3-d46e-4407-9578-1fa16812780b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=312351586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.312351586
Directory /workspace/42.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2527382218
Short name T2113
Test name
Test status
Simulation time 209739217 ps
CPU time 0.96 seconds
Started Aug 05 05:39:34 PM PDT 24
Finished Aug 05 05:39:35 PM PDT 24
Peak memory 207404 kb
Host smart-eb7117d1-53ee-40c2-aa7d-4fa56c97e5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25273
82218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2527382218
Directory /workspace/42.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3863828445
Short name T2471
Test name
Test status
Simulation time 2679672661 ps
CPU time 20.65 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:44 PM PDT 24
Peak memory 207700 kb
Host smart-9fad85c7-eb61-4c6b-9daa-c29c2dd88ebe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3863828445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3863828445
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3684443143
Short name T1537
Test name
Test status
Simulation time 153017082 ps
CPU time 0.85 seconds
Started Aug 05 05:39:40 PM PDT 24
Finished Aug 05 05:39:41 PM PDT 24
Peak memory 207416 kb
Host smart-0d8dbda1-867b-4b23-871f-5f6d763b2f92
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3684443143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3684443143
Directory /workspace/42.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.975630934
Short name T1390
Test name
Test status
Simulation time 156624962 ps
CPU time 0.86 seconds
Started Aug 05 05:39:33 PM PDT 24
Finished Aug 05 05:39:34 PM PDT 24
Peak memory 207352 kb
Host smart-3adf78f1-b3ef-438d-a42b-4eba686a95fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97563
0934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.975630934
Directory /workspace/42.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/42.usbdev_nak_trans.1699268082
Short name T2012
Test name
Test status
Simulation time 266967039 ps
CPU time 0.96 seconds
Started Aug 05 05:39:20 PM PDT 24
Finished Aug 05 05:39:21 PM PDT 24
Peak memory 207416 kb
Host smart-ccd23b2a-7d50-46e9-b14b-b0fce3e11799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16992
68082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1699268082
Directory /workspace/42.usbdev_nak_trans/latest


Test location /workspace/coverage/default/42.usbdev_out_iso.843734443
Short name T774
Test name
Test status
Simulation time 178367976 ps
CPU time 0.88 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 207324 kb
Host smart-e0b415bb-8952-4fe7-9035-8e5cdebbdb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84373
4443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.843734443
Directory /workspace/42.usbdev_out_iso/latest


Test location /workspace/coverage/default/42.usbdev_out_stall.4278109283
Short name T1407
Test name
Test status
Simulation time 173751270 ps
CPU time 0.88 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207328 kb
Host smart-ad6c4ae6-6c27-490c-a13f-8cfead329152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42781
09283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.4278109283
Directory /workspace/42.usbdev_out_stall/latest


Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3172195766
Short name T3133
Test name
Test status
Simulation time 187493640 ps
CPU time 0.86 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207272 kb
Host smart-6b3add8d-233e-4a02-8346-1b9ab77abf95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31721
95766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3172195766
Directory /workspace/42.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2749048973
Short name T2703
Test name
Test status
Simulation time 153096371 ps
CPU time 0.87 seconds
Started Aug 05 05:39:29 PM PDT 24
Finished Aug 05 05:39:30 PM PDT 24
Peak memory 207268 kb
Host smart-bd493238-30c3-4fd2-ac83-01d851154be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27490
48973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2749048973
Directory /workspace/42.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.3222363220
Short name T2230
Test name
Test status
Simulation time 244820728 ps
CPU time 0.99 seconds
Started Aug 05 05:39:26 PM PDT 24
Finished Aug 05 05:39:28 PM PDT 24
Peak memory 207272 kb
Host smart-f20598e5-169b-4ca8-9b56-b44f9f2b5c8c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3222363220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.3222363220
Directory /workspace/42.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3012488533
Short name T823
Test name
Test status
Simulation time 172684383 ps
CPU time 0.88 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:39:40 PM PDT 24
Peak memory 207228 kb
Host smart-b334a3bf-0d47-4eb6-9723-3c637a544a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30124
88533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3012488533
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2617826772
Short name T2685
Test name
Test status
Simulation time 30891548 ps
CPU time 0.69 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 207364 kb
Host smart-15b11346-e285-4a26-8143-ac2795dcbb1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26178
26772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2617826772
Directory /workspace/42.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/42.usbdev_pkt_buffer.627235935
Short name T3098
Test name
Test status
Simulation time 6393646494 ps
CPU time 16.87 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:39:54 PM PDT 24
Peak memory 215860 kb
Host smart-4cbd2bf7-e781-482f-8304-fc1fa864e305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62723
5935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.627235935
Directory /workspace/42.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/42.usbdev_pkt_received.2572380735
Short name T1092
Test name
Test status
Simulation time 199746164 ps
CPU time 0.93 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:24 PM PDT 24
Peak memory 207252 kb
Host smart-6adacdc5-514b-410d-a2da-9dc2de5b88a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25723
80735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2572380735
Directory /workspace/42.usbdev_pkt_received/latest


Test location /workspace/coverage/default/42.usbdev_pkt_sent.3647792007
Short name T3026
Test name
Test status
Simulation time 238706764 ps
CPU time 0.97 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:43 PM PDT 24
Peak memory 207316 kb
Host smart-e8015520-6365-4cf9-bcfa-1b26c1b64fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36477
92007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3647792007
Directory /workspace/42.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2978129686
Short name T1219
Test name
Test status
Simulation time 205465845 ps
CPU time 0.95 seconds
Started Aug 05 05:39:26 PM PDT 24
Finished Aug 05 05:39:28 PM PDT 24
Peak memory 207328 kb
Host smart-1a97455c-ec5b-4cf4-aad0-fc9577e93bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29781
29686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2978129686
Directory /workspace/42.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.695593817
Short name T2202
Test name
Test status
Simulation time 203399087 ps
CPU time 0.95 seconds
Started Aug 05 05:39:35 PM PDT 24
Finished Aug 05 05:39:36 PM PDT 24
Peak memory 207348 kb
Host smart-3c485771-8cf4-44eb-acc2-72847d820899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69559
3817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.695593817
Directory /workspace/42.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1379821286
Short name T1163
Test name
Test status
Simulation time 228244401 ps
CPU time 0.98 seconds
Started Aug 05 05:39:34 PM PDT 24
Finished Aug 05 05:39:36 PM PDT 24
Peak memory 207328 kb
Host smart-3337ff71-ff17-4e3d-829e-13c9ae911ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13798
21286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1379821286
Directory /workspace/42.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/42.usbdev_rx_full.3109417857
Short name T57
Test name
Test status
Simulation time 352424516 ps
CPU time 1.27 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:39:40 PM PDT 24
Peak memory 207296 kb
Host smart-16d406dd-4bb5-406c-8723-ee5a03e678a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31094
17857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.3109417857
Directory /workspace/42.usbdev_rx_full/latest


Test location /workspace/coverage/default/42.usbdev_setup_stage.365620749
Short name T931
Test name
Test status
Simulation time 152493141 ps
CPU time 0.82 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:23 PM PDT 24
Peak memory 207256 kb
Host smart-ef49ad9e-16b6-445c-9872-40e62ce313b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36562
0749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.365620749
Directory /workspace/42.usbdev_setup_stage/latest


Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3205516801
Short name T863
Test name
Test status
Simulation time 151273744 ps
CPU time 0.83 seconds
Started Aug 05 05:39:30 PM PDT 24
Finished Aug 05 05:39:31 PM PDT 24
Peak memory 207352 kb
Host smart-023bf804-fecf-4687-9b45-29d64a067f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32055
16801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3205516801
Directory /workspace/42.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/42.usbdev_smoke.3336947229
Short name T2337
Test name
Test status
Simulation time 225169885 ps
CPU time 1.06 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:39:39 PM PDT 24
Peak memory 207304 kb
Host smart-b1ff2090-8a77-4852-8c72-f963226e4eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33369
47229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3336947229
Directory /workspace/42.usbdev_smoke/latest


Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.4227518223
Short name T1764
Test name
Test status
Simulation time 2923110590 ps
CPU time 29.38 seconds
Started Aug 05 05:39:33 PM PDT 24
Finished Aug 05 05:40:03 PM PDT 24
Peak memory 217844 kb
Host smart-eacd4e95-ea62-40a5-87cb-0d6fdb83fa5d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4227518223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.4227518223
Directory /workspace/42.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.882336792
Short name T949
Test name
Test status
Simulation time 210370779 ps
CPU time 0.91 seconds
Started Aug 05 05:39:27 PM PDT 24
Finished Aug 05 05:39:28 PM PDT 24
Peak memory 207372 kb
Host smart-c847f978-c1af-4a38-96b6-45429c1cdc35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88233
6792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.882336792
Directory /workspace/42.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/42.usbdev_stall_trans.316810836
Short name T662
Test name
Test status
Simulation time 192171008 ps
CPU time 0.91 seconds
Started Aug 05 05:39:24 PM PDT 24
Finished Aug 05 05:39:25 PM PDT 24
Peak memory 207604 kb
Host smart-210a67f2-b5db-4665-a8a1-d9221dc22c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31681
0836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.316810836
Directory /workspace/42.usbdev_stall_trans/latest


Test location /workspace/coverage/default/42.usbdev_stream_len_max.2430465945
Short name T1156
Test name
Test status
Simulation time 327882220 ps
CPU time 1.21 seconds
Started Aug 05 05:39:40 PM PDT 24
Finished Aug 05 05:39:42 PM PDT 24
Peak memory 207344 kb
Host smart-352b1ed0-81f6-4279-ab38-0d60c2397ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24304
65945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.2430465945
Directory /workspace/42.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/42.usbdev_streaming_out.1925375647
Short name T836
Test name
Test status
Simulation time 3050862626 ps
CPU time 94.32 seconds
Started Aug 05 05:39:30 PM PDT 24
Finished Aug 05 05:41:04 PM PDT 24
Peak memory 215824 kb
Host smart-38210a47-460d-4843-9dcd-186af6944b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19253
75647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1925375647
Directory /workspace/42.usbdev_streaming_out/latest


Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.1792084030
Short name T572
Test name
Test status
Simulation time 2931771785 ps
CPU time 26.01 seconds
Started Aug 05 05:39:23 PM PDT 24
Finished Aug 05 05:39:50 PM PDT 24
Peak memory 207656 kb
Host smart-28e754bf-22d0-4aa7-8aa0-0ebeb6094d01
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792084030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.1792084030
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/43.usbdev_alert_test.1837770420
Short name T194
Test name
Test status
Simulation time 59948015 ps
CPU time 0.67 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:39:48 PM PDT 24
Peak memory 207416 kb
Host smart-4db71957-591c-421a-8312-22d9f97a1afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1837770420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.1837770420
Directory /workspace/43.usbdev_alert_test/latest


Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.2683318275
Short name T1776
Test name
Test status
Simulation time 5704391761 ps
CPU time 7.54 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:48 PM PDT 24
Peak memory 215848 kb
Host smart-c58f27bd-3cf3-4a45-946c-438bb2308880
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683318275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.2683318275
Directory /workspace/43.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1587382235
Short name T1140
Test name
Test status
Simulation time 21330455278 ps
CPU time 27.06 seconds
Started Aug 05 05:39:27 PM PDT 24
Finished Aug 05 05:39:54 PM PDT 24
Peak memory 207688 kb
Host smart-d27f45a3-d16f-4265-a2cb-0398de89b74c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587382235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1587382235
Directory /workspace/43.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1184154617
Short name T684
Test name
Test status
Simulation time 30138815354 ps
CPU time 32.53 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:40:11 PM PDT 24
Peak memory 207576 kb
Host smart-c605e856-12db-4d06-8c89-afa5357bb27d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184154617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.1184154617
Directory /workspace/43.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/43.usbdev_av_buffer.3912523042
Short name T636
Test name
Test status
Simulation time 239975238 ps
CPU time 0.94 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:39:39 PM PDT 24
Peak memory 207348 kb
Host smart-bfb84d9a-dfb2-4602-8216-ef78c86eb310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39125
23042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3912523042
Directory /workspace/43.usbdev_av_buffer/latest


Test location /workspace/coverage/default/43.usbdev_bitstuff_err.623618628
Short name T853
Test name
Test status
Simulation time 147043742 ps
CPU time 0.87 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:42 PM PDT 24
Peak memory 207236 kb
Host smart-eef40a56-6ddf-42f7-afc7-699b5201c4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62361
8628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.623618628
Directory /workspace/43.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2310180408
Short name T497
Test name
Test status
Simulation time 154892340 ps
CPU time 0.82 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 207312 kb
Host smart-3c877be4-dcfb-4c87-bd1c-71f4c0ebbc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23101
80408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2310180408
Directory /workspace/43.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1858271776
Short name T630
Test name
Test status
Simulation time 912164746 ps
CPU time 2.54 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:39:40 PM PDT 24
Peak memory 207528 kb
Host smart-a00c0d5c-bc2c-4c81-bce2-a06886e9837b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1858271776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1858271776
Directory /workspace/43.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/43.usbdev_device_address.660040456
Short name T1378
Test name
Test status
Simulation time 50372275892 ps
CPU time 86.77 seconds
Started Aug 05 05:39:36 PM PDT 24
Finished Aug 05 05:41:02 PM PDT 24
Peak memory 207576 kb
Host smart-dbbc9ccb-e97b-4821-a480-05b348868f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66004
0456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.660040456
Directory /workspace/43.usbdev_device_address/latest


Test location /workspace/coverage/default/43.usbdev_device_timeout.2637044987
Short name T2759
Test name
Test status
Simulation time 1503559478 ps
CPU time 13.23 seconds
Started Aug 05 05:39:29 PM PDT 24
Finished Aug 05 05:39:42 PM PDT 24
Peak memory 207460 kb
Host smart-141cb4b5-4842-43fe-82ce-ab6769f4b13f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637044987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.2637044987
Directory /workspace/43.usbdev_device_timeout/latest


Test location /workspace/coverage/default/43.usbdev_disable_endpoint.2947289340
Short name T2045
Test name
Test status
Simulation time 1060782108 ps
CPU time 2.35 seconds
Started Aug 05 05:39:34 PM PDT 24
Finished Aug 05 05:39:37 PM PDT 24
Peak memory 207324 kb
Host smart-10df5038-7452-4c62-a2ce-f649eaad3996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29472
89340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.2947289340
Directory /workspace/43.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/43.usbdev_disconnected.2851648842
Short name T1947
Test name
Test status
Simulation time 144714139 ps
CPU time 0.79 seconds
Started Aug 05 05:39:29 PM PDT 24
Finished Aug 05 05:39:30 PM PDT 24
Peak memory 207240 kb
Host smart-7d7d4780-0a8d-4629-9b93-d3b621a09408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28516
48842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2851648842
Directory /workspace/43.usbdev_disconnected/latest


Test location /workspace/coverage/default/43.usbdev_enable.3627410942
Short name T2710
Test name
Test status
Simulation time 60237742 ps
CPU time 0.79 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 207232 kb
Host smart-5c8012d2-d3d3-43c1-be2e-8ec8b0798980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36274
10942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3627410942
Directory /workspace/43.usbdev_enable/latest


Test location /workspace/coverage/default/43.usbdev_endpoint_access.1324012223
Short name T504
Test name
Test status
Simulation time 991856145 ps
CPU time 2.68 seconds
Started Aug 05 05:39:29 PM PDT 24
Finished Aug 05 05:39:32 PM PDT 24
Peak memory 207600 kb
Host smart-9e31a5ed-d9d3-4824-9f85-540956512afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13240
12223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1324012223
Directory /workspace/43.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/43.usbdev_endpoint_types.2062043281
Short name T444
Test name
Test status
Simulation time 273518996 ps
CPU time 1.02 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:39:40 PM PDT 24
Peak memory 207324 kb
Host smart-11e24d67-ba8c-4377-a522-7b09afa4e04b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2062043281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.2062043281
Directory /workspace/43.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/43.usbdev_fifo_rst.1557781930
Short name T1130
Test name
Test status
Simulation time 281832480 ps
CPU time 1.74 seconds
Started Aug 05 05:39:31 PM PDT 24
Finished Aug 05 05:39:32 PM PDT 24
Peak memory 207568 kb
Host smart-6a64dff6-a39a-4995-9ee1-c389e22b3328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15577
81930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1557781930
Directory /workspace/43.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/43.usbdev_in_iso.557752287
Short name T2203
Test name
Test status
Simulation time 154135954 ps
CPU time 0.88 seconds
Started Aug 05 05:39:29 PM PDT 24
Finished Aug 05 05:39:30 PM PDT 24
Peak memory 207404 kb
Host smart-8b93a1a0-fe4d-4e90-9cf0-3a26bfcc899f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=557752287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.557752287
Directory /workspace/43.usbdev_in_iso/latest


Test location /workspace/coverage/default/43.usbdev_in_stall.2251838904
Short name T3041
Test name
Test status
Simulation time 154676302 ps
CPU time 0.87 seconds
Started Aug 05 05:39:28 PM PDT 24
Finished Aug 05 05:39:29 PM PDT 24
Peak memory 207256 kb
Host smart-df062aa4-6df0-43ab-805b-3c015a1db125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22518
38904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2251838904
Directory /workspace/43.usbdev_in_stall/latest


Test location /workspace/coverage/default/43.usbdev_in_trans.4199918814
Short name T2582
Test name
Test status
Simulation time 260194960 ps
CPU time 1.02 seconds
Started Aug 05 05:39:35 PM PDT 24
Finished Aug 05 05:39:37 PM PDT 24
Peak memory 207352 kb
Host smart-13ad90ca-1eb9-4450-87b9-28c8d21b12f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41999
18814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.4199918814
Directory /workspace/43.usbdev_in_trans/latest


Test location /workspace/coverage/default/43.usbdev_invalid_sync.1171807864
Short name T1639
Test name
Test status
Simulation time 3235637441 ps
CPU time 25.26 seconds
Started Aug 05 05:39:45 PM PDT 24
Finished Aug 05 05:40:10 PM PDT 24
Peak memory 223932 kb
Host smart-804af477-d6f2-466b-8592-1c7d2c04bb91
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1171807864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.1171807864
Directory /workspace/43.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/43.usbdev_iso_retraction.2863969938
Short name T872
Test name
Test status
Simulation time 9108615992 ps
CPU time 69.05 seconds
Started Aug 05 05:39:35 PM PDT 24
Finished Aug 05 05:40:45 PM PDT 24
Peak memory 207620 kb
Host smart-5ca54daf-a146-461a-965a-8271de8d7903
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2863969938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.2863969938
Directory /workspace/43.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/43.usbdev_link_in_err.2638460264
Short name T965
Test name
Test status
Simulation time 267124169 ps
CPU time 1.01 seconds
Started Aug 05 05:39:43 PM PDT 24
Finished Aug 05 05:39:44 PM PDT 24
Peak memory 207300 kb
Host smart-143885bb-427f-4f9a-a240-a4f9859efc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26384
60264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2638460264
Directory /workspace/43.usbdev_link_in_err/latest


Test location /workspace/coverage/default/43.usbdev_link_resume.1251234040
Short name T825
Test name
Test status
Simulation time 28339875477 ps
CPU time 42.74 seconds
Started Aug 05 05:39:36 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207596 kb
Host smart-bd40735a-4389-4426-bd55-f069fc5c0b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12512
34040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1251234040
Directory /workspace/43.usbdev_link_resume/latest


Test location /workspace/coverage/default/43.usbdev_link_suspend.2896060759
Short name T2221
Test name
Test status
Simulation time 9636736439 ps
CPU time 11.15 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:39:49 PM PDT 24
Peak memory 207536 kb
Host smart-97b913b1-ea5a-4778-bb72-b68b9c1bd35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28960
60759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.2896060759
Directory /workspace/43.usbdev_link_suspend/latest


Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.3500942182
Short name T1807
Test name
Test status
Simulation time 3181801843 ps
CPU time 30.35 seconds
Started Aug 05 05:39:22 PM PDT 24
Finished Aug 05 05:39:53 PM PDT 24
Peak memory 217700 kb
Host smart-30cc29c1-23ce-4031-91e4-cb86a2e2c14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35009
42182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.3500942182
Directory /workspace/43.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1646405557
Short name T2091
Test name
Test status
Simulation time 2415233335 ps
CPU time 17.92 seconds
Started Aug 05 05:39:43 PM PDT 24
Finished Aug 05 05:40:01 PM PDT 24
Peak memory 216976 kb
Host smart-7386435c-b37d-431c-a647-28ac651224e2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1646405557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1646405557
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.917257034
Short name T1240
Test name
Test status
Simulation time 276568472 ps
CPU time 1.08 seconds
Started Aug 05 05:39:45 PM PDT 24
Finished Aug 05 05:39:46 PM PDT 24
Peak memory 207352 kb
Host smart-d527b1ae-2af1-471b-9f15-d8179aa7a740
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=917257034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.917257034
Directory /workspace/43.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1471749643
Short name T2741
Test name
Test status
Simulation time 198222182 ps
CPU time 0.93 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 207276 kb
Host smart-6cab10c0-02d9-489b-a3a9-3069c9117757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14717
49643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1471749643
Directory /workspace/43.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3130628937
Short name T1490
Test name
Test status
Simulation time 2089734802 ps
CPU time 58.27 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 215744 kb
Host smart-b80b825f-c822-4c52-9bce-d2d0bcefb38e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3130628937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3130628937
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2638385188
Short name T2946
Test name
Test status
Simulation time 161048431 ps
CPU time 0.84 seconds
Started Aug 05 05:39:32 PM PDT 24
Finished Aug 05 05:39:33 PM PDT 24
Peak memory 207400 kb
Host smart-c3a7883d-9138-4722-9a0b-8be3ff90a473
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2638385188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2638385188
Directory /workspace/43.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3150085625
Short name T752
Test name
Test status
Simulation time 153329047 ps
CPU time 0.86 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:42 PM PDT 24
Peak memory 207328 kb
Host smart-d0b711d8-0a30-44c9-a56f-a7cb6e0aa7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31500
85625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3150085625
Directory /workspace/43.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/43.usbdev_nak_trans.1433021038
Short name T148
Test name
Test status
Simulation time 194236586 ps
CPU time 0.94 seconds
Started Aug 05 05:39:43 PM PDT 24
Finished Aug 05 05:39:44 PM PDT 24
Peak memory 207368 kb
Host smart-c8a2bcc8-c496-4ca2-a57b-afa9312843af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14330
21038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1433021038
Directory /workspace/43.usbdev_nak_trans/latest


Test location /workspace/coverage/default/43.usbdev_out_iso.4174262153
Short name T2529
Test name
Test status
Simulation time 157095372 ps
CPU time 0.84 seconds
Started Aug 05 05:39:42 PM PDT 24
Finished Aug 05 05:39:43 PM PDT 24
Peak memory 207348 kb
Host smart-678c7ed2-b9a3-44fc-addd-181534a77cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41742
62153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.4174262153
Directory /workspace/43.usbdev_out_iso/latest


Test location /workspace/coverage/default/43.usbdev_out_stall.4079135266
Short name T1602
Test name
Test status
Simulation time 158927530 ps
CPU time 0.82 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:39:39 PM PDT 24
Peak memory 207320 kb
Host smart-f90084b5-be37-4b64-a61d-f26c978d6229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40791
35266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.4079135266
Directory /workspace/43.usbdev_out_stall/latest


Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1973473416
Short name T1312
Test name
Test status
Simulation time 167397722 ps
CPU time 0.84 seconds
Started Aug 05 05:39:33 PM PDT 24
Finished Aug 05 05:39:34 PM PDT 24
Peak memory 207384 kb
Host smart-f5b9f738-ec97-4f2f-90c1-58044bd59b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19734
73416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1973473416
Directory /workspace/43.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1631796850
Short name T1011
Test name
Test status
Simulation time 161980550 ps
CPU time 0.87 seconds
Started Aug 05 05:39:40 PM PDT 24
Finished Aug 05 05:39:41 PM PDT 24
Peak memory 207356 kb
Host smart-f49d0a94-ae6b-4d85-815c-4f631beb2697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16317
96850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1631796850
Directory /workspace/43.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.1629068885
Short name T2066
Test name
Test status
Simulation time 183475216 ps
CPU time 0.93 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:42 PM PDT 24
Peak memory 207232 kb
Host smart-80bcbdb0-61b7-4c10-acbd-945461f872ae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1629068885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.1629068885
Directory /workspace/43.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1088403624
Short name T2561
Test name
Test status
Simulation time 150710483 ps
CPU time 0.85 seconds
Started Aug 05 05:39:40 PM PDT 24
Finished Aug 05 05:39:41 PM PDT 24
Peak memory 207384 kb
Host smart-3cbdc362-d42f-4997-9d14-f78cc54250b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10884
03624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1088403624
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.109882078
Short name T44
Test name
Test status
Simulation time 37107385 ps
CPU time 0.67 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:39:40 PM PDT 24
Peak memory 207344 kb
Host smart-f1547e6d-9daa-423c-a24b-468a0aa684e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10988
2078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.109882078
Directory /workspace/43.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/43.usbdev_pkt_buffer.577054076
Short name T2281
Test name
Test status
Simulation time 13519870527 ps
CPU time 32.7 seconds
Started Aug 05 05:39:32 PM PDT 24
Finished Aug 05 05:40:04 PM PDT 24
Peak memory 215908 kb
Host smart-6d7d271b-1823-4611-a1cb-76c89c9eb39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57705
4076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.577054076
Directory /workspace/43.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/43.usbdev_pkt_received.2811557499
Short name T644
Test name
Test status
Simulation time 148187822 ps
CPU time 0.87 seconds
Started Aug 05 05:39:40 PM PDT 24
Finished Aug 05 05:39:41 PM PDT 24
Peak memory 207296 kb
Host smart-529a0af3-c157-47af-87d5-b6f8ca552135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28115
57499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2811557499
Directory /workspace/43.usbdev_pkt_received/latest


Test location /workspace/coverage/default/43.usbdev_pkt_sent.3203035236
Short name T2536
Test name
Test status
Simulation time 172953079 ps
CPU time 0.95 seconds
Started Aug 05 05:39:47 PM PDT 24
Finished Aug 05 05:39:48 PM PDT 24
Peak memory 207368 kb
Host smart-7171237f-86fc-45ad-b77b-b1ea19b47091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32030
35236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3203035236
Directory /workspace/43.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.101565077
Short name T1139
Test name
Test status
Simulation time 225975270 ps
CPU time 1.01 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:42 PM PDT 24
Peak memory 207320 kb
Host smart-fdb860a7-228c-48b3-8b92-f5d5652a5ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10156
5077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.101565077
Directory /workspace/43.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2367593848
Short name T2707
Test name
Test status
Simulation time 190742012 ps
CPU time 0.95 seconds
Started Aug 05 05:39:40 PM PDT 24
Finished Aug 05 05:39:41 PM PDT 24
Peak memory 207364 kb
Host smart-9af28dee-9ff2-4433-8081-3246c2315088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
93848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2367593848
Directory /workspace/43.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1923419895
Short name T2294
Test name
Test status
Simulation time 155294118 ps
CPU time 0.86 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:39:40 PM PDT 24
Peak memory 207236 kb
Host smart-89805fa3-f5e3-4f77-85b5-6b79df83b945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19234
19895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1923419895
Directory /workspace/43.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/43.usbdev_rx_full.1685580734
Short name T1715
Test name
Test status
Simulation time 245554204 ps
CPU time 1.09 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:39:49 PM PDT 24
Peak memory 207156 kb
Host smart-c90233c9-9dbe-46ba-8390-b4ab3b1a77f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16855
80734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.1685580734
Directory /workspace/43.usbdev_rx_full/latest


Test location /workspace/coverage/default/43.usbdev_setup_stage.1792296481
Short name T1273
Test name
Test status
Simulation time 166666027 ps
CPU time 0.88 seconds
Started Aug 05 05:39:43 PM PDT 24
Finished Aug 05 05:39:44 PM PDT 24
Peak memory 207236 kb
Host smart-8fb504c9-1d88-475c-8444-121ce9b07bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17922
96481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1792296481
Directory /workspace/43.usbdev_setup_stage/latest


Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1194868859
Short name T2006
Test name
Test status
Simulation time 149466963 ps
CPU time 0.85 seconds
Started Aug 05 05:39:33 PM PDT 24
Finished Aug 05 05:39:34 PM PDT 24
Peak memory 207368 kb
Host smart-046398c5-e5d6-4b85-8de5-22f87b97d2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11948
68859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1194868859
Directory /workspace/43.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/43.usbdev_smoke.2330883384
Short name T2367
Test name
Test status
Simulation time 223956835 ps
CPU time 1.02 seconds
Started Aug 05 05:39:42 PM PDT 24
Finished Aug 05 05:39:43 PM PDT 24
Peak memory 207324 kb
Host smart-439ed8a6-4f56-4263-85b4-6db6bca92c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23308
83384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2330883384
Directory /workspace/43.usbdev_smoke/latest


Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2786699809
Short name T1855
Test name
Test status
Simulation time 2196802794 ps
CPU time 22.56 seconds
Started Aug 05 05:39:45 PM PDT 24
Finished Aug 05 05:40:08 PM PDT 24
Peak memory 215748 kb
Host smart-95a33151-bf51-479e-897e-91afbd2b3d82
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2786699809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2786699809
Directory /workspace/43.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2244169800
Short name T2925
Test name
Test status
Simulation time 184359130 ps
CPU time 0.89 seconds
Started Aug 05 05:39:35 PM PDT 24
Finished Aug 05 05:39:36 PM PDT 24
Peak memory 207428 kb
Host smart-c54eb44e-3aa2-48a2-beba-752320703511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22441
69800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2244169800
Directory /workspace/43.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/43.usbdev_stall_trans.3600592132
Short name T1958
Test name
Test status
Simulation time 225154941 ps
CPU time 0.93 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:42 PM PDT 24
Peak memory 207268 kb
Host smart-7689c83b-8a98-44ec-9056-d3803aee231f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36005
92132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3600592132
Directory /workspace/43.usbdev_stall_trans/latest


Test location /workspace/coverage/default/43.usbdev_stream_len_max.549522978
Short name T845
Test name
Test status
Simulation time 1323184113 ps
CPU time 2.79 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:44 PM PDT 24
Peak memory 207528 kb
Host smart-d46b6a96-ec08-4b8b-8d1f-1fd9f852ac1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54952
2978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.549522978
Directory /workspace/43.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/43.usbdev_streaming_out.2634864189
Short name T1759
Test name
Test status
Simulation time 1640264760 ps
CPU time 43.63 seconds
Started Aug 05 05:39:44 PM PDT 24
Finished Aug 05 05:40:28 PM PDT 24
Peak memory 215804 kb
Host smart-13618bce-aab1-4fb0-a052-7e730d907671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26348
64189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.2634864189
Directory /workspace/43.usbdev_streaming_out/latest


Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.475032208
Short name T1802
Test name
Test status
Simulation time 2930143786 ps
CPU time 25.98 seconds
Started Aug 05 05:39:40 PM PDT 24
Finished Aug 05 05:40:06 PM PDT 24
Peak memory 207676 kb
Host smart-482cce2f-8b4d-41b0-9b48-f88c9a8d4047
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475032208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_host
_handshake.475032208
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/44.usbdev_alert_test.2008918931
Short name T193
Test name
Test status
Simulation time 50242239 ps
CPU time 0.69 seconds
Started Aug 05 05:39:47 PM PDT 24
Finished Aug 05 05:39:48 PM PDT 24
Peak memory 207468 kb
Host smart-1af2efbf-b9ce-4aad-b05b-08637a154667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2008918931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.2008918931
Directory /workspace/44.usbdev_alert_test/latest


Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.1635274618
Short name T2418
Test name
Test status
Simulation time 4698500882 ps
CPU time 6.64 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:48 PM PDT 24
Peak memory 215696 kb
Host smart-7e095ecc-19ad-4f40-8250-570ba665d7c6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635274618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.1635274618
Directory /workspace/44.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2223782144
Short name T1256
Test name
Test status
Simulation time 15455225481 ps
CPU time 16.72 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:39:56 PM PDT 24
Peak memory 215808 kb
Host smart-8463357c-b48e-4488-a694-edb6a47bf363
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223782144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2223782144
Directory /workspace/44.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2465923873
Short name T2594
Test name
Test status
Simulation time 26369825780 ps
CPU time 30.62 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 215800 kb
Host smart-7991ffb6-e203-490f-a0a3-53ad7f9d2c11
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465923873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_resume.2465923873
Directory /workspace/44.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/44.usbdev_av_buffer.182637588
Short name T1374
Test name
Test status
Simulation time 158744058 ps
CPU time 0.82 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:39:47 PM PDT 24
Peak memory 207328 kb
Host smart-cf24f783-d130-48f6-9050-3d19eb87d652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18263
7588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.182637588
Directory /workspace/44.usbdev_av_buffer/latest


Test location /workspace/coverage/default/44.usbdev_bitstuff_err.4155501312
Short name T88
Test name
Test status
Simulation time 145452311 ps
CPU time 0.8 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:39:47 PM PDT 24
Peak memory 207292 kb
Host smart-58f5407c-35d2-45d8-8d10-821f304b16af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41555
01312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.4155501312
Directory /workspace/44.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.3286097092
Short name T678
Test name
Test status
Simulation time 485815618 ps
CPU time 1.69 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:43 PM PDT 24
Peak memory 207380 kb
Host smart-5406b68e-d728-44d8-bd41-e75883849b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32860
97092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.3286097092
Directory /workspace/44.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.4172303351
Short name T2241
Test name
Test status
Simulation time 1062138130 ps
CPU time 2.83 seconds
Started Aug 05 05:39:35 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 207632 kb
Host smart-17d6a259-3914-4027-a72c-d5379085f1fd
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4172303351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.4172303351
Directory /workspace/44.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/44.usbdev_device_address.621318427
Short name T1757
Test name
Test status
Simulation time 16598678320 ps
CPU time 31.83 seconds
Started Aug 05 05:39:44 PM PDT 24
Finished Aug 05 05:40:16 PM PDT 24
Peak memory 207704 kb
Host smart-16e18e0d-3b39-4458-b85b-74878fd0436b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62131
8427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.621318427
Directory /workspace/44.usbdev_device_address/latest


Test location /workspace/coverage/default/44.usbdev_device_timeout.1763210846
Short name T962
Test name
Test status
Simulation time 6418077854 ps
CPU time 40.06 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207592 kb
Host smart-164f2ffe-53d7-40b0-8086-4e41782cae48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763210846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.1763210846
Directory /workspace/44.usbdev_device_timeout/latest


Test location /workspace/coverage/default/44.usbdev_disable_endpoint.326835154
Short name T1622
Test name
Test status
Simulation time 1155470565 ps
CPU time 2.25 seconds
Started Aug 05 05:39:42 PM PDT 24
Finished Aug 05 05:39:45 PM PDT 24
Peak memory 207324 kb
Host smart-74f4aa61-32d2-4cab-b0ee-f1315ffaca1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32683
5154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.326835154
Directory /workspace/44.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/44.usbdev_disconnected.4272137302
Short name T2928
Test name
Test status
Simulation time 238755560 ps
CPU time 0.97 seconds
Started Aug 05 05:39:45 PM PDT 24
Finished Aug 05 05:39:46 PM PDT 24
Peak memory 207424 kb
Host smart-a7a340b0-40d8-427b-9971-c708b4ca49b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42721
37302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.4272137302
Directory /workspace/44.usbdev_disconnected/latest


Test location /workspace/coverage/default/44.usbdev_enable.3911779820
Short name T1198
Test name
Test status
Simulation time 43012742 ps
CPU time 0.74 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 207340 kb
Host smart-f84aa5c3-d678-4460-93b1-cc3bf18e2b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39117
79820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3911779820
Directory /workspace/44.usbdev_enable/latest


Test location /workspace/coverage/default/44.usbdev_endpoint_access.999690001
Short name T1300
Test name
Test status
Simulation time 740653387 ps
CPU time 2.09 seconds
Started Aug 05 05:39:43 PM PDT 24
Finished Aug 05 05:39:50 PM PDT 24
Peak memory 207524 kb
Host smart-6467164f-acbf-403b-9a41-0a29db18fd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99969
0001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.999690001
Directory /workspace/44.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/44.usbdev_endpoint_types.495431134
Short name T433
Test name
Test status
Simulation time 170871244 ps
CPU time 0.93 seconds
Started Aug 05 05:39:50 PM PDT 24
Finished Aug 05 05:39:51 PM PDT 24
Peak memory 207344 kb
Host smart-8edfb724-b594-4228-821d-ef3c1268b31d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=495431134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.495431134
Directory /workspace/44.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/44.usbdev_fifo_rst.1121414231
Short name T2971
Test name
Test status
Simulation time 204160730 ps
CPU time 1.46 seconds
Started Aug 05 05:39:42 PM PDT 24
Finished Aug 05 05:39:44 PM PDT 24
Peak memory 207512 kb
Host smart-d4a84943-441f-4077-b6f3-493249381484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11214
14231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1121414231
Directory /workspace/44.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/44.usbdev_in_iso.193913812
Short name T1654
Test name
Test status
Simulation time 213183355 ps
CPU time 1.1 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:39:47 PM PDT 24
Peak memory 206864 kb
Host smart-716b2ae7-9f7a-41d4-8393-a3f476011779
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=193913812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.193913812
Directory /workspace/44.usbdev_in_iso/latest


Test location /workspace/coverage/default/44.usbdev_in_stall.1090534293
Short name T1058
Test name
Test status
Simulation time 185261853 ps
CPU time 0.89 seconds
Started Aug 05 05:39:44 PM PDT 24
Finished Aug 05 05:39:45 PM PDT 24
Peak memory 207436 kb
Host smart-101f6424-1895-4697-82f2-6b3ecf2b9236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10905
34293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1090534293
Directory /workspace/44.usbdev_in_stall/latest


Test location /workspace/coverage/default/44.usbdev_in_trans.728429136
Short name T2562
Test name
Test status
Simulation time 229503654 ps
CPU time 0.96 seconds
Started Aug 05 05:39:40 PM PDT 24
Finished Aug 05 05:39:41 PM PDT 24
Peak memory 207348 kb
Host smart-7d43da29-2c0f-487b-a539-35564f0c7350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72842
9136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.728429136
Directory /workspace/44.usbdev_in_trans/latest


Test location /workspace/coverage/default/44.usbdev_invalid_sync.3729593233
Short name T2923
Test name
Test status
Simulation time 2664539186 ps
CPU time 71.01 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:40:52 PM PDT 24
Peak memory 217516 kb
Host smart-a9ee7d4b-d750-4360-83e9-c9f44899abff
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3729593233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.3729593233
Directory /workspace/44.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/44.usbdev_iso_retraction.3954707132
Short name T661
Test name
Test status
Simulation time 5457517201 ps
CPU time 37.55 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:40:25 PM PDT 24
Peak memory 207364 kb
Host smart-a62a6b92-5c2c-48b9-b367-90bf26c35de1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3954707132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3954707132
Directory /workspace/44.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/44.usbdev_link_in_err.1390270429
Short name T650
Test name
Test status
Simulation time 205967351 ps
CPU time 0.93 seconds
Started Aug 05 05:39:43 PM PDT 24
Finished Aug 05 05:39:44 PM PDT 24
Peak memory 207060 kb
Host smart-d5f14860-5941-4dcf-aa3d-1eca96a5e0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13902
70429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1390270429
Directory /workspace/44.usbdev_link_in_err/latest


Test location /workspace/coverage/default/44.usbdev_link_resume.2835057913
Short name T1077
Test name
Test status
Simulation time 7609066339 ps
CPU time 11.69 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:53 PM PDT 24
Peak memory 216060 kb
Host smart-a44fce1b-4daf-4f56-811e-e344ba0c86d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28350
57913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2835057913
Directory /workspace/44.usbdev_link_resume/latest


Test location /workspace/coverage/default/44.usbdev_link_suspend.1283336272
Short name T2376
Test name
Test status
Simulation time 4981870022 ps
CPU time 6.38 seconds
Started Aug 05 05:39:42 PM PDT 24
Finished Aug 05 05:39:48 PM PDT 24
Peak memory 215884 kb
Host smart-19124538-803e-4c02-83a1-71b4aad9edd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12833
36272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1283336272
Directory /workspace/44.usbdev_link_suspend/latest


Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.3250327590
Short name T598
Test name
Test status
Simulation time 5545136674 ps
CPU time 53.98 seconds
Started Aug 05 05:39:45 PM PDT 24
Finished Aug 05 05:40:39 PM PDT 24
Peak memory 224084 kb
Host smart-c302cb32-2d62-4220-8d47-0b59fd56b752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32503
27590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.3250327590
Directory /workspace/44.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3505253245
Short name T1865
Test name
Test status
Simulation time 2166408427 ps
CPU time 20.62 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:40:06 PM PDT 24
Peak memory 217296 kb
Host smart-6dcf41ba-ea01-4676-9177-1a3a9a8172f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3505253245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3505253245
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.4211651754
Short name T2979
Test name
Test status
Simulation time 255496574 ps
CPU time 0.97 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:39:47 PM PDT 24
Peak memory 206688 kb
Host smart-18824211-f2eb-4ae5-a5ed-9dfff30321c6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4211651754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.4211651754
Directory /workspace/44.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1286029772
Short name T2897
Test name
Test status
Simulation time 197802692 ps
CPU time 0.98 seconds
Started Aug 05 05:39:50 PM PDT 24
Finished Aug 05 05:39:51 PM PDT 24
Peak memory 207468 kb
Host smart-ca23d9da-5f2c-4ba5-8d79-4c6573eb8e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12860
29772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1286029772
Directory /workspace/44.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.82249907
Short name T2732
Test name
Test status
Simulation time 3795348078 ps
CPU time 109.49 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:41:28 PM PDT 24
Peak memory 217164 kb
Host smart-2bf27bb9-6f62-4eed-a50a-13f896124c0c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=82249907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.82249907
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.640558603
Short name T1796
Test name
Test status
Simulation time 201752171 ps
CPU time 0.9 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:42 PM PDT 24
Peak memory 207396 kb
Host smart-fd31b61f-348a-46de-8d87-32268012aaa0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=640558603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.640558603
Directory /workspace/44.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2227642863
Short name T1107
Test name
Test status
Simulation time 186691571 ps
CPU time 0.86 seconds
Started Aug 05 05:39:34 PM PDT 24
Finished Aug 05 05:39:35 PM PDT 24
Peak memory 207416 kb
Host smart-58d153e3-a02d-42f1-b434-fcc8ed43656e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22276
42863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2227642863
Directory /workspace/44.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/44.usbdev_nak_trans.441029217
Short name T153
Test name
Test status
Simulation time 262005725 ps
CPU time 0.99 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:39:47 PM PDT 24
Peak memory 207288 kb
Host smart-a686968c-4e9d-49bb-9ebb-c12c53dbb1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44102
9217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.441029217
Directory /workspace/44.usbdev_nak_trans/latest


Test location /workspace/coverage/default/44.usbdev_out_iso.2700608784
Short name T884
Test name
Test status
Simulation time 237507686 ps
CPU time 0.94 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:39:52 PM PDT 24
Peak memory 207268 kb
Host smart-bd56a626-3b7b-4d10-ab45-f1233db7fc7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27006
08784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2700608784
Directory /workspace/44.usbdev_out_iso/latest


Test location /workspace/coverage/default/44.usbdev_out_stall.3163006076
Short name T2087
Test name
Test status
Simulation time 175089534 ps
CPU time 0.87 seconds
Started Aug 05 05:39:48 PM PDT 24
Finished Aug 05 05:39:49 PM PDT 24
Peak memory 207408 kb
Host smart-d4ce9ff9-4945-4a44-bab7-4d96d1976f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31630
06076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3163006076
Directory /workspace/44.usbdev_out_stall/latest


Test location /workspace/coverage/default/44.usbdev_out_trans_nak.4228123436
Short name T217
Test name
Test status
Simulation time 193315587 ps
CPU time 0.95 seconds
Started Aug 05 05:39:45 PM PDT 24
Finished Aug 05 05:39:46 PM PDT 24
Peak memory 207348 kb
Host smart-929f302a-e2d0-4b99-9f09-394b8bfd0b90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42281
23436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.4228123436
Directory /workspace/44.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3936717927
Short name T2108
Test name
Test status
Simulation time 155279809 ps
CPU time 0.86 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:39:47 PM PDT 24
Peak memory 207368 kb
Host smart-24928427-fb0d-4912-abde-d669ee5f33bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39367
17927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3936717927
Directory /workspace/44.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1523358943
Short name T3112
Test name
Test status
Simulation time 306348213 ps
CPU time 1.09 seconds
Started Aug 05 05:39:37 PM PDT 24
Finished Aug 05 05:39:38 PM PDT 24
Peak memory 207324 kb
Host smart-dc862e96-9d98-4508-be44-ba2b8638ad93
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1523358943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1523358943
Directory /workspace/44.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1606520194
Short name T2996
Test name
Test status
Simulation time 152306662 ps
CPU time 0.81 seconds
Started Aug 05 05:39:51 PM PDT 24
Finished Aug 05 05:39:52 PM PDT 24
Peak memory 207344 kb
Host smart-2badf60c-8e63-4f2a-a812-ddc6f1bca4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16065
20194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1606520194
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.543086413
Short name T2556
Test name
Test status
Simulation time 41723580 ps
CPU time 0.69 seconds
Started Aug 05 05:39:53 PM PDT 24
Finished Aug 05 05:39:53 PM PDT 24
Peak memory 207316 kb
Host smart-b4442670-4e68-468d-8f97-a78d002bef39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54308
6413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.543086413
Directory /workspace/44.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3857249385
Short name T250
Test name
Test status
Simulation time 18043563408 ps
CPU time 43.33 seconds
Started Aug 05 05:39:43 PM PDT 24
Finished Aug 05 05:40:27 PM PDT 24
Peak memory 215792 kb
Host smart-996ad654-80f6-45c0-8ed6-b71c57d6d16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38572
49385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3857249385
Directory /workspace/44.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/44.usbdev_pkt_received.3086004268
Short name T738
Test name
Test status
Simulation time 192251490 ps
CPU time 0.94 seconds
Started Aug 05 05:39:45 PM PDT 24
Finished Aug 05 05:39:51 PM PDT 24
Peak memory 207228 kb
Host smart-fd4b9bbf-9267-4d89-b521-dd412933bbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30860
04268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3086004268
Directory /workspace/44.usbdev_pkt_received/latest


Test location /workspace/coverage/default/44.usbdev_pkt_sent.4205649534
Short name T2024
Test name
Test status
Simulation time 174301123 ps
CPU time 0.87 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:43 PM PDT 24
Peak memory 207324 kb
Host smart-b3a77b46-8f79-4441-acdf-f88b5f4f84b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42056
49534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.4205649534
Directory /workspace/44.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2720259062
Short name T2187
Test name
Test status
Simulation time 231431526 ps
CPU time 1.01 seconds
Started Aug 05 05:39:51 PM PDT 24
Finished Aug 05 05:39:52 PM PDT 24
Peak memory 207356 kb
Host smart-5c6aad53-fe92-423c-b0c8-bac966242dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
59062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2720259062
Directory /workspace/44.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1202398231
Short name T1540
Test name
Test status
Simulation time 164280847 ps
CPU time 0.93 seconds
Started Aug 05 05:39:47 PM PDT 24
Finished Aug 05 05:39:48 PM PDT 24
Peak memory 207348 kb
Host smart-d57263c6-3135-44ad-b2ae-5dbc58ef6d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12023
98231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1202398231
Directory /workspace/44.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3919336706
Short name T988
Test name
Test status
Simulation time 136393440 ps
CPU time 0.93 seconds
Started Aug 05 05:39:43 PM PDT 24
Finished Aug 05 05:39:44 PM PDT 24
Peak memory 207336 kb
Host smart-ba3593cf-b74a-49c7-b476-d7c5519a984b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39193
36706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3919336706
Directory /workspace/44.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/44.usbdev_rx_full.190620961
Short name T870
Test name
Test status
Simulation time 388729971 ps
CPU time 1.2 seconds
Started Aug 05 05:39:53 PM PDT 24
Finished Aug 05 05:39:55 PM PDT 24
Peak memory 207352 kb
Host smart-14d4700a-0707-48af-917c-059f253530c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19062
0961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.190620961
Directory /workspace/44.usbdev_rx_full/latest


Test location /workspace/coverage/default/44.usbdev_setup_stage.602079869
Short name T2982
Test name
Test status
Simulation time 152192025 ps
CPU time 0.84 seconds
Started Aug 05 05:39:59 PM PDT 24
Finished Aug 05 05:40:00 PM PDT 24
Peak memory 207304 kb
Host smart-8d79bef5-4e43-400f-938a-9e1f30ed2d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60207
9869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.602079869
Directory /workspace/44.usbdev_setup_stage/latest


Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1196030914
Short name T2736
Test name
Test status
Simulation time 151390158 ps
CPU time 0.88 seconds
Started Aug 05 05:39:52 PM PDT 24
Finished Aug 05 05:39:53 PM PDT 24
Peak memory 207352 kb
Host smart-e0d017d4-161b-4cfe-af1e-7ad4d300a9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11960
30914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1196030914
Directory /workspace/44.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/44.usbdev_smoke.1711306266
Short name T2272
Test name
Test status
Simulation time 209677994 ps
CPU time 1.01 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:39:40 PM PDT 24
Peak memory 207240 kb
Host smart-36c70adf-cb6a-4287-a1ac-3cf0d0e13493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17113
06266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1711306266
Directory /workspace/44.usbdev_smoke/latest


Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.649802632
Short name T1534
Test name
Test status
Simulation time 2921383200 ps
CPU time 23.67 seconds
Started Aug 05 05:39:52 PM PDT 24
Finished Aug 05 05:40:15 PM PDT 24
Peak memory 224048 kb
Host smart-3c0c2112-608a-420b-b509-e0902b2f03df
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=649802632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.649802632
Directory /workspace/44.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.990184196
Short name T1769
Test name
Test status
Simulation time 187661151 ps
CPU time 0.89 seconds
Started Aug 05 05:39:42 PM PDT 24
Finished Aug 05 05:39:43 PM PDT 24
Peak memory 207368 kb
Host smart-71d3414f-159c-418f-bc58-c3fd86b23530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99018
4196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.990184196
Directory /workspace/44.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/44.usbdev_stall_trans.2848093171
Short name T1790
Test name
Test status
Simulation time 149699008 ps
CPU time 0.89 seconds
Started Aug 05 05:39:39 PM PDT 24
Finished Aug 05 05:39:40 PM PDT 24
Peak memory 207300 kb
Host smart-aa4c5368-9331-4caf-8fe1-ded47ed1c439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28480
93171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2848093171
Directory /workspace/44.usbdev_stall_trans/latest


Test location /workspace/coverage/default/44.usbdev_stream_len_max.3822938748
Short name T555
Test name
Test status
Simulation time 1371142733 ps
CPU time 2.86 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:39:49 PM PDT 24
Peak memory 207628 kb
Host smart-70533005-63ed-46b1-88f4-d202ef6dd166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38229
38748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.3822938748
Directory /workspace/44.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/44.usbdev_streaming_out.1191123778
Short name T1768
Test name
Test status
Simulation time 3057301328 ps
CPU time 31.37 seconds
Started Aug 05 05:39:48 PM PDT 24
Finished Aug 05 05:40:20 PM PDT 24
Peak memory 215936 kb
Host smart-721186b4-5c77-4693-b4f4-ac82f923d865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11911
23778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1191123778
Directory /workspace/44.usbdev_streaming_out/latest


Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.955781880
Short name T1711
Test name
Test status
Simulation time 610543014 ps
CPU time 11.16 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:39:49 PM PDT 24
Peak memory 207536 kb
Host smart-c83b38ae-c81d-4ccc-b414-09f4dafd3389
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955781880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_host
_handshake.955781880
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/45.usbdev_alert_test.3185376754
Short name T2071
Test name
Test status
Simulation time 85043793 ps
CPU time 0.69 seconds
Started Aug 05 05:39:48 PM PDT 24
Finished Aug 05 05:39:49 PM PDT 24
Peak memory 207420 kb
Host smart-b88dde59-8b1d-428d-ba56-d803071073e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3185376754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3185376754
Directory /workspace/45.usbdev_alert_test/latest


Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.68869463
Short name T2015
Test name
Test status
Simulation time 4787280524 ps
CPU time 7.02 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:39:48 PM PDT 24
Peak memory 215816 kb
Host smart-45a03532-a1a5-42e5-9a86-677bf3619ca2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68869463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon
_wake_disconnect.68869463
Directory /workspace/45.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1582698569
Short name T2077
Test name
Test status
Simulation time 20315353383 ps
CPU time 28.74 seconds
Started Aug 05 05:39:50 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207604 kb
Host smart-5897ad46-66ea-4ebb-8c93-f451cdfc260d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582698569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1582698569
Directory /workspace/45.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.2217529358
Short name T2614
Test name
Test status
Simulation time 29781782628 ps
CPU time 38.26 seconds
Started Aug 05 05:39:38 PM PDT 24
Finished Aug 05 05:40:16 PM PDT 24
Peak memory 207604 kb
Host smart-afa07ab7-5187-4510-8a27-7ea2c7a8bdb2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217529358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.2217529358
Directory /workspace/45.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/45.usbdev_av_buffer.3996168552
Short name T2675
Test name
Test status
Simulation time 177575036 ps
CPU time 0.88 seconds
Started Aug 05 05:39:45 PM PDT 24
Finished Aug 05 05:39:46 PM PDT 24
Peak memory 207224 kb
Host smart-b0b9ce9b-9f49-4a18-9abc-bfdf32884de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39961
68552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3996168552
Directory /workspace/45.usbdev_av_buffer/latest


Test location /workspace/coverage/default/45.usbdev_bitstuff_err.1588312706
Short name T2095
Test name
Test status
Simulation time 144404342 ps
CPU time 0.81 seconds
Started Aug 05 05:39:55 PM PDT 24
Finished Aug 05 05:39:55 PM PDT 24
Peak memory 207320 kb
Host smart-bf25c737-f885-42d8-a687-7610c56f3a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15883
12706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.1588312706
Directory /workspace/45.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.557493539
Short name T1218
Test name
Test status
Simulation time 380382170 ps
CPU time 1.34 seconds
Started Aug 05 05:39:48 PM PDT 24
Finished Aug 05 05:39:50 PM PDT 24
Peak memory 207372 kb
Host smart-206d8b1a-441e-483c-819d-db18a21569d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55749
3539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.557493539
Directory /workspace/45.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.757645399
Short name T983
Test name
Test status
Simulation time 643282820 ps
CPU time 1.88 seconds
Started Aug 05 05:39:52 PM PDT 24
Finished Aug 05 05:39:54 PM PDT 24
Peak memory 207352 kb
Host smart-150ac549-0d0e-48a7-a1a0-2ec94e129ff7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=757645399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.757645399
Directory /workspace/45.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/45.usbdev_device_address.1258409979
Short name T1398
Test name
Test status
Simulation time 37693695658 ps
CPU time 62.25 seconds
Started Aug 05 05:39:36 PM PDT 24
Finished Aug 05 05:40:39 PM PDT 24
Peak memory 207664 kb
Host smart-6e620879-9324-4f53-95cb-7930e32434ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12584
09979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.1258409979
Directory /workspace/45.usbdev_device_address/latest


Test location /workspace/coverage/default/45.usbdev_device_timeout.2087711221
Short name T1418
Test name
Test status
Simulation time 1575120754 ps
CPU time 13.37 seconds
Started Aug 05 05:39:43 PM PDT 24
Finished Aug 05 05:39:56 PM PDT 24
Peak memory 207496 kb
Host smart-15c3b932-7729-4379-ace7-6a6e89356415
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087711221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.2087711221
Directory /workspace/45.usbdev_device_timeout/latest


Test location /workspace/coverage/default/45.usbdev_disable_endpoint.3551764638
Short name T2033
Test name
Test status
Simulation time 736484782 ps
CPU time 1.86 seconds
Started Aug 05 05:39:50 PM PDT 24
Finished Aug 05 05:39:52 PM PDT 24
Peak memory 207336 kb
Host smart-0356ae48-6d1e-4974-a489-56f152994ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35517
64638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.3551764638
Directory /workspace/45.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/45.usbdev_disconnected.3055384830
Short name T1785
Test name
Test status
Simulation time 143181139 ps
CPU time 0.83 seconds
Started Aug 05 05:39:50 PM PDT 24
Finished Aug 05 05:39:51 PM PDT 24
Peak memory 207320 kb
Host smart-187f6c79-884a-415b-b936-2078fbae1547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30553
84830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3055384830
Directory /workspace/45.usbdev_disconnected/latest


Test location /workspace/coverage/default/45.usbdev_enable.3322369753
Short name T2775
Test name
Test status
Simulation time 46386643 ps
CPU time 0.75 seconds
Started Aug 05 05:40:03 PM PDT 24
Finished Aug 05 05:40:04 PM PDT 24
Peak memory 207316 kb
Host smart-2d690d03-6319-49ab-8351-b656b355370a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33223
69753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3322369753
Directory /workspace/45.usbdev_enable/latest


Test location /workspace/coverage/default/45.usbdev_endpoint_access.2344053853
Short name T1323
Test name
Test status
Simulation time 814021120 ps
CPU time 2.22 seconds
Started Aug 05 05:39:47 PM PDT 24
Finished Aug 05 05:39:50 PM PDT 24
Peak memory 207504 kb
Host smart-35d2c8c9-df5b-416e-bfd3-33170e74ad5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23440
53853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2344053853
Directory /workspace/45.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/45.usbdev_endpoint_types.1707500069
Short name T331
Test name
Test status
Simulation time 383254695 ps
CPU time 1.27 seconds
Started Aug 05 05:39:50 PM PDT 24
Finished Aug 05 05:39:51 PM PDT 24
Peak memory 207348 kb
Host smart-39e7c854-ba14-49e5-93d7-ec1e3227adcb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1707500069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.1707500069
Directory /workspace/45.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/45.usbdev_fifo_rst.1253577300
Short name T1110
Test name
Test status
Simulation time 200466339 ps
CPU time 1.52 seconds
Started Aug 05 05:39:44 PM PDT 24
Finished Aug 05 05:39:46 PM PDT 24
Peak memory 207608 kb
Host smart-d2c82999-ea45-4789-a184-950259e8a030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12535
77300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1253577300
Directory /workspace/45.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/45.usbdev_in_iso.2310720657
Short name T517
Test name
Test status
Simulation time 188690200 ps
CPU time 1.06 seconds
Started Aug 05 05:39:42 PM PDT 24
Finished Aug 05 05:39:43 PM PDT 24
Peak memory 207452 kb
Host smart-421ab67f-c037-4d10-bb7b-b4cae3acc064
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2310720657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2310720657
Directory /workspace/45.usbdev_in_iso/latest


Test location /workspace/coverage/default/45.usbdev_in_stall.2650407734
Short name T1127
Test name
Test status
Simulation time 157443466 ps
CPU time 0.83 seconds
Started Aug 05 05:39:52 PM PDT 24
Finished Aug 05 05:39:53 PM PDT 24
Peak memory 207320 kb
Host smart-08b10178-0be7-4415-99f2-513c73508d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26504
07734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2650407734
Directory /workspace/45.usbdev_in_stall/latest


Test location /workspace/coverage/default/45.usbdev_in_trans.2378016550
Short name T1660
Test name
Test status
Simulation time 178247457 ps
CPU time 0.93 seconds
Started Aug 05 05:39:44 PM PDT 24
Finished Aug 05 05:39:45 PM PDT 24
Peak memory 207368 kb
Host smart-0c995501-8033-40c6-aa0c-fbaab6e7dceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23780
16550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2378016550
Directory /workspace/45.usbdev_in_trans/latest


Test location /workspace/coverage/default/45.usbdev_invalid_sync.1310258611
Short name T2780
Test name
Test status
Simulation time 3562707222 ps
CPU time 101.76 seconds
Started Aug 05 05:39:40 PM PDT 24
Finished Aug 05 05:41:22 PM PDT 24
Peak memory 217664 kb
Host smart-e8fe0782-6f6e-4afd-9307-28ef01b9a52d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1310258611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.1310258611
Directory /workspace/45.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/45.usbdev_iso_retraction.1076989981
Short name T2075
Test name
Test status
Simulation time 5203390725 ps
CPU time 65.07 seconds
Started Aug 05 05:39:53 PM PDT 24
Finished Aug 05 05:40:58 PM PDT 24
Peak memory 207620 kb
Host smart-ff23ece1-0f92-47e1-a482-3c2078505fa0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1076989981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.1076989981
Directory /workspace/45.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/45.usbdev_link_in_err.671026706
Short name T2437
Test name
Test status
Simulation time 207207138 ps
CPU time 0.91 seconds
Started Aug 05 05:39:45 PM PDT 24
Finished Aug 05 05:39:46 PM PDT 24
Peak memory 207224 kb
Host smart-3ca25fe4-7ee3-419d-81c0-5e3608709142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67102
6706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.671026706
Directory /workspace/45.usbdev_link_in_err/latest


Test location /workspace/coverage/default/45.usbdev_link_resume.3797732686
Short name T908
Test name
Test status
Simulation time 27640759412 ps
CPU time 46.97 seconds
Started Aug 05 05:39:41 PM PDT 24
Finished Aug 05 05:40:32 PM PDT 24
Peak memory 215916 kb
Host smart-cd92c66d-ffe6-483b-9f8a-6e1071ac0992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37977
32686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.3797732686
Directory /workspace/45.usbdev_link_resume/latest


Test location /workspace/coverage/default/45.usbdev_link_suspend.1472685410
Short name T2469
Test name
Test status
Simulation time 6167443284 ps
CPU time 8.49 seconds
Started Aug 05 05:39:42 PM PDT 24
Finished Aug 05 05:39:51 PM PDT 24
Peak memory 215908 kb
Host smart-e5dac34a-7ae3-46e9-8365-be1db121b485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14726
85410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.1472685410
Directory /workspace/45.usbdev_link_suspend/latest


Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1008700911
Short name T1201
Test name
Test status
Simulation time 4834720589 ps
CPU time 35.91 seconds
Started Aug 05 05:39:51 PM PDT 24
Finished Aug 05 05:40:27 PM PDT 24
Peak memory 223960 kb
Host smart-9d09d38a-d057-4e26-b8ed-3c9ecce8a212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
00911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1008700911
Directory /workspace/45.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.152328184
Short name T2907
Test name
Test status
Simulation time 2831151392 ps
CPU time 27.97 seconds
Started Aug 05 05:39:46 PM PDT 24
Finished Aug 05 05:40:14 PM PDT 24
Peak memory 217392 kb
Host smart-7c51ce6e-a443-4760-ad28-d64dcddf752e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=152328184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.152328184
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.2685030577
Short name T703
Test name
Test status
Simulation time 235055726 ps
CPU time 1.02 seconds
Started Aug 05 05:39:42 PM PDT 24
Finished Aug 05 05:39:43 PM PDT 24
Peak memory 207272 kb
Host smart-1cd37ee2-9239-45ea-88e1-c81b4e85eaab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2685030577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.2685030577
Directory /workspace/45.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.395391966
Short name T689
Test name
Test status
Simulation time 225791333 ps
CPU time 1.03 seconds
Started Aug 05 05:39:51 PM PDT 24
Finished Aug 05 05:39:52 PM PDT 24
Peak memory 207376 kb
Host smart-e23f1d9d-0093-4215-ad76-2163496a35a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39539
1966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.395391966
Directory /workspace/45.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.3182428727
Short name T2610
Test name
Test status
Simulation time 3466437757 ps
CPU time 99.1 seconds
Started Aug 05 05:39:49 PM PDT 24
Finished Aug 05 05:41:29 PM PDT 24
Peak memory 217164 kb
Host smart-6759a9a0-6edf-48dc-9410-91943224b847
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3182428727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.3182428727
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3016800950
Short name T851
Test name
Test status
Simulation time 160300407 ps
CPU time 0.84 seconds
Started Aug 05 05:39:43 PM PDT 24
Finished Aug 05 05:39:44 PM PDT 24
Peak memory 207120 kb
Host smart-b318cd0b-7783-4133-868c-81d8e397cadc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3016800950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3016800950
Directory /workspace/45.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2086179105
Short name T714
Test name
Test status
Simulation time 147976836 ps
CPU time 0.81 seconds
Started Aug 05 05:39:48 PM PDT 24
Finished Aug 05 05:39:49 PM PDT 24
Peak memory 207264 kb
Host smart-ab97a035-5763-4748-9bfe-858457bf2839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20861
79105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2086179105
Directory /workspace/45.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/45.usbdev_nak_trans.1311410526
Short name T2642
Test name
Test status
Simulation time 167806727 ps
CPU time 0.89 seconds
Started Aug 05 05:40:03 PM PDT 24
Finished Aug 05 05:40:04 PM PDT 24
Peak memory 207240 kb
Host smart-58a3d17b-1ca7-4693-a3e8-cce005a2a337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13114
10526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1311410526
Directory /workspace/45.usbdev_nak_trans/latest


Test location /workspace/coverage/default/45.usbdev_out_iso.360047611
Short name T2551
Test name
Test status
Simulation time 192671261 ps
CPU time 0.96 seconds
Started Aug 05 05:39:53 PM PDT 24
Finished Aug 05 05:39:54 PM PDT 24
Peak memory 207404 kb
Host smart-73ae2730-41b4-43a4-bf70-23c5ca333b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36004
7611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.360047611
Directory /workspace/45.usbdev_out_iso/latest


Test location /workspace/coverage/default/45.usbdev_out_stall.791236340
Short name T1208
Test name
Test status
Simulation time 180716294 ps
CPU time 0.88 seconds
Started Aug 05 05:39:56 PM PDT 24
Finished Aug 05 05:39:57 PM PDT 24
Peak memory 207344 kb
Host smart-21d9c723-6ffd-47fd-bf6c-0a0a10b3b671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79123
6340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.791236340
Directory /workspace/45.usbdev_out_stall/latest


Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3005978044
Short name T2804
Test name
Test status
Simulation time 162090423 ps
CPU time 0.84 seconds
Started Aug 05 05:40:06 PM PDT 24
Finished Aug 05 05:40:07 PM PDT 24
Peak memory 207336 kb
Host smart-2c1ebc41-e17f-4f58-ba75-d94dd20ea711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30059
78044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3005978044
Directory /workspace/45.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2904811607
Short name T1795
Test name
Test status
Simulation time 156309330 ps
CPU time 0.86 seconds
Started Aug 05 05:39:50 PM PDT 24
Finished Aug 05 05:39:56 PM PDT 24
Peak memory 207356 kb
Host smart-6f7e0e57-3526-488f-b0a4-390ec2e27bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29048
11607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2904811607
Directory /workspace/45.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.2786896269
Short name T2648
Test name
Test status
Simulation time 211997134 ps
CPU time 0.98 seconds
Started Aug 05 05:39:53 PM PDT 24
Finished Aug 05 05:39:54 PM PDT 24
Peak memory 207376 kb
Host smart-be5d8c58-2a42-4260-af20-e2dc1d46261f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2786896269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.2786896269
Directory /workspace/45.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3671329162
Short name T822
Test name
Test status
Simulation time 151552922 ps
CPU time 0.84 seconds
Started Aug 05 05:39:51 PM PDT 24
Finished Aug 05 05:39:52 PM PDT 24
Peak memory 207368 kb
Host smart-e2e1897c-68a6-4e2d-9eca-71d87ea92f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36713
29162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3671329162
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1790139449
Short name T2731
Test name
Test status
Simulation time 43976596 ps
CPU time 0.69 seconds
Started Aug 05 05:39:49 PM PDT 24
Finished Aug 05 05:39:50 PM PDT 24
Peak memory 207340 kb
Host smart-93d64cf6-3162-4118-ba98-7803416ac5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17901
39449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1790139449
Directory /workspace/45.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1342357321
Short name T2942
Test name
Test status
Simulation time 19386178724 ps
CPU time 49.78 seconds
Started Aug 05 05:39:52 PM PDT 24
Finished Aug 05 05:40:41 PM PDT 24
Peak memory 215844 kb
Host smart-db479b83-25bd-4d14-ab15-848ac2929c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13423
57321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1342357321
Directory /workspace/45.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/45.usbdev_pkt_received.1245837937
Short name T724
Test name
Test status
Simulation time 191002451 ps
CPU time 0.93 seconds
Started Aug 05 05:39:51 PM PDT 24
Finished Aug 05 05:39:52 PM PDT 24
Peak memory 207396 kb
Host smart-7dcf874e-0580-4eb5-894f-6f21ce75f38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12458
37937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1245837937
Directory /workspace/45.usbdev_pkt_received/latest


Test location /workspace/coverage/default/45.usbdev_pkt_sent.3223928144
Short name T736
Test name
Test status
Simulation time 164525323 ps
CPU time 0.89 seconds
Started Aug 05 05:39:47 PM PDT 24
Finished Aug 05 05:39:48 PM PDT 24
Peak memory 207380 kb
Host smart-8ccd415f-2dd4-4fbc-9518-48f742728cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32239
28144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3223928144
Directory /workspace/45.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.2463982094
Short name T954
Test name
Test status
Simulation time 246126138 ps
CPU time 1.03 seconds
Started Aug 05 05:40:09 PM PDT 24
Finished Aug 05 05:40:11 PM PDT 24
Peak memory 207296 kb
Host smart-b881db2a-0966-4a8e-b36c-fc351336d2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24639
82094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.2463982094
Directory /workspace/45.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3486781431
Short name T608
Test name
Test status
Simulation time 182049677 ps
CPU time 0.89 seconds
Started Aug 05 05:39:58 PM PDT 24
Finished Aug 05 05:39:59 PM PDT 24
Peak memory 207344 kb
Host smart-8bb0ec2f-d860-4347-8a6b-b60bb1ab1645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34867
81431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3486781431
Directory /workspace/45.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/45.usbdev_rx_crc_err.1710562336
Short name T1157
Test name
Test status
Simulation time 173763275 ps
CPU time 0.86 seconds
Started Aug 05 05:39:47 PM PDT 24
Finished Aug 05 05:39:48 PM PDT 24
Peak memory 207304 kb
Host smart-378bb911-7671-452c-bd31-8a14970c9bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17105
62336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.1710562336
Directory /workspace/45.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/45.usbdev_rx_full.1050788189
Short name T1496
Test name
Test status
Simulation time 242007226 ps
CPU time 1.1 seconds
Started Aug 05 05:39:48 PM PDT 24
Finished Aug 05 05:39:49 PM PDT 24
Peak memory 207348 kb
Host smart-2912038e-52f8-47c8-b282-7151e0fbcfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10507
88189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.1050788189
Directory /workspace/45.usbdev_rx_full/latest


Test location /workspace/coverage/default/45.usbdev_setup_stage.1282966297
Short name T1854
Test name
Test status
Simulation time 151239710 ps
CPU time 0.88 seconds
Started Aug 05 05:40:01 PM PDT 24
Finished Aug 05 05:40:02 PM PDT 24
Peak memory 207216 kb
Host smart-d6402b7b-f6a7-4980-b6ec-61bb299662ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12829
66297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1282966297
Directory /workspace/45.usbdev_setup_stage/latest


Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.9023931
Short name T728
Test name
Test status
Simulation time 154378428 ps
CPU time 0.83 seconds
Started Aug 05 05:39:50 PM PDT 24
Finished Aug 05 05:39:51 PM PDT 24
Peak memory 207348 kb
Host smart-a06c68a0-36a8-4db6-bf2f-e57c050a5b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90239
31 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.9023931
Directory /workspace/45.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/45.usbdev_smoke.3728087819
Short name T948
Test name
Test status
Simulation time 216741314 ps
CPU time 1.03 seconds
Started Aug 05 05:39:49 PM PDT 24
Finished Aug 05 05:39:50 PM PDT 24
Peak memory 207264 kb
Host smart-5978324b-9224-4c2b-8320-da37f80ca836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37280
87819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3728087819
Directory /workspace/45.usbdev_smoke/latest


Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.2459038456
Short name T1499
Test name
Test status
Simulation time 2190200127 ps
CPU time 62.12 seconds
Started Aug 05 05:40:14 PM PDT 24
Finished Aug 05 05:41:16 PM PDT 24
Peak memory 215892 kb
Host smart-fa48b6cb-91ac-4ea4-a98e-e865f5dbebc1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2459038456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.2459038456
Directory /workspace/45.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.4177842388
Short name T2656
Test name
Test status
Simulation time 147967971 ps
CPU time 0.81 seconds
Started Aug 05 05:39:58 PM PDT 24
Finished Aug 05 05:39:59 PM PDT 24
Peak memory 207352 kb
Host smart-d83b0ab2-35a4-4514-ab4d-7c17938019f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41778
42388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.4177842388
Directory /workspace/45.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/45.usbdev_stall_trans.4607419
Short name T1304
Test name
Test status
Simulation time 155320545 ps
CPU time 0.85 seconds
Started Aug 05 05:39:54 PM PDT 24
Finished Aug 05 05:39:55 PM PDT 24
Peak memory 207364 kb
Host smart-373b89ae-4835-4bdf-aefb-785c2f62c821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46074
19 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.4607419
Directory /workspace/45.usbdev_stall_trans/latest


Test location /workspace/coverage/default/45.usbdev_stream_len_max.3480875029
Short name T2726
Test name
Test status
Simulation time 553983945 ps
CPU time 1.6 seconds
Started Aug 05 05:39:47 PM PDT 24
Finished Aug 05 05:39:49 PM PDT 24
Peak memory 207288 kb
Host smart-c6c73387-04bf-4776-817c-5536f524c03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34808
75029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.3480875029
Directory /workspace/45.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/45.usbdev_streaming_out.2134485168
Short name T2586
Test name
Test status
Simulation time 2586816483 ps
CPU time 26.84 seconds
Started Aug 05 05:39:53 PM PDT 24
Finished Aug 05 05:40:20 PM PDT 24
Peak memory 217524 kb
Host smart-7419bc2e-23ac-469c-b74f-5c4ea9687529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21344
85168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.2134485168
Directory /workspace/45.usbdev_streaming_out/latest


Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.317494272
Short name T2782
Test name
Test status
Simulation time 5681184337 ps
CPU time 51 seconds
Started Aug 05 05:39:42 PM PDT 24
Finished Aug 05 05:40:43 PM PDT 24
Peak memory 207688 kb
Host smart-a9c40639-ff60-4017-93a2-8aef729db0d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317494272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_host
_handshake.317494272
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/46.usbdev_alert_test.1663499659
Short name T1779
Test name
Test status
Simulation time 69220802 ps
CPU time 0.7 seconds
Started Aug 05 05:40:09 PM PDT 24
Finished Aug 05 05:40:10 PM PDT 24
Peak memory 207428 kb
Host smart-065ff5f2-58b0-45a8-b229-d2d76722d694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1663499659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1663499659
Directory /workspace/46.usbdev_alert_test/latest


Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.4079104077
Short name T3083
Test name
Test status
Simulation time 11106009216 ps
CPU time 14.61 seconds
Started Aug 05 05:39:49 PM PDT 24
Finished Aug 05 05:40:03 PM PDT 24
Peak memory 207536 kb
Host smart-98d75666-5661-420e-a542-5cb7bf130ff7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079104077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.4079104077
Directory /workspace/46.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2209603913
Short name T717
Test name
Test status
Simulation time 18679006098 ps
CPU time 24.32 seconds
Started Aug 05 05:39:49 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207612 kb
Host smart-5e05473f-30ef-409f-855a-3dee4ea493d3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209603913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2209603913
Directory /workspace/46.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3396458121
Short name T1174
Test name
Test status
Simulation time 30228531094 ps
CPU time 33.09 seconds
Started Aug 05 05:40:11 PM PDT 24
Finished Aug 05 05:40:44 PM PDT 24
Peak memory 207560 kb
Host smart-25c58b68-d98a-4f3b-8805-b88d78ef944e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396458121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.3396458121
Directory /workspace/46.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/46.usbdev_av_buffer.79119730
Short name T1760
Test name
Test status
Simulation time 153387161 ps
CPU time 0.87 seconds
Started Aug 05 05:39:56 PM PDT 24
Finished Aug 05 05:39:57 PM PDT 24
Peak memory 207340 kb
Host smart-7f8446c2-0e75-44c5-82a3-9b0323a2db3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79119
730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.79119730
Directory /workspace/46.usbdev_av_buffer/latest


Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3921571385
Short name T1658
Test name
Test status
Simulation time 149519404 ps
CPU time 0.87 seconds
Started Aug 05 05:39:48 PM PDT 24
Finished Aug 05 05:39:49 PM PDT 24
Peak memory 207208 kb
Host smart-46238ae7-1546-4303-9e32-f2868b042db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215
71385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3921571385
Directory /workspace/46.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.262413923
Short name T2717
Test name
Test status
Simulation time 464886562 ps
CPU time 1.62 seconds
Started Aug 05 05:39:53 PM PDT 24
Finished Aug 05 05:39:55 PM PDT 24
Peak memory 207332 kb
Host smart-df29b17a-6959-454e-bfcb-2d18f2d844cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26241
3923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.262413923
Directory /workspace/46.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2405674311
Short name T2988
Test name
Test status
Simulation time 660892080 ps
CPU time 1.9 seconds
Started Aug 05 05:39:58 PM PDT 24
Finished Aug 05 05:40:00 PM PDT 24
Peak memory 207348 kb
Host smart-1230d41a-7b9a-41ee-9a9d-63840e57ed7d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2405674311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2405674311
Directory /workspace/46.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/46.usbdev_device_timeout.121201111
Short name T1460
Test name
Test status
Simulation time 772644134 ps
CPU time 5.13 seconds
Started Aug 05 05:40:04 PM PDT 24
Finished Aug 05 05:40:09 PM PDT 24
Peak memory 207568 kb
Host smart-e3f01452-774b-4049-b39c-5f0683ffe47e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121201111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.121201111
Directory /workspace/46.usbdev_device_timeout/latest


Test location /workspace/coverage/default/46.usbdev_disable_endpoint.4182717940
Short name T1961
Test name
Test status
Simulation time 1264561154 ps
CPU time 3.09 seconds
Started Aug 05 05:40:04 PM PDT 24
Finished Aug 05 05:40:07 PM PDT 24
Peak memory 207436 kb
Host smart-bde11ea7-0f17-4881-b5d6-8f69a10fe5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41827
17940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.4182717940
Directory /workspace/46.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/46.usbdev_disconnected.4097291127
Short name T1167
Test name
Test status
Simulation time 145465395 ps
CPU time 0.82 seconds
Started Aug 05 05:39:47 PM PDT 24
Finished Aug 05 05:39:48 PM PDT 24
Peak memory 207316 kb
Host smart-dbbeff28-e7f9-4aa3-8817-38321539a0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40972
91127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.4097291127
Directory /workspace/46.usbdev_disconnected/latest


Test location /workspace/coverage/default/46.usbdev_enable.3878535774
Short name T957
Test name
Test status
Simulation time 54159078 ps
CPU time 0.73 seconds
Started Aug 05 05:40:03 PM PDT 24
Finished Aug 05 05:40:04 PM PDT 24
Peak memory 207328 kb
Host smart-68d5918a-c3e2-4cd5-b5ab-4a7192f30294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38785
35774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3878535774
Directory /workspace/46.usbdev_enable/latest


Test location /workspace/coverage/default/46.usbdev_endpoint_access.3116577713
Short name T1071
Test name
Test status
Simulation time 826795696 ps
CPU time 2.11 seconds
Started Aug 05 05:39:53 PM PDT 24
Finished Aug 05 05:39:55 PM PDT 24
Peak memory 207564 kb
Host smart-651c6379-0123-4527-b1b7-eeabbfb05ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
77713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3116577713
Directory /workspace/46.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/46.usbdev_endpoint_types.3046605875
Short name T443
Test name
Test status
Simulation time 885962767 ps
CPU time 1.88 seconds
Started Aug 05 05:39:50 PM PDT 24
Finished Aug 05 05:39:52 PM PDT 24
Peak memory 207324 kb
Host smart-3c42fcd1-4e06-4549-ab9b-e9896fd5916f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3046605875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.3046605875
Directory /workspace/46.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/46.usbdev_fifo_rst.1535621732
Short name T2508
Test name
Test status
Simulation time 319894294 ps
CPU time 2.26 seconds
Started Aug 05 05:40:10 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207564 kb
Host smart-45150d58-d626-475f-bc96-007fa5de7a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15356
21732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1535621732
Directory /workspace/46.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/46.usbdev_in_iso.3434160243
Short name T2911
Test name
Test status
Simulation time 215139259 ps
CPU time 1.03 seconds
Started Aug 05 05:40:03 PM PDT 24
Finished Aug 05 05:40:04 PM PDT 24
Peak memory 215776 kb
Host smart-376be082-fb5a-4368-936b-1af8b9857b29
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3434160243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3434160243
Directory /workspace/46.usbdev_in_iso/latest


Test location /workspace/coverage/default/46.usbdev_in_stall.1307021280
Short name T605
Test name
Test status
Simulation time 137556718 ps
CPU time 0.86 seconds
Started Aug 05 05:40:04 PM PDT 24
Finished Aug 05 05:40:05 PM PDT 24
Peak memory 207272 kb
Host smart-6d060929-e696-4a4c-b81c-4975ef7433da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13070
21280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1307021280
Directory /workspace/46.usbdev_in_stall/latest


Test location /workspace/coverage/default/46.usbdev_in_trans.3331838956
Short name T1044
Test name
Test status
Simulation time 239362334 ps
CPU time 1.01 seconds
Started Aug 05 05:40:08 PM PDT 24
Finished Aug 05 05:40:09 PM PDT 24
Peak memory 207288 kb
Host smart-d9c72fc9-e927-48d6-bf29-53bc976e700b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33318
38956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3331838956
Directory /workspace/46.usbdev_in_trans/latest


Test location /workspace/coverage/default/46.usbdev_invalid_sync.1792862555
Short name T1146
Test name
Test status
Simulation time 2746851777 ps
CPU time 20.34 seconds
Started Aug 05 05:39:57 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 224044 kb
Host smart-90b6413f-7602-4837-8012-dc04a676abf9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1792862555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.1792862555
Directory /workspace/46.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/46.usbdev_iso_retraction.1500026482
Short name T1799
Test name
Test status
Simulation time 10970543172 ps
CPU time 75.55 seconds
Started Aug 05 05:40:14 PM PDT 24
Finished Aug 05 05:41:30 PM PDT 24
Peak memory 207552 kb
Host smart-ebec1278-845e-4aed-b4d4-14a74e3d1f19
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1500026482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.1500026482
Directory /workspace/46.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/46.usbdev_link_in_err.1810781279
Short name T1329
Test name
Test status
Simulation time 242271071 ps
CPU time 0.97 seconds
Started Aug 05 05:40:01 PM PDT 24
Finished Aug 05 05:40:02 PM PDT 24
Peak memory 207348 kb
Host smart-bf69b4c6-58c4-47cf-a083-b6ec766daf3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
81279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1810781279
Directory /workspace/46.usbdev_link_in_err/latest


Test location /workspace/coverage/default/46.usbdev_link_resume.2136378244
Short name T1595
Test name
Test status
Simulation time 28432342657 ps
CPU time 42.5 seconds
Started Aug 05 05:39:56 PM PDT 24
Finished Aug 05 05:40:39 PM PDT 24
Peak memory 207640 kb
Host smart-dc0cd8fe-7960-4114-b389-dd38b1f4104d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21363
78244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2136378244
Directory /workspace/46.usbdev_link_resume/latest


Test location /workspace/coverage/default/46.usbdev_link_suspend.546752
Short name T2454
Test name
Test status
Simulation time 10545936998 ps
CPU time 13.48 seconds
Started Aug 05 05:40:01 PM PDT 24
Finished Aug 05 05:40:15 PM PDT 24
Peak memory 207692 kb
Host smart-4ecc3f07-7cda-494a-84e5-6d14245b63f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54675
2 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.546752
Directory /workspace/46.usbdev_link_suspend/latest


Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.913410147
Short name T2542
Test name
Test status
Simulation time 4171735093 ps
CPU time 44.38 seconds
Started Aug 05 05:39:56 PM PDT 24
Finished Aug 05 05:40:40 PM PDT 24
Peak memory 217720 kb
Host smart-8a1d2405-f42d-4509-80cb-a21314fab571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91341
0147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.913410147
Directory /workspace/46.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.232483898
Short name T2209
Test name
Test status
Simulation time 3654183730 ps
CPU time 110.71 seconds
Started Aug 05 05:40:11 PM PDT 24
Finished Aug 05 05:42:02 PM PDT 24
Peak memory 217184 kb
Host smart-90733aa9-33f6-45b8-9191-74c1c6d9b638
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=232483898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.232483898
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.1174077273
Short name T1291
Test name
Test status
Simulation time 286478428 ps
CPU time 1.08 seconds
Started Aug 05 05:40:02 PM PDT 24
Finished Aug 05 05:40:04 PM PDT 24
Peak memory 207308 kb
Host smart-03249ddd-981f-40d7-8160-5df503d3ad5e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1174077273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.1174077273
Directory /workspace/46.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1638367190
Short name T859
Test name
Test status
Simulation time 200152120 ps
CPU time 1.01 seconds
Started Aug 05 05:39:52 PM PDT 24
Finished Aug 05 05:39:53 PM PDT 24
Peak memory 207392 kb
Host smart-a8778335-9661-45c4-9702-7f2d1d25151a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16383
67190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1638367190
Directory /workspace/46.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2466984583
Short name T158
Test name
Test status
Simulation time 3623111680 ps
CPU time 103.79 seconds
Started Aug 05 05:39:59 PM PDT 24
Finished Aug 05 05:41:43 PM PDT 24
Peak memory 217316 kb
Host smart-67b46943-1af7-4a4b-887e-2b1383215efc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2466984583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2466984583
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1241370531
Short name T1225
Test name
Test status
Simulation time 153177959 ps
CPU time 0.92 seconds
Started Aug 05 05:40:03 PM PDT 24
Finished Aug 05 05:40:04 PM PDT 24
Peak memory 207312 kb
Host smart-61e2c84e-5109-486e-868c-9d457826fb89
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1241370531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1241370531
Directory /workspace/46.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2482658538
Short name T2022
Test name
Test status
Simulation time 142106954 ps
CPU time 0.86 seconds
Started Aug 05 05:40:08 PM PDT 24
Finished Aug 05 05:40:09 PM PDT 24
Peak memory 207300 kb
Host smart-35ff1277-077d-42f7-82f9-ba8b020d8d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24826
58538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2482658538
Directory /workspace/46.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/46.usbdev_nak_trans.1402739577
Short name T140
Test name
Test status
Simulation time 230172637 ps
CPU time 1.03 seconds
Started Aug 05 05:40:02 PM PDT 24
Finished Aug 05 05:40:03 PM PDT 24
Peak memory 207288 kb
Host smart-d81a5492-a744-4f8b-983e-4fcaa8d9b9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14027
39577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1402739577
Directory /workspace/46.usbdev_nak_trans/latest


Test location /workspace/coverage/default/46.usbdev_out_iso.1058406095
Short name T989
Test name
Test status
Simulation time 178907399 ps
CPU time 0.93 seconds
Started Aug 05 05:40:02 PM PDT 24
Finished Aug 05 05:40:03 PM PDT 24
Peak memory 207348 kb
Host smart-af51ebd8-5159-4e96-be15-e120f0be59f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10584
06095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1058406095
Directory /workspace/46.usbdev_out_iso/latest


Test location /workspace/coverage/default/46.usbdev_out_stall.3648463945
Short name T2489
Test name
Test status
Simulation time 192921914 ps
CPU time 0.87 seconds
Started Aug 05 05:40:13 PM PDT 24
Finished Aug 05 05:40:14 PM PDT 24
Peak memory 207368 kb
Host smart-61249c18-c103-4932-a78f-f023ef2346ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36484
63945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3648463945
Directory /workspace/46.usbdev_out_stall/latest


Test location /workspace/coverage/default/46.usbdev_out_trans_nak.421429581
Short name T124
Test name
Test status
Simulation time 198545055 ps
CPU time 0.94 seconds
Started Aug 05 05:40:06 PM PDT 24
Finished Aug 05 05:40:07 PM PDT 24
Peak memory 207340 kb
Host smart-9bcd1ac6-ae0e-42e4-a22e-0a799d2826f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42142
9581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.421429581
Directory /workspace/46.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/46.usbdev_pending_in_trans.117669819
Short name T1019
Test name
Test status
Simulation time 153412701 ps
CPU time 0.88 seconds
Started Aug 05 05:40:02 PM PDT 24
Finished Aug 05 05:40:03 PM PDT 24
Peak memory 207292 kb
Host smart-9ea15983-014e-4a58-8cab-63789a2d1675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11766
9819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.117669819
Directory /workspace/46.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.1744236197
Short name T1285
Test name
Test status
Simulation time 250427751 ps
CPU time 1.07 seconds
Started Aug 05 05:40:00 PM PDT 24
Finished Aug 05 05:40:01 PM PDT 24
Peak memory 207252 kb
Host smart-77c6d82e-1500-4a70-ae44-9b6e76435729
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1744236197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.1744236197
Directory /workspace/46.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.314360882
Short name T1279
Test name
Test status
Simulation time 149534458 ps
CPU time 0.85 seconds
Started Aug 05 05:40:10 PM PDT 24
Finished Aug 05 05:40:11 PM PDT 24
Peak memory 207268 kb
Host smart-d4392749-86c9-4432-a65d-8aa954212273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31436
0882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.314360882
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.4040805285
Short name T1605
Test name
Test status
Simulation time 31334446 ps
CPU time 0.69 seconds
Started Aug 05 05:39:57 PM PDT 24
Finished Aug 05 05:39:58 PM PDT 24
Peak memory 207284 kb
Host smart-c907a5f9-66be-465b-b4fb-1703bac28053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40408
05285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.4040805285
Directory /workspace/46.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1653132749
Short name T2509
Test name
Test status
Simulation time 10529398923 ps
CPU time 26.57 seconds
Started Aug 05 05:40:02 PM PDT 24
Finished Aug 05 05:40:28 PM PDT 24
Peak memory 215936 kb
Host smart-6d9746b5-fdf5-49dc-a513-ad2ff632c733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16531
32749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1653132749
Directory /workspace/46.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/46.usbdev_pkt_received.2622063217
Short name T1856
Test name
Test status
Simulation time 202694437 ps
CPU time 0.95 seconds
Started Aug 05 05:39:56 PM PDT 24
Finished Aug 05 05:39:57 PM PDT 24
Peak memory 207348 kb
Host smart-17ee7713-ede2-4102-8d1a-37a3ea2432c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26220
63217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2622063217
Directory /workspace/46.usbdev_pkt_received/latest


Test location /workspace/coverage/default/46.usbdev_pkt_sent.3098136403
Short name T3060
Test name
Test status
Simulation time 211733634 ps
CPU time 1.02 seconds
Started Aug 05 05:39:53 PM PDT 24
Finished Aug 05 05:39:54 PM PDT 24
Peak memory 207396 kb
Host smart-feac08ef-8427-48c4-9548-71f58cc9b682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30981
36403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3098136403
Directory /workspace/46.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.4262240644
Short name T729
Test name
Test status
Simulation time 174143527 ps
CPU time 0.92 seconds
Started Aug 05 05:40:05 PM PDT 24
Finished Aug 05 05:40:06 PM PDT 24
Peak memory 207224 kb
Host smart-81ff8f1d-ee3b-469a-8c6f-ed6abe9f1709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42622
40644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.4262240644
Directory /workspace/46.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1159492427
Short name T2937
Test name
Test status
Simulation time 237142033 ps
CPU time 1 seconds
Started Aug 05 05:40:13 PM PDT 24
Finished Aug 05 05:40:14 PM PDT 24
Peak memory 207288 kb
Host smart-86c49fd1-00ca-4bf3-8d40-a584f2e381c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11594
92427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1159492427
Directory /workspace/46.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/46.usbdev_rx_crc_err.11429106
Short name T883
Test name
Test status
Simulation time 182951610 ps
CPU time 0.85 seconds
Started Aug 05 05:40:04 PM PDT 24
Finished Aug 05 05:40:05 PM PDT 24
Peak memory 207340 kb
Host smart-3024f7f8-7a6e-4a73-a0cd-68e606d7bad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11429
106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.11429106
Directory /workspace/46.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/46.usbdev_rx_full.3307246126
Short name T291
Test name
Test status
Simulation time 262440685 ps
CPU time 1.02 seconds
Started Aug 05 05:39:53 PM PDT 24
Finished Aug 05 05:39:54 PM PDT 24
Peak memory 207376 kb
Host smart-f1ea0c65-6abe-43f6-b40e-7f21cc879fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33072
46126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.3307246126
Directory /workspace/46.usbdev_rx_full/latest


Test location /workspace/coverage/default/46.usbdev_setup_stage.274484973
Short name T620
Test name
Test status
Simulation time 181189881 ps
CPU time 0.87 seconds
Started Aug 05 05:40:06 PM PDT 24
Finished Aug 05 05:40:06 PM PDT 24
Peak memory 207336 kb
Host smart-6a933e0f-3f21-449d-962e-7534509f4113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27448
4973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.274484973
Directory /workspace/46.usbdev_setup_stage/latest


Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1623567259
Short name T1307
Test name
Test status
Simulation time 186668270 ps
CPU time 0.9 seconds
Started Aug 05 05:39:54 PM PDT 24
Finished Aug 05 05:39:55 PM PDT 24
Peak memory 207240 kb
Host smart-757d9f00-db4d-4e1d-9309-a570ac55ec02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16235
67259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1623567259
Directory /workspace/46.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/46.usbdev_smoke.2452738092
Short name T2993
Test name
Test status
Simulation time 227917964 ps
CPU time 1.07 seconds
Started Aug 05 05:40:13 PM PDT 24
Finished Aug 05 05:40:14 PM PDT 24
Peak memory 207400 kb
Host smart-09128631-4fde-4c10-91b7-731cb06a17fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24527
38092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2452738092
Directory /workspace/46.usbdev_smoke/latest


Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.809196096
Short name T2839
Test name
Test status
Simulation time 3205194225 ps
CPU time 32.18 seconds
Started Aug 05 05:39:57 PM PDT 24
Finished Aug 05 05:40:29 PM PDT 24
Peak memory 217724 kb
Host smart-b359bc0a-7841-4abf-85b7-6c10c8e5c428
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=809196096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.809196096
Directory /workspace/46.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.200773220
Short name T3032
Test name
Test status
Simulation time 177993615 ps
CPU time 0.85 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207300 kb
Host smart-2cfae794-2eb8-4956-a020-4ecfb0e1a420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20077
3220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.200773220
Directory /workspace/46.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/46.usbdev_stall_trans.3871386519
Short name T2888
Test name
Test status
Simulation time 163055376 ps
CPU time 0.88 seconds
Started Aug 05 05:40:17 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207308 kb
Host smart-fe083c6c-3683-4699-b6b8-2c52c0e6a5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38713
86519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3871386519
Directory /workspace/46.usbdev_stall_trans/latest


Test location /workspace/coverage/default/46.usbdev_stream_len_max.4221053288
Short name T1697
Test name
Test status
Simulation time 943630271 ps
CPU time 2.36 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207496 kb
Host smart-b49d29e4-3eae-48ec-b718-032fcecf16aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42210
53288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.4221053288
Directory /workspace/46.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/46.usbdev_streaming_out.2840169840
Short name T2432
Test name
Test status
Simulation time 2302805655 ps
CPU time 63.16 seconds
Started Aug 05 05:40:07 PM PDT 24
Finished Aug 05 05:41:10 PM PDT 24
Peak memory 215880 kb
Host smart-2cf42854-7519-4328-a18e-7acc13b29a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28401
69840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.2840169840
Directory /workspace/46.usbdev_streaming_out/latest


Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.245557618
Short name T527
Test name
Test status
Simulation time 562677623 ps
CPU time 11.69 seconds
Started Aug 05 05:39:55 PM PDT 24
Finished Aug 05 05:40:07 PM PDT 24
Peak memory 207616 kb
Host smart-1aab5777-9875-4ddc-8efa-bbf139841ab3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245557618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_host
_handshake.245557618
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/47.usbdev_alert_test.1697592854
Short name T2352
Test name
Test status
Simulation time 36854976 ps
CPU time 0.73 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207360 kb
Host smart-df7971d6-7faf-4a28-a290-2a4e6d466374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1697592854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.1697592854
Directory /workspace/47.usbdev_alert_test/latest


Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3646031919
Short name T2812
Test name
Test status
Simulation time 9833166564 ps
CPU time 11.32 seconds
Started Aug 05 05:40:08 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207640 kb
Host smart-0d6c5c13-63ac-4968-893d-1e0445a5206c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646031919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.3646031919
Directory /workspace/47.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1678680460
Short name T2689
Test name
Test status
Simulation time 15352055332 ps
CPU time 21.57 seconds
Started Aug 05 05:40:22 PM PDT 24
Finished Aug 05 05:40:43 PM PDT 24
Peak memory 215816 kb
Host smart-fd275c35-10b5-41e5-9d2c-acc501601319
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678680460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1678680460
Directory /workspace/47.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.4124599240
Short name T2912
Test name
Test status
Simulation time 28390490813 ps
CPU time 33.23 seconds
Started Aug 05 05:40:11 PM PDT 24
Finished Aug 05 05:40:45 PM PDT 24
Peak memory 207576 kb
Host smart-5a350f17-44ba-4db5-a48d-526f4b4569fa
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124599240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.4124599240
Directory /workspace/47.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/47.usbdev_av_buffer.453340370
Short name T1087
Test name
Test status
Simulation time 186570755 ps
CPU time 0.91 seconds
Started Aug 05 05:40:07 PM PDT 24
Finished Aug 05 05:40:08 PM PDT 24
Peak memory 207352 kb
Host smart-23044892-6226-480a-8bea-b3798aba7781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45334
0370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.453340370
Directory /workspace/47.usbdev_av_buffer/latest


Test location /workspace/coverage/default/47.usbdev_bitstuff_err.388527458
Short name T2310
Test name
Test status
Simulation time 146162133 ps
CPU time 0.84 seconds
Started Aug 05 05:40:28 PM PDT 24
Finished Aug 05 05:40:39 PM PDT 24
Peak memory 207316 kb
Host smart-23ae875c-c911-4b7d-a5d7-0cc8622922a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38852
7458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.388527458
Directory /workspace/47.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.3218714824
Short name T686
Test name
Test status
Simulation time 456936880 ps
CPU time 1.48 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:14 PM PDT 24
Peak memory 207328 kb
Host smart-36e03519-bf64-44cd-bae6-58ef3ce456f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32187
14824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.3218714824
Directory /workspace/47.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.2807057468
Short name T1939
Test name
Test status
Simulation time 896511136 ps
CPU time 2.31 seconds
Started Aug 05 05:40:13 PM PDT 24
Finished Aug 05 05:40:15 PM PDT 24
Peak memory 207560 kb
Host smart-8cb886a0-156c-4ba6-965c-ee3206b231eb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2807057468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.2807057468
Directory /workspace/47.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/47.usbdev_device_address.1981681346
Short name T1575
Test name
Test status
Simulation time 31292325588 ps
CPU time 44.48 seconds
Started Aug 05 05:40:13 PM PDT 24
Finished Aug 05 05:40:57 PM PDT 24
Peak memory 207616 kb
Host smart-04c252a0-aa94-48f0-9dfd-ab4368ed9b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19816
81346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.1981681346
Directory /workspace/47.usbdev_device_address/latest


Test location /workspace/coverage/default/47.usbdev_device_timeout.1481456425
Short name T986
Test name
Test status
Simulation time 309755003 ps
CPU time 4.39 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:16 PM PDT 24
Peak memory 207556 kb
Host smart-b1b0dd5c-309b-462e-8e28-1c250b03a583
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481456425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.1481456425
Directory /workspace/47.usbdev_device_timeout/latest


Test location /workspace/coverage/default/47.usbdev_disable_endpoint.62763817
Short name T1339
Test name
Test status
Simulation time 883476475 ps
CPU time 2.02 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:15 PM PDT 24
Peak memory 207320 kb
Host smart-decb3f56-74cb-4289-9e2d-f3967d761060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62763
817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.62763817
Directory /workspace/47.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/47.usbdev_disconnected.2474549776
Short name T3086
Test name
Test status
Simulation time 177787665 ps
CPU time 0.83 seconds
Started Aug 05 05:40:03 PM PDT 24
Finished Aug 05 05:40:04 PM PDT 24
Peak memory 207192 kb
Host smart-a3b87777-715c-4170-b0d7-9bfe680a521d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24745
49776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2474549776
Directory /workspace/47.usbdev_disconnected/latest


Test location /workspace/coverage/default/47.usbdev_enable.3440389582
Short name T1925
Test name
Test status
Simulation time 29693573 ps
CPU time 0.67 seconds
Started Aug 05 05:40:08 PM PDT 24
Finished Aug 05 05:40:09 PM PDT 24
Peak memory 207316 kb
Host smart-9b613959-60df-4c90-ac87-f9d80d88aeb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34403
89582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3440389582
Directory /workspace/47.usbdev_enable/latest


Test location /workspace/coverage/default/47.usbdev_endpoint_access.2244223843
Short name T1637
Test name
Test status
Simulation time 1097721333 ps
CPU time 2.44 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207524 kb
Host smart-8ddce69d-03d8-45f1-91c4-381e84db7b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22442
23843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2244223843
Directory /workspace/47.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/47.usbdev_endpoint_types.3360710053
Short name T403
Test name
Test status
Simulation time 370460508 ps
CPU time 1.26 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:14 PM PDT 24
Peak memory 207352 kb
Host smart-06671055-72fd-4ba2-8406-6c57cff18986
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3360710053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.3360710053
Directory /workspace/47.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/47.usbdev_fifo_rst.3857531161
Short name T645
Test name
Test status
Simulation time 166495493 ps
CPU time 1.6 seconds
Started Aug 05 05:40:10 PM PDT 24
Finished Aug 05 05:40:12 PM PDT 24
Peak memory 207452 kb
Host smart-41e00f28-ab5f-43fc-9b0f-e7fee9b0c372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38575
31161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3857531161
Directory /workspace/47.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/47.usbdev_in_iso.2089579396
Short name T1952
Test name
Test status
Simulation time 174479252 ps
CPU time 0.99 seconds
Started Aug 05 05:40:19 PM PDT 24
Finished Aug 05 05:40:20 PM PDT 24
Peak memory 207524 kb
Host smart-6f38f258-9fa6-4c3d-b1ca-f81ee6426057
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2089579396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2089579396
Directory /workspace/47.usbdev_in_iso/latest


Test location /workspace/coverage/default/47.usbdev_in_stall.449325976
Short name T2644
Test name
Test status
Simulation time 140799635 ps
CPU time 0.83 seconds
Started Aug 05 05:40:24 PM PDT 24
Finished Aug 05 05:40:25 PM PDT 24
Peak memory 207320 kb
Host smart-03e00886-b69a-48d2-883c-5d240ead6427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44932
5976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.449325976
Directory /workspace/47.usbdev_in_stall/latest


Test location /workspace/coverage/default/47.usbdev_in_trans.13252177
Short name T1214
Test name
Test status
Simulation time 194934627 ps
CPU time 0.98 seconds
Started Aug 05 05:40:27 PM PDT 24
Finished Aug 05 05:40:28 PM PDT 24
Peak memory 207376 kb
Host smart-7057257b-32f3-4353-9932-99cf5eb905fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13252
177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.13252177
Directory /workspace/47.usbdev_in_trans/latest


Test location /workspace/coverage/default/47.usbdev_invalid_sync.3367453253
Short name T3103
Test name
Test status
Simulation time 3678417518 ps
CPU time 27.45 seconds
Started Aug 05 05:40:10 PM PDT 24
Finished Aug 05 05:40:38 PM PDT 24
Peak memory 217596 kb
Host smart-5a15d4c2-4eb1-41a0-a6d0-2bbac1105cb7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3367453253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.3367453253
Directory /workspace/47.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/47.usbdev_iso_retraction.2174618400
Short name T538
Test name
Test status
Simulation time 11122689386 ps
CPU time 74.69 seconds
Started Aug 05 05:40:14 PM PDT 24
Finished Aug 05 05:41:29 PM PDT 24
Peak memory 207852 kb
Host smart-08cc8e7e-6720-4924-bdb7-1706e0eb2859
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2174618400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.2174618400
Directory /workspace/47.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/47.usbdev_link_in_err.1012427002
Short name T1485
Test name
Test status
Simulation time 169114257 ps
CPU time 1.01 seconds
Started Aug 05 05:40:11 PM PDT 24
Finished Aug 05 05:40:12 PM PDT 24
Peak memory 207268 kb
Host smart-6929b85a-56b7-43d2-aa11-c5727e9ba152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10124
27002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1012427002
Directory /workspace/47.usbdev_link_in_err/latest


Test location /workspace/coverage/default/47.usbdev_link_resume.2036146261
Short name T958
Test name
Test status
Simulation time 23694235200 ps
CPU time 33.96 seconds
Started Aug 05 05:40:09 PM PDT 24
Finished Aug 05 05:40:43 PM PDT 24
Peak memory 215808 kb
Host smart-b93eeb23-3f71-411e-8adc-5ef5dca85bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20361
46261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.2036146261
Directory /workspace/47.usbdev_link_resume/latest


Test location /workspace/coverage/default/47.usbdev_link_suspend.2640123401
Short name T1670
Test name
Test status
Simulation time 4997360959 ps
CPU time 7.39 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:24 PM PDT 24
Peak memory 215864 kb
Host smart-58bebb31-afbb-42fc-97f1-edc70d2f521b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26401
23401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2640123401
Directory /workspace/47.usbdev_link_suspend/latest


Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.1621503435
Short name T2723
Test name
Test status
Simulation time 4210975750 ps
CPU time 122.72 seconds
Started Aug 05 05:40:09 PM PDT 24
Finished Aug 05 05:42:11 PM PDT 24
Peak memory 218456 kb
Host smart-4c837997-90ac-4e30-8156-fd401538d375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16215
03435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.1621503435
Directory /workspace/47.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2143927763
Short name T2975
Test name
Test status
Simulation time 3078564445 ps
CPU time 23.73 seconds
Started Aug 05 05:40:11 PM PDT 24
Finished Aug 05 05:40:40 PM PDT 24
Peak memory 215712 kb
Host smart-63c9627e-1377-4edf-99eb-941adb3a92a1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2143927763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2143927763
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.2576579817
Short name T751
Test name
Test status
Simulation time 247486089 ps
CPU time 1.01 seconds
Started Aug 05 05:40:08 PM PDT 24
Finished Aug 05 05:40:09 PM PDT 24
Peak memory 207360 kb
Host smart-cc2cade0-007d-4ba8-ba19-d3cedadd5bdd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2576579817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.2576579817
Directory /workspace/47.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3328547673
Short name T2522
Test name
Test status
Simulation time 227019653 ps
CPU time 0.95 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207324 kb
Host smart-9fa913dc-91c4-4db8-93ab-dff6bb0cfe6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33285
47673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3328547673
Directory /workspace/47.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.748295689
Short name T543
Test name
Test status
Simulation time 3008385375 ps
CPU time 30.04 seconds
Started Aug 05 05:40:14 PM PDT 24
Finished Aug 05 05:40:44 PM PDT 24
Peak memory 217428 kb
Host smart-7ca74d75-8349-4f82-93b3-0b1bc414adc4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=748295689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.748295689
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.4035225655
Short name T1553
Test name
Test status
Simulation time 175274886 ps
CPU time 0.93 seconds
Started Aug 05 05:40:02 PM PDT 24
Finished Aug 05 05:40:03 PM PDT 24
Peak memory 207584 kb
Host smart-49f695aa-abb3-48ad-b2bc-a5c55f723228
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4035225655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.4035225655
Directory /workspace/47.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3717672515
Short name T1864
Test name
Test status
Simulation time 160056499 ps
CPU time 0.89 seconds
Started Aug 05 05:40:26 PM PDT 24
Finished Aug 05 05:40:27 PM PDT 24
Peak memory 207344 kb
Host smart-4e3bfaaa-978c-4940-ab2e-4dd999a27ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37176
72515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3717672515
Directory /workspace/47.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/47.usbdev_nak_trans.2399230719
Short name T2833
Test name
Test status
Simulation time 230934796 ps
CPU time 0.95 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:40:16 PM PDT 24
Peak memory 207268 kb
Host smart-617f8658-b57c-4c7f-a6b2-37c57ca29339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23992
30719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2399230719
Directory /workspace/47.usbdev_nak_trans/latest


Test location /workspace/coverage/default/47.usbdev_out_iso.1490518038
Short name T2831
Test name
Test status
Simulation time 157411644 ps
CPU time 0.9 seconds
Started Aug 05 05:40:11 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207348 kb
Host smart-f1d37ce5-9c56-443a-8ded-0ef10a5c89e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14905
18038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.1490518038
Directory /workspace/47.usbdev_out_iso/latest


Test location /workspace/coverage/default/47.usbdev_out_stall.4183500473
Short name T1995
Test name
Test status
Simulation time 197993168 ps
CPU time 0.92 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:40:16 PM PDT 24
Peak memory 207416 kb
Host smart-97e69b2e-7e18-4d4a-826a-b1455cebabe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41835
00473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.4183500473
Directory /workspace/47.usbdev_out_stall/latest


Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3882241130
Short name T1845
Test name
Test status
Simulation time 165839734 ps
CPU time 0.84 seconds
Started Aug 05 05:40:07 PM PDT 24
Finished Aug 05 05:40:08 PM PDT 24
Peak memory 207348 kb
Host smart-e6e1e14f-2278-4057-b436-3cd8c52a6c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38822
41130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3882241130
Directory /workspace/47.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/47.usbdev_pending_in_trans.1610042027
Short name T2815
Test name
Test status
Simulation time 208652529 ps
CPU time 0.91 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207364 kb
Host smart-60521cab-e8a8-411f-a45c-de4d78083f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16100
42027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.1610042027
Directory /workspace/47.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.3309776110
Short name T3027
Test name
Test status
Simulation time 220993276 ps
CPU time 1.04 seconds
Started Aug 05 05:40:08 PM PDT 24
Finished Aug 05 05:40:09 PM PDT 24
Peak memory 207404 kb
Host smart-7d8aa8f0-1940-4ced-b0c9-39f23c95bd33
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3309776110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.3309776110
Directory /workspace/47.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1282705684
Short name T761
Test name
Test status
Simulation time 180431367 ps
CPU time 0.86 seconds
Started Aug 05 05:40:14 PM PDT 24
Finished Aug 05 05:40:15 PM PDT 24
Peak memory 207348 kb
Host smart-6d567505-9940-4913-9241-1478690da8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12827
05684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1282705684
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.4017727204
Short name T2039
Test name
Test status
Simulation time 69886399 ps
CPU time 0.74 seconds
Started Aug 05 05:40:07 PM PDT 24
Finished Aug 05 05:40:08 PM PDT 24
Peak memory 207364 kb
Host smart-b9d9c35a-3e95-48c3-b242-0aa6e5cdaa2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40177
27204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.4017727204
Directory /workspace/47.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1271881861
Short name T1745
Test name
Test status
Simulation time 16630146622 ps
CPU time 39.04 seconds
Started Aug 05 05:40:09 PM PDT 24
Finished Aug 05 05:40:48 PM PDT 24
Peak memory 224044 kb
Host smart-4d19a545-f4e2-427d-865c-cf7a0f1bb7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12718
81861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1271881861
Directory /workspace/47.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/47.usbdev_pkt_received.2801387358
Short name T654
Test name
Test status
Simulation time 218516554 ps
CPU time 0.9 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207352 kb
Host smart-0697054e-0760-4e62-a552-31139e84a4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28013
87358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2801387358
Directory /workspace/47.usbdev_pkt_received/latest


Test location /workspace/coverage/default/47.usbdev_pkt_sent.1230629017
Short name T3045
Test name
Test status
Simulation time 173640681 ps
CPU time 0.88 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207256 kb
Host smart-cd581244-3248-4399-97dc-fc2dc13e9dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12306
29017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1230629017
Directory /workspace/47.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.766203088
Short name T1125
Test name
Test status
Simulation time 206479671 ps
CPU time 0.94 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:40:16 PM PDT 24
Peak memory 207292 kb
Host smart-75526b2b-0e19-4c6c-83f6-6c4b063d668e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76620
3088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.766203088
Directory /workspace/47.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.432806145
Short name T1377
Test name
Test status
Simulation time 221667068 ps
CPU time 0.92 seconds
Started Aug 05 05:40:07 PM PDT 24
Finished Aug 05 05:40:08 PM PDT 24
Peak memory 207268 kb
Host smart-95198b51-48b7-402d-bdd1-cd536351811e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43280
6145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.432806145
Directory /workspace/47.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/47.usbdev_rx_crc_err.4228991961
Short name T2548
Test name
Test status
Simulation time 184468380 ps
CPU time 0.86 seconds
Started Aug 05 05:40:09 PM PDT 24
Finished Aug 05 05:40:15 PM PDT 24
Peak memory 207404 kb
Host smart-c4dee15c-c63f-49b7-8393-b45fe561142f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42289
91961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.4228991961
Directory /workspace/47.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/47.usbdev_rx_full.771829212
Short name T2832
Test name
Test status
Simulation time 366239945 ps
CPU time 1.31 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 207348 kb
Host smart-ccefd6fa-e884-4782-81f8-af01344ec1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77182
9212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.771829212
Directory /workspace/47.usbdev_rx_full/latest


Test location /workspace/coverage/default/47.usbdev_setup_stage.592634300
Short name T2531
Test name
Test status
Simulation time 151716420 ps
CPU time 0.86 seconds
Started Aug 05 05:40:13 PM PDT 24
Finished Aug 05 05:40:15 PM PDT 24
Peak memory 207384 kb
Host smart-ff7faaf2-c5d0-43c7-b90f-73caf8882032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59263
4300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.592634300
Directory /workspace/47.usbdev_setup_stage/latest


Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3401644676
Short name T295
Test name
Test status
Simulation time 148309611 ps
CPU time 0.84 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207340 kb
Host smart-8942a26d-b774-4e7f-896c-7e34da5f071c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34016
44676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3401644676
Directory /workspace/47.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/47.usbdev_smoke.3366502609
Short name T507
Test name
Test status
Simulation time 229579015 ps
CPU time 0.99 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 207264 kb
Host smart-f001cd5e-610c-4606-8d9f-75080ab1095a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33665
02609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3366502609
Directory /workspace/47.usbdev_smoke/latest


Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2835510656
Short name T2553
Test name
Test status
Simulation time 1717865503 ps
CPU time 45.28 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:41:19 PM PDT 24
Peak memory 223824 kb
Host smart-54a0bbfc-5cfd-4c4d-9c2c-61085a651e0f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2835510656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2835510656
Directory /workspace/47.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1309499513
Short name T772
Test name
Test status
Simulation time 153922584 ps
CPU time 0.84 seconds
Started Aug 05 05:40:19 PM PDT 24
Finished Aug 05 05:40:20 PM PDT 24
Peak memory 207356 kb
Host smart-9f872af1-aade-43a5-82be-f5e9967f1b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13094
99513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1309499513
Directory /workspace/47.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/47.usbdev_stall_trans.1505995019
Short name T2302
Test name
Test status
Simulation time 191755204 ps
CPU time 0.96 seconds
Started Aug 05 05:40:20 PM PDT 24
Finished Aug 05 05:40:21 PM PDT 24
Peak memory 207396 kb
Host smart-f219133c-50e8-4bfa-bd9e-8a3674f7144d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15059
95019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1505995019
Directory /workspace/47.usbdev_stall_trans/latest


Test location /workspace/coverage/default/47.usbdev_stream_len_max.4277007621
Short name T1469
Test name
Test status
Simulation time 825559124 ps
CPU time 2.1 seconds
Started Aug 05 05:40:21 PM PDT 24
Finished Aug 05 05:40:23 PM PDT 24
Peak memory 207316 kb
Host smart-d3a45525-d16c-4d68-829a-0e7ed9e7ee3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
07621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.4277007621
Directory /workspace/47.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/47.usbdev_streaming_out.2448934250
Short name T1471
Test name
Test status
Simulation time 2407065299 ps
CPU time 19.48 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 215732 kb
Host smart-2aa0b2cd-135e-4c78-bc70-2de1cc482c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24489
34250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2448934250
Directory /workspace/47.usbdev_streaming_out/latest


Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.2643448058
Short name T2393
Test name
Test status
Simulation time 859924142 ps
CPU time 19.06 seconds
Started Aug 05 05:40:14 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207428 kb
Host smart-5c1d3c24-5c55-4bfa-aa67-df38b121b060
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643448058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.2643448058
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/48.usbdev_alert_test.263931095
Short name T998
Test name
Test status
Simulation time 62472248 ps
CPU time 0.68 seconds
Started Aug 05 05:40:19 PM PDT 24
Finished Aug 05 05:40:20 PM PDT 24
Peak memory 207380 kb
Host smart-907acd73-447c-4b70-b971-a7db34f54484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=263931095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.263931095
Directory /workspace/48.usbdev_alert_test/latest


Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.284657318
Short name T10
Test name
Test status
Simulation time 12125892886 ps
CPU time 16.42 seconds
Started Aug 05 05:40:25 PM PDT 24
Finished Aug 05 05:40:42 PM PDT 24
Peak memory 207632 kb
Host smart-3491c424-3bc3-4b0a-a728-b109e1352674
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284657318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ao
n_wake_disconnect.284657318
Directory /workspace/48.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3961442980
Short name T1890
Test name
Test status
Simulation time 21084337050 ps
CPU time 22.49 seconds
Started Aug 05 05:40:23 PM PDT 24
Finished Aug 05 05:40:46 PM PDT 24
Peak memory 207512 kb
Host smart-978ecd7a-cb60-46e0-8e6a-231181ae3e43
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961442980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3961442980
Directory /workspace/48.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.4064824138
Short name T2323
Test name
Test status
Simulation time 25314602785 ps
CPU time 28.89 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:45 PM PDT 24
Peak memory 216932 kb
Host smart-80411774-4197-4ee8-a271-2a8db599f1ec
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064824138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.4064824138
Directory /workspace/48.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/48.usbdev_av_buffer.2777879859
Short name T2482
Test name
Test status
Simulation time 156203390 ps
CPU time 0.83 seconds
Started Aug 05 05:40:27 PM PDT 24
Finished Aug 05 05:40:28 PM PDT 24
Peak memory 207404 kb
Host smart-110986b4-153f-4dee-a5b3-330a4461bdf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27778
79859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2777879859
Directory /workspace/48.usbdev_av_buffer/latest


Test location /workspace/coverage/default/48.usbdev_bitstuff_err.1603632356
Short name T2333
Test name
Test status
Simulation time 202419937 ps
CPU time 0.91 seconds
Started Aug 05 05:40:14 PM PDT 24
Finished Aug 05 05:40:15 PM PDT 24
Peak memory 207320 kb
Host smart-aa41fa60-1c33-407c-ad31-e3569b7cb51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16036
32356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.1603632356
Directory /workspace/48.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2752675108
Short name T1258
Test name
Test status
Simulation time 318615000 ps
CPU time 1.23 seconds
Started Aug 05 05:40:09 PM PDT 24
Finished Aug 05 05:40:11 PM PDT 24
Peak memory 207428 kb
Host smart-d7c1d268-332b-4ff2-a655-c60440bb567d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27526
75108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2752675108
Directory /workspace/48.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.161244638
Short name T1051
Test name
Test status
Simulation time 1293434250 ps
CPU time 3.03 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207544 kb
Host smart-187c226a-194d-4640-96e6-b1ee0728dc5f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=161244638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.161244638
Directory /workspace/48.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/48.usbdev_device_address.1397402930
Short name T2031
Test name
Test status
Simulation time 24019981137 ps
CPU time 37.96 seconds
Started Aug 05 05:40:30 PM PDT 24
Finished Aug 05 05:41:08 PM PDT 24
Peak memory 207556 kb
Host smart-6035a76b-1ab8-412e-b9f1-ade755086d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13974
02930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.1397402930
Directory /workspace/48.usbdev_device_address/latest


Test location /workspace/coverage/default/48.usbdev_device_timeout.2990185512
Short name T3031
Test name
Test status
Simulation time 1958031703 ps
CPU time 46.86 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:41:03 PM PDT 24
Peak memory 207500 kb
Host smart-452108f2-fe52-496f-8ad0-fe574dfd3cbb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990185512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.2990185512
Directory /workspace/48.usbdev_device_timeout/latest


Test location /workspace/coverage/default/48.usbdev_disable_endpoint.2213796319
Short name T1871
Test name
Test status
Simulation time 844529737 ps
CPU time 2.16 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:40:20 PM PDT 24
Peak memory 207360 kb
Host smart-45d5860f-9c83-486d-8784-facf3d751e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22137
96319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.2213796319
Directory /workspace/48.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/48.usbdev_disconnected.954109117
Short name T2762
Test name
Test status
Simulation time 158504518 ps
CPU time 0.85 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207332 kb
Host smart-352a99d6-413e-490b-898a-1f13f54c034f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95410
9117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.954109117
Directory /workspace/48.usbdev_disconnected/latest


Test location /workspace/coverage/default/48.usbdev_enable.2777913960
Short name T1975
Test name
Test status
Simulation time 49179618 ps
CPU time 0.7 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 207316 kb
Host smart-87925459-5bed-49e2-b819-520501250bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27779
13960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2777913960
Directory /workspace/48.usbdev_enable/latest


Test location /workspace/coverage/default/48.usbdev_endpoint_access.695294895
Short name T1331
Test name
Test status
Simulation time 915595526 ps
CPU time 2.45 seconds
Started Aug 05 05:40:14 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 207432 kb
Host smart-c8988012-9962-4e74-91bd-8a864de31dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69529
4895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.695294895
Directory /workspace/48.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/48.usbdev_fifo_rst.3944501238
Short name T1920
Test name
Test status
Simulation time 162078837 ps
CPU time 1.69 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207472 kb
Host smart-0537b0b7-9563-4a96-935b-a45bc1dcbaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39445
01238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3944501238
Directory /workspace/48.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/48.usbdev_in_iso.3079189197
Short name T1710
Test name
Test status
Simulation time 206901333 ps
CPU time 1.05 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207532 kb
Host smart-dff9d12b-d12f-41e0-893c-922a79540f63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3079189197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3079189197
Directory /workspace/48.usbdev_in_iso/latest


Test location /workspace/coverage/default/48.usbdev_in_stall.690889772
Short name T2916
Test name
Test status
Simulation time 149697038 ps
CPU time 0.83 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207292 kb
Host smart-316a1d3f-ff69-4832-9129-26c2a3c1b79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69088
9772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.690889772
Directory /workspace/48.usbdev_in_stall/latest


Test location /workspace/coverage/default/48.usbdev_in_trans.2245168980
Short name T1841
Test name
Test status
Simulation time 246879902 ps
CPU time 1.06 seconds
Started Aug 05 05:40:17 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207384 kb
Host smart-33a4adce-f591-43dc-be0e-8e838789bb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22451
68980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2245168980
Directory /workspace/48.usbdev_in_trans/latest


Test location /workspace/coverage/default/48.usbdev_invalid_sync.109177867
Short name T1126
Test name
Test status
Simulation time 3017678367 ps
CPU time 24.46 seconds
Started Aug 05 05:40:20 PM PDT 24
Finished Aug 05 05:40:44 PM PDT 24
Peak memory 215712 kb
Host smart-0c7a1c4b-fcde-4700-b74c-799bea4ddba7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=109177867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.109177867
Directory /workspace/48.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/48.usbdev_link_in_err.2943817574
Short name T2686
Test name
Test status
Simulation time 171451059 ps
CPU time 0.84 seconds
Started Aug 05 05:40:17 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207348 kb
Host smart-51fd44e6-9c84-4ad7-a0fe-6fd252f26cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29438
17574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2943817574
Directory /workspace/48.usbdev_link_in_err/latest


Test location /workspace/coverage/default/48.usbdev_link_resume.43005299
Short name T3018
Test name
Test status
Simulation time 27322384359 ps
CPU time 33.13 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:41:08 PM PDT 24
Peak memory 215808 kb
Host smart-4664ccd4-a0a5-463b-9f9e-794afb020c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43005
299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.43005299
Directory /workspace/48.usbdev_link_resume/latest


Test location /workspace/coverage/default/48.usbdev_link_suspend.898498750
Short name T2050
Test name
Test status
Simulation time 5778261396 ps
CPU time 7.49 seconds
Started Aug 05 05:40:27 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 215800 kb
Host smart-e84b456d-9ef2-4e73-83fc-9fab8551258a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89849
8750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.898498750
Directory /workspace/48.usbdev_link_suspend/latest


Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1472763078
Short name T696
Test name
Test status
Simulation time 2370319533 ps
CPU time 63.14 seconds
Started Aug 05 05:40:19 PM PDT 24
Finished Aug 05 05:41:22 PM PDT 24
Peak memory 217352 kb
Host smart-e3924eb0-afec-4387-9fd6-d84afdd932c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14727
63078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1472763078
Directory /workspace/48.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3038449966
Short name T3006
Test name
Test status
Simulation time 3689903840 ps
CPU time 35.8 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:52 PM PDT 24
Peak memory 215860 kb
Host smart-31bfe5e1-8e14-4fc9-bdc1-02241d9717b8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3038449966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3038449966
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1843621070
Short name T1753
Test name
Test status
Simulation time 265863585 ps
CPU time 1.01 seconds
Started Aug 05 05:40:19 PM PDT 24
Finished Aug 05 05:40:20 PM PDT 24
Peak memory 207408 kb
Host smart-e04868ad-af5c-4c84-a3d6-0342d619d00b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1843621070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1843621070
Directory /workspace/48.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3710285411
Short name T895
Test name
Test status
Simulation time 197514460 ps
CPU time 0.96 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:40:16 PM PDT 24
Peak memory 207276 kb
Host smart-c898a95a-6718-4b86-9f2a-e84ccf035e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37102
85411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3710285411
Directory /workspace/48.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2875336894
Short name T2165
Test name
Test status
Simulation time 1348557574 ps
CPU time 37.15 seconds
Started Aug 05 05:40:14 PM PDT 24
Finished Aug 05 05:40:52 PM PDT 24
Peak memory 217212 kb
Host smart-7aff14d6-9036-4aa7-9a4e-0d9b285abea0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2875336894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2875336894
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2542407130
Short name T1128
Test name
Test status
Simulation time 157208535 ps
CPU time 0.85 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:40:16 PM PDT 24
Peak memory 207252 kb
Host smart-54702673-c8d1-43f3-a56a-75e02fd052eb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2542407130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2542407130
Directory /workspace/48.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3519488310
Short name T2217
Test name
Test status
Simulation time 202816793 ps
CPU time 0.88 seconds
Started Aug 05 05:40:29 PM PDT 24
Finished Aug 05 05:40:30 PM PDT 24
Peak memory 207396 kb
Host smart-74a4dd41-2375-4500-9f86-f008334a7ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35194
88310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3519488310
Directory /workspace/48.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/48.usbdev_nak_trans.2769716473
Short name T127
Test name
Test status
Simulation time 194922425 ps
CPU time 0.96 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 207288 kb
Host smart-6134c976-4999-44b0-a758-4083d4f6d367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27697
16473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2769716473
Directory /workspace/48.usbdev_nak_trans/latest


Test location /workspace/coverage/default/48.usbdev_out_iso.334151198
Short name T2498
Test name
Test status
Simulation time 239340310 ps
CPU time 0.93 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207324 kb
Host smart-88217434-9d7c-4e85-835d-df7f4bda1f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33415
1198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.334151198
Directory /workspace/48.usbdev_out_iso/latest


Test location /workspace/coverage/default/48.usbdev_out_stall.789177512
Short name T2088
Test name
Test status
Simulation time 186404502 ps
CPU time 0.92 seconds
Started Aug 05 05:40:12 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 207232 kb
Host smart-5d5a4d79-19f8-4d91-be83-0cf202224758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78917
7512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.789177512
Directory /workspace/48.usbdev_out_stall/latest


Test location /workspace/coverage/default/48.usbdev_out_trans_nak.328450382
Short name T1669
Test name
Test status
Simulation time 182683832 ps
CPU time 0.94 seconds
Started Aug 05 05:40:14 PM PDT 24
Finished Aug 05 05:40:15 PM PDT 24
Peak memory 207612 kb
Host smart-1764fe5d-e7e4-46e1-88f0-f468bd19abaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32845
0382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.328450382
Directory /workspace/48.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/48.usbdev_pending_in_trans.821962581
Short name T1788
Test name
Test status
Simulation time 165434993 ps
CPU time 0.87 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:40:16 PM PDT 24
Peak memory 207272 kb
Host smart-0b1358be-3581-4c72-8502-bc48698e51af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82196
2581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.821962581
Directory /workspace/48.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3458374655
Short name T750
Test name
Test status
Simulation time 211977103 ps
CPU time 1.01 seconds
Started Aug 05 05:40:11 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 207384 kb
Host smart-8ebf08b3-5077-4780-bfe2-da0b36b6759d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3458374655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3458374655
Directory /workspace/48.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.791770092
Short name T1709
Test name
Test status
Simulation time 163358612 ps
CPU time 0.85 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207320 kb
Host smart-885f7a15-7c26-4317-b96a-c8f3d82633b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79177
0092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.791770092
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.648352892
Short name T2417
Test name
Test status
Simulation time 36503621 ps
CPU time 0.68 seconds
Started Aug 05 05:40:19 PM PDT 24
Finished Aug 05 05:40:20 PM PDT 24
Peak memory 207316 kb
Host smart-3af7198e-cb10-4269-9b1f-3170a31bd20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64835
2892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.648352892
Directory /workspace/48.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3146424140
Short name T2662
Test name
Test status
Simulation time 18698143145 ps
CPU time 46.28 seconds
Started Aug 05 05:40:29 PM PDT 24
Finished Aug 05 05:41:15 PM PDT 24
Peak memory 215812 kb
Host smart-f3d0d8e2-a099-4b3a-90bc-adcc9a0c51c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31464
24140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3146424140
Directory /workspace/48.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/48.usbdev_pkt_received.2231063416
Short name T2773
Test name
Test status
Simulation time 179342595 ps
CPU time 1 seconds
Started Aug 05 05:40:17 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207320 kb
Host smart-787e08f8-5f9c-410e-a507-8ae0c12ab582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22310
63416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2231063416
Directory /workspace/48.usbdev_pkt_received/latest


Test location /workspace/coverage/default/48.usbdev_pkt_sent.1577645718
Short name T2020
Test name
Test status
Simulation time 204946856 ps
CPU time 0.95 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 207368 kb
Host smart-f60030ad-a57b-4c88-b48b-7b1f8f1db6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15776
45718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1577645718
Directory /workspace/48.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.3309994881
Short name T607
Test name
Test status
Simulation time 201523636 ps
CPU time 0.93 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207348 kb
Host smart-bbbf2478-2c89-4d54-80ff-cb9eae170303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33099
94881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.3309994881
Directory /workspace/48.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1822610243
Short name T2753
Test name
Test status
Simulation time 148940125 ps
CPU time 0.87 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 207376 kb
Host smart-9563fb15-e87e-4a88-8828-722b5743e2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18226
10243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1822610243
Directory /workspace/48.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2548795022
Short name T2151
Test name
Test status
Simulation time 182240144 ps
CPU time 0.91 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:32 PM PDT 24
Peak memory 207320 kb
Host smart-cf0af3d2-76db-446c-8d50-1c26981bc3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25487
95022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2548795022
Directory /workspace/48.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/48.usbdev_rx_full.1716301947
Short name T1111
Test name
Test status
Simulation time 345180514 ps
CPU time 1.16 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207268 kb
Host smart-ba7f84aa-cb6f-43b3-8014-2fffd94e0f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17163
01947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.1716301947
Directory /workspace/48.usbdev_rx_full/latest


Test location /workspace/coverage/default/48.usbdev_setup_stage.2548470137
Short name T1241
Test name
Test status
Simulation time 163181895 ps
CPU time 0.84 seconds
Started Aug 05 05:40:17 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207316 kb
Host smart-6cca6483-6f01-414b-a0be-ea652ebb2f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25484
70137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2548470137
Directory /workspace/48.usbdev_setup_stage/latest


Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.575225714
Short name T1730
Test name
Test status
Simulation time 157225983 ps
CPU time 0.86 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207232 kb
Host smart-0380a8ff-1ada-489c-b0ea-d705e905c713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57522
5714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.575225714
Directory /workspace/48.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/48.usbdev_smoke.2346120616
Short name T914
Test name
Test status
Simulation time 271272637 ps
CPU time 1.13 seconds
Started Aug 05 05:40:17 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207272 kb
Host smart-9be3f491-5657-43a1-9b78-019705043477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23461
20616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2346120616
Directory /workspace/48.usbdev_smoke/latest


Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2640759853
Short name T520
Test name
Test status
Simulation time 1684620058 ps
CPU time 46.65 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:41:05 PM PDT 24
Peak memory 217416 kb
Host smart-8177d137-7bb6-4b2e-8b0c-1ed7394172a4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2640759853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2640759853
Directory /workspace/48.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1581096381
Short name T3033
Test name
Test status
Simulation time 158215369 ps
CPU time 0.83 seconds
Started Aug 05 05:40:11 PM PDT 24
Finished Aug 05 05:40:12 PM PDT 24
Peak memory 207328 kb
Host smart-f0332e97-410b-4dc3-a759-d094528fdb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15810
96381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1581096381
Directory /workspace/48.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/48.usbdev_stall_trans.1728078088
Short name T985
Test name
Test status
Simulation time 150276021 ps
CPU time 0.87 seconds
Started Aug 05 05:40:19 PM PDT 24
Finished Aug 05 05:40:20 PM PDT 24
Peak memory 207396 kb
Host smart-61307591-91fa-4471-bb81-4a32cec38818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17280
78088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1728078088
Directory /workspace/48.usbdev_stall_trans/latest


Test location /workspace/coverage/default/48.usbdev_stream_len_max.2845694283
Short name T850
Test name
Test status
Simulation time 1272222231 ps
CPU time 3.12 seconds
Started Aug 05 05:40:23 PM PDT 24
Finished Aug 05 05:40:26 PM PDT 24
Peak memory 207372 kb
Host smart-fdcde12f-5ec8-447d-9ec4-88edd3d13f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28456
94283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.2845694283
Directory /workspace/48.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/48.usbdev_streaming_out.2217884863
Short name T2289
Test name
Test status
Simulation time 2469510961 ps
CPU time 18.6 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 223932 kb
Host smart-a796cc5a-9a2d-4465-ba81-784fc51ac286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22178
84863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.2217884863
Directory /workspace/48.usbdev_streaming_out/latest


Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.1950843922
Short name T2935
Test name
Test status
Simulation time 1532815056 ps
CPU time 13.21 seconds
Started Aug 05 05:40:17 PM PDT 24
Finished Aug 05 05:40:30 PM PDT 24
Peak memory 207504 kb
Host smart-06ec7f73-dda4-47ac-86aa-09c2b43a3ffc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950843922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.1950843922
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/49.usbdev_alert_test.1901819617
Short name T192
Test name
Test status
Simulation time 57392738 ps
CPU time 0.73 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207420 kb
Host smart-a1ff4f56-bda7-4572-b660-0e0cde8c9f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1901819617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1901819617
Directory /workspace/49.usbdev_alert_test/latest


Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2791061670
Short name T1758
Test name
Test status
Simulation time 5514490394 ps
CPU time 7.26 seconds
Started Aug 05 05:40:17 PM PDT 24
Finished Aug 05 05:40:24 PM PDT 24
Peak memory 215820 kb
Host smart-eb8c845f-8d7a-44db-87c2-ae5023332447
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791061670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.2791061670
Directory /workspace/49.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.4107039246
Short name T602
Test name
Test status
Simulation time 20450372297 ps
CPU time 24.28 seconds
Started Aug 05 05:40:17 PM PDT 24
Finished Aug 05 05:40:41 PM PDT 24
Peak memory 207564 kb
Host smart-cc56710a-ec03-4ad2-98c2-07248751dd73
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107039246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.4107039246
Directory /workspace/49.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3580172552
Short name T2844
Test name
Test status
Simulation time 25914616725 ps
CPU time 34.62 seconds
Started Aug 05 05:40:09 PM PDT 24
Finished Aug 05 05:40:44 PM PDT 24
Peak memory 215824 kb
Host smart-f33d260d-89a9-4957-afe7-c802f0551719
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580172552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.3580172552
Directory /workspace/49.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/49.usbdev_av_buffer.481829031
Short name T633
Test name
Test status
Simulation time 213261648 ps
CPU time 0.92 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207384 kb
Host smart-a4e02c23-0127-47fd-9540-be23aa402d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48182
9031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.481829031
Directory /workspace/49.usbdev_av_buffer/latest


Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.3898179970
Short name T2994
Test name
Test status
Simulation time 393391955 ps
CPU time 1.38 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:32 PM PDT 24
Peak memory 207272 kb
Host smart-96bfebb7-c467-45aa-8592-9c2e27b4705d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38981
79970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.3898179970
Directory /workspace/49.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3476725264
Short name T1041
Test name
Test status
Simulation time 620552484 ps
CPU time 1.77 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207332 kb
Host smart-22eb860a-df54-4dbb-8c6f-20028e49fc6c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3476725264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3476725264
Directory /workspace/49.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/49.usbdev_device_address.691822753
Short name T1600
Test name
Test status
Simulation time 37822833842 ps
CPU time 60.33 seconds
Started Aug 05 05:40:20 PM PDT 24
Finished Aug 05 05:41:20 PM PDT 24
Peak memory 207592 kb
Host smart-8589a27b-e00f-4d81-a42f-e1d04289d64a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69182
2753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.691822753
Directory /workspace/49.usbdev_device_address/latest


Test location /workspace/coverage/default/49.usbdev_device_timeout.1906413294
Short name T1299
Test name
Test status
Simulation time 2209552209 ps
CPU time 15.44 seconds
Started Aug 05 05:40:30 PM PDT 24
Finished Aug 05 05:40:46 PM PDT 24
Peak memory 207724 kb
Host smart-80040378-fae5-4672-9247-a8aaf73453c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906413294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.1906413294
Directory /workspace/49.usbdev_device_timeout/latest


Test location /workspace/coverage/default/49.usbdev_disable_endpoint.3315637262
Short name T1613
Test name
Test status
Simulation time 614697851 ps
CPU time 1.42 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207268 kb
Host smart-b303be68-d373-4aa2-a243-e06912a2c30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33156
37262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.3315637262
Directory /workspace/49.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/49.usbdev_disconnected.2572864767
Short name T927
Test name
Test status
Simulation time 128916524 ps
CPU time 0.79 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207280 kb
Host smart-a2ed9cc1-65e3-4bb1-b99b-a18f3c09a662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25728
64767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2572864767
Directory /workspace/49.usbdev_disconnected/latest


Test location /workspace/coverage/default/49.usbdev_enable.960856875
Short name T1927
Test name
Test status
Simulation time 34877816 ps
CPU time 0.67 seconds
Started Aug 05 05:40:26 PM PDT 24
Finished Aug 05 05:40:27 PM PDT 24
Peak memory 207276 kb
Host smart-f039bfc5-eb39-4a49-8d92-a5d67f170522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96085
6875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.960856875
Directory /workspace/49.usbdev_enable/latest


Test location /workspace/coverage/default/49.usbdev_endpoint_access.429527629
Short name T2900
Test name
Test status
Simulation time 867411242 ps
CPU time 2.21 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 207552 kb
Host smart-29de2cf2-e033-4f4a-b4a4-a5d2f87d2de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42952
7629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.429527629
Directory /workspace/49.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/49.usbdev_endpoint_types.1289848632
Short name T300
Test name
Test status
Simulation time 687071631 ps
CPU time 1.69 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:34 PM PDT 24
Peak memory 207244 kb
Host smart-98dad867-2b69-4028-8927-31924edc77b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1289848632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.1289848632
Directory /workspace/49.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/49.usbdev_fifo_rst.549033315
Short name T3091
Test name
Test status
Simulation time 228019729 ps
CPU time 1.56 seconds
Started Aug 05 05:40:24 PM PDT 24
Finished Aug 05 05:40:25 PM PDT 24
Peak memory 207444 kb
Host smart-6dea9091-8bbb-4a15-855b-6ccc02756e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54903
3315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.549033315
Directory /workspace/49.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/49.usbdev_in_iso.3469719688
Short name T2737
Test name
Test status
Simulation time 292623464 ps
CPU time 1.22 seconds
Started Aug 05 05:40:22 PM PDT 24
Finished Aug 05 05:40:23 PM PDT 24
Peak memory 207572 kb
Host smart-2c87186b-fd17-4da5-bfa6-f52cda861870
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3469719688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3469719688
Directory /workspace/49.usbdev_in_iso/latest


Test location /workspace/coverage/default/49.usbdev_in_stall.1518891473
Short name T591
Test name
Test status
Simulation time 145731811 ps
CPU time 0.85 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207308 kb
Host smart-a2b35f11-5e2f-4ab5-8de1-4d6c77da3845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15188
91473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1518891473
Directory /workspace/49.usbdev_in_stall/latest


Test location /workspace/coverage/default/49.usbdev_in_trans.1533124964
Short name T2734
Test name
Test status
Simulation time 224703625 ps
CPU time 1 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:32 PM PDT 24
Peak memory 207316 kb
Host smart-e25f8e89-595f-4e61-bc17-49d8b1b0ca44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15331
24964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1533124964
Directory /workspace/49.usbdev_in_trans/latest


Test location /workspace/coverage/default/49.usbdev_invalid_sync.1223694042
Short name T2326
Test name
Test status
Simulation time 5637936570 ps
CPU time 164.35 seconds
Started Aug 05 05:40:23 PM PDT 24
Finished Aug 05 05:43:08 PM PDT 24
Peak memory 218176 kb
Host smart-3bb6ddb6-b2d6-476a-9242-2965b641fd48
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1223694042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1223694042
Directory /workspace/49.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/49.usbdev_link_in_err.1266080788
Short name T1170
Test name
Test status
Simulation time 171350589 ps
CPU time 0.93 seconds
Started Aug 05 05:40:26 PM PDT 24
Finished Aug 05 05:40:27 PM PDT 24
Peak memory 207256 kb
Host smart-dc6d680e-db17-43d9-a26a-e10062f10ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12660
80788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1266080788
Directory /workspace/49.usbdev_link_in_err/latest


Test location /workspace/coverage/default/49.usbdev_link_resume.522896434
Short name T47
Test name
Test status
Simulation time 32519275116 ps
CPU time 57.05 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:41:13 PM PDT 24
Peak memory 207700 kb
Host smart-e4913e79-13fe-43c7-a3ab-6784d7372754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52289
6434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.522896434
Directory /workspace/49.usbdev_link_resume/latest


Test location /workspace/coverage/default/49.usbdev_link_suspend.1897724695
Short name T2201
Test name
Test status
Simulation time 10207747934 ps
CPU time 12.81 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:40:28 PM PDT 24
Peak memory 207592 kb
Host smart-9d016256-ffc8-415c-91f5-0c05ab5a7352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18977
24695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1897724695
Directory /workspace/49.usbdev_link_suspend/latest


Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.15292065
Short name T718
Test name
Test status
Simulation time 2608774119 ps
CPU time 24.76 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:57 PM PDT 24
Peak memory 224044 kb
Host smart-81c9eeeb-fe14-4389-9264-5509ccfa75fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15292
065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.15292065
Directory /workspace/49.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.3412578400
Short name T1571
Test name
Test status
Simulation time 3822814541 ps
CPU time 27.89 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:41:01 PM PDT 24
Peak memory 215788 kb
Host smart-c6b57a61-fdba-43e3-b33e-5783b87da3e1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3412578400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.3412578400
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3686007746
Short name T946
Test name
Test status
Simulation time 261818363 ps
CPU time 0.98 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207352 kb
Host smart-86caac29-4c0c-44f4-9de1-5b51f1a5a80b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3686007746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3686007746
Directory /workspace/49.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2778506112
Short name T532
Test name
Test status
Simulation time 199360420 ps
CPU time 1.06 seconds
Started Aug 05 05:40:26 PM PDT 24
Finished Aug 05 05:40:27 PM PDT 24
Peak memory 207352 kb
Host smart-28290a2c-085b-41bb-a3cb-64c61be3cb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27785
06112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2778506112
Directory /workspace/49.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.2489101163
Short name T2146
Test name
Test status
Simulation time 1654713216 ps
CPU time 45.7 seconds
Started Aug 05 05:40:36 PM PDT 24
Finished Aug 05 05:41:22 PM PDT 24
Peak memory 215752 kb
Host smart-77a4889c-a0f2-49d3-ab54-6329186ef816
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2489101163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.2489101163
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1927301059
Short name T672
Test name
Test status
Simulation time 162579338 ps
CPU time 0.87 seconds
Started Aug 05 05:40:38 PM PDT 24
Finished Aug 05 05:40:39 PM PDT 24
Peak memory 207272 kb
Host smart-bcbc2b21-45a4-4190-86e8-b00680c559ed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1927301059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1927301059
Directory /workspace/49.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3163469809
Short name T584
Test name
Test status
Simulation time 182705340 ps
CPU time 0.88 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 207328 kb
Host smart-68d254b9-8ad7-44de-97a8-a9b54fccec89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31634
69809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3163469809
Directory /workspace/49.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/49.usbdev_nak_trans.616638174
Short name T146
Test name
Test status
Simulation time 167467262 ps
CPU time 0.88 seconds
Started Aug 05 05:40:24 PM PDT 24
Finished Aug 05 05:40:25 PM PDT 24
Peak memory 207368 kb
Host smart-1c6c8647-33ed-4149-8fbc-ec10d786af9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61663
8174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.616638174
Directory /workspace/49.usbdev_nak_trans/latest


Test location /workspace/coverage/default/49.usbdev_out_iso.2243533960
Short name T2288
Test name
Test status
Simulation time 219258022 ps
CPU time 0.96 seconds
Started Aug 05 05:40:15 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 207376 kb
Host smart-b9361caf-c300-4ff1-bdb1-6149e47463df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22435
33960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2243533960
Directory /workspace/49.usbdev_out_iso/latest


Test location /workspace/coverage/default/49.usbdev_out_stall.2533463059
Short name T2539
Test name
Test status
Simulation time 177159217 ps
CPU time 0.88 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:32 PM PDT 24
Peak memory 207268 kb
Host smart-fdec0099-9e60-4594-b908-62d4196b05f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25334
63059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2533463059
Directory /workspace/49.usbdev_out_stall/latest


Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2442944568
Short name T3065
Test name
Test status
Simulation time 179089612 ps
CPU time 0.93 seconds
Started Aug 05 05:40:16 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 207276 kb
Host smart-e9825994-60ee-4d06-b3b2-601ae8f705a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24429
44568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2442944568
Directory /workspace/49.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/49.usbdev_pending_in_trans.4108780131
Short name T2213
Test name
Test status
Simulation time 218763703 ps
CPU time 1 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:34 PM PDT 24
Peak memory 207276 kb
Host smart-a4938205-9c1a-4ee2-9b61-779cbfefe9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41087
80131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.4108780131
Directory /workspace/49.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.2613777293
Short name T2457
Test name
Test status
Simulation time 230447829 ps
CPU time 1.02 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:32 PM PDT 24
Peak memory 207328 kb
Host smart-3e1ba3e0-c492-47fd-9fd6-4cd406d205a3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2613777293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.2613777293
Directory /workspace/49.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1642209438
Short name T1734
Test name
Test status
Simulation time 187790378 ps
CPU time 0.93 seconds
Started Aug 05 05:40:21 PM PDT 24
Finished Aug 05 05:40:22 PM PDT 24
Peak memory 207392 kb
Host smart-e17ea929-55a7-4f1d-8ab2-6da806406a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16422
09438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1642209438
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1121681285
Short name T2603
Test name
Test status
Simulation time 93089894 ps
CPU time 0.74 seconds
Started Aug 05 05:40:21 PM PDT 24
Finished Aug 05 05:40:22 PM PDT 24
Peak memory 207316 kb
Host smart-fc5c9fc2-bd63-46dd-b52b-10e1592bd97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11216
81285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1121681285
Directory /workspace/49.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/49.usbdev_pkt_buffer.4269980899
Short name T3116
Test name
Test status
Simulation time 17368903473 ps
CPU time 42.52 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:41:15 PM PDT 24
Peak memory 215856 kb
Host smart-989e6b95-9af6-46ee-9fad-f5d956753e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42699
80899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.4269980899
Directory /workspace/49.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/49.usbdev_pkt_received.1445673591
Short name T2
Test name
Test status
Simulation time 188441490 ps
CPU time 0.88 seconds
Started Aug 05 05:40:19 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207352 kb
Host smart-98918e19-ea22-4aea-bedd-e7aabfbea2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14456
73591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1445673591
Directory /workspace/49.usbdev_pkt_received/latest


Test location /workspace/coverage/default/49.usbdev_pkt_sent.4038847785
Short name T562
Test name
Test status
Simulation time 203079131 ps
CPU time 0.93 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207296 kb
Host smart-07c0739e-1307-4a18-bd9d-213d6ae2d007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40388
47785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.4038847785
Directory /workspace/49.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.566189579
Short name T1698
Test name
Test status
Simulation time 213303221 ps
CPU time 0.96 seconds
Started Aug 05 05:40:24 PM PDT 24
Finished Aug 05 05:40:25 PM PDT 24
Peak memory 207376 kb
Host smart-92441b96-9543-4cc0-bca3-58bb64bf8126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56618
9579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.566189579
Directory /workspace/49.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.3299509212
Short name T680
Test name
Test status
Simulation time 185686271 ps
CPU time 0.88 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207312 kb
Host smart-5acca897-9e37-4305-97b2-5e28c8bb0f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32995
09212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.3299509212
Directory /workspace/49.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2722424201
Short name T2453
Test name
Test status
Simulation time 174592652 ps
CPU time 0.86 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207368 kb
Host smart-335a802d-ead6-4844-a1d3-2a88a390f3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27224
24201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2722424201
Directory /workspace/49.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/49.usbdev_rx_full.3975450408
Short name T2540
Test name
Test status
Simulation time 251526749 ps
CPU time 1.02 seconds
Started Aug 05 05:40:19 PM PDT 24
Finished Aug 05 05:40:21 PM PDT 24
Peak memory 207320 kb
Host smart-18fff393-3ddb-4f3e-af71-fa1160ddfcaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
50408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.3975450408
Directory /workspace/49.usbdev_rx_full/latest


Test location /workspace/coverage/default/49.usbdev_setup_stage.4279334261
Short name T1026
Test name
Test status
Simulation time 165476667 ps
CPU time 0.85 seconds
Started Aug 05 05:40:17 PM PDT 24
Finished Aug 05 05:40:18 PM PDT 24
Peak memory 207276 kb
Host smart-bc49e0bf-bca4-4221-af80-8eccefcb8715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42793
34261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.4279334261
Directory /workspace/49.usbdev_setup_stage/latest


Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1261246028
Short name T1644
Test name
Test status
Simulation time 156131882 ps
CPU time 0.79 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 207292 kb
Host smart-4b74ab33-ee11-4e35-ad00-c450ca349608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12612
46028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1261246028
Directory /workspace/49.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/49.usbdev_smoke.3871704775
Short name T660
Test name
Test status
Simulation time 245474045 ps
CPU time 0.99 seconds
Started Aug 05 05:40:18 PM PDT 24
Finished Aug 05 05:40:19 PM PDT 24
Peak memory 207608 kb
Host smart-9a9a37bc-922d-44ea-a994-4417f9316ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38717
04775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3871704775
Directory /workspace/49.usbdev_smoke/latest


Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.3518987460
Short name T1018
Test name
Test status
Simulation time 2906063630 ps
CPU time 81.09 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:41:52 PM PDT 24
Peak memory 217852 kb
Host smart-ef1afe5e-ad7c-492c-83c0-d791abcb1c7f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3518987460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.3518987460
Directory /workspace/49.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.136751958
Short name T1406
Test name
Test status
Simulation time 179694843 ps
CPU time 0.89 seconds
Started Aug 05 05:40:20 PM PDT 24
Finished Aug 05 05:40:21 PM PDT 24
Peak memory 207404 kb
Host smart-4ef1320b-3371-4458-bce4-26725364aa50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13675
1958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.136751958
Directory /workspace/49.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/49.usbdev_stall_trans.197277168
Short name T1232
Test name
Test status
Simulation time 239531884 ps
CPU time 0.94 seconds
Started Aug 05 05:40:19 PM PDT 24
Finished Aug 05 05:40:20 PM PDT 24
Peak memory 207292 kb
Host smart-7e9f83e7-29fe-4f6f-b339-f7c6e53ce172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19727
7168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.197277168
Directory /workspace/49.usbdev_stall_trans/latest


Test location /workspace/coverage/default/49.usbdev_stream_len_max.2014387162
Short name T512
Test name
Test status
Simulation time 195628636 ps
CPU time 0.93 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207280 kb
Host smart-7a95ddcb-9a2e-4663-aaa2-03f2f7110755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20143
87162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2014387162
Directory /workspace/49.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/49.usbdev_streaming_out.1210782351
Short name T2254
Test name
Test status
Simulation time 3166486631 ps
CPU time 30.48 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:41:03 PM PDT 24
Peak memory 215848 kb
Host smart-101ffa73-079b-4614-94c9-1e52305f1da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
82351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1210782351
Directory /workspace/49.usbdev_streaming_out/latest


Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.2759693152
Short name T3094
Test name
Test status
Simulation time 4909933377 ps
CPU time 35.3 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:41:07 PM PDT 24
Peak memory 207700 kb
Host smart-83fb3604-b87e-43a4-9583-780007fae4a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759693152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.2759693152
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/5.usbdev_alert_test.2172910511
Short name T992
Test name
Test status
Simulation time 83664209 ps
CPU time 0.72 seconds
Started Aug 05 05:34:04 PM PDT 24
Finished Aug 05 05:34:05 PM PDT 24
Peak memory 207380 kb
Host smart-c14d1c56-f44f-438d-b8bc-28e248cf80f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2172910511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2172910511
Directory /workspace/5.usbdev_alert_test/latest


Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1226826266
Short name T1930
Test name
Test status
Simulation time 9598848635 ps
CPU time 11.98 seconds
Started Aug 05 05:33:55 PM PDT 24
Finished Aug 05 05:34:08 PM PDT 24
Peak memory 207628 kb
Host smart-d5939b83-758e-4220-85dd-beacf699d259
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226826266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.1226826266
Directory /workspace/5.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2755794899
Short name T2318
Test name
Test status
Simulation time 15761656421 ps
CPU time 18.82 seconds
Started Aug 05 05:33:56 PM PDT 24
Finished Aug 05 05:34:15 PM PDT 24
Peak memory 215836 kb
Host smart-7923fe28-54ad-44bb-8458-8c45c421b14a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755794899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2755794899
Directory /workspace/5.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.4020342347
Short name T2699
Test name
Test status
Simulation time 28953107330 ps
CPU time 31.34 seconds
Started Aug 05 05:33:59 PM PDT 24
Finished Aug 05 05:34:30 PM PDT 24
Peak memory 207504 kb
Host smart-2ecedf1b-1825-42ff-9d59-8c85b9590f7e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020342347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.4020342347
Directory /workspace/5.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/5.usbdev_av_buffer.3964406921
Short name T2279
Test name
Test status
Simulation time 160163593 ps
CPU time 0.84 seconds
Started Aug 05 05:33:56 PM PDT 24
Finished Aug 05 05:33:57 PM PDT 24
Peak memory 207264 kb
Host smart-4c649176-486e-4252-ba07-167c53b1d1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39644
06921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3964406921
Directory /workspace/5.usbdev_av_buffer/latest


Test location /workspace/coverage/default/5.usbdev_bitstuff_err.2479573076
Short name T2048
Test name
Test status
Simulation time 150770274 ps
CPU time 0.84 seconds
Started Aug 05 05:33:59 PM PDT 24
Finished Aug 05 05:34:00 PM PDT 24
Peak memory 207252 kb
Host smart-8564d199-6596-4938-80c7-a4a0c1f12637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24795
73076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2479573076
Directory /workspace/5.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.1619824347
Short name T1693
Test name
Test status
Simulation time 229691230 ps
CPU time 1.08 seconds
Started Aug 05 05:33:56 PM PDT 24
Finished Aug 05 05:33:57 PM PDT 24
Peak memory 207260 kb
Host smart-2d3213cb-16aa-46fb-8ae6-91942621f808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16198
24347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.1619824347
Directory /workspace/5.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2746324119
Short name T2573
Test name
Test status
Simulation time 1096653919 ps
CPU time 2.88 seconds
Started Aug 05 05:33:59 PM PDT 24
Finished Aug 05 05:34:02 PM PDT 24
Peak memory 207568 kb
Host smart-702793e7-f175-4989-a5f3-fdaaef061da3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2746324119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2746324119
Directory /workspace/5.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/5.usbdev_device_address.3012365976
Short name T1847
Test name
Test status
Simulation time 48425147308 ps
CPU time 77.42 seconds
Started Aug 05 05:33:55 PM PDT 24
Finished Aug 05 05:35:12 PM PDT 24
Peak memory 207708 kb
Host smart-3aff255d-0acc-408b-adca-57ae56d5e4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30123
65976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3012365976
Directory /workspace/5.usbdev_device_address/latest


Test location /workspace/coverage/default/5.usbdev_device_timeout.1258131882
Short name T1171
Test name
Test status
Simulation time 835194211 ps
CPU time 5.33 seconds
Started Aug 05 05:33:59 PM PDT 24
Finished Aug 05 05:34:04 PM PDT 24
Peak memory 207568 kb
Host smart-e71be42b-138f-4808-bf52-a9a783649842
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258131882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.1258131882
Directory /workspace/5.usbdev_device_timeout/latest


Test location /workspace/coverage/default/5.usbdev_disable_endpoint.2576202861
Short name T2455
Test name
Test status
Simulation time 990714065 ps
CPU time 2.06 seconds
Started Aug 05 05:33:54 PM PDT 24
Finished Aug 05 05:33:56 PM PDT 24
Peak memory 207328 kb
Host smart-658faa17-d35f-4fd5-a68d-551116c1025b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25762
02861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.2576202861
Directory /workspace/5.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/5.usbdev_disconnected.2001642703
Short name T2963
Test name
Test status
Simulation time 174464758 ps
CPU time 0.86 seconds
Started Aug 05 05:33:57 PM PDT 24
Finished Aug 05 05:33:58 PM PDT 24
Peak memory 207316 kb
Host smart-7263ddc4-936e-4dd2-983d-1b72e28d4607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20016
42703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2001642703
Directory /workspace/5.usbdev_disconnected/latest


Test location /workspace/coverage/default/5.usbdev_enable.1691541689
Short name T764
Test name
Test status
Simulation time 39814409 ps
CPU time 0.72 seconds
Started Aug 05 05:34:00 PM PDT 24
Finished Aug 05 05:34:01 PM PDT 24
Peak memory 207316 kb
Host smart-5ddce0aa-31b3-46e1-9ce9-e0ed73839269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16915
41689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1691541689
Directory /workspace/5.usbdev_enable/latest


Test location /workspace/coverage/default/5.usbdev_endpoint_access.1268831090
Short name T2494
Test name
Test status
Simulation time 721207970 ps
CPU time 2.44 seconds
Started Aug 05 05:33:54 PM PDT 24
Finished Aug 05 05:33:57 PM PDT 24
Peak memory 207608 kb
Host smart-363af991-38de-4d83-9920-faa76a9fbec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12688
31090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1268831090
Directory /workspace/5.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/5.usbdev_endpoint_types.3540192303
Short name T383
Test name
Test status
Simulation time 466187867 ps
CPU time 1.45 seconds
Started Aug 05 05:34:00 PM PDT 24
Finished Aug 05 05:34:02 PM PDT 24
Peak memory 207324 kb
Host smart-4822f7ea-dfeb-462d-abfc-f3706384e4ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3540192303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.3540192303
Directory /workspace/5.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/5.usbdev_fifo_rst.3985964081
Short name T2673
Test name
Test status
Simulation time 255819165 ps
CPU time 1.94 seconds
Started Aug 05 05:33:57 PM PDT 24
Finished Aug 05 05:33:59 PM PDT 24
Peak memory 207412 kb
Host smart-b54b33c7-eb90-4b4d-b369-dbc8b3b4c924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39859
64081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3985964081
Directory /workspace/5.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/5.usbdev_in_iso.3855508258
Short name T1230
Test name
Test status
Simulation time 160013715 ps
CPU time 0.88 seconds
Started Aug 05 05:33:59 PM PDT 24
Finished Aug 05 05:34:00 PM PDT 24
Peak memory 207256 kb
Host smart-2d689882-441b-4dde-a32c-7b9cab392561
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3855508258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3855508258
Directory /workspace/5.usbdev_in_iso/latest


Test location /workspace/coverage/default/5.usbdev_in_stall.981177714
Short name T2282
Test name
Test status
Simulation time 139806791 ps
CPU time 0.84 seconds
Started Aug 05 05:33:56 PM PDT 24
Finished Aug 05 05:33:57 PM PDT 24
Peak memory 207332 kb
Host smart-ba78dfde-1bb0-499b-bb93-4ea5d5d4bb93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98117
7714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.981177714
Directory /workspace/5.usbdev_in_stall/latest


Test location /workspace/coverage/default/5.usbdev_in_trans.2069579206
Short name T655
Test name
Test status
Simulation time 217137785 ps
CPU time 1 seconds
Started Aug 05 05:33:58 PM PDT 24
Finished Aug 05 05:33:59 PM PDT 24
Peak memory 207460 kb
Host smart-06c0a0c4-8213-459d-b4ed-23dea58226a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20695
79206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2069579206
Directory /workspace/5.usbdev_in_trans/latest


Test location /workspace/coverage/default/5.usbdev_invalid_sync.3538313688
Short name T1777
Test name
Test status
Simulation time 3132056384 ps
CPU time 31.15 seconds
Started Aug 05 05:33:55 PM PDT 24
Finished Aug 05 05:34:26 PM PDT 24
Peak memory 224068 kb
Host smart-a768837d-2c48-448b-86ee-81707b9db7df
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3538313688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.3538313688
Directory /workspace/5.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/5.usbdev_iso_retraction.4076400929
Short name T2909
Test name
Test status
Simulation time 5361054649 ps
CPU time 57.47 seconds
Started Aug 05 05:33:56 PM PDT 24
Finished Aug 05 05:34:53 PM PDT 24
Peak memory 207640 kb
Host smart-d20fab99-8957-4030-9725-3e388a6028ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4076400929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.4076400929
Directory /workspace/5.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/5.usbdev_link_in_err.2893727409
Short name T828
Test name
Test status
Simulation time 235775282 ps
CPU time 1.03 seconds
Started Aug 05 05:33:54 PM PDT 24
Finished Aug 05 05:33:56 PM PDT 24
Peak memory 207308 kb
Host smart-58c2b97c-7ac0-4c1b-8847-fad9659d1058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28937
27409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2893727409
Directory /workspace/5.usbdev_link_in_err/latest


Test location /workspace/coverage/default/5.usbdev_link_resume.323742478
Short name T632
Test name
Test status
Simulation time 8656491878 ps
CPU time 13.96 seconds
Started Aug 05 05:33:56 PM PDT 24
Finished Aug 05 05:34:10 PM PDT 24
Peak memory 216024 kb
Host smart-c58799de-ff9a-4b49-8e2e-eafcefb13300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32374
2478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.323742478
Directory /workspace/5.usbdev_link_resume/latest


Test location /workspace/coverage/default/5.usbdev_link_suspend.312305208
Short name T784
Test name
Test status
Simulation time 10850616348 ps
CPU time 12.89 seconds
Started Aug 05 05:33:57 PM PDT 24
Finished Aug 05 05:34:10 PM PDT 24
Peak memory 207636 kb
Host smart-de7f4f3d-a5f8-47cb-b592-f9c64f7f2b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31230
5208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.312305208
Directory /workspace/5.usbdev_link_suspend/latest


Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.2016280671
Short name T1651
Test name
Test status
Simulation time 3342970695 ps
CPU time 94.71 seconds
Started Aug 05 05:33:56 PM PDT 24
Finished Aug 05 05:35:30 PM PDT 24
Peak memory 215880 kb
Host smart-1fe51fb2-2134-4e85-9809-59416c0acea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20162
80671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.2016280671
Directory /workspace/5.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2510507567
Short name T2038
Test name
Test status
Simulation time 2079465436 ps
CPU time 58.37 seconds
Started Aug 05 05:34:04 PM PDT 24
Finished Aug 05 05:35:02 PM PDT 24
Peak memory 215740 kb
Host smart-f9b190b1-9b4a-4904-a39a-cffa825ce8ee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2510507567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2510507567
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.1030099728
Short name T2459
Test name
Test status
Simulation time 246156372 ps
CPU time 1.02 seconds
Started Aug 05 05:34:11 PM PDT 24
Finished Aug 05 05:34:12 PM PDT 24
Peak memory 207352 kb
Host smart-d237f59e-3c64-413c-a37c-6d4d3d34dd1b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1030099728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1030099728
Directory /workspace/5.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3901297991
Short name T2967
Test name
Test status
Simulation time 201998321 ps
CPU time 1.06 seconds
Started Aug 05 05:34:03 PM PDT 24
Finished Aug 05 05:34:04 PM PDT 24
Peak memory 207424 kb
Host smart-0faf2fa5-4f35-4127-b1a0-c3673a3f6b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39012
97991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3901297991
Directory /workspace/5.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.723891588
Short name T2596
Test name
Test status
Simulation time 1877717693 ps
CPU time 56.17 seconds
Started Aug 05 05:34:04 PM PDT 24
Finished Aug 05 05:35:01 PM PDT 24
Peak memory 215640 kb
Host smart-f95e8dbe-9df4-4a2e-94ab-fd2307de1db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72389
1588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.723891588
Directory /workspace/5.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.101881872
Short name T117
Test name
Test status
Simulation time 1737708673 ps
CPU time 15.58 seconds
Started Aug 05 05:34:05 PM PDT 24
Finished Aug 05 05:34:20 PM PDT 24
Peak memory 207580 kb
Host smart-74538838-b289-44cc-bc05-fc176a084407
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=101881872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.101881872
Directory /workspace/5.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.1837587747
Short name T1330
Test name
Test status
Simulation time 3112491485 ps
CPU time 88.4 seconds
Started Aug 05 05:34:00 PM PDT 24
Finished Aug 05 05:35:29 PM PDT 24
Peak memory 215832 kb
Host smart-260fcaed-6dc4-4c26-a0a1-3e455a9418eb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1837587747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.1837587747
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.2121223074
Short name T2248
Test name
Test status
Simulation time 160354837 ps
CPU time 0.8 seconds
Started Aug 05 05:34:04 PM PDT 24
Finished Aug 05 05:34:05 PM PDT 24
Peak memory 207284 kb
Host smart-26176846-3b39-421d-83d5-700f1fce5164
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2121223074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.2121223074
Directory /workspace/5.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1557202389
Short name T1271
Test name
Test status
Simulation time 147135386 ps
CPU time 0.91 seconds
Started Aug 05 05:34:06 PM PDT 24
Finished Aug 05 05:34:07 PM PDT 24
Peak memory 207288 kb
Host smart-44d377cf-cf39-4d21-91d5-79aff5416316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15572
02389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1557202389
Directory /workspace/5.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/5.usbdev_nak_trans.2410626393
Short name T130
Test name
Test status
Simulation time 169927373 ps
CPU time 0.87 seconds
Started Aug 05 05:34:02 PM PDT 24
Finished Aug 05 05:34:03 PM PDT 24
Peak memory 207368 kb
Host smart-d0b7ea95-2b62-4397-888b-b76199a89629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24106
26393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2410626393
Directory /workspace/5.usbdev_nak_trans/latest


Test location /workspace/coverage/default/5.usbdev_out_iso.993809031
Short name T2198
Test name
Test status
Simulation time 178514577 ps
CPU time 0.89 seconds
Started Aug 05 05:34:04 PM PDT 24
Finished Aug 05 05:34:05 PM PDT 24
Peak memory 207228 kb
Host smart-5d63fd66-ed7f-417c-b47b-ba213b5d669e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99380
9031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.993809031
Directory /workspace/5.usbdev_out_iso/latest


Test location /workspace/coverage/default/5.usbdev_out_stall.203112461
Short name T894
Test name
Test status
Simulation time 149474463 ps
CPU time 0.88 seconds
Started Aug 05 05:34:02 PM PDT 24
Finished Aug 05 05:34:03 PM PDT 24
Peak memory 207344 kb
Host smart-7b98fde4-2651-4d91-abbd-8362724b9f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20311
2461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.203112461
Directory /workspace/5.usbdev_out_stall/latest


Test location /workspace/coverage/default/5.usbdev_out_trans_nak.187086786
Short name T2853
Test name
Test status
Simulation time 188569169 ps
CPU time 0.89 seconds
Started Aug 05 05:34:02 PM PDT 24
Finished Aug 05 05:34:03 PM PDT 24
Peak memory 207252 kb
Host smart-61220e86-ee5e-46ab-a80a-f72ef4616736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18708
6786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.187086786
Directory /workspace/5.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1765641602
Short name T2052
Test name
Test status
Simulation time 147167671 ps
CPU time 0.83 seconds
Started Aug 05 05:34:04 PM PDT 24
Finished Aug 05 05:34:05 PM PDT 24
Peak memory 207440 kb
Host smart-040bbd4d-ce37-4b52-b8a9-e36c6b9d28e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17656
41602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1765641602
Directory /workspace/5.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.4063318393
Short name T1671
Test name
Test status
Simulation time 192600212 ps
CPU time 1.05 seconds
Started Aug 05 05:34:01 PM PDT 24
Finished Aug 05 05:34:02 PM PDT 24
Peak memory 207384 kb
Host smart-a2396bcf-6722-406d-96ab-32363b2f2248
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4063318393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.4063318393
Directory /workspace/5.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.158290163
Short name T2372
Test name
Test status
Simulation time 138677250 ps
CPU time 0.84 seconds
Started Aug 05 05:34:04 PM PDT 24
Finished Aug 05 05:34:05 PM PDT 24
Peak memory 207364 kb
Host smart-400d7f0e-1623-4a31-8c15-28cab09cae22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15829
0163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.158290163
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1676988477
Short name T2356
Test name
Test status
Simulation time 39522509 ps
CPU time 0.71 seconds
Started Aug 05 05:34:04 PM PDT 24
Finished Aug 05 05:34:05 PM PDT 24
Peak memory 207252 kb
Host smart-11f1414b-297d-48b7-ac44-85765019c487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16769
88477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1676988477
Directory /workspace/5.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3309623062
Short name T277
Test name
Test status
Simulation time 9236064099 ps
CPU time 22.79 seconds
Started Aug 05 05:34:04 PM PDT 24
Finished Aug 05 05:34:27 PM PDT 24
Peak memory 215960 kb
Host smart-77bcf3bf-678f-4a16-a618-1b4ffc7edb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33096
23062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3309623062
Directory /workspace/5.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/5.usbdev_pkt_received.766540040
Short name T2473
Test name
Test status
Simulation time 180685680 ps
CPU time 0.99 seconds
Started Aug 05 05:34:05 PM PDT 24
Finished Aug 05 05:34:06 PM PDT 24
Peak memory 207268 kb
Host smart-18bffc0b-6c60-404e-92f3-d5b6e3914675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76654
0040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.766540040
Directory /workspace/5.usbdev_pkt_received/latest


Test location /workspace/coverage/default/5.usbdev_pkt_sent.3128768190
Short name T1585
Test name
Test status
Simulation time 215967645 ps
CPU time 1.05 seconds
Started Aug 05 05:34:02 PM PDT 24
Finished Aug 05 05:34:03 PM PDT 24
Peak memory 207268 kb
Host smart-dd8a1a9d-16f4-433d-a26a-3c31a847c47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31287
68190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3128768190
Directory /workspace/5.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2655473958
Short name T1501
Test name
Test status
Simulation time 3566745526 ps
CPU time 96.04 seconds
Started Aug 05 05:34:05 PM PDT 24
Finished Aug 05 05:35:41 PM PDT 24
Peak memory 215884 kb
Host smart-744611e3-bebe-49bd-8190-f22ba6a60ec1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655473958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2655473958
Directory /workspace/5.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1827637451
Short name T2407
Test name
Test status
Simulation time 2904983863 ps
CPU time 82 seconds
Started Aug 05 05:34:05 PM PDT 24
Finished Aug 05 05:35:27 PM PDT 24
Peak memory 218516 kb
Host smart-1cd359c7-bfd8-4f03-ae91-695dd2399031
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1827637451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1827637451
Directory /workspace/5.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/5.usbdev_rand_suspends.3085015713
Short name T2268
Test name
Test status
Simulation time 6314814323 ps
CPU time 95.53 seconds
Started Aug 05 05:34:05 PM PDT 24
Finished Aug 05 05:35:40 PM PDT 24
Peak memory 215816 kb
Host smart-47c816bd-0481-42e4-a317-6196f17d58b8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085015713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3085015713
Directory /workspace/5.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2494707041
Short name T3101
Test name
Test status
Simulation time 187021100 ps
CPU time 0.93 seconds
Started Aug 05 05:34:03 PM PDT 24
Finished Aug 05 05:34:04 PM PDT 24
Peak memory 207324 kb
Host smart-820f2226-1629-4f3d-af3b-bb9d7749e94f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24947
07041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2494707041
Directory /workspace/5.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.3150370532
Short name T2657
Test name
Test status
Simulation time 208550395 ps
CPU time 0.9 seconds
Started Aug 05 05:34:03 PM PDT 24
Finished Aug 05 05:34:04 PM PDT 24
Peak memory 207380 kb
Host smart-f4a7392d-c561-4269-a669-b8023b77b23a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31503
70532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3150370532
Directory /workspace/5.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/5.usbdev_resume_link_active.1693645207
Short name T1981
Test name
Test status
Simulation time 20169440380 ps
CPU time 24.85 seconds
Started Aug 05 05:34:05 PM PDT 24
Finished Aug 05 05:34:30 PM PDT 24
Peak memory 207392 kb
Host smart-38381b8a-31fe-4467-b125-c8d87258272e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16936
45207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.1693645207
Directory /workspace/5.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/5.usbdev_rx_crc_err.3368906187
Short name T1039
Test name
Test status
Simulation time 177588510 ps
CPU time 0.89 seconds
Started Aug 05 05:34:11 PM PDT 24
Finished Aug 05 05:34:12 PM PDT 24
Peak memory 207368 kb
Host smart-ce2a16b4-d228-4125-946d-26bcc39d7403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33689
06187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.3368906187
Directory /workspace/5.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/5.usbdev_rx_full.373692942
Short name T288
Test name
Test status
Simulation time 249213944 ps
CPU time 1.15 seconds
Started Aug 05 05:34:09 PM PDT 24
Finished Aug 05 05:34:11 PM PDT 24
Peak memory 207352 kb
Host smart-967a57f8-55bb-40aa-84a9-70984d17a36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37369
2942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.373692942
Directory /workspace/5.usbdev_rx_full/latest


Test location /workspace/coverage/default/5.usbdev_setup_stage.876844085
Short name T1284
Test name
Test status
Simulation time 148693519 ps
CPU time 0.85 seconds
Started Aug 05 05:34:04 PM PDT 24
Finished Aug 05 05:34:05 PM PDT 24
Peak memory 207332 kb
Host smart-26b26ef0-0be7-48f8-b3de-f41119d3e094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87684
4085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.876844085
Directory /workspace/5.usbdev_setup_stage/latest


Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3121750602
Short name T2226
Test name
Test status
Simulation time 151887992 ps
CPU time 0.88 seconds
Started Aug 05 05:34:06 PM PDT 24
Finished Aug 05 05:34:07 PM PDT 24
Peak memory 207288 kb
Host smart-d281b6f3-9b34-494c-9677-bf261c838d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31217
50602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3121750602
Directory /workspace/5.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/5.usbdev_smoke.1883044786
Short name T2140
Test name
Test status
Simulation time 246147599 ps
CPU time 1.03 seconds
Started Aug 05 05:34:02 PM PDT 24
Finished Aug 05 05:34:04 PM PDT 24
Peak memory 207364 kb
Host smart-8965841d-f5ce-4897-b53e-4bda37e06293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18830
44786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1883044786
Directory /workspace/5.usbdev_smoke/latest


Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.3556169209
Short name T3095
Test name
Test status
Simulation time 2648149900 ps
CPU time 19.98 seconds
Started Aug 05 05:34:03 PM PDT 24
Finished Aug 05 05:34:23 PM PDT 24
Peak memory 224044 kb
Host smart-b1e91286-4a52-40c5-a39c-ce159ae52695
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3556169209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.3556169209
Directory /workspace/5.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1491116828
Short name T2106
Test name
Test status
Simulation time 195281691 ps
CPU time 0.91 seconds
Started Aug 05 05:34:03 PM PDT 24
Finished Aug 05 05:34:04 PM PDT 24
Peak memory 207356 kb
Host smart-43089812-dfc5-4863-aae0-35fc2edfda81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14911
16828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1491116828
Directory /workspace/5.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/5.usbdev_stall_trans.2695570753
Short name T1942
Test name
Test status
Simulation time 166769799 ps
CPU time 0.89 seconds
Started Aug 05 05:34:07 PM PDT 24
Finished Aug 05 05:34:08 PM PDT 24
Peak memory 207348 kb
Host smart-a91c23f1-d3a8-4db8-96d8-780704cbea41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26955
70753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2695570753
Directory /workspace/5.usbdev_stall_trans/latest


Test location /workspace/coverage/default/5.usbdev_stream_len_max.3804139166
Short name T1933
Test name
Test status
Simulation time 770179887 ps
CPU time 2.09 seconds
Started Aug 05 05:34:01 PM PDT 24
Finished Aug 05 05:34:03 PM PDT 24
Peak memory 207240 kb
Host smart-097b312e-2f6f-44a8-be8e-8a13b1ba860d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38041
39166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.3804139166
Directory /workspace/5.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/5.usbdev_streaming_out.475899728
Short name T2955
Test name
Test status
Simulation time 2219111937 ps
CPU time 20.81 seconds
Started Aug 05 05:34:04 PM PDT 24
Finished Aug 05 05:34:25 PM PDT 24
Peak memory 216784 kb
Host smart-038c9bc7-2728-4aee-bdad-54f71acefc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47589
9728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.475899728
Directory /workspace/5.usbdev_streaming_out/latest


Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.2168823919
Short name T2615
Test name
Test status
Simulation time 430967272 ps
CPU time 8.15 seconds
Started Aug 05 05:33:55 PM PDT 24
Finished Aug 05 05:34:03 PM PDT 24
Peak memory 207572 kb
Host smart-80d2b447-dff4-4ca8-8471-2f93a8a70f94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168823919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.2168823919
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/50.usbdev_endpoint_types.798234217
Short name T19
Test name
Test status
Simulation time 380196292 ps
CPU time 1.24 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207344 kb
Host smart-c6349d94-41df-4039-9a0a-f02cd69b43fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=798234217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.798234217
Directory /workspace/50.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/51.usbdev_endpoint_types.3092761146
Short name T345
Test name
Test status
Simulation time 796510225 ps
CPU time 1.96 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207316 kb
Host smart-f38e8ee3-b939-41ec-ba46-e480d8b10856
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3092761146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.3092761146
Directory /workspace/51.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/52.usbdev_endpoint_types.1580533895
Short name T464
Test name
Test status
Simulation time 356225809 ps
CPU time 1.07 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:32 PM PDT 24
Peak memory 207316 kb
Host smart-39bc6e23-5dc5-465f-a76d-e40f3719afa4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1580533895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.1580533895
Directory /workspace/52.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/53.usbdev_endpoint_types.3795906778
Short name T452
Test name
Test status
Simulation time 409141448 ps
CPU time 1.32 seconds
Started Aug 05 05:40:26 PM PDT 24
Finished Aug 05 05:40:28 PM PDT 24
Peak memory 207324 kb
Host smart-0c408435-f526-4c1f-a077-ad82452985c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3795906778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.3795906778
Directory /workspace/53.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/54.usbdev_endpoint_types.4175971926
Short name T2259
Test name
Test status
Simulation time 161161783 ps
CPU time 0.86 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207372 kb
Host smart-a00b6000-b1d9-4cf5-b5ed-d3a15f346a80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4175971926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.4175971926
Directory /workspace/54.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/55.usbdev_endpoint_types.3482374393
Short name T462
Test name
Test status
Simulation time 357145822 ps
CPU time 1.16 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:32 PM PDT 24
Peak memory 207224 kb
Host smart-0904d9fa-fd4e-4125-80ca-52fd20c5562e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3482374393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.3482374393
Directory /workspace/55.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/57.usbdev_endpoint_types.2498560138
Short name T333
Test name
Test status
Simulation time 894601132 ps
CPU time 1.93 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:34 PM PDT 24
Peak memory 207404 kb
Host smart-63f8a1b8-fda7-42fa-9ed7-e323d4b941a2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2498560138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.2498560138
Directory /workspace/57.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/6.usbdev_alert_test.3007939710
Short name T2111
Test name
Test status
Simulation time 36320504 ps
CPU time 0.67 seconds
Started Aug 05 05:34:18 PM PDT 24
Finished Aug 05 05:34:18 PM PDT 24
Peak memory 207376 kb
Host smart-b111bca3-9be5-4365-8348-9012cdd89103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3007939710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.3007939710
Directory /workspace/6.usbdev_alert_test/latest


Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.2552767875
Short name T3122
Test name
Test status
Simulation time 10076284963 ps
CPU time 11.34 seconds
Started Aug 05 05:34:02 PM PDT 24
Finished Aug 05 05:34:14 PM PDT 24
Peak memory 207680 kb
Host smart-b46a785b-1214-47ef-b942-1b3394f53de4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552767875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.2552767875
Directory /workspace/6.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3177826158
Short name T665
Test name
Test status
Simulation time 14061204186 ps
CPU time 17.01 seconds
Started Aug 05 05:34:01 PM PDT 24
Finished Aug 05 05:34:18 PM PDT 24
Peak memory 215756 kb
Host smart-c9171d3c-258a-4061-95df-e5e1afb4d056
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177826158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3177826158
Directory /workspace/6.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3502845887
Short name T2962
Test name
Test status
Simulation time 31427910440 ps
CPU time 47.08 seconds
Started Aug 05 05:34:01 PM PDT 24
Finished Aug 05 05:34:48 PM PDT 24
Peak memory 207620 kb
Host smart-49db0336-437e-4682-a19d-abbfde496c26
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502845887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.3502845887
Directory /workspace/6.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/6.usbdev_av_buffer.582950336
Short name T1206
Test name
Test status
Simulation time 186169102 ps
CPU time 0.97 seconds
Started Aug 05 05:34:09 PM PDT 24
Finished Aug 05 05:34:10 PM PDT 24
Peak memory 207260 kb
Host smart-d68dfc43-9fa6-48b4-8cc1-a7923db93400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58295
0336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.582950336
Directory /workspace/6.usbdev_av_buffer/latest


Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1663745484
Short name T2344
Test name
Test status
Simulation time 156355340 ps
CPU time 0.84 seconds
Started Aug 05 05:34:10 PM PDT 24
Finished Aug 05 05:34:11 PM PDT 24
Peak memory 207288 kb
Host smart-493fdfdf-d636-41b6-bdb0-216913d0570c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16637
45484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1663745484
Directory /workspace/6.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.625252326
Short name T2595
Test name
Test status
Simulation time 158836020 ps
CPU time 0.84 seconds
Started Aug 05 05:34:11 PM PDT 24
Finished Aug 05 05:34:12 PM PDT 24
Peak memory 207364 kb
Host smart-1e958ccd-c5f3-4cce-9365-0afa934eec26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62525
2326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.625252326
Directory /workspace/6.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3797792931
Short name T1817
Test name
Test status
Simulation time 761954017 ps
CPU time 2.15 seconds
Started Aug 05 05:34:10 PM PDT 24
Finished Aug 05 05:34:12 PM PDT 24
Peak memory 207452 kb
Host smart-114c6322-2813-4217-b9d0-20526e169cda
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3797792931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3797792931
Directory /workspace/6.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/6.usbdev_device_address.780288422
Short name T1450
Test name
Test status
Simulation time 53361392718 ps
CPU time 81.96 seconds
Started Aug 05 05:34:09 PM PDT 24
Finished Aug 05 05:35:32 PM PDT 24
Peak memory 207692 kb
Host smart-f114190d-e9cd-43b3-9cf1-2d6923baf24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78028
8422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.780288422
Directory /workspace/6.usbdev_device_address/latest


Test location /workspace/coverage/default/6.usbdev_device_timeout.1233143851
Short name T2403
Test name
Test status
Simulation time 837494678 ps
CPU time 19.53 seconds
Started Aug 05 05:34:12 PM PDT 24
Finished Aug 05 05:34:31 PM PDT 24
Peak memory 207624 kb
Host smart-19a26598-e29e-4082-bbbd-fd76edb10428
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233143851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.1233143851
Directory /workspace/6.usbdev_device_timeout/latest


Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3699818125
Short name T2679
Test name
Test status
Simulation time 958200032 ps
CPU time 2.13 seconds
Started Aug 05 05:34:14 PM PDT 24
Finished Aug 05 05:34:16 PM PDT 24
Peak memory 207320 kb
Host smart-50570a4f-9683-4c69-9ad3-f227dd9e6a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36998
18125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3699818125
Directory /workspace/6.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/6.usbdev_disconnected.239388621
Short name T1181
Test name
Test status
Simulation time 162525492 ps
CPU time 0.87 seconds
Started Aug 05 05:34:15 PM PDT 24
Finished Aug 05 05:34:16 PM PDT 24
Peak memory 207332 kb
Host smart-a6e9128f-8dc3-4149-908f-3d532671055a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23938
8621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.239388621
Directory /workspace/6.usbdev_disconnected/latest


Test location /workspace/coverage/default/6.usbdev_enable.1258647701
Short name T2362
Test name
Test status
Simulation time 97710779 ps
CPU time 0.77 seconds
Started Aug 05 05:34:09 PM PDT 24
Finished Aug 05 05:34:10 PM PDT 24
Peak memory 207312 kb
Host smart-c9f03580-208c-42f2-b005-274002cd2867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12586
47701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1258647701
Directory /workspace/6.usbdev_enable/latest


Test location /workspace/coverage/default/6.usbdev_endpoint_access.3812811790
Short name T1848
Test name
Test status
Simulation time 909743084 ps
CPU time 2.48 seconds
Started Aug 05 05:34:15 PM PDT 24
Finished Aug 05 05:34:18 PM PDT 24
Peak memory 207580 kb
Host smart-99c4db2d-2ad5-4755-bba1-dffd02716e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38128
11790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3812811790
Directory /workspace/6.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/6.usbdev_fifo_rst.2986638781
Short name T2434
Test name
Test status
Simulation time 310247716 ps
CPU time 2.07 seconds
Started Aug 05 05:34:13 PM PDT 24
Finished Aug 05 05:34:15 PM PDT 24
Peak memory 207444 kb
Host smart-84aeca0c-49e8-4de5-acf1-4f702af497ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29866
38781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2986638781
Directory /workspace/6.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/6.usbdev_in_iso.3908596884
Short name T3058
Test name
Test status
Simulation time 206236093 ps
CPU time 1.1 seconds
Started Aug 05 05:34:11 PM PDT 24
Finished Aug 05 05:34:12 PM PDT 24
Peak memory 215760 kb
Host smart-5b337701-7493-472e-a8ad-9efe1d53f9ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3908596884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3908596884
Directory /workspace/6.usbdev_in_iso/latest


Test location /workspace/coverage/default/6.usbdev_in_stall.1362640867
Short name T1239
Test name
Test status
Simulation time 146763153 ps
CPU time 0.82 seconds
Started Aug 05 05:34:09 PM PDT 24
Finished Aug 05 05:34:10 PM PDT 24
Peak memory 207320 kb
Host smart-c1a37caf-cb02-4320-9bd2-c462c3073ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13626
40867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1362640867
Directory /workspace/6.usbdev_in_stall/latest


Test location /workspace/coverage/default/6.usbdev_in_trans.1317640588
Short name T590
Test name
Test status
Simulation time 198246834 ps
CPU time 0.95 seconds
Started Aug 05 05:34:11 PM PDT 24
Finished Aug 05 05:34:12 PM PDT 24
Peak memory 207324 kb
Host smart-1a00965d-1b91-4dff-aec4-43079afa226a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13176
40588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1317640588
Directory /workspace/6.usbdev_in_trans/latest


Test location /workspace/coverage/default/6.usbdev_invalid_sync.1645645229
Short name T2378
Test name
Test status
Simulation time 3967495694 ps
CPU time 29.99 seconds
Started Aug 05 05:34:10 PM PDT 24
Finished Aug 05 05:34:40 PM PDT 24
Peak memory 215916 kb
Host smart-3e5a5f37-7eea-40e2-bf77-09030fa2cd3d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1645645229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.1645645229
Directory /workspace/6.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/6.usbdev_iso_retraction.3745099040
Short name T1573
Test name
Test status
Simulation time 12311399025 ps
CPU time 154.3 seconds
Started Aug 05 05:34:10 PM PDT 24
Finished Aug 05 05:36:44 PM PDT 24
Peak memory 207540 kb
Host smart-4d1c4392-1c4b-4529-8071-166a251656ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3745099040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.3745099040
Directory /workspace/6.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/6.usbdev_link_in_err.2999603401
Short name T704
Test name
Test status
Simulation time 251841211 ps
CPU time 0.95 seconds
Started Aug 05 05:34:12 PM PDT 24
Finished Aug 05 05:34:13 PM PDT 24
Peak memory 207320 kb
Host smart-329a8dbc-5eb6-49bd-92db-bf9425ab3a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29996
03401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2999603401
Directory /workspace/6.usbdev_link_in_err/latest


Test location /workspace/coverage/default/6.usbdev_link_suspend.3491905142
Short name T2072
Test name
Test status
Simulation time 4198503477 ps
CPU time 6.05 seconds
Started Aug 05 05:34:10 PM PDT 24
Finished Aug 05 05:34:16 PM PDT 24
Peak memory 215824 kb
Host smart-3ea9fbb3-c7a7-46d2-8c7d-2ade28736929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34919
05142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3491905142
Directory /workspace/6.usbdev_link_suspend/latest


Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.100416802
Short name T2110
Test name
Test status
Simulation time 4852346043 ps
CPU time 47.46 seconds
Started Aug 05 05:34:09 PM PDT 24
Finished Aug 05 05:34:56 PM PDT 24
Peak memory 223940 kb
Host smart-e42523f4-8aec-4d29-bf5e-293c512d3cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10041
6802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.100416802
Directory /workspace/6.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3646966846
Short name T3053
Test name
Test status
Simulation time 2218009535 ps
CPU time 21.53 seconds
Started Aug 05 05:34:11 PM PDT 24
Finished Aug 05 05:34:32 PM PDT 24
Peak memory 217248 kb
Host smart-836b89b2-3f51-499c-9cd8-fa49aef09f7f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3646966846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3646966846
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2645173883
Short name T2893
Test name
Test status
Simulation time 256853294 ps
CPU time 0.98 seconds
Started Aug 05 05:34:13 PM PDT 24
Finished Aug 05 05:34:15 PM PDT 24
Peak memory 207352 kb
Host smart-61961bbe-a9a5-4025-9f29-9e4b15f3c849
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2645173883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2645173883
Directory /workspace/6.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3966199799
Short name T3016
Test name
Test status
Simulation time 192996979 ps
CPU time 0.9 seconds
Started Aug 05 05:34:11 PM PDT 24
Finished Aug 05 05:34:13 PM PDT 24
Peak memory 207376 kb
Host smart-ab863d5b-f8de-46ba-9654-f02583ac7129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39661
99799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3966199799
Directory /workspace/6.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.276645665
Short name T1805
Test name
Test status
Simulation time 3285801292 ps
CPU time 25.79 seconds
Started Aug 05 05:34:10 PM PDT 24
Finished Aug 05 05:34:36 PM PDT 24
Peak memory 224052 kb
Host smart-9a54d4a7-ffad-4a0e-ab8c-10df4f81946b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27664
5665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.276645665
Directory /workspace/6.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3763624289
Short name T2129
Test name
Test status
Simulation time 1900279507 ps
CPU time 19.92 seconds
Started Aug 05 05:34:10 PM PDT 24
Finished Aug 05 05:34:30 PM PDT 24
Peak memory 217292 kb
Host smart-0742151b-d575-4581-a6ad-8b8b20efa840
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3763624289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3763624289
Directory /workspace/6.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.2583104342
Short name T2136
Test name
Test status
Simulation time 2141689726 ps
CPU time 56.56 seconds
Started Aug 05 05:34:08 PM PDT 24
Finished Aug 05 05:35:05 PM PDT 24
Peak memory 215764 kb
Host smart-e1fffb74-635f-46ca-9878-f91e10d00212
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2583104342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.2583104342
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.208881762
Short name T2894
Test name
Test status
Simulation time 145267495 ps
CPU time 0.89 seconds
Started Aug 05 05:34:13 PM PDT 24
Finished Aug 05 05:34:14 PM PDT 24
Peak memory 207376 kb
Host smart-758d5e87-7142-46ae-af00-df72de156e17
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=208881762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.208881762
Directory /workspace/6.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.102605397
Short name T2438
Test name
Test status
Simulation time 143691071 ps
CPU time 0.81 seconds
Started Aug 05 05:34:09 PM PDT 24
Finished Aug 05 05:34:10 PM PDT 24
Peak memory 207352 kb
Host smart-4e8f478b-b2fa-4163-a630-745703479de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10260
5397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.102605397
Directory /workspace/6.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/6.usbdev_nak_trans.518727716
Short name T125
Test name
Test status
Simulation time 160482323 ps
CPU time 0.87 seconds
Started Aug 05 05:34:14 PM PDT 24
Finished Aug 05 05:34:15 PM PDT 24
Peak memory 207348 kb
Host smart-88768b2e-0557-47c2-84f8-abfb784ba908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51872
7716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.518727716
Directory /workspace/6.usbdev_nak_trans/latest


Test location /workspace/coverage/default/6.usbdev_out_iso.4021652390
Short name T1419
Test name
Test status
Simulation time 168900714 ps
CPU time 0.93 seconds
Started Aug 05 05:34:12 PM PDT 24
Finished Aug 05 05:34:13 PM PDT 24
Peak memory 207320 kb
Host smart-fff0ca71-1253-45df-9448-86e0615ea1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40216
52390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.4021652390
Directory /workspace/6.usbdev_out_iso/latest


Test location /workspace/coverage/default/6.usbdev_out_stall.1563897021
Short name T1308
Test name
Test status
Simulation time 182746936 ps
CPU time 0.94 seconds
Started Aug 05 05:34:23 PM PDT 24
Finished Aug 05 05:34:24 PM PDT 24
Peak memory 207392 kb
Host smart-5cd3495f-9bdf-4097-8aa6-de4bc14f75af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15638
97021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1563897021
Directory /workspace/6.usbdev_out_stall/latest


Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2620108028
Short name T3036
Test name
Test status
Simulation time 168151727 ps
CPU time 0.85 seconds
Started Aug 05 05:34:18 PM PDT 24
Finished Aug 05 05:34:19 PM PDT 24
Peak memory 207376 kb
Host smart-ef95612e-20db-475e-ba16-66c9a9e2b5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26201
08028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2620108028
Directory /workspace/6.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3257148302
Short name T3075
Test name
Test status
Simulation time 187067815 ps
CPU time 0.94 seconds
Started Aug 05 05:34:18 PM PDT 24
Finished Aug 05 05:34:19 PM PDT 24
Peak memory 207272 kb
Host smart-b1acb2cd-4728-4698-bf35-15375c89e3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32571
48302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3257148302
Directory /workspace/6.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.3422741792
Short name T2653
Test name
Test status
Simulation time 193521962 ps
CPU time 0.95 seconds
Started Aug 05 05:34:18 PM PDT 24
Finished Aug 05 05:34:19 PM PDT 24
Peak memory 207400 kb
Host smart-8d012127-0adc-45b5-ad0d-b68e533bec33
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3422741792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.3422741792
Directory /workspace/6.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.515753245
Short name T1360
Test name
Test status
Simulation time 139137927 ps
CPU time 0.77 seconds
Started Aug 05 05:34:17 PM PDT 24
Finished Aug 05 05:34:18 PM PDT 24
Peak memory 207268 kb
Host smart-43eaa7a3-cc74-4d78-b7f5-4f6b83dc31de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51575
3245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.515753245
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3622341043
Short name T1309
Test name
Test status
Simulation time 36837765 ps
CPU time 0.68 seconds
Started Aug 05 05:34:19 PM PDT 24
Finished Aug 05 05:34:20 PM PDT 24
Peak memory 207312 kb
Host smart-ae7a4c61-77b8-4c6f-b60d-1842f6bea5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36223
41043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3622341043
Directory /workspace/6.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3857017301
Short name T246
Test name
Test status
Simulation time 5344012040 ps
CPU time 14.03 seconds
Started Aug 05 05:34:19 PM PDT 24
Finished Aug 05 05:34:33 PM PDT 24
Peak memory 215732 kb
Host smart-0f12a5f2-7cbf-46fa-8eff-8fe2fe0144d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38570
17301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3857017301
Directory /workspace/6.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/6.usbdev_pkt_received.3251458884
Short name T3021
Test name
Test status
Simulation time 177115891 ps
CPU time 0.94 seconds
Started Aug 05 05:34:18 PM PDT 24
Finished Aug 05 05:34:19 PM PDT 24
Peak memory 207364 kb
Host smart-ef6a80b0-6333-411f-b21c-5e43c986c295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32514
58884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3251458884
Directory /workspace/6.usbdev_pkt_received/latest


Test location /workspace/coverage/default/6.usbdev_pkt_sent.655522100
Short name T2926
Test name
Test status
Simulation time 186603724 ps
CPU time 0.93 seconds
Started Aug 05 05:34:19 PM PDT 24
Finished Aug 05 05:34:20 PM PDT 24
Peak memory 207344 kb
Host smart-06078753-384b-41af-9679-bf5812fad1d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65552
2100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.655522100
Directory /workspace/6.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.775345181
Short name T2969
Test name
Test status
Simulation time 6178160822 ps
CPU time 72.11 seconds
Started Aug 05 05:34:19 PM PDT 24
Finished Aug 05 05:35:31 PM PDT 24
Peak memory 218820 kb
Host smart-53e5884b-58a3-496f-861d-b9ce5228508d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=775345181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.775345181
Directory /workspace/6.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/6.usbdev_rand_suspends.1472427355
Short name T1905
Test name
Test status
Simulation time 10159400268 ps
CPU time 202.22 seconds
Started Aug 05 05:34:17 PM PDT 24
Finished Aug 05 05:37:39 PM PDT 24
Peak memory 218380 kb
Host smart-ab168ee8-1f07-4546-bf97-d9ee50ba9f1e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472427355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1472427355
Directory /workspace/6.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.3651756099
Short name T2515
Test name
Test status
Simulation time 206810830 ps
CPU time 1 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:21 PM PDT 24
Peak memory 207368 kb
Host smart-7f6d394c-87be-45d3-9de3-458eb3ad447b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36517
56099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.3651756099
Directory /workspace/6.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1938211521
Short name T997
Test name
Test status
Simulation time 162856406 ps
CPU time 0.85 seconds
Started Aug 05 05:34:16 PM PDT 24
Finished Aug 05 05:34:17 PM PDT 24
Peak memory 207268 kb
Host smart-eada0df8-86f1-410f-9d82-2308fbfbf5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19382
11521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1938211521
Directory /workspace/6.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/6.usbdev_resume_link_active.1408714369
Short name T2906
Test name
Test status
Simulation time 20178830337 ps
CPU time 22.65 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:43 PM PDT 24
Peak memory 207404 kb
Host smart-8847dd0c-d24f-449a-864c-9383e138e36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14087
14369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.1408714369
Directory /workspace/6.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/6.usbdev_rx_crc_err.225971708
Short name T1421
Test name
Test status
Simulation time 199394284 ps
CPU time 0.88 seconds
Started Aug 05 05:34:21 PM PDT 24
Finished Aug 05 05:34:21 PM PDT 24
Peak memory 207332 kb
Host smart-327f6555-f2d7-4e8c-b97e-5be7b7c5c591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22597
1708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.225971708
Directory /workspace/6.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/6.usbdev_rx_full.1762433521
Short name T3068
Test name
Test status
Simulation time 391758838 ps
CPU time 1.34 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:21 PM PDT 24
Peak memory 207368 kb
Host smart-f1900179-65c6-47de-ba60-b15fb0f0a068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17624
33521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.1762433521
Directory /workspace/6.usbdev_rx_full/latest


Test location /workspace/coverage/default/6.usbdev_setup_stage.3158140724
Short name T2742
Test name
Test status
Simulation time 160401310 ps
CPU time 0.87 seconds
Started Aug 05 05:34:17 PM PDT 24
Finished Aug 05 05:34:18 PM PDT 24
Peak memory 207572 kb
Host smart-7b96e27d-883f-47a2-b492-12a1a23b30cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31581
40724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3158140724
Directory /workspace/6.usbdev_setup_stage/latest


Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2280210206
Short name T2959
Test name
Test status
Simulation time 145895883 ps
CPU time 0.82 seconds
Started Aug 05 05:34:18 PM PDT 24
Finished Aug 05 05:34:19 PM PDT 24
Peak memory 207400 kb
Host smart-bdb65f85-2aae-4f79-9e8f-d7e56f3b0446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22802
10206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2280210206
Directory /workspace/6.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/6.usbdev_smoke.1944032995
Short name T2721
Test name
Test status
Simulation time 253335064 ps
CPU time 1.03 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:21 PM PDT 24
Peak memory 207368 kb
Host smart-62b83f86-db22-4aa2-bdbe-aee32c1f3d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19440
32995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1944032995
Directory /workspace/6.usbdev_smoke/latest


Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3365668469
Short name T3004
Test name
Test status
Simulation time 1976798055 ps
CPU time 15.71 seconds
Started Aug 05 05:34:23 PM PDT 24
Finished Aug 05 05:34:38 PM PDT 24
Peak memory 223900 kb
Host smart-f89ca422-2a6b-4c13-a6a6-b64573b0958a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3365668469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3365668469
Directory /workspace/6.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3964279071
Short name T2692
Test name
Test status
Simulation time 175614589 ps
CPU time 0.89 seconds
Started Aug 05 05:34:17 PM PDT 24
Finished Aug 05 05:34:18 PM PDT 24
Peak memory 207496 kb
Host smart-b3a5ca07-0201-49f6-9a22-bef37e2f1229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39642
79071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3964279071
Directory /workspace/6.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/6.usbdev_stall_trans.1602751461
Short name T1884
Test name
Test status
Simulation time 196059469 ps
CPU time 0.89 seconds
Started Aug 05 05:34:18 PM PDT 24
Finished Aug 05 05:34:19 PM PDT 24
Peak memory 207416 kb
Host smart-c681a8df-3669-4f8f-8775-32f500cc2034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16027
51461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1602751461
Directory /workspace/6.usbdev_stall_trans/latest


Test location /workspace/coverage/default/6.usbdev_stream_len_max.427504087
Short name T2830
Test name
Test status
Simulation time 390789224 ps
CPU time 1.41 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:21 PM PDT 24
Peak memory 207308 kb
Host smart-5645f0fa-977f-4c1c-9151-16a66c71ef65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42750
4087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.427504087
Directory /workspace/6.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/6.usbdev_streaming_out.1965855098
Short name T1257
Test name
Test status
Simulation time 2745164548 ps
CPU time 27.91 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:48 PM PDT 24
Peak memory 215824 kb
Host smart-5ead5ab4-c341-4d91-9b93-678630e11198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19658
55098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.1965855098
Directory /workspace/6.usbdev_streaming_out/latest


Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.1991038566
Short name T2332
Test name
Test status
Simulation time 732624252 ps
CPU time 15.06 seconds
Started Aug 05 05:34:10 PM PDT 24
Finished Aug 05 05:34:26 PM PDT 24
Peak memory 207444 kb
Host smart-e08c2d2b-a5af-4e9e-b32b-83c2fb879663
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991038566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.1991038566
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/60.usbdev_endpoint_types.2586155774
Short name T477
Test name
Test status
Simulation time 592583892 ps
CPU time 1.58 seconds
Started Aug 05 05:40:28 PM PDT 24
Finished Aug 05 05:40:30 PM PDT 24
Peak memory 207344 kb
Host smart-54c7f206-f60d-40dc-9554-cb83619315c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2586155774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.2586155774
Directory /workspace/60.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/61.usbdev_endpoint_types.3930874235
Short name T392
Test name
Test status
Simulation time 980496409 ps
CPU time 1.92 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 207224 kb
Host smart-4df9cf89-277e-4a76-98a8-e03b1d0f19e1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3930874235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.3930874235
Directory /workspace/61.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/62.usbdev_endpoint_types.1355935261
Short name T2828
Test name
Test status
Simulation time 381666883 ps
CPU time 1.28 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207272 kb
Host smart-529f5860-0641-4090-bf34-6aa9bc639258
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1355935261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.1355935261
Directory /workspace/62.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/63.usbdev_endpoint_types.990243936
Short name T401
Test name
Test status
Simulation time 339069620 ps
CPU time 1.15 seconds
Started Aug 05 05:40:33 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207316 kb
Host smart-750c9814-a0f4-405f-b5bf-59389312a3af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=990243936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.990243936
Directory /workspace/63.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/65.usbdev_endpoint_types.906390152
Short name T474
Test name
Test status
Simulation time 631300210 ps
CPU time 1.61 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207272 kb
Host smart-6aac779a-2f2d-420a-9856-fa1c2ccdc213
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=906390152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.906390152
Directory /workspace/65.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/66.usbdev_endpoint_types.2500083022
Short name T388
Test name
Test status
Simulation time 366622861 ps
CPU time 1.15 seconds
Started Aug 05 05:40:29 PM PDT 24
Finished Aug 05 05:40:31 PM PDT 24
Peak memory 207340 kb
Host smart-da9ac9c6-217b-4f2c-893b-c62644d7d86e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2500083022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.2500083022
Directory /workspace/66.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/67.usbdev_endpoint_types.2170403690
Short name T369
Test name
Test status
Simulation time 580301590 ps
CPU time 1.48 seconds
Started Aug 05 05:40:48 PM PDT 24
Finished Aug 05 05:40:49 PM PDT 24
Peak memory 207244 kb
Host smart-870dbf48-f2fb-4716-b848-3f9c97ebfcc7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2170403690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.2170403690
Directory /workspace/67.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/68.usbdev_endpoint_types.3523984680
Short name T1683
Test name
Test status
Simulation time 670829011 ps
CPU time 1.48 seconds
Started Aug 05 05:40:41 PM PDT 24
Finished Aug 05 05:40:42 PM PDT 24
Peak memory 207276 kb
Host smart-31a03368-ae9d-4888-bbcd-b3ab8ba96569
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3523984680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.3523984680
Directory /workspace/68.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/69.usbdev_endpoint_types.2959106617
Short name T1342
Test name
Test status
Simulation time 162038300 ps
CPU time 0.84 seconds
Started Aug 05 05:40:51 PM PDT 24
Finished Aug 05 05:40:52 PM PDT 24
Peak memory 207244 kb
Host smart-8a47fda6-2322-46e2-9d04-15e4e0c6f700
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2959106617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.2959106617
Directory /workspace/69.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/7.usbdev_alert_test.1056055748
Short name T1102
Test name
Test status
Simulation time 37395013 ps
CPU time 0.68 seconds
Started Aug 05 05:34:32 PM PDT 24
Finished Aug 05 05:34:33 PM PDT 24
Peak memory 207360 kb
Host smart-1200b516-1c20-4072-bd51-b2be7e3ea136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1056055748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1056055748
Directory /workspace/7.usbdev_alert_test/latest


Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.4125135303
Short name T1466
Test name
Test status
Simulation time 5938054919 ps
CPU time 7.41 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:27 PM PDT 24
Peak memory 215792 kb
Host smart-8ecb3692-41b9-4573-b469-2eb135047c39
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125135303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.4125135303
Directory /workspace/7.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1399285796
Short name T818
Test name
Test status
Simulation time 14715117381 ps
CPU time 17.56 seconds
Started Aug 05 05:34:18 PM PDT 24
Finished Aug 05 05:34:35 PM PDT 24
Peak memory 215696 kb
Host smart-41e32f9f-d092-42bf-aa19-772c12c4ad93
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399285796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1399285796
Directory /workspace/7.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3500770819
Short name T2276
Test name
Test status
Simulation time 29476401384 ps
CPU time 33.6 seconds
Started Aug 05 05:34:21 PM PDT 24
Finished Aug 05 05:34:54 PM PDT 24
Peak memory 207528 kb
Host smart-b9126c8e-061b-493f-bb22-b0b4f95c15b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500770819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.3500770819
Directory /workspace/7.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/7.usbdev_av_buffer.2281661423
Short name T1183
Test name
Test status
Simulation time 174956687 ps
CPU time 0.94 seconds
Started Aug 05 05:34:19 PM PDT 24
Finished Aug 05 05:34:21 PM PDT 24
Peak memory 207340 kb
Host smart-e83930d5-541b-491d-ad92-3ac389e772b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22816
61423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2281661423
Directory /workspace/7.usbdev_av_buffer/latest


Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3337925687
Short name T768
Test name
Test status
Simulation time 163261255 ps
CPU time 0.87 seconds
Started Aug 05 05:34:18 PM PDT 24
Finished Aug 05 05:34:19 PM PDT 24
Peak memory 207356 kb
Host smart-182fd30a-6f83-49ac-aeed-4706986a0e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33379
25687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3337925687
Directory /workspace/7.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.2552369909
Short name T1818
Test name
Test status
Simulation time 464395078 ps
CPU time 1.68 seconds
Started Aug 05 05:34:21 PM PDT 24
Finished Aug 05 05:34:22 PM PDT 24
Peak memory 207340 kb
Host smart-7f264b6d-fd3c-4062-b10b-8a3eca602c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25523
69909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2552369909
Directory /workspace/7.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3057211565
Short name T2073
Test name
Test status
Simulation time 458020556 ps
CPU time 1.38 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:21 PM PDT 24
Peak memory 207332 kb
Host smart-55deba08-83d7-48f7-9cb0-e8a97adaf4a6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3057211565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3057211565
Directory /workspace/7.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/7.usbdev_device_address.1392222850
Short name T180
Test name
Test status
Simulation time 39258260857 ps
CPU time 59.68 seconds
Started Aug 05 05:34:19 PM PDT 24
Finished Aug 05 05:35:19 PM PDT 24
Peak memory 207664 kb
Host smart-7666cc3e-a8c1-4855-b3c7-81c36a777283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13922
22850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.1392222850
Directory /workspace/7.usbdev_device_address/latest


Test location /workspace/coverage/default/7.usbdev_device_timeout.4006703553
Short name T2104
Test name
Test status
Simulation time 3417040589 ps
CPU time 32.58 seconds
Started Aug 05 05:34:21 PM PDT 24
Finished Aug 05 05:34:54 PM PDT 24
Peak memory 207588 kb
Host smart-19b250f6-3ddb-4f79-9456-c25bc5757e56
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006703553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.4006703553
Directory /workspace/7.usbdev_device_timeout/latest


Test location /workspace/coverage/default/7.usbdev_disable_endpoint.933992497
Short name T2028
Test name
Test status
Simulation time 824722519 ps
CPU time 1.86 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:22 PM PDT 24
Peak memory 207216 kb
Host smart-36c70fea-dfa6-4aba-9a9f-47f9be670478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93399
2497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.933992497
Directory /workspace/7.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/7.usbdev_disconnected.2698990189
Short name T1980
Test name
Test status
Simulation time 134460342 ps
CPU time 0.86 seconds
Started Aug 05 05:34:22 PM PDT 24
Finished Aug 05 05:34:23 PM PDT 24
Peak memory 207316 kb
Host smart-00e3ab02-ba01-4a63-b45b-9de0dad55baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26989
90189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2698990189
Directory /workspace/7.usbdev_disconnected/latest


Test location /workspace/coverage/default/7.usbdev_enable.2437393925
Short name T586
Test name
Test status
Simulation time 44717476 ps
CPU time 0.71 seconds
Started Aug 05 05:34:21 PM PDT 24
Finished Aug 05 05:34:21 PM PDT 24
Peak memory 207300 kb
Host smart-12dae816-e500-4adf-9aa9-73717739b6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24373
93925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2437393925
Directory /workspace/7.usbdev_enable/latest


Test location /workspace/coverage/default/7.usbdev_endpoint_access.4085565783
Short name T508
Test name
Test status
Simulation time 828678380 ps
CPU time 2.09 seconds
Started Aug 05 05:34:22 PM PDT 24
Finished Aug 05 05:34:25 PM PDT 24
Peak memory 207552 kb
Host smart-24ed5f24-2ac2-4863-8062-7ebf6a888d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40855
65783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.4085565783
Directory /workspace/7.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/7.usbdev_endpoint_types.1154078255
Short name T716
Test name
Test status
Simulation time 243264159 ps
CPU time 0.98 seconds
Started Aug 05 05:34:22 PM PDT 24
Finished Aug 05 05:34:23 PM PDT 24
Peak memory 207344 kb
Host smart-93125270-b58e-4b8b-ab29-2fafbf3995d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1154078255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.1154078255
Directory /workspace/7.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/7.usbdev_fifo_rst.2321611461
Short name T1899
Test name
Test status
Simulation time 171526522 ps
CPU time 2.23 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:22 PM PDT 24
Peak memory 207496 kb
Host smart-41faec59-309a-4166-8a43-2f4a421cc498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23216
11461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2321611461
Directory /workspace/7.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/7.usbdev_in_iso.3304524381
Short name T1526
Test name
Test status
Simulation time 189116428 ps
CPU time 1.02 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:21 PM PDT 24
Peak memory 207548 kb
Host smart-89c59e6f-a295-436a-87d0-d6b6b9d4e7d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3304524381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3304524381
Directory /workspace/7.usbdev_in_iso/latest


Test location /workspace/coverage/default/7.usbdev_in_stall.1937635500
Short name T97
Test name
Test status
Simulation time 169162199 ps
CPU time 0.88 seconds
Started Aug 05 05:34:22 PM PDT 24
Finished Aug 05 05:34:22 PM PDT 24
Peak memory 207344 kb
Host smart-ea48ed52-490f-473b-af23-b06d33fd9c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19376
35500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1937635500
Directory /workspace/7.usbdev_in_stall/latest


Test location /workspace/coverage/default/7.usbdev_in_trans.2616806695
Short name T1596
Test name
Test status
Simulation time 248828880 ps
CPU time 1.16 seconds
Started Aug 05 05:34:20 PM PDT 24
Finished Aug 05 05:34:21 PM PDT 24
Peak memory 207312 kb
Host smart-c898e545-1b04-4311-ba6a-4a93f2b1957f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26168
06695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2616806695
Directory /workspace/7.usbdev_in_trans/latest


Test location /workspace/coverage/default/7.usbdev_invalid_sync.3514667311
Short name T3121
Test name
Test status
Simulation time 4443031656 ps
CPU time 37.17 seconds
Started Aug 05 05:34:22 PM PDT 24
Finished Aug 05 05:34:59 PM PDT 24
Peak memory 224008 kb
Host smart-0ad45e1c-e257-4cca-9329-4bc52301c806
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3514667311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.3514667311
Directory /workspace/7.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/7.usbdev_iso_retraction.3047189909
Short name T2608
Test name
Test status
Simulation time 9753733972 ps
CPU time 62.54 seconds
Started Aug 05 05:34:24 PM PDT 24
Finished Aug 05 05:35:27 PM PDT 24
Peak memory 207676 kb
Host smart-3df971cb-60bd-43a8-86ec-e73ffcc1fa63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3047189909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.3047189909
Directory /workspace/7.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/7.usbdev_link_in_err.1519436870
Short name T3119
Test name
Test status
Simulation time 219293166 ps
CPU time 0.96 seconds
Started Aug 05 05:34:27 PM PDT 24
Finished Aug 05 05:34:28 PM PDT 24
Peak memory 207268 kb
Host smart-a4edb19c-8388-438a-91ce-94481dc6c3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194
36870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1519436870
Directory /workspace/7.usbdev_link_in_err/latest


Test location /workspace/coverage/default/7.usbdev_link_resume.846697931
Short name T1814
Test name
Test status
Simulation time 31743049194 ps
CPU time 48.16 seconds
Started Aug 05 05:34:28 PM PDT 24
Finished Aug 05 05:35:17 PM PDT 24
Peak memory 207684 kb
Host smart-9ec4ba7e-f35e-4760-886b-51c9cb99a304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84669
7931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.846697931
Directory /workspace/7.usbdev_link_resume/latest


Test location /workspace/coverage/default/7.usbdev_link_suspend.3600680489
Short name T1353
Test name
Test status
Simulation time 8626346196 ps
CPU time 10.65 seconds
Started Aug 05 05:34:28 PM PDT 24
Finished Aug 05 05:34:39 PM PDT 24
Peak memory 207660 kb
Host smart-b7b5d952-e301-4699-88bc-ea42ceaebb18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36006
80489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3600680489
Directory /workspace/7.usbdev_link_suspend/latest


Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.3979014915
Short name T2715
Test name
Test status
Simulation time 4528816868 ps
CPU time 34.93 seconds
Started Aug 05 05:34:25 PM PDT 24
Finished Aug 05 05:35:00 PM PDT 24
Peak memory 215852 kb
Host smart-d6c494c2-70ec-47bb-b89e-10d0831c104d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39790
14915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3979014915
Directory /workspace/7.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.4286039767
Short name T2651
Test name
Test status
Simulation time 3840263994 ps
CPU time 31.92 seconds
Started Aug 05 05:34:31 PM PDT 24
Finished Aug 05 05:35:03 PM PDT 24
Peak memory 217520 kb
Host smart-f9972687-2ca6-4398-9b20-20df89f999ef
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4286039767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.4286039767
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.1519592481
Short name T2747
Test name
Test status
Simulation time 313125047 ps
CPU time 1.12 seconds
Started Aug 05 05:34:24 PM PDT 24
Finished Aug 05 05:34:26 PM PDT 24
Peak memory 207368 kb
Host smart-f446228f-29f7-4f83-90f8-bb7cd02c6a36
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1519592481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.1519592481
Directory /workspace/7.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2007020646
Short name T978
Test name
Test status
Simulation time 193234736 ps
CPU time 0.99 seconds
Started Aug 05 05:34:30 PM PDT 24
Finished Aug 05 05:34:31 PM PDT 24
Peak memory 207300 kb
Host smart-c2c81e8f-3d93-4b44-b54e-9725561ebe08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20070
20646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2007020646
Directory /workspace/7.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.1152082066
Short name T1264
Test name
Test status
Simulation time 2591334757 ps
CPU time 24.02 seconds
Started Aug 05 05:34:30 PM PDT 24
Finished Aug 05 05:34:55 PM PDT 24
Peak memory 223992 kb
Host smart-bc4aa659-2797-486c-a3e7-473d1f0188bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11520
82066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.1152082066
Directory /workspace/7.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1981329625
Short name T118
Test name
Test status
Simulation time 3311085277 ps
CPU time 28.34 seconds
Started Aug 05 05:34:27 PM PDT 24
Finished Aug 05 05:34:56 PM PDT 24
Peak memory 207668 kb
Host smart-c43c66b1-cf2c-429d-898d-3a61d99326e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1981329625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1981329625
Directory /workspace/7.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.2485915789
Short name T2760
Test name
Test status
Simulation time 2498217943 ps
CPU time 19.31 seconds
Started Aug 05 05:34:25 PM PDT 24
Finished Aug 05 05:34:44 PM PDT 24
Peak memory 215812 kb
Host smart-59cf35e4-f5f8-4d93-b822-13616f0c6612
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2485915789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.2485915789
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.2640915601
Short name T573
Test name
Test status
Simulation time 169356878 ps
CPU time 0.88 seconds
Started Aug 05 05:34:24 PM PDT 24
Finished Aug 05 05:34:25 PM PDT 24
Peak memory 207252 kb
Host smart-ad2b0706-cbbb-477d-bc8e-c0812dda9307
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2640915601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.2640915601
Directory /workspace/7.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.11861254
Short name T2389
Test name
Test status
Simulation time 158548939 ps
CPU time 0.89 seconds
Started Aug 05 05:34:29 PM PDT 24
Finished Aug 05 05:34:30 PM PDT 24
Peak memory 207356 kb
Host smart-22bb7a92-9dbe-4de4-b089-2050b243b995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11861
254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.11861254
Directory /workspace/7.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/7.usbdev_nak_trans.717727269
Short name T2122
Test name
Test status
Simulation time 188394633 ps
CPU time 0.9 seconds
Started Aug 05 05:34:25 PM PDT 24
Finished Aug 05 05:34:26 PM PDT 24
Peak memory 207408 kb
Host smart-9e86a5f1-c2ab-4c39-8a9c-9f1174b48032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71772
7269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.717727269
Directory /workspace/7.usbdev_nak_trans/latest


Test location /workspace/coverage/default/7.usbdev_out_iso.3581450920
Short name T2520
Test name
Test status
Simulation time 171930786 ps
CPU time 0.96 seconds
Started Aug 05 05:34:27 PM PDT 24
Finished Aug 05 05:34:28 PM PDT 24
Peak memory 207268 kb
Host smart-0792f52d-6345-4c09-a14a-77698ae63097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35814
50920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.3581450920
Directory /workspace/7.usbdev_out_iso/latest


Test location /workspace/coverage/default/7.usbdev_out_stall.3350194476
Short name T2873
Test name
Test status
Simulation time 178130247 ps
CPU time 0.9 seconds
Started Aug 05 05:34:26 PM PDT 24
Finished Aug 05 05:34:27 PM PDT 24
Peak memory 207352 kb
Host smart-f6e57bce-be50-49ea-99da-74ce166ca926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33501
94476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3350194476
Directory /workspace/7.usbdev_out_stall/latest


Test location /workspace/coverage/default/7.usbdev_out_trans_nak.283239212
Short name T1159
Test name
Test status
Simulation time 187757363 ps
CPU time 0.96 seconds
Started Aug 05 05:34:25 PM PDT 24
Finished Aug 05 05:34:26 PM PDT 24
Peak memory 207324 kb
Host smart-42d16a90-a881-4eca-9881-71607ac77d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28323
9212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.283239212
Directory /workspace/7.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3665997608
Short name T2958
Test name
Test status
Simulation time 149191097 ps
CPU time 0.84 seconds
Started Aug 05 05:34:25 PM PDT 24
Finished Aug 05 05:34:26 PM PDT 24
Peak memory 207324 kb
Host smart-bda94582-1d40-4ec8-a0e3-4a0042f08d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36659
97608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3665997608
Directory /workspace/7.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1361368006
Short name T2778
Test name
Test status
Simulation time 239479575 ps
CPU time 1.1 seconds
Started Aug 05 05:34:27 PM PDT 24
Finished Aug 05 05:34:28 PM PDT 24
Peak memory 207272 kb
Host smart-b4b8453e-1d78-456f-9265-3f7bc5ffc4c1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1361368006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1361368006
Directory /workspace/7.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3520046819
Short name T2934
Test name
Test status
Simulation time 141133251 ps
CPU time 0.83 seconds
Started Aug 05 05:34:34 PM PDT 24
Finished Aug 05 05:34:35 PM PDT 24
Peak memory 207344 kb
Host smart-d882efe8-2e4f-46f9-9b70-f13ca2bc25b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35200
46819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3520046819
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2631138696
Short name T2752
Test name
Test status
Simulation time 48792426 ps
CPU time 0.74 seconds
Started Aug 05 05:34:28 PM PDT 24
Finished Aug 05 05:34:29 PM PDT 24
Peak memory 207316 kb
Host smart-94f98732-c9fb-416f-85c8-ed5922ab9f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26311
38696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2631138696
Directory /workspace/7.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3843169975
Short name T1396
Test name
Test status
Simulation time 22786278485 ps
CPU time 61.31 seconds
Started Aug 05 05:34:26 PM PDT 24
Finished Aug 05 05:35:28 PM PDT 24
Peak memory 224020 kb
Host smart-56da59ce-d60f-468f-a366-c110fabc810b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38431
69975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3843169975
Directory /workspace/7.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/7.usbdev_pkt_received.581909685
Short name T610
Test name
Test status
Simulation time 175822323 ps
CPU time 0.87 seconds
Started Aug 05 05:34:25 PM PDT 24
Finished Aug 05 05:34:26 PM PDT 24
Peak memory 207396 kb
Host smart-3a1d8fd1-b09f-4071-af4b-f8ca6c29db72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58190
9685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.581909685
Directory /workspace/7.usbdev_pkt_received/latest


Test location /workspace/coverage/default/7.usbdev_pkt_sent.932095049
Short name T1347
Test name
Test status
Simulation time 239367837 ps
CPU time 0.98 seconds
Started Aug 05 05:34:26 PM PDT 24
Finished Aug 05 05:34:27 PM PDT 24
Peak memory 207372 kb
Host smart-a419595f-a45a-4e3c-9a23-82ffc6765286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93209
5049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.932095049
Directory /workspace/7.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.2855267073
Short name T902
Test name
Test status
Simulation time 7050131164 ps
CPU time 27.35 seconds
Started Aug 05 05:34:24 PM PDT 24
Finished Aug 05 05:34:51 PM PDT 24
Peak memory 215896 kb
Host smart-415aabbd-fdea-49a2-ba29-d888d09bf310
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855267073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.2855267073
Directory /workspace/7.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.3706025326
Short name T2763
Test name
Test status
Simulation time 2609303063 ps
CPU time 17.18 seconds
Started Aug 05 05:34:29 PM PDT 24
Finished Aug 05 05:34:46 PM PDT 24
Peak memory 223916 kb
Host smart-ecf1ab8b-0f31-48af-a5f3-7095639fec23
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3706025326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.3706025326
Directory /workspace/7.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/7.usbdev_rand_suspends.720954698
Short name T1175
Test name
Test status
Simulation time 13667364722 ps
CPU time 103.23 seconds
Started Aug 05 05:34:26 PM PDT 24
Finished Aug 05 05:36:10 PM PDT 24
Peak memory 223968 kb
Host smart-74fe5b4c-cab5-47f1-8301-302268023905
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=720954698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.720954698
Directory /workspace/7.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3706578564
Short name T770
Test name
Test status
Simulation time 200889886 ps
CPU time 0.94 seconds
Started Aug 05 05:34:27 PM PDT 24
Finished Aug 05 05:34:28 PM PDT 24
Peak memory 207284 kb
Host smart-db505c26-7779-44f9-a6a2-89c990dfe976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37065
78564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3706578564
Directory /workspace/7.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.397943858
Short name T1774
Test name
Test status
Simulation time 179504907 ps
CPU time 0.91 seconds
Started Aug 05 05:34:24 PM PDT 24
Finished Aug 05 05:34:25 PM PDT 24
Peak memory 207348 kb
Host smart-6d3c3e58-72e6-4d07-b9d9-953247264ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39794
3858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.397943858
Directory /workspace/7.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/7.usbdev_resume_link_active.2551400031
Short name T944
Test name
Test status
Simulation time 20192240645 ps
CPU time 23.56 seconds
Started Aug 05 05:34:27 PM PDT 24
Finished Aug 05 05:34:51 PM PDT 24
Peak memory 207428 kb
Host smart-43ef99f2-ae0a-41e8-b89c-eb98ed95e45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25514
00031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.2551400031
Directory /workspace/7.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/7.usbdev_rx_crc_err.644305887
Short name T993
Test name
Test status
Simulation time 159134848 ps
CPU time 0.86 seconds
Started Aug 05 05:34:27 PM PDT 24
Finished Aug 05 05:34:28 PM PDT 24
Peak memory 207256 kb
Host smart-c2851f4d-0696-4f4b-97ee-0b1bce747f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64430
5887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.644305887
Directory /workspace/7.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/7.usbdev_rx_full.1645265216
Short name T1906
Test name
Test status
Simulation time 377003840 ps
CPU time 1.29 seconds
Started Aug 05 05:34:25 PM PDT 24
Finished Aug 05 05:34:27 PM PDT 24
Peak memory 207396 kb
Host smart-1d826eec-63b8-47d7-bba8-f8b7aa73d067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16452
65216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.1645265216
Directory /workspace/7.usbdev_rx_full/latest


Test location /workspace/coverage/default/7.usbdev_setup_stage.3845392031
Short name T1076
Test name
Test status
Simulation time 168179594 ps
CPU time 0.83 seconds
Started Aug 05 05:34:28 PM PDT 24
Finished Aug 05 05:34:29 PM PDT 24
Peak memory 207316 kb
Host smart-354d0b24-a1d4-4311-b97b-2d97ca28aa0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38453
92031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3845392031
Directory /workspace/7.usbdev_setup_stage/latest


Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.799902607
Short name T2425
Test name
Test status
Simulation time 163875307 ps
CPU time 0.85 seconds
Started Aug 05 05:34:26 PM PDT 24
Finished Aug 05 05:34:26 PM PDT 24
Peak memory 207288 kb
Host smart-2a81e143-5333-435a-9bcb-f909859ffd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79990
2607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.799902607
Directory /workspace/7.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/7.usbdev_smoke.886151607
Short name T2669
Test name
Test status
Simulation time 261962157 ps
CPU time 1.18 seconds
Started Aug 05 05:34:26 PM PDT 24
Finished Aug 05 05:34:28 PM PDT 24
Peak memory 207352 kb
Host smart-e5e6ae8e-c9df-4c3d-a20e-a317da1bf195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88615
1607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.886151607
Directory /workspace/7.usbdev_smoke/latest


Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.1377838119
Short name T1851
Test name
Test status
Simulation time 2123006025 ps
CPU time 16.7 seconds
Started Aug 05 05:34:25 PM PDT 24
Finished Aug 05 05:34:42 PM PDT 24
Peak memory 223884 kb
Host smart-a5a1b87b-d7c3-4099-ab3b-01b014665b4e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1377838119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.1377838119
Directory /workspace/7.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3318697561
Short name T554
Test name
Test status
Simulation time 175169981 ps
CPU time 0.93 seconds
Started Aug 05 05:34:32 PM PDT 24
Finished Aug 05 05:34:33 PM PDT 24
Peak memory 207300 kb
Host smart-c7a433c8-b91e-4f76-8164-57385c87e623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33186
97561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3318697561
Directory /workspace/7.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/7.usbdev_stall_trans.683654309
Short name T1366
Test name
Test status
Simulation time 189064012 ps
CPU time 0.95 seconds
Started Aug 05 05:34:25 PM PDT 24
Finished Aug 05 05:34:26 PM PDT 24
Peak memory 207312 kb
Host smart-6e4c2930-4b63-4d91-9467-4197565e7bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68365
4309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.683654309
Directory /workspace/7.usbdev_stall_trans/latest


Test location /workspace/coverage/default/7.usbdev_stream_len_max.1907699065
Short name T2401
Test name
Test status
Simulation time 890970685 ps
CPU time 2.37 seconds
Started Aug 05 05:34:28 PM PDT 24
Finished Aug 05 05:34:31 PM PDT 24
Peak memory 207320 kb
Host smart-513515d9-5581-40b8-aab5-901546230d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19076
99065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.1907699065
Directory /workspace/7.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/7.usbdev_streaming_out.3060401818
Short name T964
Test name
Test status
Simulation time 2857403603 ps
CPU time 81.68 seconds
Started Aug 05 05:34:28 PM PDT 24
Finished Aug 05 05:35:50 PM PDT 24
Peak memory 217320 kb
Host smart-9d84ddae-54cb-4ad5-b45e-188e9860e8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30604
01818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3060401818
Directory /workspace/7.usbdev_streaming_out/latest


Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.1752915791
Short name T2960
Test name
Test status
Simulation time 2247195559 ps
CPU time 14.11 seconds
Started Aug 05 05:34:17 PM PDT 24
Finished Aug 05 05:34:31 PM PDT 24
Peak memory 207660 kb
Host smart-433dea1a-08a7-46a4-9e86-aee0cec9a785
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752915791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.1752915791
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/70.usbdev_endpoint_types.1160251914
Short name T351
Test name
Test status
Simulation time 489327295 ps
CPU time 1.37 seconds
Started Aug 05 05:40:23 PM PDT 24
Finished Aug 05 05:40:25 PM PDT 24
Peak memory 207296 kb
Host smart-346aa748-07ef-433c-ba08-1f7fcdd43285
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1160251914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.1160251914
Directory /workspace/70.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/71.usbdev_endpoint_types.517496389
Short name T2924
Test name
Test status
Simulation time 684313191 ps
CPU time 1.58 seconds
Started Aug 05 05:40:31 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 207316 kb
Host smart-c45970a0-aac8-47f9-b8b8-561339ce1d45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=517496389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.517496389
Directory /workspace/71.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/72.usbdev_endpoint_types.2836035771
Short name T360
Test name
Test status
Simulation time 734351066 ps
CPU time 1.83 seconds
Started Aug 05 05:40:45 PM PDT 24
Finished Aug 05 05:40:47 PM PDT 24
Peak memory 207296 kb
Host smart-7f50b72e-41ea-42fe-a192-e7448e30b7f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2836035771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.2836035771
Directory /workspace/72.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/73.usbdev_endpoint_types.2266251846
Short name T436
Test name
Test status
Simulation time 164158284 ps
CPU time 0.87 seconds
Started Aug 05 05:40:40 PM PDT 24
Finished Aug 05 05:40:41 PM PDT 24
Peak memory 207244 kb
Host smart-5fec2817-b440-46b5-a490-ddb9d70324e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2266251846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.2266251846
Directory /workspace/73.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/74.usbdev_endpoint_types.1712755382
Short name T467
Test name
Test status
Simulation time 176344859 ps
CPU time 0.92 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 207244 kb
Host smart-5eb81031-341e-4c21-91d2-102a9e0bb919
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1712755382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.1712755382
Directory /workspace/74.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/75.usbdev_endpoint_types.1274833205
Short name T394
Test name
Test status
Simulation time 810480744 ps
CPU time 1.65 seconds
Started Aug 05 05:40:48 PM PDT 24
Finished Aug 05 05:40:50 PM PDT 24
Peak memory 207352 kb
Host smart-8104348f-b255-4dae-9fa2-a0afa446ab71
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1274833205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.1274833205
Directory /workspace/75.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/76.usbdev_endpoint_types.3434911342
Short name T297
Test name
Test status
Simulation time 420349836 ps
CPU time 1.31 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 207324 kb
Host smart-29bf556d-86eb-4f49-9ff9-305edf6a5591
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3434911342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.3434911342
Directory /workspace/76.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/77.usbdev_endpoint_types.684867557
Short name T435
Test name
Test status
Simulation time 949015283 ps
CPU time 2.09 seconds
Started Aug 05 05:40:42 PM PDT 24
Finished Aug 05 05:40:44 PM PDT 24
Peak memory 207372 kb
Host smart-0f18a393-dd30-444e-bebc-c66e91c876bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=684867557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.684867557
Directory /workspace/77.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/78.usbdev_endpoint_types.1006033385
Short name T446
Test name
Test status
Simulation time 641434148 ps
CPU time 1.56 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207340 kb
Host smart-80ee210c-4365-46d2-b417-9dcdf8aea2f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1006033385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.1006033385
Directory /workspace/78.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/79.usbdev_endpoint_types.3529883105
Short name T338
Test name
Test status
Simulation time 668552324 ps
CPU time 1.9 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207300 kb
Host smart-5f1fad8d-5ccb-45a6-bd0f-23703ff241c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3529883105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.3529883105
Directory /workspace/79.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/8.usbdev_alert_test.1006111381
Short name T2790
Test name
Test status
Simulation time 53467738 ps
CPU time 0.67 seconds
Started Aug 05 05:34:40 PM PDT 24
Finished Aug 05 05:34:41 PM PDT 24
Peak memory 207320 kb
Host smart-792abe47-3ceb-4ebb-9661-f1b378cb9095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1006111381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1006111381
Directory /workspace/8.usbdev_alert_test/latest


Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3297828519
Short name T2696
Test name
Test status
Simulation time 9398798010 ps
CPU time 11.09 seconds
Started Aug 05 05:34:35 PM PDT 24
Finished Aug 05 05:34:46 PM PDT 24
Peak memory 207540 kb
Host smart-2c7bf3a7-b010-4e56-bea4-7f8b5c96cf9d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297828519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.3297828519
Directory /workspace/8.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1263972865
Short name T8
Test name
Test status
Simulation time 14363672517 ps
CPU time 15.73 seconds
Started Aug 05 05:34:33 PM PDT 24
Finished Aug 05 05:34:49 PM PDT 24
Peak memory 215888 kb
Host smart-0f010dbf-2262-4165-a86a-d38e4f3397de
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263972865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1263972865
Directory /workspace/8.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3683265686
Short name T2214
Test name
Test status
Simulation time 26382046630 ps
CPU time 31.33 seconds
Started Aug 05 05:34:35 PM PDT 24
Finished Aug 05 05:35:07 PM PDT 24
Peak memory 215824 kb
Host smart-6862ef4d-b2e2-4af1-92e0-316bf6bff85e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683265686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.3683265686
Directory /workspace/8.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/8.usbdev_av_buffer.1764196980
Short name T1512
Test name
Test status
Simulation time 176638356 ps
CPU time 0.85 seconds
Started Aug 05 05:34:34 PM PDT 24
Finished Aug 05 05:34:35 PM PDT 24
Peak memory 207264 kb
Host smart-f586d08d-50f6-4b38-8f7c-acb0200f9b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17641
96980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1764196980
Directory /workspace/8.usbdev_av_buffer/latest


Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1717587305
Short name T1030
Test name
Test status
Simulation time 142551347 ps
CPU time 0.84 seconds
Started Aug 05 05:34:33 PM PDT 24
Finished Aug 05 05:34:34 PM PDT 24
Peak memory 207288 kb
Host smart-ff1f116f-293b-428a-87e0-b1b704cbe135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17175
87305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1717587305
Directory /workspace/8.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.1826849739
Short name T2467
Test name
Test status
Simulation time 293419184 ps
CPU time 1.17 seconds
Started Aug 05 05:34:34 PM PDT 24
Finished Aug 05 05:34:35 PM PDT 24
Peak memory 207368 kb
Host smart-2c9fa905-5d54-44d0-87fa-c4bb6aef83dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18268
49739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.1826849739
Directory /workspace/8.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.1429450791
Short name T32
Test name
Test status
Simulation time 371783350 ps
CPU time 1.21 seconds
Started Aug 05 05:34:36 PM PDT 24
Finished Aug 05 05:34:37 PM PDT 24
Peak memory 207356 kb
Host smart-0eea42a9-88df-4cc4-b899-f60032f39506
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1429450791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1429450791
Directory /workspace/8.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/8.usbdev_device_address.3488038655
Short name T900
Test name
Test status
Simulation time 35342709609 ps
CPU time 56.07 seconds
Started Aug 05 05:34:34 PM PDT 24
Finished Aug 05 05:35:30 PM PDT 24
Peak memory 207704 kb
Host smart-75005087-e4f3-4850-9ab8-9cbf945a8a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34880
38655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.3488038655
Directory /workspace/8.usbdev_device_address/latest


Test location /workspace/coverage/default/8.usbdev_device_timeout.1442615249
Short name T529
Test name
Test status
Simulation time 646037615 ps
CPU time 5.31 seconds
Started Aug 05 05:34:32 PM PDT 24
Finished Aug 05 05:34:38 PM PDT 24
Peak memory 207644 kb
Host smart-fc02d3b1-a804-483b-8138-48c38310880a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442615249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.1442615249
Directory /workspace/8.usbdev_device_timeout/latest


Test location /workspace/coverage/default/8.usbdev_disable_endpoint.2011735710
Short name T1849
Test name
Test status
Simulation time 817244310 ps
CPU time 2.02 seconds
Started Aug 05 05:34:36 PM PDT 24
Finished Aug 05 05:34:38 PM PDT 24
Peak memory 207316 kb
Host smart-8889e4e2-a401-4244-80fe-b335de1059b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20117
35710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.2011735710
Directory /workspace/8.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/8.usbdev_disconnected.188279989
Short name T1649
Test name
Test status
Simulation time 146021062 ps
CPU time 0.8 seconds
Started Aug 05 05:34:35 PM PDT 24
Finished Aug 05 05:34:36 PM PDT 24
Peak memory 207252 kb
Host smart-9e905281-4c8e-46d6-9148-cfaceed86bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18827
9989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.188279989
Directory /workspace/8.usbdev_disconnected/latest


Test location /workspace/coverage/default/8.usbdev_enable.281026472
Short name T922
Test name
Test status
Simulation time 66009446 ps
CPU time 0.72 seconds
Started Aug 05 05:34:32 PM PDT 24
Finished Aug 05 05:34:33 PM PDT 24
Peak memory 207204 kb
Host smart-ae20306f-995e-4126-9d42-9ab0b4238ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28102
6472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.281026472
Directory /workspace/8.usbdev_enable/latest


Test location /workspace/coverage/default/8.usbdev_endpoint_access.2524519030
Short name T1084
Test name
Test status
Simulation time 966851785 ps
CPU time 2.49 seconds
Started Aug 05 05:34:32 PM PDT 24
Finished Aug 05 05:34:34 PM PDT 24
Peak memory 207604 kb
Host smart-cf490034-733c-4c6d-a098-cceb5f2c8ab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245
19030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.2524519030
Directory /workspace/8.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/8.usbdev_endpoint_types.2306289214
Short name T442
Test name
Test status
Simulation time 268999018 ps
CPU time 0.99 seconds
Started Aug 05 05:34:33 PM PDT 24
Finished Aug 05 05:34:34 PM PDT 24
Peak memory 207344 kb
Host smart-601ae868-af7d-45f7-ae0a-7ef0eac12b3f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2306289214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.2306289214
Directory /workspace/8.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/8.usbdev_fifo_rst.46243004
Short name T1510
Test name
Test status
Simulation time 336831931 ps
CPU time 2.8 seconds
Started Aug 05 05:34:35 PM PDT 24
Finished Aug 05 05:34:37 PM PDT 24
Peak memory 207492 kb
Host smart-ab7d1671-7442-4b3c-983f-dc6f2976cf12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46243
004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.46243004
Directory /workspace/8.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/8.usbdev_in_iso.598236443
Short name T2774
Test name
Test status
Simulation time 224106939 ps
CPU time 0.94 seconds
Started Aug 05 05:34:32 PM PDT 24
Finished Aug 05 05:34:33 PM PDT 24
Peak memory 207380 kb
Host smart-6a00ba77-40c9-44b7-8c1f-1d32ff94fc68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=598236443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.598236443
Directory /workspace/8.usbdev_in_iso/latest


Test location /workspace/coverage/default/8.usbdev_in_stall.2227425372
Short name T550
Test name
Test status
Simulation time 218824057 ps
CPU time 0.88 seconds
Started Aug 05 05:34:35 PM PDT 24
Finished Aug 05 05:34:36 PM PDT 24
Peak memory 207316 kb
Host smart-4ded2d71-d55d-4127-9ac2-cfef6194891b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22274
25372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2227425372
Directory /workspace/8.usbdev_in_stall/latest


Test location /workspace/coverage/default/8.usbdev_in_trans.1621479342
Short name T653
Test name
Test status
Simulation time 219508516 ps
CPU time 0.95 seconds
Started Aug 05 05:34:34 PM PDT 24
Finished Aug 05 05:34:35 PM PDT 24
Peak memory 207392 kb
Host smart-f808099d-455e-4c69-b252-3e9097538c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16214
79342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1621479342
Directory /workspace/8.usbdev_in_trans/latest


Test location /workspace/coverage/default/8.usbdev_invalid_sync.1699113439
Short name T1869
Test name
Test status
Simulation time 3184464354 ps
CPU time 96.75 seconds
Started Aug 05 05:34:34 PM PDT 24
Finished Aug 05 05:36:11 PM PDT 24
Peak memory 218140 kb
Host smart-e8d79132-a298-4f48-991a-c167b3020639
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1699113439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.1699113439
Directory /workspace/8.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/8.usbdev_iso_retraction.329970536
Short name T2659
Test name
Test status
Simulation time 11101112502 ps
CPU time 71.54 seconds
Started Aug 05 05:34:34 PM PDT 24
Finished Aug 05 05:35:46 PM PDT 24
Peak memory 207620 kb
Host smart-fb5a66c8-5058-41b9-9d0e-69eb69dcf111
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=329970536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.329970536
Directory /workspace/8.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/8.usbdev_link_in_err.1927508001
Short name T2738
Test name
Test status
Simulation time 179561389 ps
CPU time 0.87 seconds
Started Aug 05 05:34:35 PM PDT 24
Finished Aug 05 05:34:36 PM PDT 24
Peak memory 207416 kb
Host smart-f7f5f802-c56c-4259-9e5e-8be0506bd0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19275
08001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1927508001
Directory /workspace/8.usbdev_link_in_err/latest


Test location /workspace/coverage/default/8.usbdev_link_resume.587266667
Short name T765
Test name
Test status
Simulation time 26947306717 ps
CPU time 42.94 seconds
Started Aug 05 05:34:32 PM PDT 24
Finished Aug 05 05:35:15 PM PDT 24
Peak memory 215896 kb
Host smart-734077e6-e0f0-46c3-8033-9aeacce60574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58726
6667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.587266667
Directory /workspace/8.usbdev_link_resume/latest


Test location /workspace/coverage/default/8.usbdev_link_suspend.3142472080
Short name T1882
Test name
Test status
Simulation time 9867149138 ps
CPU time 11.06 seconds
Started Aug 05 05:34:34 PM PDT 24
Finished Aug 05 05:34:46 PM PDT 24
Peak memory 207536 kb
Host smart-fa804de2-af40-46e9-8573-f0ed42d4aa97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31424
72080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3142472080
Directory /workspace/8.usbdev_link_suspend/latest


Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.2839009480
Short name T160
Test name
Test status
Simulation time 2418673709 ps
CPU time 23.14 seconds
Started Aug 05 05:34:33 PM PDT 24
Finished Aug 05 05:34:56 PM PDT 24
Peak memory 223980 kb
Host smart-a6295212-1a00-4adb-a2ee-4c1a9365e61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28390
09480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2839009480
Directory /workspace/8.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.505781056
Short name T218
Test name
Test status
Simulation time 2676624608 ps
CPU time 26.81 seconds
Started Aug 05 05:34:38 PM PDT 24
Finished Aug 05 05:35:05 PM PDT 24
Peak memory 217456 kb
Host smart-73564fe5-0d6a-4703-9aa6-8a92ccf99ea6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=505781056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.505781056
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1851028169
Short name T3132
Test name
Test status
Simulation time 240635332 ps
CPU time 0.97 seconds
Started Aug 05 05:34:32 PM PDT 24
Finished Aug 05 05:34:33 PM PDT 24
Peak memory 207360 kb
Host smart-d0992dda-4352-45ba-bc4a-b398c55a2da5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1851028169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1851028169
Directory /workspace/8.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1243283901
Short name T878
Test name
Test status
Simulation time 192081385 ps
CPU time 1 seconds
Started Aug 05 05:34:31 PM PDT 24
Finished Aug 05 05:34:32 PM PDT 24
Peak memory 207272 kb
Host smart-4cede096-608e-4bd1-be63-4dd262f5f9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12432
83901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1243283901
Directory /workspace/8.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.1167490355
Short name T2910
Test name
Test status
Simulation time 2233745967 ps
CPU time 22.5 seconds
Started Aug 05 05:34:33 PM PDT 24
Finished Aug 05 05:34:56 PM PDT 24
Peak memory 217684 kb
Host smart-b0d95ae4-ddd3-4ac6-876e-db982f0310a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11674
90355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.1167490355
Directory /workspace/8.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2180411278
Short name T123
Test name
Test status
Simulation time 3369444362 ps
CPU time 107.21 seconds
Started Aug 05 05:34:31 PM PDT 24
Finished Aug 05 05:36:18 PM PDT 24
Peak memory 217628 kb
Host smart-0a88ebaa-ef8e-46de-9ec6-884ef2d992b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2180411278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2180411278
Directory /workspace/8.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.4076462521
Short name T780
Test name
Test status
Simulation time 2627993510 ps
CPU time 25.67 seconds
Started Aug 05 05:34:33 PM PDT 24
Finished Aug 05 05:34:59 PM PDT 24
Peak memory 217704 kb
Host smart-1b42341c-b0cd-4813-9e6d-445c6026ae94
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4076462521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.4076462521
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.2103584822
Short name T1352
Test name
Test status
Simulation time 173591366 ps
CPU time 0.89 seconds
Started Aug 05 05:34:37 PM PDT 24
Finished Aug 05 05:34:38 PM PDT 24
Peak memory 207360 kb
Host smart-7d39e3bc-2f6e-4b77-8cdb-443b1d4a4596
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2103584822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.2103584822
Directory /workspace/8.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.217593886
Short name T2148
Test name
Test status
Simulation time 213682655 ps
CPU time 0.93 seconds
Started Aug 05 05:34:37 PM PDT 24
Finished Aug 05 05:34:39 PM PDT 24
Peak memory 207368 kb
Host smart-75914823-3e36-4f69-9b21-53c05d8d4a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21759
3886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.217593886
Directory /workspace/8.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/8.usbdev_nak_trans.1678217778
Short name T1989
Test name
Test status
Simulation time 225470765 ps
CPU time 1.01 seconds
Started Aug 05 05:34:39 PM PDT 24
Finished Aug 05 05:34:41 PM PDT 24
Peak memory 207416 kb
Host smart-7e38db72-3cba-4393-a456-9eb87332ce6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16782
17778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1678217778
Directory /workspace/8.usbdev_nak_trans/latest


Test location /workspace/coverage/default/8.usbdev_out_iso.3003545828
Short name T2249
Test name
Test status
Simulation time 154112740 ps
CPU time 0.93 seconds
Started Aug 05 05:34:38 PM PDT 24
Finished Aug 05 05:34:39 PM PDT 24
Peak memory 207376 kb
Host smart-a299458a-a55a-472f-b8cd-459c91a93c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30035
45828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.3003545828
Directory /workspace/8.usbdev_out_iso/latest


Test location /workspace/coverage/default/8.usbdev_out_stall.1586157499
Short name T904
Test name
Test status
Simulation time 182707667 ps
CPU time 0.86 seconds
Started Aug 05 05:34:41 PM PDT 24
Finished Aug 05 05:34:42 PM PDT 24
Peak memory 207344 kb
Host smart-73337a34-8a23-4891-b03c-1bc77d446bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15861
57499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1586157499
Directory /workspace/8.usbdev_out_stall/latest


Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3582857331
Short name T1659
Test name
Test status
Simulation time 172630034 ps
CPU time 0.93 seconds
Started Aug 05 05:34:41 PM PDT 24
Finished Aug 05 05:34:42 PM PDT 24
Peak memory 207348 kb
Host smart-e32fa572-f6e6-4b5a-a668-062257ff6052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35828
57331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3582857331
Directory /workspace/8.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/8.usbdev_pending_in_trans.4273582159
Short name T1987
Test name
Test status
Simulation time 165058946 ps
CPU time 0.93 seconds
Started Aug 05 05:34:42 PM PDT 24
Finished Aug 05 05:34:44 PM PDT 24
Peak memory 207292 kb
Host smart-270d13ec-024b-48d0-b926-b84e64250a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42735
82159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.4273582159
Directory /workspace/8.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.284758595
Short name T1116
Test name
Test status
Simulation time 198050590 ps
CPU time 0.93 seconds
Started Aug 05 05:34:43 PM PDT 24
Finished Aug 05 05:34:44 PM PDT 24
Peak memory 207372 kb
Host smart-c43cae73-5580-407b-95a2-ad982331b5e1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=284758595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.284758595
Directory /workspace/8.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1312641793
Short name T1732
Test name
Test status
Simulation time 152934590 ps
CPU time 0.85 seconds
Started Aug 05 05:34:42 PM PDT 24
Finished Aug 05 05:34:44 PM PDT 24
Peak memory 207368 kb
Host smart-de4949ec-5a2a-4198-b0dc-e6b9e2e05d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13126
41793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1312641793
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2798290762
Short name T1786
Test name
Test status
Simulation time 30344983 ps
CPU time 0.72 seconds
Started Aug 05 05:34:43 PM PDT 24
Finished Aug 05 05:34:44 PM PDT 24
Peak memory 207456 kb
Host smart-954aef6c-525e-486a-ac4f-06594bb4e87c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27982
90762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2798290762
Directory /workspace/8.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/8.usbdev_pkt_buffer.4095536889
Short name T2845
Test name
Test status
Simulation time 21152121252 ps
CPU time 57.3 seconds
Started Aug 05 05:34:40 PM PDT 24
Finished Aug 05 05:35:38 PM PDT 24
Peak memory 215840 kb
Host smart-4a7f8065-9381-460e-bdee-8f8222b6b98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40955
36889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.4095536889
Directory /workspace/8.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/8.usbdev_pkt_received.3130115204
Short name T2841
Test name
Test status
Simulation time 237475916 ps
CPU time 1.02 seconds
Started Aug 05 05:34:40 PM PDT 24
Finished Aug 05 05:34:41 PM PDT 24
Peak memory 207364 kb
Host smart-55e1c865-4e2b-4c8b-956f-106e8642566f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31301
15204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3130115204
Directory /workspace/8.usbdev_pkt_received/latest


Test location /workspace/coverage/default/8.usbdev_pkt_sent.861641974
Short name T2991
Test name
Test status
Simulation time 246496189 ps
CPU time 1.04 seconds
Started Aug 05 05:34:44 PM PDT 24
Finished Aug 05 05:34:45 PM PDT 24
Peak memory 207328 kb
Host smart-c41cca8b-dec3-43a7-ba52-cf6a6aacb277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86164
1974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.861641974
Directory /workspace/8.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.531128384
Short name T1090
Test name
Test status
Simulation time 5859254026 ps
CPU time 24.9 seconds
Started Aug 05 05:34:48 PM PDT 24
Finished Aug 05 05:35:13 PM PDT 24
Peak memory 224036 kb
Host smart-d087f25d-04e1-4ef3-ae23-dd6174237e82
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=531128384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.531128384
Directory /workspace/8.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1280733972
Short name T574
Test name
Test status
Simulation time 6484071792 ps
CPU time 92.94 seconds
Started Aug 05 05:34:43 PM PDT 24
Finished Aug 05 05:36:17 PM PDT 24
Peak memory 219224 kb
Host smart-98d0dc16-8975-4abd-bd16-1cddb384b7db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1280733972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1280733972
Directory /workspace/8.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/8.usbdev_rand_suspends.1312190635
Short name T771
Test name
Test status
Simulation time 7232077588 ps
CPU time 31.26 seconds
Started Aug 05 05:34:40 PM PDT 24
Finished Aug 05 05:35:11 PM PDT 24
Peak memory 219204 kb
Host smart-3dbcf75a-808a-4da0-ac36-ee251d37e7ac
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312190635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1312190635
Directory /workspace/8.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.727800206
Short name T2709
Test name
Test status
Simulation time 213499095 ps
CPU time 0.96 seconds
Started Aug 05 05:34:38 PM PDT 24
Finished Aug 05 05:34:40 PM PDT 24
Peak memory 207336 kb
Host smart-38b840f2-6cbf-4e46-9fd7-dac30c6e57b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72780
0206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.727800206
Directory /workspace/8.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.2351558720
Short name T2097
Test name
Test status
Simulation time 238754075 ps
CPU time 0.94 seconds
Started Aug 05 05:34:41 PM PDT 24
Finished Aug 05 05:34:42 PM PDT 24
Peak memory 207464 kb
Host smart-4d8570b6-0436-486a-ad88-81e969d51dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23515
58720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2351558720
Directory /workspace/8.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/8.usbdev_resume_link_active.462087608
Short name T1731
Test name
Test status
Simulation time 20181421828 ps
CPU time 26.77 seconds
Started Aug 05 05:34:38 PM PDT 24
Finished Aug 05 05:35:05 PM PDT 24
Peak memory 207396 kb
Host smart-931063d9-fbc6-43b2-9ee4-83dd90ab54f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46208
7608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.462087608
Directory /workspace/8.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/8.usbdev_rx_crc_err.496336123
Short name T1236
Test name
Test status
Simulation time 229511100 ps
CPU time 0.99 seconds
Started Aug 05 05:34:43 PM PDT 24
Finished Aug 05 05:34:44 PM PDT 24
Peak memory 207348 kb
Host smart-21b3b44c-5dce-4ebb-8b82-7ac9a1774ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49633
6123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.496336123
Directory /workspace/8.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/8.usbdev_rx_full.1579100991
Short name T1857
Test name
Test status
Simulation time 386577033 ps
CPU time 1.43 seconds
Started Aug 05 05:34:42 PM PDT 24
Finished Aug 05 05:34:44 PM PDT 24
Peak memory 207348 kb
Host smart-53e49fdf-921a-4e1d-a676-6c19d0aba3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15791
00991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.1579100991
Directory /workspace/8.usbdev_rx_full/latest


Test location /workspace/coverage/default/8.usbdev_setup_stage.1336200218
Short name T220
Test name
Test status
Simulation time 179933221 ps
CPU time 0.9 seconds
Started Aug 05 05:34:41 PM PDT 24
Finished Aug 05 05:34:42 PM PDT 24
Peak memory 207196 kb
Host smart-cb6c9f1d-d6ed-4929-a87a-b4b6b24eefcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13362
00218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1336200218
Directory /workspace/8.usbdev_setup_stage/latest


Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3457060437
Short name T580
Test name
Test status
Simulation time 151186745 ps
CPU time 0.84 seconds
Started Aug 05 05:34:38 PM PDT 24
Finished Aug 05 05:34:39 PM PDT 24
Peak memory 207404 kb
Host smart-cf827bf6-bf88-46af-99bf-9b2a475ae630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34570
60437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3457060437
Directory /workspace/8.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/8.usbdev_smoke.4023559517
Short name T1024
Test name
Test status
Simulation time 202505172 ps
CPU time 0.98 seconds
Started Aug 05 05:34:38 PM PDT 24
Finished Aug 05 05:34:39 PM PDT 24
Peak memory 207324 kb
Host smart-8e5cf5f9-4589-4758-955b-668f09937a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40235
59517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.4023559517
Directory /workspace/8.usbdev_smoke/latest


Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.2577678494
Short name T3124
Test name
Test status
Simulation time 3191673384 ps
CPU time 30.58 seconds
Started Aug 05 05:34:44 PM PDT 24
Finished Aug 05 05:35:15 PM PDT 24
Peak memory 223980 kb
Host smart-b5d8e3e5-0d73-495e-8b8d-dccb2098af33
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2577678494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.2577678494
Directory /workspace/8.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1949794817
Short name T2365
Test name
Test status
Simulation time 204776584 ps
CPU time 0.94 seconds
Started Aug 05 05:34:37 PM PDT 24
Finished Aug 05 05:34:38 PM PDT 24
Peak memory 207608 kb
Host smart-ebce0cde-474c-46c3-b14b-f33bf51e91df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19497
94817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1949794817
Directory /workspace/8.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/8.usbdev_stall_trans.3027488239
Short name T244
Test name
Test status
Simulation time 210262828 ps
CPU time 0.93 seconds
Started Aug 05 05:34:38 PM PDT 24
Finished Aug 05 05:34:39 PM PDT 24
Peak memory 207348 kb
Host smart-687eed2b-5513-4925-80ec-425d8b4f7d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30274
88239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3027488239
Directory /workspace/8.usbdev_stall_trans/latest


Test location /workspace/coverage/default/8.usbdev_stream_len_max.1458711087
Short name T934
Test name
Test status
Simulation time 834611177 ps
CPU time 2.31 seconds
Started Aug 05 05:34:43 PM PDT 24
Finished Aug 05 05:34:45 PM PDT 24
Peak memory 207320 kb
Host smart-8d4e6d62-919b-474d-a54a-3ce5faaa997a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14587
11087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.1458711087
Directory /workspace/8.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/8.usbdev_streaming_out.1996472298
Short name T609
Test name
Test status
Simulation time 2198774459 ps
CPU time 63.35 seconds
Started Aug 05 05:34:39 PM PDT 24
Finished Aug 05 05:35:43 PM PDT 24
Peak memory 217200 kb
Host smart-228150a4-6c13-4086-82be-8cc1f7d49a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19964
72298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1996472298
Directory /workspace/8.usbdev_streaming_out/latest


Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.739764321
Short name T918
Test name
Test status
Simulation time 301815747 ps
CPU time 4.92 seconds
Started Aug 05 05:34:31 PM PDT 24
Finished Aug 05 05:34:36 PM PDT 24
Peak memory 207424 kb
Host smart-4da31820-1e57-44b5-b072-22e0dfa862d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739764321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host_
handshake.739764321
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/80.usbdev_endpoint_types.1691468122
Short name T2801
Test name
Test status
Simulation time 577313780 ps
CPU time 1.49 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207272 kb
Host smart-37cc2770-4830-44c2-9f21-29ad70c9153c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1691468122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.1691468122
Directory /workspace/80.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/82.usbdev_endpoint_types.3964376762
Short name T387
Test name
Test status
Simulation time 501516277 ps
CPU time 1.4 seconds
Started Aug 05 05:40:36 PM PDT 24
Finished Aug 05 05:40:38 PM PDT 24
Peak memory 207324 kb
Host smart-76827ef4-5022-45da-a55b-11353a1bbe1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3964376762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.3964376762
Directory /workspace/82.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/84.usbdev_endpoint_types.1826403821
Short name T463
Test name
Test status
Simulation time 181064799 ps
CPU time 0.91 seconds
Started Aug 05 05:40:42 PM PDT 24
Finished Aug 05 05:40:43 PM PDT 24
Peak memory 207352 kb
Host smart-2b839a12-3b48-4a0d-80b3-5c76e044140d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1826403821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.1826403821
Directory /workspace/84.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/85.usbdev_endpoint_types.1032993641
Short name T422
Test name
Test status
Simulation time 483019995 ps
CPU time 1.52 seconds
Started Aug 05 05:40:45 PM PDT 24
Finished Aug 05 05:40:47 PM PDT 24
Peak memory 207244 kb
Host smart-3a10f60b-0ceb-4615-a39b-14834d0effb9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1032993641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.1032993641
Directory /workspace/85.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/86.usbdev_endpoint_types.847420861
Short name T386
Test name
Test status
Simulation time 756960894 ps
CPU time 1.96 seconds
Started Aug 05 05:40:36 PM PDT 24
Finished Aug 05 05:40:38 PM PDT 24
Peak memory 207352 kb
Host smart-7c7f5a4c-9a4c-4a22-9d03-f798e9cc1dff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=847420861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.847420861
Directory /workspace/86.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/87.usbdev_endpoint_types.3584857943
Short name T475
Test name
Test status
Simulation time 343073035 ps
CPU time 1.26 seconds
Started Aug 05 05:40:37 PM PDT 24
Finished Aug 05 05:40:38 PM PDT 24
Peak memory 207352 kb
Host smart-94c81495-7de5-47ba-bc08-864535ee8dc4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3584857943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.3584857943
Directory /workspace/87.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/88.usbdev_endpoint_types.3479672848
Short name T1951
Test name
Test status
Simulation time 265822722 ps
CPU time 1.03 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207216 kb
Host smart-c2d3aabf-7405-4f43-98ea-c83aad0d1a5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3479672848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.3479672848
Directory /workspace/88.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/89.usbdev_endpoint_types.3601906509
Short name T451
Test name
Test status
Simulation time 266422035 ps
CPU time 1.07 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207352 kb
Host smart-75167f99-645a-44cb-8027-7458a82a392d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3601906509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.3601906509
Directory /workspace/89.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/9.usbdev_alert_test.1545286327
Short name T1328
Test name
Test status
Simulation time 54570959 ps
CPU time 0.67 seconds
Started Aug 05 05:34:54 PM PDT 24
Finished Aug 05 05:34:54 PM PDT 24
Peak memory 207412 kb
Host smart-88a0f6d3-7810-4558-96b4-16921493b736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1545286327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1545286327
Directory /workspace/9.usbdev_alert_test/latest


Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.3047658003
Short name T1502
Test name
Test status
Simulation time 11710379643 ps
CPU time 14.53 seconds
Started Aug 05 05:34:39 PM PDT 24
Finished Aug 05 05:34:54 PM PDT 24
Peak memory 207536 kb
Host smart-05d068ec-760a-40b7-96cd-4661c29977f1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047658003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.3047658003
Directory /workspace/9.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.460489575
Short name T1108
Test name
Test status
Simulation time 15307957136 ps
CPU time 21.77 seconds
Started Aug 05 05:34:39 PM PDT 24
Finished Aug 05 05:35:01 PM PDT 24
Peak memory 215880 kb
Host smart-1b3b280f-a098-4000-851f-a90e421b5d1f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=460489575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.460489575
Directory /workspace/9.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.2055545172
Short name T1982
Test name
Test status
Simulation time 29565507225 ps
CPU time 33.24 seconds
Started Aug 05 05:34:44 PM PDT 24
Finished Aug 05 05:35:17 PM PDT 24
Peak memory 207604 kb
Host smart-48940550-767a-48e9-b1ee-8f95e22bbada
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055545172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.2055545172
Directory /workspace/9.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/9.usbdev_av_buffer.1205098818
Short name T1500
Test name
Test status
Simulation time 175952499 ps
CPU time 0.93 seconds
Started Aug 05 05:34:39 PM PDT 24
Finished Aug 05 05:34:41 PM PDT 24
Peak memory 207260 kb
Host smart-becf9f7a-c614-43fe-af1a-1ddfc8dfdc04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12050
98818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1205098818
Directory /workspace/9.usbdev_av_buffer/latest


Test location /workspace/coverage/default/9.usbdev_bitstuff_err.316587072
Short name T2665
Test name
Test status
Simulation time 158735226 ps
CPU time 0.84 seconds
Started Aug 05 05:34:39 PM PDT 24
Finished Aug 05 05:34:40 PM PDT 24
Peak memory 207224 kb
Host smart-7e87c59d-f818-4a03-bdcd-b534651f76f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31658
7072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.316587072
Directory /workspace/9.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.917446660
Short name T2299
Test name
Test status
Simulation time 565362464 ps
CPU time 1.76 seconds
Started Aug 05 05:34:42 PM PDT 24
Finished Aug 05 05:34:44 PM PDT 24
Peak memory 207368 kb
Host smart-64f610c3-64c4-45ac-b26b-df34f9b9c8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91744
6660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.917446660
Directory /workspace/9.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.4141246567
Short name T1233
Test name
Test status
Simulation time 337936598 ps
CPU time 1.08 seconds
Started Aug 05 05:34:44 PM PDT 24
Finished Aug 05 05:34:45 PM PDT 24
Peak memory 207352 kb
Host smart-4f532b5e-66a8-46ba-ab12-e858c1b64647
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4141246567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.4141246567
Directory /workspace/9.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/9.usbdev_device_address.4117910176
Short name T2668
Test name
Test status
Simulation time 41517245263 ps
CPU time 70.46 seconds
Started Aug 05 05:34:39 PM PDT 24
Finished Aug 05 05:35:49 PM PDT 24
Peak memory 207520 kb
Host smart-78473bf8-817d-44af-b44e-b7426a6ae661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41179
10176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.4117910176
Directory /workspace/9.usbdev_device_address/latest


Test location /workspace/coverage/default/9.usbdev_device_timeout.4220409358
Short name T530
Test name
Test status
Simulation time 958309756 ps
CPU time 23.83 seconds
Started Aug 05 05:34:38 PM PDT 24
Finished Aug 05 05:35:02 PM PDT 24
Peak memory 207576 kb
Host smart-089af98d-6993-477a-b930-ab4ad1e33693
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220409358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.4220409358
Directory /workspace/9.usbdev_device_timeout/latest


Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1912004303
Short name T2019
Test name
Test status
Simulation time 1123525718 ps
CPU time 2.42 seconds
Started Aug 05 05:34:50 PM PDT 24
Finished Aug 05 05:34:53 PM PDT 24
Peak memory 207392 kb
Host smart-ca37cbb7-4bc5-4c93-a0ad-c8a9a5f681cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19120
04303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1912004303
Directory /workspace/9.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/9.usbdev_disconnected.393238930
Short name T1974
Test name
Test status
Simulation time 190214505 ps
CPU time 0.86 seconds
Started Aug 05 05:34:49 PM PDT 24
Finished Aug 05 05:34:50 PM PDT 24
Peak memory 207396 kb
Host smart-dc14e3e3-9859-41a7-a97f-eced15cd3696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39323
8930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.393238930
Directory /workspace/9.usbdev_disconnected/latest


Test location /workspace/coverage/default/9.usbdev_enable.2113208601
Short name T2103
Test name
Test status
Simulation time 50305673 ps
CPU time 0.71 seconds
Started Aug 05 05:34:50 PM PDT 24
Finished Aug 05 05:34:51 PM PDT 24
Peak memory 207312 kb
Host smart-387118a0-b357-47e2-997a-18cb6b6796ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21132
08601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2113208601
Directory /workspace/9.usbdev_enable/latest


Test location /workspace/coverage/default/9.usbdev_endpoint_access.1352317035
Short name T1820
Test name
Test status
Simulation time 781113175 ps
CPU time 2.18 seconds
Started Aug 05 05:34:46 PM PDT 24
Finished Aug 05 05:34:49 PM PDT 24
Peak memory 207628 kb
Host smart-5eb31572-e17a-4a64-83e4-9baa98ae49a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13523
17035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1352317035
Directory /workspace/9.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/9.usbdev_endpoint_types.1061265973
Short name T835
Test name
Test status
Simulation time 223072749 ps
CPU time 0.96 seconds
Started Aug 05 05:34:47 PM PDT 24
Finished Aug 05 05:34:48 PM PDT 24
Peak memory 207204 kb
Host smart-637b6fee-7b73-4a4a-8aff-f9b45d983c34
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1061265973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.1061265973
Directory /workspace/9.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/9.usbdev_fifo_rst.3053270648
Short name T1262
Test name
Test status
Simulation time 315683450 ps
CPU time 2.51 seconds
Started Aug 05 05:34:46 PM PDT 24
Finished Aug 05 05:34:49 PM PDT 24
Peak memory 207392 kb
Host smart-e54cd44c-3adc-4fa0-b0e7-cc64ce7ee037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30532
70648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3053270648
Directory /workspace/9.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/9.usbdev_in_iso.2044869377
Short name T804
Test name
Test status
Simulation time 202106707 ps
CPU time 1.1 seconds
Started Aug 05 05:34:52 PM PDT 24
Finished Aug 05 05:34:53 PM PDT 24
Peak memory 215736 kb
Host smart-a38ea190-1343-4f92-bb0f-be44c821b8cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2044869377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2044869377
Directory /workspace/9.usbdev_in_iso/latest


Test location /workspace/coverage/default/9.usbdev_in_stall.354181921
Short name T697
Test name
Test status
Simulation time 164060576 ps
CPU time 0.87 seconds
Started Aug 05 05:34:47 PM PDT 24
Finished Aug 05 05:34:48 PM PDT 24
Peak memory 207364 kb
Host smart-0dc35b53-1818-4946-b29e-5fb08ded8437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35418
1921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.354181921
Directory /workspace/9.usbdev_in_stall/latest


Test location /workspace/coverage/default/9.usbdev_in_trans.2410540393
Short name T1196
Test name
Test status
Simulation time 168995623 ps
CPU time 0.94 seconds
Started Aug 05 05:34:50 PM PDT 24
Finished Aug 05 05:34:51 PM PDT 24
Peak memory 207380 kb
Host smart-3737caa8-2eac-48fb-9f9d-21c03702a370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24105
40393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2410540393
Directory /workspace/9.usbdev_in_trans/latest


Test location /workspace/coverage/default/9.usbdev_invalid_sync.3630374002
Short name T3082
Test name
Test status
Simulation time 5739807537 ps
CPU time 56.96 seconds
Started Aug 05 05:34:48 PM PDT 24
Finished Aug 05 05:35:45 PM PDT 24
Peak memory 223980 kb
Host smart-c53a54ac-1abe-4e82-b6bb-d4e015918810
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3630374002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.3630374002
Directory /workspace/9.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/9.usbdev_iso_retraction.282283462
Short name T1638
Test name
Test status
Simulation time 6037932648 ps
CPU time 43.74 seconds
Started Aug 05 05:34:47 PM PDT 24
Finished Aug 05 05:35:31 PM PDT 24
Peak memory 207612 kb
Host smart-3f38f352-e689-4af0-9047-385fdfc43994
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=282283462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.282283462
Directory /workspace/9.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/9.usbdev_link_in_err.1446660124
Short name T1511
Test name
Test status
Simulation time 233161401 ps
CPU time 1.07 seconds
Started Aug 05 05:34:48 PM PDT 24
Finished Aug 05 05:34:50 PM PDT 24
Peak memory 207248 kb
Host smart-1c066da4-c6a9-40df-9d8d-640b0471085d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14466
60124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1446660124
Directory /workspace/9.usbdev_link_in_err/latest


Test location /workspace/coverage/default/9.usbdev_link_resume.364043103
Short name T46
Test name
Test status
Simulation time 8067683111 ps
CPU time 13.46 seconds
Started Aug 05 05:34:47 PM PDT 24
Finished Aug 05 05:35:01 PM PDT 24
Peak memory 215912 kb
Host smart-231d7577-4fa2-443a-aaed-50d71d106fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36404
3103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.364043103
Directory /workspace/9.usbdev_link_resume/latest


Test location /workspace/coverage/default/9.usbdev_link_suspend.757264448
Short name T2118
Test name
Test status
Simulation time 5948740544 ps
CPU time 9.53 seconds
Started Aug 05 05:34:46 PM PDT 24
Finished Aug 05 05:34:56 PM PDT 24
Peak memory 215924 kb
Host smart-fcbcc842-e15c-487c-8124-99520d717a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75726
4448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.757264448
Directory /workspace/9.usbdev_link_suspend/latest


Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.2855228294
Short name T1073
Test name
Test status
Simulation time 3283393287 ps
CPU time 93.88 seconds
Started Aug 05 05:34:45 PM PDT 24
Finished Aug 05 05:36:19 PM PDT 24
Peak memory 224000 kb
Host smart-2c68155a-05f7-478b-b525-34ffb93e4533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28552
28294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.2855228294
Directory /workspace/9.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.1303751739
Short name T715
Test name
Test status
Simulation time 1876115469 ps
CPU time 18.13 seconds
Started Aug 05 05:34:47 PM PDT 24
Finished Aug 05 05:35:05 PM PDT 24
Peak memory 217264 kb
Host smart-b409db32-fd28-423b-9e0d-5beff1de5b0e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1303751739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.1303751739
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2091915970
Short name T1787
Test name
Test status
Simulation time 250870496 ps
CPU time 0.96 seconds
Started Aug 05 05:34:46 PM PDT 24
Finished Aug 05 05:34:47 PM PDT 24
Peak memory 207400 kb
Host smart-02f18a23-ccb8-4b01-b5b9-77dbb99c8604
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2091915970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2091915970
Directory /workspace/9.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.319388997
Short name T639
Test name
Test status
Simulation time 198072372 ps
CPU time 0.97 seconds
Started Aug 05 05:34:48 PM PDT 24
Finished Aug 05 05:34:49 PM PDT 24
Peak memory 207340 kb
Host smart-2a1389b6-3159-4e32-be12-fbe19f5e9930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31938
8997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.319388997
Directory /workspace/9.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.4131932842
Short name T1067
Test name
Test status
Simulation time 2284129361 ps
CPU time 16.69 seconds
Started Aug 05 05:34:49 PM PDT 24
Finished Aug 05 05:35:05 PM PDT 24
Peak memory 223968 kb
Host smart-f1dbebd3-511c-49ee-a720-1999db8e504a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41319
32842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.4131932842
Directory /workspace/9.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.1496388932
Short name T1859
Test name
Test status
Simulation time 3334502425 ps
CPU time 92.86 seconds
Started Aug 05 05:34:48 PM PDT 24
Finished Aug 05 05:36:21 PM PDT 24
Peak memory 217308 kb
Host smart-d3cb8529-ceba-4e53-bbac-c262bc4f7558
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1496388932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.1496388932
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2836919135
Short name T2021
Test name
Test status
Simulation time 153908563 ps
CPU time 0.89 seconds
Started Aug 05 05:34:49 PM PDT 24
Finished Aug 05 05:34:50 PM PDT 24
Peak memory 207376 kb
Host smart-3b9848d4-015e-4350-9eb2-3e590dd23cab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2836919135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2836919135
Directory /workspace/9.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2202971490
Short name T2600
Test name
Test status
Simulation time 186288180 ps
CPU time 0.88 seconds
Started Aug 05 05:34:45 PM PDT 24
Finished Aug 05 05:34:46 PM PDT 24
Peak memory 207272 kb
Host smart-b60aa682-5841-41f8-902f-5e4a70204a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22029
71490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2202971490
Directory /workspace/9.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/9.usbdev_out_iso.1314403823
Short name T1484
Test name
Test status
Simulation time 203022555 ps
CPU time 1 seconds
Started Aug 05 05:34:48 PM PDT 24
Finished Aug 05 05:34:50 PM PDT 24
Peak memory 207224 kb
Host smart-30962afd-e829-4d8d-a9ed-347a22a23423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13144
03823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.1314403823
Directory /workspace/9.usbdev_out_iso/latest


Test location /workspace/coverage/default/9.usbdev_out_stall.1614200585
Short name T2291
Test name
Test status
Simulation time 176815878 ps
CPU time 0.93 seconds
Started Aug 05 05:34:52 PM PDT 24
Finished Aug 05 05:34:54 PM PDT 24
Peak memory 207368 kb
Host smart-e9dee240-3309-4fde-8a00-ffe94ec64139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16142
00585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1614200585
Directory /workspace/9.usbdev_out_stall/latest


Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3014334070
Short name T3007
Test name
Test status
Simulation time 162914228 ps
CPU time 0.87 seconds
Started Aug 05 05:34:46 PM PDT 24
Finished Aug 05 05:34:47 PM PDT 24
Peak memory 207356 kb
Host smart-5aeb260e-2a87-4573-9762-625ced2aeb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30143
34070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3014334070
Directory /workspace/9.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3492893953
Short name T185
Test name
Test status
Simulation time 157509920 ps
CPU time 0.89 seconds
Started Aug 05 05:34:54 PM PDT 24
Finished Aug 05 05:34:55 PM PDT 24
Peak memory 207336 kb
Host smart-fe4d929e-9661-4197-a374-a9ae024d8aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34928
93953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3492893953
Directory /workspace/9.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.3465042828
Short name T1012
Test name
Test status
Simulation time 220333158 ps
CPU time 1.17 seconds
Started Aug 05 05:34:47 PM PDT 24
Finished Aug 05 05:34:49 PM PDT 24
Peak memory 207352 kb
Host smart-1dd4c08a-58ca-4899-98cf-c8b6c5fb264e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3465042828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.3465042828
Directory /workspace/9.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1257607979
Short name T786
Test name
Test status
Simulation time 177962576 ps
CPU time 0.98 seconds
Started Aug 05 05:34:46 PM PDT 24
Finished Aug 05 05:34:47 PM PDT 24
Peak memory 207320 kb
Host smart-a9da494d-ca2b-4e6f-9279-52ba910cb807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12576
07979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1257607979
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2767463319
Short name T2138
Test name
Test status
Simulation time 31673929 ps
CPU time 0.73 seconds
Started Aug 05 05:34:47 PM PDT 24
Finished Aug 05 05:34:48 PM PDT 24
Peak memory 207316 kb
Host smart-ba20a464-fe87-4897-9eba-59c68bee4a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27674
63319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2767463319
Directory /workspace/9.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1308127848
Short name T103
Test name
Test status
Simulation time 22432087986 ps
CPU time 58.18 seconds
Started Aug 05 05:34:49 PM PDT 24
Finished Aug 05 05:35:47 PM PDT 24
Peak memory 224140 kb
Host smart-644aaa96-6ef6-4aab-9895-f3b97d2428fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13081
27848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1308127848
Directory /workspace/9.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/9.usbdev_pkt_received.3730798923
Short name T2526
Test name
Test status
Simulation time 246850339 ps
CPU time 1.05 seconds
Started Aug 05 05:34:47 PM PDT 24
Finished Aug 05 05:34:48 PM PDT 24
Peak memory 207268 kb
Host smart-69dc7c55-c3ab-4118-965b-bb500c7f05ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37307
98923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3730798923
Directory /workspace/9.usbdev_pkt_received/latest


Test location /workspace/coverage/default/9.usbdev_pkt_sent.2375128498
Short name T912
Test name
Test status
Simulation time 196292274 ps
CPU time 0.91 seconds
Started Aug 05 05:34:46 PM PDT 24
Finished Aug 05 05:34:47 PM PDT 24
Peak memory 207308 kb
Host smart-5bf62719-3ce1-4018-bc5f-c81057f5a504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23751
28498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2375128498
Directory /workspace/9.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.3143807447
Short name T173
Test name
Test status
Simulation time 8463475657 ps
CPU time 48.24 seconds
Started Aug 05 05:34:45 PM PDT 24
Finished Aug 05 05:35:34 PM PDT 24
Peak memory 224036 kb
Host smart-614d71c1-eecc-4aa4-abfe-e985a82a259f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143807447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.3143807447
Directory /workspace/9.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.693801231
Short name T1344
Test name
Test status
Simulation time 6198838907 ps
CPU time 83.59 seconds
Started Aug 05 05:34:49 PM PDT 24
Finished Aug 05 05:36:12 PM PDT 24
Peak memory 215840 kb
Host smart-f570fa89-ca13-462b-9abb-50ce86b0a246
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=693801231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.693801231
Directory /workspace/9.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/9.usbdev_rand_suspends.1928891533
Short name T1554
Test name
Test status
Simulation time 9976289641 ps
CPU time 66.48 seconds
Started Aug 05 05:34:53 PM PDT 24
Finished Aug 05 05:35:59 PM PDT 24
Peak memory 224072 kb
Host smart-38a35680-8386-42e2-9ce0-e011f4ec7921
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928891533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1928891533
Directory /workspace/9.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.1398941222
Short name T2179
Test name
Test status
Simulation time 197192617 ps
CPU time 0.98 seconds
Started Aug 05 05:34:48 PM PDT 24
Finished Aug 05 05:34:49 PM PDT 24
Peak memory 207340 kb
Host smart-ee363bef-a465-4556-bcac-af0c8cc71b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13989
41222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.1398941222
Directory /workspace/9.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.123149351
Short name T913
Test name
Test status
Simulation time 157928996 ps
CPU time 0.85 seconds
Started Aug 05 05:34:48 PM PDT 24
Finished Aug 05 05:34:49 PM PDT 24
Peak memory 207380 kb
Host smart-6dbcd32c-3d94-4482-a9a7-f01f87ab4b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12314
9351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.123149351
Directory /workspace/9.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/9.usbdev_resume_link_active.1994284741
Short name T2682
Test name
Test status
Simulation time 20160930004 ps
CPU time 25.18 seconds
Started Aug 05 05:34:54 PM PDT 24
Finished Aug 05 05:35:20 PM PDT 24
Peak memory 207456 kb
Host smart-098d2a33-cec5-4b04-86e3-1bc85c3376f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19942
84741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.1994284741
Directory /workspace/9.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1319958552
Short name T2200
Test name
Test status
Simulation time 170443067 ps
CPU time 0.91 seconds
Started Aug 05 05:34:55 PM PDT 24
Finished Aug 05 05:34:56 PM PDT 24
Peak memory 207416 kb
Host smart-436e73f3-1906-4bda-9365-e81720b2634e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13199
58552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1319958552
Directory /workspace/9.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/9.usbdev_rx_full.2500234787
Short name T2826
Test name
Test status
Simulation time 357037971 ps
CPU time 1.23 seconds
Started Aug 05 05:34:56 PM PDT 24
Finished Aug 05 05:34:58 PM PDT 24
Peak memory 207348 kb
Host smart-c4148678-1dea-4cef-aae3-843dc3e04e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25002
34787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.2500234787
Directory /workspace/9.usbdev_rx_full/latest


Test location /workspace/coverage/default/9.usbdev_setup_stage.4062593907
Short name T1007
Test name
Test status
Simulation time 165954705 ps
CPU time 0.88 seconds
Started Aug 05 05:34:55 PM PDT 24
Finished Aug 05 05:34:56 PM PDT 24
Peak memory 207436 kb
Host smart-5337c388-d724-47c8-b34b-bd4d5265df46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40625
93907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.4062593907
Directory /workspace/9.usbdev_setup_stage/latest


Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1231671976
Short name T2700
Test name
Test status
Simulation time 149438573 ps
CPU time 0.82 seconds
Started Aug 05 05:34:53 PM PDT 24
Finished Aug 05 05:34:54 PM PDT 24
Peak memory 207400 kb
Host smart-c48dfc1c-c72a-4209-b33d-2532a9b8a228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12316
71976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1231671976
Directory /workspace/9.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/9.usbdev_smoke.3419857672
Short name T1714
Test name
Test status
Simulation time 199047216 ps
CPU time 0.92 seconds
Started Aug 05 05:34:53 PM PDT 24
Finished Aug 05 05:34:54 PM PDT 24
Peak memory 207296 kb
Host smart-4728ee93-a325-49de-a4fb-091eb9dc0d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34198
57672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3419857672
Directory /workspace/9.usbdev_smoke/latest


Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.477106317
Short name T2519
Test name
Test status
Simulation time 3234443163 ps
CPU time 95.9 seconds
Started Aug 05 05:34:57 PM PDT 24
Finished Aug 05 05:36:33 PM PDT 24
Peak memory 217556 kb
Host smart-12f0dddb-c0d2-43c2-aec9-179511ecd894
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=477106317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.477106317
Directory /workspace/9.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1054750968
Short name T2525
Test name
Test status
Simulation time 203572905 ps
CPU time 0.95 seconds
Started Aug 05 05:34:56 PM PDT 24
Finished Aug 05 05:34:57 PM PDT 24
Peak memory 207276 kb
Host smart-2761f390-4017-4066-8730-f5abe637b63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10547
50968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1054750968
Directory /workspace/9.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/9.usbdev_stall_trans.3599248924
Short name T1763
Test name
Test status
Simulation time 228840724 ps
CPU time 0.91 seconds
Started Aug 05 05:34:53 PM PDT 24
Finished Aug 05 05:34:55 PM PDT 24
Peak memory 207336 kb
Host smart-e0587801-ee02-47b8-9cc0-c94f0b2017fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35992
48924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3599248924
Directory /workspace/9.usbdev_stall_trans/latest


Test location /workspace/coverage/default/9.usbdev_stream_len_max.664800409
Short name T2439
Test name
Test status
Simulation time 1026276625 ps
CPU time 2.58 seconds
Started Aug 05 05:34:54 PM PDT 24
Finished Aug 05 05:34:57 PM PDT 24
Peak memory 207540 kb
Host smart-a6b1e625-7d1b-4e4d-a5aa-8adc3a42d5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66480
0409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.664800409
Directory /workspace/9.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/9.usbdev_streaming_out.564005437
Short name T2751
Test name
Test status
Simulation time 3662602163 ps
CPU time 109.86 seconds
Started Aug 05 05:34:56 PM PDT 24
Finished Aug 05 05:36:46 PM PDT 24
Peak memory 217268 kb
Host smart-5bb370fb-f0e7-449b-a819-181e69c4c4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56400
5437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.564005437
Directory /workspace/9.usbdev_streaming_out/latest


Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.754752361
Short name T791
Test name
Test status
Simulation time 3901754845 ps
CPU time 34.38 seconds
Started Aug 05 05:34:39 PM PDT 24
Finished Aug 05 05:35:14 PM PDT 24
Peak memory 207660 kb
Host smart-1c8d7d07-be05-4c5e-b642-0fdb8851ad37
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754752361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host_
handshake.754752361
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/90.usbdev_endpoint_types.1374545739
Short name T439
Test name
Test status
Simulation time 482192438 ps
CPU time 1.34 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 207216 kb
Host smart-c08982e1-b5ce-408e-8ed7-a27742633156
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1374545739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.1374545739
Directory /workspace/90.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/91.usbdev_endpoint_types.1277175982
Short name T428
Test name
Test status
Simulation time 205798599 ps
CPU time 0.97 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:36 PM PDT 24
Peak memory 207352 kb
Host smart-2434c6e9-63a6-4765-9371-bdaaac0b29b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1277175982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.1277175982
Directory /workspace/91.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/92.usbdev_endpoint_types.3774329187
Short name T566
Test name
Test status
Simulation time 133194939 ps
CPU time 0.81 seconds
Started Aug 05 05:40:34 PM PDT 24
Finished Aug 05 05:40:35 PM PDT 24
Peak memory 207204 kb
Host smart-98796ac9-ff28-4cfb-a919-e788601edc8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3774329187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.3774329187
Directory /workspace/92.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/93.usbdev_endpoint_types.3829639598
Short name T3108
Test name
Test status
Simulation time 185131088 ps
CPU time 0.87 seconds
Started Aug 05 05:40:56 PM PDT 24
Finished Aug 05 05:40:57 PM PDT 24
Peak memory 207372 kb
Host smart-38162352-414b-4ff9-b132-dec972de9ed7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3829639598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.3829639598
Directory /workspace/93.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/94.usbdev_endpoint_types.4150314529
Short name T426
Test name
Test status
Simulation time 255435039 ps
CPU time 1.03 seconds
Started Aug 05 05:40:36 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207352 kb
Host smart-6d76c16b-a2db-47ea-9e2a-6b0afc6ddbd2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4150314529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.4150314529
Directory /workspace/94.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/95.usbdev_endpoint_types.4283082528
Short name T458
Test name
Test status
Simulation time 899378462 ps
CPU time 1.89 seconds
Started Aug 05 05:40:53 PM PDT 24
Finished Aug 05 05:40:54 PM PDT 24
Peak memory 207372 kb
Host smart-527ebc03-8a20-4335-a41d-0695254fbded
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4283082528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.4283082528
Directory /workspace/95.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/96.usbdev_endpoint_types.1003684939
Short name T368
Test name
Test status
Simulation time 592029598 ps
CPU time 1.59 seconds
Started Aug 05 05:40:32 PM PDT 24
Finished Aug 05 05:40:34 PM PDT 24
Peak memory 207296 kb
Host smart-b0803554-89c6-4d65-b20a-6aca001c36e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1003684939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.1003684939
Directory /workspace/96.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/97.usbdev_endpoint_types.2859053579
Short name T350
Test name
Test status
Simulation time 639831339 ps
CPU time 1.58 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207200 kb
Host smart-06294560-d801-4aca-bc8d-f2f3d8fe4dc6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2859053579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.2859053579
Directory /workspace/97.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/98.usbdev_endpoint_types.3393479502
Short name T2630
Test name
Test status
Simulation time 710802777 ps
CPU time 1.64 seconds
Started Aug 05 05:40:36 PM PDT 24
Finished Aug 05 05:40:38 PM PDT 24
Peak memory 207200 kb
Host smart-9252359e-7b38-4b67-b479-2cce5f9a656d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3393479502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.3393479502
Directory /workspace/98.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/99.usbdev_endpoint_types.2543120544
Short name T364
Test name
Test status
Simulation time 513879079 ps
CPU time 1.51 seconds
Started Aug 05 05:40:35 PM PDT 24
Finished Aug 05 05:40:37 PM PDT 24
Peak memory 207324 kb
Host smart-f6694700-ab85-4bcf-93db-14552adb8493
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2543120544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.2543120544
Directory /workspace/99.usbdev_endpoint_types/latest
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