Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	88509	1		T1	3		T2	2		T3	14
all_values[1]	88509	1		T1	3		T2	2		T3	14
all_values[2]	88509	1		T1	3		T2	2		T3	14
all_values[3]	88509	1		T1	3		T2	2		T3	14
all_values[4]	88509	1		T1	3		T2	2		T3	14
all_values[5]	88509	1		T1	3		T2	2		T3	14
all_values[6]	88509	1		T1	3		T2	2		T3	14
all_values[7]	88509	1		T1	3		T2	2		T3	14
all_values[8]	88509	1		T1	3		T2	2		T3	14
all_values[9]	88509	1		T1	3		T2	2		T3	14
all_values[10]	88509	1		T1	3		T2	2		T3	14
all_values[11]	88509	1		T1	3		T2	2		T3	14
all_values[12]	88509	1		T1	3		T2	2		T3	14
all_values[13]	88509	1		T1	3		T2	2		T3	14
all_values[14]	88509	1		T1	3		T2	2		T3	14
all_values[15]	88509	1		T1	3		T2	2		T3	14
all_values[16]	88509	1		T1	3		T2	2		T3	14
all_values[17]	88509	1		T1	3		T2	2		T3	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2824932	1		T1	96		T2	64		T3	448
auto[1]	7356	1		T34	2		T28	10		T16	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2367911	1		T1	78		T2	58		T3	377
auto[1]	464377	1		T1	18		T2	6		T3	71

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	62908	1		T2	2		T3	8		T4	2
all_values[0]	auto[0]	auto[1]	24776	1		T1	3		T3	6		T28	7
all_values[0]	auto[1]	auto[0]	734	1		T21	3		T44	3		T45	3
all_values[0]	auto[1]	auto[1]	91	1		T21	1		T44	1		T45	1
all_values[1]	auto[0]	auto[0]	85493	1		T3	14		T4	2		T32	2
all_values[1]	auto[0]	auto[1]	1573	1		T1	3		T2	2		T5	2
all_values[1]	auto[1]	auto[0]	553	1		T16	2		T40	2		T46	2
all_values[1]	auto[1]	auto[1]	890	1		T16	1		T40	1		T46	1
all_values[2]	auto[0]	auto[0]	3719	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	84515	1		T1	2		T2	1		T3	13
all_values[2]	auto[1]	auto[0]	149	1		T42	1		T43	1		T64	1
all_values[2]	auto[1]	auto[1]	126	1		T42	1		T43	1		T64	1
all_values[3]	auto[0]	auto[0]	86594	1		T1	3		T2	2		T3	14
all_values[3]	auto[0]	auto[1]	277	1		T5	1		T41	1		T59	1
all_values[3]	auto[1]	auto[0]	1574	1		T41	1484		T232	2		T235	2
all_values[3]	auto[1]	auto[1]	64	1		T41	1		T232	2		T235	4
all_values[4]	auto[0]	auto[0]	3713	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	84637	1		T1	2		T2	1		T3	13
all_values[4]	auto[1]	auto[0]	95	1		T65	1		T232	1		T235	2
all_values[4]	auto[1]	auto[1]	64	1		T65	1		T235	1		T233	1
all_values[5]	auto[0]	auto[0]	87983	1		T1	3		T2	2		T3	14
all_values[5]	auto[0]	auto[1]	358	1		T5	1		T6	1		T7	1
all_values[5]	auto[1]	auto[0]	95	1		T232	4		T235	1		T233	1
all_values[5]	auto[1]	auto[1]	73	1		T232	1		T235	1		T233	1
all_values[6]	auto[0]	auto[0]	88074	1		T1	3		T2	2		T3	14
all_values[6]	auto[0]	auto[1]	222	1		T5	1		T7	1		T66	1
all_values[6]	auto[1]	auto[0]	103	1		T235	4		T233	2		T234	3
all_values[6]	auto[1]	auto[1]	110	1		T67	1		T68	1		T69	1
all_values[7]	auto[0]	auto[0]	35249	1		T2	2		T3	2		T4	2
all_values[7]	auto[0]	auto[1]	53078	1		T1	3		T3	12		T27	2
all_values[7]	auto[1]	auto[0]	119	1		T47	1		T48	1		T235	4
all_values[7]	auto[1]	auto[1]	63	1		T47	1		T48	1		T232	1
all_values[8]	auto[0]	auto[0]	87772	1		T1	3		T2	2		T3	14
all_values[8]	auto[0]	auto[1]	53	1		T235	3		T233	1		T315	1
all_values[8]	auto[1]	auto[0]	610	1		T28	10		T52	10		T49	10
all_values[8]	auto[1]	auto[1]	74	1		T49	1		T50	1		T55	1
all_values[9]	auto[0]	auto[0]	88251	1		T1	3		T2	2		T3	14
all_values[9]	auto[0]	auto[1]	64	1		T235	3		T233	2		T314	1
all_values[9]	auto[1]	auto[0]	119	1		T61	3		T62	3		T63	3
all_values[9]	auto[1]	auto[1]	75	1		T61	2		T62	2		T63	2
all_values[10]	auto[0]	auto[0]	88018	1		T1	3		T2	2		T3	14
all_values[10]	auto[0]	auto[1]	317	1		T22	1		T59	1		T60	1
all_values[10]	auto[1]	auto[0]	107	1		T235	1		T234	3		T236	2
all_values[10]	auto[1]	auto[1]	67	1		T232	2		T235	3		T236	1
all_values[11]	auto[0]	auto[0]	88111	1		T1	3		T2	2		T3	14
all_values[11]	auto[0]	auto[1]	133	1		T5	1		T73	1		T76	1
all_values[11]	auto[1]	auto[0]	139	1		T34	1		T74	1		T75	1
all_values[11]	auto[1]	auto[1]	126	1		T34	1		T74	1		T75	1
all_values[12]	auto[0]	auto[0]	88277	1		T1	3		T2	2		T3	14
all_values[12]	auto[0]	auto[1]	71	1		T5	1		T80	1		T81	1
all_values[12]	auto[1]	auto[0]	95	1		T77	2		T78	2		T79	2
all_values[12]	auto[1]	auto[1]	66	1		T77	1		T78	1		T79	1
all_values[13]	auto[0]	auto[0]	88161	1		T1	3		T2	2		T3	14
all_values[13]	auto[0]	auto[1]	75	1		T5	1		T80	1		T81	1
all_values[13]	auto[1]	auto[0]	145	1		T73	1		T76	1		T82	1
all_values[13]	auto[1]	auto[1]	128	1		T73	1		T76	1		T82	1
all_values[14]	auto[0]	auto[0]	15626	1		T1	3		T2	1		T3	14
all_values[14]	auto[0]	auto[1]	72719	1		T2	1		T4	1		T5	1
all_values[14]	auto[1]	auto[0]	107	1		T232	2		T235	2		T233	2
all_values[14]	auto[1]	auto[1]	57	1		T232	2		T235	1		T233	1
all_values[15]	auto[0]	auto[0]	3760	1		T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	84585	1		T1	2		T2	1		T3	13
all_values[15]	auto[1]	auto[0]	109	1		T233	3		T314	1		T236	3
all_values[15]	auto[1]	auto[1]	55	1		T232	1		T233	4		T234	2
all_values[16]	auto[0]	auto[0]	87823	1		T1	3		T2	2		T3	14
all_values[16]	auto[0]	auto[1]	473	1		T5	1		T17	1		T19	1
all_values[16]	auto[1]	auto[0]	136	1		T70	4		T71	4		T72	4
all_values[16]	auto[1]	auto[1]	77	1		T70	4		T71	4		T72	4
all_values[17]	auto[0]	auto[0]	34167	1		T2	2		T4	2		T32	2
all_values[17]	auto[0]	auto[1]	54181	1		T1	3		T3	14		T27	2
all_values[17]	auto[1]	auto[0]	97	1		T56	1		T57	1		T58	1
all_values[17]	auto[1]	auto[1]	64	1		T56	1		T57	1		T58	1