Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	112117	1		T1	1		T2	51		T3	6
auto[1]	43912	1		T1	1		T2	51		T4	46

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29043	1		T3	6		T22	1		T92	2
max_len_m1	828	1		T2	2		T4	2		T109	2
max_len_m2	781	1		T2	2		T105	2		T171	2
max_len_m3	794	1		T2	2		T4	2		T5	2
five	1067	1		T4	2		T5	3		T190	2
four	1106	1		T2	2		T5	4		T28	1
three	732	1		T5	2		T44	1		T491	1
one	825	1		T41	4		T492	2		T493	1
zero	11690	1		T1	2		T5	1		T29	2

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23691	1		T3	6		T22	1		T92	1
max_len	auto[1]	5352	1		T92	1		T93	1		T94	1
max_len_m1	auto[0]	584	1		T2	1		T4	1		T109	1
max_len_m1	auto[1]	244	1		T2	1		T4	1		T109	1
max_len_m2	auto[0]	548	1		T2	1		T105	1		T171	1
max_len_m2	auto[1]	233	1		T2	1		T105	1		T171	1
max_len_m3	auto[0]	538	1		T2	1		T4	1		T5	1
max_len_m3	auto[1]	256	1		T2	1		T4	1		T5	1
five	auto[0]	562	1		T4	1		T5	2		T190	1
five	auto[1]	505	1		T4	1		T5	1		T190	1
four	auto[0]	557	1		T2	1		T5	2		T28	1
four	auto[1]	549	1		T2	1		T5	2		T171	1
three	auto[0]	358	1		T5	2		T44	1		T491	1
three	auto[1]	374	1		T494	1		T495	1		T496	1
one	auto[0]	341	1		T41	4		T492	1		T493	1
one	auto[1]	484	1		T492	1		T110	15		T111	14
zero	auto[0]	511	1		T1	1		T5	1		T29	1
zero	auto[1]	11179	1		T1	1		T29	1		T31	4