Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
56.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	96	48	48	50.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	48	48	50.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	66235	1		T1	1		T2	51		T3	6
auto[1]	38286	1		T1	1		T2	51		T4	46

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	10964	1		T5	14		T31	13		T22	1
endpoints[0x1]	7599	1		T3	6		T17	1		T18	1
endpoints[0x2]	6256	1		T40	2		T105	2		T102	4
endpoints[0x3]	9233	1		T2	102		T170	34		T92	2
endpoints[0x4]	9007	1		T4	92		T5	13		T19	1
endpoints[0x5]	7656	1		T29	2		T16	2		T21	1
endpoints[0x6]	10717	1		T1	2		T108	1		T22	2
endpoints[0x7]	7106	1		T5	12		T30	1		T22	1
endpoints[0x8]	8705	1		T5	13		T22	1		T105	2
endpoints[0x9]	8943	1		T5	15		T28	7		T20	1
endpoints[0xa]	7530	1		T5	13		T104	1		T105	2
endpoints[0xb]	10805	1		T5	14		T105	2		T172	14

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
nak	0	1	1
ack	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	48198	1		T2	51		T3	3		T4	45
data0	56317	1		T1	2		T2	51		T3	3

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	48	48	50.00	48

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER
[nak , ack]	*	*	--	--	48

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	endpoints[0x0]	3391	1		T5	3		T31	3		T172	3
data1	auto[0]	endpoints[0x1]	1766	1		T3	3		T22	1		T170	5
data1	auto[0]	endpoints[0x2]	1334	1		T102	2		T171	20		T172	3
data1	auto[0]	endpoints[0x3]	2696	1		T2	18		T170	8		T177	3
data1	auto[0]	endpoints[0x4]	2435	1		T4	19		T5	2		T172	3
data1	auto[0]	endpoints[0x5]	1889	1		T172	2		T60	2		T183	3
data1	auto[0]	endpoints[0x6]	3195	1		T22	1		T170	5		T172	1
data1	auto[0]	endpoints[0x7]	1792	1		T5	3		T22	1		T172	2
data1	auto[0]	endpoints[0x8]	2258	1		T5	3		T133	1		T94	3
data1	auto[0]	endpoints[0x9]	2464	1		T5	4		T28	3		T177	3
data1	auto[0]	endpoints[0xa]	1857	1		T5	3		T172	3		T60	2
data1	auto[0]	endpoints[0xb]	3273	1		T5	3		T172	3		T60	2
data1	auto[1]	endpoints[0x0]	1744	1		T5	4		T31	5		T172	3
data1	auto[1]	endpoints[0x1]	1673	1		T170	12		T109	42		T190	24
data1	auto[1]	endpoints[0x2]	1457	1		T171	36		T172	4		T177	3
data1	auto[1]	endpoints[0x3]	1583	1		T2	33		T170	8		T177	3
data1	auto[1]	endpoints[0x4]	1736	1		T4	26		T5	4		T22	1
data1	auto[1]	endpoints[0x5]	1595	1		T172	5		T60	1		T183	3
data1	auto[1]	endpoints[0x6]	1807	1		T170	11		T172	6		T177	5
data1	auto[1]	endpoints[0x7]	1441	1		T5	3		T172	4		T94	3
data1	auto[1]	endpoints[0x8]	1753	1		T5	3		T94	4		T183	3
data1	auto[1]	endpoints[0x9]	1747	1		T5	3		T177	4		T181	44
data1	auto[1]	endpoints[0xa]	1522	1		T5	3		T172	3		T326	3
data1	auto[1]	endpoints[0xb]	1790	1		T5	4		T172	4		T94	5
data0	auto[0]	endpoints[0x0]	4207	1		T5	4		T31	5		T138	1
data0	auto[0]	endpoints[0x1]	2661	1		T3	3		T17	1		T18	1
data0	auto[0]	endpoints[0x2]	2032	1		T40	1		T105	1		T102	2
data0	auto[0]	endpoints[0x3]	3491	1		T2	33		T170	9		T92	1
data0	auto[0]	endpoints[0x4]	3224	1		T4	27		T5	4		T19	1
data0	auto[0]	endpoints[0x5]	2708	1		T29	1		T16	1		T21	1
data0	auto[0]	endpoints[0x6]	4080	1		T1	1		T108	1		T170	12
data0	auto[0]	endpoints[0x7]	2515	1		T5	3		T30	1		T105	1
data0	auto[0]	endpoints[0x8]	3154	1		T5	4		T22	1		T105	1
data0	auto[0]	endpoints[0x9]	3122	1		T5	4		T28	4		T20	1
data0	auto[0]	endpoints[0xa]	2655	1		T5	4		T104	1		T105	1
data0	auto[0]	endpoints[0xb]	4030	1		T5	4		T105	1		T172	4
data0	auto[1]	endpoints[0x0]	1620	1		T5	2		T22	1		T105	1
data0	auto[1]	endpoints[0x1]	1499	1		T170	5		T105	1		T109	18
data0	auto[1]	endpoints[0x2]	1433	1		T40	1		T105	1		T171	20
data0	auto[1]	endpoints[0x3]	1463	1		T2	18		T170	9		T92	1
data0	auto[1]	endpoints[0x4]	1611	1		T4	20		T5	2		T22	1
data0	auto[1]	endpoints[0x5]	1464	1		T29	1		T16	1		T105	1
data0	auto[1]	endpoints[0x6]	1635	1		T1	1		T22	1		T170	6
data0	auto[1]	endpoints[0x7]	1357	1		T5	3		T105	1		T172	3
data0	auto[1]	endpoints[0x8]	1540	1		T5	3		T105	1		T60	1
data0	auto[1]	endpoints[0x9]	1609	1		T5	3		T46	1		T105	1
data0	auto[1]	endpoints[0xa]	1496	1		T5	3		T105	1		T172	4
data0	auto[1]	endpoints[0xb]	1711	1		T5	2		T105	1		T172	3