Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	6	10	62.50

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	6	10	62.50	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6651	1		T32	1		T5	1		T103	2
auto[1]	49657	1		T1	1		T2	52		T4	47

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	50247	1		T1	1		T2	52		T4	47
auto[1]	6061	1		T32	1		T33	1		T30	1

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	51263	1		T1	1		T2	52		T4	47
auto[1]	5045	1		T32	1		T27	1		T33	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
ignore_pre[PidTypePre]	321	1		T176	6		T205	5		T327	4
pkt_types[PidTypeInToken]	55987	1		T1	1		T2	52		T4	47

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	6	10	62.50	6

Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes

cp_pid	cp_in_enable	cp_in_iso	cp_in_stall	COUNT	AT LEAST	NUMBER
[ignore_pre[PidTypePre]]	*	[auto[0]]	[auto[1]]	--	--	2
[ignore_pre[PidTypePre]]	*	[auto[1]]	*	--	--	4

Covered bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

166

1

T176

5

T205

2

T327

4

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

155

1

T176

1

T205

3

T328

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3684

1

T5

1

T86

1

T248

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2669

1

T329

1

T89

54

T330

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

75

1

T32

1

T248

1

T331

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

57

1

T103

2

T136

1

T332

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

41312

1

T1

1

T2

52

T4

47

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2261

1

T32

1

T27

1

T100

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

5871

1

T30

1

T20

1

T99

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

58

1

T33

1

T103

2

T136

1