Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	88509	1		T1	3		T2	2		T3	14
all_pins[1]	88509	1		T1	3		T2	2		T3	14
all_pins[2]	88509	1		T1	3		T2	2		T3	14
all_pins[3]	88509	1		T1	3		T2	2		T3	14
all_pins[4]	88509	1		T1	3		T2	2		T3	14
all_pins[5]	88509	1		T1	3		T2	2		T3	14
all_pins[6]	88509	1		T1	3		T2	2		T3	14
all_pins[7]	88509	1		T1	3		T2	2		T3	14
all_pins[8]	88509	1		T1	3		T2	2		T3	14
all_pins[9]	88509	1		T1	3		T2	2		T3	14
all_pins[10]	88509	1		T1	3		T2	2		T3	14
all_pins[11]	88509	1		T1	3		T2	2		T3	14
all_pins[12]	88509	1		T1	3		T2	2		T3	14
all_pins[13]	88509	1		T1	3		T2	2		T3	14
all_pins[14]	88509	1		T1	3		T2	2		T3	14
all_pins[15]	88509	1		T1	3		T2	2		T3	14
all_pins[16]	88509	1		T1	3		T2	2		T3	14
all_pins[17]	88509	1		T1	3		T2	2		T3	14

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2830018	1		T1	96		T2	64		T3	448
values[0x1]	2270	1		T34	1		T16	1		T21	1
transitions[0x0=>0x1]	2030	1		T34	1		T16	1		T21	1
transitions[0x1=>0x0]	2030	1		T34	1		T16	1		T21	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	88418	1		T1	3		T2	2		T3	14
all_pins[0]	values[0x1]	91	1		T21	1		T44	1		T45	1
all_pins[0]	transitions[0x0=>0x1]	82	1		T21	1		T44	1		T45	1
all_pins[0]	transitions[0x1=>0x0]	881	1		T16	1		T40	1		T46	1
all_pins[1]	values[0x0]	87619	1		T1	3		T2	2		T3	14
all_pins[1]	values[0x1]	890	1		T16	1		T40	1		T46	1
all_pins[1]	transitions[0x0=>0x1]	869	1		T16	1		T40	1		T46	1
all_pins[1]	transitions[0x1=>0x0]	105	1		T42	1		T43	1		T64	1
all_pins[2]	values[0x0]	88383	1		T1	3		T2	2		T3	14
all_pins[2]	values[0x1]	126	1		T42	1		T43	1		T64	1
all_pins[2]	transitions[0x0=>0x1]	109	1		T42	1		T43	1		T64	1
all_pins[2]	transitions[0x1=>0x0]	47	1		T41	1		T232	2		T235	4
all_pins[3]	values[0x0]	88445	1		T1	3		T2	2		T3	14
all_pins[3]	values[0x1]	64	1		T41	1		T232	2		T235	4
all_pins[3]	transitions[0x0=>0x1]	50	1		T41	1		T232	2		T235	4
all_pins[3]	transitions[0x1=>0x0]	50	1		T65	1		T235	1		T233	1
all_pins[4]	values[0x0]	88445	1		T1	3		T2	2		T3	14
all_pins[4]	values[0x1]	64	1		T65	1		T235	1		T233	1
all_pins[4]	transitions[0x0=>0x1]	52	1		T65	1		T235	1		T233	1
all_pins[4]	transitions[0x1=>0x0]	61	1		T232	1		T235	1		T233	1
all_pins[5]	values[0x0]	88436	1		T1	3		T2	2		T3	14
all_pins[5]	values[0x1]	73	1		T232	1		T235	1		T233	1
all_pins[5]	transitions[0x0=>0x1]	63	1		T232	1		T235	1		T314	3
all_pins[5]	transitions[0x1=>0x0]	100	1		T67	1		T68	1		T69	1
all_pins[6]	values[0x0]	88399	1		T1	3		T2	2		T3	14
all_pins[6]	values[0x1]	110	1		T67	1		T68	1		T69	1
all_pins[6]	transitions[0x0=>0x1]	96	1		T67	1		T68	1		T69	1
all_pins[6]	transitions[0x1=>0x0]	49	1		T47	1		T48	1		T232	1
all_pins[7]	values[0x0]	88446	1		T1	3		T2	2		T3	14
all_pins[7]	values[0x1]	63	1		T47	1		T48	1		T232	1
all_pins[7]	transitions[0x0=>0x1]	54	1		T47	1		T48	1		T232	1
all_pins[7]	transitions[0x1=>0x0]	65	1		T49	1		T50	1		T55	1
all_pins[8]	values[0x0]	88435	1		T1	3		T2	2		T3	14
all_pins[8]	values[0x1]	74	1		T49	1		T50	1		T55	1
all_pins[8]	transitions[0x0=>0x1]	63	1		T49	1		T50	1		T55	1
all_pins[8]	transitions[0x1=>0x0]	64	1		T61	2		T62	2		T63	2
all_pins[9]	values[0x0]	88434	1		T1	3		T2	2		T3	14
all_pins[9]	values[0x1]	75	1		T61	2		T62	2		T63	2
all_pins[9]	transitions[0x0=>0x1]	59	1		T61	2		T62	2		T63	2
all_pins[9]	transitions[0x1=>0x0]	51	1		T235	2		T236	1		T315	2
all_pins[10]	values[0x0]	88442	1		T1	3		T2	2		T3	14
all_pins[10]	values[0x1]	67	1		T232	2		T235	3		T236	1
all_pins[10]	transitions[0x0=>0x1]	51	1		T232	1		T235	2		T236	1
all_pins[10]	transitions[0x1=>0x0]	110	1		T34	1		T74	1		T75	1
all_pins[11]	values[0x0]	88383	1		T1	3		T2	2		T3	14
all_pins[11]	values[0x1]	126	1		T34	1		T74	1		T75	1
all_pins[11]	transitions[0x0=>0x1]	108	1		T34	1		T74	1		T75	1
all_pins[11]	transitions[0x1=>0x0]	48	1		T77	1		T78	1		T79	1
all_pins[12]	values[0x0]	88443	1		T1	3		T2	2		T3	14
all_pins[12]	values[0x1]	66	1		T77	1		T78	1		T79	1
all_pins[12]	transitions[0x0=>0x1]	53	1		T77	1		T78	1		T79	1
all_pins[12]	transitions[0x1=>0x0]	115	1		T73	1		T76	1		T82	1
all_pins[13]	values[0x0]	88381	1		T1	3		T2	2		T3	14
all_pins[13]	values[0x1]	128	1		T73	1		T76	1		T82	1
all_pins[13]	transitions[0x0=>0x1]	111	1		T73	1		T76	1		T82	1
all_pins[13]	transitions[0x1=>0x0]	40	1		T232	2		T235	1		T233	1
all_pins[14]	values[0x0]	88452	1		T1	3		T2	2		T3	14
all_pins[14]	values[0x1]	57	1		T232	2		T235	1		T233	1
all_pins[14]	transitions[0x0=>0x1]	46	1		T232	2		T235	1		T233	1
all_pins[14]	transitions[0x1=>0x0]	44	1		T232	1		T233	4		T234	1
all_pins[15]	values[0x0]	88454	1		T1	3		T2	2		T3	14
all_pins[15]	values[0x1]	55	1		T232	1		T233	4		T234	2
all_pins[15]	transitions[0x0=>0x1]	40	1		T232	1		T233	2		T234	2
all_pins[15]	transitions[0x1=>0x0]	62	1		T70	4		T71	4		T72	4
all_pins[16]	values[0x0]	88432	1		T1	3		T2	2		T3	14
all_pins[16]	values[0x1]	77	1		T70	4		T71	4		T72	4
all_pins[16]	transitions[0x0=>0x1]	60	1		T70	4		T71	4		T72	4
all_pins[16]	transitions[0x1=>0x0]	47	1		T56	1		T57	1		T58	1
all_pins[17]	values[0x0]	88445	1		T1	3		T2	2		T3	14
all_pins[17]	values[0x1]	64	1		T56	1		T57	1		T58	1
all_pins[17]	transitions[0x0=>0x1]	64	1		T56	1		T57	1		T58	1