Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4435	1		T32	1		T33	3		T103	1
invalid_ep[0xd]	4517	1		T32	1		T33	2		T103	1
invalid_ep[0xe]	4490	1		T32	1		T33	2		T103	1
invalid_ep[0xf]	4579	1		T32	2		T33	1		T5	5
endpoints[0x0]	15063	1		T33	1		T5	16		T31	13
endpoints[0x1]	11508	1		T3	6		T5	2		T17	1
endpoints[0x2]	10597	1		T32	2		T33	1		T5	3
endpoints[0x3]	13397	1		T2	103		T5	1		T321	1
endpoints[0x4]	13276	1		T4	93		T32	1		T5	17
endpoints[0x5]	11667	1		T32	1		T27	1		T5	3
endpoints[0x6]	15288	1		T1	2		T32	1		T5	2
endpoints[0x7]	11246	1		T33	2		T5	14		T30	2
endpoints[0x8]	12896	1		T32	2		T33	2		T34	1
endpoints[0x9]	12797	1		T33	1		T5	17		T28	7
endpoints[0xa]	11858	1		T33	1		T5	16		T103	2
endpoints[0xb]	14846	1		T33	2		T5	18		T105	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	20999	1		T2	24		T4	19		T32	2
pkt_types[PidTypeOutToken]	74094	1		T1	1		T2	27		T3	6
pkt_types[PidTypeInToken]	59990	1		T1	1		T2	52		T4	47

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	942	1		T33	1		T103	1		T87	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	987	1		T103	1		T321	1		T89	22
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	981	1		T89	16		T361	1		T90	24
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	945	1		T33	1		T332	1		T89	16
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1462	1		T5	4		T31	5		T103	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1498	1		T5	1		T18	1		T103	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1323	1		T5	1		T171	23		T172	2
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1438	1		T2	24		T321	1		T87	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1460	1		T4	19		T5	6		T172	3
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1445	1		T321	1		T172	4		T175	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1408	1		T5	1		T170	7		T172	6
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1371	1		T33	1		T172	3		T87	1
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1528	1		T32	2		T94	1		T114	1
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1412	1		T33	1		T177	2		T329	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1365	1		T5	1		T103	1		T248	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1434	1		T5	3		T172	2		T185	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1518	1		T33	2		T136	1		T128	1
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1515	1		T87	1		T209	17		T89	16
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1483	1		T33	1		T209	10		T331	1
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1578	1		T5	5		T103	1		T87	1
pkt_types[PidTypeOutToken]	endpoints[0x0]	7746	1		T33	1		T5	5		T31	3
pkt_types[PidTypeOutToken]	endpoints[0x1]	4517	1		T3	6		T17	1		T22	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	3651	1		T5	1		T40	1		T105	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	6210	1		T2	27		T5	1		T170	17
pkt_types[PidTypeOutToken]	endpoints[0x4]	5953	1		T4	27		T5	4		T19	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	4702	1		T32	1		T5	3		T29	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	7368	1		T1	1		T108	1		T22	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	4416	1		T33	1		T5	7		T30	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	5571	1		T34	1		T5	7		T22	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	5753	1		T5	10		T28	7		T20	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	4715	1		T5	6		T104	1		T105	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	7398	1		T5	6		T105	1		T172	5
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1025	1		T87	1		T89	15		T401	1
pkt_types[PidTypeInToken]	invalid_ep[0xd]	948	1		T32	1		T86	1		T87	1
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1035	1		T32	1		T248	1		T89	11
pkt_types[PidTypeInToken]	invalid_ep[0xf]	995	1		T87	1		T89	15		T434	1
pkt_types[PidTypeInToken]	endpoints[0x0]	4723	1		T5	7		T31	5		T22	1
pkt_types[PidTypeInToken]	endpoints[0x1]	4369	1		T170	18		T105	1		T109	61
pkt_types[PidTypeInToken]	endpoints[0x2]	4569	1		T32	1		T5	1		T40	1
pkt_types[PidTypeInToken]	endpoints[0x3]	4647	1		T2	52		T170	18		T92	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4755	1		T4	47		T5	7		T22	2
pkt_types[PidTypeInToken]	endpoints[0x5]	4402	1		T27	1		T29	1		T16	1
pkt_types[PidTypeInToken]	endpoints[0x6]	5398	1		T1	1		T32	1		T22	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4345	1		T5	7		T30	1		T105	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4691	1		T5	7		T103	1		T105	1
pkt_types[PidTypeInToken]	endpoints[0x9]	4528	1		T5	7		T20	1		T46	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4645	1		T33	1		T5	7		T103	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4915	1		T33	1		T5	7		T105	1