Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T232	4		T235	7		T233	7
all_values[1]	281	1		T232	4		T235	7		T233	7
all_values[2]	281	1		T232	4		T235	7		T233	7
all_values[3]	281	1		T232	4		T235	7		T233	7
all_values[4]	281	1		T232	4		T235	7		T233	7
all_values[5]	281	1		T232	4		T235	7		T233	7
all_values[6]	281	1		T232	4		T235	7		T233	7
all_values[7]	281	1		T232	4		T235	7		T233	7
all_values[8]	281	1		T232	4		T235	7		T233	7
all_values[9]	281	1		T232	4		T235	7		T233	7
all_values[10]	281	1		T232	4		T235	7		T233	7
all_values[11]	281	1		T232	4		T235	7		T233	7
all_values[12]	281	1		T232	4		T235	7		T233	7
all_values[13]	281	1		T232	4		T235	7		T233	7
all_values[14]	281	1		T232	4		T235	7		T233	7
all_values[15]	281	1		T232	4		T235	7		T233	7
all_values[16]	281	1		T232	4		T235	7		T233	7
all_values[17]	281	1		T232	4		T235	7		T233	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6667	1		T232	90		T235	176		T233	161
auto[1]	2325	1		T232	38		T235	48		T233	63

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6164	1		T232	86		T235	151		T233	150
auto[1]	2828	1		T232	42		T235	73		T233	74

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5291	1		T232	83		T235	139		T233	127
auto[1]	3701	1		T232	45		T235	85		T233	97

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	97	1		T232	1		T235	2		T233	3
all_values[0]	auto[0]	auto[1]	auto[0]	82	1		T232	1		T235	2		T233	2
all_values[0]	auto[1]	auto[0]	auto[1]	63	1		T232	2		T235	2		T233	1
all_values[0]	auto[1]	auto[1]	auto[1]	39	1		T235	1		T233	1		T314	2
all_values[1]	auto[0]	auto[0]	auto[0]	84	1		T235	3		T233	2		T314	1
all_values[1]	auto[0]	auto[1]	auto[0]	87	1		T232	1		T235	1		T233	2
all_values[1]	auto[1]	auto[0]	auto[1]	52	1		T235	3		T233	1		T236	2
all_values[1]	auto[1]	auto[1]	auto[1]	58	1		T232	3		T233	2		T314	1
all_values[2]	auto[0]	auto[0]	auto[0]	32	1		T235	2		T337	2		T338	2
all_values[2]	auto[0]	auto[0]	auto[1]	48	1		T235	2		T233	1		T314	1
all_values[2]	auto[0]	auto[1]	auto[0]	45	1		T232	2		T235	2		T314	2
all_values[2]	auto[0]	auto[1]	auto[1]	33	1		T233	1		T315	1		T316	1
all_values[2]	auto[1]	auto[0]	auto[1]	68	1		T235	1		T233	1		T314	1
all_values[2]	auto[1]	auto[1]	auto[1]	55	1		T232	2		T233	4		T234	2
all_values[3]	auto[0]	auto[0]	auto[0]	73	1		T232	1		T235	2		T233	1
all_values[3]	auto[0]	auto[0]	auto[1]	25	1		T233	3		T316	1		T337	1
all_values[3]	auto[0]	auto[1]	auto[0]	49	1		T232	1		T233	1		T314	2
all_values[3]	auto[0]	auto[1]	auto[1]	22	1		T232	1		T235	2		T234	1
all_values[3]	auto[1]	auto[0]	auto[1]	56	1		T232	1		T233	1		T314	1
all_values[3]	auto[1]	auto[1]	auto[1]	56	1		T235	3		T233	1		T234	2
all_values[4]	auto[0]	auto[0]	auto[0]	51	1		T232	1		T235	1		T233	2
all_values[4]	auto[0]	auto[0]	auto[1]	28	1		T232	1		T235	1		T314	1
all_values[4]	auto[0]	auto[1]	auto[0]	45	1		T232	1		T235	1		T234	2
all_values[4]	auto[0]	auto[1]	auto[1]	25	1		T235	1		T314	1		T339	1
all_values[4]	auto[1]	auto[0]	auto[1]	73	1		T232	1		T235	3		T233	3
all_values[4]	auto[1]	auto[1]	auto[1]	59	1		T233	2		T236	1		T315	1
all_values[5]	auto[0]	auto[0]	auto[0]	55	1		T235	1		T233	2		T316	1
all_values[5]	auto[0]	auto[0]	auto[1]	36	1		T235	1		T233	3		T234	2
all_values[5]	auto[0]	auto[1]	auto[0]	45	1		T232	2		T235	1		T236	1
all_values[5]	auto[0]	auto[1]	auto[1]	30	1		T314	2		T236	2		T315	1
all_values[5]	auto[1]	auto[0]	auto[1]	65	1		T235	4		T233	1		T314	2
all_values[5]	auto[1]	auto[1]	auto[1]	50	1		T232	2		T233	1		T234	2
all_values[6]	auto[0]	auto[0]	auto[0]	60	1		T235	1		T314	2		T236	3
all_values[6]	auto[0]	auto[0]	auto[1]	23	1		T232	1		T314	1		T316	1
all_values[6]	auto[0]	auto[1]	auto[0]	55	1		T235	2		T233	1		T234	2
all_values[6]	auto[0]	auto[1]	auto[1]	27	1		T235	1		T233	2		T315	1
all_values[6]	auto[1]	auto[0]	auto[1]	70	1		T232	3		T235	3		T314	1
all_values[6]	auto[1]	auto[1]	auto[1]	46	1		T233	4		T315	1		T316	3
all_values[7]	auto[0]	auto[0]	auto[0]	80	1		T232	1		T235	3		T233	1
all_values[7]	auto[0]	auto[1]	auto[0]	88	1		T235	2		T233	4		T234	2
all_values[7]	auto[1]	auto[0]	auto[1]	59	1		T232	1		T233	1		T314	2
all_values[7]	auto[1]	auto[1]	auto[1]	54	1		T232	2		T235	2		T233	1
all_values[8]	auto[0]	auto[0]	auto[0]	112	1		T232	1		T233	3		T314	3
all_values[8]	auto[0]	auto[1]	auto[0]	69	1		T232	2		T235	2		T233	1
all_values[8]	auto[1]	auto[0]	auto[1]	57	1		T235	3		T233	1		T315	1
all_values[8]	auto[1]	auto[1]	auto[1]	43	1		T232	1		T235	2		T233	2
all_values[9]	auto[0]	auto[0]	auto[0]	58	1		T235	1		T314	1		T234	2
all_values[9]	auto[0]	auto[0]	auto[1]	23	1		T235	1		T236	1		T340	1
all_values[9]	auto[0]	auto[1]	auto[0]	56	1		T232	2		T235	1		T233	4
all_values[9]	auto[0]	auto[1]	auto[1]	29	1		T232	1		T235	2		T314	1
all_values[9]	auto[1]	auto[0]	auto[1]	61	1		T235	2		T233	3		T314	1
all_values[9]	auto[1]	auto[1]	auto[1]	54	1		T232	1		T314	1		T236	1
all_values[10]	auto[0]	auto[0]	auto[0]	56	1		T235	2		T233	2		T314	2
all_values[10]	auto[0]	auto[0]	auto[1]	29	1		T232	1		T233	1		T236	2
all_values[10]	auto[0]	auto[1]	auto[0]	48	1		T234	2		T236	1		T316	2
all_values[10]	auto[0]	auto[1]	auto[1]	30	1		T235	1		T236	1		T315	1
all_values[10]	auto[1]	auto[0]	auto[1]	63	1		T235	2		T233	4		T314	2
all_values[10]	auto[1]	auto[1]	auto[1]	55	1		T232	3		T235	2		T236	2
all_values[11]	auto[0]	auto[0]	auto[0]	64	1		T232	1		T233	2		T314	2
all_values[11]	auto[0]	auto[0]	auto[1]	24	1		T235	1		T234	1		T236	1
all_values[11]	auto[0]	auto[1]	auto[0]	42	1		T232	1		T235	4		T341	2
all_values[11]	auto[0]	auto[1]	auto[1]	25	1		T233	1		T338	2		T340	1
all_values[11]	auto[1]	auto[0]	auto[1]	71	1		T232	1		T235	1		T233	1
all_values[11]	auto[1]	auto[1]	auto[1]	55	1		T232	1		T235	1		T233	3
all_values[12]	auto[0]	auto[0]	auto[0]	71	1		T232	1		T235	4		T233	2
all_values[12]	auto[0]	auto[0]	auto[1]	28	1		T234	1		T236	1		T341	1
all_values[12]	auto[0]	auto[1]	auto[0]	38	1		T232	2		T315	2		T316	1
all_values[12]	auto[0]	auto[1]	auto[1]	26	1		T236	2		T339	2		T342	1
all_values[12]	auto[1]	auto[0]	auto[1]	72	1		T232	1		T235	2		T233	4
all_values[12]	auto[1]	auto[1]	auto[1]	46	1		T235	1		T233	1		T314	1
all_values[13]	auto[0]	auto[0]	auto[0]	50	1		T232	1		T233	3		T234	3
all_values[13]	auto[0]	auto[0]	auto[1]	23	1		T232	1		T235	1		T339	1
all_values[13]	auto[0]	auto[1]	auto[0]	41	1		T233	4		T236	2		T337	3
all_values[13]	auto[0]	auto[1]	auto[1]	41	1		T235	2		T314	1		T236	2
all_values[13]	auto[1]	auto[0]	auto[1]	70	1		T232	2		T235	2		T314	1
all_values[13]	auto[1]	auto[1]	auto[1]	56	1		T235	2		T314	2		T236	2
all_values[14]	auto[0]	auto[0]	auto[0]	53	1		T232	1		T235	4		T233	3
all_values[14]	auto[0]	auto[0]	auto[1]	35	1		T314	1		T234	2		T236	1
all_values[14]	auto[0]	auto[1]	auto[0]	59	1		T232	1		T235	1		T233	1
all_values[14]	auto[0]	auto[1]	auto[1]	25	1		T232	1		T235	1		T233	1
all_values[14]	auto[1]	auto[0]	auto[1]	61	1		T235	1		T314	2		T234	1
all_values[14]	auto[1]	auto[1]	auto[1]	48	1		T232	1		T233	2		T236	2
all_values[15]	auto[0]	auto[0]	auto[0]	61	1		T235	2		T314	1		T234	2
all_values[15]	auto[0]	auto[0]	auto[1]	27	1		T232	2		T233	1		T314	1
all_values[15]	auto[0]	auto[1]	auto[0]	52	1		T233	1		T314	1		T236	1
all_values[15]	auto[0]	auto[1]	auto[1]	25	1		T233	1		T234	1		T236	1
all_values[15]	auto[1]	auto[0]	auto[1]	72	1		T232	1		T235	5		T233	1
all_values[15]	auto[1]	auto[1]	auto[1]	44	1		T232	1		T233	3		T234	1
all_values[16]	auto[0]	auto[0]	auto[0]	49	1		T234	1		T236	1		T316	1
all_values[16]	auto[0]	auto[0]	auto[1]	28	1		T232	1		T235	1		T314	3
all_values[16]	auto[0]	auto[1]	auto[0]	68	1		T232	1		T235	2		T233	2
all_values[16]	auto[0]	auto[1]	auto[1]	28	1		T233	1		T341	1		T338	1
all_values[16]	auto[1]	auto[0]	auto[1]	58	1		T232	2		T235	2		T233	2
all_values[16]	auto[1]	auto[1]	auto[1]	50	1		T235	2		T233	2		T236	2
all_values[17]	auto[0]	auto[0]	auto[0]	84	1		T232	3		T235	3		T314	2
all_values[17]	auto[0]	auto[1]	auto[0]	71	1		T232	1		T235	1		T233	3
all_values[17]	auto[1]	auto[0]	auto[1]	75	1		T235	3		T233	3		T314	2
all_values[17]	auto[1]	auto[1]	auto[1]	51	1		T233	1		T234	2		T316	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal