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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.62 97.98 93.97 97.44 81.25 96.46 98.17 90.05


Total test records in report: 3234
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T3068 /workspace/coverage/default/23.usbdev_device_address.1759252639 Aug 06 08:05:21 PM PDT 24 Aug 06 08:06:08 PM PDT 24 31296100726 ps
T3069 /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2865757392 Aug 06 08:05:40 PM PDT 24 Aug 06 08:06:03 PM PDT 24 3065473394 ps
T3070 /workspace/coverage/default/21.usbdev_invalid_sync.3850275638 Aug 06 08:05:05 PM PDT 24 Aug 06 08:07:35 PM PDT 24 5052847177 ps
T3071 /workspace/coverage/default/45.usbdev_pkt_sent.2054426218 Aug 06 08:08:15 PM PDT 24 Aug 06 08:08:16 PM PDT 24 208137760 ps
T3072 /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.4092728325 Aug 06 08:04:35 PM PDT 24 Aug 06 08:05:16 PM PDT 24 6389118143 ps
T3073 /workspace/coverage/default/27.usbdev_out_iso.550926798 Aug 06 08:06:02 PM PDT 24 Aug 06 08:06:03 PM PDT 24 156802916 ps
T3074 /workspace/coverage/default/10.usbdev_fifo_rst.2900112166 Aug 06 08:03:22 PM PDT 24 Aug 06 08:03:24 PM PDT 24 247146091 ps
T3075 /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.1946904454 Aug 06 08:03:43 PM PDT 24 Aug 06 08:04:07 PM PDT 24 3275735609 ps
T3076 /workspace/coverage/default/11.usbdev_bitstuff_err.938424629 Aug 06 08:03:27 PM PDT 24 Aug 06 08:03:28 PM PDT 24 149404097 ps
T113 /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3046027044 Aug 06 08:00:56 PM PDT 24 Aug 06 08:00:57 PM PDT 24 357956384 ps
T3077 /workspace/coverage/default/8.usbdev_stall_trans.3228877463 Aug 06 08:03:15 PM PDT 24 Aug 06 08:03:16 PM PDT 24 197670907 ps
T3078 /workspace/coverage/default/66.usbdev_endpoint_types.233511433 Aug 06 08:09:11 PM PDT 24 Aug 06 08:09:12 PM PDT 24 320510833 ps
T3079 /workspace/coverage/default/4.usbdev_disconnected.3191193173 Aug 06 08:02:02 PM PDT 24 Aug 06 08:02:03 PM PDT 24 176769961 ps
T3080 /workspace/coverage/default/11.usbdev_invalid_sync.703677245 Aug 06 08:03:29 PM PDT 24 Aug 06 08:04:13 PM PDT 24 4327506476 ps
T3081 /workspace/coverage/default/30.usbdev_nak_trans.3044018988 Aug 06 08:06:27 PM PDT 24 Aug 06 08:06:28 PM PDT 24 192743975 ps
T3082 /workspace/coverage/default/47.usbdev_rx_crc_err.2763402227 Aug 06 08:08:48 PM PDT 24 Aug 06 08:08:49 PM PDT 24 151011270 ps
T3083 /workspace/coverage/default/13.usbdev_aon_wake_reset.298554031 Aug 06 08:03:45 PM PDT 24 Aug 06 08:04:11 PM PDT 24 19628671038 ps
T3084 /workspace/coverage/default/146.usbdev_endpoint_types.3697350487 Aug 06 08:09:34 PM PDT 24 Aug 06 08:09:35 PM PDT 24 183880760 ps
T3085 /workspace/coverage/default/6.usbdev_link_suspend.3072524367 Aug 06 08:02:51 PM PDT 24 Aug 06 08:02:58 PM PDT 24 4526437502 ps
T3086 /workspace/coverage/default/39.usbdev_in_iso.919083921 Aug 06 08:07:25 PM PDT 24 Aug 06 08:07:26 PM PDT 24 233614184 ps
T3087 /workspace/coverage/default/33.usbdev_in_iso.3342404047 Aug 06 08:06:43 PM PDT 24 Aug 06 08:06:44 PM PDT 24 222091881 ps
T3088 /workspace/coverage/default/35.usbdev_max_length_out_transaction.1625082011 Aug 06 08:07:02 PM PDT 24 Aug 06 08:07:03 PM PDT 24 225910879 ps
T3089 /workspace/coverage/default/25.usbdev_data_toggle_restore.3450784524 Aug 06 08:05:36 PM PDT 24 Aug 06 08:05:38 PM PDT 24 688944183 ps
T3090 /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.2119872296 Aug 06 08:07:01 PM PDT 24 Aug 06 08:07:22 PM PDT 24 2045738668 ps
T3091 /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1613413539 Aug 06 08:05:24 PM PDT 24 Aug 06 08:05:41 PM PDT 24 2219705084 ps
T3092 /workspace/coverage/default/12.usbdev_fifo_rst.2093749129 Aug 06 08:03:42 PM PDT 24 Aug 06 08:03:45 PM PDT 24 176881120 ps
T3093 /workspace/coverage/default/34.usbdev_in_iso.3525329599 Aug 06 08:06:58 PM PDT 24 Aug 06 08:06:59 PM PDT 24 208185568 ps
T3094 /workspace/coverage/default/6.usbdev_stream_len_max.158442672 Aug 06 08:02:51 PM PDT 24 Aug 06 08:02:54 PM PDT 24 1295133397 ps
T3095 /workspace/coverage/default/25.usbdev_bitstuff_err.4251689873 Aug 06 08:05:37 PM PDT 24 Aug 06 08:05:38 PM PDT 24 153909337 ps
T3096 /workspace/coverage/default/49.usbdev_endpoint_types.3544619698 Aug 06 08:09:01 PM PDT 24 Aug 06 08:09:02 PM PDT 24 448654144 ps
T3097 /workspace/coverage/default/13.usbdev_phy_config_pinflip.284430626 Aug 06 08:03:59 PM PDT 24 Aug 06 08:04:00 PM PDT 24 191753131 ps
T3098 /workspace/coverage/default/31.usbdev_stall_trans.783023087 Aug 06 08:06:30 PM PDT 24 Aug 06 08:06:31 PM PDT 24 202167333 ps
T3099 /workspace/coverage/default/7.usbdev_data_toggle_clear.2907245158 Aug 06 08:02:52 PM PDT 24 Aug 06 08:02:54 PM PDT 24 393082798 ps
T3100 /workspace/coverage/default/29.usbdev_pkt_received.3252908873 Aug 06 08:06:17 PM PDT 24 Aug 06 08:06:18 PM PDT 24 217312201 ps
T3101 /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3499620337 Aug 06 08:05:44 PM PDT 24 Aug 06 08:06:39 PM PDT 24 2082920928 ps
T3102 /workspace/coverage/default/145.usbdev_endpoint_types.72666855 Aug 06 08:09:15 PM PDT 24 Aug 06 08:09:16 PM PDT 24 148571956 ps
T3103 /workspace/coverage/default/27.usbdev_data_toggle_restore.1945697586 Aug 06 08:06:05 PM PDT 24 Aug 06 08:06:06 PM PDT 24 326112171 ps
T3104 /workspace/coverage/default/36.usbdev_disable_endpoint.60117008 Aug 06 08:07:02 PM PDT 24 Aug 06 08:07:04 PM PDT 24 629147454 ps
T3105 /workspace/coverage/default/33.usbdev_alert_test.245356108 Aug 06 08:06:55 PM PDT 24 Aug 06 08:06:56 PM PDT 24 44254404 ps
T3106 /workspace/coverage/default/35.usbdev_data_toggle_restore.413883012 Aug 06 08:06:58 PM PDT 24 Aug 06 08:07:00 PM PDT 24 597264424 ps
T3107 /workspace/coverage/default/33.usbdev_out_trans_nak.101449246 Aug 06 08:06:46 PM PDT 24 Aug 06 08:06:47 PM PDT 24 155291909 ps
T3108 /workspace/coverage/default/24.usbdev_phy_config_pinflip.1213022210 Aug 06 08:05:27 PM PDT 24 Aug 06 08:05:28 PM PDT 24 309797393 ps
T3109 /workspace/coverage/default/46.usbdev_aon_wake_resume.3332849129 Aug 06 08:08:45 PM PDT 24 Aug 06 08:09:14 PM PDT 24 25078666053 ps
T3110 /workspace/coverage/default/33.usbdev_link_in_err.3236993143 Aug 06 08:06:42 PM PDT 24 Aug 06 08:06:43 PM PDT 24 198312418 ps
T3111 /workspace/coverage/default/15.usbdev_link_suspend.2307332573 Aug 06 08:04:09 PM PDT 24 Aug 06 08:04:17 PM PDT 24 5086535172 ps
T3112 /workspace/coverage/default/30.usbdev_in_iso.1588792869 Aug 06 08:06:16 PM PDT 24 Aug 06 08:06:17 PM PDT 24 208407691 ps
T3113 /workspace/coverage/default/42.usbdev_rx_full.3067898930 Aug 06 08:08:04 PM PDT 24 Aug 06 08:08:05 PM PDT 24 289124221 ps
T3114 /workspace/coverage/default/24.usbdev_low_speed_traffic.2632253607 Aug 06 08:05:33 PM PDT 24 Aug 06 08:06:06 PM PDT 24 4489062940 ps
T3115 /workspace/coverage/default/11.usbdev_out_trans_nak.963378485 Aug 06 08:03:42 PM PDT 24 Aug 06 08:03:43 PM PDT 24 147874964 ps
T3116 /workspace/coverage/default/48.usbdev_aon_wake_resume.4015524308 Aug 06 08:08:41 PM PDT 24 Aug 06 08:09:11 PM PDT 24 26113820486 ps
T3117 /workspace/coverage/default/14.usbdev_rx_full.3102110550 Aug 06 08:04:10 PM PDT 24 Aug 06 08:04:12 PM PDT 24 403343241 ps
T3118 /workspace/coverage/default/22.usbdev_in_stall.3545005627 Aug 06 08:05:24 PM PDT 24 Aug 06 08:05:25 PM PDT 24 147801523 ps
T3119 /workspace/coverage/default/36.usbdev_aon_wake_reset.676037772 Aug 06 08:07:08 PM PDT 24 Aug 06 08:07:33 PM PDT 24 19660319739 ps
T3120 /workspace/coverage/default/7.usbdev_stall_trans.2680132535 Aug 06 08:03:07 PM PDT 24 Aug 06 08:03:08 PM PDT 24 188248148 ps
T3121 /workspace/coverage/default/49.usbdev_stream_len_max.4224805625 Aug 06 08:09:09 PM PDT 24 Aug 06 08:09:12 PM PDT 24 952378358 ps
T3122 /workspace/coverage/default/14.usbdev_streaming_out.1611945103 Aug 06 08:04:08 PM PDT 24 Aug 06 08:05:44 PM PDT 24 3349720245 ps
T3123 /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2607295559 Aug 06 08:05:23 PM PDT 24 Aug 06 08:05:42 PM PDT 24 2475497025 ps
T3124 /workspace/coverage/default/2.usbdev_av_buffer.2445859496 Aug 06 08:01:42 PM PDT 24 Aug 06 08:01:43 PM PDT 24 181249329 ps
T3125 /workspace/coverage/default/22.usbdev_link_resume.3925506970 Aug 06 08:05:25 PM PDT 24 Aug 06 08:06:16 PM PDT 24 28853744651 ps
T224 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1512905380 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:50 PM PDT 24 175664378 ps
T252 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3160062443 Aug 06 07:51:51 PM PDT 24 Aug 06 07:51:52 PM PDT 24 54659551 ps
T225 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.4089808690 Aug 06 07:51:24 PM PDT 24 Aug 06 07:51:27 PM PDT 24 514872570 ps
T232 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.837638842 Aug 06 07:51:52 PM PDT 24 Aug 06 07:51:53 PM PDT 24 54163445 ps
T228 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2875464412 Aug 06 07:51:29 PM PDT 24 Aug 06 07:51:34 PM PDT 24 1070334937 ps
T287 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2795961835 Aug 06 07:51:22 PM PDT 24 Aug 06 07:51:25 PM PDT 24 88099696 ps
T300 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.160036988 Aug 06 07:52:00 PM PDT 24 Aug 06 07:52:02 PM PDT 24 261696332 ps
T301 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3841236251 Aug 06 07:51:51 PM PDT 24 Aug 06 07:51:52 PM PDT 24 81696466 ps
T235 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3975373497 Aug 06 07:51:18 PM PDT 24 Aug 06 07:51:19 PM PDT 24 57913353 ps
T226 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3294447796 Aug 06 07:51:25 PM PDT 24 Aug 06 07:51:30 PM PDT 24 682595561 ps
T233 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3871126844 Aug 06 07:51:52 PM PDT 24 Aug 06 07:51:53 PM PDT 24 39861507 ps
T3126 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.701772356 Aug 06 07:51:22 PM PDT 24 Aug 06 07:51:24 PM PDT 24 270918085 ps
T249 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3370989186 Aug 06 07:51:26 PM PDT 24 Aug 06 07:51:27 PM PDT 24 124987218 ps
T314 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2697361892 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:49 PM PDT 24 102874439 ps
T250 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1251350005 Aug 06 07:51:46 PM PDT 24 Aug 06 07:51:48 PM PDT 24 79784556 ps
T234 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4016104572 Aug 06 07:52:14 PM PDT 24 Aug 06 07:52:14 PM PDT 24 50014947 ps
T288 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1328120412 Aug 06 07:51:17 PM PDT 24 Aug 06 07:51:18 PM PDT 24 64466813 ps
T302 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3531419773 Aug 06 07:51:44 PM PDT 24 Aug 06 07:51:46 PM PDT 24 235260262 ps
T289 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.848694462 Aug 06 07:51:49 PM PDT 24 Aug 06 07:51:51 PM PDT 24 111805542 ps
T236 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2456370022 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:51 PM PDT 24 51667435 ps
T251 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.275967907 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:55 PM PDT 24 843630481 ps
T290 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2760844882 Aug 06 07:51:20 PM PDT 24 Aug 06 07:51:24 PM PDT 24 700298563 ps
T315 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.4030509976 Aug 06 07:51:51 PM PDT 24 Aug 06 07:51:52 PM PDT 24 65189956 ps
T303 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.629107779 Aug 06 07:51:47 PM PDT 24 Aug 06 07:51:48 PM PDT 24 148732561 ps
T316 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1784069984 Aug 06 07:51:51 PM PDT 24 Aug 06 07:51:52 PM PDT 24 44056225 ps
T337 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1627663097 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:48 PM PDT 24 36511146 ps
T341 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.224140162 Aug 06 07:51:53 PM PDT 24 Aug 06 07:51:54 PM PDT 24 39363154 ps
T258 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2857988423 Aug 06 07:51:42 PM PDT 24 Aug 06 07:51:44 PM PDT 24 147696949 ps
T338 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4056077378 Aug 06 07:51:53 PM PDT 24 Aug 06 07:51:53 PM PDT 24 44718071 ps
T339 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.995018251 Aug 06 07:51:52 PM PDT 24 Aug 06 07:51:53 PM PDT 24 36221573 ps
T255 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1746649104 Aug 06 07:51:42 PM PDT 24 Aug 06 07:51:45 PM PDT 24 117904902 ps
T256 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2488998082 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:49 PM PDT 24 143928773 ps
T269 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2346354766 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:53 PM PDT 24 600679708 ps
T259 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.700816817 Aug 06 07:51:26 PM PDT 24 Aug 06 07:51:28 PM PDT 24 132712831 ps
T263 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2432455807 Aug 06 07:51:47 PM PDT 24 Aug 06 07:51:49 PM PDT 24 197506846 ps
T340 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2679705691 Aug 06 07:51:46 PM PDT 24 Aug 06 07:51:46 PM PDT 24 42474374 ps
T342 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4085699749 Aug 06 07:51:51 PM PDT 24 Aug 06 07:51:52 PM PDT 24 92818248 ps
T317 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2387850963 Aug 06 07:51:51 PM PDT 24 Aug 06 07:51:52 PM PDT 24 46805356 ps
T3127 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.864963436 Aug 06 07:51:59 PM PDT 24 Aug 06 07:51:59 PM PDT 24 39322806 ps
T3128 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3898466057 Aug 06 07:51:49 PM PDT 24 Aug 06 07:51:50 PM PDT 24 36156951 ps
T264 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1036996433 Aug 06 07:51:26 PM PDT 24 Aug 06 07:51:28 PM PDT 24 143049656 ps
T265 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3252915362 Aug 06 07:51:20 PM PDT 24 Aug 06 07:51:22 PM PDT 24 56459309 ps
T3129 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1586335127 Aug 06 07:51:20 PM PDT 24 Aug 06 07:51:21 PM PDT 24 54901820 ps
T474 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2694960188 Aug 06 07:51:55 PM PDT 24 Aug 06 07:52:01 PM PDT 24 1857663323 ps
T3130 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3629107454 Aug 06 07:51:47 PM PDT 24 Aug 06 07:51:47 PM PDT 24 41313243 ps
T261 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4043037811 Aug 06 07:51:44 PM PDT 24 Aug 06 07:51:46 PM PDT 24 158527256 ps
T3131 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1329509921 Aug 06 07:51:56 PM PDT 24 Aug 06 07:51:57 PM PDT 24 37969383 ps
T309 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2391847769 Aug 06 07:51:28 PM PDT 24 Aug 06 07:51:30 PM PDT 24 90708711 ps
T262 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1329832070 Aug 06 07:51:23 PM PDT 24 Aug 06 07:51:26 PM PDT 24 258397179 ps
T304 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2995104648 Aug 06 07:51:51 PM PDT 24 Aug 06 07:51:52 PM PDT 24 156418624 ps
T305 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.842986456 Aug 06 07:51:47 PM PDT 24 Aug 06 07:51:48 PM PDT 24 84677636 ps
T291 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4259548672 Aug 06 07:52:11 PM PDT 24 Aug 06 07:52:12 PM PDT 24 61766953 ps
T292 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1260961915 Aug 06 07:51:25 PM PDT 24 Aug 06 07:51:33 PM PDT 24 1566661149 ps
T3132 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3107012151 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:51 PM PDT 24 122139468 ps
T3133 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3294540102 Aug 06 07:51:51 PM PDT 24 Aug 06 07:51:53 PM PDT 24 87378705 ps
T293 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3582425576 Aug 06 07:51:19 PM PDT 24 Aug 06 07:51:20 PM PDT 24 81616665 ps
T3134 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2899775828 Aug 06 07:51:21 PM PDT 24 Aug 06 07:51:24 PM PDT 24 116088006 ps
T3135 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2900069392 Aug 06 07:51:49 PM PDT 24 Aug 06 07:51:51 PM PDT 24 109323917 ps
T3136 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2967783440 Aug 06 07:51:21 PM PDT 24 Aug 06 07:51:22 PM PDT 24 79561762 ps
T3137 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.128733949 Aug 06 07:51:23 PM PDT 24 Aug 06 07:51:25 PM PDT 24 115810681 ps
T3138 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2918879324 Aug 06 07:51:58 PM PDT 24 Aug 06 07:51:59 PM PDT 24 47721455 ps
T3139 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.826729458 Aug 06 07:51:46 PM PDT 24 Aug 06 07:51:47 PM PDT 24 97920248 ps
T3140 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2498919548 Aug 06 07:51:46 PM PDT 24 Aug 06 07:51:47 PM PDT 24 41725706 ps
T310 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2450038098 Aug 06 07:51:28 PM PDT 24 Aug 06 07:51:29 PM PDT 24 57501487 ps
T3141 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2495208556 Aug 06 07:51:25 PM PDT 24 Aug 06 07:51:27 PM PDT 24 75651488 ps
T294 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2355066681 Aug 06 07:51:23 PM PDT 24 Aug 06 07:51:25 PM PDT 24 88380146 ps
T3142 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.890159865 Aug 06 07:51:25 PM PDT 24 Aug 06 07:51:29 PM PDT 24 264520444 ps
T3143 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2676229515 Aug 06 07:52:10 PM PDT 24 Aug 06 07:52:11 PM PDT 24 53138325 ps
T311 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3574874459 Aug 06 07:51:44 PM PDT 24 Aug 06 07:51:46 PM PDT 24 198011940 ps
T3144 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.601644189 Aug 06 07:51:19 PM PDT 24 Aug 06 07:51:20 PM PDT 24 55487055 ps
T312 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.392949185 Aug 06 07:51:46 PM PDT 24 Aug 06 07:51:48 PM PDT 24 164282772 ps
T3145 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1704984292 Aug 06 07:51:27 PM PDT 24 Aug 06 07:51:28 PM PDT 24 49865568 ps
T3146 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2345503937 Aug 06 07:51:19 PM PDT 24 Aug 06 07:51:25 PM PDT 24 788510311 ps
T295 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1276745289 Aug 06 07:51:49 PM PDT 24 Aug 06 07:51:50 PM PDT 24 43245180 ps
T475 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1070439481 Aug 06 07:51:43 PM PDT 24 Aug 06 07:51:49 PM PDT 24 1483315677 ps
T313 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.295797577 Aug 06 07:51:27 PM PDT 24 Aug 06 07:51:30 PM PDT 24 896539368 ps
T3147 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.272484476 Aug 06 07:51:53 PM PDT 24 Aug 06 07:51:54 PM PDT 24 70902364 ps
T3148 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2107418119 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:51 PM PDT 24 187893988 ps
T296 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.986652737 Aug 06 07:51:26 PM PDT 24 Aug 06 07:51:27 PM PDT 24 105189794 ps
T3149 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.309092910 Aug 06 07:51:26 PM PDT 24 Aug 06 07:51:28 PM PDT 24 158667210 ps
T3150 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3688759307 Aug 06 07:51:21 PM PDT 24 Aug 06 07:51:25 PM PDT 24 367559248 ps
T3151 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3104067864 Aug 06 07:51:20 PM PDT 24 Aug 06 07:51:21 PM PDT 24 121108417 ps
T3152 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.689923427 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:53 PM PDT 24 165494365 ps
T3153 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4120859031 Aug 06 07:51:54 PM PDT 24 Aug 06 07:51:54 PM PDT 24 42805310 ps
T3154 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3338105871 Aug 06 07:51:27 PM PDT 24 Aug 06 07:51:29 PM PDT 24 108764611 ps
T268 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3837443709 Aug 06 07:51:45 PM PDT 24 Aug 06 07:51:50 PM PDT 24 802485977 ps
T3155 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2491806855 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:51 PM PDT 24 54652799 ps
T472 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3329696943 Aug 06 07:51:26 PM PDT 24 Aug 06 07:51:30 PM PDT 24 561491931 ps
T3156 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1725303052 Aug 06 07:51:29 PM PDT 24 Aug 06 07:51:31 PM PDT 24 298212786 ps
T3157 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3462909439 Aug 06 07:51:23 PM PDT 24 Aug 06 07:51:24 PM PDT 24 60707733 ps
T3158 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3767560288 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:49 PM PDT 24 46431890 ps
T3159 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1701511889 Aug 06 07:51:29 PM PDT 24 Aug 06 07:51:30 PM PDT 24 79076818 ps
T3160 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2532659911 Aug 06 07:51:44 PM PDT 24 Aug 06 07:51:46 PM PDT 24 99275212 ps
T297 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.578106490 Aug 06 07:51:26 PM PDT 24 Aug 06 07:51:29 PM PDT 24 77933171 ps
T3161 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3835173433 Aug 06 07:51:20 PM PDT 24 Aug 06 07:51:22 PM PDT 24 260626495 ps
T3162 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2776111223 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:52 PM PDT 24 577917507 ps
T3163 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1775666890 Aug 06 07:51:26 PM PDT 24 Aug 06 07:51:28 PM PDT 24 94199014 ps
T473 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3526790430 Aug 06 07:51:29 PM PDT 24 Aug 06 07:51:32 PM PDT 24 354731797 ps
T3164 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1588390948 Aug 06 07:51:49 PM PDT 24 Aug 06 07:51:51 PM PDT 24 233355486 ps
T3165 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1747931323 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:50 PM PDT 24 120703292 ps
T3166 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3790512424 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:51 PM PDT 24 49350501 ps
T3167 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.129124412 Aug 06 07:51:58 PM PDT 24 Aug 06 07:51:59 PM PDT 24 87929984 ps
T3168 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1261254441 Aug 06 07:51:23 PM PDT 24 Aug 06 07:51:25 PM PDT 24 113089773 ps
T3169 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3284411702 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:50 PM PDT 24 84780139 ps
T3170 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4287525464 Aug 06 07:51:53 PM PDT 24 Aug 06 07:51:54 PM PDT 24 42462035 ps
T3171 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.235596974 Aug 06 07:51:55 PM PDT 24 Aug 06 07:51:56 PM PDT 24 44243062 ps
T3172 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4073193240 Aug 06 07:51:47 PM PDT 24 Aug 06 07:51:48 PM PDT 24 45390049 ps
T3173 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.683326595 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:51 PM PDT 24 446258939 ps
T3174 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.271050219 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:52 PM PDT 24 96370475 ps
T298 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.547549577 Aug 06 07:51:21 PM PDT 24 Aug 06 07:51:22 PM PDT 24 119529379 ps
T3175 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1245237222 Aug 06 07:51:22 PM PDT 24 Aug 06 07:51:24 PM PDT 24 251189471 ps
T299 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.793857238 Aug 06 07:51:26 PM PDT 24 Aug 06 07:51:27 PM PDT 24 71146503 ps
T3176 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2835983433 Aug 06 07:51:31 PM PDT 24 Aug 06 07:51:32 PM PDT 24 115086640 ps
T3177 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1341979060 Aug 06 07:51:46 PM PDT 24 Aug 06 07:51:50 PM PDT 24 779125021 ps
T3178 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1564013971 Aug 06 07:51:47 PM PDT 24 Aug 06 07:51:48 PM PDT 24 70916247 ps
T3179 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1921142735 Aug 06 07:51:24 PM PDT 24 Aug 06 07:51:26 PM PDT 24 118410049 ps
T3180 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1370869863 Aug 06 07:51:58 PM PDT 24 Aug 06 07:52:00 PM PDT 24 218820051 ps
T3181 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1407333453 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:50 PM PDT 24 54807881 ps
T3182 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1371319586 Aug 06 07:51:31 PM PDT 24 Aug 06 07:51:33 PM PDT 24 219509774 ps
T3183 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3704158988 Aug 06 07:51:51 PM PDT 24 Aug 06 07:51:52 PM PDT 24 34070546 ps
T3184 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3146784713 Aug 06 07:51:59 PM PDT 24 Aug 06 07:52:01 PM PDT 24 86007441 ps
T3185 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3177399492 Aug 06 07:51:28 PM PDT 24 Aug 06 07:51:29 PM PDT 24 107627162 ps
T478 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4130450173 Aug 06 07:51:51 PM PDT 24 Aug 06 07:51:56 PM PDT 24 876600176 ps
T3186 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2338436801 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:50 PM PDT 24 172132636 ps
T3187 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1109928722 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:52 PM PDT 24 68375487 ps
T3188 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3268396665 Aug 06 07:51:21 PM PDT 24 Aug 06 07:51:23 PM PDT 24 97405867 ps
T3189 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.4150938725 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:50 PM PDT 24 204006226 ps
T3190 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3104651573 Aug 06 07:51:28 PM PDT 24 Aug 06 07:51:29 PM PDT 24 101003214 ps
T3191 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3966089048 Aug 06 07:51:54 PM PDT 24 Aug 06 07:51:55 PM PDT 24 41076393 ps
T3192 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4125939281 Aug 06 07:51:49 PM PDT 24 Aug 06 07:51:51 PM PDT 24 171473910 ps
T3193 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1434721835 Aug 06 07:51:49 PM PDT 24 Aug 06 07:51:51 PM PDT 24 96810412 ps
T3194 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.691508960 Aug 06 07:51:46 PM PDT 24 Aug 06 07:51:47 PM PDT 24 109877484 ps
T3195 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2639872645 Aug 06 07:51:30 PM PDT 24 Aug 06 07:51:40 PM PDT 24 2017461014 ps
T3196 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4272177830 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:49 PM PDT 24 51973068 ps
T3197 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1593796426 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:49 PM PDT 24 66038463 ps
T3198 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.318524206 Aug 06 07:51:24 PM PDT 24 Aug 06 07:51:25 PM PDT 24 38829328 ps
T3199 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3726911823 Aug 06 07:51:27 PM PDT 24 Aug 06 07:51:30 PM PDT 24 199285758 ps
T3200 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2912046798 Aug 06 07:51:52 PM PDT 24 Aug 06 07:51:53 PM PDT 24 65485365 ps
T3201 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1861596740 Aug 06 07:51:45 PM PDT 24 Aug 06 07:51:48 PM PDT 24 497857791 ps
T3202 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3648520027 Aug 06 07:51:47 PM PDT 24 Aug 06 07:51:48 PM PDT 24 38180651 ps
T3203 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2952310047 Aug 06 07:51:28 PM PDT 24 Aug 06 07:51:30 PM PDT 24 160884319 ps
T3204 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.453213968 Aug 06 07:51:29 PM PDT 24 Aug 06 07:51:30 PM PDT 24 47726186 ps
T3205 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.12888428 Aug 06 07:51:32 PM PDT 24 Aug 06 07:51:33 PM PDT 24 103047645 ps
T479 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4083326924 Aug 06 07:52:08 PM PDT 24 Aug 06 07:52:13 PM PDT 24 1523271163 ps
T3206 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.592983603 Aug 06 07:51:47 PM PDT 24 Aug 06 07:51:49 PM PDT 24 84407244 ps
T3207 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2792471892 Aug 06 07:51:23 PM PDT 24 Aug 06 07:51:24 PM PDT 24 159266122 ps
T3208 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.640070989 Aug 06 07:51:46 PM PDT 24 Aug 06 07:51:48 PM PDT 24 194115997 ps
T3209 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3290791887 Aug 06 07:51:45 PM PDT 24 Aug 06 07:51:46 PM PDT 24 67846516 ps
T3210 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1180134355 Aug 06 07:51:47 PM PDT 24 Aug 06 07:51:49 PM PDT 24 179204415 ps
T3211 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4132231890 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:49 PM PDT 24 39395159 ps
T3212 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.933133662 Aug 06 07:51:25 PM PDT 24 Aug 06 07:51:26 PM PDT 24 32018397 ps
T3213 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1207894223 Aug 06 07:52:10 PM PDT 24 Aug 06 07:52:10 PM PDT 24 50339628 ps
T3214 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3126901978 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:49 PM PDT 24 37174287 ps
T3215 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1916108528 Aug 06 07:51:52 PM PDT 24 Aug 06 07:51:53 PM PDT 24 44148020 ps
T3216 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1862706476 Aug 06 07:51:50 PM PDT 24 Aug 06 07:51:53 PM PDT 24 292609969 ps
T3217 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4230079947 Aug 06 07:51:26 PM PDT 24 Aug 06 07:51:29 PM PDT 24 307180674 ps
T476 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.939604604 Aug 06 07:51:20 PM PDT 24 Aug 06 07:51:23 PM PDT 24 285104237 ps
T3218 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.800797881 Aug 06 07:51:28 PM PDT 24 Aug 06 07:51:30 PM PDT 24 88146394 ps
T3219 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3659162993 Aug 06 07:51:27 PM PDT 24 Aug 06 07:51:29 PM PDT 24 80679398 ps
T3220 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.202936866 Aug 06 07:51:51 PM PDT 24 Aug 06 07:51:52 PM PDT 24 56949476 ps
T3221 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2732987657 Aug 06 07:51:47 PM PDT 24 Aug 06 07:51:47 PM PDT 24 54146465 ps
T3222 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3709418222 Aug 06 07:51:44 PM PDT 24 Aug 06 07:51:45 PM PDT 24 85113854 ps
T3223 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1544962731 Aug 06 07:51:49 PM PDT 24 Aug 06 07:51:51 PM PDT 24 149604757 ps
T3224 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1735245030 Aug 06 07:51:55 PM PDT 24 Aug 06 07:51:56 PM PDT 24 38031050 ps
T477 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.18169202 Aug 06 07:52:03 PM PDT 24 Aug 06 07:52:08 PM PDT 24 988573030 ps
T3225 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2446473161 Aug 06 07:51:24 PM PDT 24 Aug 06 07:51:28 PM PDT 24 387878517 ps
T3226 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2445504882 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:50 PM PDT 24 130565176 ps
T3227 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3294813380 Aug 06 07:51:44 PM PDT 24 Aug 06 07:51:47 PM PDT 24 108044113 ps
T3228 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4078839468 Aug 06 07:51:53 PM PDT 24 Aug 06 07:51:54 PM PDT 24 41126533 ps
T3229 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1103550957 Aug 06 07:51:22 PM PDT 24 Aug 06 07:51:23 PM PDT 24 82888693 ps
T3230 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.328107116 Aug 06 07:51:49 PM PDT 24 Aug 06 07:51:50 PM PDT 24 93281077 ps
T3231 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.805281165 Aug 06 07:51:29 PM PDT 24 Aug 06 07:51:31 PM PDT 24 355869779 ps
T3232 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2920959606 Aug 06 07:52:05 PM PDT 24 Aug 06 07:52:06 PM PDT 24 39983810 ps
T3233 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.670554217 Aug 06 07:51:21 PM PDT 24 Aug 06 07:51:25 PM PDT 24 176427372 ps
T3234 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3829915678 Aug 06 07:51:48 PM PDT 24 Aug 06 07:51:52 PM PDT 24 144828964 ps

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2201633731
Short name T5
Test name
Test status
Simulation time 10526576893 ps
CPU time 199.15 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:05:02 PM PDT 24
Peak memory 215840 kb
Host smart-2d6a45e6-89c5-4fc7-84c1-d87fb3df61bd
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201633731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2201633731
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.432380545
Short name T105
Test name
Test status
Simulation time 896846651 ps
CPU time 2.19 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:57 PM PDT 24
Peak memory 206868 kb
Host smart-9b1740fc-08ca-40d9-9274-fe2229630651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43238
0545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.432380545
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/101.usbdev_endpoint_types.1050006189
Short name T33
Test name
Test status
Simulation time 900532188 ps
CPU time 1.92 seconds
Started Aug 06 08:09:08 PM PDT 24
Finished Aug 06 08:09:10 PM PDT 24
Peak memory 207268 kb
Host smart-2f81d825-c8b4-41ff-a761-f6749ce1a3ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1050006189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.1050006189
Directory /workspace/101.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3975373497
Short name T235
Test name
Test status
Simulation time 57913353 ps
CPU time 0.73 seconds
Started Aug 06 07:51:18 PM PDT 24
Finished Aug 06 07:51:19 PM PDT 24
Peak memory 206872 kb
Host smart-f1994956-ec02-47cd-b247-042df1cb4b33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3975373497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3975373497
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2947024160
Short name T11
Test name
Test status
Simulation time 20301377580 ps
CPU time 26.44 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:36 PM PDT 24
Peak memory 207624 kb
Host smart-e00371a0-d88b-4609-8d36-4326102fb22e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947024160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2947024160
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1512905380
Short name T224
Test name
Test status
Simulation time 175664378 ps
CPU time 1.74 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 215356 kb
Host smart-5f03bb2b-b381-40e1-b84a-e99306928d00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512905380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1512905380
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.766752905
Short name T60
Test name
Test status
Simulation time 1063805967 ps
CPU time 2.73 seconds
Started Aug 06 08:00:40 PM PDT 24
Finished Aug 06 08:00:42 PM PDT 24
Peak memory 207632 kb
Host smart-a6acd060-500f-4860-b5bb-6b4dfa1006cd
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=766752905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.766752905
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3899914130
Short name T664
Test name
Test status
Simulation time 26682124148 ps
CPU time 28.76 seconds
Started Aug 06 08:05:55 PM PDT 24
Finished Aug 06 08:06:24 PM PDT 24
Peak memory 215812 kb
Host smart-9d50f882-5c47-41e1-a5ff-b4a24f95e025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38999
14130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3899914130
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1390145273
Short name T631
Test name
Test status
Simulation time 12227018180 ps
CPU time 14.67 seconds
Started Aug 06 08:04:58 PM PDT 24
Finished Aug 06 08:05:13 PM PDT 24
Peak memory 207664 kb
Host smart-97f9dba6-68cd-46cc-80f6-af20b2ed2928
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390145273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_disconnect.1390145273
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_types.1919653647
Short name T128
Test name
Test status
Simulation time 453351132 ps
CPU time 1.31 seconds
Started Aug 06 08:08:12 PM PDT 24
Finished Aug 06 08:08:14 PM PDT 24
Peak memory 207328 kb
Host smart-652b0a06-6217-4380-8647-b14009876f7a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1919653647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.1919653647
Directory /workspace/43.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/43.usbdev_device_address.949509564
Short name T90
Test name
Test status
Simulation time 29056165978 ps
CPU time 51.98 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:09:00 PM PDT 24
Peak memory 207692 kb
Host smart-45a3e179-0292-49bc-bc9a-f56bd52289aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94950
9564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.949509564
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3046027044
Short name T113
Test name
Test status
Simulation time 357956384 ps
CPU time 1.2 seconds
Started Aug 06 08:00:56 PM PDT 24
Finished Aug 06 08:00:57 PM PDT 24
Peak memory 207384 kb
Host smart-2b859e5d-c1f6-4e2c-b32e-d27a2d6c4726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30460
27044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3046027044
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2921375824
Short name T26
Test name
Test status
Simulation time 45609829 ps
CPU time 0.7 seconds
Started Aug 06 08:03:39 PM PDT 24
Finished Aug 06 08:03:40 PM PDT 24
Peak memory 207276 kb
Host smart-6d31dcbf-a424-4540-879b-2f35abc6c750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29213
75824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2921375824
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4056077378
Short name T338
Test name
Test status
Simulation time 44718071 ps
CPU time 0.73 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:51:53 PM PDT 24
Peak memory 206864 kb
Host smart-17e4dea5-0e9b-4dac-a362-825e034048c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4056077378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.4056077378
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2694960188
Short name T474
Test name
Test status
Simulation time 1857663323 ps
CPU time 5.78 seconds
Started Aug 06 07:51:55 PM PDT 24
Finished Aug 06 07:52:01 PM PDT 24
Peak memory 207244 kb
Host smart-78df2919-ec37-4739-bac5-c37fc5781c30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2694960188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2694960188
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1443838577
Short name T43
Test name
Test status
Simulation time 152712556 ps
CPU time 0.83 seconds
Started Aug 06 08:03:52 PM PDT 24
Finished Aug 06 08:03:53 PM PDT 24
Peak memory 207340 kb
Host smart-d3801efd-bb39-4a67-8dc9-3ee98bf0fe8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14438
38577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1443838577
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1368463199
Short name T30
Test name
Test status
Simulation time 182297173 ps
CPU time 1.02 seconds
Started Aug 06 08:06:15 PM PDT 24
Finished Aug 06 08:06:16 PM PDT 24
Peak memory 207584 kb
Host smart-011fd435-54c9-4834-816f-8d77a928a5e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1368463199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1368463199
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.2296610659
Short name T172
Test name
Test status
Simulation time 2985904827 ps
CPU time 81.94 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:05:43 PM PDT 24
Peak memory 223912 kb
Host smart-8f787b43-0232-4727-8c60-80ee4e278198
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2296610659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2296610659
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.4003650347
Short name T221
Test name
Test status
Simulation time 579984713 ps
CPU time 1.44 seconds
Started Aug 06 08:00:58 PM PDT 24
Finished Aug 06 08:01:00 PM PDT 24
Peak memory 224344 kb
Host smart-3c7bd407-61c5-4472-96d1-109d032837c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4003650347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.4003650347
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.1405344777
Short name T740
Test name
Test status
Simulation time 88197916 ps
CPU time 0.74 seconds
Started Aug 06 08:05:09 PM PDT 24
Finished Aug 06 08:05:09 PM PDT 24
Peak memory 207444 kb
Host smart-22d3fdde-35be-43b3-a479-28a1052916dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1405344777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.1405344777
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.2635682484
Short name T120
Test name
Test status
Simulation time 25133689634 ps
CPU time 28.47 seconds
Started Aug 06 08:03:29 PM PDT 24
Finished Aug 06 08:03:58 PM PDT 24
Peak memory 215772 kb
Host smart-a4f92a6a-4607-408d-9b46-ad7924ff58b9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635682484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.2635682484
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_device_address.2168054122
Short name T89
Test name
Test status
Simulation time 44048849834 ps
CPU time 73.77 seconds
Started Aug 06 08:08:12 PM PDT 24
Finished Aug 06 08:09:26 PM PDT 24
Peak memory 207756 kb
Host smart-5d60bc89-45c3-4ce7-831f-a21f34167c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21680
54122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.2168054122
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1328120412
Short name T288
Test name
Test status
Simulation time 64466813 ps
CPU time 1 seconds
Started Aug 06 07:51:17 PM PDT 24
Finished Aug 06 07:51:18 PM PDT 24
Peak memory 207008 kb
Host smart-882e27fc-2b9a-41c6-a28e-b56452e0e655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1328120412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1328120412
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/default/31.usbdev_rx_full.3989737161
Short name T50
Test name
Test status
Simulation time 255226540 ps
CPU time 1.1 seconds
Started Aug 06 08:06:27 PM PDT 24
Finished Aug 06 08:06:28 PM PDT 24
Peak memory 207348 kb
Host smart-ff3fcdea-e284-499b-974a-04dd7b2bb809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39897
37161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.3989737161
Directory /workspace/31.usbdev_rx_full/latest

Test location /workspace/coverage/default/76.usbdev_endpoint_types.2524034259
Short name T139
Test name
Test status
Simulation time 592335827 ps
CPU time 1.54 seconds
Started Aug 06 08:08:57 PM PDT 24
Finished Aug 06 08:08:58 PM PDT 24
Peak memory 207264 kb
Host smart-c2616b81-653e-4bfd-a95b-18d174a25e76
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2524034259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.2524034259
Directory /workspace/76.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3377656051
Short name T278
Test name
Test status
Simulation time 17588035299 ps
CPU time 48.86 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:02:47 PM PDT 24
Peak memory 215892 kb
Host smart-fccd9f05-0d00-434c-9d1d-d60a571db891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33776
56051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3377656051
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/135.usbdev_endpoint_types.3014309147
Short name T417
Test name
Test status
Simulation time 546801448 ps
CPU time 1.44 seconds
Started Aug 06 08:09:10 PM PDT 24
Finished Aug 06 08:09:12 PM PDT 24
Peak memory 207348 kb
Host smart-41264075-1aa3-48bd-9525-1430d237eeac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3014309147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.3014309147
Directory /workspace/135.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4043037811
Short name T261
Test name
Test status
Simulation time 158527256 ps
CPU time 2.06 seconds
Started Aug 06 07:51:44 PM PDT 24
Finished Aug 06 07:51:46 PM PDT 24
Peak memory 207228 kb
Host smart-c2d9c147-e386-42f4-a824-b8003d5d7c77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4043037811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.4043037811
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1784069984
Short name T316
Test name
Test status
Simulation time 44056225 ps
CPU time 0.72 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 206880 kb
Host smart-de476246-0cc4-4da5-8665-d9fafbff5628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1784069984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1784069984
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/default/104.usbdev_endpoint_types.299527171
Short name T384
Test name
Test status
Simulation time 598307182 ps
CPU time 1.48 seconds
Started Aug 06 08:09:05 PM PDT 24
Finished Aug 06 08:09:07 PM PDT 24
Peak memory 207328 kb
Host smart-28333ed1-2904-45bb-a63f-7f51481555f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=299527171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.299527171
Directory /workspace/104.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/177.usbdev_endpoint_types.924135715
Short name T345
Test name
Test status
Simulation time 873410811 ps
CPU time 1.79 seconds
Started Aug 06 08:09:44 PM PDT 24
Finished Aug 06 08:09:46 PM PDT 24
Peak memory 207348 kb
Host smart-abea6a6e-393c-4981-ac35-954f74e5ea14
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=924135715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.924135715
Directory /workspace/177.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.3197068915
Short name T34
Test name
Test status
Simulation time 140468964 ps
CPU time 0.81 seconds
Started Aug 06 08:05:31 PM PDT 24
Finished Aug 06 08:05:32 PM PDT 24
Peak memory 207312 kb
Host smart-f690597e-fecd-4add-bdd9-98cc2f07a30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31970
68915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.3197068915
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.4138936939
Short name T45
Test name
Test status
Simulation time 181980379 ps
CPU time 1.05 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 207408 kb
Host smart-4f5bcce1-257b-44eb-bbe7-bc031205b104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41389
36939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4138936939
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/119.usbdev_endpoint_types.125575175
Short name T376
Test name
Test status
Simulation time 999751645 ps
CPU time 2.06 seconds
Started Aug 06 08:09:17 PM PDT 24
Finished Aug 06 08:09:19 PM PDT 24
Peak memory 207316 kb
Host smart-006b28d8-da11-40d5-a4c6-505fc6477a2c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=125575175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.125575175
Directory /workspace/119.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1240580625
Short name T556
Test name
Test status
Simulation time 147783314 ps
CPU time 0.84 seconds
Started Aug 06 08:00:40 PM PDT 24
Finished Aug 06 08:00:41 PM PDT 24
Peak memory 207336 kb
Host smart-b1fec878-3c4b-4f6d-ac27-ec3e7bff6178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12405
80625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1240580625
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.873449131
Short name T183
Test name
Test status
Simulation time 2917745065 ps
CPU time 28.62 seconds
Started Aug 06 08:00:51 PM PDT 24
Finished Aug 06 08:01:20 PM PDT 24
Peak memory 223980 kb
Host smart-e83f2092-ce1e-4cd1-8142-cfc0a60e38d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87344
9131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.873449131
Directory /workspace/0.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/112.usbdev_endpoint_types.645975610
Short name T2687
Test name
Test status
Simulation time 712112314 ps
CPU time 1.69 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207288 kb
Host smart-b0b1e54c-9c70-4388-b976-f0195cc5ac72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=645975610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.645975610
Directory /workspace/112.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/113.usbdev_endpoint_types.803866058
Short name T393
Test name
Test status
Simulation time 656546810 ps
CPU time 1.86 seconds
Started Aug 06 08:09:10 PM PDT 24
Finished Aug 06 08:09:12 PM PDT 24
Peak memory 207340 kb
Host smart-fb990f29-6ae0-4c81-bbc3-234e8144651c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=803866058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.803866058
Directory /workspace/113.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/171.usbdev_endpoint_types.1632284571
Short name T404
Test name
Test status
Simulation time 777800779 ps
CPU time 1.76 seconds
Started Aug 06 08:09:32 PM PDT 24
Finished Aug 06 08:09:34 PM PDT 24
Peak memory 207328 kb
Host smart-f8f0c91d-c980-47fe-868a-de7f9d0f09f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1632284571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.1632284571
Directory /workspace/171.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/49.usbdev_device_address.1035022920
Short name T197
Test name
Test status
Simulation time 34379970964 ps
CPU time 53.12 seconds
Started Aug 06 08:09:03 PM PDT 24
Finished Aug 06 08:09:56 PM PDT 24
Peak memory 207644 kb
Host smart-70e0842e-b72c-4f86-ba6d-44ebb5c1584a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10350
22920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.1035022920
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/130.usbdev_endpoint_types.978695879
Short name T350
Test name
Test status
Simulation time 830271155 ps
CPU time 1.89 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207424 kb
Host smart-d8fe1294-9972-491c-b8a4-f613ac23c794
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=978695879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.978695879
Directory /workspace/130.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/169.usbdev_endpoint_types.3591798104
Short name T459
Test name
Test status
Simulation time 727881933 ps
CPU time 1.77 seconds
Started Aug 06 08:09:21 PM PDT 24
Finished Aug 06 08:09:23 PM PDT 24
Peak memory 207296 kb
Host smart-37f20f10-4cbe-45e8-8d50-cb27e2baf525
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3591798104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.3591798104
Directory /workspace/169.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/75.usbdev_endpoint_types.2031595857
Short name T406
Test name
Test status
Simulation time 570904935 ps
CPU time 1.38 seconds
Started Aug 06 08:09:04 PM PDT 24
Finished Aug 06 08:09:05 PM PDT 24
Peak memory 207300 kb
Host smart-cde713ad-3974-49e7-a64a-11aa962d31d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2031595857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.2031595857
Directory /workspace/75.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_types.7368526
Short name T358
Test name
Test status
Simulation time 814158298 ps
CPU time 1.86 seconds
Started Aug 06 08:00:44 PM PDT 24
Finished Aug 06 08:00:46 PM PDT 24
Peak memory 207344 kb
Host smart-5dccbbe9-57cf-4350-b5f0-6bdabb53d9ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=7368526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.7368526
Directory /workspace/0.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/168.usbdev_endpoint_types.2399429612
Short name T429
Test name
Test status
Simulation time 631150991 ps
CPU time 1.69 seconds
Started Aug 06 08:09:21 PM PDT 24
Finished Aug 06 08:09:23 PM PDT 24
Peak memory 207336 kb
Host smart-85ae8cca-0845-4285-bc6a-38ab9e350b2b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2399429612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.2399429612
Directory /workspace/168.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_types.4116038523
Short name T442
Test name
Test status
Simulation time 641342753 ps
CPU time 1.71 seconds
Started Aug 06 08:03:08 PM PDT 24
Finished Aug 06 08:03:10 PM PDT 24
Peak memory 207272 kb
Host smart-39129cca-c572-4447-92e4-f5014cfe5bc9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4116038523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.4116038523
Directory /workspace/9.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1979698792
Short name T53
Test name
Test status
Simulation time 444090191 ps
CPU time 1.47 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:00:55 PM PDT 24
Peak memory 207320 kb
Host smart-328e83f5-0dbe-4ef2-818d-1fdb14d86fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19796
98792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1979698792
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2819093041
Short name T124
Test name
Test status
Simulation time 1911478098 ps
CPU time 20.9 seconds
Started Aug 06 08:03:40 PM PDT 24
Finished Aug 06 08:04:01 PM PDT 24
Peak memory 223804 kb
Host smart-229234c1-5057-45a1-b1a9-eec9ba1efe17
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2819093041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2819093041
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/167.usbdev_endpoint_types.2824564053
Short name T399
Test name
Test status
Simulation time 630755333 ps
CPU time 1.55 seconds
Started Aug 06 08:09:30 PM PDT 24
Finished Aug 06 08:09:32 PM PDT 24
Peak memory 207288 kb
Host smart-bf13d788-a9be-4c7a-aa26-418e379a3115
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2824564053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.2824564053
Directory /workspace/167.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.144552751
Short name T80
Test name
Test status
Simulation time 5538407700 ps
CPU time 46.44 seconds
Started Aug 06 08:00:54 PM PDT 24
Finished Aug 06 08:01:41 PM PDT 24
Peak memory 218288 kb
Host smart-012e625b-59e0-4c70-ada3-1db6ca499944
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144552751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.144552751
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2597707333
Short name T19
Test name
Test status
Simulation time 166637400 ps
CPU time 0.98 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207300 kb
Host smart-01cbfbe8-38e7-434f-8f44-5b92527b0742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25977
07333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2597707333
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/188.usbdev_endpoint_types.3810188907
Short name T98
Test name
Test status
Simulation time 547517985 ps
CPU time 1.54 seconds
Started Aug 06 08:09:26 PM PDT 24
Finished Aug 06 08:09:28 PM PDT 24
Peak memory 207368 kb
Host smart-1b01289f-1db0-449d-9864-5c614ea9c619
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3810188907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.3810188907
Directory /workspace/188.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3996012757
Short name T913
Test name
Test status
Simulation time 3976719710 ps
CPU time 41.08 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 218188 kb
Host smart-52391c68-cb8b-40e5-af26-87bbf30debc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39960
12757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3996012757
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/126.usbdev_endpoint_types.1781756464
Short name T348
Test name
Test status
Simulation time 818584955 ps
CPU time 1.89 seconds
Started Aug 06 08:09:02 PM PDT 24
Finished Aug 06 08:09:04 PM PDT 24
Peak memory 207364 kb
Host smart-41ee824c-3899-4c97-aace-1ea557783fc7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1781756464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.1781756464
Directory /workspace/126.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/151.usbdev_endpoint_types.4108508519
Short name T2931
Test name
Test status
Simulation time 646464774 ps
CPU time 1.69 seconds
Started Aug 06 08:09:22 PM PDT 24
Finished Aug 06 08:09:24 PM PDT 24
Peak memory 207284 kb
Host smart-fabd419f-f164-48e1-b530-189377f2b0e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4108508519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.4108508519
Directory /workspace/151.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/43.usbdev_rx_full.1005785070
Short name T320
Test name
Test status
Simulation time 247787208 ps
CPU time 1.06 seconds
Started Aug 06 08:08:18 PM PDT 24
Finished Aug 06 08:08:20 PM PDT 24
Peak memory 207312 kb
Host smart-a5c313df-63b6-44e4-be0e-4e268cc22661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10057
85070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.1005785070
Directory /workspace/43.usbdev_rx_full/latest

Test location /workspace/coverage/default/84.usbdev_endpoint_types.1772109020
Short name T354
Test name
Test status
Simulation time 822576356 ps
CPU time 1.85 seconds
Started Aug 06 08:09:20 PM PDT 24
Finished Aug 06 08:09:22 PM PDT 24
Peak memory 207388 kb
Host smart-259378f8-fd36-4266-992a-c36e446bc839
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1772109020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.1772109020
Directory /workspace/84.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.1665069499
Short name T71
Test name
Test status
Simulation time 412520835 ps
CPU time 1.5 seconds
Started Aug 06 08:00:43 PM PDT 24
Finished Aug 06 08:00:45 PM PDT 24
Peak memory 207252 kb
Host smart-ddec58aa-2129-4a91-8b1f-6eb484c628e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16650
69499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.1665069499
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3294447796
Short name T226
Test name
Test status
Simulation time 682595561 ps
CPU time 4.77 seconds
Started Aug 06 07:51:25 PM PDT 24
Finished Aug 06 07:51:30 PM PDT 24
Peak memory 207252 kb
Host smart-933b0584-22b3-4ee8-b5da-5c3a3af34849
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3294447796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3294447796
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.1503828315
Short name T61
Test name
Test status
Simulation time 163225279 ps
CPU time 0.85 seconds
Started Aug 06 08:00:41 PM PDT 24
Finished Aug 06 08:00:42 PM PDT 24
Peak memory 207332 kb
Host smart-373594d7-e852-4867-a58d-fb6334a23641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15038
28315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.1503828315
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4130450173
Short name T478
Test name
Test status
Simulation time 876600176 ps
CPU time 4.74 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:56 PM PDT 24
Peak memory 207268 kb
Host smart-1683e541-fc47-4df1-86bc-dbc42cbb982d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4130450173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.4130450173
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1488821505
Short name T31
Test name
Test status
Simulation time 5107448792 ps
CPU time 48.02 seconds
Started Aug 06 08:00:47 PM PDT 24
Finished Aug 06 08:01:35 PM PDT 24
Peak memory 207624 kb
Host smart-6d319a5e-bbe8-4038-a2d5-59fc74639b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14888
21505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1488821505
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/107.usbdev_endpoint_types.3569108429
Short name T362
Test name
Test status
Simulation time 584172272 ps
CPU time 1.64 seconds
Started Aug 06 08:09:03 PM PDT 24
Finished Aug 06 08:09:05 PM PDT 24
Peak memory 207344 kb
Host smart-82548df7-7c92-443b-bbe0-e9fd492b7b7a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3569108429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.3569108429
Directory /workspace/107.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/162.usbdev_endpoint_types.1159583020
Short name T461
Test name
Test status
Simulation time 524661053 ps
CPU time 1.55 seconds
Started Aug 06 08:09:30 PM PDT 24
Finished Aug 06 08:09:32 PM PDT 24
Peak memory 207288 kb
Host smart-e51d1a20-ca32-41aa-9999-f0a66cd2d0f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1159583020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.1159583020
Directory /workspace/162.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/189.usbdev_endpoint_types.3233091138
Short name T380
Test name
Test status
Simulation time 466891621 ps
CPU time 1.35 seconds
Started Aug 06 08:09:39 PM PDT 24
Finished Aug 06 08:09:40 PM PDT 24
Peak memory 207348 kb
Host smart-1c6330f8-c257-44ef-8d65-26e0fef94a86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3233091138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.3233091138
Directory /workspace/189.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_types.856854147
Short name T408
Test name
Test status
Simulation time 686574069 ps
CPU time 1.75 seconds
Started Aug 06 08:06:43 PM PDT 24
Finished Aug 06 08:06:45 PM PDT 24
Peak memory 207344 kb
Host smart-f80bf26b-15a9-418c-9ff8-3ab535ae8e62
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=856854147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.856854147
Directory /workspace/33.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_types.3505170867
Short name T332
Test name
Test status
Simulation time 635667189 ps
CPU time 1.52 seconds
Started Aug 06 08:07:36 PM PDT 24
Finished Aug 06 08:07:38 PM PDT 24
Peak memory 207340 kb
Host smart-4f4f2a16-484f-4c16-bd72-158948811d6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3505170867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.3505170867
Directory /workspace/39.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/58.usbdev_endpoint_types.662951002
Short name T368
Test name
Test status
Simulation time 671355440 ps
CPU time 1.49 seconds
Started Aug 06 08:08:57 PM PDT 24
Finished Aug 06 08:08:59 PM PDT 24
Peak memory 207380 kb
Host smart-0318bee0-7280-44b0-87d8-f6db669c2362
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=662951002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.662951002
Directory /workspace/58.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1329832070
Short name T262
Test name
Test status
Simulation time 258397179 ps
CPU time 3.28 seconds
Started Aug 06 07:51:23 PM PDT 24
Finished Aug 06 07:51:26 PM PDT 24
Peak memory 220776 kb
Host smart-71e40d47-17a2-421c-b3b9-c3899bea353e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1329832070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1329832070
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2717370792
Short name T174
Test name
Test status
Simulation time 227636103 ps
CPU time 1.03 seconds
Started Aug 06 08:03:34 PM PDT 24
Finished Aug 06 08:03:35 PM PDT 24
Peak memory 207356 kb
Host smart-9ccc4e9b-f8ea-4132-8386-9837b8bd6d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27173
70792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2717370792
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.995266695
Short name T157
Test name
Test status
Simulation time 203189862 ps
CPU time 0.98 seconds
Started Aug 06 08:04:10 PM PDT 24
Finished Aug 06 08:04:11 PM PDT 24
Peak memory 207316 kb
Host smart-d6fd0099-890c-4563-bb9a-492ce9f76e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99526
6695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.995266695
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.2418238605
Short name T192
Test name
Test status
Simulation time 6582478433 ps
CPU time 28.7 seconds
Started Aug 06 08:02:00 PM PDT 24
Finished Aug 06 08:02:29 PM PDT 24
Peak memory 219492 kb
Host smart-35b57497-5260-4137-bc9b-6d72eeb5db1b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418238605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2418238605
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3790512424
Short name T3166
Test name
Test status
Simulation time 49350501 ps
CPU time 0.73 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 206944 kb
Host smart-3663878c-e43d-4bbc-a475-199069e771dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3790512424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3790512424
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1070439481
Short name T475
Test name
Test status
Simulation time 1483315677 ps
CPU time 5.74 seconds
Started Aug 06 07:51:43 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 207252 kb
Host smart-738f9899-c41d-4312-9e51-2ce6670cd54c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1070439481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1070439481
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.1371763351
Short name T336
Test name
Test status
Simulation time 114096340921 ps
CPU time 169 seconds
Started Aug 06 08:00:42 PM PDT 24
Finished Aug 06 08:03:31 PM PDT 24
Peak memory 207680 kb
Host smart-a32258ec-5045-41b8-8136-0839ede12fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371763351 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.1371763351
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3686565002
Short name T620
Test name
Test status
Simulation time 164748232 ps
CPU time 0.89 seconds
Started Aug 06 08:03:29 PM PDT 24
Finished Aug 06 08:03:30 PM PDT 24
Peak memory 207336 kb
Host smart-aaffcbca-0671-4f5c-8d55-affd65f52cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36865
65002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3686565002
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3714197816
Short name T469
Test name
Test status
Simulation time 186124957 ps
CPU time 0.86 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207400 kb
Host smart-50e0478e-4925-48de-ba1a-8c17d78f50dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37141
97816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3714197816
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/121.usbdev_endpoint_types.1756877040
Short name T377
Test name
Test status
Simulation time 804300104 ps
CPU time 1.86 seconds
Started Aug 06 08:09:04 PM PDT 24
Finished Aug 06 08:09:06 PM PDT 24
Peak memory 207304 kb
Host smart-7b419a1f-4613-4b79-aeb9-d86477fec164
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1756877040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.1756877040
Directory /workspace/121.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/122.usbdev_endpoint_types.1578972455
Short name T438
Test name
Test status
Simulation time 905536572 ps
CPU time 2.12 seconds
Started Aug 06 08:09:12 PM PDT 24
Finished Aug 06 08:09:15 PM PDT 24
Peak memory 207328 kb
Host smart-e8fb7416-f8c9-4d8d-a64a-60b9e53385e1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1578972455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.1578972455
Directory /workspace/122.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/136.usbdev_endpoint_types.1112392142
Short name T409
Test name
Test status
Simulation time 563175570 ps
CPU time 1.53 seconds
Started Aug 06 08:09:13 PM PDT 24
Finished Aug 06 08:09:14 PM PDT 24
Peak memory 207348 kb
Host smart-8a5ee4f1-9ad4-4487-ade0-dc50ab73d925
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1112392142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.1112392142
Directory /workspace/136.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/165.usbdev_endpoint_types.4262941252
Short name T396
Test name
Test status
Simulation time 754084100 ps
CPU time 1.94 seconds
Started Aug 06 08:09:29 PM PDT 24
Finished Aug 06 08:09:31 PM PDT 24
Peak memory 207208 kb
Host smart-d08075af-a78f-400b-9cb3-8af8f2f12040
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4262941252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.4262941252
Directory /workspace/165.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/184.usbdev_endpoint_types.1462686423
Short name T387
Test name
Test status
Simulation time 581144791 ps
CPU time 1.46 seconds
Started Aug 06 08:09:34 PM PDT 24
Finished Aug 06 08:09:35 PM PDT 24
Peak memory 207328 kb
Host smart-0b048a3e-f6ad-417d-b911-2f6727e67400
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1462686423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.1462686423
Directory /workspace/184.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/190.usbdev_endpoint_types.1492415235
Short name T374
Test name
Test status
Simulation time 588617966 ps
CPU time 1.47 seconds
Started Aug 06 08:09:41 PM PDT 24
Finished Aug 06 08:09:42 PM PDT 24
Peak memory 207376 kb
Host smart-d91a079a-17ba-46e6-b07c-19e5e0c24a17
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1492415235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.1492415235
Directory /workspace/190.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_rx_full.2071678054
Short name T324
Test name
Test status
Simulation time 437086556 ps
CPU time 1.42 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 207128 kb
Host smart-a864c56e-e8f4-4791-a39f-528a7f11923b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20716
78054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.2071678054
Directory /workspace/2.usbdev_rx_full/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1572226282
Short name T486
Test name
Test status
Simulation time 2508611047 ps
CPU time 18.74 seconds
Started Aug 06 08:06:31 PM PDT 24
Finished Aug 06 08:06:50 PM PDT 24
Peak memory 218296 kb
Host smart-606ceb4e-cf59-4829-bf60-742ee8cad896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15722
26282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1572226282
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_types.3358328187
Short name T103
Test name
Test status
Simulation time 808584016 ps
CPU time 1.71 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207328 kb
Host smart-2d3c555e-d197-4fbe-890f-1eff12206a62
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3358328187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.3358328187
Directory /workspace/44.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/74.usbdev_endpoint_types.788286122
Short name T437
Test name
Test status
Simulation time 275918103 ps
CPU time 1.08 seconds
Started Aug 06 08:08:57 PM PDT 24
Finished Aug 06 08:08:58 PM PDT 24
Peak memory 207380 kb
Host smart-31e58900-8a13-41da-b9a5-c3b5a4122f79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=788286122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.788286122
Directory /workspace/74.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.274621479
Short name T218
Test name
Test status
Simulation time 147356978 ps
CPU time 0.81 seconds
Started Aug 06 08:01:22 PM PDT 24
Finished Aug 06 08:01:23 PM PDT 24
Peak memory 207316 kb
Host smart-db614c4b-5d2d-4e1b-916f-c4a89d4c88cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27462
1479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.274621479
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.432554150
Short name T106
Test name
Test status
Simulation time 149847189 ps
CPU time 0.84 seconds
Started Aug 06 08:01:06 PM PDT 24
Finished Aug 06 08:01:07 PM PDT 24
Peak memory 207304 kb
Host smart-3196ccea-2795-4533-bd40-e6254628336a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43255
4150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.432554150
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2521515969
Short name T37
Test name
Test status
Simulation time 44330230 ps
CPU time 0.68 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:04:39 PM PDT 24
Peak memory 207320 kb
Host smart-ea842d61-5acc-42c8-9e0a-b91176e1b4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25215
15969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2521515969
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3831385933
Short name T58
Test name
Test status
Simulation time 205030834 ps
CPU time 0.94 seconds
Started Aug 06 08:00:43 PM PDT 24
Finished Aug 06 08:00:44 PM PDT 24
Peak memory 207324 kb
Host smart-f7678087-cd02-4099-b845-40b57a9939bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38313
85933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3831385933
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3473450593
Short name T41
Test name
Test status
Simulation time 4169491833 ps
CPU time 9.85 seconds
Started Aug 06 08:00:44 PM PDT 24
Finished Aug 06 08:00:54 PM PDT 24
Peak memory 207668 kb
Host smart-f463a0e3-5eb4-471a-90e6-3ba5e0a61b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34734
50593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3473450593
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1711395814
Short name T65
Test name
Test status
Simulation time 181739067 ps
CPU time 0.9 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:00:55 PM PDT 24
Peak memory 207416 kb
Host smart-00516761-0ad0-4b00-b3b2-223e5447ab3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17113
95814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1711395814
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2211758900
Short name T2071
Test name
Test status
Simulation time 215436215 ps
CPU time 0.91 seconds
Started Aug 06 08:00:54 PM PDT 24
Finished Aug 06 08:00:55 PM PDT 24
Peak memory 207372 kb
Host smart-d8e78b0b-ba12-4e0e-ab46-19082d076a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22117
58900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2211758900
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2281893744
Short name T84
Test name
Test status
Simulation time 6803377818 ps
CPU time 31.05 seconds
Started Aug 06 08:01:39 PM PDT 24
Finished Aug 06 08:02:11 PM PDT 24
Peak memory 219120 kb
Host smart-718c8fed-8992-456b-82e9-8a607fcf3ded
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281893744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.2281893744
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.3649371613
Short name T48
Test name
Test status
Simulation time 155805331 ps
CPU time 0.85 seconds
Started Aug 06 08:01:38 PM PDT 24
Finished Aug 06 08:01:38 PM PDT 24
Peak memory 207328 kb
Host smart-e0a61ba7-c084-422b-ba44-6d5b2a8fa733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36493
71613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3649371613
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.828452684
Short name T186
Test name
Test status
Simulation time 6896313704 ps
CPU time 32.82 seconds
Started Aug 06 08:03:04 PM PDT 24
Finished Aug 06 08:03:37 PM PDT 24
Peak memory 224028 kb
Host smart-12a29f92-15d7-461f-acc4-54554f867a68
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=828452684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.828452684
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3837443709
Short name T268
Test name
Test status
Simulation time 802485977 ps
CPU time 5.31 seconds
Started Aug 06 07:51:45 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 207288 kb
Host smart-e5d0344d-3eb8-4ea8-936d-34bf5e9a388f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3837443709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3837443709
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.275967907
Short name T251
Test name
Test status
Simulation time 843630481 ps
CPU time 5 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:55 PM PDT 24
Peak memory 207272 kb
Host smart-59e7d78b-af34-46ef-9c06-1233af881a59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=275967907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.275967907
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.368698307
Short name T886
Test name
Test status
Simulation time 306211807 ps
CPU time 2.35 seconds
Started Aug 06 08:01:05 PM PDT 24
Finished Aug 06 08:01:08 PM PDT 24
Peak memory 207388 kb
Host smart-6e8d8501-05f5-4ce1-89b2-53954f2fefff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36869
8307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.368698307
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.188438159
Short name T160
Test name
Test status
Simulation time 172630266 ps
CPU time 0.88 seconds
Started Aug 06 08:01:04 PM PDT 24
Finished Aug 06 08:01:05 PM PDT 24
Peak memory 207344 kb
Host smart-7ac98d15-c85f-4ce2-b97a-910e9e699671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18843
8159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.188438159
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2342399800
Short name T150
Test name
Test status
Simulation time 227858244 ps
CPU time 1 seconds
Started Aug 06 08:03:23 PM PDT 24
Finished Aug 06 08:03:24 PM PDT 24
Peak memory 207372 kb
Host smart-b23a9fd1-c269-4312-9ea3-534d2a587845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23423
99800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2342399800
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.4064979417
Short name T163
Test name
Test status
Simulation time 224502037 ps
CPU time 1.01 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:10 PM PDT 24
Peak memory 207416 kb
Host smart-531529d5-83e8-47da-86bf-6b31ffd7ae4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40649
79417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.4064979417
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.326901669
Short name T142
Test name
Test status
Simulation time 233392010 ps
CPU time 0.97 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:25 PM PDT 24
Peak memory 207400 kb
Host smart-43387d3b-50a4-4ebd-a993-9cefdd641a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32690
1669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.326901669
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3423107818
Short name T148
Test name
Test status
Simulation time 185026902 ps
CPU time 0.86 seconds
Started Aug 06 08:04:37 PM PDT 24
Finished Aug 06 08:04:38 PM PDT 24
Peak memory 207372 kb
Host smart-fdb8659c-5f15-4a3d-ac02-bb29b7695ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34231
07818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3423107818
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2142900994
Short name T1769
Test name
Test status
Simulation time 195883065 ps
CPU time 0.92 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 207304 kb
Host smart-b5c5c255-308f-469a-8ee5-512bb46ecd09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21429
00994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2142900994
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3343863459
Short name T169
Test name
Test status
Simulation time 212449594 ps
CPU time 0.93 seconds
Started Aug 06 08:05:21 PM PDT 24
Finished Aug 06 08:05:22 PM PDT 24
Peak memory 207364 kb
Host smart-b5be16b8-ebbf-4fff-8389-f9c6d92aa2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33438
63459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3343863459
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.364968904
Short name T154
Test name
Test status
Simulation time 203612876 ps
CPU time 0.93 seconds
Started Aug 06 08:05:55 PM PDT 24
Finished Aug 06 08:05:56 PM PDT 24
Peak memory 207372 kb
Host smart-cb0308c0-eec6-4bad-be53-88529c7a1a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36496
8904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.364968904
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_types.660674369
Short name T149
Test name
Test status
Simulation time 810157797 ps
CPU time 1.88 seconds
Started Aug 06 08:02:29 PM PDT 24
Finished Aug 06 08:02:31 PM PDT 24
Peak memory 207324 kb
Host smart-9e6c85b9-2eae-455d-a2a8-f59a134032c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=660674369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.660674369
Directory /workspace/5.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2234149642
Short name T146
Test name
Test status
Simulation time 233846245 ps
CPU time 1.01 seconds
Started Aug 06 08:02:30 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207340 kb
Host smart-eda651e7-f940-4d40-aa3b-3d454a4002c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22341
49642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2234149642
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1257021239
Short name T191
Test name
Test status
Simulation time 7418370259 ps
CPU time 44.09 seconds
Started Aug 06 08:03:18 PM PDT 24
Finished Aug 06 08:04:02 PM PDT 24
Peak memory 224024 kb
Host smart-ac1131e1-ec7d-4c9a-83ca-754cd933a518
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1257021239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1257021239
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4230079947
Short name T3217
Test name
Test status
Simulation time 307180674 ps
CPU time 3.58 seconds
Started Aug 06 07:51:26 PM PDT 24
Finished Aug 06 07:51:29 PM PDT 24
Peak memory 207108 kb
Host smart-335c6328-814c-415b-9b24-1d3d4b45c59c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4230079947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.4230079947
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2760844882
Short name T290
Test name
Test status
Simulation time 700298563 ps
CPU time 4.5 seconds
Started Aug 06 07:51:20 PM PDT 24
Finished Aug 06 07:51:24 PM PDT 24
Peak memory 207252 kb
Host smart-16ae8321-b5b9-4f10-9213-dc69eb835b8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2760844882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2760844882
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3104067864
Short name T3151
Test name
Test status
Simulation time 121108417 ps
CPU time 0.94 seconds
Started Aug 06 07:51:20 PM PDT 24
Finished Aug 06 07:51:21 PM PDT 24
Peak memory 206988 kb
Host smart-56b9b5cb-cc52-4723-a809-5a07b3ed981f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3104067864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3104067864
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3370989186
Short name T249
Test name
Test status
Simulation time 124987218 ps
CPU time 1.8 seconds
Started Aug 06 07:51:26 PM PDT 24
Finished Aug 06 07:51:27 PM PDT 24
Peak memory 215396 kb
Host smart-3431c90d-63b8-4f58-b0fe-eb666ecfbf87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370989186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3370989186
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.601644189
Short name T3144
Test name
Test status
Simulation time 55487055 ps
CPU time 0.82 seconds
Started Aug 06 07:51:19 PM PDT 24
Finished Aug 06 07:51:20 PM PDT 24
Peak memory 206952 kb
Host smart-2219abda-0489-42d5-8a28-75d3af65daf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=601644189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.601644189
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.318524206
Short name T3198
Test name
Test status
Simulation time 38829328 ps
CPU time 0.74 seconds
Started Aug 06 07:51:24 PM PDT 24
Finished Aug 06 07:51:25 PM PDT 24
Peak memory 206760 kb
Host smart-50e6c991-c06c-44a8-830a-71da4ed04911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=318524206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.318524206
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.578106490
Short name T297
Test name
Test status
Simulation time 77933171 ps
CPU time 2.15 seconds
Started Aug 06 07:51:26 PM PDT 24
Finished Aug 06 07:51:29 PM PDT 24
Peak memory 215404 kb
Host smart-42d26187-2eaf-47dc-8b37-02d062a151fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=578106490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.578106490
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.701772356
Short name T3126
Test name
Test status
Simulation time 270918085 ps
CPU time 2.57 seconds
Started Aug 06 07:51:22 PM PDT 24
Finished Aug 06 07:51:24 PM PDT 24
Peak memory 207172 kb
Host smart-41e757e1-c503-4fa0-8708-513d1d71c16f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=701772356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.701772356
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1371319586
Short name T3182
Test name
Test status
Simulation time 219509774 ps
CPU time 1.94 seconds
Started Aug 06 07:51:31 PM PDT 24
Finished Aug 06 07:51:33 PM PDT 24
Peak memory 207256 kb
Host smart-be4bba10-7b92-4182-9fe5-48fddcf1ed90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1371319586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1371319586
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3252915362
Short name T265
Test name
Test status
Simulation time 56459309 ps
CPU time 1.55 seconds
Started Aug 06 07:51:20 PM PDT 24
Finished Aug 06 07:51:22 PM PDT 24
Peak memory 207272 kb
Host smart-3931b715-20ed-499f-a4bd-ab227064df35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3252915362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3252915362
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1725303052
Short name T3156
Test name
Test status
Simulation time 298212786 ps
CPU time 2.53 seconds
Started Aug 06 07:51:29 PM PDT 24
Finished Aug 06 07:51:31 PM PDT 24
Peak memory 207236 kb
Host smart-0ce0e245-db09-4557-b842-619294faf328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1725303052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1725303052
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3268396665
Short name T3188
Test name
Test status
Simulation time 97405867 ps
CPU time 1.93 seconds
Started Aug 06 07:51:21 PM PDT 24
Finished Aug 06 07:51:23 PM PDT 24
Peak memory 207156 kb
Host smart-e1d354ae-7c94-4c7f-98a5-97e0a8551fa9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3268396665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3268396665
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2875464412
Short name T228
Test name
Test status
Simulation time 1070334937 ps
CPU time 4.75 seconds
Started Aug 06 07:51:29 PM PDT 24
Finished Aug 06 07:51:34 PM PDT 24
Peak memory 207240 kb
Host smart-40482b39-f468-4ae7-b2ae-ae87c3e5515a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2875464412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2875464412
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3177399492
Short name T3185
Test name
Test status
Simulation time 107627162 ps
CPU time 0.94 seconds
Started Aug 06 07:51:28 PM PDT 24
Finished Aug 06 07:51:29 PM PDT 24
Peak memory 206864 kb
Host smart-9689197c-5629-4e2c-8cd9-4138b1281705
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3177399492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3177399492
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.128733949
Short name T3137
Test name
Test status
Simulation time 115810681 ps
CPU time 1.32 seconds
Started Aug 06 07:51:23 PM PDT 24
Finished Aug 06 07:51:25 PM PDT 24
Peak memory 215452 kb
Host smart-84abe4bb-4623-469a-adcd-4f4723e63aa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128733949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.128733949
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.12888428
Short name T3205
Test name
Test status
Simulation time 103047645 ps
CPU time 0.9 seconds
Started Aug 06 07:51:32 PM PDT 24
Finished Aug 06 07:51:33 PM PDT 24
Peak memory 207084 kb
Host smart-55e959d6-f1bd-4d17-8078-f7b7ac10e5c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=12888428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.12888428
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.933133662
Short name T3212
Test name
Test status
Simulation time 32018397 ps
CPU time 0.77 seconds
Started Aug 06 07:51:25 PM PDT 24
Finished Aug 06 07:51:26 PM PDT 24
Peak memory 206892 kb
Host smart-40fc5d2a-1fbf-47a0-b766-d201bc8bae4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=933133662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.933133662
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3659162993
Short name T3219
Test name
Test status
Simulation time 80679398 ps
CPU time 2.23 seconds
Started Aug 06 07:51:27 PM PDT 24
Finished Aug 06 07:51:29 PM PDT 24
Peak memory 215416 kb
Host smart-3aa7f3dd-3ae7-4211-a6d4-96999cc81ae8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3659162993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3659162993
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3338105871
Short name T3154
Test name
Test status
Simulation time 108764611 ps
CPU time 2.42 seconds
Started Aug 06 07:51:27 PM PDT 24
Finished Aug 06 07:51:29 PM PDT 24
Peak memory 207120 kb
Host smart-8049376b-8ef9-40cc-9122-4ed50c04c268
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3338105871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3338105871
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1245237222
Short name T3175
Test name
Test status
Simulation time 251189471 ps
CPU time 1.77 seconds
Started Aug 06 07:51:22 PM PDT 24
Finished Aug 06 07:51:24 PM PDT 24
Peak memory 207200 kb
Host smart-5b5be27c-b7b4-430c-a68b-5b268ca37928
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1245237222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1245237222
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.890159865
Short name T3142
Test name
Test status
Simulation time 264520444 ps
CPU time 3.43 seconds
Started Aug 06 07:51:25 PM PDT 24
Finished Aug 06 07:51:29 PM PDT 24
Peak memory 222972 kb
Host smart-1477a325-638c-42b4-84b0-4adc3674f5bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=890159865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.890159865
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3526790430
Short name T473
Test name
Test status
Simulation time 354731797 ps
CPU time 2.62 seconds
Started Aug 06 07:51:29 PM PDT 24
Finished Aug 06 07:51:32 PM PDT 24
Peak memory 207284 kb
Host smart-9e16ca62-4a87-486a-b7d6-418bc659861a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3526790430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3526790430
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3841236251
Short name T301
Test name
Test status
Simulation time 81696466 ps
CPU time 1 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 206968 kb
Host smart-f75fb217-01ee-4e93-9a41-e3b82f02d191
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3841236251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3841236251
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4073193240
Short name T3172
Test name
Test status
Simulation time 45390049 ps
CPU time 0.73 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:48 PM PDT 24
Peak memory 206860 kb
Host smart-7f2a309f-aa53-4fec-80fc-9179233e0cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4073193240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.4073193240
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1588390948
Short name T3164
Test name
Test status
Simulation time 233355486 ps
CPU time 1.34 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 207028 kb
Host smart-1a46960b-89f8-4eda-aa72-919c8714f950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1588390948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1588390948
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3294813380
Short name T3227
Test name
Test status
Simulation time 108044113 ps
CPU time 2.99 seconds
Started Aug 06 07:51:44 PM PDT 24
Finished Aug 06 07:51:47 PM PDT 24
Peak memory 220848 kb
Host smart-7db904fc-254f-4248-9477-710a6ea414b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3294813380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3294813380
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1861596740
Short name T3201
Test name
Test status
Simulation time 497857791 ps
CPU time 2.95 seconds
Started Aug 06 07:51:45 PM PDT 24
Finished Aug 06 07:51:48 PM PDT 24
Peak memory 207320 kb
Host smart-28a8baee-6d22-46ea-89a5-742627a71702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1861596740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1861596740
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3574874459
Short name T311
Test name
Test status
Simulation time 198011940 ps
CPU time 1.91 seconds
Started Aug 06 07:51:44 PM PDT 24
Finished Aug 06 07:51:46 PM PDT 24
Peak memory 215472 kb
Host smart-801651ec-1686-4bff-8418-3bf703d3ab50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574874459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3574874459
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3709418222
Short name T3222
Test name
Test status
Simulation time 85113854 ps
CPU time 0.98 seconds
Started Aug 06 07:51:44 PM PDT 24
Finished Aug 06 07:51:45 PM PDT 24
Peak memory 207060 kb
Host smart-f4ea1162-774e-4963-9cc0-997c589f19d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3709418222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3709418222
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1627663097
Short name T337
Test name
Test status
Simulation time 36511146 ps
CPU time 0.68 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:48 PM PDT 24
Peak memory 206892 kb
Host smart-dbd4ab98-4b93-4e72-b71c-9f4834f9dd51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1627663097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1627663097
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4125939281
Short name T3192
Test name
Test status
Simulation time 171473910 ps
CPU time 1.2 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 207316 kb
Host smart-474a29e6-6935-412e-b176-8779bcb75dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4125939281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.4125939281
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1747931323
Short name T3165
Test name
Test status
Simulation time 120703292 ps
CPU time 1.64 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 207192 kb
Host smart-3180dca7-dd65-477a-bf5e-8daf6263ff48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1747931323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1747931323
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1341979060
Short name T3177
Test name
Test status
Simulation time 779125021 ps
CPU time 3.27 seconds
Started Aug 06 07:51:46 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 207316 kb
Host smart-596240e1-8ada-4acb-8c68-cd7b84cb758e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1341979060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1341979060
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.691508960
Short name T3194
Test name
Test status
Simulation time 109877484 ps
CPU time 1.22 seconds
Started Aug 06 07:51:46 PM PDT 24
Finished Aug 06 07:51:47 PM PDT 24
Peak memory 215268 kb
Host smart-d1a64e19-c97d-49df-818e-866a4fa2118b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691508960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.691508960
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.629107779
Short name T303
Test name
Test status
Simulation time 148732561 ps
CPU time 1.02 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:48 PM PDT 24
Peak memory 207036 kb
Host smart-9b0ede76-9688-42e3-b8cd-990fd4027266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=629107779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.629107779
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1916108528
Short name T3215
Test name
Test status
Simulation time 44148020 ps
CPU time 0.72 seconds
Started Aug 06 07:51:52 PM PDT 24
Finished Aug 06 07:51:53 PM PDT 24
Peak memory 206984 kb
Host smart-ee4f2b92-f0b6-4e12-8d67-788900c5df31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1916108528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1916108528
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3531419773
Short name T302
Test name
Test status
Simulation time 235260262 ps
CPU time 1.65 seconds
Started Aug 06 07:51:44 PM PDT 24
Finished Aug 06 07:51:46 PM PDT 24
Peak memory 207256 kb
Host smart-8a336262-2416-458e-bd72-a222ce58b4bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3531419773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3531419773
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2488998082
Short name T256
Test name
Test status
Simulation time 143928773 ps
CPU time 1.8 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 207204 kb
Host smart-4cc1dee7-318a-4e90-b129-355cb62f727a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2488998082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2488998082
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2776111223
Short name T3162
Test name
Test status
Simulation time 577917507 ps
CPU time 4.32 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 207272 kb
Host smart-d393ffcd-7490-4a17-9ce9-ef85d70e9cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2776111223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2776111223
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1251350005
Short name T250
Test name
Test status
Simulation time 79784556 ps
CPU time 2.11 seconds
Started Aug 06 07:51:46 PM PDT 24
Finished Aug 06 07:51:48 PM PDT 24
Peak memory 215368 kb
Host smart-22b90dae-cb3f-49c2-9297-d2579d6ad248
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251350005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1251350005
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1593796426
Short name T3197
Test name
Test status
Simulation time 66038463 ps
CPU time 0.9 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 206968 kb
Host smart-1f8e67cc-cff8-4169-8692-3831060e2875
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1593796426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1593796426
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3629107454
Short name T3130
Test name
Test status
Simulation time 41313243 ps
CPU time 0.67 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:47 PM PDT 24
Peak memory 206884 kb
Host smart-8b8958cf-bc89-4a79-98f3-3498968c7c4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3629107454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3629107454
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2338436801
Short name T3186
Test name
Test status
Simulation time 172132636 ps
CPU time 1.6 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 207356 kb
Host smart-1c99b4fb-31d2-47e3-a3a0-4a24a902adc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2338436801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2338436801
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2432455807
Short name T263
Test name
Test status
Simulation time 197506846 ps
CPU time 2.55 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 207252 kb
Host smart-30c05321-4b60-48d0-82a6-2732b3e30863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2432455807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2432455807
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.683326595
Short name T3173
Test name
Test status
Simulation time 446258939 ps
CPU time 2.93 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 207212 kb
Host smart-04da46d3-fd76-4a7d-aa9d-6a66b81c14a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=683326595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.683326595
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.392949185
Short name T312
Test name
Test status
Simulation time 164282772 ps
CPU time 2.05 seconds
Started Aug 06 07:51:46 PM PDT 24
Finished Aug 06 07:51:48 PM PDT 24
Peak memory 215520 kb
Host smart-15beae95-f99f-43ec-bf5f-9406ab9622a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392949185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.392949185
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.328107116
Short name T3230
Test name
Test status
Simulation time 93281077 ps
CPU time 1.06 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 207068 kb
Host smart-09ca6b09-c60d-4d41-9c32-930ea8e6e7ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=328107116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.328107116
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2697361892
Short name T314
Test name
Test status
Simulation time 102874439 ps
CPU time 0.74 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 206780 kb
Host smart-acf0187a-5039-4868-bbdc-055bc836cde3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2697361892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.2697361892
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2445504882
Short name T3226
Test name
Test status
Simulation time 130565176 ps
CPU time 1.22 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 207320 kb
Host smart-0bef6c85-e477-456c-ad16-8382d6420578
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2445504882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2445504882
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.592983603
Short name T3206
Test name
Test status
Simulation time 84407244 ps
CPU time 1.86 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 207264 kb
Host smart-eec5b422-9d98-411e-a871-3e72a615cbfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=592983603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.592983603
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.4150938725
Short name T3189
Test name
Test status
Simulation time 204006226 ps
CPU time 2 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 215448 kb
Host smart-33b57ac0-2d72-4fa2-b963-38c15333c35c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150938725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.4150938725
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.842986456
Short name T305
Test name
Test status
Simulation time 84677636 ps
CPU time 0.88 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:48 PM PDT 24
Peak memory 207032 kb
Host smart-14988d03-4399-4926-b142-287b88776bdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=842986456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.842986456
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1564013971
Short name T3178
Test name
Test status
Simulation time 70916247 ps
CPU time 1.38 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:48 PM PDT 24
Peak memory 207272 kb
Host smart-390b7aaa-f5fa-44aa-a114-33c84d081a1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1564013971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1564013971
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3829915678
Short name T3234
Test name
Test status
Simulation time 144828964 ps
CPU time 3.92 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 223588 kb
Host smart-6510bd7d-bbec-435c-9bf3-e13a00b68030
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3829915678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3829915678
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1862706476
Short name T3216
Test name
Test status
Simulation time 292609969 ps
CPU time 2.61 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:53 PM PDT 24
Peak memory 207336 kb
Host smart-b7c307e7-4d54-4428-9463-2ffc03a15bce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1862706476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1862706476
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1180134355
Short name T3210
Test name
Test status
Simulation time 179204415 ps
CPU time 1.83 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 215500 kb
Host smart-134c13d2-fb04-4630-94ee-d217a9f1e020
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180134355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1180134355
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3160062443
Short name T252
Test name
Test status
Simulation time 54659551 ps
CPU time 0.84 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 207096 kb
Host smart-643ca7e0-0cd9-44b3-b07f-fb7062b74ddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3160062443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3160062443
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4085699749
Short name T342
Test name
Test status
Simulation time 92818248 ps
CPU time 0.82 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 206924 kb
Host smart-c378c161-11de-459f-ab17-34cf68beb864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4085699749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.4085699749
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2107418119
Short name T3148
Test name
Test status
Simulation time 187893988 ps
CPU time 1.41 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 207344 kb
Host smart-574890c1-d730-4b9e-8a2e-55334c96064c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2107418119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2107418119
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1544962731
Short name T3223
Test name
Test status
Simulation time 149604757 ps
CPU time 2.12 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 207232 kb
Host smart-4eb5a2a2-8f02-411d-b8b6-c1e032d4917b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1544962731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1544962731
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1434721835
Short name T3193
Test name
Test status
Simulation time 96810412 ps
CPU time 1.31 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 215516 kb
Host smart-2d19e490-5cfc-4b54-aaba-09c46161bed0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434721835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1434721835
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4259548672
Short name T291
Test name
Test status
Simulation time 61766953 ps
CPU time 0.8 seconds
Started Aug 06 07:52:11 PM PDT 24
Finished Aug 06 07:52:12 PM PDT 24
Peak memory 207048 kb
Host smart-87d979e2-3559-43ec-9c6f-445aab74397b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4259548672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.4259548672
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3767560288
Short name T3158
Test name
Test status
Simulation time 46431890 ps
CPU time 0.75 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 206856 kb
Host smart-304cf0a9-cf1d-40a1-962e-0fe38dbe3d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3767560288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3767560288
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1370869863
Short name T3180
Test name
Test status
Simulation time 218820051 ps
CPU time 1.58 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:52:00 PM PDT 24
Peak memory 207324 kb
Host smart-97bd11e0-c750-4bf9-ae00-be8aef348bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1370869863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1370869863
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2900069392
Short name T3135
Test name
Test status
Simulation time 109323917 ps
CPU time 1.52 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 207232 kb
Host smart-8628c025-ec99-4b04-bb8d-d46c7bd68043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2900069392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2900069392
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.129124412
Short name T3167
Test name
Test status
Simulation time 87929984 ps
CPU time 1.15 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:51:59 PM PDT 24
Peak memory 215396 kb
Host smart-8a688e9e-b156-4b44-820f-5bed6ab92e7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129124412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde
v_csr_mem_rw_with_rand_reset.129124412
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1276745289
Short name T295
Test name
Test status
Simulation time 43245180 ps
CPU time 0.95 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 207104 kb
Host smart-b5b7463e-b2b9-4be3-8c85-aff5c179fc35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1276745289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1276745289
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.995018251
Short name T339
Test name
Test status
Simulation time 36221573 ps
CPU time 0.67 seconds
Started Aug 06 07:51:52 PM PDT 24
Finished Aug 06 07:51:53 PM PDT 24
Peak memory 206924 kb
Host smart-57644adf-d826-4cbc-90d5-277d408b330f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=995018251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.995018251
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.160036988
Short name T300
Test name
Test status
Simulation time 261696332 ps
CPU time 1.99 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:02 PM PDT 24
Peak memory 207296 kb
Host smart-edcccd0f-c867-4eea-9fdd-001256b52a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=160036988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.160036988
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3284411702
Short name T3169
Test name
Test status
Simulation time 84780139 ps
CPU time 1.63 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 207312 kb
Host smart-10b132d8-27a9-440f-836b-b6d0f4df94c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3284411702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3284411702
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.689923427
Short name T3152
Test name
Test status
Simulation time 165494365 ps
CPU time 2.28 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:53 PM PDT 24
Peak memory 215420 kb
Host smart-1fe0ca0d-9694-4186-9d49-b33a521041e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689923427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.689923427
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4132231890
Short name T3211
Test name
Test status
Simulation time 39395159 ps
CPU time 0.79 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 207076 kb
Host smart-55f1d9bd-b41f-4c74-a719-a0dc26c9c23a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4132231890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4132231890
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3871126844
Short name T233
Test name
Test status
Simulation time 39861507 ps
CPU time 0.71 seconds
Started Aug 06 07:51:52 PM PDT 24
Finished Aug 06 07:51:53 PM PDT 24
Peak memory 206928 kb
Host smart-64f46f97-d9f5-41a8-890f-920567794e7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3871126844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3871126844
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.271050219
Short name T3174
Test name
Test status
Simulation time 96370475 ps
CPU time 1.51 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 207168 kb
Host smart-8e4440c7-df95-416a-b8d6-a4be5e16acbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=271050219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.271050219
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3146784713
Short name T3184
Test name
Test status
Simulation time 86007441 ps
CPU time 2.08 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:52:01 PM PDT 24
Peak memory 207272 kb
Host smart-b3d5d1f0-193a-4714-af8b-0848154f8d57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3146784713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3146784713
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.18169202
Short name T477
Test name
Test status
Simulation time 988573030 ps
CPU time 4.81 seconds
Started Aug 06 07:52:03 PM PDT 24
Finished Aug 06 07:52:08 PM PDT 24
Peak memory 207288 kb
Host smart-79c4628d-cd30-40d9-83b0-509954320d97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=18169202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.18169202
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3688759307
Short name T3150
Test name
Test status
Simulation time 367559248 ps
CPU time 3.58 seconds
Started Aug 06 07:51:21 PM PDT 24
Finished Aug 06 07:51:25 PM PDT 24
Peak memory 207268 kb
Host smart-e1340289-4f77-4745-a3ff-9edd23f44623
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3688759307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3688759307
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1260961915
Short name T292
Test name
Test status
Simulation time 1566661149 ps
CPU time 8.05 seconds
Started Aug 06 07:51:25 PM PDT 24
Finished Aug 06 07:51:33 PM PDT 24
Peak memory 207240 kb
Host smart-fbe48303-0f5a-4c95-8573-a094ba58744c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1260961915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1260961915
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3582425576
Short name T293
Test name
Test status
Simulation time 81616665 ps
CPU time 0.97 seconds
Started Aug 06 07:51:19 PM PDT 24
Finished Aug 06 07:51:20 PM PDT 24
Peak memory 207052 kb
Host smart-094fce08-1cfa-4127-8f9a-edb69230fc2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3582425576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3582425576
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1775666890
Short name T3163
Test name
Test status
Simulation time 94199014 ps
CPU time 2.41 seconds
Started Aug 06 07:51:26 PM PDT 24
Finished Aug 06 07:51:28 PM PDT 24
Peak memory 215500 kb
Host smart-f7d89e2a-8fe4-4254-96f4-f39a13a24d86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775666890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1775666890
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.453213968
Short name T3204
Test name
Test status
Simulation time 47726186 ps
CPU time 0.73 seconds
Started Aug 06 07:51:29 PM PDT 24
Finished Aug 06 07:51:30 PM PDT 24
Peak memory 206864 kb
Host smart-d00af924-8a71-4d16-a2ba-b00c15e2ebf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=453213968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.453213968
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2795961835
Short name T287
Test name
Test status
Simulation time 88099696 ps
CPU time 2.19 seconds
Started Aug 06 07:51:22 PM PDT 24
Finished Aug 06 07:51:25 PM PDT 24
Peak memory 207200 kb
Host smart-4b324db6-3dd3-4573-b92e-7aa21fc3caa6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2795961835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2795961835
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2899775828
Short name T3134
Test name
Test status
Simulation time 116088006 ps
CPU time 2.31 seconds
Started Aug 06 07:51:21 PM PDT 24
Finished Aug 06 07:51:24 PM PDT 24
Peak memory 207104 kb
Host smart-53a0707f-9e22-45ea-a25e-4e0205f79ac8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2899775828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2899775828
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1921142735
Short name T3179
Test name
Test status
Simulation time 118410049 ps
CPU time 1.21 seconds
Started Aug 06 07:51:24 PM PDT 24
Finished Aug 06 07:51:26 PM PDT 24
Peak memory 207244 kb
Host smart-dd720e42-d0c0-4a86-949e-388953755acf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1921142735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1921142735
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1036996433
Short name T264
Test name
Test status
Simulation time 143049656 ps
CPU time 1.85 seconds
Started Aug 06 07:51:26 PM PDT 24
Finished Aug 06 07:51:28 PM PDT 24
Peak memory 207240 kb
Host smart-c6a5ef26-46d9-47d6-837f-e48661fa1fae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1036996433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1036996433
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3329696943
Short name T472
Test name
Test status
Simulation time 561491931 ps
CPU time 4.24 seconds
Started Aug 06 07:51:26 PM PDT 24
Finished Aug 06 07:51:30 PM PDT 24
Peak memory 207240 kb
Host smart-988c75cf-da75-4853-a52f-c20b3bc6458e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3329696943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3329696943
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2920959606
Short name T3232
Test name
Test status
Simulation time 39983810 ps
CPU time 0.7 seconds
Started Aug 06 07:52:05 PM PDT 24
Finished Aug 06 07:52:06 PM PDT 24
Peak memory 206880 kb
Host smart-000bab05-6621-4f16-bd2c-9288003f3560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2920959606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2920959606
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2912046798
Short name T3200
Test name
Test status
Simulation time 65485365 ps
CPU time 0.76 seconds
Started Aug 06 07:51:52 PM PDT 24
Finished Aug 06 07:51:53 PM PDT 24
Peak memory 206880 kb
Host smart-f82c6d17-bbb1-4d4b-aff0-89238a56fe77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2912046798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2912046798
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1735245030
Short name T3224
Test name
Test status
Simulation time 38031050 ps
CPU time 0.7 seconds
Started Aug 06 07:51:55 PM PDT 24
Finished Aug 06 07:51:56 PM PDT 24
Peak memory 206760 kb
Host smart-105ae2ca-347e-43aa-8238-3d2b5223b4ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1735245030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1735245030
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4016104572
Short name T234
Test name
Test status
Simulation time 50014947 ps
CPU time 0.7 seconds
Started Aug 06 07:52:14 PM PDT 24
Finished Aug 06 07:52:14 PM PDT 24
Peak memory 206880 kb
Host smart-a4f40e71-64bf-447d-8441-df94b189d816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4016104572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.4016104572
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3126901978
Short name T3214
Test name
Test status
Simulation time 37174287 ps
CPU time 0.72 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 206884 kb
Host smart-9c71b222-1839-44e9-9652-bff550240ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3126901978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3126901978
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.235596974
Short name T3171
Test name
Test status
Simulation time 44243062 ps
CPU time 0.71 seconds
Started Aug 06 07:51:55 PM PDT 24
Finished Aug 06 07:51:56 PM PDT 24
Peak memory 206708 kb
Host smart-fa25a85f-4d87-44c8-b16e-7b6f527b5f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=235596974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.235596974
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.202936866
Short name T3220
Test name
Test status
Simulation time 56949476 ps
CPU time 0.74 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 206908 kb
Host smart-fe3b5a93-4be0-4889-be0e-d8dbc1e20c08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=202936866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.202936866
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.4030509976
Short name T315
Test name
Test status
Simulation time 65189956 ps
CPU time 0.77 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 206904 kb
Host smart-9cf6010d-6b31-462e-abcd-0fde7b8ae303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4030509976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.4030509976
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2732987657
Short name T3221
Test name
Test status
Simulation time 54146465 ps
CPU time 0.75 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:47 PM PDT 24
Peak memory 206908 kb
Host smart-48714e36-ade2-4c3a-8d5b-f6f9e7ba385a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2732987657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2732987657
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2446473161
Short name T3225
Test name
Test status
Simulation time 387878517 ps
CPU time 3.87 seconds
Started Aug 06 07:51:24 PM PDT 24
Finished Aug 06 07:51:28 PM PDT 24
Peak memory 207200 kb
Host smart-c3e02338-4374-44eb-9da5-64de639fb7cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2446473161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2446473161
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2345503937
Short name T3146
Test name
Test status
Simulation time 788510311 ps
CPU time 5.79 seconds
Started Aug 06 07:51:19 PM PDT 24
Finished Aug 06 07:51:25 PM PDT 24
Peak memory 207196 kb
Host smart-f11832c5-1861-4f41-9af1-91f05c44b733
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2345503937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2345503937
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3104651573
Short name T3190
Test name
Test status
Simulation time 101003214 ps
CPU time 0.93 seconds
Started Aug 06 07:51:28 PM PDT 24
Finished Aug 06 07:51:29 PM PDT 24
Peak memory 206928 kb
Host smart-654756af-b0c3-4f7d-b4a5-4cd778a4ba1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3104651573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3104651573
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2967783440
Short name T3136
Test name
Test status
Simulation time 79561762 ps
CPU time 1.34 seconds
Started Aug 06 07:51:21 PM PDT 24
Finished Aug 06 07:51:22 PM PDT 24
Peak memory 215468 kb
Host smart-1b794dd1-42dd-4552-8f06-828c13bae7e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967783440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2967783440
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2450038098
Short name T310
Test name
Test status
Simulation time 57501487 ps
CPU time 0.82 seconds
Started Aug 06 07:51:28 PM PDT 24
Finished Aug 06 07:51:29 PM PDT 24
Peak memory 206956 kb
Host smart-a8b061cd-047d-4bc8-8496-52591898b246
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2450038098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2450038098
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.986652737
Short name T296
Test name
Test status
Simulation time 105189794 ps
CPU time 1.39 seconds
Started Aug 06 07:51:26 PM PDT 24
Finished Aug 06 07:51:27 PM PDT 24
Peak memory 207172 kb
Host smart-adf6dccb-d249-41b0-a10d-841d2df9857f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=986652737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.986652737
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.670554217
Short name T3233
Test name
Test status
Simulation time 176427372 ps
CPU time 4.02 seconds
Started Aug 06 07:51:21 PM PDT 24
Finished Aug 06 07:51:25 PM PDT 24
Peak memory 207120 kb
Host smart-b74a4346-c1bc-469b-aedd-fe385ae94d25
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=670554217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.670554217
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.805281165
Short name T3231
Test name
Test status
Simulation time 355869779 ps
CPU time 1.87 seconds
Started Aug 06 07:51:29 PM PDT 24
Finished Aug 06 07:51:31 PM PDT 24
Peak memory 207300 kb
Host smart-3d2b6a6b-a38c-4e66-9aec-9f6088497cdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=805281165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.805281165
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2495208556
Short name T3141
Test name
Test status
Simulation time 75651488 ps
CPU time 1.8 seconds
Started Aug 06 07:51:25 PM PDT 24
Finished Aug 06 07:51:27 PM PDT 24
Peak memory 207224 kb
Host smart-b7a9808b-76a6-47cc-9609-489d9d77e08c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2495208556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2495208556
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2456370022
Short name T236
Test name
Test status
Simulation time 51667435 ps
CPU time 0.73 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 206904 kb
Host smart-d05b053f-510f-48bd-ba2f-0329b13d5f59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2456370022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2456370022
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2918879324
Short name T3138
Test name
Test status
Simulation time 47721455 ps
CPU time 0.75 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:51:59 PM PDT 24
Peak memory 206916 kb
Host smart-865483d0-b4f4-404d-8452-f3e72a0a6feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2918879324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2918879324
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.224140162
Short name T341
Test name
Test status
Simulation time 39363154 ps
CPU time 0.73 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:51:54 PM PDT 24
Peak memory 206912 kb
Host smart-511eac5e-5230-4881-bd15-3e54345cd8ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=224140162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.224140162
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2387850963
Short name T317
Test name
Test status
Simulation time 46805356 ps
CPU time 0.72 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 206900 kb
Host smart-0ce0f602-9790-4c01-8a40-72a56cf6fc8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2387850963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2387850963
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.837638842
Short name T232
Test name
Test status
Simulation time 54163445 ps
CPU time 0.73 seconds
Started Aug 06 07:51:52 PM PDT 24
Finished Aug 06 07:51:53 PM PDT 24
Peak memory 206912 kb
Host smart-99eaa67b-0c6d-4a87-9a9b-be28400eaf85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=837638842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.837638842
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.272484476
Short name T3147
Test name
Test status
Simulation time 70902364 ps
CPU time 0.73 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:51:54 PM PDT 24
Peak memory 206912 kb
Host smart-48d4bbe7-d231-4f78-9d30-afefb2ab1be0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=272484476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.272484476
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4078839468
Short name T3228
Test name
Test status
Simulation time 41126533 ps
CPU time 0.76 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:51:54 PM PDT 24
Peak memory 206908 kb
Host smart-58f03831-b000-4f64-aca0-1d4c9f014d63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4078839468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.4078839468
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.864963436
Short name T3127
Test name
Test status
Simulation time 39322806 ps
CPU time 0.7 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:51:59 PM PDT 24
Peak memory 206900 kb
Host smart-f5edaaa6-5229-4a2d-856b-51259ad667ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=864963436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.864963436
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4287525464
Short name T3170
Test name
Test status
Simulation time 42462035 ps
CPU time 0.73 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:51:54 PM PDT 24
Peak memory 206928 kb
Host smart-d95c48c6-a73b-49a5-9a96-507822e18012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4287525464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.4287525464
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1207894223
Short name T3213
Test name
Test status
Simulation time 50339628 ps
CPU time 0.73 seconds
Started Aug 06 07:52:10 PM PDT 24
Finished Aug 06 07:52:10 PM PDT 24
Peak memory 206884 kb
Host smart-d7aee7a5-4f1b-45f4-b627-3603f5288902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1207894223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1207894223
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2355066681
Short name T294
Test name
Test status
Simulation time 88380146 ps
CPU time 2 seconds
Started Aug 06 07:51:23 PM PDT 24
Finished Aug 06 07:51:25 PM PDT 24
Peak memory 207216 kb
Host smart-a5ba1b11-1cb9-4637-85a0-6248e84e83dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2355066681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2355066681
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2639872645
Short name T3195
Test name
Test status
Simulation time 2017461014 ps
CPU time 9.24 seconds
Started Aug 06 07:51:30 PM PDT 24
Finished Aug 06 07:51:40 PM PDT 24
Peak memory 207176 kb
Host smart-fb3fb25f-0405-43a0-a55e-c036462372d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2639872645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2639872645
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.793857238
Short name T299
Test name
Test status
Simulation time 71146503 ps
CPU time 0.83 seconds
Started Aug 06 07:51:26 PM PDT 24
Finished Aug 06 07:51:27 PM PDT 24
Peak memory 207044 kb
Host smart-1b478374-7a72-4128-9527-e64bc8cf1866
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=793857238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.793857238
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2952310047
Short name T3203
Test name
Test status
Simulation time 160884319 ps
CPU time 1.86 seconds
Started Aug 06 07:51:28 PM PDT 24
Finished Aug 06 07:51:30 PM PDT 24
Peak memory 215264 kb
Host smart-492f2bc4-90bd-4f88-adf3-eda207a9e7c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952310047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2952310047
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2835983433
Short name T3176
Test name
Test status
Simulation time 115086640 ps
CPU time 1.06 seconds
Started Aug 06 07:51:31 PM PDT 24
Finished Aug 06 07:51:32 PM PDT 24
Peak memory 207016 kb
Host smart-029f9063-16e0-4f46-998b-43a8b652fc3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2835983433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2835983433
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1701511889
Short name T3159
Test name
Test status
Simulation time 79076818 ps
CPU time 0.76 seconds
Started Aug 06 07:51:29 PM PDT 24
Finished Aug 06 07:51:30 PM PDT 24
Peak memory 206868 kb
Host smart-a005c801-e39d-42bc-8091-fb9ca7c6a84b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1701511889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1701511889
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.547549577
Short name T298
Test name
Test status
Simulation time 119529379 ps
CPU time 1.5 seconds
Started Aug 06 07:51:21 PM PDT 24
Finished Aug 06 07:51:22 PM PDT 24
Peak memory 215388 kb
Host smart-1e92bcf1-113f-4cec-b95e-fd2613c56d1a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=547549577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.547549577
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3835173433
Short name T3161
Test name
Test status
Simulation time 260626495 ps
CPU time 2.53 seconds
Started Aug 06 07:51:20 PM PDT 24
Finished Aug 06 07:51:22 PM PDT 24
Peak memory 207220 kb
Host smart-9b638da4-bd81-40d3-bc8d-84e0985aec9f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3835173433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3835173433
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.309092910
Short name T3149
Test name
Test status
Simulation time 158667210 ps
CPU time 1.54 seconds
Started Aug 06 07:51:26 PM PDT 24
Finished Aug 06 07:51:28 PM PDT 24
Peak memory 207252 kb
Host smart-9e067498-3487-4055-862d-b0cd957a9dd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=309092910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.309092910
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.700816817
Short name T259
Test name
Test status
Simulation time 132712831 ps
CPU time 1.83 seconds
Started Aug 06 07:51:26 PM PDT 24
Finished Aug 06 07:51:28 PM PDT 24
Peak memory 207224 kb
Host smart-4b0a5aed-417e-42cf-8f41-647431be9d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=700816817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.700816817
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.939604604
Short name T476
Test name
Test status
Simulation time 285104237 ps
CPU time 2.61 seconds
Started Aug 06 07:51:20 PM PDT 24
Finished Aug 06 07:51:23 PM PDT 24
Peak memory 207244 kb
Host smart-76666182-0a3f-4c16-ae5a-6355ee614381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=939604604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.939604604
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3966089048
Short name T3191
Test name
Test status
Simulation time 41076393 ps
CPU time 0.74 seconds
Started Aug 06 07:51:54 PM PDT 24
Finished Aug 06 07:51:55 PM PDT 24
Peak memory 206928 kb
Host smart-fb22b2a6-02d5-45eb-ba40-75930508adaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3966089048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3966089048
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1329509921
Short name T3131
Test name
Test status
Simulation time 37969383 ps
CPU time 0.77 seconds
Started Aug 06 07:51:56 PM PDT 24
Finished Aug 06 07:51:57 PM PDT 24
Peak memory 206932 kb
Host smart-bbd7976b-9e6c-48cb-b083-09df59fc1a19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1329509921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1329509921
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4120859031
Short name T3153
Test name
Test status
Simulation time 42805310 ps
CPU time 0.71 seconds
Started Aug 06 07:51:54 PM PDT 24
Finished Aug 06 07:51:54 PM PDT 24
Peak memory 206864 kb
Host smart-def5bd9b-4e6e-46b5-99f8-0a79adf6e5ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4120859031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.4120859031
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2676229515
Short name T3143
Test name
Test status
Simulation time 53138325 ps
CPU time 0.71 seconds
Started Aug 06 07:52:10 PM PDT 24
Finished Aug 06 07:52:11 PM PDT 24
Peak memory 206884 kb
Host smart-5b22ff39-27c2-4961-8df9-bdec9d3d9544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2676229515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2676229515
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2491806855
Short name T3155
Test name
Test status
Simulation time 54652799 ps
CPU time 0.75 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 206904 kb
Host smart-1586e9ca-7832-43f8-b620-d2809c4b98e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2491806855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2491806855
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1407333453
Short name T3181
Test name
Test status
Simulation time 54807881 ps
CPU time 0.73 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 206936 kb
Host smart-5617a73e-cef4-4582-9c17-c46f5384979b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1407333453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1407333453
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3704158988
Short name T3183
Test name
Test status
Simulation time 34070546 ps
CPU time 0.75 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 206792 kb
Host smart-6abd0325-f7af-4c1e-8d49-9663ebc6aa37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3704158988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3704158988
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3898466057
Short name T3128
Test name
Test status
Simulation time 36156951 ps
CPU time 0.68 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 206856 kb
Host smart-620b9741-4e9e-400a-90b5-0bd115f2d224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3898466057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3898466057
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1109928722
Short name T3187
Test name
Test status
Simulation time 68375487 ps
CPU time 0.78 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 206904 kb
Host smart-f4877835-9317-4b03-a9ba-e5250ede3667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1109928722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1109928722
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1103550957
Short name T3229
Test name
Test status
Simulation time 82888693 ps
CPU time 1.24 seconds
Started Aug 06 07:51:22 PM PDT 24
Finished Aug 06 07:51:23 PM PDT 24
Peak memory 215504 kb
Host smart-d0499156-5edb-492f-8e65-a07f5c5ea469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103550957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1103550957
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3462909439
Short name T3157
Test name
Test status
Simulation time 60707733 ps
CPU time 0.96 seconds
Started Aug 06 07:51:23 PM PDT 24
Finished Aug 06 07:51:24 PM PDT 24
Peak memory 207036 kb
Host smart-c66831d9-2da9-46c5-9152-6157638f85a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3462909439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3462909439
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1586335127
Short name T3129
Test name
Test status
Simulation time 54901820 ps
CPU time 0.75 seconds
Started Aug 06 07:51:20 PM PDT 24
Finished Aug 06 07:51:21 PM PDT 24
Peak memory 206900 kb
Host smart-ebd447af-abd9-460d-8ebe-667c2d012dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1586335127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1586335127
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1261254441
Short name T3168
Test name
Test status
Simulation time 113089773 ps
CPU time 1.66 seconds
Started Aug 06 07:51:23 PM PDT 24
Finished Aug 06 07:51:25 PM PDT 24
Peak memory 207228 kb
Host smart-5c6ed71e-1aef-45ff-b4a3-ac0dad94a838
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1261254441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1261254441
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3726911823
Short name T3199
Test name
Test status
Simulation time 199285758 ps
CPU time 2.36 seconds
Started Aug 06 07:51:27 PM PDT 24
Finished Aug 06 07:51:30 PM PDT 24
Peak memory 207332 kb
Host smart-f5163554-b0a2-48e9-88d6-47f66628298c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3726911823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3726911823
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.295797577
Short name T313
Test name
Test status
Simulation time 896539368 ps
CPU time 3.18 seconds
Started Aug 06 07:51:27 PM PDT 24
Finished Aug 06 07:51:30 PM PDT 24
Peak memory 207344 kb
Host smart-05739d13-d9a0-41fc-aebc-7c0f04f383d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=295797577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.295797577
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2391847769
Short name T309
Test name
Test status
Simulation time 90708711 ps
CPU time 1.25 seconds
Started Aug 06 07:51:28 PM PDT 24
Finished Aug 06 07:51:30 PM PDT 24
Peak memory 215324 kb
Host smart-bcce47ea-6357-4952-8303-5f16ca1228ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391847769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2391847769
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2792471892
Short name T3207
Test name
Test status
Simulation time 159266122 ps
CPU time 0.9 seconds
Started Aug 06 07:51:23 PM PDT 24
Finished Aug 06 07:51:24 PM PDT 24
Peak memory 206932 kb
Host smart-2d1561c8-bc3d-46ad-9dfc-27f28ca16e89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2792471892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2792471892
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1704984292
Short name T3145
Test name
Test status
Simulation time 49865568 ps
CPU time 0.75 seconds
Started Aug 06 07:51:27 PM PDT 24
Finished Aug 06 07:51:28 PM PDT 24
Peak memory 206808 kb
Host smart-85c2e5ab-9771-41c0-bed8-099f0bc9cdaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1704984292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1704984292
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.800797881
Short name T3218
Test name
Test status
Simulation time 88146394 ps
CPU time 1.37 seconds
Started Aug 06 07:51:28 PM PDT 24
Finished Aug 06 07:51:30 PM PDT 24
Peak memory 207172 kb
Host smart-d74f8ded-bc0f-44fe-b26b-d5e7231544a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=800797881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.800797881
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.4089808690
Short name T225
Test name
Test status
Simulation time 514872570 ps
CPU time 2.65 seconds
Started Aug 06 07:51:24 PM PDT 24
Finished Aug 06 07:51:27 PM PDT 24
Peak memory 207288 kb
Host smart-0aaf6db8-e3d8-4fb4-93e9-062b41703d67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4089808690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.4089808690
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.826729458
Short name T3139
Test name
Test status
Simulation time 97920248 ps
CPU time 1.25 seconds
Started Aug 06 07:51:46 PM PDT 24
Finished Aug 06 07:51:47 PM PDT 24
Peak memory 215500 kb
Host smart-2d28a72b-c314-4fd1-ab4a-24577e77cb38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826729458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.826729458
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3290791887
Short name T3209
Test name
Test status
Simulation time 67846516 ps
CPU time 1 seconds
Started Aug 06 07:51:45 PM PDT 24
Finished Aug 06 07:51:46 PM PDT 24
Peak memory 206924 kb
Host smart-103d8b78-c395-4fea-aec1-914674029624
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3290791887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3290791887
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3648520027
Short name T3202
Test name
Test status
Simulation time 38180651 ps
CPU time 0.71 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:48 PM PDT 24
Peak memory 206988 kb
Host smart-1743e1b3-485a-49c6-8282-beb975a9e715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3648520027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3648520027
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2532659911
Short name T3160
Test name
Test status
Simulation time 99275212 ps
CPU time 1.52 seconds
Started Aug 06 07:51:44 PM PDT 24
Finished Aug 06 07:51:46 PM PDT 24
Peak memory 207256 kb
Host smart-6e715b53-1715-47b4-9b08-e1ed6fafab48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2532659911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2532659911
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1746649104
Short name T255
Test name
Test status
Simulation time 117904902 ps
CPU time 2.86 seconds
Started Aug 06 07:51:42 PM PDT 24
Finished Aug 06 07:51:45 PM PDT 24
Peak memory 215380 kb
Host smart-23916f40-a9d0-4d8c-bf68-a2f4201721a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1746649104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1746649104
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2346354766
Short name T269
Test name
Test status
Simulation time 600679708 ps
CPU time 2.81 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:53 PM PDT 24
Peak memory 207316 kb
Host smart-8789c3c2-260f-4de3-80e6-b4b0553c93db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2346354766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2346354766
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2857988423
Short name T258
Test name
Test status
Simulation time 147696949 ps
CPU time 1.9 seconds
Started Aug 06 07:51:42 PM PDT 24
Finished Aug 06 07:51:44 PM PDT 24
Peak memory 218340 kb
Host smart-89059123-b12c-4845-8cda-55c0af50a9b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857988423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2857988423
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4272177830
Short name T3196
Test name
Test status
Simulation time 51973068 ps
CPU time 0.94 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 206948 kb
Host smart-c42989ce-bba4-451b-9344-c2cb047dd136
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4272177830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.4272177830
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2679705691
Short name T340
Test name
Test status
Simulation time 42474374 ps
CPU time 0.7 seconds
Started Aug 06 07:51:46 PM PDT 24
Finished Aug 06 07:51:46 PM PDT 24
Peak memory 206864 kb
Host smart-09881e8a-dfae-42bf-90c3-12f8ec43b54e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2679705691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2679705691
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2995104648
Short name T304
Test name
Test status
Simulation time 156418624 ps
CPU time 1.17 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 207256 kb
Host smart-b45e1380-889a-4d8e-8c7f-0b835d9d4717
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2995104648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2995104648
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3107012151
Short name T3132
Test name
Test status
Simulation time 122139468 ps
CPU time 1.33 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 215536 kb
Host smart-b898d046-4e88-4530-a1f4-21092c5b9616
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107012151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3107012151
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.848694462
Short name T289
Test name
Test status
Simulation time 111805542 ps
CPU time 1.04 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 207092 kb
Host smart-38bec2fd-7f32-40eb-9adc-5fb6d2063ebf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=848694462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.848694462
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2498919548
Short name T3140
Test name
Test status
Simulation time 41725706 ps
CPU time 0.71 seconds
Started Aug 06 07:51:46 PM PDT 24
Finished Aug 06 07:51:47 PM PDT 24
Peak memory 206912 kb
Host smart-5389c1f9-dcf6-4472-b259-57b18624c275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2498919548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2498919548
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.640070989
Short name T3208
Test name
Test status
Simulation time 194115997 ps
CPU time 1.7 seconds
Started Aug 06 07:51:46 PM PDT 24
Finished Aug 06 07:51:48 PM PDT 24
Peak memory 207284 kb
Host smart-286d2764-498c-44c4-bd15-f9ce60ffe62c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=640070989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.640070989
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3294540102
Short name T3133
Test name
Test status
Simulation time 87378705 ps
CPU time 2.1 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:53 PM PDT 24
Peak memory 207180 kb
Host smart-f4aca38e-64bb-4c5b-8e50-844596b277b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3294540102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3294540102
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4083326924
Short name T479
Test name
Test status
Simulation time 1523271163 ps
CPU time 5.19 seconds
Started Aug 06 07:52:08 PM PDT 24
Finished Aug 06 07:52:13 PM PDT 24
Peak memory 207264 kb
Host smart-205ccfc6-68bc-4a47-908a-527462fb26cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4083326924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.4083326924
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.3809351961
Short name T2262
Test name
Test status
Simulation time 46916154 ps
CPU time 0.67 seconds
Started Aug 06 08:01:02 PM PDT 24
Finished Aug 06 08:01:03 PM PDT 24
Peak memory 207436 kb
Host smart-d412e296-3c53-4ef6-adf9-4727e8b4fe35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3809351961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.3809351961
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1338546801
Short name T1022
Test name
Test status
Simulation time 4252886431 ps
CPU time 5.9 seconds
Started Aug 06 08:00:44 PM PDT 24
Finished Aug 06 08:00:50 PM PDT 24
Peak memory 215864 kb
Host smart-a7d53378-8ac7-4e43-a225-f4b4ee06d2b0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338546801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.1338546801
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.197249311
Short name T1121
Test name
Test status
Simulation time 13666212520 ps
CPU time 15.07 seconds
Started Aug 06 08:00:41 PM PDT 24
Finished Aug 06 08:00:56 PM PDT 24
Peak memory 215804 kb
Host smart-ecaa6db7-348f-4f07-9d02-7e00d13d0d3c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=197249311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.197249311
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2023751008
Short name T765
Test name
Test status
Simulation time 24484616171 ps
CPU time 30.19 seconds
Started Aug 06 08:00:43 PM PDT 24
Finished Aug 06 08:01:14 PM PDT 24
Peak memory 215808 kb
Host smart-ac6f863b-3a9e-4e4d-ab85-6117fc7c8e81
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023751008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.2023751008
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2153835599
Short name T3066
Test name
Test status
Simulation time 191506107 ps
CPU time 0.98 seconds
Started Aug 06 08:00:44 PM PDT 24
Finished Aug 06 08:00:45 PM PDT 24
Peak memory 207356 kb
Host smart-06eb5762-42f1-4154-9fc3-5797b69a790d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21538
35599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2153835599
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.2972856216
Short name T2122
Test name
Test status
Simulation time 288313493 ps
CPU time 1.05 seconds
Started Aug 06 08:00:44 PM PDT 24
Finished Aug 06 08:00:45 PM PDT 24
Peak memory 207376 kb
Host smart-36e6c428-215f-44c8-91d6-ea2030aef619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29728
56216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.2972856216
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2296116871
Short name T194
Test name
Test status
Simulation time 55007098458 ps
CPU time 92.28 seconds
Started Aug 06 08:00:47 PM PDT 24
Finished Aug 06 08:02:19 PM PDT 24
Peak memory 207620 kb
Host smart-df36659e-b0c1-4e80-bc1a-98e0bce86a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22961
16871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2296116871
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.836703924
Short name T1166
Test name
Test status
Simulation time 1955991235 ps
CPU time 45.25 seconds
Started Aug 06 08:00:43 PM PDT 24
Finished Aug 06 08:01:28 PM PDT 24
Peak memory 207620 kb
Host smart-59acbe88-e6a2-4c16-b99c-774597ea774a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836703924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.836703924
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.432325281
Short name T2034
Test name
Test status
Simulation time 760293896 ps
CPU time 2.09 seconds
Started Aug 06 08:00:43 PM PDT 24
Finished Aug 06 08:00:45 PM PDT 24
Peak memory 207224 kb
Host smart-72bae53e-0607-4774-99be-93c3a983d7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43232
5281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.432325281
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.3974970701
Short name T1543
Test name
Test status
Simulation time 134502837 ps
CPU time 0.82 seconds
Started Aug 06 08:00:47 PM PDT 24
Finished Aug 06 08:00:48 PM PDT 24
Peak memory 207320 kb
Host smart-9720cd35-35c7-4c31-abba-24df833bf446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39749
70701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.3974970701
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.1945447153
Short name T1910
Test name
Test status
Simulation time 40591916 ps
CPU time 0.7 seconds
Started Aug 06 08:00:45 PM PDT 24
Finished Aug 06 08:00:45 PM PDT 24
Peak memory 207280 kb
Host smart-b4db6d2f-b560-42b4-8bd8-30798e4c6b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19454
47153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1945447153
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2517982450
Short name T2743
Test name
Test status
Simulation time 844835726 ps
CPU time 2.49 seconds
Started Aug 06 08:00:40 PM PDT 24
Finished Aug 06 08:00:42 PM PDT 24
Peak memory 207416 kb
Host smart-70122426-4e0f-45c4-a9be-8f9a9532fa02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25179
82450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2517982450
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1107406434
Short name T2778
Test name
Test status
Simulation time 187135765 ps
CPU time 1.35 seconds
Started Aug 06 08:00:42 PM PDT 24
Finished Aug 06 08:00:43 PM PDT 24
Peak memory 207532 kb
Host smart-398d6239-667e-48d7-bf4f-d0e62b208001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11074
06434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1107406434
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2508105147
Short name T1386
Test name
Test status
Simulation time 92208370731 ps
CPU time 138.33 seconds
Started Aug 06 08:00:43 PM PDT 24
Finished Aug 06 08:03:01 PM PDT 24
Peak memory 207668 kb
Host smart-6c398b5e-64b0-4db8-a4b3-d2de3a34fce2
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2508105147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2508105147
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.3801868445
Short name T2934
Test name
Test status
Simulation time 88130443036 ps
CPU time 135.21 seconds
Started Aug 06 08:00:44 PM PDT 24
Finished Aug 06 08:03:00 PM PDT 24
Peak memory 207636 kb
Host smart-df264b12-4323-4922-b334-78952bccf68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801868445 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.3801868445
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.3240504520
Short name T2449
Test name
Test status
Simulation time 100098975661 ps
CPU time 160.6 seconds
Started Aug 06 08:00:44 PM PDT 24
Finished Aug 06 08:03:25 PM PDT 24
Peak memory 207592 kb
Host smart-bc91de9a-d09d-4e8a-a76f-85f68669a9d0
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3240504520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.3240504520
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3148530351
Short name T2024
Test name
Test status
Simulation time 109175225212 ps
CPU time 174.92 seconds
Started Aug 06 08:00:39 PM PDT 24
Finished Aug 06 08:03:34 PM PDT 24
Peak memory 207692 kb
Host smart-89b47788-65c5-42bd-99fe-18569cece17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31485
30351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3148530351
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.268981910
Short name T1363
Test name
Test status
Simulation time 227336037 ps
CPU time 1.15 seconds
Started Aug 06 08:00:47 PM PDT 24
Finished Aug 06 08:00:48 PM PDT 24
Peak memory 216660 kb
Host smart-1a795b80-4246-48de-a0c3-5f130ae4da7e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=268981910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.268981910
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.339636508
Short name T2380
Test name
Test status
Simulation time 153689028 ps
CPU time 0.9 seconds
Started Aug 06 08:00:41 PM PDT 24
Finished Aug 06 08:00:42 PM PDT 24
Peak memory 207320 kb
Host smart-4db87043-3812-41b5-9b10-39dfc3668d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33963
6508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.339636508
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.95939612
Short name T1268
Test name
Test status
Simulation time 282785830 ps
CPU time 1.19 seconds
Started Aug 06 08:00:41 PM PDT 24
Finished Aug 06 08:00:42 PM PDT 24
Peak memory 207356 kb
Host smart-4574a7bf-fa53-4fed-821e-2811046b2e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95939
612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.95939612
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.947668657
Short name T2092
Test name
Test status
Simulation time 2713423476 ps
CPU time 20.34 seconds
Started Aug 06 08:00:44 PM PDT 24
Finished Aug 06 08:01:04 PM PDT 24
Peak memory 224004 kb
Host smart-dd9f8888-3d19-45bf-94ef-f6fe7e149b7a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=947668657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.947668657
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.2801599687
Short name T2042
Test name
Test status
Simulation time 6721133817 ps
CPU time 44.57 seconds
Started Aug 06 08:00:41 PM PDT 24
Finished Aug 06 08:01:25 PM PDT 24
Peak memory 207636 kb
Host smart-6e79bcba-df8e-4967-968d-2ae81bfb7aa7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2801599687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.2801599687
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.2183713079
Short name T1083
Test name
Test status
Simulation time 228571960 ps
CPU time 0.94 seconds
Started Aug 06 08:00:43 PM PDT 24
Finished Aug 06 08:00:44 PM PDT 24
Peak memory 207312 kb
Host smart-b09ebb4f-d4d0-4e84-ac3d-3dbb8f29c6cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21837
13079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2183713079
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.822761816
Short name T72
Test name
Test status
Simulation time 496334671 ps
CPU time 1.5 seconds
Started Aug 06 08:00:56 PM PDT 24
Finished Aug 06 08:00:57 PM PDT 24
Peak memory 207020 kb
Host smart-0df0c485-34ae-4e22-bfcd-9f2b2a07aa87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82276
1816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.822761816
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2101350815
Short name T1726
Test name
Test status
Simulation time 28263067354 ps
CPU time 43.41 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:01:37 PM PDT 24
Peak memory 215836 kb
Host smart-ccfce397-e1a7-4cc6-ab29-59c2c96fc8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21013
50815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2101350815
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2753446893
Short name T274
Test name
Test status
Simulation time 5539644092 ps
CPU time 6.59 seconds
Started Aug 06 08:00:52 PM PDT 24
Finished Aug 06 08:00:59 PM PDT 24
Peak memory 215884 kb
Host smart-8e1a25a8-66e2-44e8-8377-7617b811feaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27534
46893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2753446893
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.4242971886
Short name T2340
Test name
Test status
Simulation time 4869510813 ps
CPU time 36.89 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:01:30 PM PDT 24
Peak memory 218516 kb
Host smart-bc1a7485-b524-4250-b6c8-acd9770ee5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42429
71886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.4242971886
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2885106258
Short name T588
Test name
Test status
Simulation time 2152133621 ps
CPU time 21.2 seconds
Started Aug 06 08:00:51 PM PDT 24
Finished Aug 06 08:01:12 PM PDT 24
Peak memory 215824 kb
Host smart-a8fd7d0f-d891-4154-ad16-2d2ed6ab553f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2885106258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2885106258
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3108218169
Short name T1206
Test name
Test status
Simulation time 233065359 ps
CPU time 0.97 seconds
Started Aug 06 08:00:54 PM PDT 24
Finished Aug 06 08:00:55 PM PDT 24
Peak memory 207320 kb
Host smart-45d1fc03-086c-46f9-89ed-25db8483aee4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3108218169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3108218169
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.4040495691
Short name T721
Test name
Test status
Simulation time 195770832 ps
CPU time 0.95 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:00:54 PM PDT 24
Peak memory 207420 kb
Host smart-ca90c79d-420f-4283-b968-f9ff3b963fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40404
95691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.4040495691
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.789938365
Short name T1577
Test name
Test status
Simulation time 2451256739 ps
CPU time 18.42 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:01:12 PM PDT 24
Peak memory 207660 kb
Host smart-3f23d55b-160c-4383-b8af-6414033678a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=789938365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.789938365
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.294669857
Short name T1037
Test name
Test status
Simulation time 2622747335 ps
CPU time 20.14 seconds
Started Aug 06 08:00:52 PM PDT 24
Finished Aug 06 08:01:12 PM PDT 24
Peak memory 224028 kb
Host smart-17b7e177-1bc6-41f7-b8bf-61c5d9936867
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=294669857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.294669857
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.3843638199
Short name T2830
Test name
Test status
Simulation time 242300272 ps
CPU time 0.9 seconds
Started Aug 06 08:00:56 PM PDT 24
Finished Aug 06 08:00:57 PM PDT 24
Peak memory 207440 kb
Host smart-c349455c-552d-483b-b047-43f76c9b9fac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3843638199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.3843638199
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3867760116
Short name T1338
Test name
Test status
Simulation time 179608453 ps
CPU time 0.83 seconds
Started Aug 06 08:00:52 PM PDT 24
Finished Aug 06 08:00:52 PM PDT 24
Peak memory 207296 kb
Host smart-f604505f-e39f-4992-88a5-3b9be4401187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38677
60116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3867760116
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2244613637
Short name T70
Test name
Test status
Simulation time 567266451 ps
CPU time 1.69 seconds
Started Aug 06 08:00:55 PM PDT 24
Finished Aug 06 08:00:57 PM PDT 24
Peak memory 207272 kb
Host smart-8ce6bd48-b088-447a-aa9b-116544a4ca2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22446
13637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2244613637
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.100653207
Short name T2798
Test name
Test status
Simulation time 203802770 ps
CPU time 0.91 seconds
Started Aug 06 08:00:51 PM PDT 24
Finished Aug 06 08:00:52 PM PDT 24
Peak memory 207384 kb
Host smart-527ae9b1-515d-4f97-b303-24b4eefdf03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10065
3207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.100653207
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2238852168
Short name T1951
Test name
Test status
Simulation time 152803850 ps
CPU time 0.83 seconds
Started Aug 06 08:00:54 PM PDT 24
Finished Aug 06 08:00:55 PM PDT 24
Peak memory 207452 kb
Host smart-17a0b543-c387-45b9-82b5-22a371ef69e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22388
52168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2238852168
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.97452242
Short name T3038
Test name
Test status
Simulation time 189192442 ps
CPU time 0.85 seconds
Started Aug 06 08:00:51 PM PDT 24
Finished Aug 06 08:00:52 PM PDT 24
Peak memory 207348 kb
Host smart-a1f39123-52d2-4399-a775-2e5da4bffe6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97452
242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.97452242
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2700109412
Short name T565
Test name
Test status
Simulation time 195666749 ps
CPU time 0.96 seconds
Started Aug 06 08:00:56 PM PDT 24
Finished Aug 06 08:00:57 PM PDT 24
Peak memory 206988 kb
Host smart-4172aa33-f4ea-48a0-840d-1bf7bda1a942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27001
09412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2700109412
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.4203389342
Short name T1745
Test name
Test status
Simulation time 157396278 ps
CPU time 0.84 seconds
Started Aug 06 08:00:52 PM PDT 24
Finished Aug 06 08:00:53 PM PDT 24
Peak memory 207348 kb
Host smart-3c8f80ee-0e0a-4a60-ab63-1c8bb189165c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42033
89342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.4203389342
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.716322530
Short name T2955
Test name
Test status
Simulation time 173828534 ps
CPU time 0.86 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:00:55 PM PDT 24
Peak memory 207360 kb
Host smart-5487c9ac-a0c6-455b-995d-4b3ea6b27d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71632
2530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.716322530
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1208271286
Short name T1949
Test name
Test status
Simulation time 239278487 ps
CPU time 1.06 seconds
Started Aug 06 08:00:54 PM PDT 24
Finished Aug 06 08:00:55 PM PDT 24
Peak memory 207356 kb
Host smart-95bdb93a-d592-4cab-a76d-0fcb895acc30
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1208271286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1208271286
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.2109496674
Short name T229
Test name
Test status
Simulation time 186630761 ps
CPU time 0.91 seconds
Started Aug 06 08:00:58 PM PDT 24
Finished Aug 06 08:00:59 PM PDT 24
Peak memory 207344 kb
Host smart-9b7ea3d3-ea73-4b67-bcdb-f42db10c31d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21094
96674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.2109496674
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1791374811
Short name T2718
Test name
Test status
Simulation time 214686000 ps
CPU time 1.01 seconds
Started Aug 06 08:00:58 PM PDT 24
Finished Aug 06 08:00:59 PM PDT 24
Peak memory 207364 kb
Host smart-a4e60896-9246-44f7-a4b4-93003b5984c7
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1791374811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1791374811
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2392242685
Short name T231
Test name
Test status
Simulation time 244527240 ps
CPU time 1.07 seconds
Started Aug 06 08:00:51 PM PDT 24
Finished Aug 06 08:00:52 PM PDT 24
Peak memory 207356 kb
Host smart-c939cda7-3584-441d-9238-5d1e5db976b3
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2392242685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.2392242685
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2379107473
Short name T3058
Test name
Test status
Simulation time 153367941 ps
CPU time 0.82 seconds
Started Aug 06 08:00:56 PM PDT 24
Finished Aug 06 08:00:57 PM PDT 24
Peak memory 207388 kb
Host smart-c12045ec-cf1c-422a-a3de-f4a36f726b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23791
07473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2379107473
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3347072128
Short name T1583
Test name
Test status
Simulation time 54712952 ps
CPU time 0.69 seconds
Started Aug 06 08:00:57 PM PDT 24
Finished Aug 06 08:00:58 PM PDT 24
Peak memory 207304 kb
Host smart-d0468126-d8c1-43b3-b6bb-76eda0c32324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33470
72128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3347072128
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3027792187
Short name T2910
Test name
Test status
Simulation time 14382537162 ps
CPU time 39.25 seconds
Started Aug 06 08:00:51 PM PDT 24
Finished Aug 06 08:01:30 PM PDT 24
Peak memory 215900 kb
Host smart-2f39e016-fd26-479e-b241-82b7b53024a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30277
92187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3027792187
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3255246365
Short name T1563
Test name
Test status
Simulation time 164557441 ps
CPU time 0.86 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:00:55 PM PDT 24
Peak memory 207356 kb
Host smart-f44e09ef-097b-4a2c-8d51-bf0dd31cc340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32552
46365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3255246365
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.861498712
Short name T760
Test name
Test status
Simulation time 215172000 ps
CPU time 0.97 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:00:55 PM PDT 24
Peak memory 207312 kb
Host smart-6e606b32-4826-4202-ad2c-fbef243befdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86149
8712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.861498712
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2782679282
Short name T187
Test name
Test status
Simulation time 3603473201 ps
CPU time 24.42 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:01:18 PM PDT 24
Peak memory 223908 kb
Host smart-82f242d4-9866-4fce-996d-58ae8635254b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782679282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2782679282
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.3301017233
Short name T2996
Test name
Test status
Simulation time 11069900756 ps
CPU time 57 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:01:50 PM PDT 24
Peak memory 223964 kb
Host smart-5bfe6c4d-8a26-455f-a4f0-0dc7d812c328
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3301017233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.3301017233
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.2133369623
Short name T1796
Test name
Test status
Simulation time 9971783711 ps
CPU time 52.29 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:01:45 PM PDT 24
Peak memory 224080 kb
Host smart-a70f12be-571a-4ba8-9257-0f54f94e690b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133369623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.2133369623
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.2642146104
Short name T2105
Test name
Test status
Simulation time 193621829 ps
CPU time 0.9 seconds
Started Aug 06 08:00:52 PM PDT 24
Finished Aug 06 08:00:54 PM PDT 24
Peak memory 207372 kb
Host smart-7ba1d101-9b85-427e-ae95-437b8d4f1770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26421
46104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.2642146104
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3500662659
Short name T104
Test name
Test status
Simulation time 178432639 ps
CPU time 0.86 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:00:55 PM PDT 24
Peak memory 207396 kb
Host smart-7665ebf0-1652-45dd-bf8c-620b42953739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35006
62659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3500662659
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.661252602
Short name T3017
Test name
Test status
Simulation time 20164660163 ps
CPU time 22.88 seconds
Started Aug 06 08:00:55 PM PDT 24
Finished Aug 06 08:01:18 PM PDT 24
Peak memory 207420 kb
Host smart-b98c426c-fb08-4cd1-9f3e-b786ca9cdfef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66125
2602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.661252602
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1422573606
Short name T1655
Test name
Test status
Simulation time 142672472 ps
CPU time 0.8 seconds
Started Aug 06 08:00:51 PM PDT 24
Finished Aug 06 08:00:52 PM PDT 24
Peak memory 207352 kb
Host smart-1a7e4e97-3ae2-4590-82b5-74821d457727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14225
73606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1422573606
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.555127233
Short name T1129
Test name
Test status
Simulation time 261085603 ps
CPU time 1.07 seconds
Started Aug 06 08:00:51 PM PDT 24
Finished Aug 06 08:00:52 PM PDT 24
Peak memory 207300 kb
Host smart-71836dc2-420f-4d9c-8960-589b7c96733c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55512
7233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.555127233
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.2467811551
Short name T2681
Test name
Test status
Simulation time 189229247 ps
CPU time 0.97 seconds
Started Aug 06 08:00:54 PM PDT 24
Finished Aug 06 08:00:55 PM PDT 24
Peak memory 207596 kb
Host smart-60b7656b-b370-466c-b186-c54602a5029d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24678
11551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2467811551
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2518886582
Short name T1404
Test name
Test status
Simulation time 156953202 ps
CPU time 0.83 seconds
Started Aug 06 08:00:57 PM PDT 24
Finished Aug 06 08:00:58 PM PDT 24
Peak memory 207308 kb
Host smart-f049836e-033e-41e6-89b8-d74f3f157863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25188
86582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2518886582
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3196458451
Short name T2081
Test name
Test status
Simulation time 154828485 ps
CPU time 0.8 seconds
Started Aug 06 08:00:51 PM PDT 24
Finished Aug 06 08:00:52 PM PDT 24
Peak memory 207360 kb
Host smart-f8047bd0-60b3-4595-8056-ec2274b7716c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31964
58451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3196458451
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1018691752
Short name T1504
Test name
Test status
Simulation time 199510905 ps
CPU time 0.96 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:00:54 PM PDT 24
Peak memory 207352 kb
Host smart-fd474f2b-9bb5-4189-a318-eb9b718a8961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10186
91752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1018691752
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1563372017
Short name T2808
Test name
Test status
Simulation time 1850453804 ps
CPU time 53.3 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:01:47 PM PDT 24
Peak memory 223880 kb
Host smart-965cf9c4-97dc-48cc-aed7-5cdba83f8052
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1563372017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1563372017
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3942520863
Short name T2631
Test name
Test status
Simulation time 176144644 ps
CPU time 0.88 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:00:54 PM PDT 24
Peak memory 207356 kb
Host smart-33e8ec4f-dfaf-48c1-aa9e-5f61e948d48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39425
20863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3942520863
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.796899826
Short name T2013
Test name
Test status
Simulation time 197705248 ps
CPU time 0.9 seconds
Started Aug 06 08:00:52 PM PDT 24
Finished Aug 06 08:00:53 PM PDT 24
Peak memory 207392 kb
Host smart-7c53f294-66ab-495e-93a3-1c6e0e0977ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79689
9826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.796899826
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.736293071
Short name T850
Test name
Test status
Simulation time 1004707056 ps
CPU time 2.37 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:00:56 PM PDT 24
Peak memory 207480 kb
Host smart-492164d7-a7b4-4e00-a09b-2df2ee7c80f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73629
3071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.736293071
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.1208658870
Short name T672
Test name
Test status
Simulation time 2843985095 ps
CPU time 30.86 seconds
Started Aug 06 08:00:53 PM PDT 24
Finished Aug 06 08:01:25 PM PDT 24
Peak memory 224208 kb
Host smart-d6fd43db-1a9e-4951-934f-501ca293a192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12086
58870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1208658870
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.615183480
Short name T962
Test name
Test status
Simulation time 1069227004 ps
CPU time 8.68 seconds
Started Aug 06 08:00:44 PM PDT 24
Finished Aug 06 08:00:52 PM PDT 24
Peak memory 207568 kb
Host smart-b76ef20a-04da-4ed6-b1be-9c67f0e32e80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615183480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host_
handshake.615183480
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.4193310230
Short name T1452
Test name
Test status
Simulation time 41294028 ps
CPU time 0.7 seconds
Started Aug 06 08:01:38 PM PDT 24
Finished Aug 06 08:01:38 PM PDT 24
Peak memory 207488 kb
Host smart-90ef5ddf-7f06-45be-b611-50dc833f2437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4193310230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.4193310230
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.3979689672
Short name T2941
Test name
Test status
Simulation time 4066915193 ps
CPU time 5.74 seconds
Started Aug 06 08:01:08 PM PDT 24
Finished Aug 06 08:01:14 PM PDT 24
Peak memory 215740 kb
Host smart-182a833c-0dd2-4fd5-864a-de8e0991ee87
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979689672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.3979689672
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.778743243
Short name T2675
Test name
Test status
Simulation time 14520269134 ps
CPU time 16.34 seconds
Started Aug 06 08:01:07 PM PDT 24
Finished Aug 06 08:01:24 PM PDT 24
Peak memory 215788 kb
Host smart-5dd0e927-d4ad-471a-b5da-0fd9c5625d59
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=778743243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.778743243
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2220557683
Short name T2604
Test name
Test status
Simulation time 29118024892 ps
CPU time 33.81 seconds
Started Aug 06 08:01:03 PM PDT 24
Finished Aug 06 08:01:37 PM PDT 24
Peak memory 207596 kb
Host smart-d931f603-b2b6-4e43-a990-a0e2cc600652
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220557683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.2220557683
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.4225313496
Short name T1455
Test name
Test status
Simulation time 193754250 ps
CPU time 0.87 seconds
Started Aug 06 08:01:03 PM PDT 24
Finished Aug 06 08:01:04 PM PDT 24
Peak memory 207336 kb
Host smart-8b6aa1c8-d271-41ce-9906-ecc035134684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42253
13496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.4225313496
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1033827677
Short name T57
Test name
Test status
Simulation time 179519732 ps
CPU time 0.89 seconds
Started Aug 06 08:01:06 PM PDT 24
Finished Aug 06 08:01:07 PM PDT 24
Peak memory 207396 kb
Host smart-766e2906-8323-43da-87b7-334a846a3e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10338
27677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1033827677
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.764417243
Short name T3048
Test name
Test status
Simulation time 162707974 ps
CPU time 0.87 seconds
Started Aug 06 08:01:04 PM PDT 24
Finished Aug 06 08:01:05 PM PDT 24
Peak memory 207320 kb
Host smart-1c0d85ec-57ae-42c4-a249-f19a3ff92ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76441
7243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.764417243
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.4014576044
Short name T2441
Test name
Test status
Simulation time 239026199 ps
CPU time 1.09 seconds
Started Aug 06 08:01:05 PM PDT 24
Finished Aug 06 08:01:06 PM PDT 24
Peak memory 207352 kb
Host smart-9aa2f6c8-c245-4bce-bd7b-6f15945dae1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40145
76044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.4014576044
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.708702449
Short name T1882
Test name
Test status
Simulation time 317420924 ps
CPU time 1.12 seconds
Started Aug 06 08:01:06 PM PDT 24
Finished Aug 06 08:01:07 PM PDT 24
Peak memory 207400 kb
Host smart-a818de56-ef70-443d-a3db-456026c146ea
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=708702449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.708702449
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2806885417
Short name T134
Test name
Test status
Simulation time 55802205450 ps
CPU time 85.77 seconds
Started Aug 06 08:01:07 PM PDT 24
Finished Aug 06 08:02:33 PM PDT 24
Peak memory 207660 kb
Host smart-ccb75e46-c6fc-4cde-b7c7-2a6e10cc6cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28068
85417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2806885417
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.2892772126
Short name T937
Test name
Test status
Simulation time 859931282 ps
CPU time 5.71 seconds
Started Aug 06 08:01:05 PM PDT 24
Finished Aug 06 08:01:11 PM PDT 24
Peak memory 207632 kb
Host smart-9e118eda-a495-4c0a-9d72-afa50c66d6d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892772126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.2892772126
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.3083484882
Short name T1488
Test name
Test status
Simulation time 1249645775 ps
CPU time 2.39 seconds
Started Aug 06 08:01:10 PM PDT 24
Finished Aug 06 08:01:12 PM PDT 24
Peak memory 207284 kb
Host smart-b49c960a-40fe-4538-a4f4-027f5ecbd582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30834
84882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.3083484882
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.360257926
Short name T2088
Test name
Test status
Simulation time 183070511 ps
CPU time 0.87 seconds
Started Aug 06 08:01:08 PM PDT 24
Finished Aug 06 08:01:08 PM PDT 24
Peak memory 207272 kb
Host smart-f32eee0a-f2c6-4551-990f-70168790f0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36025
7926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.360257926
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.142170603
Short name T1430
Test name
Test status
Simulation time 34624240 ps
CPU time 0.68 seconds
Started Aug 06 08:01:02 PM PDT 24
Finished Aug 06 08:01:02 PM PDT 24
Peak memory 207320 kb
Host smart-4b0d73c3-6150-458b-a023-fd5ed9a2b694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14217
0603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.142170603
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.1286899260
Short name T1038
Test name
Test status
Simulation time 881020863 ps
CPU time 2.28 seconds
Started Aug 06 08:01:05 PM PDT 24
Finished Aug 06 08:01:07 PM PDT 24
Peak memory 207572 kb
Host smart-8bd149fa-a579-4282-80e3-160a842d7da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12868
99260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.1286899260
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_types.11802657
Short name T463
Test name
Test status
Simulation time 277356346 ps
CPU time 1.07 seconds
Started Aug 06 08:01:04 PM PDT 24
Finished Aug 06 08:01:05 PM PDT 24
Peak memory 207340 kb
Host smart-874727a8-24d1-417c-ac58-c8aeae27bfdf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=11802657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.11802657
Directory /workspace/1.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.1635829754
Short name T957
Test name
Test status
Simulation time 99226623026 ps
CPU time 145.58 seconds
Started Aug 06 08:01:08 PM PDT 24
Finished Aug 06 08:03:33 PM PDT 24
Peak memory 207640 kb
Host smart-162b2320-6fa0-490d-857a-90d58dce6266
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1635829754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.1635829754
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.707376756
Short name T2495
Test name
Test status
Simulation time 91279897518 ps
CPU time 128.8 seconds
Started Aug 06 08:01:10 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207532 kb
Host smart-be8cac5b-1c3a-433e-bc03-d379c3fceaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707376756 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.707376756
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.1420696144
Short name T586
Test name
Test status
Simulation time 104158286603 ps
CPU time 165.07 seconds
Started Aug 06 08:01:06 PM PDT 24
Finished Aug 06 08:03:51 PM PDT 24
Peak memory 207672 kb
Host smart-0742d782-39aa-45d4-9db6-7323a2b45494
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1420696144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.1420696144
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.2749518342
Short name T709
Test name
Test status
Simulation time 91135889024 ps
CPU time 142.49 seconds
Started Aug 06 08:01:03 PM PDT 24
Finished Aug 06 08:03:25 PM PDT 24
Peak memory 207544 kb
Host smart-bb3fa1f7-8a1f-4c0c-8089-5cf538e81188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749518342 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.2749518342
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.31264172
Short name T1500
Test name
Test status
Simulation time 104148520414 ps
CPU time 165.36 seconds
Started Aug 06 08:01:04 PM PDT 24
Finished Aug 06 08:03:49 PM PDT 24
Peak memory 207572 kb
Host smart-f3ef7fae-1a07-496f-b068-ddd0f2dc1834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31264
172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.31264172
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3223927978
Short name T1998
Test name
Test status
Simulation time 225656829 ps
CPU time 1.23 seconds
Started Aug 06 08:01:05 PM PDT 24
Finished Aug 06 08:01:06 PM PDT 24
Peak memory 215732 kb
Host smart-6aab8920-be25-4680-83d4-2552f715b3db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3223927978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3223927978
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.52238320
Short name T27
Test name
Test status
Simulation time 159843156 ps
CPU time 0.88 seconds
Started Aug 06 08:01:03 PM PDT 24
Finished Aug 06 08:01:04 PM PDT 24
Peak memory 207348 kb
Host smart-a82ce74b-76ea-4844-910b-41182e3cb4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52238
320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.52238320
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2095441921
Short name T1990
Test name
Test status
Simulation time 239644277 ps
CPU time 0.96 seconds
Started Aug 06 08:01:04 PM PDT 24
Finished Aug 06 08:01:05 PM PDT 24
Peak memory 207356 kb
Host smart-c736b012-9181-4a35-b424-9f30996f6921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20954
41921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2095441921
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.4238143790
Short name T2638
Test name
Test status
Simulation time 6105022630 ps
CPU time 48.04 seconds
Started Aug 06 08:01:06 PM PDT 24
Finished Aug 06 08:01:54 PM PDT 24
Peak memory 224036 kb
Host smart-5df81fe2-2080-4806-afa3-b31430713fe0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4238143790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.4238143790
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.2424084480
Short name T1374
Test name
Test status
Simulation time 6816317572 ps
CPU time 51.04 seconds
Started Aug 06 08:01:06 PM PDT 24
Finished Aug 06 08:01:57 PM PDT 24
Peak memory 207592 kb
Host smart-83e32a75-8f0b-4c78-a31a-5c902609e791
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2424084480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.2424084480
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1867969021
Short name T1087
Test name
Test status
Simulation time 208753001 ps
CPU time 0.98 seconds
Started Aug 06 08:01:04 PM PDT 24
Finished Aug 06 08:01:05 PM PDT 24
Peak memory 207448 kb
Host smart-dc15db91-2c3b-4917-877d-78ab0f2755dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18679
69021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1867969021
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.2098664072
Short name T1714
Test name
Test status
Simulation time 32781560532 ps
CPU time 50.12 seconds
Started Aug 06 08:01:04 PM PDT 24
Finished Aug 06 08:01:55 PM PDT 24
Peak memory 207560 kb
Host smart-5b2a44b9-250b-4943-a645-b69216873cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20986
64072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2098664072
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1473336041
Short name T1450
Test name
Test status
Simulation time 5636946135 ps
CPU time 7.6 seconds
Started Aug 06 08:01:06 PM PDT 24
Finished Aug 06 08:01:14 PM PDT 24
Peak memory 207592 kb
Host smart-def117db-0da7-447a-a2db-57f7ed3ade66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14733
36041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1473336041
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.1287144093
Short name T1633
Test name
Test status
Simulation time 4092889181 ps
CPU time 39.82 seconds
Started Aug 06 08:01:03 PM PDT 24
Finished Aug 06 08:01:43 PM PDT 24
Peak memory 218520 kb
Host smart-a7c97811-88ee-46d6-add9-9543e7a99a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12871
44093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.1287144093
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1964999267
Short name T2
Test name
Test status
Simulation time 2611675539 ps
CPU time 19.39 seconds
Started Aug 06 08:01:09 PM PDT 24
Finished Aug 06 08:01:29 PM PDT 24
Peak memory 223976 kb
Host smart-791121e1-5b68-4c94-aef2-c8ef80f667c6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1964999267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1964999267
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.624718228
Short name T2689
Test name
Test status
Simulation time 238390523 ps
CPU time 0.99 seconds
Started Aug 06 08:01:06 PM PDT 24
Finished Aug 06 08:01:07 PM PDT 24
Peak memory 207364 kb
Host smart-47d8a2f6-9259-4041-afca-48be42af577c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=624718228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.624718228
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1939862604
Short name T1309
Test name
Test status
Simulation time 195535588 ps
CPU time 0.93 seconds
Started Aug 06 08:01:05 PM PDT 24
Finished Aug 06 08:01:06 PM PDT 24
Peak memory 207348 kb
Host smart-9a3ee69b-4495-4811-9561-3436dca42caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19398
62604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1939862604
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.615630926
Short name T2517
Test name
Test status
Simulation time 1748808940 ps
CPU time 13.23 seconds
Started Aug 06 08:01:06 PM PDT 24
Finished Aug 06 08:01:19 PM PDT 24
Peak memory 207568 kb
Host smart-f85b989e-f7f4-4f07-947c-d1558508b699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61563
0926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.615630926
Directory /workspace/1.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.2745838353
Short name T135
Test name
Test status
Simulation time 2769032573 ps
CPU time 76.57 seconds
Started Aug 06 08:01:06 PM PDT 24
Finished Aug 06 08:02:22 PM PDT 24
Peak memory 223856 kb
Host smart-adc6f8e7-192d-46cc-afe6-bd5f65107f6c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2745838353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2745838353
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.730194399
Short name T582
Test name
Test status
Simulation time 2312016668 ps
CPU time 59.96 seconds
Started Aug 06 08:01:03 PM PDT 24
Finished Aug 06 08:02:03 PM PDT 24
Peak memory 215832 kb
Host smart-735c6fb8-6bd0-4161-9724-0524fd45b622
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=730194399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.730194399
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.3994058501
Short name T1160
Test name
Test status
Simulation time 154579918 ps
CPU time 0.87 seconds
Started Aug 06 08:01:02 PM PDT 24
Finished Aug 06 08:01:03 PM PDT 24
Peak memory 207380 kb
Host smart-ccab9bbe-db28-4f6e-abc5-2878ab5941f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3994058501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.3994058501
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2570021927
Short name T1963
Test name
Test status
Simulation time 154691822 ps
CPU time 0.85 seconds
Started Aug 06 08:01:03 PM PDT 24
Finished Aug 06 08:01:04 PM PDT 24
Peak memory 207428 kb
Host smart-c265fa96-dd81-43ea-af51-222136c0ee33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25700
21927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2570021927
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.634289528
Short name T1499
Test name
Test status
Simulation time 176515549 ps
CPU time 0.88 seconds
Started Aug 06 08:01:03 PM PDT 24
Finished Aug 06 08:01:04 PM PDT 24
Peak memory 207292 kb
Host smart-5587de3f-0bcd-455a-894b-ad0b52867f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63428
9528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.634289528
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3232732011
Short name T2597
Test name
Test status
Simulation time 185001861 ps
CPU time 0.88 seconds
Started Aug 06 08:01:04 PM PDT 24
Finished Aug 06 08:01:05 PM PDT 24
Peak memory 207392 kb
Host smart-cd646318-c4a5-47a1-9ae5-b14816c88e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32327
32011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3232732011
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1824186321
Short name T1046
Test name
Test status
Simulation time 161022209 ps
CPU time 0.84 seconds
Started Aug 06 08:01:06 PM PDT 24
Finished Aug 06 08:01:07 PM PDT 24
Peak memory 207368 kb
Host smart-fefef2eb-6168-4dea-b2a1-53747040f670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18241
86321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1824186321
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3365947379
Short name T199
Test name
Test status
Simulation time 149681808 ps
CPU time 0.83 seconds
Started Aug 06 08:01:07 PM PDT 24
Finished Aug 06 08:01:08 PM PDT 24
Peak memory 207324 kb
Host smart-28171834-940d-4277-be0d-47e6b3eb5bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33659
47379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3365947379
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.1924976885
Short name T1584
Test name
Test status
Simulation time 277468105 ps
CPU time 1.16 seconds
Started Aug 06 08:01:04 PM PDT 24
Finished Aug 06 08:01:05 PM PDT 24
Peak memory 207372 kb
Host smart-0b7e2ae1-862a-4e6f-988e-d76d10a4672c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1924976885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.1924976885
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.4041169861
Short name T230
Test name
Test status
Simulation time 237946552 ps
CPU time 0.99 seconds
Started Aug 06 08:01:21 PM PDT 24
Finished Aug 06 08:01:22 PM PDT 24
Peak memory 207348 kb
Host smart-bc2bd48b-d92d-4c7d-b3b8-7526b4545221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40411
69861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.4041169861
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3967620275
Short name T855
Test name
Test status
Simulation time 47081112 ps
CPU time 0.73 seconds
Started Aug 06 08:01:21 PM PDT 24
Finished Aug 06 08:01:22 PM PDT 24
Peak memory 207312 kb
Host smart-d544b586-9e17-4c19-90d8-4937807fe71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39676
20275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3967620275
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2181550672
Short name T281
Test name
Test status
Simulation time 19286111956 ps
CPU time 48.5 seconds
Started Aug 06 08:01:21 PM PDT 24
Finished Aug 06 08:02:10 PM PDT 24
Peak memory 220452 kb
Host smart-703e930b-1929-49cc-8914-55588f175fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21815
50672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2181550672
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2253871461
Short name T2045
Test name
Test status
Simulation time 184331789 ps
CPU time 0.95 seconds
Started Aug 06 08:01:21 PM PDT 24
Finished Aug 06 08:01:22 PM PDT 24
Peak memory 207352 kb
Host smart-353dfc4f-674d-47a0-95ac-5eeadba0e13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22538
71461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2253871461
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1290893943
Short name T484
Test name
Test status
Simulation time 240792554 ps
CPU time 1.02 seconds
Started Aug 06 08:01:23 PM PDT 24
Finished Aug 06 08:01:24 PM PDT 24
Peak memory 207340 kb
Host smart-20a5739b-ea8e-48c5-837f-ffbb33fa47f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12908
93943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1290893943
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1899935209
Short name T1812
Test name
Test status
Simulation time 5655921310 ps
CPU time 21.62 seconds
Started Aug 06 08:01:22 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 215904 kb
Host smart-2b11dc80-0abe-4c84-aab6-cad0d72810de
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899935209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1899935209
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.1157211761
Short name T1214
Test name
Test status
Simulation time 6424908971 ps
CPU time 29.87 seconds
Started Aug 06 08:01:21 PM PDT 24
Finished Aug 06 08:01:51 PM PDT 24
Peak memory 224140 kb
Host smart-af6df75a-7870-43fa-807b-ec980e5cc21a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1157211761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.1157211761
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.587537104
Short name T3028
Test name
Test status
Simulation time 9090512253 ps
CPU time 161.19 seconds
Started Aug 06 08:01:22 PM PDT 24
Finished Aug 06 08:04:03 PM PDT 24
Peak memory 223832 kb
Host smart-36c97782-4d9b-46e9-8ee4-5c9febafb67c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=587537104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.587537104
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.2238388894
Short name T2198
Test name
Test status
Simulation time 168553305 ps
CPU time 0.88 seconds
Started Aug 06 08:01:21 PM PDT 24
Finished Aug 06 08:01:22 PM PDT 24
Peak memory 207300 kb
Host smart-688d2082-b2dd-4969-ad92-f0b30e9a7b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22383
88894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.2238388894
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2112533907
Short name T1034
Test name
Test status
Simulation time 195388189 ps
CPU time 0.94 seconds
Started Aug 06 08:01:22 PM PDT 24
Finished Aug 06 08:01:24 PM PDT 24
Peak memory 207316 kb
Host smart-bddea6f3-3b93-4017-8014-a7504c5ff7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21125
33907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2112533907
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_resume_link_active.1837423029
Short name T3056
Test name
Test status
Simulation time 20167595600 ps
CPU time 26.08 seconds
Started Aug 06 08:01:20 PM PDT 24
Finished Aug 06 08:01:46 PM PDT 24
Peak memory 207456 kb
Host smart-0223d458-506c-45e6-865a-8db282197b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18374
23029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.1837423029
Directory /workspace/1.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2124522937
Short name T563
Test name
Test status
Simulation time 198975817 ps
CPU time 0.84 seconds
Started Aug 06 08:01:23 PM PDT 24
Finished Aug 06 08:01:24 PM PDT 24
Peak memory 207288 kb
Host smart-36d99e55-8472-4913-8d27-8d3a75111b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21245
22937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2124522937
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_full.1024868620
Short name T540
Test name
Test status
Simulation time 365333298 ps
CPU time 1.28 seconds
Started Aug 06 08:01:23 PM PDT 24
Finished Aug 06 08:01:24 PM PDT 24
Peak memory 207348 kb
Host smart-f0d094dd-c8b0-4892-9e90-379d033ce0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10248
68620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.1024868620
Directory /workspace/1.usbdev_rx_full/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.3860988202
Short name T2924
Test name
Test status
Simulation time 177177017 ps
CPU time 0.89 seconds
Started Aug 06 08:01:21 PM PDT 24
Finished Aug 06 08:01:22 PM PDT 24
Peak memory 207368 kb
Host smart-45929a0b-8c87-490f-b2c1-9e93e868bb6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38609
88202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.3860988202
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3261618555
Short name T223
Test name
Test status
Simulation time 227164075 ps
CPU time 1.05 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:01:42 PM PDT 24
Peak memory 223464 kb
Host smart-dd1d94d8-1868-42e4-8bbc-fb36f8df9e29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3261618555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3261618555
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.207972949
Short name T51
Test name
Test status
Simulation time 338077915 ps
CPU time 1.17 seconds
Started Aug 06 08:01:18 PM PDT 24
Finished Aug 06 08:01:19 PM PDT 24
Peak memory 207416 kb
Host smart-c5d5793c-1d49-43ed-808a-3f116a50c571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20797
2949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.207972949
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.3913901836
Short name T2685
Test name
Test status
Simulation time 197414105 ps
CPU time 0.94 seconds
Started Aug 06 08:01:20 PM PDT 24
Finished Aug 06 08:01:21 PM PDT 24
Peak memory 207360 kb
Host smart-00944779-be70-4235-ae02-853bc6c4a7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39139
01836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3913901836
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.354356825
Short name T1371
Test name
Test status
Simulation time 148734321 ps
CPU time 0.83 seconds
Started Aug 06 08:01:19 PM PDT 24
Finished Aug 06 08:01:20 PM PDT 24
Peak memory 207280 kb
Host smart-a86d8e02-3789-4a19-ac65-4b603f213e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35435
6825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.354356825
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3336229824
Short name T981
Test name
Test status
Simulation time 181929050 ps
CPU time 0.91 seconds
Started Aug 06 08:01:22 PM PDT 24
Finished Aug 06 08:01:23 PM PDT 24
Peak memory 207372 kb
Host smart-03400a1c-b84a-445f-b39b-6beac4589117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33362
29824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3336229824
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.415563225
Short name T558
Test name
Test status
Simulation time 243487691 ps
CPU time 1.05 seconds
Started Aug 06 08:01:22 PM PDT 24
Finished Aug 06 08:01:23 PM PDT 24
Peak memory 207368 kb
Host smart-f673b3c3-261d-4cab-ae95-8ece49aa47a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41556
3225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.415563225
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.207368598
Short name T2592
Test name
Test status
Simulation time 2790390693 ps
CPU time 81.36 seconds
Started Aug 06 08:01:22 PM PDT 24
Finished Aug 06 08:02:44 PM PDT 24
Peak memory 217216 kb
Host smart-4e4ffed7-b2a8-485a-b0b1-5e8938336f07
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=207368598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.207368598
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2424467597
Short name T3019
Test name
Test status
Simulation time 160802682 ps
CPU time 0.84 seconds
Started Aug 06 08:01:20 PM PDT 24
Finished Aug 06 08:01:21 PM PDT 24
Peak memory 207376 kb
Host smart-21a1ec97-5a07-4fdf-b74b-70a8ada0bc38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24244
67597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2424467597
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.2724102156
Short name T2960
Test name
Test status
Simulation time 225768440 ps
CPU time 0.95 seconds
Started Aug 06 08:01:23 PM PDT 24
Finished Aug 06 08:01:24 PM PDT 24
Peak memory 207396 kb
Host smart-0341f4f5-ea87-4b5d-a919-0a0fe8759ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27241
02156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2724102156
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.4097115324
Short name T786
Test name
Test status
Simulation time 508752414 ps
CPU time 1.44 seconds
Started Aug 06 08:01:23 PM PDT 24
Finished Aug 06 08:01:25 PM PDT 24
Peak memory 207368 kb
Host smart-d30a958d-664c-4daf-a248-3f8261aafaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40971
15324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.4097115324
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2143522947
Short name T2269
Test name
Test status
Simulation time 2996862240 ps
CPU time 81.19 seconds
Started Aug 06 08:01:22 PM PDT 24
Finished Aug 06 08:02:43 PM PDT 24
Peak memory 217340 kb
Host smart-a20de6f8-a843-401c-b6fb-6f61b3f39575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21435
22947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2143522947
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.859107385
Short name T1442
Test name
Test status
Simulation time 3721081317 ps
CPU time 25.98 seconds
Started Aug 06 08:01:04 PM PDT 24
Finished Aug 06 08:01:30 PM PDT 24
Peak memory 207684 kb
Host smart-c1dba640-be08-4398-81c9-7884038b30a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859107385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host_
handshake.859107385
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.578448025
Short name T1224
Test name
Test status
Simulation time 57255190 ps
CPU time 0.72 seconds
Started Aug 06 08:03:29 PM PDT 24
Finished Aug 06 08:03:30 PM PDT 24
Peak memory 207488 kb
Host smart-df6dbb58-71a2-46ac-9e17-9989e281593d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=578448025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.578448025
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3933689367
Short name T728
Test name
Test status
Simulation time 11662607816 ps
CPU time 13.62 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:29 PM PDT 24
Peak memory 207604 kb
Host smart-aa7bd4a1-558c-47b5-9d9b-329f6da72bd0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933689367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.3933689367
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1420172540
Short name T2881
Test name
Test status
Simulation time 13325552973 ps
CPU time 16.82 seconds
Started Aug 06 08:03:31 PM PDT 24
Finished Aug 06 08:03:48 PM PDT 24
Peak memory 215792 kb
Host smart-3f44b7b5-ddb4-4d95-b8da-c410dc17bb29
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420172540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1420172540
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1085660853
Short name T2164
Test name
Test status
Simulation time 26207072456 ps
CPU time 29.64 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:45 PM PDT 24
Peak memory 215880 kb
Host smart-39e05939-d809-451a-9c74-6317ed357b30
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085660853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.1085660853
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3846567573
Short name T1361
Test name
Test status
Simulation time 172056619 ps
CPU time 0.89 seconds
Started Aug 06 08:03:22 PM PDT 24
Finished Aug 06 08:03:23 PM PDT 24
Peak memory 207340 kb
Host smart-cd51f7f8-67cd-4767-b8ee-536f5041f80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38465
67573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3846567573
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3275451619
Short name T73
Test name
Test status
Simulation time 141307533 ps
CPU time 0.83 seconds
Started Aug 06 08:03:22 PM PDT 24
Finished Aug 06 08:03:23 PM PDT 24
Peak memory 207296 kb
Host smart-a63cd9d6-1995-4027-b566-0abde09aedf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32754
51619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3275451619
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.2971020366
Short name T963
Test name
Test status
Simulation time 409897619 ps
CPU time 1.38 seconds
Started Aug 06 08:03:22 PM PDT 24
Finished Aug 06 08:03:23 PM PDT 24
Peak memory 207428 kb
Host smart-66b160d3-6b41-4f64-9df7-df822c08942a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29710
20366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.2971020366
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2843253141
Short name T2489
Test name
Test status
Simulation time 444585579 ps
CPU time 1.43 seconds
Started Aug 06 08:03:17 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207384 kb
Host smart-36ae26b1-31d6-4126-970d-5d42699a762b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2843253141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2843253141
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.1497458433
Short name T1985
Test name
Test status
Simulation time 56408199012 ps
CPU time 87.81 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:04:44 PM PDT 24
Peak memory 207600 kb
Host smart-dda96cc7-2933-4c50-ac1d-7deeb51d374c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14974
58433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1497458433
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.768479818
Short name T59
Test name
Test status
Simulation time 8461429108 ps
CPU time 57.14 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207712 kb
Host smart-21ae941c-65ac-4a7e-b7d2-c3df39bed868
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768479818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.768479818
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2951439549
Short name T2149
Test name
Test status
Simulation time 623755578 ps
CPU time 1.77 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207328 kb
Host smart-13763037-d8ad-472c-9b53-25c3eca444bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29514
39549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2951439549
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.145630083
Short name T1680
Test name
Test status
Simulation time 200278875 ps
CPU time 0.9 seconds
Started Aug 06 08:03:14 PM PDT 24
Finished Aug 06 08:03:15 PM PDT 24
Peak memory 207340 kb
Host smart-0c5b61e2-3209-4800-a38c-40a6d9bdab82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14563
0083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.145630083
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1575304301
Short name T658
Test name
Test status
Simulation time 57714773 ps
CPU time 0.76 seconds
Started Aug 06 08:03:17 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207316 kb
Host smart-6e6eafa0-1eb8-45d5-9839-5fcee71dae4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15753
04301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1575304301
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2657596836
Short name T2253
Test name
Test status
Simulation time 830613632 ps
CPU time 2.48 seconds
Started Aug 06 08:03:22 PM PDT 24
Finished Aug 06 08:03:25 PM PDT 24
Peak memory 207604 kb
Host smart-bb51ad45-115f-42b4-8b96-fb5f8fda9614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26575
96836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2657596836
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_types.3054086241
Short name T1601
Test name
Test status
Simulation time 498953444 ps
CPU time 1.46 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207324 kb
Host smart-3f16f4f0-1a80-4462-a7b2-5607a2883034
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3054086241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.3054086241
Directory /workspace/10.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2900112166
Short name T3074
Test name
Test status
Simulation time 247146091 ps
CPU time 2.06 seconds
Started Aug 06 08:03:22 PM PDT 24
Finished Aug 06 08:03:24 PM PDT 24
Peak memory 207528 kb
Host smart-07053516-6ccf-4d45-8914-88ad738fa509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29001
12166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2900112166
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1647225026
Short name T1320
Test name
Test status
Simulation time 215862820 ps
CPU time 1.06 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207544 kb
Host smart-7fee3c18-458e-4db1-9c29-33f64f3f7a75
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1647225026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1647225026
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2743679031
Short name T1335
Test name
Test status
Simulation time 158004186 ps
CPU time 0.83 seconds
Started Aug 06 08:03:22 PM PDT 24
Finished Aug 06 08:03:23 PM PDT 24
Peak memory 207388 kb
Host smart-673fabca-b3d9-42eb-92bb-fcdbcb4d27a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27436
79031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2743679031
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1670092978
Short name T2725
Test name
Test status
Simulation time 181563973 ps
CPU time 0.98 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207292 kb
Host smart-651d93d5-ad38-49de-add0-63310a4d38ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16700
92978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1670092978
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.1135394518
Short name T2816
Test name
Test status
Simulation time 2734106576 ps
CPU time 27.52 seconds
Started Aug 06 08:03:14 PM PDT 24
Finished Aug 06 08:03:42 PM PDT 24
Peak memory 217560 kb
Host smart-4f178155-aa6a-449f-8abd-d34a6f42377c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1135394518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.1135394518
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.3657779013
Short name T2467
Test name
Test status
Simulation time 8887136440 ps
CPU time 111.28 seconds
Started Aug 06 08:03:17 PM PDT 24
Finished Aug 06 08:05:08 PM PDT 24
Peak memory 207620 kb
Host smart-4a781d60-da54-41c7-9137-10ac49c70798
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3657779013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.3657779013
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3576724953
Short name T1533
Test name
Test status
Simulation time 208495334 ps
CPU time 0.94 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207312 kb
Host smart-0195d638-a0cb-4635-81d1-da96e8292d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767
24953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3576724953
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.2467626119
Short name T1873
Test name
Test status
Simulation time 29631751402 ps
CPU time 44.8 seconds
Started Aug 06 08:03:23 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207692 kb
Host smart-5a6ff3bf-b197-4a57-902c-f8c06c1dd361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24676
26119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2467626119
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.733433416
Short name T2249
Test name
Test status
Simulation time 8710635651 ps
CPU time 12.67 seconds
Started Aug 06 08:03:23 PM PDT 24
Finished Aug 06 08:03:36 PM PDT 24
Peak memory 207624 kb
Host smart-0071ee7e-12fb-426d-88b1-aba8cb5284af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73343
3416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.733433416
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.694402977
Short name T2355
Test name
Test status
Simulation time 1585808802 ps
CPU time 41.93 seconds
Started Aug 06 08:03:31 PM PDT 24
Finished Aug 06 08:04:14 PM PDT 24
Peak memory 215676 kb
Host smart-0c6b7ace-5e67-494c-adb7-bb8d4bedefbe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=694402977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.694402977
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2302282132
Short name T712
Test name
Test status
Simulation time 251722672 ps
CPU time 1.1 seconds
Started Aug 06 08:03:23 PM PDT 24
Finished Aug 06 08:03:25 PM PDT 24
Peak memory 207356 kb
Host smart-5e895fe4-e6d0-4895-bd62-59e25b3627d4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2302282132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2302282132
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2964790301
Short name T2491
Test name
Test status
Simulation time 195637732 ps
CPU time 1 seconds
Started Aug 06 08:03:22 PM PDT 24
Finished Aug 06 08:03:23 PM PDT 24
Peak memory 207380 kb
Host smart-8c90a97d-923f-49d9-a2cd-231383ddff2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29647
90301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2964790301
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.3036527013
Short name T2833
Test name
Test status
Simulation time 2236299041 ps
CPU time 62.78 seconds
Started Aug 06 08:03:31 PM PDT 24
Finished Aug 06 08:04:34 PM PDT 24
Peak memory 215788 kb
Host smart-b41ccff9-bb5b-4dd6-bb13-5a5989dde0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30365
27013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.3036527013
Directory /workspace/10.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1488194977
Short name T2055
Test name
Test status
Simulation time 2527874053 ps
CPU time 73.74 seconds
Started Aug 06 08:03:31 PM PDT 24
Finished Aug 06 08:04:45 PM PDT 24
Peak memory 215840 kb
Host smart-1512a7f9-4207-4bd5-8b14-382957913030
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1488194977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1488194977
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.800463189
Short name T1927
Test name
Test status
Simulation time 3959474855 ps
CPU time 40.36 seconds
Started Aug 06 08:03:31 PM PDT 24
Finished Aug 06 08:04:11 PM PDT 24
Peak memory 217348 kb
Host smart-b8015d4d-9c15-40f2-ae27-19c340ff4350
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=800463189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.800463189
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1201370510
Short name T2544
Test name
Test status
Simulation time 156592358 ps
CPU time 0.83 seconds
Started Aug 06 08:03:31 PM PDT 24
Finished Aug 06 08:03:32 PM PDT 24
Peak memory 207336 kb
Host smart-722b2117-0ae4-4b59-88c8-40bec27eb23c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1201370510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1201370510
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2885279869
Short name T1332
Test name
Test status
Simulation time 142720258 ps
CPU time 0.83 seconds
Started Aug 06 08:03:23 PM PDT 24
Finished Aug 06 08:03:24 PM PDT 24
Peak memory 207380 kb
Host smart-519f9224-50b0-465d-8952-a2a5ad1ac010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28852
79869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2885279869
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.3103332710
Short name T1607
Test name
Test status
Simulation time 208320148 ps
CPU time 0.92 seconds
Started Aug 06 08:03:23 PM PDT 24
Finished Aug 06 08:03:24 PM PDT 24
Peak memory 207352 kb
Host smart-4aff0288-8b75-4d5f-84d5-bf0657a864bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31033
32710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3103332710
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.365550985
Short name T2179
Test name
Test status
Simulation time 201075606 ps
CPU time 0.98 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 207356 kb
Host smart-8a4011f8-3988-42bb-b556-d2696a0356bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36555
0985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.365550985
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3933475669
Short name T1697
Test name
Test status
Simulation time 144979043 ps
CPU time 0.87 seconds
Started Aug 06 08:03:31 PM PDT 24
Finished Aug 06 08:03:32 PM PDT 24
Peak memory 207324 kb
Host smart-c1285f43-40f0-4c12-b23c-7b94fcd68e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39334
75669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3933475669
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3937182370
Short name T2791
Test name
Test status
Simulation time 146623652 ps
CPU time 0.87 seconds
Started Aug 06 08:03:31 PM PDT 24
Finished Aug 06 08:03:32 PM PDT 24
Peak memory 207328 kb
Host smart-9eae1656-6323-4c53-9eef-a3fade9c9c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39371
82370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3937182370
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1789780141
Short name T1314
Test name
Test status
Simulation time 219690456 ps
CPU time 1.11 seconds
Started Aug 06 08:03:21 PM PDT 24
Finished Aug 06 08:03:23 PM PDT 24
Peak memory 207356 kb
Host smart-5223b4f1-3f84-4e02-9c45-c33b893bcd33
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1789780141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1789780141
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.4106469560
Short name T1876
Test name
Test status
Simulation time 151548026 ps
CPU time 0.83 seconds
Started Aug 06 08:03:21 PM PDT 24
Finished Aug 06 08:03:22 PM PDT 24
Peak memory 207348 kb
Host smart-f68ac8db-5444-4528-be47-7ab021b3c700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41064
69560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.4106469560
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1154823501
Short name T717
Test name
Test status
Simulation time 31713818 ps
CPU time 0.72 seconds
Started Aug 06 08:03:17 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207284 kb
Host smart-992eee33-348d-42f7-8576-732b0af2f401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11548
23501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1154823501
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3555783955
Short name T1968
Test name
Test status
Simulation time 8893657232 ps
CPU time 23.45 seconds
Started Aug 06 08:03:21 PM PDT 24
Finished Aug 06 08:03:45 PM PDT 24
Peak memory 215864 kb
Host smart-555ea6b4-e7c8-4b21-9c5c-0de958574fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35557
83955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3555783955
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.168587775
Short name T1010
Test name
Test status
Simulation time 180357349 ps
CPU time 0.91 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207412 kb
Host smart-3adb4e0d-c179-46d8-ac3c-9a2654aa9424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16858
7775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.168587775
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2345093854
Short name T789
Test name
Test status
Simulation time 206803283 ps
CPU time 1.01 seconds
Started Aug 06 08:03:21 PM PDT 24
Finished Aug 06 08:03:22 PM PDT 24
Peak memory 207272 kb
Host smart-fa06d22d-9771-4a21-adf7-d221b89274b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23450
93854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2345093854
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.2826123223
Short name T2967
Test name
Test status
Simulation time 221593971 ps
CPU time 1.02 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:03:29 PM PDT 24
Peak memory 207292 kb
Host smart-8ecb3852-ad9c-45e5-9481-475860602574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28261
23223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.2826123223
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3227859191
Short name T1013
Test name
Test status
Simulation time 187019983 ps
CPU time 0.96 seconds
Started Aug 06 08:03:28 PM PDT 24
Finished Aug 06 08:03:29 PM PDT 24
Peak memory 207352 kb
Host smart-c41aa221-c7f1-4dd2-bb4f-d8b57543bc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32278
59191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3227859191
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_resume_link_active.3853756599
Short name T848
Test name
Test status
Simulation time 20180711493 ps
CPU time 21.57 seconds
Started Aug 06 08:03:32 PM PDT 24
Finished Aug 06 08:03:54 PM PDT 24
Peak memory 207440 kb
Host smart-5cbd7286-bcaf-47cb-8cff-862fa0b4b020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38537
56599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.3853756599
Directory /workspace/10.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2528812476
Short name T909
Test name
Test status
Simulation time 161980382 ps
CPU time 0.86 seconds
Started Aug 06 08:03:34 PM PDT 24
Finished Aug 06 08:03:35 PM PDT 24
Peak memory 207372 kb
Host smart-15c54e7c-b52f-481c-83ff-2607d6d95550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25288
12476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2528812476
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_rx_full.83917284
Short name T1667
Test name
Test status
Simulation time 425600973 ps
CPU time 1.25 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:03:29 PM PDT 24
Peak memory 207444 kb
Host smart-53997bba-122c-4083-8b01-3d9b71b74013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83917
284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.83917284
Directory /workspace/10.usbdev_rx_full/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2689958901
Short name T2047
Test name
Test status
Simulation time 159920353 ps
CPU time 0.92 seconds
Started Aug 06 08:03:28 PM PDT 24
Finished Aug 06 08:03:29 PM PDT 24
Peak memory 207256 kb
Host smart-b1bfd241-3766-4835-8f89-519f5712afe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26899
58901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2689958901
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.52468932
Short name T1399
Test name
Test status
Simulation time 1864278116 ps
CPU time 14.63 seconds
Started Aug 06 08:03:29 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 215548 kb
Host smart-f54bbba3-67f9-42f8-a312-c23c80a65239
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=52468932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.52468932
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.440148236
Short name T1032
Test name
Test status
Simulation time 162431793 ps
CPU time 0.85 seconds
Started Aug 06 08:03:29 PM PDT 24
Finished Aug 06 08:03:30 PM PDT 24
Peak memory 207204 kb
Host smart-a0a9875a-7ad8-49a2-973d-d1375ac66e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44014
8236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.440148236
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.360747800
Short name T1414
Test name
Test status
Simulation time 154193687 ps
CPU time 0.85 seconds
Started Aug 06 08:03:26 PM PDT 24
Finished Aug 06 08:03:27 PM PDT 24
Peak memory 207368 kb
Host smart-99e0a0c8-a7ef-4744-a759-ea82428dcecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36074
7800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.360747800
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.333703982
Short name T849
Test name
Test status
Simulation time 498946009 ps
CPU time 1.55 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:03:29 PM PDT 24
Peak memory 207324 kb
Host smart-6ed1ceaf-5715-49e3-b390-56571b6af39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33370
3982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.333703982
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1798842313
Short name T1425
Test name
Test status
Simulation time 2496359713 ps
CPU time 17.9 seconds
Started Aug 06 08:03:26 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 215816 kb
Host smart-2e13531c-4b83-4baf-b98f-eb34c335a904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17988
42313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1798842313
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.1500256457
Short name T2259
Test name
Test status
Simulation time 1353261313 ps
CPU time 30.82 seconds
Started Aug 06 08:03:22 PM PDT 24
Finished Aug 06 08:03:53 PM PDT 24
Peak memory 207572 kb
Host smart-4d791717-de70-4d35-b3b1-47d99a16248d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500256457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.1500256457
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/100.usbdev_endpoint_types.4058981951
Short name T1913
Test name
Test status
Simulation time 312889766 ps
CPU time 1.17 seconds
Started Aug 06 08:09:10 PM PDT 24
Finished Aug 06 08:09:12 PM PDT 24
Peak memory 207376 kb
Host smart-256ad229-d384-42a8-9ff3-9f5884c5ff11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4058981951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.4058981951
Directory /workspace/100.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/102.usbdev_endpoint_types.3535989728
Short name T370
Test name
Test status
Simulation time 556972213 ps
CPU time 1.34 seconds
Started Aug 06 08:09:14 PM PDT 24
Finished Aug 06 08:09:15 PM PDT 24
Peak memory 207300 kb
Host smart-ba3baced-36f7-47d7-9c5e-121f03b5897d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3535989728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.3535989728
Directory /workspace/102.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/103.usbdev_endpoint_types.1450902135
Short name T419
Test name
Test status
Simulation time 515618121 ps
CPU time 1.65 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207288 kb
Host smart-6a3722bd-ebfe-4e83-bcf9-4f116998e1d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1450902135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.1450902135
Directory /workspace/103.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/105.usbdev_endpoint_types.3163485225
Short name T421
Test name
Test status
Simulation time 495829994 ps
CPU time 1.36 seconds
Started Aug 06 08:09:02 PM PDT 24
Finished Aug 06 08:09:04 PM PDT 24
Peak memory 207296 kb
Host smart-99e84684-c656-43bd-b3df-579d9ea7b0f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3163485225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.3163485225
Directory /workspace/105.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/106.usbdev_endpoint_types.1903877815
Short name T394
Test name
Test status
Simulation time 557233036 ps
CPU time 1.45 seconds
Started Aug 06 08:09:13 PM PDT 24
Finished Aug 06 08:09:14 PM PDT 24
Peak memory 207352 kb
Host smart-6dce40dc-dede-4718-b1ce-51c01ace5b67
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1903877815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.1903877815
Directory /workspace/106.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/108.usbdev_endpoint_types.767747083
Short name T440
Test name
Test status
Simulation time 344433619 ps
CPU time 1.23 seconds
Started Aug 06 08:08:57 PM PDT 24
Finished Aug 06 08:08:59 PM PDT 24
Peak memory 207340 kb
Host smart-65a62ad5-73ac-4102-8375-ea0b418cffbf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=767747083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.767747083
Directory /workspace/108.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/109.usbdev_endpoint_types.2448478835
Short name T32
Test name
Test status
Simulation time 659336251 ps
CPU time 1.7 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207292 kb
Host smart-0684dc79-e58e-43f7-888f-dc93722e793a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2448478835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.2448478835
Directory /workspace/109.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.3059036727
Short name T2651
Test name
Test status
Simulation time 34535184 ps
CPU time 0.7 seconds
Started Aug 06 08:03:46 PM PDT 24
Finished Aug 06 08:03:47 PM PDT 24
Peak memory 207452 kb
Host smart-549d29ef-5b36-4ab8-a862-7b6aab0f722a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3059036727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3059036727
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1949081867
Short name T2069
Test name
Test status
Simulation time 4530545029 ps
CPU time 6.26 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:03:34 PM PDT 24
Peak memory 216864 kb
Host smart-99b7937b-21b1-49a8-901a-f4609ecda0b8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949081867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.1949081867
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1709424266
Short name T1716
Test name
Test status
Simulation time 13406038894 ps
CPU time 15.97 seconds
Started Aug 06 08:03:36 PM PDT 24
Finished Aug 06 08:03:52 PM PDT 24
Peak memory 215752 kb
Host smart-66f8a131-5f47-47b5-94c8-32b50cb14e4a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709424266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1709424266
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.52717442
Short name T2528
Test name
Test status
Simulation time 249304814 ps
CPU time 0.96 seconds
Started Aug 06 08:03:28 PM PDT 24
Finished Aug 06 08:03:29 PM PDT 24
Peak memory 207344 kb
Host smart-5253f9bf-0338-4838-a6cf-6f5a13408709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52717
442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.52717442
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.938424629
Short name T3076
Test name
Test status
Simulation time 149404097 ps
CPU time 0.88 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:03:28 PM PDT 24
Peak memory 207344 kb
Host smart-a1e01d3e-6d35-4229-8579-8b04460d2fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93842
4629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.938424629
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.2839665600
Short name T1216
Test name
Test status
Simulation time 255510074 ps
CPU time 1.03 seconds
Started Aug 06 08:03:35 PM PDT 24
Finished Aug 06 08:03:36 PM PDT 24
Peak memory 207348 kb
Host smart-8023dbbf-ad01-49f6-911c-ad73e53363a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28396
65600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2839665600
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.4242642535
Short name T2155
Test name
Test status
Simulation time 449452631 ps
CPU time 1.51 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:03:29 PM PDT 24
Peak memory 207308 kb
Host smart-a839aa14-d236-4b5c-8010-ff104862a365
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4242642535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.4242642535
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1013390052
Short name T1978
Test name
Test status
Simulation time 37230750335 ps
CPU time 59.12 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:04:27 PM PDT 24
Peak memory 207724 kb
Host smart-e1161add-5132-4a9d-a55c-b2e7dbbcea2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10133
90052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1013390052
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.801168412
Short name T198
Test name
Test status
Simulation time 591395204 ps
CPU time 11.58 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:03:38 PM PDT 24
Peak memory 207604 kb
Host smart-c0f36b0f-aae6-4871-9d0d-ba5dbb1e1e14
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801168412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.801168412
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2776858457
Short name T2640
Test name
Test status
Simulation time 1112809197 ps
CPU time 2.83 seconds
Started Aug 06 08:03:29 PM PDT 24
Finished Aug 06 08:03:32 PM PDT 24
Peak memory 207328 kb
Host smart-31304ed1-7a9a-4652-80de-c9887b352dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27768
58457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2776858457
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.663539428
Short name T781
Test name
Test status
Simulation time 138622775 ps
CPU time 0.81 seconds
Started Aug 06 08:03:26 PM PDT 24
Finished Aug 06 08:03:27 PM PDT 24
Peak memory 207340 kb
Host smart-eef57bbc-6d51-439c-b7d5-29b6b6116678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66353
9428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.663539428
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3284504608
Short name T1437
Test name
Test status
Simulation time 88918260 ps
CPU time 0.77 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:03:28 PM PDT 24
Peak memory 207364 kb
Host smart-7705a1b7-40a0-4451-a523-641e739540ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32845
04608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3284504608
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2653994137
Short name T1644
Test name
Test status
Simulation time 753447245 ps
CPU time 2.13 seconds
Started Aug 06 08:03:29 PM PDT 24
Finished Aug 06 08:03:31 PM PDT 24
Peak memory 207600 kb
Host smart-5385e458-115e-4b60-a72d-4b6be8f96141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26539
94137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2653994137
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_types.3975272810
Short name T431
Test name
Test status
Simulation time 249888850 ps
CPU time 0.99 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:03:28 PM PDT 24
Peak memory 207344 kb
Host smart-3fdfa822-daca-47d1-9eac-dfc68ec2b5f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3975272810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.3975272810
Directory /workspace/11.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.252092679
Short name T2286
Test name
Test status
Simulation time 174271422 ps
CPU time 1.82 seconds
Started Aug 06 08:03:28 PM PDT 24
Finished Aug 06 08:03:30 PM PDT 24
Peak memory 207468 kb
Host smart-e45731e4-ab3b-4448-a457-31bf515ff6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25209
2679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.252092679
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2162648544
Short name T633
Test name
Test status
Simulation time 257437576 ps
CPU time 1.19 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:03:28 PM PDT 24
Peak memory 207484 kb
Host smart-fdfae628-24bc-41f7-8cbf-952e7c5e2c45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2162648544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2162648544
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.147140111
Short name T1744
Test name
Test status
Simulation time 137233838 ps
CPU time 0.81 seconds
Started Aug 06 08:03:33 PM PDT 24
Finished Aug 06 08:03:34 PM PDT 24
Peak memory 207320 kb
Host smart-dcc18ec9-4295-4908-b403-ea0934319e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14714
0111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.147140111
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.408865511
Short name T1567
Test name
Test status
Simulation time 250192523 ps
CPU time 0.99 seconds
Started Aug 06 08:03:27 PM PDT 24
Finished Aug 06 08:03:28 PM PDT 24
Peak memory 207304 kb
Host smart-7bd1359c-3659-4317-84a2-e7dcc1890adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40886
5511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.408865511
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.703677245
Short name T3080
Test name
Test status
Simulation time 4327506476 ps
CPU time 43.77 seconds
Started Aug 06 08:03:29 PM PDT 24
Finished Aug 06 08:04:13 PM PDT 24
Peak memory 217812 kb
Host smart-9dbe4959-ee07-4d30-80d0-9a5e441aedde
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=703677245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.703677245
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.4011810059
Short name T2643
Test name
Test status
Simulation time 268490427 ps
CPU time 1.03 seconds
Started Aug 06 08:03:36 PM PDT 24
Finished Aug 06 08:03:38 PM PDT 24
Peak memory 207288 kb
Host smart-ed60a497-65e7-407d-8698-6448b246f93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40118
10059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.4011810059
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.455834327
Short name T1165
Test name
Test status
Simulation time 23973357498 ps
CPU time 30.63 seconds
Started Aug 06 08:03:30 PM PDT 24
Finished Aug 06 08:04:01 PM PDT 24
Peak memory 215832 kb
Host smart-1376a98f-e285-4b76-bd49-db4621244185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45583
4327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.455834327
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.4078051459
Short name T2185
Test name
Test status
Simulation time 11028943973 ps
CPU time 14.85 seconds
Started Aug 06 08:03:36 PM PDT 24
Finished Aug 06 08:03:51 PM PDT 24
Peak memory 207552 kb
Host smart-f2b45b95-2114-476c-93b7-d82b415c0f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40780
51459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.4078051459
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.3096278683
Short name T2652
Test name
Test status
Simulation time 3305568776 ps
CPU time 23.16 seconds
Started Aug 06 08:03:29 PM PDT 24
Finished Aug 06 08:03:52 PM PDT 24
Peak memory 215688 kb
Host smart-3267210e-643b-4d77-b260-42d11972d2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30962
78683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3096278683
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.1119812694
Short name T1388
Test name
Test status
Simulation time 2787988188 ps
CPU time 28.55 seconds
Started Aug 06 08:03:36 PM PDT 24
Finished Aug 06 08:04:05 PM PDT 24
Peak memory 217468 kb
Host smart-f614dcd7-a40a-4641-9c3f-fb105c1d0724
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1119812694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.1119812694
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2204997614
Short name T1789
Test name
Test status
Simulation time 271726743 ps
CPU time 1.01 seconds
Started Aug 06 08:03:30 PM PDT 24
Finished Aug 06 08:03:32 PM PDT 24
Peak memory 207348 kb
Host smart-825d5130-00e6-438a-b12b-061e5327941e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2204997614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2204997614
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.4008114980
Short name T1663
Test name
Test status
Simulation time 206787171 ps
CPU time 1.05 seconds
Started Aug 06 08:03:26 PM PDT 24
Finished Aug 06 08:03:27 PM PDT 24
Peak memory 207396 kb
Host smart-3dab271f-34e2-40a9-9f5b-384650cd0810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40081
14980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.4008114980
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.4111348089
Short name T2171
Test name
Test status
Simulation time 2093954897 ps
CPU time 21.02 seconds
Started Aug 06 08:03:40 PM PDT 24
Finished Aug 06 08:04:01 PM PDT 24
Peak memory 217320 kb
Host smart-70d37796-ec62-4fea-a950-ab5eb6547f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41113
48089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.4111348089
Directory /workspace/11.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.938754937
Short name T2124
Test name
Test status
Simulation time 2560001430 ps
CPU time 70.49 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:04:52 PM PDT 24
Peak memory 215856 kb
Host smart-6313840c-4f2a-4058-b6fa-0e17e79234d4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=938754937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.938754937
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.938430054
Short name T779
Test name
Test status
Simulation time 156969796 ps
CPU time 0.84 seconds
Started Aug 06 08:03:40 PM PDT 24
Finished Aug 06 08:03:40 PM PDT 24
Peak memory 207344 kb
Host smart-0f488fac-c0c6-42dc-870f-83ba0fe5cb35
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=938430054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.938430054
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3212329037
Short name T1191
Test name
Test status
Simulation time 148939801 ps
CPU time 0.88 seconds
Started Aug 06 08:03:40 PM PDT 24
Finished Aug 06 08:03:41 PM PDT 24
Peak memory 207296 kb
Host smart-4530e338-05a5-4344-8ddd-ce531ad788ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32123
29037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3212329037
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3892638705
Short name T141
Test name
Test status
Simulation time 212735008 ps
CPU time 0.96 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:03:42 PM PDT 24
Peak memory 207364 kb
Host smart-f8150aca-4eb6-4e7a-b6dc-fdbe12f1c13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38926
38705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3892638705
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2024632607
Short name T927
Test name
Test status
Simulation time 169827386 ps
CPU time 0.91 seconds
Started Aug 06 08:03:40 PM PDT 24
Finished Aug 06 08:03:41 PM PDT 24
Peak memory 207364 kb
Host smart-330a0db3-a211-44e0-a35e-ce235b984dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20246
32607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2024632607
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2390859063
Short name T520
Test name
Test status
Simulation time 173409243 ps
CPU time 0.93 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207412 kb
Host smart-d6419c14-5513-4e78-a710-9f1f2f225138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23908
59063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2390859063
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.963378485
Short name T3115
Test name
Test status
Simulation time 147874964 ps
CPU time 0.85 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207320 kb
Host smart-b09aa1d0-d2e3-4b53-817c-48cfefcde721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96337
8485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.963378485
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.634411295
Short name T2302
Test name
Test status
Simulation time 172412490 ps
CPU time 0.88 seconds
Started Aug 06 08:03:44 PM PDT 24
Finished Aug 06 08:03:45 PM PDT 24
Peak memory 207356 kb
Host smart-0b8b6065-fb1c-4bdd-93d0-a52f20de92cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63441
1295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.634411295
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.3276344970
Short name T2859
Test name
Test status
Simulation time 251437402 ps
CPU time 1.01 seconds
Started Aug 06 08:03:39 PM PDT 24
Finished Aug 06 08:03:40 PM PDT 24
Peak memory 207432 kb
Host smart-69cfc5c1-3bfb-4aab-a072-f29c1fdde899
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3276344970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.3276344970
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.856563508
Short name T219
Test name
Test status
Simulation time 163048230 ps
CPU time 0.86 seconds
Started Aug 06 08:03:38 PM PDT 24
Finished Aug 06 08:03:39 PM PDT 24
Peak memory 207284 kb
Host smart-c663fc57-320c-4b51-b3fc-83f339fb9dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85656
3508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.856563508
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3449028230
Short name T1593
Test name
Test status
Simulation time 22804505600 ps
CPU time 58.95 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:04:40 PM PDT 24
Peak memory 215876 kb
Host smart-a463284c-7a68-4b50-9309-7249d052e007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34490
28230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3449028230
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.376322469
Short name T2226
Test name
Test status
Simulation time 168982465 ps
CPU time 0.96 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207376 kb
Host smart-2e55026b-008d-49f2-80e2-19b2dc1872cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37632
2469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.376322469
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2364587561
Short name T2177
Test name
Test status
Simulation time 296135671 ps
CPU time 1.02 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 207328 kb
Host smart-f6fa9805-63ee-46c9-9851-63885f3d473d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23645
87561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2364587561
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.2897451776
Short name T3032
Test name
Test status
Simulation time 224627318 ps
CPU time 0.99 seconds
Started Aug 06 08:03:46 PM PDT 24
Finished Aug 06 08:03:47 PM PDT 24
Peak memory 207348 kb
Host smart-2be41034-8c78-498e-95de-6eb85a051d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28974
51776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.2897451776
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.2217007143
Short name T2620
Test name
Test status
Simulation time 182202838 ps
CPU time 0.91 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:03:42 PM PDT 24
Peak memory 207336 kb
Host smart-9cd6ff97-10a4-4bb8-be12-42cd3dfa1988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22170
07143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2217007143
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_resume_link_active.3172190486
Short name T240
Test name
Test status
Simulation time 20191986264 ps
CPU time 21.57 seconds
Started Aug 06 08:03:43 PM PDT 24
Finished Aug 06 08:04:05 PM PDT 24
Peak memory 207404 kb
Host smart-96a6927f-0930-4c0f-a9e1-0aebf5d97ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31721
90486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.3172190486
Directory /workspace/11.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1539099050
Short name T1523
Test name
Test status
Simulation time 175346670 ps
CPU time 0.84 seconds
Started Aug 06 08:03:38 PM PDT 24
Finished Aug 06 08:03:39 PM PDT 24
Peak memory 207340 kb
Host smart-8e7620bc-9eb6-4022-b9a0-e177bc7569e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15390
99050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1539099050
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_rx_full.4175882972
Short name T52
Test name
Test status
Simulation time 383390469 ps
CPU time 1.3 seconds
Started Aug 06 08:03:46 PM PDT 24
Finished Aug 06 08:03:47 PM PDT 24
Peak memory 207304 kb
Host smart-209f61db-361f-4782-b03a-051319d03856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41758
82972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.4175882972
Directory /workspace/11.usbdev_rx_full/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.4034372207
Short name T2755
Test name
Test status
Simulation time 152664054 ps
CPU time 0.84 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207360 kb
Host smart-187f8104-08dd-4fc1-bf5c-ddfd95f6ec2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40343
72207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.4034372207
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.961710740
Short name T97
Test name
Test status
Simulation time 143943887 ps
CPU time 0.92 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207604 kb
Host smart-e8f78d09-7697-4030-a128-afca876908d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96171
0740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.961710740
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1993045912
Short name T2360
Test name
Test status
Simulation time 178140688 ps
CPU time 0.95 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207404 kb
Host smart-9d95c5f3-c976-4453-8956-92b3556a1854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19930
45912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1993045912
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.2424404206
Short name T1885
Test name
Test status
Simulation time 3354948544 ps
CPU time 34.59 seconds
Started Aug 06 08:03:40 PM PDT 24
Finished Aug 06 08:04:15 PM PDT 24
Peak memory 223960 kb
Host smart-7bea4780-0ca2-4b26-9088-0e618ca54a4e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2424404206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.2424404206
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3455030732
Short name T555
Test name
Test status
Simulation time 167277769 ps
CPU time 0.86 seconds
Started Aug 06 08:03:40 PM PDT 24
Finished Aug 06 08:03:41 PM PDT 24
Peak memory 207288 kb
Host smart-f0d74b4d-8dac-4980-a16a-c25027ddf5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34550
30732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3455030732
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.257888912
Short name T1828
Test name
Test status
Simulation time 1306838905 ps
CPU time 3.05 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:03:45 PM PDT 24
Peak memory 207544 kb
Host smart-dacbccdd-28b3-43f8-ad5f-3fb88c150b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25788
8912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.257888912
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2786704322
Short name T3001
Test name
Test status
Simulation time 2050413551 ps
CPU time 21.24 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:04:02 PM PDT 24
Peak memory 217004 kb
Host smart-8c67b161-e06b-47cb-9c7c-3b6929b2ead4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
04322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2786704322
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.990646777
Short name T1107
Test name
Test status
Simulation time 4359522677 ps
CPU time 39.43 seconds
Started Aug 06 08:03:36 PM PDT 24
Finished Aug 06 08:04:16 PM PDT 24
Peak memory 207652 kb
Host smart-b84aeaad-199f-4bb9-9742-48de79a94287
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990646777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_host
_handshake.990646777
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/110.usbdev_endpoint_types.1335080556
Short name T1970
Test name
Test status
Simulation time 396961454 ps
CPU time 1.2 seconds
Started Aug 06 08:09:10 PM PDT 24
Finished Aug 06 08:09:11 PM PDT 24
Peak memory 207348 kb
Host smart-c75ec961-ef7e-4267-93cf-28deebe36bcf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1335080556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.1335080556
Directory /workspace/110.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/111.usbdev_endpoint_types.3026859948
Short name T412
Test name
Test status
Simulation time 316089299 ps
CPU time 1.21 seconds
Started Aug 06 08:09:05 PM PDT 24
Finished Aug 06 08:09:06 PM PDT 24
Peak memory 207292 kb
Host smart-487a68e6-b88a-41f9-9211-39a7232ebeb6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3026859948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.3026859948
Directory /workspace/111.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/114.usbdev_endpoint_types.885145901
Short name T1271
Test name
Test status
Simulation time 163990057 ps
CPU time 0.93 seconds
Started Aug 06 08:09:18 PM PDT 24
Finished Aug 06 08:09:19 PM PDT 24
Peak memory 207344 kb
Host smart-48317023-e440-455f-ae94-940aefb3a710
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=885145901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.885145901
Directory /workspace/114.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/115.usbdev_endpoint_types.4057296100
Short name T471
Test name
Test status
Simulation time 578777822 ps
CPU time 1.44 seconds
Started Aug 06 08:09:12 PM PDT 24
Finished Aug 06 08:09:14 PM PDT 24
Peak memory 207328 kb
Host smart-599861a6-e1fa-4145-aacd-6b34a00a8e68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4057296100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.4057296100
Directory /workspace/115.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/116.usbdev_endpoint_types.3589913318
Short name T401
Test name
Test status
Simulation time 661813643 ps
CPU time 1.6 seconds
Started Aug 06 08:09:13 PM PDT 24
Finished Aug 06 08:09:15 PM PDT 24
Peak memory 207292 kb
Host smart-ee0b7102-c6ea-4a1f-965b-138c362b71ec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3589913318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.3589913318
Directory /workspace/116.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/117.usbdev_endpoint_types.1215512933
Short name T402
Test name
Test status
Simulation time 418718665 ps
CPU time 1.3 seconds
Started Aug 06 08:09:15 PM PDT 24
Finished Aug 06 08:09:16 PM PDT 24
Peak memory 207348 kb
Host smart-7ffccd84-1e6c-49b2-98d6-53c66dce88cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1215512933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.1215512933
Directory /workspace/117.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/118.usbdev_endpoint_types.2476715871
Short name T2872
Test name
Test status
Simulation time 454487908 ps
CPU time 1.51 seconds
Started Aug 06 08:09:14 PM PDT 24
Finished Aug 06 08:09:16 PM PDT 24
Peak memory 207328 kb
Host smart-ca0f60a9-a913-4dc6-8b48-36ac8c28bd2b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2476715871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.2476715871
Directory /workspace/118.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.3062141371
Short name T2018
Test name
Test status
Simulation time 35932178 ps
CPU time 0.66 seconds
Started Aug 06 08:03:49 PM PDT 24
Finished Aug 06 08:03:49 PM PDT 24
Peak memory 207428 kb
Host smart-22b5c150-4ec6-4cbc-a7ba-e71496d8ca65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3062141371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.3062141371
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.502490633
Short name T641
Test name
Test status
Simulation time 11803338792 ps
CPU time 13.81 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207652 kb
Host smart-3b3404c0-e6fe-4402-910e-5582abf58144
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502490633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ao
n_wake_disconnect.502490633
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.887038133
Short name T1749
Test name
Test status
Simulation time 13929848695 ps
CPU time 18.06 seconds
Started Aug 06 08:03:40 PM PDT 24
Finished Aug 06 08:03:58 PM PDT 24
Peak memory 215816 kb
Host smart-be93077a-0bf3-463c-93a2-5b3acfe504df
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=887038133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.887038133
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.1351805816
Short name T585
Test name
Test status
Simulation time 23962677396 ps
CPU time 26.04 seconds
Started Aug 06 08:03:39 PM PDT 24
Finished Aug 06 08:04:06 PM PDT 24
Peak memory 215856 kb
Host smart-8c4c1dbb-6f6e-4b95-9d1d-e89811cbd8b7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351805816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.1351805816
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2759758007
Short name T2892
Test name
Test status
Simulation time 148996644 ps
CPU time 0.83 seconds
Started Aug 06 08:03:46 PM PDT 24
Finished Aug 06 08:03:47 PM PDT 24
Peak memory 207324 kb
Host smart-ca26c701-e268-442f-8bd5-8d7d6e32d2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27597
58007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2759758007
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1231220958
Short name T1053
Test name
Test status
Simulation time 164214452 ps
CPU time 0.92 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207380 kb
Host smart-6ec319a8-4929-4c5a-92a3-950b37829b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12312
20958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1231220958
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3473941689
Short name T1397
Test name
Test status
Simulation time 419814059 ps
CPU time 1.37 seconds
Started Aug 06 08:03:44 PM PDT 24
Finished Aug 06 08:03:45 PM PDT 24
Peak memory 207360 kb
Host smart-16c21994-9791-47ee-81cb-6042f29db08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34739
41689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3473941689
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3222935834
Short name T2470
Test name
Test status
Simulation time 841869945 ps
CPU time 2.23 seconds
Started Aug 06 08:03:43 PM PDT 24
Finished Aug 06 08:03:45 PM PDT 24
Peak memory 207636 kb
Host smart-fc187a0a-fd52-44bd-8861-2251f0cbd3a0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3222935834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3222935834
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.2043595307
Short name T987
Test name
Test status
Simulation time 28795310449 ps
CPU time 50.58 seconds
Started Aug 06 08:03:40 PM PDT 24
Finished Aug 06 08:04:31 PM PDT 24
Peak memory 207644 kb
Host smart-3830ff9f-4fa9-4dff-a196-11e94e25a82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20435
95307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.2043595307
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.32453463
Short name T1562
Test name
Test status
Simulation time 1303804594 ps
CPU time 30.71 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207432 kb
Host smart-a47ea466-32e8-409b-9cd7-5964d790adb3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32453463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.32453463
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3931473366
Short name T1849
Test name
Test status
Simulation time 940075177 ps
CPU time 1.99 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 207376 kb
Host smart-0a5b64d0-e71a-45c5-b42f-03c97d01a419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39314
73366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3931473366
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3589623296
Short name T2375
Test name
Test status
Simulation time 144059660 ps
CPU time 0.84 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:03:42 PM PDT 24
Peak memory 207300 kb
Host smart-a02d4e72-5ee4-4b23-bbeb-991cb57030a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35896
23296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3589623296
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.314845069
Short name T2925
Test name
Test status
Simulation time 41249464 ps
CPU time 0.76 seconds
Started Aug 06 08:03:43 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 207320 kb
Host smart-d11dd99c-eba4-436a-a2b4-2dad481abcb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31484
5069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.314845069
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.944559081
Short name T1099
Test name
Test status
Simulation time 980616970 ps
CPU time 2.62 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 207576 kb
Host smart-c604ac6a-b128-408a-a0ab-276cdc0fc3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94455
9081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.944559081
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_types.2237667412
Short name T433
Test name
Test status
Simulation time 428243226 ps
CPU time 1.35 seconds
Started Aug 06 08:03:39 PM PDT 24
Finished Aug 06 08:03:40 PM PDT 24
Peak memory 207212 kb
Host smart-de0f4a75-df7a-4095-9b65-1fadc9d16e91
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2237667412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.2237667412
Directory /workspace/12.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2093749129
Short name T3092
Test name
Test status
Simulation time 176881120 ps
CPU time 2.06 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:45 PM PDT 24
Peak memory 207452 kb
Host smart-9ae7c4a5-9e0b-4c73-a9ef-f700e68c2cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20937
49129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2093749129
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1865179952
Short name T993
Test name
Test status
Simulation time 167505808 ps
CPU time 0.93 seconds
Started Aug 06 08:03:39 PM PDT 24
Finished Aug 06 08:03:40 PM PDT 24
Peak memory 207380 kb
Host smart-efb59c80-549a-4e09-a1ff-75846cda5ab5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1865179952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1865179952
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.116567035
Short name T2906
Test name
Test status
Simulation time 155232302 ps
CPU time 0.84 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:03:42 PM PDT 24
Peak memory 207260 kb
Host smart-c595cdbd-870f-4edd-9995-c38f6ee6a4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
7035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.116567035
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1810984621
Short name T2868
Test name
Test status
Simulation time 240986566 ps
CPU time 1.04 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207416 kb
Host smart-14d71de5-f3f5-4532-bd63-dca5e914465e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18109
84621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1810984621
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.288663490
Short name T2145
Test name
Test status
Simulation time 3307760370 ps
CPU time 24.68 seconds
Started Aug 06 08:03:45 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 215852 kb
Host smart-f8c638a5-a1eb-43f6-b729-dbb9b799d40a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=288663490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.288663490
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.2838454030
Short name T2700
Test name
Test status
Simulation time 6478005540 ps
CPU time 73.93 seconds
Started Aug 06 08:03:40 PM PDT 24
Finished Aug 06 08:04:54 PM PDT 24
Peak memory 207580 kb
Host smart-fe41712d-c234-469b-b985-670242d974e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2838454030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.2838454030
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.497656067
Short name T2031
Test name
Test status
Simulation time 163290672 ps
CPU time 0.85 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:03:42 PM PDT 24
Peak memory 207332 kb
Host smart-1655e297-221d-426f-b9a0-4606416d2953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49765
6067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.497656067
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.3297085517
Short name T2132
Test name
Test status
Simulation time 9649401074 ps
CPU time 12.61 seconds
Started Aug 06 08:03:45 PM PDT 24
Finished Aug 06 08:03:57 PM PDT 24
Peak memory 207620 kb
Host smart-3e109097-55c5-4bab-8f93-cabca6bdaf67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32970
85517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.3297085517
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.284475901
Short name T2771
Test name
Test status
Simulation time 9624094629 ps
CPU time 12.72 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:03:54 PM PDT 24
Peak memory 207660 kb
Host smart-288a44e8-62e7-416e-8428-5260704e322e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28447
5901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.284475901
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.3673964465
Short name T2976
Test name
Test status
Simulation time 4810332608 ps
CPU time 35.89 seconds
Started Aug 06 08:03:46 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 217208 kb
Host smart-b36368c4-4ea0-4343-8bdb-92e5aef9969a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36739
64465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.3673964465
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.1709114847
Short name T2964
Test name
Test status
Simulation time 1976298644 ps
CPU time 53.11 seconds
Started Aug 06 08:03:47 PM PDT 24
Finished Aug 06 08:04:40 PM PDT 24
Peak memory 215640 kb
Host smart-14833322-6f18-440d-bdba-c8dd39a6503e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1709114847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.1709114847
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.3037579477
Short name T2365
Test name
Test status
Simulation time 241493410 ps
CPU time 1.03 seconds
Started Aug 06 08:03:46 PM PDT 24
Finished Aug 06 08:03:47 PM PDT 24
Peak memory 207288 kb
Host smart-764cfad2-b5eb-4863-83be-a593ce4301f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3037579477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.3037579477
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3399818901
Short name T2257
Test name
Test status
Simulation time 204620828 ps
CPU time 0.96 seconds
Started Aug 06 08:03:43 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 207400 kb
Host smart-e9c78108-1726-4d54-9b4c-705390d35d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33998
18901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3399818901
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.1946904454
Short name T3075
Test name
Test status
Simulation time 3275735609 ps
CPU time 23.72 seconds
Started Aug 06 08:03:43 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 224068 kb
Host smart-c92b80ab-99f3-4984-882a-a092e1c3b67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19469
04454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.1946904454
Directory /workspace/12.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.4114633750
Short name T126
Test name
Test status
Simulation time 3350457742 ps
CPU time 92.68 seconds
Started Aug 06 08:03:44 PM PDT 24
Finished Aug 06 08:05:16 PM PDT 24
Peak memory 217472 kb
Host smart-125900ff-b5d6-487c-8b7d-3650cfc74109
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4114633750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.4114633750
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.283250053
Short name T2143
Test name
Test status
Simulation time 3142865601 ps
CPU time 24.87 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 215840 kb
Host smart-1b6216b5-fa2c-47e8-b5df-99a39d88e413
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=283250053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.283250053
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3294890184
Short name T1310
Test name
Test status
Simulation time 160436597 ps
CPU time 0.89 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207308 kb
Host smart-db36bfa1-30c2-45c8-a126-087b277020dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3294890184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3294890184
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2992047103
Short name T737
Test name
Test status
Simulation time 165194645 ps
CPU time 0.85 seconds
Started Aug 06 08:03:46 PM PDT 24
Finished Aug 06 08:03:47 PM PDT 24
Peak memory 207292 kb
Host smart-9ef458cb-8b52-48e4-8951-62068d57612a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29920
47103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2992047103
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.127288659
Short name T132
Test name
Test status
Simulation time 238514884 ps
CPU time 1.01 seconds
Started Aug 06 08:03:43 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 207596 kb
Host smart-2abfe68e-8687-4da8-8c30-ea7fcfc3a28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12728
8659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.127288659
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3611767812
Short name T130
Test name
Test status
Simulation time 185139649 ps
CPU time 0.93 seconds
Started Aug 06 08:03:43 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 207376 kb
Host smart-c34b22e9-2762-4c3c-b704-9f3e279580a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36117
67812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3611767812
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1696262956
Short name T788
Test name
Test status
Simulation time 164567660 ps
CPU time 0.83 seconds
Started Aug 06 08:03:44 PM PDT 24
Finished Aug 06 08:03:45 PM PDT 24
Peak memory 207348 kb
Host smart-2dcec1cb-fa04-470d-8968-c9a96c4e9a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16962
62956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1696262956
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3184304650
Short name T2170
Test name
Test status
Simulation time 232662312 ps
CPU time 1.02 seconds
Started Aug 06 08:03:44 PM PDT 24
Finished Aug 06 08:03:45 PM PDT 24
Peak memory 207292 kb
Host smart-5f662e58-f184-4218-8712-6907f0f85ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31843
04650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3184304650
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.35062168
Short name T1732
Test name
Test status
Simulation time 165942049 ps
CPU time 0.84 seconds
Started Aug 06 08:03:45 PM PDT 24
Finished Aug 06 08:03:46 PM PDT 24
Peak memory 207356 kb
Host smart-4b841263-dcc8-4a05-a253-be3dd058c495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35062
168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.35062168
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.22138602
Short name T2648
Test name
Test status
Simulation time 260352044 ps
CPU time 1.11 seconds
Started Aug 06 08:03:40 PM PDT 24
Finished Aug 06 08:03:41 PM PDT 24
Peak memory 207388 kb
Host smart-2c377303-8096-4abc-8862-b5a4e9bebf63
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=22138602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.22138602
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1044870527
Short name T1286
Test name
Test status
Simulation time 187136942 ps
CPU time 0.93 seconds
Started Aug 06 08:03:43 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 207348 kb
Host smart-2365ba5a-2014-4a56-b07f-4aefc827b274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10448
70527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1044870527
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3386537554
Short name T2568
Test name
Test status
Simulation time 52472287 ps
CPU time 0.68 seconds
Started Aug 06 08:03:45 PM PDT 24
Finished Aug 06 08:03:46 PM PDT 24
Peak memory 207344 kb
Host smart-c85e12b0-16b9-4fc9-be55-b3d8be782ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33865
37554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3386537554
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3483650687
Short name T1871
Test name
Test status
Simulation time 9568151622 ps
CPU time 26.49 seconds
Started Aug 06 08:03:45 PM PDT 24
Finished Aug 06 08:04:11 PM PDT 24
Peak memory 215872 kb
Host smart-e2c2ad9b-04f3-46a4-b88a-dba4a1b5ac1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
50687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3483650687
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1239392613
Short name T1441
Test name
Test status
Simulation time 166536549 ps
CPU time 0.92 seconds
Started Aug 06 08:03:46 PM PDT 24
Finished Aug 06 08:03:47 PM PDT 24
Peak memory 207288 kb
Host smart-d95a5428-5629-4a51-b806-0167e90e8eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12393
92613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1239392613
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3354084376
Short name T1866
Test name
Test status
Simulation time 222190430 ps
CPU time 0.96 seconds
Started Aug 06 08:03:45 PM PDT 24
Finished Aug 06 08:03:46 PM PDT 24
Peak memory 207324 kb
Host smart-35534619-f9e3-4b33-ac22-f3c3482844ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33540
84376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3354084376
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.2006442588
Short name T2038
Test name
Test status
Simulation time 192972758 ps
CPU time 0.89 seconds
Started Aug 06 08:03:43 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 207384 kb
Host smart-2e2ec021-55e5-4083-9c7b-aa1302ca97b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20064
42588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.2006442588
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.2077772208
Short name T2649
Test name
Test status
Simulation time 177854902 ps
CPU time 0.87 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207396 kb
Host smart-9a32fbda-b5b8-4996-8427-952dbef92965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20777
72208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.2077772208
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_resume_link_active.3199495136
Short name T2363
Test name
Test status
Simulation time 20167604939 ps
CPU time 24.18 seconds
Started Aug 06 08:03:48 PM PDT 24
Finished Aug 06 08:04:13 PM PDT 24
Peak memory 207404 kb
Host smart-a8a9214c-f983-450e-b7bb-1de7aa8fd347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31994
95136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.3199495136
Directory /workspace/12.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.120138552
Short name T552
Test name
Test status
Simulation time 166473699 ps
CPU time 0.86 seconds
Started Aug 06 08:03:45 PM PDT 24
Finished Aug 06 08:03:46 PM PDT 24
Peak memory 207380 kb
Host smart-3807fdae-1c9d-4936-8da2-83cd7c64ecc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12013
8552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.120138552
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_rx_full.3822732159
Short name T2406
Test name
Test status
Simulation time 330214933 ps
CPU time 1.15 seconds
Started Aug 06 08:03:39 PM PDT 24
Finished Aug 06 08:03:41 PM PDT 24
Peak memory 207356 kb
Host smart-89de7971-419c-4821-a85f-0fc5ab4dc5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227
32159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.3822732159
Directory /workspace/12.usbdev_rx_full/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2297782065
Short name T2184
Test name
Test status
Simulation time 146592510 ps
CPU time 0.84 seconds
Started Aug 06 08:03:48 PM PDT 24
Finished Aug 06 08:03:49 PM PDT 24
Peak memory 207284 kb
Host smart-9dc8c846-6519-4065-b68d-1ef583526459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22977
82065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2297782065
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1480306856
Short name T589
Test name
Test status
Simulation time 151615560 ps
CPU time 0.83 seconds
Started Aug 06 08:03:45 PM PDT 24
Finished Aug 06 08:03:46 PM PDT 24
Peak memory 207344 kb
Host smart-635076e4-e0db-4cc5-bc1d-9ecd7088a69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14803
06856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1480306856
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3811867665
Short name T1340
Test name
Test status
Simulation time 222236045 ps
CPU time 0.99 seconds
Started Aug 06 08:03:45 PM PDT 24
Finished Aug 06 08:03:46 PM PDT 24
Peak memory 207380 kb
Host smart-3be50db0-aefe-48d2-9f07-848a2e6a3f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38118
67665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3811867665
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3878949309
Short name T2699
Test name
Test status
Simulation time 1832340907 ps
CPU time 52.05 seconds
Started Aug 06 08:03:50 PM PDT 24
Finished Aug 06 08:04:42 PM PDT 24
Peak memory 217068 kb
Host smart-3d80b4fd-a409-42cf-9a8f-e9a15ebcb483
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3878949309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3878949309
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.355770652
Short name T1383
Test name
Test status
Simulation time 196961681 ps
CPU time 0.85 seconds
Started Aug 06 08:03:44 PM PDT 24
Finished Aug 06 08:03:45 PM PDT 24
Peak memory 207320 kb
Host smart-317301a1-13a8-4c78-bff6-9bb8accdb852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35577
0652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.355770652
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3832975469
Short name T534
Test name
Test status
Simulation time 170273235 ps
CPU time 0.88 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207400 kb
Host smart-c20a6f3c-6d0d-40db-b464-fca7bbaadcfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38329
75469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3832975469
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3053026388
Short name T2949
Test name
Test status
Simulation time 506856976 ps
CPU time 1.61 seconds
Started Aug 06 08:03:49 PM PDT 24
Finished Aug 06 08:03:51 PM PDT 24
Peak memory 207288 kb
Host smart-0247b95f-6084-4eaa-b93d-4d69c977a821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30530
26388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3053026388
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.2400492643
Short name T561
Test name
Test status
Simulation time 3141831042 ps
CPU time 33.82 seconds
Started Aug 06 08:03:41 PM PDT 24
Finished Aug 06 08:04:15 PM PDT 24
Peak memory 217236 kb
Host smart-d1cfdb4e-0789-4810-a14c-7925d88b8a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24004
92643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.2400492643
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.577975794
Short name T941
Test name
Test status
Simulation time 287312329 ps
CPU time 4.29 seconds
Started Aug 06 08:03:42 PM PDT 24
Finished Aug 06 08:03:47 PM PDT 24
Peak memory 207544 kb
Host smart-f739fc6f-5c7f-4b60-93fe-9cdb62853b13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577975794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_host
_handshake.577975794
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/120.usbdev_endpoint_types.2214641318
Short name T372
Test name
Test status
Simulation time 603487634 ps
CPU time 1.56 seconds
Started Aug 06 08:09:14 PM PDT 24
Finished Aug 06 08:09:16 PM PDT 24
Peak memory 207288 kb
Host smart-11c4e386-4506-4c82-b0cb-97dd62a856d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2214641318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.2214641318
Directory /workspace/120.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/123.usbdev_endpoint_types.2515680215
Short name T427
Test name
Test status
Simulation time 373762994 ps
CPU time 1.21 seconds
Started Aug 06 08:09:08 PM PDT 24
Finished Aug 06 08:09:10 PM PDT 24
Peak memory 207288 kb
Host smart-ef43302d-47cb-422a-b07c-f41580c4680a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2515680215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.2515680215
Directory /workspace/123.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/124.usbdev_endpoint_types.1991440009
Short name T390
Test name
Test status
Simulation time 733464774 ps
CPU time 1.6 seconds
Started Aug 06 08:09:19 PM PDT 24
Finished Aug 06 08:09:20 PM PDT 24
Peak memory 207288 kb
Host smart-6ba3b56e-50d6-4843-996d-048f697edc99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1991440009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.1991440009
Directory /workspace/124.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/125.usbdev_endpoint_types.3712595590
Short name T457
Test name
Test status
Simulation time 600257003 ps
CPU time 1.57 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:12 PM PDT 24
Peak memory 207348 kb
Host smart-6e35a731-b275-4ea4-826a-bbaacef28e48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3712595590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.3712595590
Directory /workspace/125.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/127.usbdev_endpoint_types.2820151437
Short name T405
Test name
Test status
Simulation time 559848192 ps
CPU time 1.39 seconds
Started Aug 06 08:09:09 PM PDT 24
Finished Aug 06 08:09:11 PM PDT 24
Peak memory 207268 kb
Host smart-a543a11f-4560-4790-9372-f714b7e260ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2820151437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.2820151437
Directory /workspace/127.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/128.usbdev_endpoint_types.1694957300
Short name T407
Test name
Test status
Simulation time 286138429 ps
CPU time 1.15 seconds
Started Aug 06 08:09:08 PM PDT 24
Finished Aug 06 08:09:09 PM PDT 24
Peak memory 207372 kb
Host smart-1705622c-fbd3-48fd-a735-d7f7f354ab9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1694957300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.1694957300
Directory /workspace/128.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/129.usbdev_endpoint_types.1375984542
Short name T2513
Test name
Test status
Simulation time 202396832 ps
CPU time 0.95 seconds
Started Aug 06 08:09:15 PM PDT 24
Finished Aug 06 08:09:16 PM PDT 24
Peak memory 207356 kb
Host smart-8ca20062-aaed-47e5-9ae5-55627ad04157
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1375984542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.1375984542
Directory /workspace/129.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.4167732587
Short name T2237
Test name
Test status
Simulation time 90395864 ps
CPU time 0.69 seconds
Started Aug 06 08:03:59 PM PDT 24
Finished Aug 06 08:04:00 PM PDT 24
Peak memory 207444 kb
Host smart-27bf1599-223a-42ae-acd3-1a9981e6fbb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4167732587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.4167732587
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.4261921796
Short name T14
Test name
Test status
Simulation time 4496109621 ps
CPU time 7.26 seconds
Started Aug 06 08:03:49 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 215772 kb
Host smart-93f18f3c-4332-4bbe-ab4f-30bc5f1f585d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261921796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.4261921796
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.298554031
Short name T3083
Test name
Test status
Simulation time 19628671038 ps
CPU time 25.6 seconds
Started Aug 06 08:03:45 PM PDT 24
Finished Aug 06 08:04:11 PM PDT 24
Peak memory 207612 kb
Host smart-c75fc7af-6467-4eaf-babe-75f5d1deab6b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=298554031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.298554031
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3405529894
Short name T1445
Test name
Test status
Simulation time 29126241746 ps
CPU time 37.74 seconds
Started Aug 06 08:03:45 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207660 kb
Host smart-6f53c7e6-cd49-4664-9531-ce8c50757356
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405529894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.3405529894
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3005613392
Short name T1742
Test name
Test status
Simulation time 177900183 ps
CPU time 0.92 seconds
Started Aug 06 08:03:51 PM PDT 24
Finished Aug 06 08:03:52 PM PDT 24
Peak memory 207332 kb
Host smart-497758fc-45c9-4386-b12f-4ca89ade8894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30056
13392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3005613392
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.1289458791
Short name T2626
Test name
Test status
Simulation time 135598284 ps
CPU time 0.93 seconds
Started Aug 06 08:03:53 PM PDT 24
Finished Aug 06 08:03:54 PM PDT 24
Peak memory 207280 kb
Host smart-105e53e3-7b5e-4b8d-9b9f-1893baec7674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12894
58791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1289458791
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.460449301
Short name T2845
Test name
Test status
Simulation time 265509494 ps
CPU time 1.01 seconds
Started Aug 06 08:03:58 PM PDT 24
Finished Aug 06 08:03:59 PM PDT 24
Peak memory 207352 kb
Host smart-f8c59408-29f5-4733-8fc4-9fb53cdb7c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46044
9301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.460449301
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.4161013373
Short name T2461
Test name
Test status
Simulation time 1140163910 ps
CPU time 2.86 seconds
Started Aug 06 08:03:53 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207508 kb
Host smart-8ef529d6-3b3e-4816-a564-10401514689d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4161013373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.4161013373
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.181894146
Short name T2596
Test name
Test status
Simulation time 56980929187 ps
CPU time 91.92 seconds
Started Aug 06 08:04:00 PM PDT 24
Finished Aug 06 08:05:32 PM PDT 24
Peak memory 207584 kb
Host smart-dd91495b-3716-4df6-bae6-34599f217b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18189
4146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.181894146
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.877083263
Short name T564
Test name
Test status
Simulation time 1616951065 ps
CPU time 10.43 seconds
Started Aug 06 08:03:53 PM PDT 24
Finished Aug 06 08:04:03 PM PDT 24
Peak memory 207572 kb
Host smart-ee7394ce-c571-4338-bd8c-9a207fedbd0e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877083263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.877083263
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.4145062088
Short name T2676
Test name
Test status
Simulation time 873117586 ps
CPU time 1.87 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:03:57 PM PDT 24
Peak memory 207356 kb
Host smart-5ff3bdac-25be-443f-830f-293f97b1c6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41450
62088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.4145062088
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_enable.3438683449
Short name T514
Test name
Test status
Simulation time 62001762 ps
CPU time 0.74 seconds
Started Aug 06 08:03:59 PM PDT 24
Finished Aug 06 08:04:00 PM PDT 24
Peak memory 207316 kb
Host smart-ba3a484a-3bb3-4911-995e-3455ad2ad47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34386
83449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3438683449
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.629109103
Short name T2657
Test name
Test status
Simulation time 744525683 ps
CPU time 2.03 seconds
Started Aug 06 08:03:52 PM PDT 24
Finished Aug 06 08:03:54 PM PDT 24
Peak memory 207420 kb
Host smart-38673e1e-63b3-4eed-b607-e6ddf015fcc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62910
9103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.629109103
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_types.2191695825
Short name T1706
Test name
Test status
Simulation time 210381734 ps
CPU time 1.04 seconds
Started Aug 06 08:03:56 PM PDT 24
Finished Aug 06 08:03:57 PM PDT 24
Peak memory 207296 kb
Host smart-4c87e0b0-fbaf-440a-b54e-0206cf7a49fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2191695825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.2191695825
Directory /workspace/13.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.912866242
Short name T2574
Test name
Test status
Simulation time 169263646 ps
CPU time 1.4 seconds
Started Aug 06 08:03:56 PM PDT 24
Finished Aug 06 08:03:57 PM PDT 24
Peak memory 207520 kb
Host smart-20cc431c-0767-44b6-a154-12ab2a6bf03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91286
6242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.912866242
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2242083226
Short name T1884
Test name
Test status
Simulation time 193413611 ps
CPU time 0.99 seconds
Started Aug 06 08:03:59 PM PDT 24
Finished Aug 06 08:04:00 PM PDT 24
Peak memory 207520 kb
Host smart-494a9653-05c4-4724-86c1-f2288ea5c0cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2242083226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2242083226
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3096530101
Short name T2637
Test name
Test status
Simulation time 168802485 ps
CPU time 0.85 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207336 kb
Host smart-a8c99450-5df1-4323-b9ae-3db1d191123a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30965
30101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3096530101
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.4240016799
Short name T617
Test name
Test status
Simulation time 213431473 ps
CPU time 0.93 seconds
Started Aug 06 08:03:54 PM PDT 24
Finished Aug 06 08:03:55 PM PDT 24
Peak memory 207396 kb
Host smart-67f8c3d6-2099-4df8-b0da-067ab8ffc2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42400
16799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.4240016799
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.1311365499
Short name T245
Test name
Test status
Simulation time 4213901317 ps
CPU time 42.89 seconds
Started Aug 06 08:03:52 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 224008 kb
Host smart-83b456c3-9b24-4cac-86e8-53670f0c1834
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1311365499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.1311365499
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.4032478894
Short name T1836
Test name
Test status
Simulation time 7271054769 ps
CPU time 90.02 seconds
Started Aug 06 08:03:54 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207620 kb
Host smart-5250774e-a4f3-4089-a740-574bf908c341
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4032478894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.4032478894
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.444162663
Short name T813
Test name
Test status
Simulation time 189728841 ps
CPU time 0.92 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207320 kb
Host smart-6f5e16dd-6f96-4681-8502-8e52ab85dfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44416
2663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.444162663
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.1194707897
Short name T1118
Test name
Test status
Simulation time 7483938824 ps
CPU time 9.08 seconds
Started Aug 06 08:03:54 PM PDT 24
Finished Aug 06 08:04:03 PM PDT 24
Peak memory 215748 kb
Host smart-61025cfe-7307-4646-8af2-cd08571a410f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11947
07897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.1194707897
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.1869599374
Short name T2655
Test name
Test status
Simulation time 9293912069 ps
CPU time 11.44 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207628 kb
Host smart-00205265-15d9-4644-a5ce-33c28f0f44ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18695
99374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.1869599374
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2124951224
Short name T1770
Test name
Test status
Simulation time 3944000661 ps
CPU time 39.08 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 217984 kb
Host smart-8c1092c2-fc35-4970-a657-cf982c9efc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21249
51224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2124951224
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1930275701
Short name T996
Test name
Test status
Simulation time 3715541545 ps
CPU time 28.47 seconds
Started Aug 06 08:03:58 PM PDT 24
Finished Aug 06 08:04:26 PM PDT 24
Peak memory 216124 kb
Host smart-2c7da949-8091-430b-a81c-ded157bfd69e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1930275701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1930275701
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2673187321
Short name T1096
Test name
Test status
Simulation time 245179780 ps
CPU time 0.99 seconds
Started Aug 06 08:03:54 PM PDT 24
Finished Aug 06 08:03:55 PM PDT 24
Peak memory 207368 kb
Host smart-2d83e437-38aa-415e-9df1-aa125ea4376a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2673187321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2673187321
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3496956230
Short name T2877
Test name
Test status
Simulation time 203968678 ps
CPU time 0.95 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207372 kb
Host smart-7d2d1755-d07a-4a12-9246-53645df4b975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34969
56230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3496956230
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.4233413515
Short name T1689
Test name
Test status
Simulation time 2924445654 ps
CPU time 22.91 seconds
Started Aug 06 08:03:57 PM PDT 24
Finished Aug 06 08:04:20 PM PDT 24
Peak memory 207652 kb
Host smart-c57c2a84-43ed-472d-b8fc-c8bff58a4ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42334
13515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.4233413515
Directory /workspace/13.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2885750909
Short name T1289
Test name
Test status
Simulation time 2336967939 ps
CPU time 70.76 seconds
Started Aug 06 08:03:57 PM PDT 24
Finished Aug 06 08:05:08 PM PDT 24
Peak memory 224044 kb
Host smart-0dbf1b81-a2a1-40df-ad49-f55bf9f4218a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2885750909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2885750909
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.274376994
Short name T583
Test name
Test status
Simulation time 2040089638 ps
CPU time 20.95 seconds
Started Aug 06 08:03:53 PM PDT 24
Finished Aug 06 08:04:14 PM PDT 24
Peak memory 217352 kb
Host smart-a78fc69c-f7d9-441f-8d00-b207074b08bb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=274376994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.274376994
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.4176664922
Short name T2228
Test name
Test status
Simulation time 190547556 ps
CPU time 1.01 seconds
Started Aug 06 08:03:56 PM PDT 24
Finished Aug 06 08:03:58 PM PDT 24
Peak memory 207356 kb
Host smart-4a20b00e-f03c-4f08-a69e-0cc524d06395
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4176664922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.4176664922
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.694170225
Short name T1569
Test name
Test status
Simulation time 166381444 ps
CPU time 0.83 seconds
Started Aug 06 08:04:00 PM PDT 24
Finished Aug 06 08:04:01 PM PDT 24
Peak memory 207356 kb
Host smart-6be593f3-2def-4bcb-a276-1275c359f533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69417
0225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.694170225
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3094310105
Short name T2785
Test name
Test status
Simulation time 213870682 ps
CPU time 0.97 seconds
Started Aug 06 08:03:57 PM PDT 24
Finished Aug 06 08:03:59 PM PDT 24
Peak memory 207372 kb
Host smart-841ef119-be96-497a-978c-b6a2ffcf0b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30943
10105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3094310105
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.483082173
Short name T2123
Test name
Test status
Simulation time 164179894 ps
CPU time 0.87 seconds
Started Aug 06 08:03:56 PM PDT 24
Finished Aug 06 08:03:57 PM PDT 24
Peak memory 207344 kb
Host smart-3397ce2b-b6cc-4d99-9d3d-35bc1a004ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48308
2173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.483082173
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2860803332
Short name T1171
Test name
Test status
Simulation time 180694327 ps
CPU time 0.91 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207400 kb
Host smart-bc6d6f80-8773-4e55-baad-d8e0de02f95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28608
03332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2860803332
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3321612973
Short name T653
Test name
Test status
Simulation time 191353364 ps
CPU time 0.9 seconds
Started Aug 06 08:03:59 PM PDT 24
Finished Aug 06 08:04:00 PM PDT 24
Peak memory 207408 kb
Host smart-9c1cc2e9-5960-4237-9b69-606de860b37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33216
12973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3321612973
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.747519006
Short name T18
Test name
Test status
Simulation time 162389004 ps
CPU time 0.89 seconds
Started Aug 06 08:03:58 PM PDT 24
Finished Aug 06 08:03:59 PM PDT 24
Peak memory 207424 kb
Host smart-d9ef9bc5-c711-4089-892c-5969745cbb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74751
9006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.747519006
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.284430626
Short name T3097
Test name
Test status
Simulation time 191753131 ps
CPU time 0.94 seconds
Started Aug 06 08:03:59 PM PDT 24
Finished Aug 06 08:04:00 PM PDT 24
Peak memory 207404 kb
Host smart-a25d6ef6-e524-4ec7-b9cc-5d51f42a2659
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=284430626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.284430626
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3218993042
Short name T220
Test name
Test status
Simulation time 163528685 ps
CPU time 0.93 seconds
Started Aug 06 08:04:03 PM PDT 24
Finished Aug 06 08:04:04 PM PDT 24
Peak memory 207292 kb
Host smart-5cbf3305-e21b-4467-8312-b305b81c04fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32189
93042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3218993042
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1856225562
Short name T3049
Test name
Test status
Simulation time 38419193 ps
CPU time 0.7 seconds
Started Aug 06 08:03:56 PM PDT 24
Finished Aug 06 08:03:57 PM PDT 24
Peak memory 207304 kb
Host smart-68f2582f-d2f8-47ec-9517-9bd624cba365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18562
25562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1856225562
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3200040215
Short name T2994
Test name
Test status
Simulation time 7118275610 ps
CPU time 18.58 seconds
Started Aug 06 08:03:56 PM PDT 24
Finished Aug 06 08:04:14 PM PDT 24
Peak memory 224096 kb
Host smart-95feabef-68a2-427f-936c-1db5f9d38c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32000
40215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3200040215
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2050050330
Short name T2287
Test name
Test status
Simulation time 162424942 ps
CPU time 0.92 seconds
Started Aug 06 08:04:02 PM PDT 24
Finished Aug 06 08:04:03 PM PDT 24
Peak memory 207340 kb
Host smart-5a56c5ce-760c-4881-bc51-886fe13b841b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20500
50330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2050050330
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.299914910
Short name T1074
Test name
Test status
Simulation time 219023864 ps
CPU time 0.97 seconds
Started Aug 06 08:04:02 PM PDT 24
Finished Aug 06 08:04:03 PM PDT 24
Peak memory 207312 kb
Host smart-c7f67680-314b-40d1-900c-5dce10a1ec46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29991
4910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.299914910
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.4270315940
Short name T2070
Test name
Test status
Simulation time 237998556 ps
CPU time 0.96 seconds
Started Aug 06 08:04:00 PM PDT 24
Finished Aug 06 08:04:01 PM PDT 24
Peak memory 207356 kb
Host smart-26f7c545-390a-4665-805f-b665e891eee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42703
15940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.4270315940
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.1284615254
Short name T863
Test name
Test status
Simulation time 201799727 ps
CPU time 0.93 seconds
Started Aug 06 08:04:02 PM PDT 24
Finished Aug 06 08:04:03 PM PDT 24
Peak memory 207344 kb
Host smart-31c97412-2bcb-48f4-ae44-f86df0e722a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12846
15254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.1284615254
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_resume_link_active.3190976070
Short name T2167
Test name
Test status
Simulation time 20171114392 ps
CPU time 28.7 seconds
Started Aug 06 08:04:00 PM PDT 24
Finished Aug 06 08:04:28 PM PDT 24
Peak memory 207376 kb
Host smart-c95a4738-828d-455b-b8cb-d8c2bbe80eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31909
76070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.3190976070
Directory /workspace/13.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.1243202086
Short name T2939
Test name
Test status
Simulation time 141300937 ps
CPU time 0.82 seconds
Started Aug 06 08:03:57 PM PDT 24
Finished Aug 06 08:03:58 PM PDT 24
Peak memory 207364 kb
Host smart-a52c245f-5c7a-40a0-b9ca-64acb394b69f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12432
02086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1243202086
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_rx_full.1423310782
Short name T2099
Test name
Test status
Simulation time 242363473 ps
CPU time 1.02 seconds
Started Aug 06 08:03:59 PM PDT 24
Finished Aug 06 08:04:01 PM PDT 24
Peak memory 207348 kb
Host smart-d6bdd9e8-38a2-4eec-bc4a-a52452b23302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14233
10782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.1423310782
Directory /workspace/13.usbdev_rx_full/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.4228040358
Short name T1369
Test name
Test status
Simulation time 161115463 ps
CPU time 0.85 seconds
Started Aug 06 08:04:00 PM PDT 24
Finished Aug 06 08:04:01 PM PDT 24
Peak memory 207320 kb
Host smart-feef7fa8-9e7b-4b6c-b8f5-37cb4bb313ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42280
40358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.4228040358
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.939610521
Short name T575
Test name
Test status
Simulation time 166038918 ps
CPU time 0.83 seconds
Started Aug 06 08:04:00 PM PDT 24
Finished Aug 06 08:04:00 PM PDT 24
Peak memory 207356 kb
Host smart-f65c4167-4ea0-4eac-94de-b97bd5bfff64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93961
0521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.939610521
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1952780262
Short name T2731
Test name
Test status
Simulation time 220974583 ps
CPU time 0.96 seconds
Started Aug 06 08:03:59 PM PDT 24
Finished Aug 06 08:04:00 PM PDT 24
Peak memory 207292 kb
Host smart-0edca385-3361-44c1-849c-f9729a142ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19527
80262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1952780262
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.993303169
Short name T845
Test name
Test status
Simulation time 1821920361 ps
CPU time 16.52 seconds
Started Aug 06 08:04:00 PM PDT 24
Finished Aug 06 08:04:17 PM PDT 24
Peak memory 217360 kb
Host smart-da36ca15-c6aa-45f4-9b76-a9940dcb216c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=993303169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.993303169
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1892192229
Short name T973
Test name
Test status
Simulation time 182782733 ps
CPU time 0.88 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207300 kb
Host smart-973e1621-61d6-450f-9b38-374c4ce0b835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18921
92229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1892192229
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2845798710
Short name T1524
Test name
Test status
Simulation time 170429773 ps
CPU time 0.9 seconds
Started Aug 06 08:03:57 PM PDT 24
Finished Aug 06 08:03:58 PM PDT 24
Peak memory 207396 kb
Host smart-e6ebb226-cc42-41d9-8956-79fdad6712d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28457
98710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2845798710
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1603750039
Short name T1669
Test name
Test status
Simulation time 768706684 ps
CPU time 2.11 seconds
Started Aug 06 08:03:58 PM PDT 24
Finished Aug 06 08:04:01 PM PDT 24
Peak memory 207308 kb
Host smart-29d421eb-fd22-4596-8b13-ea6b73564213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16037
50039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1603750039
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2284533950
Short name T678
Test name
Test status
Simulation time 1732225628 ps
CPU time 13.27 seconds
Started Aug 06 08:03:56 PM PDT 24
Finished Aug 06 08:04:10 PM PDT 24
Peak memory 223940 kb
Host smart-cec7cb80-0ceb-461b-88d6-58f86023277c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22845
33950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2284533950
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.390178349
Short name T1058
Test name
Test status
Simulation time 1312550767 ps
CPU time 30.17 seconds
Started Aug 06 08:03:52 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 207584 kb
Host smart-8f21b347-8ecc-47a6-b8ef-1dbd0176ee4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390178349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_host
_handshake.390178349
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/131.usbdev_endpoint_types.586743129
Short name T1956
Test name
Test status
Simulation time 301789442 ps
CPU time 1.13 seconds
Started Aug 06 08:09:07 PM PDT 24
Finished Aug 06 08:09:08 PM PDT 24
Peak memory 207336 kb
Host smart-4a75b969-dac5-4c2e-b324-b4fc42994004
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=586743129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.586743129
Directory /workspace/131.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/132.usbdev_endpoint_types.2361025075
Short name T2616
Test name
Test status
Simulation time 335149850 ps
CPU time 1.11 seconds
Started Aug 06 08:09:07 PM PDT 24
Finished Aug 06 08:09:08 PM PDT 24
Peak memory 207336 kb
Host smart-362c0ff0-dc25-4653-9a23-50317226a748
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2361025075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.2361025075
Directory /workspace/132.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/133.usbdev_endpoint_types.2348323939
Short name T137
Test name
Test status
Simulation time 296546252 ps
CPU time 1.13 seconds
Started Aug 06 08:09:08 PM PDT 24
Finished Aug 06 08:09:09 PM PDT 24
Peak memory 207324 kb
Host smart-af425d19-eeca-4252-87c1-a663a33ca7b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2348323939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.2348323939
Directory /workspace/133.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/134.usbdev_endpoint_types.550428209
Short name T426
Test name
Test status
Simulation time 632253724 ps
CPU time 1.7 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207316 kb
Host smart-ecb8e304-bcf4-49d2-8691-7bf8c69eb890
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=550428209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.550428209
Directory /workspace/134.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/137.usbdev_endpoint_types.2464514965
Short name T400
Test name
Test status
Simulation time 589951836 ps
CPU time 1.68 seconds
Started Aug 06 08:09:09 PM PDT 24
Finished Aug 06 08:09:11 PM PDT 24
Peak memory 207320 kb
Host smart-5f950bae-43e8-4cc7-95fc-431d86dcc507
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2464514965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.2464514965
Directory /workspace/137.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/138.usbdev_endpoint_types.758749601
Short name T411
Test name
Test status
Simulation time 589952067 ps
CPU time 1.51 seconds
Started Aug 06 08:09:12 PM PDT 24
Finished Aug 06 08:09:14 PM PDT 24
Peak memory 207360 kb
Host smart-16e8c103-0356-4e70-90af-0540a44c0f5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=758749601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.758749601
Directory /workspace/138.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/139.usbdev_endpoint_types.191288300
Short name T428
Test name
Test status
Simulation time 424552094 ps
CPU time 1.31 seconds
Started Aug 06 08:09:09 PM PDT 24
Finished Aug 06 08:09:10 PM PDT 24
Peak memory 207348 kb
Host smart-f3576984-48fd-4e9f-b26f-5b1886323062
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=191288300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.191288300
Directory /workspace/139.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2977949524
Short name T2600
Test name
Test status
Simulation time 53389405 ps
CPU time 0.71 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 207440 kb
Host smart-d288652f-2201-46bc-8b11-c910c3473928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2977949524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2977949524
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.725745451
Short name T645
Test name
Test status
Simulation time 10202934788 ps
CPU time 13.5 seconds
Started Aug 06 08:03:54 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207620 kb
Host smart-b583d2cd-b5ff-4231-83f8-80c6c7851320
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725745451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_ao
n_wake_disconnect.725745451
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.53558243
Short name T1589
Test name
Test status
Simulation time 20599973493 ps
CPU time 26.23 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:04:21 PM PDT 24
Peak memory 207604 kb
Host smart-d165137a-8a58-479d-9c32-b4c20a67eeb2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=53558243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.53558243
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.237218400
Short name T1159
Test name
Test status
Simulation time 26472350372 ps
CPU time 36.08 seconds
Started Aug 06 08:03:52 PM PDT 24
Finished Aug 06 08:04:28 PM PDT 24
Peak memory 215824 kb
Host smart-188b5c6b-c818-44f3-9bd4-f51564216e7e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237218400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_ao
n_wake_resume.237218400
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2486776516
Short name T1955
Test name
Test status
Simulation time 260065122 ps
CPU time 0.98 seconds
Started Aug 06 08:03:51 PM PDT 24
Finished Aug 06 08:03:52 PM PDT 24
Peak memory 207356 kb
Host smart-dccabee2-9a98-4818-8e4c-cea026f90b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24867
76516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2486776516
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.4127663702
Short name T827
Test name
Test status
Simulation time 145341818 ps
CPU time 0.82 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207264 kb
Host smart-63331d00-20f0-4da9-961a-0543ee37dfdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41276
63702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.4127663702
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.1391299429
Short name T1891
Test name
Test status
Simulation time 164751098 ps
CPU time 0.88 seconds
Started Aug 06 08:03:53 PM PDT 24
Finished Aug 06 08:03:54 PM PDT 24
Peak memory 207340 kb
Host smart-2e441b3a-233b-446a-815a-c7fe8026738c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13912
99429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.1391299429
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1063341660
Short name T275
Test name
Test status
Simulation time 1416518126 ps
CPU time 3.37 seconds
Started Aug 06 08:03:51 PM PDT 24
Finished Aug 06 08:03:55 PM PDT 24
Peak memory 207644 kb
Host smart-09508df7-b6f0-4c23-bc05-6136cee509e3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1063341660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1063341660
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.1743470391
Short name T2097
Test name
Test status
Simulation time 61394073610 ps
CPU time 103.09 seconds
Started Aug 06 08:03:56 PM PDT 24
Finished Aug 06 08:05:39 PM PDT 24
Peak memory 207628 kb
Host smart-8b253a16-3917-4378-a622-d911a34f4530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17434
70391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.1743470391
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.143024115
Short name T2291
Test name
Test status
Simulation time 3179933279 ps
CPU time 22.42 seconds
Started Aug 06 08:03:53 PM PDT 24
Finished Aug 06 08:04:15 PM PDT 24
Peak memory 207696 kb
Host smart-8a6076ec-7955-4c4e-a6b1-6424f235725f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143024115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.143024115
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.134596903
Short name T344
Test name
Test status
Simulation time 1097743344 ps
CPU time 2.32 seconds
Started Aug 06 08:03:53 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207380 kb
Host smart-73d12e5b-bd1e-4d31-b8cd-7f2095253741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13459
6903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.134596903
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.583217227
Short name T3016
Test name
Test status
Simulation time 150205146 ps
CPU time 0.8 seconds
Started Aug 06 08:03:56 PM PDT 24
Finished Aug 06 08:03:57 PM PDT 24
Peak memory 207348 kb
Host smart-3dabbff6-00b6-4ecf-95ff-8672256f8086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58321
7227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.583217227
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1837182867
Short name T1461
Test name
Test status
Simulation time 31448461 ps
CPU time 0.7 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207344 kb
Host smart-4d3dc4cb-f23b-459c-8692-2e227f5585f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18371
82867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1837182867
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1862442888
Short name T1719
Test name
Test status
Simulation time 934570759 ps
CPU time 2.49 seconds
Started Aug 06 08:03:54 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207672 kb
Host smart-00e3b323-6eb8-46c4-98f8-c577962e9991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18624
42888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1862442888
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_types.3024921329
Short name T1658
Test name
Test status
Simulation time 161853262 ps
CPU time 0.87 seconds
Started Aug 06 08:04:01 PM PDT 24
Finished Aug 06 08:04:02 PM PDT 24
Peak memory 207376 kb
Host smart-e6c15f79-97b5-4ae4-ba13-787c802fb220
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3024921329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.3024921329
Directory /workspace/14.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3434507771
Short name T1621
Test name
Test status
Simulation time 331108508 ps
CPU time 2.27 seconds
Started Aug 06 08:03:59 PM PDT 24
Finished Aug 06 08:04:02 PM PDT 24
Peak memory 207544 kb
Host smart-7355effa-6c45-4ce6-8050-1ec184df74e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34345
07771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3434507771
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3596210883
Short name T2410
Test name
Test status
Simulation time 163861831 ps
CPU time 0.95 seconds
Started Aug 06 08:04:00 PM PDT 24
Finished Aug 06 08:04:01 PM PDT 24
Peak memory 207552 kb
Host smart-607892ed-2ebe-4290-b559-2aea4e8c2fb7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3596210883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3596210883
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.372548024
Short name T1771
Test name
Test status
Simulation time 153910856 ps
CPU time 0.8 seconds
Started Aug 06 08:03:59 PM PDT 24
Finished Aug 06 08:04:00 PM PDT 24
Peak memory 207292 kb
Host smart-99dcf9be-55fa-417c-9783-c8de2080972a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37254
8024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.372548024
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1177261852
Short name T1337
Test name
Test status
Simulation time 199321940 ps
CPU time 0.96 seconds
Started Aug 06 08:03:58 PM PDT 24
Finished Aug 06 08:03:59 PM PDT 24
Peak memory 207596 kb
Host smart-091207a5-0c9e-47a7-9d65-e552be94968a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11772
61852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1177261852
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.3549514662
Short name T578
Test name
Test status
Simulation time 4115849925 ps
CPU time 39.83 seconds
Started Aug 06 08:03:53 PM PDT 24
Finished Aug 06 08:04:33 PM PDT 24
Peak memory 224052 kb
Host smart-d61af14d-c5d6-417c-be70-7327a20aa742
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3549514662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.3549514662
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.1373813499
Short name T2293
Test name
Test status
Simulation time 6705544907 ps
CPU time 43.08 seconds
Started Aug 06 08:03:57 PM PDT 24
Finished Aug 06 08:04:41 PM PDT 24
Peak memory 207864 kb
Host smart-398dac1d-aa0f-496a-930f-05f7787d879e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1373813499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.1373813499
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3333600769
Short name T1471
Test name
Test status
Simulation time 173911788 ps
CPU time 0.9 seconds
Started Aug 06 08:03:55 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207344 kb
Host smart-dd8f8d06-d81f-48f8-afda-da63bb44f65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33336
00769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3333600769
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.98374781
Short name T2005
Test name
Test status
Simulation time 25723572371 ps
CPU time 40.85 seconds
Started Aug 06 08:03:53 PM PDT 24
Finished Aug 06 08:04:34 PM PDT 24
Peak memory 207616 kb
Host smart-dc3b760f-089a-4132-a730-a76526b7a949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98374
781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.98374781
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3465983959
Short name T2007
Test name
Test status
Simulation time 6284922137 ps
CPU time 9.55 seconds
Started Aug 06 08:03:59 PM PDT 24
Finished Aug 06 08:04:08 PM PDT 24
Peak memory 216672 kb
Host smart-7d7b2cc8-b434-4e23-839f-cbec985e31e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34659
83959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3465983959
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.3867146223
Short name T2400
Test name
Test status
Simulation time 5543210259 ps
CPU time 161.8 seconds
Started Aug 06 08:04:00 PM PDT 24
Finished Aug 06 08:06:41 PM PDT 24
Peak memory 218288 kb
Host smart-297dd238-d8b1-4513-a84c-56f9bfd07dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38671
46223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3867146223
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3369276393
Short name T2822
Test name
Test status
Simulation time 1740275020 ps
CPU time 17.81 seconds
Started Aug 06 08:04:07 PM PDT 24
Finished Aug 06 08:04:25 PM PDT 24
Peak memory 223928 kb
Host smart-fa5c42a6-5bd0-4518-b672-548891c83b4b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3369276393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3369276393
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.3124567555
Short name T626
Test name
Test status
Simulation time 257085468 ps
CPU time 1.15 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:10 PM PDT 24
Peak memory 207324 kb
Host smart-6bf84782-0b22-496d-8439-ebbc2752916d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3124567555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3124567555
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.4170281640
Short name T2815
Test name
Test status
Simulation time 194303041 ps
CPU time 0.96 seconds
Started Aug 06 08:04:05 PM PDT 24
Finished Aug 06 08:04:06 PM PDT 24
Peak memory 207288 kb
Host smart-ba3cf3fd-f5f3-4cb1-b7a0-b6f4c7de1209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41702
81640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.4170281640
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.476246463
Short name T2766
Test name
Test status
Simulation time 1703494660 ps
CPU time 16.18 seconds
Started Aug 06 08:04:11 PM PDT 24
Finished Aug 06 08:04:27 PM PDT 24
Peak memory 216396 kb
Host smart-9a3a5bd1-4a10-4dbc-94ae-804406f4525f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47624
6463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.476246463
Directory /workspace/14.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1361673926
Short name T1997
Test name
Test status
Simulation time 3290911745 ps
CPU time 36.56 seconds
Started Aug 06 08:04:03 PM PDT 24
Finished Aug 06 08:04:40 PM PDT 24
Peak memory 218216 kb
Host smart-94f918a9-68e0-43f3-a87d-f3fddd5d9130
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1361673926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1361673926
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.1460551778
Short name T570
Test name
Test status
Simulation time 3910566754 ps
CPU time 31.45 seconds
Started Aug 06 08:04:04 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 215824 kb
Host smart-bbe01e0c-7987-4edf-a3b2-c94f29639408
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1460551778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.1460551778
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3500894571
Short name T609
Test name
Test status
Simulation time 202856403 ps
CPU time 0.93 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 207372 kb
Host smart-f6675808-9365-4623-b327-4ac5165450e5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3500894571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3500894571
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.211316412
Short name T532
Test name
Test status
Simulation time 164595227 ps
CPU time 0.83 seconds
Started Aug 06 08:04:04 PM PDT 24
Finished Aug 06 08:04:05 PM PDT 24
Peak memory 207224 kb
Host smart-829b4fb8-8ebe-491c-967f-f7e661e40071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21131
6412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.211316412
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2267088086
Short name T611
Test name
Test status
Simulation time 176632323 ps
CPU time 0.94 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 207328 kb
Host smart-5178f208-357b-421f-8c3f-4bf7ff89b915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22670
88086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2267088086
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.4244527246
Short name T17
Test name
Test status
Simulation time 209212830 ps
CPU time 0.91 seconds
Started Aug 06 08:04:07 PM PDT 24
Finished Aug 06 08:04:08 PM PDT 24
Peak memory 207396 kb
Host smart-d8853a93-2aac-475d-bab1-7f19d0c92d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42445
27246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.4244527246
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.961377804
Short name T131
Test name
Test status
Simulation time 172897521 ps
CPU time 0.87 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 207252 kb
Host smart-570b639e-eb4a-458c-9cad-79c573f15a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96137
7804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.961377804
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.597597178
Short name T207
Test name
Test status
Simulation time 146023436 ps
CPU time 0.83 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207336 kb
Host smart-3da08fd3-c6ff-44ad-a7b4-c29562d459e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59759
7178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.597597178
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.354291470
Short name T2205
Test name
Test status
Simulation time 238689304 ps
CPU time 1.03 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207348 kb
Host smart-af8501b0-1fdc-4539-a242-ec363a8cb970
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=354291470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.354291470
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2226770605
Short name T2327
Test name
Test status
Simulation time 167869633 ps
CPU time 0.85 seconds
Started Aug 06 08:04:11 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207316 kb
Host smart-6322f779-279a-4938-9703-cf17643366ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22267
70605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2226770605
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1190651349
Short name T2377
Test name
Test status
Simulation time 43005918 ps
CPU time 0.73 seconds
Started Aug 06 08:04:07 PM PDT 24
Finished Aug 06 08:04:08 PM PDT 24
Peak memory 207320 kb
Host smart-015b6dbc-5924-4d17-a6c2-0ca6ff6d2e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11906
51349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1190651349
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.182746726
Short name T1255
Test name
Test status
Simulation time 9050526179 ps
CPU time 22.36 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:30 PM PDT 24
Peak memory 215964 kb
Host smart-dd89db94-6a4b-4c5e-b73d-7a83d0a0cbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18274
6726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.182746726
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.107624718
Short name T621
Test name
Test status
Simulation time 212712583 ps
CPU time 0.92 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:10 PM PDT 24
Peak memory 207248 kb
Host smart-432d85d2-7430-478d-8cbd-14a0eaf556b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10762
4718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.107624718
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.1561866201
Short name T2463
Test name
Test status
Simulation time 237720282 ps
CPU time 1.1 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:10 PM PDT 24
Peak memory 207412 kb
Host smart-d21eef4d-ee7e-4688-b426-bca58517c012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15618
66201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.1561866201
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2045488484
Short name T689
Test name
Test status
Simulation time 169774254 ps
CPU time 1 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207400 kb
Host smart-9e8aa992-98eb-41c5-9ced-c330920ebd5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20454
88484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2045488484
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_resume_link_active.3913172604
Short name T2432
Test name
Test status
Simulation time 20171309126 ps
CPU time 22.26 seconds
Started Aug 06 08:04:07 PM PDT 24
Finished Aug 06 08:04:29 PM PDT 24
Peak memory 207460 kb
Host smart-48179429-7751-434f-88fc-9768b695a917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39131
72604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.3913172604
Directory /workspace/14.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.1730855198
Short name T652
Test name
Test status
Simulation time 162330487 ps
CPU time 0.82 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 207352 kb
Host smart-f41752d6-0293-4adb-b493-7faa92b804ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17308
55198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1730855198
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_rx_full.3102110550
Short name T3117
Test name
Test status
Simulation time 403343241 ps
CPU time 1.4 seconds
Started Aug 06 08:04:10 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207320 kb
Host smart-556f5dd5-eb14-4789-ac0d-3802563dc3cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31021
10550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.3102110550
Directory /workspace/14.usbdev_rx_full/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1041124394
Short name T2615
Test name
Test status
Simulation time 155013105 ps
CPU time 0.85 seconds
Started Aug 06 08:04:05 PM PDT 24
Finished Aug 06 08:04:06 PM PDT 24
Peak memory 207288 kb
Host smart-7e5e64ab-419d-4658-a080-ea17493e387b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10411
24394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1041124394
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1761793280
Short name T2639
Test name
Test status
Simulation time 170313755 ps
CPU time 0.91 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207380 kb
Host smart-1f8799e9-196e-40b1-89b0-543c3d78c0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17617
93280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1761793280
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1769751159
Short name T2222
Test name
Test status
Simulation time 216465965 ps
CPU time 0.96 seconds
Started Aug 06 08:04:04 PM PDT 24
Finished Aug 06 08:04:05 PM PDT 24
Peak memory 207352 kb
Host smart-9a0a3cd5-c584-4851-b236-2665991eddca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17697
51159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1769751159
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.3859717596
Short name T2464
Test name
Test status
Simulation time 2698302451 ps
CPU time 74.29 seconds
Started Aug 06 08:04:07 PM PDT 24
Finished Aug 06 08:05:22 PM PDT 24
Peak memory 224036 kb
Host smart-f0e4cabc-db6b-4813-947b-24deae60d686
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3859717596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.3859717596
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.165586089
Short name T470
Test name
Test status
Simulation time 187886988 ps
CPU time 0.89 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207372 kb
Host smart-f605abb1-fb80-4001-8010-324954eb5b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16558
6089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.165586089
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1130329246
Short name T1652
Test name
Test status
Simulation time 189101487 ps
CPU time 0.91 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207396 kb
Host smart-70759e5f-d4cf-4528-9f97-c704eb5b33cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11303
29246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1130329246
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2339399588
Short name T2471
Test name
Test status
Simulation time 661197465 ps
CPU time 1.88 seconds
Started Aug 06 08:04:07 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 207260 kb
Host smart-af97efae-eb39-4567-abaa-ac61bf082165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23393
99588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2339399588
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1611945103
Short name T3122
Test name
Test status
Simulation time 3349720245 ps
CPU time 95.69 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:05:44 PM PDT 24
Peak memory 217440 kb
Host smart-a2f0776f-c34b-4ca2-ac6e-7bed15f2ed50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16119
45103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1611945103
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.900481529
Short name T2959
Test name
Test status
Simulation time 832801170 ps
CPU time 5.28 seconds
Started Aug 06 08:03:52 PM PDT 24
Finished Aug 06 08:03:58 PM PDT 24
Peak memory 207580 kb
Host smart-7b26bef7-558a-44fc-9afa-7bb0a6e01d95
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900481529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_host
_handshake.900481529
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/140.usbdev_endpoint_types.1892992593
Short name T403
Test name
Test status
Simulation time 470136622 ps
CPU time 1.32 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207208 kb
Host smart-e86d19f1-633d-4af5-9e93-4e48a70d3410
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1892992593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.1892992593
Directory /workspace/140.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/141.usbdev_endpoint_types.3500660451
Short name T413
Test name
Test status
Simulation time 234865637 ps
CPU time 0.93 seconds
Started Aug 06 08:09:10 PM PDT 24
Finished Aug 06 08:09:11 PM PDT 24
Peak memory 207376 kb
Host smart-7df649b7-3786-4537-9f77-8d74dd41d246
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3500660451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.3500660451
Directory /workspace/141.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/142.usbdev_endpoint_types.168899922
Short name T2686
Test name
Test status
Simulation time 509279058 ps
CPU time 1.49 seconds
Started Aug 06 08:09:15 PM PDT 24
Finished Aug 06 08:09:17 PM PDT 24
Peak memory 207264 kb
Host smart-e6d62803-3418-42eb-b850-91e6520318c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=168899922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.168899922
Directory /workspace/142.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/143.usbdev_endpoint_types.2001150736
Short name T379
Test name
Test status
Simulation time 786717873 ps
CPU time 1.66 seconds
Started Aug 06 08:09:14 PM PDT 24
Finished Aug 06 08:09:15 PM PDT 24
Peak memory 207292 kb
Host smart-5f9d0c7f-db0a-44aa-8c36-12473a1578d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2001150736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.2001150736
Directory /workspace/143.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/144.usbdev_endpoint_types.954304631
Short name T2870
Test name
Test status
Simulation time 454468840 ps
CPU time 1.27 seconds
Started Aug 06 08:09:06 PM PDT 24
Finished Aug 06 08:09:07 PM PDT 24
Peak memory 207344 kb
Host smart-504fb4db-6830-4485-9db5-ea2b23f49b75
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=954304631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.954304631
Directory /workspace/144.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/145.usbdev_endpoint_types.72666855
Short name T3102
Test name
Test status
Simulation time 148571956 ps
CPU time 0.88 seconds
Started Aug 06 08:09:15 PM PDT 24
Finished Aug 06 08:09:16 PM PDT 24
Peak memory 207388 kb
Host smart-321323e5-4b86-45d3-a1cf-c1501c1867f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=72666855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.72666855
Directory /workspace/145.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/146.usbdev_endpoint_types.3697350487
Short name T3084
Test name
Test status
Simulation time 183880760 ps
CPU time 0.94 seconds
Started Aug 06 08:09:34 PM PDT 24
Finished Aug 06 08:09:35 PM PDT 24
Peak memory 207380 kb
Host smart-6992c70f-3b63-40a7-a731-21f2d8a469c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3697350487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.3697350487
Directory /workspace/146.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/147.usbdev_endpoint_types.223615711
Short name T414
Test name
Test status
Simulation time 366587419 ps
CPU time 1.21 seconds
Started Aug 06 08:09:22 PM PDT 24
Finished Aug 06 08:09:23 PM PDT 24
Peak memory 207372 kb
Host smart-b308731d-5238-4eed-8445-bee78ad5d4bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=223615711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.223615711
Directory /workspace/147.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/148.usbdev_endpoint_types.43429744
Short name T410
Test name
Test status
Simulation time 895023286 ps
CPU time 2.17 seconds
Started Aug 06 08:09:23 PM PDT 24
Finished Aug 06 08:09:26 PM PDT 24
Peak memory 207324 kb
Host smart-4e353643-4c5c-456e-9ddd-eac3397d6759
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=43429744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.43429744
Directory /workspace/148.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/149.usbdev_endpoint_types.3585915686
Short name T389
Test name
Test status
Simulation time 457207505 ps
CPU time 1.38 seconds
Started Aug 06 08:09:37 PM PDT 24
Finished Aug 06 08:09:38 PM PDT 24
Peak memory 207240 kb
Host smart-103a441f-f2e5-4b0c-ae00-ae8584fc3344
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3585915686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.3585915686
Directory /workspace/149.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.498108373
Short name T1281
Test name
Test status
Simulation time 60309765 ps
CPU time 0.75 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207444 kb
Host smart-8f4357ee-3c29-4b93-aa91-abfe8f0656e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=498108373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.498108373
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1359896385
Short name T1127
Test name
Test status
Simulation time 10647977127 ps
CPU time 13.06 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 207596 kb
Host smart-f670fdaf-aec3-4446-85ed-d507636f1394
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359896385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.1359896385
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.1731838692
Short name T2978
Test name
Test status
Simulation time 21365966868 ps
CPU time 30.4 seconds
Started Aug 06 08:04:05 PM PDT 24
Finished Aug 06 08:04:36 PM PDT 24
Peak memory 207656 kb
Host smart-193bc8ff-a124-4264-a96c-3a062ffb1ff1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731838692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.1731838692
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2593794182
Short name T2349
Test name
Test status
Simulation time 29840328534 ps
CPU time 36.47 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:43 PM PDT 24
Peak memory 207680 kb
Host smart-aa93bbd5-168c-4254-82e1-7794492f42cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593794182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.2593794182
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3893253275
Short name T1014
Test name
Test status
Simulation time 148191883 ps
CPU time 0.85 seconds
Started Aug 06 08:04:05 PM PDT 24
Finished Aug 06 08:04:06 PM PDT 24
Peak memory 207344 kb
Host smart-67248125-86d8-4c7e-8f9c-8d7334adb0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38932
53275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3893253275
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3239696369
Short name T1149
Test name
Test status
Simulation time 141686557 ps
CPU time 0.81 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 207348 kb
Host smart-4aebde92-1ba5-48f8-8134-404073778f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396
96369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3239696369
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.2209926016
Short name T1588
Test name
Test status
Simulation time 364355069 ps
CPU time 1.37 seconds
Started Aug 06 08:04:04 PM PDT 24
Finished Aug 06 08:04:06 PM PDT 24
Peak memory 207380 kb
Host smart-75492109-cc94-424c-aa00-51db54b59ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22099
26016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.2209926016
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.168190610
Short name T2391
Test name
Test status
Simulation time 1106483953 ps
CPU time 2.69 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207532 kb
Host smart-0680ff79-dd5b-4a9a-8877-2276ae72408b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=168190610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.168190610
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.967832971
Short name T2330
Test name
Test status
Simulation time 15905668709 ps
CPU time 25.5 seconds
Started Aug 06 08:04:10 PM PDT 24
Finished Aug 06 08:04:36 PM PDT 24
Peak memory 207584 kb
Host smart-268ebfff-08cf-41ef-bbd0-352d999f5cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96783
2971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.967832971
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.3475827363
Short name T890
Test name
Test status
Simulation time 1818257084 ps
CPU time 44.94 seconds
Started Aug 06 08:04:11 PM PDT 24
Finished Aug 06 08:04:56 PM PDT 24
Peak memory 207496 kb
Host smart-5b250adc-c32f-4400-a347-1ade9aba3721
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475827363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.3475827363
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3252703577
Short name T1422
Test name
Test status
Simulation time 949493251 ps
CPU time 2.08 seconds
Started Aug 06 08:04:07 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 207224 kb
Host smart-159ad062-dd67-43ef-95fd-9faff3305fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32527
03577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3252703577
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1887641032
Short name T1729
Test name
Test status
Simulation time 162067546 ps
CPU time 0.86 seconds
Started Aug 06 08:04:03 PM PDT 24
Finished Aug 06 08:04:04 PM PDT 24
Peak memory 207348 kb
Host smart-0d8b0da6-9919-475c-8a07-f14585b11d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18876
41032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1887641032
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.726152098
Short name T1033
Test name
Test status
Simulation time 32283562 ps
CPU time 0.68 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:06 PM PDT 24
Peak memory 207332 kb
Host smart-1a376363-13fa-44f7-bdcb-7329308bdee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72615
2098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.726152098
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.257506027
Short name T2075
Test name
Test status
Simulation time 813191673 ps
CPU time 2.49 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207604 kb
Host smart-933d1284-506e-451e-a634-efb350fe20cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25750
6027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.257506027
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_types.4245828199
Short name T2181
Test name
Test status
Simulation time 146899950 ps
CPU time 0.88 seconds
Started Aug 06 08:04:05 PM PDT 24
Finished Aug 06 08:04:06 PM PDT 24
Peak memory 207312 kb
Host smart-7b5f0c70-7a8a-44cb-a327-b3ccb7b7621a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4245828199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.4245828199
Directory /workspace/15.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2381337770
Short name T1527
Test name
Test status
Simulation time 179597700 ps
CPU time 2.1 seconds
Started Aug 06 08:04:10 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207532 kb
Host smart-192f128d-dcfc-44e6-835d-359e925fdadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23813
37770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2381337770
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2216183667
Short name T1078
Test name
Test status
Simulation time 243122668 ps
CPU time 1.14 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 215696 kb
Host smart-8de02fc0-5c6b-4c61-9c48-b56d504d7214
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2216183667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2216183667
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2615909636
Short name T2244
Test name
Test status
Simulation time 165551038 ps
CPU time 0.83 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207264 kb
Host smart-850e6919-e95f-4770-a75b-b29b6db1b45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26159
09636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2615909636
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1500227320
Short name T2565
Test name
Test status
Simulation time 185721288 ps
CPU time 0.96 seconds
Started Aug 06 08:04:11 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207372 kb
Host smart-76c344ef-b331-47fa-832c-e4b0ed528385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15002
27320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1500227320
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.3364965140
Short name T2709
Test name
Test status
Simulation time 4760341579 ps
CPU time 47.75 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:57 PM PDT 24
Peak memory 224076 kb
Host smart-2b44a437-1dec-46f3-99ea-f37a88126493
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3364965140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3364965140
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.4073430285
Short name T1691
Test name
Test status
Simulation time 10091704423 ps
CPU time 65.59 seconds
Started Aug 06 08:04:07 PM PDT 24
Finished Aug 06 08:05:13 PM PDT 24
Peak memory 207508 kb
Host smart-bfe5ec12-0ade-4cbd-9c63-f35df20b49a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4073430285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.4073430285
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3984430310
Short name T971
Test name
Test status
Simulation time 168570698 ps
CPU time 0.85 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:10 PM PDT 24
Peak memory 207232 kb
Host smart-b56c01f9-abe3-4a21-a4b9-e3322c1d221f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39844
30310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3984430310
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.2584553088
Short name T67
Test name
Test status
Simulation time 23580873965 ps
CPU time 36.73 seconds
Started Aug 06 08:04:07 PM PDT 24
Finished Aug 06 08:04:43 PM PDT 24
Peak memory 215908 kb
Host smart-7e8b8045-5c88-4d5c-ac67-6eb08a27a72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25845
53088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.2584553088
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2307332573
Short name T3111
Test name
Test status
Simulation time 5086535172 ps
CPU time 7.14 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:17 PM PDT 24
Peak memory 215872 kb
Host smart-0fe39bc7-7d31-45d9-990d-3c4ce06d1b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23073
32573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2307332573
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.1076377391
Short name T2695
Test name
Test status
Simulation time 2397909767 ps
CPU time 16.45 seconds
Started Aug 06 08:04:11 PM PDT 24
Finished Aug 06 08:04:28 PM PDT 24
Peak memory 217812 kb
Host smart-b377fbc3-6c20-4fc5-a921-b2f947678bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10763
77391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.1076377391
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3426347621
Short name T1432
Test name
Test status
Simulation time 1598820640 ps
CPU time 45.69 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 223800 kb
Host smart-33349c2b-6110-4947-8401-8038d96195f3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3426347621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3426347621
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.1313377365
Short name T1797
Test name
Test status
Simulation time 258186725 ps
CPU time 1.02 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 207324 kb
Host smart-71986f09-ecf6-4541-8608-3f43376dd364
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1313377365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1313377365
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.781418361
Short name T1708
Test name
Test status
Simulation time 197891228 ps
CPU time 0.97 seconds
Started Aug 06 08:04:11 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207380 kb
Host smart-08da880a-f7d6-46b2-bfa3-f8d18fc99945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78141
8361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.781418361
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.2572547085
Short name T713
Test name
Test status
Simulation time 2273826389 ps
CPU time 22.18 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:31 PM PDT 24
Peak memory 217464 kb
Host smart-5672ab6e-a2b6-4f28-b5b8-db2ca1f667aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25725
47085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.2572547085
Directory /workspace/15.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1947236414
Short name T1153
Test name
Test status
Simulation time 2341726866 ps
CPU time 23.14 seconds
Started Aug 06 08:04:13 PM PDT 24
Finished Aug 06 08:04:37 PM PDT 24
Peak memory 217488 kb
Host smart-4e074df3-3493-4bcb-9e25-3b4868387ea6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1947236414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1947236414
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1472290868
Short name T2036
Test name
Test status
Simulation time 154143580 ps
CPU time 0.81 seconds
Started Aug 06 08:04:12 PM PDT 24
Finished Aug 06 08:04:13 PM PDT 24
Peak memory 207360 kb
Host smart-f1d8fedb-8911-45c3-bd24-ae4daa50f473
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1472290868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1472290868
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.200348685
Short name T969
Test name
Test status
Simulation time 154809882 ps
CPU time 0.83 seconds
Started Aug 06 08:04:13 PM PDT 24
Finished Aug 06 08:04:14 PM PDT 24
Peak memory 207384 kb
Host smart-0b96b0a7-01ff-4a5b-a065-8ec2aa7f4df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20034
8685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.200348685
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1614471102
Short name T2711
Test name
Test status
Simulation time 182057122 ps
CPU time 0.95 seconds
Started Aug 06 08:04:11 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207352 kb
Host smart-a10b7ccf-62b7-427a-8f91-257735d0573f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16144
71102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1614471102
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.303127593
Short name T1986
Test name
Test status
Simulation time 204492868 ps
CPU time 1.02 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:10 PM PDT 24
Peak memory 207316 kb
Host smart-f1c467d6-6ff8-49f3-8f50-c5bd4534ff42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30312
7593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.303127593
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2480213853
Short name T2388
Test name
Test status
Simulation time 189228570 ps
CPU time 1 seconds
Started Aug 06 08:04:09 PM PDT 24
Finished Aug 06 08:04:10 PM PDT 24
Peak memory 207312 kb
Host smart-5f857960-c4f2-476a-b541-2e280ac659d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24802
13853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2480213853
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.827955730
Short name T185
Test name
Test status
Simulation time 173359423 ps
CPU time 0.88 seconds
Started Aug 06 08:04:10 PM PDT 24
Finished Aug 06 08:04:11 PM PDT 24
Peak memory 207320 kb
Host smart-c99e71f7-09be-416f-99ee-f9588db3d47e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82795
5730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.827955730
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.141601886
Short name T1082
Test name
Test status
Simulation time 238278241 ps
CPU time 1.07 seconds
Started Aug 06 08:04:13 PM PDT 24
Finished Aug 06 08:04:14 PM PDT 24
Peak memory 207360 kb
Host smart-dbfa3718-5970-4cff-a6e0-4df4e86ae71d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=141601886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.141601886
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1481710664
Short name T2534
Test name
Test status
Simulation time 174891280 ps
CPU time 0.86 seconds
Started Aug 06 08:04:11 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207348 kb
Host smart-c3eec678-eb2e-44ff-b192-016fce7aeb46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14817
10664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1481710664
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3401077359
Short name T2985
Test name
Test status
Simulation time 48569629 ps
CPU time 0.7 seconds
Started Aug 06 08:04:12 PM PDT 24
Finished Aug 06 08:04:13 PM PDT 24
Peak memory 207324 kb
Host smart-83de4346-3e3c-434c-b6ae-185302c455b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34010
77359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3401077359
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2964109014
Short name T2838
Test name
Test status
Simulation time 14626349783 ps
CPU time 33.5 seconds
Started Aug 06 08:04:13 PM PDT 24
Finished Aug 06 08:04:47 PM PDT 24
Peak memory 215920 kb
Host smart-76d49985-edb5-4fa2-bced-0d3fd56e57b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29641
09014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2964109014
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.965719861
Short name T2516
Test name
Test status
Simulation time 251623228 ps
CPU time 0.97 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207356 kb
Host smart-e0a57ecd-8eb8-4f10-82ae-656676ab6328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96571
9861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.965719861
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1815098421
Short name T2511
Test name
Test status
Simulation time 173252038 ps
CPU time 0.93 seconds
Started Aug 06 08:04:10 PM PDT 24
Finished Aug 06 08:04:11 PM PDT 24
Peak memory 207304 kb
Host smart-a3704cf3-cd84-4a92-9e4a-6a4e2dad9473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18150
98421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1815098421
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3961534425
Short name T654
Test name
Test status
Simulation time 159966058 ps
CPU time 0.87 seconds
Started Aug 06 08:04:07 PM PDT 24
Finished Aug 06 08:04:08 PM PDT 24
Peak memory 207380 kb
Host smart-cc5a9584-5bcb-4156-b22d-e7d459876486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39615
34425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3961534425
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2317584824
Short name T2328
Test name
Test status
Simulation time 186647694 ps
CPU time 0.95 seconds
Started Aug 06 08:04:06 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 207332 kb
Host smart-e02c20cc-ac0c-48f1-b0bd-2845d28d9a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23175
84824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2317584824
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_resume_link_active.1247055774
Short name T860
Test name
Test status
Simulation time 20195086621 ps
CPU time 25.71 seconds
Started Aug 06 08:04:10 PM PDT 24
Finished Aug 06 08:04:36 PM PDT 24
Peak memory 207452 kb
Host smart-1edd95c4-b5bd-4056-86d9-734a20f5e694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12470
55774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.1247055774
Directory /workspace/15.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.503739056
Short name T1575
Test name
Test status
Simulation time 146973612 ps
CPU time 0.84 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:08 PM PDT 24
Peak memory 207224 kb
Host smart-8bd0df05-9a71-4689-bad8-be9bf608a961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50373
9056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.503739056
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_rx_full.2343546345
Short name T908
Test name
Test status
Simulation time 347683179 ps
CPU time 1.27 seconds
Started Aug 06 08:04:10 PM PDT 24
Finished Aug 06 08:04:12 PM PDT 24
Peak memory 207320 kb
Host smart-9e4f7cd5-1507-497d-bcbc-f6c262f253b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23435
46345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.2343546345
Directory /workspace/15.usbdev_rx_full/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2956499066
Short name T676
Test name
Test status
Simulation time 172709150 ps
CPU time 0.83 seconds
Started Aug 06 08:04:07 PM PDT 24
Finished Aug 06 08:04:08 PM PDT 24
Peak memory 207256 kb
Host smart-cbeb7152-fe53-4952-b161-c2ae0671f70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29564
99066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2956499066
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.617518324
Short name T123
Test name
Test status
Simulation time 151606625 ps
CPU time 0.87 seconds
Started Aug 06 08:04:10 PM PDT 24
Finished Aug 06 08:04:11 PM PDT 24
Peak memory 207372 kb
Host smart-96fa7d18-7415-4f5d-91e2-446273ee06e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61751
8324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.617518324
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2580476685
Short name T1390
Test name
Test status
Simulation time 236926823 ps
CPU time 1.09 seconds
Started Aug 06 08:04:10 PM PDT 24
Finished Aug 06 08:04:11 PM PDT 24
Peak memory 207368 kb
Host smart-40f12511-f77c-44c3-82b8-3a950eb507dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25804
76685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2580476685
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.909793367
Short name T2708
Test name
Test status
Simulation time 3355541473 ps
CPU time 25.53 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 224044 kb
Host smart-35fe3c7c-fa61-46fd-bedc-b1f929dcc477
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=909793367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.909793367
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1311800821
Short name T2103
Test name
Test status
Simulation time 199627427 ps
CPU time 0.91 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:24 PM PDT 24
Peak memory 207316 kb
Host smart-9a4b2543-b173-4bce-af77-884849af686c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13118
00821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1311800821
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3571769072
Short name T511
Test name
Test status
Simulation time 160958223 ps
CPU time 0.85 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207328 kb
Host smart-012dfc92-5c50-4184-af79-d30f58bc5931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35717
69072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3571769072
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.2738559213
Short name T1428
Test name
Test status
Simulation time 256050575 ps
CPU time 1.02 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207364 kb
Host smart-f946270a-643c-4e70-b35e-b22859a0556f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27385
59213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2738559213
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.147002698
Short name T1203
Test name
Test status
Simulation time 4171694103 ps
CPU time 31.8 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:53 PM PDT 24
Peak memory 215936 kb
Host smart-08387e59-5b0e-4ddf-98f6-4a529586aadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14700
2698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.147002698
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.1969433409
Short name T2900
Test name
Test status
Simulation time 4310023925 ps
CPU time 36.99 seconds
Started Aug 06 08:04:08 PM PDT 24
Finished Aug 06 08:04:45 PM PDT 24
Peak memory 207704 kb
Host smart-7b02bb34-30e6-469c-a6cf-a185fa8f3d02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969433409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.1969433409
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/150.usbdev_endpoint_types.229072346
Short name T434
Test name
Test status
Simulation time 213375549 ps
CPU time 1.01 seconds
Started Aug 06 08:09:31 PM PDT 24
Finished Aug 06 08:09:33 PM PDT 24
Peak memory 207372 kb
Host smart-48b92453-a66e-43ba-946c-28db4d62f53c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=229072346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.229072346
Directory /workspace/150.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/152.usbdev_endpoint_types.3292234324
Short name T385
Test name
Test status
Simulation time 535155745 ps
CPU time 1.44 seconds
Started Aug 06 08:09:31 PM PDT 24
Finished Aug 06 08:09:32 PM PDT 24
Peak memory 207328 kb
Host smart-40a04a80-66f0-4e1d-a2c8-bc43ee52e8d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3292234324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.3292234324
Directory /workspace/152.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/153.usbdev_endpoint_types.1437087797
Short name T383
Test name
Test status
Simulation time 657992190 ps
CPU time 1.61 seconds
Started Aug 06 08:09:26 PM PDT 24
Finished Aug 06 08:09:28 PM PDT 24
Peak memory 207320 kb
Host smart-70478bc4-3a08-4b0d-b258-e25fbec6f68c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1437087797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.1437087797
Directory /workspace/153.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/154.usbdev_endpoint_types.2980719197
Short name T2950
Test name
Test status
Simulation time 161526796 ps
CPU time 0.88 seconds
Started Aug 06 08:09:38 PM PDT 24
Finished Aug 06 08:09:39 PM PDT 24
Peak memory 207268 kb
Host smart-3000d841-c5ce-44e5-9184-b9e1ae0454c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2980719197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.2980719197
Directory /workspace/154.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/155.usbdev_endpoint_types.2741745078
Short name T366
Test name
Test status
Simulation time 678075017 ps
CPU time 1.61 seconds
Started Aug 06 08:09:41 PM PDT 24
Finished Aug 06 08:09:42 PM PDT 24
Peak memory 207348 kb
Host smart-2e292b57-4e77-461a-bcda-adb024cb928a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2741745078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.2741745078
Directory /workspace/155.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/156.usbdev_endpoint_types.3086615415
Short name T422
Test name
Test status
Simulation time 668044403 ps
CPU time 1.7 seconds
Started Aug 06 08:09:27 PM PDT 24
Finished Aug 06 08:09:28 PM PDT 24
Peak memory 207316 kb
Host smart-de3524a5-550f-491b-be43-91c5111c8999
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3086615415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.3086615415
Directory /workspace/156.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/157.usbdev_endpoint_types.2500912183
Short name T2759
Test name
Test status
Simulation time 369471833 ps
CPU time 1.18 seconds
Started Aug 06 08:09:33 PM PDT 24
Finished Aug 06 08:09:34 PM PDT 24
Peak memory 207356 kb
Host smart-a4d3b996-043f-4d74-8d83-42cee7e491e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2500912183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.2500912183
Directory /workspace/157.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/158.usbdev_endpoint_types.2885140689
Short name T2902
Test name
Test status
Simulation time 280481279 ps
CPU time 1.1 seconds
Started Aug 06 08:09:45 PM PDT 24
Finished Aug 06 08:09:47 PM PDT 24
Peak memory 207276 kb
Host smart-5ede898b-b8ab-4b08-84c1-183853df2086
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2885140689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.2885140689
Directory /workspace/158.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/159.usbdev_endpoint_types.2025329113
Short name T392
Test name
Test status
Simulation time 486496786 ps
CPU time 1.55 seconds
Started Aug 06 08:09:24 PM PDT 24
Finished Aug 06 08:09:25 PM PDT 24
Peak memory 207392 kb
Host smart-b7befa9e-08d5-4f72-9fee-4b8e48da066e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2025329113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.2025329113
Directory /workspace/159.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.501462448
Short name T3044
Test name
Test status
Simulation time 37534719 ps
CPU time 0.68 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:24 PM PDT 24
Peak memory 207488 kb
Host smart-a13a2708-ed5b-4e70-bbeb-53c88ae9f830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=501462448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.501462448
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3744823519
Short name T1456
Test name
Test status
Simulation time 10808135274 ps
CPU time 14.43 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:37 PM PDT 24
Peak memory 207612 kb
Host smart-e7915a75-f91f-4a26-a6f4-4bb48c51ac38
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744823519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.3744823519
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.4068445446
Short name T1230
Test name
Test status
Simulation time 14243799703 ps
CPU time 16.38 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:37 PM PDT 24
Peak memory 215808 kb
Host smart-d2bdf57d-7fe6-48c3-9876-2f425a1bcdfc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068445446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.4068445446
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.441144678
Short name T1784
Test name
Test status
Simulation time 31329077208 ps
CPU time 34.46 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:56 PM PDT 24
Peak memory 207588 kb
Host smart-9a226a26-ee5b-438b-af61-8aebf2b3b9ca
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441144678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ao
n_wake_resume.441144678
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.862429204
Short name T1220
Test name
Test status
Simulation time 170808433 ps
CPU time 0.88 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:25 PM PDT 24
Peak memory 207316 kb
Host smart-861764e7-63b2-43f2-a5ae-ffebbf0b1b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86242
9204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.862429204
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.187930172
Short name T2828
Test name
Test status
Simulation time 177198260 ps
CPU time 0.88 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:25 PM PDT 24
Peak memory 207320 kb
Host smart-b0b6b78e-bf32-4ac0-9922-e8f15f41580d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18793
0172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.187930172
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1577404873
Short name T801
Test name
Test status
Simulation time 400417200 ps
CPU time 1.51 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207600 kb
Host smart-dae50aa7-aa87-4518-876f-f3d6995a5ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15774
04873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1577404873
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1218051025
Short name T1006
Test name
Test status
Simulation time 480148047 ps
CPU time 1.58 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207360 kb
Host smart-dcf205dd-cf95-4e7e-b8c9-8ce68d0102a6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1218051025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1218051025
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.4174026706
Short name T2156
Test name
Test status
Simulation time 44234381864 ps
CPU time 68.39 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:05:29 PM PDT 24
Peak memory 207540 kb
Host smart-50659c57-3e6f-44b2-8964-786c7e89dbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41740
26706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.4174026706
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.5718910
Short name T884
Test name
Test status
Simulation time 890210575 ps
CPU time 18.56 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:04:53 PM PDT 24
Peak memory 207584 kb
Host smart-ca93f79a-7e8b-4b96-8ef0-435678e26eda
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5718910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.5718910
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.1192057482
Short name T2404
Test name
Test status
Simulation time 1279448016 ps
CPU time 2.46 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207380 kb
Host smart-7bb6b1b5-739a-40ee-b586-20bf2f2229ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11920
57482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1192057482
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3974479347
Short name T2642
Test name
Test status
Simulation time 162597133 ps
CPU time 0.82 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:24 PM PDT 24
Peak memory 207332 kb
Host smart-83cf4c4c-bb6b-4095-9bea-07096d6025aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39744
79347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3974479347
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3299524625
Short name T1924
Test name
Test status
Simulation time 56643834 ps
CPU time 0.73 seconds
Started Aug 06 08:04:19 PM PDT 24
Finished Aug 06 08:04:20 PM PDT 24
Peak memory 207264 kb
Host smart-c48aab6a-b9a5-40fc-8719-8c973185e072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32995
24625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3299524625
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1369017230
Short name T173
Test name
Test status
Simulation time 871433017 ps
CPU time 2.32 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:26 PM PDT 24
Peak memory 207632 kb
Host smart-e8673e1a-3adb-4056-9583-2d0f76e25081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13690
17230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1369017230
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_types.494197948
Short name T2981
Test name
Test status
Simulation time 590261796 ps
CPU time 1.75 seconds
Started Aug 06 08:04:20 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 207372 kb
Host smart-47cbe3b9-d23b-45b2-b752-55c58f8e8d05
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=494197948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.494197948
Directory /workspace/16.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2803018868
Short name T2235
Test name
Test status
Simulation time 195106561 ps
CPU time 2.01 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:24 PM PDT 24
Peak memory 207596 kb
Host smart-da1906aa-b5b0-492a-91f2-a9a0d0d17129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28030
18868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2803018868
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3599929216
Short name T99
Test name
Test status
Simulation time 187198919 ps
CPU time 1.02 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207244 kb
Host smart-72956c82-036b-441d-a631-eeca04a12217
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3599929216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3599929216
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3509015718
Short name T101
Test name
Test status
Simulation time 145895822 ps
CPU time 0.89 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:24 PM PDT 24
Peak memory 207340 kb
Host smart-e10dd005-4614-43d8-a4dd-c317393137dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35090
15718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3509015718
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.349763174
Short name T1521
Test name
Test status
Simulation time 159529852 ps
CPU time 0.91 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:25 PM PDT 24
Peak memory 207352 kb
Host smart-1f94181c-6bdd-41f4-ac9f-785a6177a11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34976
3174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.349763174
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.580612784
Short name T1109
Test name
Test status
Simulation time 3212742419 ps
CPU time 24.09 seconds
Started Aug 06 08:04:20 PM PDT 24
Finished Aug 06 08:04:45 PM PDT 24
Peak memory 223928 kb
Host smart-8f12a4d5-0fb8-4661-bc3d-e3a24fa81b72
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=580612784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.580612784
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.184221134
Short name T2065
Test name
Test status
Simulation time 9850622208 ps
CPU time 63.98 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207560 kb
Host smart-09e50df8-878d-40a7-abce-f21ea60e0a47
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=184221134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.184221134
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.978869528
Short name T1516
Test name
Test status
Simulation time 194773914 ps
CPU time 0.92 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 207364 kb
Host smart-8a9dc777-9597-4ecd-bf4a-145f8e76dbbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97886
9528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.978869528
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.116702228
Short name T754
Test name
Test status
Simulation time 15697062069 ps
CPU time 21.98 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:45 PM PDT 24
Peak memory 207608 kb
Host smart-f0aa08a5-ab57-4f70-9dd4-ef42d7f75211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670
2228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.116702228
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1043619593
Short name T3029
Test name
Test status
Simulation time 11307268834 ps
CPU time 14.88 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:39 PM PDT 24
Peak memory 207604 kb
Host smart-aef0eadd-4499-4811-a288-5b6497be1e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10436
19593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1043619593
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.3204194246
Short name T205
Test name
Test status
Simulation time 3933553947 ps
CPU time 36.29 seconds
Started Aug 06 08:04:19 PM PDT 24
Finished Aug 06 08:04:55 PM PDT 24
Peak memory 218300 kb
Host smart-0178683c-9b3f-49e4-894c-9093f5c1118e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32041
94246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.3204194246
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1137307731
Short name T2232
Test name
Test status
Simulation time 3080117831 ps
CPU time 86.39 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:05:48 PM PDT 24
Peak memory 215720 kb
Host smart-9169779c-c726-4822-aea5-ae52d0a6cdcb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1137307731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1137307731
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.338273321
Short name T2458
Test name
Test status
Simulation time 243631371 ps
CPU time 1.09 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:25 PM PDT 24
Peak memory 207396 kb
Host smart-499cba8d-e261-4c41-9ae1-57608fa5ac98
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=338273321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.338273321
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1897717940
Short name T2292
Test name
Test status
Simulation time 213095992 ps
CPU time 0.95 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 207316 kb
Host smart-9d46be79-3a47-4dd8-8c5d-5ea871fb1a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18977
17940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1897717940
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.1197119368
Short name T2787
Test name
Test status
Simulation time 1963446132 ps
CPU time 20.1 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:42 PM PDT 24
Peak memory 217256 kb
Host smart-d7a872f5-b390-45c9-9d13-5741912807d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11971
19368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.1197119368
Directory /workspace/16.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1673096719
Short name T1668
Test name
Test status
Simulation time 2860624168 ps
CPU time 84.02 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:05:46 PM PDT 24
Peak memory 217348 kb
Host smart-d30d2d96-7b1f-4075-8133-d998e861e7b4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1673096719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1673096719
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.390583591
Short name T2414
Test name
Test status
Simulation time 158853357 ps
CPU time 0.86 seconds
Started Aug 06 08:04:25 PM PDT 24
Finished Aug 06 08:04:26 PM PDT 24
Peak memory 207420 kb
Host smart-0aa15657-aba0-4cce-a4de-34a5280b940f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=390583591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.390583591
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.691188564
Short name T1725
Test name
Test status
Simulation time 137934414 ps
CPU time 0.86 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207396 kb
Host smart-ba24d02b-741d-40d8-9147-27734c4e42b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69118
8564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.691188564
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.84986341
Short name T2159
Test name
Test status
Simulation time 186801247 ps
CPU time 0.91 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 207316 kb
Host smart-9b16de7d-645a-4860-9310-da23e212f97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84986
341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.84986341
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.4132748267
Short name T1081
Test name
Test status
Simulation time 185535641 ps
CPU time 0.94 seconds
Started Aug 06 08:04:20 PM PDT 24
Finished Aug 06 08:04:21 PM PDT 24
Peak memory 207352 kb
Host smart-5618416d-05ea-46bb-8723-92d1436bfc77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41327
48267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.4132748267
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.359846096
Short name T1130
Test name
Test status
Simulation time 198429769 ps
CPU time 0.89 seconds
Started Aug 06 08:04:20 PM PDT 24
Finished Aug 06 08:04:21 PM PDT 24
Peak memory 207320 kb
Host smart-b578ccfc-e042-4c70-ba15-80a7dcb2532c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35984
6096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.359846096
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1293634335
Short name T1950
Test name
Test status
Simulation time 159746742 ps
CPU time 0.88 seconds
Started Aug 06 08:04:20 PM PDT 24
Finished Aug 06 08:04:21 PM PDT 24
Peak memory 207388 kb
Host smart-aa91335c-14d3-4126-9c10-274a93702353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12936
34335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1293634335
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.99982927
Short name T1072
Test name
Test status
Simulation time 195427073 ps
CPU time 0.97 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:25 PM PDT 24
Peak memory 207416 kb
Host smart-71d6a885-71f6-4a62-b705-6841703a4f76
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=99982927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.99982927
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3932080480
Short name T755
Test name
Test status
Simulation time 154122423 ps
CPU time 0.91 seconds
Started Aug 06 08:04:27 PM PDT 24
Finished Aug 06 08:04:28 PM PDT 24
Peak memory 207340 kb
Host smart-27fb2581-d4db-4f51-95c0-0a109808cfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39320
80480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3932080480
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.532731995
Short name T1799
Test name
Test status
Simulation time 40205286 ps
CPU time 0.81 seconds
Started Aug 06 08:04:20 PM PDT 24
Finished Aug 06 08:04:21 PM PDT 24
Peak memory 207312 kb
Host smart-c7bac9d4-44b5-4fd0-8ed4-1d6c047671b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53273
1995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.532731995
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3024993292
Short name T1252
Test name
Test status
Simulation time 11616780835 ps
CPU time 28.67 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 215852 kb
Host smart-f5a7be6a-6bcd-4a46-a17e-de3bb959c093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30249
93292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3024993292
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1217016132
Short name T491
Test name
Test status
Simulation time 142706762 ps
CPU time 0.83 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:25 PM PDT 24
Peak memory 207412 kb
Host smart-46e392c5-1c43-47fd-8076-b0915b588fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12170
16132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1217016132
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2637628439
Short name T1210
Test name
Test status
Simulation time 191970236 ps
CPU time 0.91 seconds
Started Aug 06 08:04:25 PM PDT 24
Finished Aug 06 08:04:26 PM PDT 24
Peak memory 207384 kb
Host smart-790563bc-31e1-4f6f-a31e-c5f647373eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26376
28439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2637628439
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.3373361598
Short name T600
Test name
Test status
Simulation time 201126099 ps
CPU time 0.93 seconds
Started Aug 06 08:04:19 PM PDT 24
Finished Aug 06 08:04:20 PM PDT 24
Peak memory 207332 kb
Host smart-e3c39da5-bdb9-47b7-93eb-9f83bb05c9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33733
61598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.3373361598
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1613248809
Short name T2254
Test name
Test status
Simulation time 153551467 ps
CPU time 0.87 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 207596 kb
Host smart-4c751d22-df7c-4592-b258-15190e15029a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16132
48809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1613248809
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_resume_link_active.1650938678
Short name T1988
Test name
Test status
Simulation time 20166765009 ps
CPU time 23.6 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:47 PM PDT 24
Peak memory 207440 kb
Host smart-7088bcf1-6d68-4ce5-8215-f731d1733d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16509
38678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.1650938678
Directory /workspace/16.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.4167036538
Short name T1435
Test name
Test status
Simulation time 183919245 ps
CPU time 0.84 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 207340 kb
Host smart-2bf51f3d-ec67-4434-9d56-810ac442c2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41670
36538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.4167036538
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_rx_full.3978054839
Short name T2612
Test name
Test status
Simulation time 390893325 ps
CPU time 1.39 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207400 kb
Host smart-15989dce-0c6e-4dd4-9d12-d5d0934b4430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39780
54839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.3978054839
Directory /workspace/16.usbdev_rx_full/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3702374735
Short name T2009
Test name
Test status
Simulation time 184963086 ps
CPU time 0.88 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 207284 kb
Host smart-a1ef1bce-56c4-4f27-b2e2-b86658ca7e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37023
74735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3702374735
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3314353001
Short name T1496
Test name
Test status
Simulation time 160025257 ps
CPU time 0.91 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:25 PM PDT 24
Peak memory 207316 kb
Host smart-a45250dc-c83a-4741-af9a-6ec2a43497eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33143
53001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3314353001
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1608003715
Short name T615
Test name
Test status
Simulation time 186978303 ps
CPU time 0.93 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:24 PM PDT 24
Peak memory 207396 kb
Host smart-f87f7eef-1954-4983-acfe-838b262200e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16080
03715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1608003715
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.601872916
Short name T543
Test name
Test status
Simulation time 145545486 ps
CPU time 0.9 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207336 kb
Host smart-e47e4fbf-4448-4194-a884-93f9eac7c5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60187
2916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.601872916
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3538403757
Short name T824
Test name
Test status
Simulation time 201014303 ps
CPU time 0.92 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 207356 kb
Host smart-40d5d3d4-4607-4788-b141-881b0263a937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35384
03757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3538403757
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3202269495
Short name T697
Test name
Test status
Simulation time 635048074 ps
CPU time 1.72 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:25 PM PDT 24
Peak memory 207348 kb
Host smart-4113b80f-39fa-4302-a92c-da4a2bc2f3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32022
69495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3202269495
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.1914144650
Short name T2705
Test name
Test status
Simulation time 3267738895 ps
CPU time 91.51 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:05:52 PM PDT 24
Peak memory 217180 kb
Host smart-79d61145-f58d-4985-b802-76db77ed5579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19141
44650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1914144650
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.2193611087
Short name T614
Test name
Test status
Simulation time 1507540622 ps
CPU time 13.13 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:37 PM PDT 24
Peak memory 207496 kb
Host smart-b5d2633e-6661-4cb9-826f-f640a75854bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193611087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_hos
t_handshake.2193611087
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/160.usbdev_endpoint_types.3760700041
Short name T460
Test name
Test status
Simulation time 316244127 ps
CPU time 1.16 seconds
Started Aug 06 08:09:37 PM PDT 24
Finished Aug 06 08:09:38 PM PDT 24
Peak memory 207264 kb
Host smart-7957c13f-c40e-408f-ac5b-32f61dd4be5c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3760700041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.3760700041
Directory /workspace/160.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/161.usbdev_endpoint_types.328762162
Short name T363
Test name
Test status
Simulation time 383317925 ps
CPU time 1.2 seconds
Started Aug 06 08:09:37 PM PDT 24
Finished Aug 06 08:09:38 PM PDT 24
Peak memory 207356 kb
Host smart-9fefeca3-82b4-4b1d-beef-70211aa53234
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=328762162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.328762162
Directory /workspace/161.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/163.usbdev_endpoint_types.826853505
Short name T2323
Test name
Test status
Simulation time 253744672 ps
CPU time 1.02 seconds
Started Aug 06 08:09:34 PM PDT 24
Finished Aug 06 08:09:35 PM PDT 24
Peak memory 207424 kb
Host smart-8764c577-63ff-4db3-8831-642622fc723b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=826853505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.826853505
Directory /workspace/163.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/164.usbdev_endpoint_types.2593899992
Short name T365
Test name
Test status
Simulation time 315858202 ps
CPU time 1.05 seconds
Started Aug 06 08:09:37 PM PDT 24
Finished Aug 06 08:09:38 PM PDT 24
Peak memory 207356 kb
Host smart-7a17c5a9-3644-4db3-a073-6cf82385d93d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2593899992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.2593899992
Directory /workspace/164.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/166.usbdev_endpoint_types.1914350952
Short name T271
Test name
Test status
Simulation time 367486177 ps
CPU time 1.26 seconds
Started Aug 06 08:09:27 PM PDT 24
Finished Aug 06 08:09:29 PM PDT 24
Peak memory 207372 kb
Host smart-f922831d-3ba5-460c-8038-8705e796f0fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1914350952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.1914350952
Directory /workspace/166.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.2096774372
Short name T1838
Test name
Test status
Simulation time 36455878 ps
CPU time 0.68 seconds
Started Aug 06 08:04:39 PM PDT 24
Finished Aug 06 08:04:40 PM PDT 24
Peak memory 207504 kb
Host smart-97490ca7-b9c0-44b5-855f-22041f76095a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2096774372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.2096774372
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2345754353
Short name T1287
Test name
Test status
Simulation time 5126969545 ps
CPU time 8.37 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:32 PM PDT 24
Peak memory 215760 kb
Host smart-eacb105b-983c-4feb-9d5b-a504ad763878
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345754353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.2345754353
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3197414628
Short name T1805
Test name
Test status
Simulation time 13499837824 ps
CPU time 18.26 seconds
Started Aug 06 08:04:21 PM PDT 24
Finished Aug 06 08:04:39 PM PDT 24
Peak memory 215824 kb
Host smart-9e501240-f81e-40b1-9c1c-6f9dfd17cde8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197414628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3197414628
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.4017043562
Short name T1278
Test name
Test status
Simulation time 25744012932 ps
CPU time 30.37 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:54 PM PDT 24
Peak memory 215820 kb
Host smart-27cbf295-c23b-4231-917e-73ac8cf69bea
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017043562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.4017043562
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.4228499303
Short name T1315
Test name
Test status
Simulation time 219472576 ps
CPU time 0.97 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:23 PM PDT 24
Peak memory 207392 kb
Host smart-1cbd70bc-48c2-404a-90af-4da7b51b3891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42284
99303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.4228499303
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1418029366
Short name T1643
Test name
Test status
Simulation time 147959429 ps
CPU time 0.83 seconds
Started Aug 06 08:04:24 PM PDT 24
Finished Aug 06 08:04:25 PM PDT 24
Peak memory 207276 kb
Host smart-8fe7b163-98a6-4532-aa35-e7b02e8f7fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14180
29366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1418029366
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1780027904
Short name T1094
Test name
Test status
Simulation time 378507827 ps
CPU time 1.36 seconds
Started Aug 06 08:04:22 PM PDT 24
Finished Aug 06 08:04:24 PM PDT 24
Peak memory 207396 kb
Host smart-48246572-cf73-4936-a855-46d45a2a4745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17800
27904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1780027904
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.176030586
Short name T757
Test name
Test status
Simulation time 738295947 ps
CPU time 2.19 seconds
Started Aug 06 08:04:26 PM PDT 24
Finished Aug 06 08:04:28 PM PDT 24
Peak memory 207556 kb
Host smart-e9c28377-dbb1-4e62-a112-ba70404fde67
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=176030586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.176030586
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.725404506
Short name T3037
Test name
Test status
Simulation time 41683781806 ps
CPU time 65.6 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:05:29 PM PDT 24
Peak memory 207600 kb
Host smart-973e02e6-4f2d-4291-8447-68ef51f6a119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72540
4506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.725404506
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.869416160
Short name T1958
Test name
Test status
Simulation time 1406865246 ps
CPU time 33.67 seconds
Started Aug 06 08:04:23 PM PDT 24
Finished Aug 06 08:04:57 PM PDT 24
Peak memory 207612 kb
Host smart-1f95fad5-de10-4b8e-b285-efc021fa696e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869416160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.869416160
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1789491664
Short name T1347
Test name
Test status
Simulation time 847935922 ps
CPU time 1.87 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:04:36 PM PDT 24
Peak memory 207368 kb
Host smart-ddb9277f-e899-47ca-9442-c1581f2c9657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17894
91664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1789491664
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.148767706
Short name T1731
Test name
Test status
Simulation time 154603431 ps
CPU time 0.86 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 207336 kb
Host smart-58a0daac-8d63-4e34-a31f-df2eb101a388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14876
7706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.148767706
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.531063479
Short name T23
Test name
Test status
Simulation time 38026479 ps
CPU time 0.68 seconds
Started Aug 06 08:04:37 PM PDT 24
Finished Aug 06 08:04:38 PM PDT 24
Peak memory 207300 kb
Host smart-be31b6d7-de1e-47c5-96b4-99e28f2ee591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53106
3479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.531063479
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.475524307
Short name T2720
Test name
Test status
Simulation time 810445831 ps
CPU time 2.18 seconds
Started Aug 06 08:04:33 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 207524 kb
Host smart-9945acd1-3b0a-4c9e-956d-a4f6431138aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47552
4307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.475524307
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_types.3561870221
Short name T2536
Test name
Test status
Simulation time 247489814 ps
CPU time 0.98 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:04:36 PM PDT 24
Peak memory 207264 kb
Host smart-99cdbfba-bb78-49ed-aa13-8ad0373070d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3561870221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.3561870221
Directory /workspace/17.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3885061841
Short name T1926
Test name
Test status
Simulation time 333546278 ps
CPU time 2.82 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:04:38 PM PDT 24
Peak memory 207432 kb
Host smart-d51fe9b6-41d5-491f-b7a0-bd28bc02b5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38850
61841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3885061841
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1008302340
Short name T1972
Test name
Test status
Simulation time 213525747 ps
CPU time 1.11 seconds
Started Aug 06 08:04:39 PM PDT 24
Finished Aug 06 08:04:41 PM PDT 24
Peak memory 215784 kb
Host smart-d77ac1a6-ecbf-4e7a-97b1-f14460fb0edb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1008302340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1008302340
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.824707630
Short name T1605
Test name
Test status
Simulation time 238427274 ps
CPU time 0.88 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:04:36 PM PDT 24
Peak memory 207308 kb
Host smart-058d4ec7-8f3f-44f6-ac72-f1041d935831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82470
7630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.824707630
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1106983108
Short name T541
Test name
Test status
Simulation time 244525705 ps
CPU time 1.01 seconds
Started Aug 06 08:04:36 PM PDT 24
Finished Aug 06 08:04:37 PM PDT 24
Peak memory 207292 kb
Host smart-b34f4383-1a4d-4b43-be1b-fd588f953329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11069
83108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1106983108
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.1139761053
Short name T668
Test name
Test status
Simulation time 5443784615 ps
CPU time 52.89 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 217896 kb
Host smart-b6df90df-a178-41e6-9578-9864b3c9b093
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1139761053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.1139761053
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.1142392082
Short name T1994
Test name
Test status
Simulation time 11832290026 ps
CPU time 147.21 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:07:01 PM PDT 24
Peak memory 207632 kb
Host smart-234d9a4a-4da4-4633-a077-64ee084c32c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1142392082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.1142392082
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3666715718
Short name T1200
Test name
Test status
Simulation time 208889194 ps
CPU time 0.96 seconds
Started Aug 06 08:04:36 PM PDT 24
Finished Aug 06 08:04:37 PM PDT 24
Peak memory 207288 kb
Host smart-90ecc694-c776-4ce7-88e7-a1e3d447cf86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36667
15718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3666715718
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.1852805990
Short name T2369
Test name
Test status
Simulation time 24779684365 ps
CPU time 30.03 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:05:04 PM PDT 24
Peak memory 215808 kb
Host smart-eeaabf1d-688c-4269-b771-2b230c344d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18528
05990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.1852805990
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.327913014
Short name T921
Test name
Test status
Simulation time 10386518028 ps
CPU time 16.02 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 207620 kb
Host smart-5a0dcc51-7104-4e93-b1f9-5d8a53be8acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32791
3014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.327913014
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3730677014
Short name T879
Test name
Test status
Simulation time 4807887518 ps
CPU time 34.95 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:05:13 PM PDT 24
Peak memory 218216 kb
Host smart-ee4c0c1f-1e6a-48bd-b3a7-d0efed01096e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37306
77014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3730677014
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1996718636
Short name T2002
Test name
Test status
Simulation time 2532075599 ps
CPU time 69 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:05:44 PM PDT 24
Peak memory 215772 kb
Host smart-40c6388e-f07d-4eac-8ace-115f8924a7ba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1996718636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1996718636
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2033044607
Short name T549
Test name
Test status
Simulation time 237609870 ps
CPU time 1.04 seconds
Started Aug 06 08:04:33 PM PDT 24
Finished Aug 06 08:04:34 PM PDT 24
Peak memory 207332 kb
Host smart-972a6959-d074-4934-a51e-87ea686ae76c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2033044607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2033044607
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3703266373
Short name T2784
Test name
Test status
Simulation time 248284926 ps
CPU time 0.93 seconds
Started Aug 06 08:04:32 PM PDT 24
Finished Aug 06 08:04:33 PM PDT 24
Peak memory 207296 kb
Host smart-75e7aeb7-a327-418f-8761-c7141f092a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37032
66373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3703266373
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.1653860884
Short name T1712
Test name
Test status
Simulation time 3347466719 ps
CPU time 26.55 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:05:01 PM PDT 24
Peak memory 217756 kb
Host smart-32e141c7-b0f9-441f-905a-b96fad41b6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16538
60884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.1653860884
Directory /workspace/17.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2685700074
Short name T2482
Test name
Test status
Simulation time 1629569142 ps
CPU time 46.18 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 217128 kb
Host smart-05075de8-28ac-4a87-88e9-cc5454b37e68
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2685700074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2685700074
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.1712131657
Short name T2750
Test name
Test status
Simulation time 175735373 ps
CPU time 0.86 seconds
Started Aug 06 08:04:31 PM PDT 24
Finished Aug 06 08:04:32 PM PDT 24
Peak memory 207352 kb
Host smart-7a4df327-a68a-4dcb-8393-eb40d6a4085a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1712131657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.1712131657
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.188666759
Short name T830
Test name
Test status
Simulation time 170255880 ps
CPU time 0.84 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:04:39 PM PDT 24
Peak memory 207348 kb
Host smart-e9cf4ecf-7353-4116-a77e-96cf3ea6e985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18866
6759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.188666759
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2757528398
Short name T143
Test name
Test status
Simulation time 229840759 ps
CPU time 0.95 seconds
Started Aug 06 08:04:40 PM PDT 24
Finished Aug 06 08:04:41 PM PDT 24
Peak memory 207348 kb
Host smart-7c2b636a-f951-45b6-a31c-1178a3abb90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27575
28398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2757528398
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1844302850
Short name T2284
Test name
Test status
Simulation time 160940611 ps
CPU time 0.92 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:04:39 PM PDT 24
Peak memory 207332 kb
Host smart-6926682b-edb9-44c1-b2fe-a16151acf213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18443
02850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1844302850
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.110931186
Short name T2991
Test name
Test status
Simulation time 187580909 ps
CPU time 0.86 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 207256 kb
Host smart-543b6aaa-748d-4d9e-8ab5-915fff946f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11093
1186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.110931186
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3763681861
Short name T2163
Test name
Test status
Simulation time 151072637 ps
CPU time 0.81 seconds
Started Aug 06 08:04:33 PM PDT 24
Finished Aug 06 08:04:34 PM PDT 24
Peak memory 207364 kb
Host smart-e0dd95c8-5fc8-439e-be2d-61f0bd1d43eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37636
81861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3763681861
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2632593046
Short name T2716
Test name
Test status
Simulation time 144911751 ps
CPU time 0.88 seconds
Started Aug 06 08:04:37 PM PDT 24
Finished Aug 06 08:04:38 PM PDT 24
Peak memory 207348 kb
Host smart-7a637518-989b-47c7-9435-ea48ae1ac597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26325
93046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2632593046
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3606054380
Short name T1477
Test name
Test status
Simulation time 232216599 ps
CPU time 1.07 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 207364 kb
Host smart-2eb88856-0f27-43e7-8a8c-d02944ad5093
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3606054380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3606054380
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.4195850940
Short name T2488
Test name
Test status
Simulation time 164529810 ps
CPU time 0.86 seconds
Started Aug 06 08:04:33 PM PDT 24
Finished Aug 06 08:04:34 PM PDT 24
Peak memory 207388 kb
Host smart-22bc9253-03bb-4d46-a8a3-166fe0d03e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41958
50940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.4195850940
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2094294550
Short name T2786
Test name
Test status
Simulation time 43325982 ps
CPU time 0.71 seconds
Started Aug 06 08:04:43 PM PDT 24
Finished Aug 06 08:04:43 PM PDT 24
Peak memory 207364 kb
Host smart-68e3d7a2-ec7c-4071-9114-6b590916b3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20942
94550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2094294550
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.4268651887
Short name T1365
Test name
Test status
Simulation time 13450351727 ps
CPU time 34.85 seconds
Started Aug 06 08:04:28 PM PDT 24
Finished Aug 06 08:05:03 PM PDT 24
Peak memory 223992 kb
Host smart-ee8528a8-3525-40c6-b2d3-641619e52248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42686
51887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.4268651887
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.706343676
Short name T2227
Test name
Test status
Simulation time 187699703 ps
CPU time 0.9 seconds
Started Aug 06 08:04:37 PM PDT 24
Finished Aug 06 08:04:38 PM PDT 24
Peak memory 207348 kb
Host smart-52034947-b2d3-42ee-97b7-aa9baa709064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70634
3676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.706343676
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2658388403
Short name T2726
Test name
Test status
Simulation time 195949658 ps
CPU time 0.96 seconds
Started Aug 06 08:04:40 PM PDT 24
Finished Aug 06 08:04:41 PM PDT 24
Peak memory 207356 kb
Host smart-5d46bf01-af4c-424d-82b6-02c878345a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26583
88403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2658388403
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.3805785282
Short name T2405
Test name
Test status
Simulation time 209619075 ps
CPU time 0.9 seconds
Started Aug 06 08:04:39 PM PDT 24
Finished Aug 06 08:04:40 PM PDT 24
Peak memory 207356 kb
Host smart-3fe3129d-1691-454e-b266-911f91fcfb72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38057
85282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.3805785282
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1344084808
Short name T2183
Test name
Test status
Simulation time 164526318 ps
CPU time 0.9 seconds
Started Aug 06 08:04:32 PM PDT 24
Finished Aug 06 08:04:33 PM PDT 24
Peak memory 207332 kb
Host smart-d6204436-076e-48c9-9b26-9b8bcedd5f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13440
84808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1344084808
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_resume_link_active.1437948651
Short name T1480
Test name
Test status
Simulation time 20159422031 ps
CPU time 29.55 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:05:04 PM PDT 24
Peak memory 207396 kb
Host smart-51330186-02c6-4c24-bf88-1e25197da876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14379
48651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.1437948651
Directory /workspace/17.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1794175988
Short name T1923
Test name
Test status
Simulation time 198438982 ps
CPU time 0.87 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 207028 kb
Host smart-193fd619-7058-48ab-9cda-a0022f253c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17941
75988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1794175988
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_rx_full.1212857115
Short name T2541
Test name
Test status
Simulation time 255966702 ps
CPU time 1.08 seconds
Started Aug 06 08:04:33 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 207380 kb
Host smart-426946cd-efec-46e7-915c-2ff50b8c3b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12128
57115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.1212857115
Directory /workspace/17.usbdev_rx_full/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1526975064
Short name T1325
Test name
Test status
Simulation time 216265567 ps
CPU time 0.96 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 207340 kb
Host smart-2044c504-b0ce-4aa1-8756-b60d5593e074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15269
75064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1526975064
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3605086467
Short name T2526
Test name
Test status
Simulation time 154593346 ps
CPU time 0.82 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 206896 kb
Host smart-9c985571-ed30-4a16-8daa-3bade8e4b8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36050
86467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3605086467
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3778169713
Short name T1247
Test name
Test status
Simulation time 245793761 ps
CPU time 1.02 seconds
Started Aug 06 08:04:36 PM PDT 24
Finished Aug 06 08:04:37 PM PDT 24
Peak memory 207324 kb
Host smart-dea9423c-107b-4e9c-9285-1a557142d670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37781
69713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3778169713
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.619510323
Short name T922
Test name
Test status
Simulation time 2661941670 ps
CPU time 77.3 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:05:55 PM PDT 24
Peak memory 217424 kb
Host smart-af230717-6520-4dd2-b759-99ae542acbf5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=619510323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.619510323
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.4255922663
Short name T730
Test name
Test status
Simulation time 147899854 ps
CPU time 0.84 seconds
Started Aug 06 08:04:44 PM PDT 24
Finished Aug 06 08:04:45 PM PDT 24
Peak memory 207400 kb
Host smart-dbceaf17-e6ed-4b7f-81bc-5ff161e46546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42559
22663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.4255922663
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.115581967
Short name T2518
Test name
Test status
Simulation time 193774171 ps
CPU time 0.94 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 207420 kb
Host smart-06bae238-6bd3-4fcd-9820-1f0e7b7d8473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11558
1967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.115581967
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.3267805080
Short name T519
Test name
Test status
Simulation time 1273274983 ps
CPU time 2.95 seconds
Started Aug 06 08:04:32 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 207476 kb
Host smart-9a3cc994-f5bc-4d4d-b3df-68b3955397e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32678
05080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.3267805080
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.1560878333
Short name T2617
Test name
Test status
Simulation time 2473316642 ps
CPU time 18.99 seconds
Started Aug 06 08:04:36 PM PDT 24
Finished Aug 06 08:04:55 PM PDT 24
Peak memory 217508 kb
Host smart-b0587cc0-ea53-4d77-82b4-eea6fca9ee9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15608
78333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.1560878333
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.4092728325
Short name T3072
Test name
Test status
Simulation time 6389118143 ps
CPU time 40.47 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:05:16 PM PDT 24
Peak memory 207648 kb
Host smart-7b0ab944-3cf4-4e53-9b8d-5554fec91108
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092728325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_hos
t_handshake.4092728325
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/170.usbdev_endpoint_types.2126555736
Short name T357
Test name
Test status
Simulation time 623403745 ps
CPU time 1.63 seconds
Started Aug 06 08:09:25 PM PDT 24
Finished Aug 06 08:09:27 PM PDT 24
Peak memory 207348 kb
Host smart-b751f497-3b86-4d5c-8c4e-282d88cbbb79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2126555736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.2126555736
Directory /workspace/170.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/172.usbdev_endpoint_types.2809854838
Short name T2916
Test name
Test status
Simulation time 666533901 ps
CPU time 1.56 seconds
Started Aug 06 08:09:34 PM PDT 24
Finished Aug 06 08:09:36 PM PDT 24
Peak memory 207308 kb
Host smart-686d0e6c-75e7-4801-82b2-072f4704f37c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2809854838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.2809854838
Directory /workspace/172.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/173.usbdev_endpoint_types.2318518761
Short name T347
Test name
Test status
Simulation time 769309384 ps
CPU time 1.86 seconds
Started Aug 06 08:09:25 PM PDT 24
Finished Aug 06 08:09:27 PM PDT 24
Peak memory 207324 kb
Host smart-67a3be39-a9a9-455c-8b0f-ed772a2c0d4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2318518761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.2318518761
Directory /workspace/173.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/174.usbdev_endpoint_types.1647491357
Short name T86
Test name
Test status
Simulation time 176142796 ps
CPU time 0.89 seconds
Started Aug 06 08:09:24 PM PDT 24
Finished Aug 06 08:09:25 PM PDT 24
Peak memory 206912 kb
Host smart-6de6ea3e-501c-456f-8cdd-9f3c8b21d85a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1647491357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.1647491357
Directory /workspace/174.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/175.usbdev_endpoint_types.76351848
Short name T416
Test name
Test status
Simulation time 691769040 ps
CPU time 1.72 seconds
Started Aug 06 08:09:34 PM PDT 24
Finished Aug 06 08:09:41 PM PDT 24
Peak memory 207264 kb
Host smart-9cf7a88a-24bb-4dcf-8094-b86ea46a8914
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=76351848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.76351848
Directory /workspace/175.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/176.usbdev_endpoint_types.2411800834
Short name T398
Test name
Test status
Simulation time 670980704 ps
CPU time 1.69 seconds
Started Aug 06 08:09:25 PM PDT 24
Finished Aug 06 08:09:27 PM PDT 24
Peak memory 207324 kb
Host smart-77ae88a9-74af-4e22-be60-9d9e431f3815
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2411800834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.2411800834
Directory /workspace/176.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/178.usbdev_endpoint_types.1777391216
Short name T439
Test name
Test status
Simulation time 532022810 ps
CPU time 1.45 seconds
Started Aug 06 08:09:40 PM PDT 24
Finished Aug 06 08:09:41 PM PDT 24
Peak memory 207332 kb
Host smart-9c3ce219-f397-47b0-835a-e1b023610413
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1777391216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.1777391216
Directory /workspace/178.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/179.usbdev_endpoint_types.2688656666
Short name T2133
Test name
Test status
Simulation time 463641295 ps
CPU time 1.26 seconds
Started Aug 06 08:09:35 PM PDT 24
Finished Aug 06 08:09:36 PM PDT 24
Peak memory 207340 kb
Host smart-eea26f5c-3191-4fd6-846d-204053923e3b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2688656666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.2688656666
Directory /workspace/179.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.310651126
Short name T1590
Test name
Test status
Simulation time 55278124 ps
CPU time 0.71 seconds
Started Aug 06 08:04:44 PM PDT 24
Finished Aug 06 08:04:45 PM PDT 24
Peak memory 207432 kb
Host smart-153450cd-f18b-487e-b858-16de243859e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=310651126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.310651126
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3007600169
Short name T2754
Test name
Test status
Simulation time 6440546023 ps
CPU time 8.35 seconds
Started Aug 06 08:04:33 PM PDT 24
Finished Aug 06 08:04:42 PM PDT 24
Peak memory 215792 kb
Host smart-2c59f451-134f-4228-a8af-b4c23dcfe91d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007600169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.3007600169
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.3934394348
Short name T2591
Test name
Test status
Simulation time 19767675912 ps
CPU time 24.51 seconds
Started Aug 06 08:04:40 PM PDT 24
Finished Aug 06 08:05:04 PM PDT 24
Peak memory 207668 kb
Host smart-ffb46fbb-e230-41c8-ac68-d9e69350bfe1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934394348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.3934394348
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.2353927446
Short name T2846
Test name
Test status
Simulation time 23593820131 ps
CPU time 31.24 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:05:06 PM PDT 24
Peak memory 215904 kb
Host smart-53f72eac-06cc-4fa9-846f-4c96c3009826
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353927446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.2353927446
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3284967516
Short name T1256
Test name
Test status
Simulation time 152974165 ps
CPU time 0.89 seconds
Started Aug 06 08:04:37 PM PDT 24
Finished Aug 06 08:04:38 PM PDT 24
Peak memory 207416 kb
Host smart-f7022fd2-7983-4484-84e8-0e6476a3dff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32849
67516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3284967516
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1942043421
Short name T2666
Test name
Test status
Simulation time 169655751 ps
CPU time 0.88 seconds
Started Aug 06 08:04:43 PM PDT 24
Finished Aug 06 08:04:44 PM PDT 24
Peak memory 207288 kb
Host smart-730ba37f-fbca-430d-9a47-9a4e86ea64ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19420
43421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1942043421
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3162446921
Short name T729
Test name
Test status
Simulation time 502730410 ps
CPU time 1.82 seconds
Started Aug 06 08:04:37 PM PDT 24
Finished Aug 06 08:04:39 PM PDT 24
Peak memory 207424 kb
Host smart-c5ab64dd-2a80-4352-aa0b-194ca7b155bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31624
46921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3162446921
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.4054393155
Short name T810
Test name
Test status
Simulation time 453187212 ps
CPU time 1.47 seconds
Started Aug 06 08:04:33 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 207204 kb
Host smart-a91ec7e2-90ef-446a-93eb-204df4e1ed56
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4054393155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.4054393155
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.325660772
Short name T2241
Test name
Test status
Simulation time 34258085630 ps
CPU time 54.67 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:05:29 PM PDT 24
Peak memory 207660 kb
Host smart-9cff7cbc-7cca-4876-9b35-421acecfc421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32566
0772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.325660772
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.4144148788
Short name T2696
Test name
Test status
Simulation time 2035611165 ps
CPU time 18.21 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:04:53 PM PDT 24
Peak memory 207816 kb
Host smart-ff3b3542-ef18-4ec9-99ef-b1767ccae79e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144148788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.4144148788
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.326397929
Short name T3007
Test name
Test status
Simulation time 602203883 ps
CPU time 1.65 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:04:37 PM PDT 24
Peak memory 207368 kb
Host smart-11625bcf-df48-429a-9c24-88bd3b3abe20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32639
7929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.326397929
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2623958382
Short name T1587
Test name
Test status
Simulation time 177063594 ps
CPU time 0.9 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:04:36 PM PDT 24
Peak memory 207340 kb
Host smart-51cade72-96e6-414d-9fb9-2e33d8bad5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26239
58382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2623958382
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1286996937
Short name T1819
Test name
Test status
Simulation time 61862713 ps
CPU time 0.73 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:04:39 PM PDT 24
Peak memory 207308 kb
Host smart-48c4add4-a4fe-4c6a-be1c-8104588c8605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12869
96937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1286996937
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.349125452
Short name T2993
Test name
Test status
Simulation time 855776591 ps
CPU time 2.32 seconds
Started Aug 06 08:04:40 PM PDT 24
Finished Aug 06 08:04:42 PM PDT 24
Peak memory 207580 kb
Host smart-ecb6adcf-a643-4244-98c0-f78e586e41b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34912
5452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.349125452
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_types.2315416838
Short name T441
Test name
Test status
Simulation time 258886407 ps
CPU time 0.98 seconds
Started Aug 06 08:04:43 PM PDT 24
Finished Aug 06 08:04:44 PM PDT 24
Peak memory 207368 kb
Host smart-e8319cff-29ee-4301-b586-7d60d5ce6ea0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2315416838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.2315416838
Directory /workspace/18.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.298926511
Short name T2733
Test name
Test status
Simulation time 255714112 ps
CPU time 1.91 seconds
Started Aug 06 08:04:40 PM PDT 24
Finished Aug 06 08:04:42 PM PDT 24
Peak memory 207444 kb
Host smart-1d4856ed-2696-49a5-aa7f-458ba53dc8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29892
6511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.298926511
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.47054720
Short name T2747
Test name
Test status
Simulation time 212542002 ps
CPU time 1.1 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:04:36 PM PDT 24
Peak memory 215712 kb
Host smart-061594f7-c6d0-403a-a80e-6a1fa6fd0e07
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=47054720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.47054720
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1243475721
Short name T1232
Test name
Test status
Simulation time 153764798 ps
CPU time 0.83 seconds
Started Aug 06 08:04:31 PM PDT 24
Finished Aug 06 08:04:32 PM PDT 24
Peak memory 207312 kb
Host smart-b0d18b7a-3020-4872-9d82-a7807f34ac52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12434
75721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1243475721
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2186984261
Short name T2744
Test name
Test status
Simulation time 150081445 ps
CPU time 0.83 seconds
Started Aug 06 08:04:37 PM PDT 24
Finished Aug 06 08:04:38 PM PDT 24
Peak memory 207372 kb
Host smart-6f239c33-8053-47d6-8d55-c31d172f037e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21869
84261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2186984261
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.276252552
Short name T1559
Test name
Test status
Simulation time 2897852162 ps
CPU time 29.55 seconds
Started Aug 06 08:04:40 PM PDT 24
Finished Aug 06 08:05:10 PM PDT 24
Peak memory 223976 kb
Host smart-5be41cec-35f9-42ee-883b-0002c7f558ab
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=276252552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.276252552
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.415414268
Short name T1088
Test name
Test status
Simulation time 11240543023 ps
CPU time 77.17 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:05:51 PM PDT 24
Peak memory 207636 kb
Host smart-33983f89-cee7-42f8-ac74-35c3b9449409
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=415414268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.415414268
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.1082244562
Short name T3018
Test name
Test status
Simulation time 225701514 ps
CPU time 1.01 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:04:35 PM PDT 24
Peak memory 207380 kb
Host smart-a3b19cae-c631-4e42-b5c4-acb640645459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10822
44562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.1082244562
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1121458172
Short name T1756
Test name
Test status
Simulation time 28198019495 ps
CPU time 43.27 seconds
Started Aug 06 08:04:34 PM PDT 24
Finished Aug 06 08:05:17 PM PDT 24
Peak memory 207616 kb
Host smart-a6e632e4-77f9-4442-821b-3201ae179abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11214
58172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1121458172
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.579620944
Short name T1198
Test name
Test status
Simulation time 9448477791 ps
CPU time 10.73 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:04:46 PM PDT 24
Peak memory 207680 kb
Host smart-1f5b6ac8-58a2-4006-ba81-6b30e23bf69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57962
0944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.579620944
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.2381965416
Short name T1675
Test name
Test status
Simulation time 3223087531 ps
CPU time 86.55 seconds
Started Aug 06 08:04:39 PM PDT 24
Finished Aug 06 08:06:06 PM PDT 24
Peak memory 224076 kb
Host smart-3bea9054-b257-4946-a216-ade89e621dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23819
65416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.2381965416
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1349512630
Short name T3025
Test name
Test status
Simulation time 2441286711 ps
CPU time 24.81 seconds
Started Aug 06 08:04:43 PM PDT 24
Finished Aug 06 08:05:07 PM PDT 24
Peak memory 223980 kb
Host smart-1b0b0a65-bc2b-413c-b6e4-57d19aa35a65
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1349512630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1349512630
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2482524672
Short name T528
Test name
Test status
Simulation time 245417436 ps
CPU time 1 seconds
Started Aug 06 08:04:40 PM PDT 24
Finished Aug 06 08:04:41 PM PDT 24
Peak memory 207392 kb
Host smart-82058ec1-acbf-48de-919e-9a6e66b62242
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2482524672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2482524672
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.937717186
Short name T1409
Test name
Test status
Simulation time 185830466 ps
CPU time 0.94 seconds
Started Aug 06 08:04:39 PM PDT 24
Finished Aug 06 08:04:40 PM PDT 24
Peak memory 207348 kb
Host smart-42f12a42-c245-434d-b715-96216c6baf0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93771
7186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.937717186
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.4162923141
Short name T995
Test name
Test status
Simulation time 2139456547 ps
CPU time 21.33 seconds
Started Aug 06 08:04:39 PM PDT 24
Finished Aug 06 08:05:00 PM PDT 24
Peak memory 223916 kb
Host smart-b461d3fc-baac-41a3-b01b-80b3d74a8906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41629
23141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.4162923141
Directory /workspace/18.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.3288611100
Short name T1893
Test name
Test status
Simulation time 2391427721 ps
CPU time 68.06 seconds
Started Aug 06 08:04:39 PM PDT 24
Finished Aug 06 08:05:47 PM PDT 24
Peak memory 217376 kb
Host smart-761b6ce4-a241-48a5-b5a3-b89acf099b2e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3288611100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.3288611100
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.1762220757
Short name T947
Test name
Test status
Simulation time 161836701 ps
CPU time 0.85 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:04:39 PM PDT 24
Peak memory 207368 kb
Host smart-ebf8ad7b-2282-4747-8e49-02a1320e9a7e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1762220757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.1762220757
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3058304095
Short name T2706
Test name
Test status
Simulation time 139162946 ps
CPU time 0.78 seconds
Started Aug 06 08:04:43 PM PDT 24
Finished Aug 06 08:04:44 PM PDT 24
Peak memory 207380 kb
Host smart-a5040ec4-f3b9-48e4-954b-5aed7c5f42e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30583
04095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3058304095
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.862116289
Short name T527
Test name
Test status
Simulation time 225450637 ps
CPU time 0.94 seconds
Started Aug 06 08:04:43 PM PDT 24
Finished Aug 06 08:04:44 PM PDT 24
Peak memory 207320 kb
Host smart-6d69a4a4-4015-4d5b-9014-0566b71bdd12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86211
6289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.862116289
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.4263796652
Short name T270
Test name
Test status
Simulation time 199688528 ps
CPU time 0.9 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:04:36 PM PDT 24
Peak memory 207420 kb
Host smart-726f0e6c-635a-4b0c-87b3-bc5cf3771c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42637
96652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.4263796652
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.4120954853
Short name T2392
Test name
Test status
Simulation time 191929004 ps
CPU time 0.89 seconds
Started Aug 06 08:04:40 PM PDT 24
Finished Aug 06 08:04:41 PM PDT 24
Peak memory 207380 kb
Host smart-10436a24-9952-4ecf-87a7-a05f9947feb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41209
54853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.4120954853
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2470350218
Short name T2519
Test name
Test status
Simulation time 155252524 ps
CPU time 0.92 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:04:39 PM PDT 24
Peak memory 207364 kb
Host smart-eb5ce379-d5c3-4503-a12f-6a46c7d3f07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24703
50218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2470350218
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.3177235271
Short name T2356
Test name
Test status
Simulation time 228130304 ps
CPU time 1.04 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:04:40 PM PDT 24
Peak memory 207348 kb
Host smart-4644a068-1320-448b-b72d-5e3824d19483
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3177235271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.3177235271
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.2389148385
Short name T1282
Test name
Test status
Simulation time 151966496 ps
CPU time 0.82 seconds
Started Aug 06 08:04:42 PM PDT 24
Finished Aug 06 08:04:43 PM PDT 24
Peak memory 207296 kb
Host smart-13869afe-41b8-492d-b198-8caa4d199b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23891
48385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.2389148385
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3648630096
Short name T1051
Test name
Test status
Simulation time 14949083877 ps
CPU time 40.75 seconds
Started Aug 06 08:04:35 PM PDT 24
Finished Aug 06 08:05:16 PM PDT 24
Peak memory 215864 kb
Host smart-18fd53c4-e12b-4eda-af78-f7a559605d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36486
30096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3648630096
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.3776488136
Short name T2378
Test name
Test status
Simulation time 203571062 ps
CPU time 0.98 seconds
Started Aug 06 08:04:42 PM PDT 24
Finished Aug 06 08:04:43 PM PDT 24
Peak memory 207324 kb
Host smart-68d94a5f-c10d-4704-80e8-1e8c20d0d281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37764
88136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.3776488136
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.727230614
Short name T901
Test name
Test status
Simulation time 229730397 ps
CPU time 0.92 seconds
Started Aug 06 08:04:41 PM PDT 24
Finished Aug 06 08:04:42 PM PDT 24
Peak memory 207328 kb
Host smart-2fdb45c8-c009-48cf-aa11-ed22cc122e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72723
0614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.727230614
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.1802494868
Short name T1431
Test name
Test status
Simulation time 170712378 ps
CPU time 0.89 seconds
Started Aug 06 08:04:39 PM PDT 24
Finished Aug 06 08:04:40 PM PDT 24
Peak memory 207360 kb
Host smart-7ec75279-ad6a-4779-8cab-325d6b379106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18024
94868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.1802494868
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.2742199451
Short name T2339
Test name
Test status
Simulation time 155021162 ps
CPU time 0.84 seconds
Started Aug 06 08:04:41 PM PDT 24
Finished Aug 06 08:04:47 PM PDT 24
Peak memory 207320 kb
Host smart-7d27b963-8cd4-429c-bc80-122f6a8a46aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27421
99451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2742199451
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_resume_link_active.3728997179
Short name T2032
Test name
Test status
Simulation time 20173916828 ps
CPU time 21.94 seconds
Started Aug 06 08:04:37 PM PDT 24
Finished Aug 06 08:04:59 PM PDT 24
Peak memory 207684 kb
Host smart-ebd13e8f-e88c-46bf-8675-24eb9535949f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37289
97179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_resume_link_active.3728997179
Directory /workspace/18.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3397147760
Short name T595
Test name
Test status
Simulation time 178816648 ps
CPU time 0.92 seconds
Started Aug 06 08:04:36 PM PDT 24
Finished Aug 06 08:04:37 PM PDT 24
Peak memory 207316 kb
Host smart-bbf5435b-3de8-4387-8aa2-5a59be136ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33971
47760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3397147760
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_rx_full.3097357913
Short name T1463
Test name
Test status
Simulation time 411035455 ps
CPU time 1.34 seconds
Started Aug 06 08:04:40 PM PDT 24
Finished Aug 06 08:04:42 PM PDT 24
Peak memory 207352 kb
Host smart-31618a63-6c11-4027-a4cf-a9a931b53a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30973
57913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.3097357913
Directory /workspace/18.usbdev_rx_full/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1491114020
Short name T2326
Test name
Test status
Simulation time 193855393 ps
CPU time 0.86 seconds
Started Aug 06 08:04:36 PM PDT 24
Finished Aug 06 08:04:37 PM PDT 24
Peak memory 207288 kb
Host smart-6b2f4018-edb0-456d-a5a7-97a5327c2c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14911
14020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1491114020
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1583746484
Short name T1126
Test name
Test status
Simulation time 168901729 ps
CPU time 0.85 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:04:39 PM PDT 24
Peak memory 207344 kb
Host smart-357cb347-e03f-4138-973e-f0d61c88a648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15837
46484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1583746484
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3201418599
Short name T2367
Test name
Test status
Simulation time 226169686 ps
CPU time 1.03 seconds
Started Aug 06 08:04:40 PM PDT 24
Finished Aug 06 08:04:41 PM PDT 24
Peak memory 207348 kb
Host smart-ca718ed5-018c-42a1-be05-06059d689ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32014
18599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3201418599
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.25745874
Short name T594
Test name
Test status
Simulation time 2362746954 ps
CPU time 67.77 seconds
Started Aug 06 08:04:44 PM PDT 24
Finished Aug 06 08:05:52 PM PDT 24
Peak memory 215916 kb
Host smart-b2339c8f-c5c4-483b-bed4-6bb5b7d02dab
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=25745874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.25745874
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3998411925
Short name T2393
Test name
Test status
Simulation time 149668688 ps
CPU time 0.88 seconds
Started Aug 06 08:04:38 PM PDT 24
Finished Aug 06 08:04:39 PM PDT 24
Peak memory 207408 kb
Host smart-f886d6e8-f1cc-41e3-b2bd-cbff19960f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39984
11925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3998411925
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2577748219
Short name T753
Test name
Test status
Simulation time 156090992 ps
CPU time 0.84 seconds
Started Aug 06 08:04:41 PM PDT 24
Finished Aug 06 08:04:42 PM PDT 24
Peak memory 207324 kb
Host smart-c89fd784-a43c-4ae4-b5e7-f574f6356912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25777
48219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2577748219
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.1980065395
Short name T1585
Test name
Test status
Simulation time 863203667 ps
CPU time 2.23 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 207504 kb
Host smart-79abce9b-1de4-43e4-ae8c-f45d45ffae71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19800
65395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.1980065395
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.3792377117
Short name T2566
Test name
Test status
Simulation time 4161391697 ps
CPU time 118.19 seconds
Started Aug 06 08:04:46 PM PDT 24
Finished Aug 06 08:06:44 PM PDT 24
Peak memory 215880 kb
Host smart-7f827b2b-1397-44c8-9f30-038b0ce45d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37923
77117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.3792377117
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.3300080556
Short name T1896
Test name
Test status
Simulation time 5004801796 ps
CPU time 34.87 seconds
Started Aug 06 08:04:36 PM PDT 24
Finished Aug 06 08:05:11 PM PDT 24
Peak memory 207624 kb
Host smart-072dbeb1-5391-4c49-9706-f908ea09da29
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300080556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_hos
t_handshake.3300080556
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/180.usbdev_endpoint_types.1780935030
Short name T449
Test name
Test status
Simulation time 160954653 ps
CPU time 0.86 seconds
Started Aug 06 08:09:21 PM PDT 24
Finished Aug 06 08:09:22 PM PDT 24
Peak memory 207320 kb
Host smart-8eebf15e-a070-4895-b321-b8117738df96
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1780935030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.1780935030
Directory /workspace/180.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/181.usbdev_endpoint_types.20650436
Short name T423
Test name
Test status
Simulation time 582560356 ps
CPU time 1.57 seconds
Started Aug 06 08:09:20 PM PDT 24
Finished Aug 06 08:09:22 PM PDT 24
Peak memory 207372 kb
Host smart-520e0963-0183-4b91-a26b-1b613323ba5a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=20650436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.20650436
Directory /workspace/181.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/182.usbdev_endpoint_types.3854649798
Short name T444
Test name
Test status
Simulation time 197568299 ps
CPU time 1 seconds
Started Aug 06 08:09:35 PM PDT 24
Finished Aug 06 08:09:36 PM PDT 24
Peak memory 207328 kb
Host smart-02adc887-e884-42ac-afb8-e9d919e5eafb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3854649798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.3854649798
Directory /workspace/182.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/183.usbdev_endpoint_types.3698154715
Short name T2570
Test name
Test status
Simulation time 324174918 ps
CPU time 1.05 seconds
Started Aug 06 08:09:36 PM PDT 24
Finished Aug 06 08:09:37 PM PDT 24
Peak memory 207316 kb
Host smart-e43eae3a-016e-4f12-b540-dc98311fbc01
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3698154715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.3698154715
Directory /workspace/183.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/185.usbdev_endpoint_types.2803912824
Short name T378
Test name
Test status
Simulation time 482199847 ps
CPU time 1.32 seconds
Started Aug 06 08:09:25 PM PDT 24
Finished Aug 06 08:09:27 PM PDT 24
Peak memory 207348 kb
Host smart-65e32061-9e8a-4a42-b51f-dfa082da072a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2803912824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.2803912824
Directory /workspace/185.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/186.usbdev_endpoint_types.3635330699
Short name T2563
Test name
Test status
Simulation time 371433301 ps
CPU time 1.25 seconds
Started Aug 06 08:09:44 PM PDT 24
Finished Aug 06 08:09:46 PM PDT 24
Peak memory 207328 kb
Host smart-c89c3d2b-270c-4344-b8a6-be0c832d9fdd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3635330699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.3635330699
Directory /workspace/186.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/187.usbdev_endpoint_types.2135880045
Short name T425
Test name
Test status
Simulation time 194627353 ps
CPU time 1.08 seconds
Started Aug 06 08:09:24 PM PDT 24
Finished Aug 06 08:09:25 PM PDT 24
Peak memory 207392 kb
Host smart-ac059120-85c9-4168-b908-c3fdb524a34d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2135880045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.2135880045
Directory /workspace/187.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.300805777
Short name T2806
Test name
Test status
Simulation time 42487880 ps
CPU time 0.68 seconds
Started Aug 06 08:04:53 PM PDT 24
Finished Aug 06 08:04:53 PM PDT 24
Peak memory 207484 kb
Host smart-a9a840b2-64ba-4416-ae3d-36aeb8bae16a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=300805777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.300805777
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.381934934
Short name T1491
Test name
Test status
Simulation time 6384260108 ps
CPU time 9.26 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:58 PM PDT 24
Peak memory 215816 kb
Host smart-48f61570-3030-4403-ab03-a1e094612f4b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381934934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_disconnect.381934934
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1523638694
Short name T1586
Test name
Test status
Simulation time 14597451007 ps
CPU time 15.35 seconds
Started Aug 06 08:04:47 PM PDT 24
Finished Aug 06 08:05:03 PM PDT 24
Peak memory 215848 kb
Host smart-3f3d14cd-1a08-4154-b20c-c239207472cc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523638694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1523638694
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.383709323
Short name T1711
Test name
Test status
Simulation time 31444170798 ps
CPU time 42.88 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:05:31 PM PDT 24
Peak memory 207604 kb
Host smart-8137e6c7-685b-4cf4-99a9-29c5f46fea84
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383709323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_resume.383709323
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2356019879
Short name T2847
Test name
Test status
Simulation time 174218231 ps
CPU time 0.84 seconds
Started Aug 06 08:04:51 PM PDT 24
Finished Aug 06 08:04:52 PM PDT 24
Peak memory 207292 kb
Host smart-1cd25775-eca8-41f9-81c8-19c89d433df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23560
19879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2356019879
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1594354241
Short name T2093
Test name
Test status
Simulation time 169197927 ps
CPU time 0.87 seconds
Started Aug 06 08:04:57 PM PDT 24
Finished Aug 06 08:04:58 PM PDT 24
Peak memory 207412 kb
Host smart-ec9706ee-16bb-4a61-8e13-684aeefc5e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15943
54241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1594354241
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.4174444954
Short name T2114
Test name
Test status
Simulation time 275751688 ps
CPU time 1.21 seconds
Started Aug 06 08:04:50 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 207264 kb
Host smart-faa0c556-9515-4a43-b007-79b8fb44ef5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41744
44954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.4174444954
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.161481754
Short name T2948
Test name
Test status
Simulation time 1146619472 ps
CPU time 2.78 seconds
Started Aug 06 08:04:46 PM PDT 24
Finished Aug 06 08:04:49 PM PDT 24
Peak memory 207524 kb
Host smart-c37dd25d-62a9-422b-9695-75617733e740
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=161481754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.161481754
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.3671072819
Short name T1172
Test name
Test status
Simulation time 42126802030 ps
CPU time 66.39 seconds
Started Aug 06 08:04:47 PM PDT 24
Finished Aug 06 08:05:54 PM PDT 24
Peak memory 207648 kb
Host smart-7bf31bf5-7d11-4678-bb5f-7ad836da2d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36710
72819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.3671072819
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.2614386637
Short name T1467
Test name
Test status
Simulation time 2188853637 ps
CPU time 14.26 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:05:03 PM PDT 24
Peak memory 207652 kb
Host smart-9f187973-ed99-41b7-a31b-99c5021ab994
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614386637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.2614386637
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.1075049706
Short name T2236
Test name
Test status
Simulation time 580793728 ps
CPU time 1.6 seconds
Started Aug 06 08:04:46 PM PDT 24
Finished Aug 06 08:04:48 PM PDT 24
Peak memory 207376 kb
Host smart-91d7eead-5d5d-4324-9e9e-92a1a555dfa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10750
49706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.1075049706
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.2109041224
Short name T992
Test name
Test status
Simulation time 145222775 ps
CPU time 0.86 seconds
Started Aug 06 08:04:51 PM PDT 24
Finished Aug 06 08:04:52 PM PDT 24
Peak memory 207320 kb
Host smart-c42904ab-28c7-4364-82ce-65bb44543d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21090
41224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.2109041224
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2449412785
Short name T1007
Test name
Test status
Simulation time 63447792 ps
CPU time 0.69 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207340 kb
Host smart-5198dc60-2982-4b4c-821d-38094cf3fd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24494
12785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2449412785
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3075358078
Short name T1522
Test name
Test status
Simulation time 899709918 ps
CPU time 2.62 seconds
Started Aug 06 08:04:50 PM PDT 24
Finished Aug 06 08:04:52 PM PDT 24
Peak memory 207488 kb
Host smart-94ae2be7-6fd2-461c-99ce-7a3d5052f0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30753
58078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3075358078
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_types.4283576617
Short name T1914
Test name
Test status
Simulation time 413489045 ps
CPU time 1.2 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 207304 kb
Host smart-e7ed436d-061b-4f8b-8671-d55355212451
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4283576617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.4283576617
Directory /workspace/19.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.3032585956
Short name T2564
Test name
Test status
Simulation time 166039316 ps
CPU time 1.81 seconds
Started Aug 06 08:04:47 PM PDT 24
Finished Aug 06 08:04:48 PM PDT 24
Peak memory 207476 kb
Host smart-718258e7-853f-46f7-a9f7-b7a766a80097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30325
85956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.3032585956
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.203797621
Short name T1717
Test name
Test status
Simulation time 249020460 ps
CPU time 1.2 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:49 PM PDT 24
Peak memory 215692 kb
Host smart-6613ee1d-0307-4422-b573-12d183a2adf9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=203797621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.203797621
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.626727726
Short name T1921
Test name
Test status
Simulation time 135547085 ps
CPU time 0.84 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207320 kb
Host smart-1d36e064-a6ac-4ac1-8b1b-dc3037cf4dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62672
7726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.626727726
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2268581673
Short name T1095
Test name
Test status
Simulation time 181803105 ps
CPU time 0.91 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:49 PM PDT 24
Peak memory 207376 kb
Host smart-d5223fbb-44d3-45d7-a047-2090a78480c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22685
81673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2268581673
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.1966584170
Short name T869
Test name
Test status
Simulation time 2745097769 ps
CPU time 21.34 seconds
Started Aug 06 08:04:58 PM PDT 24
Finished Aug 06 08:05:19 PM PDT 24
Peak memory 215904 kb
Host smart-30802cf9-94b6-468e-af7f-ba70742061cf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1966584170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.1966584170
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.2238355841
Short name T1201
Test name
Test status
Simulation time 8513500750 ps
CPU time 55.89 seconds
Started Aug 06 08:04:47 PM PDT 24
Finished Aug 06 08:05:43 PM PDT 24
Peak memory 207608 kb
Host smart-3da36d8e-1ef0-4a6e-bb5b-1d0f9d265385
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2238355841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.2238355841
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.3778326546
Short name T1600
Test name
Test status
Simulation time 192451799 ps
CPU time 0.96 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:04:56 PM PDT 24
Peak memory 207344 kb
Host smart-96e2f341-9a37-44cf-acd4-a418db0bb3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37783
26546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.3778326546
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.859743395
Short name T2646
Test name
Test status
Simulation time 23963089351 ps
CPU time 35.03 seconds
Started Aug 06 08:04:44 PM PDT 24
Finished Aug 06 08:05:19 PM PDT 24
Peak memory 215816 kb
Host smart-2edf4103-0131-4946-a2f3-1191ada79f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85974
3395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.859743395
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.3364790505
Short name T216
Test name
Test status
Simulation time 10300445488 ps
CPU time 12.79 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:05:02 PM PDT 24
Peak memory 207584 kb
Host smart-b25a7091-ede0-4848-b8fa-90e2d4ffd3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33647
90505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.3364790505
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.881448322
Short name T1199
Test name
Test status
Simulation time 4746174866 ps
CPU time 134.49 seconds
Started Aug 06 08:04:46 PM PDT 24
Finished Aug 06 08:07:01 PM PDT 24
Peak memory 218240 kb
Host smart-65da8d10-05ee-4090-b3b5-1b43012c86a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88144
8322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.881448322
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2251399001
Short name T2017
Test name
Test status
Simulation time 2353323383 ps
CPU time 68.37 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:05:57 PM PDT 24
Peak memory 217500 kb
Host smart-970d3ee6-2e81-44c3-8ba4-c2271579e2b5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2251399001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2251399001
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.8993512
Short name T1400
Test name
Test status
Simulation time 262305960 ps
CPU time 0.96 seconds
Started Aug 06 08:04:57 PM PDT 24
Finished Aug 06 08:04:58 PM PDT 24
Peak memory 207444 kb
Host smart-f0abd43e-cc9f-49a6-9c4f-4910119f78aa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=8993512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.8993512
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.823869454
Short name T925
Test name
Test status
Simulation time 211056469 ps
CPU time 0.95 seconds
Started Aug 06 08:04:42 PM PDT 24
Finished Aug 06 08:04:43 PM PDT 24
Peak memory 207368 kb
Host smart-4d799694-b2fd-4cdb-95b2-0f7da48ddf42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82386
9454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.823869454
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.2429234933
Short name T784
Test name
Test status
Simulation time 3130542961 ps
CPU time 91.46 seconds
Started Aug 06 08:04:47 PM PDT 24
Finished Aug 06 08:06:24 PM PDT 24
Peak memory 217724 kb
Host smart-7c5e7795-c97b-4499-a843-169412686379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24292
34933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.2429234933
Directory /workspace/19.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2520347672
Short name T196
Test name
Test status
Simulation time 2277875234 ps
CPU time 64.34 seconds
Started Aug 06 08:04:57 PM PDT 24
Finished Aug 06 08:06:02 PM PDT 24
Peak memory 215960 kb
Host smart-65676d83-f4a4-4314-9912-0b6bd9f6a3eb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2520347672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2520347672
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.1852661565
Short name T1
Test name
Test status
Simulation time 197482477 ps
CPU time 0.84 seconds
Started Aug 06 08:04:44 PM PDT 24
Finished Aug 06 08:04:45 PM PDT 24
Peak memory 207376 kb
Host smart-cedff766-b704-461c-910e-020933327301
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1852661565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1852661565
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.89615743
Short name T2788
Test name
Test status
Simulation time 145962271 ps
CPU time 0.81 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:49 PM PDT 24
Peak memory 207400 kb
Host smart-7f2f968d-d7df-4ce2-94c3-89df1bb1dd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89615
743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.89615743
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2827121439
Short name T158
Test name
Test status
Simulation time 190088275 ps
CPU time 0.92 seconds
Started Aug 06 08:04:56 PM PDT 24
Finished Aug 06 08:04:57 PM PDT 24
Peak memory 207444 kb
Host smart-7496b94b-e54f-42f6-b0f5-c6325b4e7828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28271
21439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2827121439
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.4246190189
Short name T1690
Test name
Test status
Simulation time 242219005 ps
CPU time 1.01 seconds
Started Aug 06 08:04:45 PM PDT 24
Finished Aug 06 08:04:47 PM PDT 24
Peak memory 207236 kb
Host smart-545e74d0-7182-4315-ad01-280cf26e5099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42461
90189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.4246190189
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3284991934
Short name T2549
Test name
Test status
Simulation time 186162532 ps
CPU time 0.91 seconds
Started Aug 06 08:04:57 PM PDT 24
Finished Aug 06 08:04:58 PM PDT 24
Peak memory 207444 kb
Host smart-5865e303-0b5e-41fe-9d54-de446177b69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32849
91934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3284991934
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.3595219038
Short name T1279
Test name
Test status
Simulation time 240166797 ps
CPU time 0.93 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:49 PM PDT 24
Peak memory 207392 kb
Host smart-95b88db4-ddd0-476c-98b7-60d512db7e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35952
19038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.3595219038
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1622058399
Short name T838
Test name
Test status
Simulation time 149213926 ps
CPU time 0.88 seconds
Started Aug 06 08:04:51 PM PDT 24
Finished Aug 06 08:04:52 PM PDT 24
Peak memory 207216 kb
Host smart-df2a1521-bcbe-4cdb-a619-f7671be4bedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16220
58399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1622058399
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3295442799
Short name T2151
Test name
Test status
Simulation time 256686594 ps
CPU time 1.08 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207348 kb
Host smart-89d36577-d3e1-4fda-a78b-0d3ddfed91d4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3295442799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3295442799
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2804210856
Short name T790
Test name
Test status
Simulation time 144883603 ps
CPU time 0.86 seconds
Started Aug 06 08:04:52 PM PDT 24
Finished Aug 06 08:04:52 PM PDT 24
Peak memory 207344 kb
Host smart-b7cf6aa6-589b-45d5-af9d-e6a23dcebf69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28042
10856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2804210856
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3381709644
Short name T1932
Test name
Test status
Simulation time 37852225 ps
CPU time 0.68 seconds
Started Aug 06 08:04:51 PM PDT 24
Finished Aug 06 08:04:52 PM PDT 24
Peak memory 207288 kb
Host smart-80555f8b-6551-4084-8a69-c40f9a503ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33817
09644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3381709644
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1720257953
Short name T1560
Test name
Test status
Simulation time 17160859106 ps
CPU time 43.38 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:05:38 PM PDT 24
Peak memory 215856 kb
Host smart-f77d4ef7-c635-4aa6-892d-d0487f64bc0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17202
57953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1720257953
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.827844609
Short name T497
Test name
Test status
Simulation time 264673231 ps
CPU time 1.05 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207200 kb
Host smart-7e1f92da-448d-4cd0-96eb-f490df4ad3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82784
4609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.827844609
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2586900193
Short name T2102
Test name
Test status
Simulation time 225030894 ps
CPU time 0.95 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207336 kb
Host smart-99ebc7b4-e8d1-401f-b9a2-047a02cce033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25869
00193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2586900193
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2770092116
Short name T1622
Test name
Test status
Simulation time 159772165 ps
CPU time 0.97 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:04:56 PM PDT 24
Peak memory 207352 kb
Host smart-740f0134-6d31-4efc-88e5-fc9dec4b269d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27700
92116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2770092116
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.477480524
Short name T2698
Test name
Test status
Simulation time 176300161 ps
CPU time 0.88 seconds
Started Aug 06 08:05:03 PM PDT 24
Finished Aug 06 08:05:04 PM PDT 24
Peak memory 207444 kb
Host smart-5de42621-a1e7-4e98-a6f0-382079172394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47748
0524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.477480524
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_resume_link_active.3578591687
Short name T2140
Test name
Test status
Simulation time 20170159870 ps
CPU time 24 seconds
Started Aug 06 08:04:46 PM PDT 24
Finished Aug 06 08:05:10 PM PDT 24
Peak memory 207384 kb
Host smart-79d5b07a-424c-4f44-92bc-8e7a78261fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35785
91687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.3578591687
Directory /workspace/19.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.654909014
Short name T632
Test name
Test status
Simulation time 145570517 ps
CPU time 0.89 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:04:56 PM PDT 24
Peak memory 207332 kb
Host smart-8a5f289c-545c-4b5c-9967-6803eda0765c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65490
9014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.654909014
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_rx_full.2824978206
Short name T2248
Test name
Test status
Simulation time 257967543 ps
CPU time 1.08 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:04:56 PM PDT 24
Peak memory 207344 kb
Host smart-9ef9ab03-ce1e-446a-8861-ae3d49eaa123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28249
78206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.2824978206
Directory /workspace/19.usbdev_rx_full/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.784758887
Short name T2618
Test name
Test status
Simulation time 159679911 ps
CPU time 0.86 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:49 PM PDT 24
Peak memory 207320 kb
Host smart-9dc0ece9-4be1-4720-8ae3-9709b523a5b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78475
8887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.784758887
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.422824072
Short name T656
Test name
Test status
Simulation time 174558347 ps
CPU time 0.87 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:04:56 PM PDT 24
Peak memory 207352 kb
Host smart-1e8ff328-5b85-45ba-9d41-365de927a0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42282
4072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.422824072
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.230941411
Short name T1596
Test name
Test status
Simulation time 259396441 ps
CPU time 1.07 seconds
Started Aug 06 08:04:50 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 207288 kb
Host smart-0144f6f7-3e4f-4cda-9f52-e80ec6fde337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23094
1411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.230941411
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3441537349
Short name T2802
Test name
Test status
Simulation time 3476895574 ps
CPU time 26.37 seconds
Started Aug 06 08:04:51 PM PDT 24
Finished Aug 06 08:05:17 PM PDT 24
Peak memory 215888 kb
Host smart-e4da97a3-f004-4c73-81f9-4766e413bf98
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3441537349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3441537349
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.673768686
Short name T2602
Test name
Test status
Simulation time 182781122 ps
CPU time 0.88 seconds
Started Aug 06 08:04:52 PM PDT 24
Finished Aug 06 08:04:53 PM PDT 24
Peak memory 207312 kb
Host smart-9df3db17-766a-49b6-b90f-01da910628d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67376
8686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.673768686
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.4205665650
Short name T1700
Test name
Test status
Simulation time 229399458 ps
CPU time 0.89 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:55 PM PDT 24
Peak memory 207352 kb
Host smart-74dd74c7-302f-43a5-b0d7-e741d80ab7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42056
65650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.4205665650
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.2604406235
Short name T934
Test name
Test status
Simulation time 450629653 ps
CPU time 1.44 seconds
Started Aug 06 08:04:52 PM PDT 24
Finished Aug 06 08:04:54 PM PDT 24
Peak memory 207304 kb
Host smart-08a0c57f-9934-4322-90ab-69cbbffce90f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26044
06235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.2604406235
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.4288774971
Short name T677
Test name
Test status
Simulation time 4000621297 ps
CPU time 41.48 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:05:31 PM PDT 24
Peak memory 217364 kb
Host smart-ff493d1e-ac11-4b44-952d-3a9038c7fe48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42887
74971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.4288774971
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.1378009945
Short name T2324
Test name
Test status
Simulation time 1443604618 ps
CPU time 31.55 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:05:20 PM PDT 24
Peak memory 207528 kb
Host smart-8ac1ac44-7875-4ce0-9c78-f40c2175abe2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378009945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.1378009945
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/191.usbdev_endpoint_types.1454253302
Short name T424
Test name
Test status
Simulation time 256800077 ps
CPU time 1.07 seconds
Started Aug 06 08:09:32 PM PDT 24
Finished Aug 06 08:09:33 PM PDT 24
Peak memory 207292 kb
Host smart-c410e79c-6df4-4f8a-bbe0-87522c433c96
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1454253302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.1454253302
Directory /workspace/191.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/192.usbdev_endpoint_types.4140221141
Short name T446
Test name
Test status
Simulation time 428475026 ps
CPU time 1.38 seconds
Started Aug 06 08:09:39 PM PDT 24
Finished Aug 06 08:09:40 PM PDT 24
Peak memory 207296 kb
Host smart-ab691f1e-8473-467c-9c83-102fa6cefe47
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4140221141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.4140221141
Directory /workspace/192.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/193.usbdev_endpoint_types.2709369880
Short name T371
Test name
Test status
Simulation time 267313988 ps
CPU time 1.05 seconds
Started Aug 06 08:09:22 PM PDT 24
Finished Aug 06 08:09:23 PM PDT 24
Peak memory 207568 kb
Host smart-872c3c09-5f23-4f9a-acb8-dfddd2c2bfdc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2709369880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.2709369880
Directory /workspace/193.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/194.usbdev_endpoint_types.461574553
Short name T2195
Test name
Test status
Simulation time 478846891 ps
CPU time 1.39 seconds
Started Aug 06 08:09:25 PM PDT 24
Finished Aug 06 08:09:26 PM PDT 24
Peak memory 207348 kb
Host smart-a8c90754-56b7-49be-bc19-7e1271f68585
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=461574553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.461574553
Directory /workspace/194.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/195.usbdev_endpoint_types.297422283
Short name T455
Test name
Test status
Simulation time 213824282 ps
CPU time 0.98 seconds
Started Aug 06 08:09:35 PM PDT 24
Finished Aug 06 08:09:36 PM PDT 24
Peak memory 207296 kb
Host smart-5142e843-001d-413f-949e-5b07e2b6a07c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=297422283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.297422283
Directory /workspace/195.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/196.usbdev_endpoint_types.1938455926
Short name T447
Test name
Test status
Simulation time 392733224 ps
CPU time 1.21 seconds
Started Aug 06 08:09:24 PM PDT 24
Finished Aug 06 08:09:25 PM PDT 24
Peak memory 206892 kb
Host smart-d24d6cfc-a5d1-427e-b5aa-3aab952f0b6a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1938455926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.1938455926
Directory /workspace/196.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/197.usbdev_endpoint_types.4124238486
Short name T87
Test name
Test status
Simulation time 805673896 ps
CPU time 1.71 seconds
Started Aug 06 08:09:25 PM PDT 24
Finished Aug 06 08:09:27 PM PDT 24
Peak memory 207352 kb
Host smart-8cd00cff-b43a-4389-ad6c-2885cb4f6c35
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4124238486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.4124238486
Directory /workspace/197.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/198.usbdev_endpoint_types.382570386
Short name T352
Test name
Test status
Simulation time 771132967 ps
CPU time 1.82 seconds
Started Aug 06 08:09:36 PM PDT 24
Finished Aug 06 08:09:38 PM PDT 24
Peak memory 207344 kb
Host smart-6a398f10-7570-4a68-8991-cb31ae0b8518
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=382570386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.382570386
Directory /workspace/198.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/199.usbdev_endpoint_types.2950836030
Short name T2665
Test name
Test status
Simulation time 397041713 ps
CPU time 1.21 seconds
Started Aug 06 08:09:36 PM PDT 24
Finished Aug 06 08:09:38 PM PDT 24
Peak memory 207380 kb
Host smart-ff1bf92b-a3e4-475e-8faa-74010f10dc86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2950836030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.2950836030
Directory /workspace/199.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.1633294407
Short name T1403
Test name
Test status
Simulation time 39935365 ps
CPU time 0.69 seconds
Started Aug 06 08:01:55 PM PDT 24
Finished Aug 06 08:01:55 PM PDT 24
Peak memory 207380 kb
Host smart-1e6969da-98b4-4e82-9dc5-c071ec49a827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1633294407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.1633294407
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.4187525956
Short name T1122
Test name
Test status
Simulation time 4707614780 ps
CPU time 6.58 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:01:49 PM PDT 24
Peak memory 215768 kb
Host smart-49577357-e923-4b8a-878e-f5616d69d6dd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187525956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.4187525956
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1594753756
Short name T1438
Test name
Test status
Simulation time 20350749698 ps
CPU time 23.12 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:02:03 PM PDT 24
Peak memory 207632 kb
Host smart-b0c0cb58-886c-418b-942c-2aca45f7c3e5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594753756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1594753756
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.3681246568
Short name T1941
Test name
Test status
Simulation time 31383146630 ps
CPU time 45.08 seconds
Started Aug 06 08:01:39 PM PDT 24
Finished Aug 06 08:02:24 PM PDT 24
Peak memory 207620 kb
Host smart-dc7d5de0-78dd-41c4-a9ad-f8be8c49b563
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681246568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.3681246568
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2445859496
Short name T3124
Test name
Test status
Simulation time 181249329 ps
CPU time 0.88 seconds
Started Aug 06 08:01:42 PM PDT 24
Finished Aug 06 08:01:43 PM PDT 24
Peak memory 207364 kb
Host smart-d57fa5de-ffb8-43f1-8eb0-5078e3587987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24458
59496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2445859496
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.3046654136
Short name T2761
Test name
Test status
Simulation time 168472618 ps
CPU time 0.84 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:01:42 PM PDT 24
Peak memory 207348 kb
Host smart-98b8f309-d5a0-4a34-9db8-137b3884bfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30466
54136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.3046654136
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2233471358
Short name T1377
Test name
Test status
Simulation time 153131920 ps
CPU time 0.82 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:01:42 PM PDT 24
Peak memory 207344 kb
Host smart-d200f42b-6075-439c-bff4-1733327dbd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22334
71358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2233471358
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.2275991598
Short name T2469
Test name
Test status
Simulation time 251224971 ps
CPU time 1.04 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:01:42 PM PDT 24
Peak memory 207384 kb
Host smart-2a1625fd-df83-4de9-b8ae-22147b8fbd30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22759
91598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.2275991598
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2857302271
Short name T2535
Test name
Test status
Simulation time 582655835 ps
CPU time 1.69 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:01:45 PM PDT 24
Peak memory 207320 kb
Host smart-76d88b6c-bd75-431e-b745-7c02cabf2917
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2857302271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2857302271
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.4068301724
Short name T1084
Test name
Test status
Simulation time 43674620540 ps
CPU time 70.7 seconds
Started Aug 06 08:01:38 PM PDT 24
Finished Aug 06 08:02:49 PM PDT 24
Peak memory 207600 kb
Host smart-058055db-033d-49f9-b5dc-a7472160d6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40683
01724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.4068301724
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.768601791
Short name T623
Test name
Test status
Simulation time 3884650418 ps
CPU time 34.15 seconds
Started Aug 06 08:01:42 PM PDT 24
Finished Aug 06 08:02:16 PM PDT 24
Peak memory 207608 kb
Host smart-0f7973d6-c7a2-405c-a4ed-37431fc004b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768601791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.768601791
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1618003772
Short name T1616
Test name
Test status
Simulation time 874044695 ps
CPU time 2.08 seconds
Started Aug 06 08:01:38 PM PDT 24
Finished Aug 06 08:01:40 PM PDT 24
Peak memory 207388 kb
Host smart-801a207e-2da8-4f89-b66b-0bf8549e8f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16180
03772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1618003772
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2118617874
Short name T1900
Test name
Test status
Simulation time 136528573 ps
CPU time 0.83 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:01:42 PM PDT 24
Peak memory 207320 kb
Host smart-cd8e31a5-dc18-4c8c-b90e-a3d5cc8c11b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21186
17874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2118617874
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.877526999
Short name T1685
Test name
Test status
Simulation time 64967120 ps
CPU time 0.73 seconds
Started Aug 06 08:01:45 PM PDT 24
Finished Aug 06 08:01:45 PM PDT 24
Peak memory 207320 kb
Host smart-cd97acb8-bdc2-4426-896e-58e7ebd750d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87752
6999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.877526999
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3874710263
Short name T1881
Test name
Test status
Simulation time 728321923 ps
CPU time 2.13 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 207564 kb
Host smart-b552c81a-f5ac-45c9-8c6f-885ae991cc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38747
10263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3874710263
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_types.3308822677
Short name T450
Test name
Test status
Simulation time 420558230 ps
CPU time 1.27 seconds
Started Aug 06 08:01:42 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 207388 kb
Host smart-0ca169f3-c649-4449-91bf-ebe893ea92c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3308822677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.3308822677
Directory /workspace/2.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2811492714
Short name T840
Test name
Test status
Simulation time 310458715 ps
CPU time 2.75 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:01:43 PM PDT 24
Peak memory 207544 kb
Host smart-5617eb87-1227-4894-8272-8302db01a68d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28114
92714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2811492714
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.150950143
Short name T1098
Test name
Test status
Simulation time 83243799400 ps
CPU time 122 seconds
Started Aug 06 08:01:42 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 207636 kb
Host smart-1697c58a-9bc1-47d6-b90b-acf98416d5aa
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=150950143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.150950143
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1202039477
Short name T787
Test name
Test status
Simulation time 105285679920 ps
CPU time 188.81 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:04:52 PM PDT 24
Peak memory 207628 kb
Host smart-3c8e476d-89bf-4af0-acec-ee0a03073c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202039477 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1202039477
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.4216379018
Short name T1506
Test name
Test status
Simulation time 109104912109 ps
CPU time 171.2 seconds
Started Aug 06 08:01:39 PM PDT 24
Finished Aug 06 08:04:30 PM PDT 24
Peak memory 207628 kb
Host smart-04931ea3-43db-4378-97c2-3fa1c67d22ea
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4216379018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.4216379018
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.2824791271
Short name T1245
Test name
Test status
Simulation time 97945116637 ps
CPU time 154.12 seconds
Started Aug 06 08:01:42 PM PDT 24
Finished Aug 06 08:04:16 PM PDT 24
Peak memory 207700 kb
Host smart-b2b8345c-e17c-418b-b817-c3982121767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824791271 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.2824791271
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.48565704
Short name T334
Test name
Test status
Simulation time 106151991144 ps
CPU time 170.57 seconds
Started Aug 06 08:01:39 PM PDT 24
Finished Aug 06 08:04:30 PM PDT 24
Peak memory 207672 kb
Host smart-0fa37a69-1160-44b7-88a6-806e39836627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48565
704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.48565704
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.806237804
Short name T2213
Test name
Test status
Simulation time 220412323 ps
CPU time 1.13 seconds
Started Aug 06 08:01:39 PM PDT 24
Finished Aug 06 08:01:41 PM PDT 24
Peak memory 207476 kb
Host smart-236491c8-375a-4617-81b8-8199ad6a61ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=806237804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.806237804
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1246528286
Short name T247
Test name
Test status
Simulation time 151018814 ps
CPU time 0.81 seconds
Started Aug 06 08:01:39 PM PDT 24
Finished Aug 06 08:01:40 PM PDT 24
Peak memory 207352 kb
Host smart-6bb5b29f-0603-4945-aebb-8b23435bb7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12465
28286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1246528286
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3077053101
Short name T1090
Test name
Test status
Simulation time 174541671 ps
CPU time 0.93 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 207340 kb
Host smart-f3681859-8625-4897-ab7a-919377db0e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30770
53101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3077053101
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.327256049
Short name T778
Test name
Test status
Simulation time 3038338291 ps
CPU time 32.15 seconds
Started Aug 06 08:01:39 PM PDT 24
Finished Aug 06 08:02:11 PM PDT 24
Peak memory 224012 kb
Host smart-9f06f9f4-d8da-4e4e-a038-d895e18a16c7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=327256049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.327256049
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.1525134505
Short name T1490
Test name
Test status
Simulation time 6219056387 ps
CPU time 41.63 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:02:22 PM PDT 24
Peak memory 207664 kb
Host smart-bb1023d0-d0c7-410a-bff6-a326e54bdaad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1525134505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.1525134505
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1688688734
Short name T2304
Test name
Test status
Simulation time 210901213 ps
CPU time 1.04 seconds
Started Aug 06 08:01:38 PM PDT 24
Finished Aug 06 08:01:39 PM PDT 24
Peak memory 207596 kb
Host smart-a7b7356d-fae3-4f35-8645-bfd8abfe7b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16886
88734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1688688734
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.3055196071
Short name T2396
Test name
Test status
Simulation time 29495289730 ps
CPU time 44.67 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:02:26 PM PDT 24
Peak memory 207636 kb
Host smart-421c1b88-478f-4fd4-8e4c-ca431a16f8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30551
96071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3055196071
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3891401647
Short name T1212
Test name
Test status
Simulation time 11277454438 ps
CPU time 13.52 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:01:57 PM PDT 24
Peak memory 207612 kb
Host smart-cdf34595-4f1b-41c3-b775-9c6554116472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38914
01647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3891401647
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.1261225167
Short name T2507
Test name
Test status
Simulation time 3673509957 ps
CPU time 26.26 seconds
Started Aug 06 08:01:38 PM PDT 24
Finished Aug 06 08:02:05 PM PDT 24
Peak memory 224044 kb
Host smart-c9a8a2e7-e731-43c4-9910-2023d1253570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12612
25167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.1261225167
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3867550486
Short name T1379
Test name
Test status
Simulation time 2604626099 ps
CPU time 25.93 seconds
Started Aug 06 08:01:39 PM PDT 24
Finished Aug 06 08:02:06 PM PDT 24
Peak memory 217572 kb
Host smart-7d8cdcc7-c4e6-4797-a17c-3e5695b88edf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3867550486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3867550486
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.2897966438
Short name T1826
Test name
Test status
Simulation time 237916802 ps
CPU time 0.98 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:01:41 PM PDT 24
Peak memory 207316 kb
Host smart-0fb6c0a6-b311-4bf2-88b9-b7200e2cb73f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2897966438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.2897966438
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1365605441
Short name T991
Test name
Test status
Simulation time 220592556 ps
CPU time 1.01 seconds
Started Aug 06 08:01:38 PM PDT 24
Finished Aug 06 08:01:39 PM PDT 24
Peak memory 207324 kb
Host smart-3c09552e-6cc9-4127-a9ca-ef84cd0e2edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13656
05441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1365605441
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.3468639951
Short name T2629
Test name
Test status
Simulation time 2388852863 ps
CPU time 66.4 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:02:46 PM PDT 24
Peak memory 224064 kb
Host smart-3f9ee505-2f67-4c24-b1eb-d8c7b66da649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34686
39951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.3468639951
Directory /workspace/2.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.111389080
Short name T2888
Test name
Test status
Simulation time 3172091693 ps
CPU time 98.19 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:03:22 PM PDT 24
Peak memory 215804 kb
Host smart-a9964012-aa1d-4c2e-82af-6ccf12c8fe89
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=111389080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.111389080
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.669325927
Short name T2256
Test name
Test status
Simulation time 2748414330 ps
CPU time 80.48 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:03:01 PM PDT 24
Peak memory 217556 kb
Host smart-ca8dfc33-f881-4e28-83dc-101d3e807bc5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=669325927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.669325927
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.109831463
Short name T2769
Test name
Test status
Simulation time 198884084 ps
CPU time 0.9 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:01:42 PM PDT 24
Peak memory 207364 kb
Host smart-27ab2407-85aa-4c39-9ceb-9eb8b04fa502
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=109831463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.109831463
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1755972614
Short name T1177
Test name
Test status
Simulation time 184892099 ps
CPU time 0.9 seconds
Started Aug 06 08:01:44 PM PDT 24
Finished Aug 06 08:01:45 PM PDT 24
Peak memory 207380 kb
Host smart-ca832ad5-6f38-4bf0-898e-c529e6e050ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17559
72614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1755972614
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2428684182
Short name T2478
Test name
Test status
Simulation time 154629553 ps
CPU time 0.93 seconds
Started Aug 06 08:01:44 PM PDT 24
Finished Aug 06 08:01:45 PM PDT 24
Peak memory 207344 kb
Host smart-1f69c941-d2e0-4e5d-a380-83fc1afccb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24286
84182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2428684182
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.887149225
Short name T881
Test name
Test status
Simulation time 161093326 ps
CPU time 0.89 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:01:42 PM PDT 24
Peak memory 207372 kb
Host smart-365add10-e3c5-4279-a3f4-2994a9209172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88714
9225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.887149225
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3762690245
Short name T598
Test name
Test status
Simulation time 195239611 ps
CPU time 0.85 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:01:41 PM PDT 24
Peak memory 207448 kb
Host smart-c00e9d7f-2938-4f2f-afb5-bb728bb8ce83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37626
90245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3762690245
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.4060961001
Short name T2963
Test name
Test status
Simulation time 180315156 ps
CPU time 0.85 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:01:42 PM PDT 24
Peak memory 207376 kb
Host smart-067c3f9b-b39a-41be-9e58-1f3b86ae2be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40609
61001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.4060961001
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.865909429
Short name T1071
Test name
Test status
Simulation time 263425863 ps
CPU time 1.07 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:01:41 PM PDT 24
Peak memory 207392 kb
Host smart-3ffdde63-ae2a-4f9c-8c21-61cd941fdb9f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=865909429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.865909429
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1120307601
Short name T452
Test name
Test status
Simulation time 210841102 ps
CPU time 0.97 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 207348 kb
Host smart-ff3ecc35-f39f-4369-b615-caea87396b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11203
07601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1120307601
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1847822169
Short name T2882
Test name
Test status
Simulation time 152278357 ps
CPU time 0.84 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:01:41 PM PDT 24
Peak memory 207368 kb
Host smart-2389ede1-63cd-4b5e-9a13-2239b7a9d9fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18478
22169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1847822169
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.231996460
Short name T39
Test name
Test status
Simulation time 61230075 ps
CPU time 0.72 seconds
Started Aug 06 08:01:39 PM PDT 24
Finished Aug 06 08:01:40 PM PDT 24
Peak memory 207312 kb
Host smart-4420b389-c41c-401c-aa7e-ee8ba76cd02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23199
6460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.231996460
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1352142093
Short name T307
Test name
Test status
Simulation time 16462328199 ps
CPU time 38.37 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:02:19 PM PDT 24
Peak memory 215888 kb
Host smart-6ce39f01-c278-40f5-ab11-8e5aad52b2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13521
42093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1352142093
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.2236066195
Short name T1628
Test name
Test status
Simulation time 156993053 ps
CPU time 0.88 seconds
Started Aug 06 08:01:41 PM PDT 24
Finished Aug 06 08:01:42 PM PDT 24
Peak memory 207376 kb
Host smart-c38eb3dc-fda6-40bd-a07d-6819a79e319f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22360
66195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2236066195
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3557912617
Short name T1581
Test name
Test status
Simulation time 253263848 ps
CPU time 1.16 seconds
Started Aug 06 08:01:44 PM PDT 24
Finished Aug 06 08:01:45 PM PDT 24
Peak memory 207340 kb
Host smart-4b232716-f4d1-4045-b27a-a3ec562b030e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35579
12617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3557912617
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.2838557837
Short name T2793
Test name
Test status
Simulation time 7773651898 ps
CPU time 53.2 seconds
Started Aug 06 08:01:42 PM PDT 24
Finished Aug 06 08:02:36 PM PDT 24
Peak memory 215884 kb
Host smart-f5997d2e-8e0f-4014-8a98-60a436a31c36
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838557837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.2838557837
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3630136382
Short name T2667
Test name
Test status
Simulation time 5925880719 ps
CPU time 23.11 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:02:03 PM PDT 24
Peak memory 224020 kb
Host smart-2abbed45-09b0-49e7-984c-d9b46ca6d1ce
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3630136382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3630136382
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3552050025
Short name T1330
Test name
Test status
Simulation time 6376903861 ps
CPU time 27.13 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:02:10 PM PDT 24
Peak memory 224032 kb
Host smart-f9d97418-1bc4-4244-ad0e-d608a541fcc7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552050025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3552050025
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3799187909
Short name T777
Test name
Test status
Simulation time 193810858 ps
CPU time 0.98 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 207336 kb
Host smart-132acacd-7e38-47b0-aff8-dd48f7dfde3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37991
87909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3799187909
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.848032515
Short name T1839
Test name
Test status
Simulation time 156300778 ps
CPU time 0.88 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:01:41 PM PDT 24
Peak memory 207352 kb
Host smart-e167dd4e-baf5-4b1c-aa69-20b251121bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84803
2515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.848032515
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_resume_link_active.3651694346
Short name T1553
Test name
Test status
Simulation time 20167772316 ps
CPU time 24.59 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:02:04 PM PDT 24
Peak memory 207440 kb
Host smart-512eb8da-a459-4f69-9226-9740b64d485c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36516
94346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.3651694346
Directory /workspace/2.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.2076207660
Short name T2712
Test name
Test status
Simulation time 178110407 ps
CPU time 0.87 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:01:41 PM PDT 24
Peak memory 207356 kb
Host smart-ae059c25-46ef-4986-a4ac-d063fc1f2e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20762
07660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.2076207660
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.3283739848
Short name T77
Test name
Test status
Simulation time 138053010 ps
CPU time 0.82 seconds
Started Aug 06 08:01:44 PM PDT 24
Finished Aug 06 08:01:45 PM PDT 24
Peak memory 207340 kb
Host smart-f2bb58ce-9f93-41dd-9b9c-1308f0dea219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32837
39848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.3283739848
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.355225396
Short name T238
Test name
Test status
Simulation time 582748125 ps
CPU time 1.51 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:01:59 PM PDT 24
Peak memory 224416 kb
Host smart-d4debfc0-4512-45d8-88aa-ba3243eec136
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=355225396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.355225396
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.113650340
Short name T54
Test name
Test status
Simulation time 418639291 ps
CPU time 1.52 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 207012 kb
Host smart-16a5486d-b2fc-4683-85f4-083be0cd3ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11365
0340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.113650340
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3126667549
Short name T918
Test name
Test status
Simulation time 306148973 ps
CPU time 1.14 seconds
Started Aug 06 08:01:45 PM PDT 24
Finished Aug 06 08:01:46 PM PDT 24
Peak memory 207356 kb
Host smart-5e5f5749-0811-42f0-9236-c1c6ffb14195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31266
67549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3126667549
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.589442600
Short name T2552
Test name
Test status
Simulation time 164574749 ps
CPU time 0.84 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 207304 kb
Host smart-629f3966-351a-4b76-8f4a-9e0485123216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58944
2600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.589442600
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.386069585
Short name T1253
Test name
Test status
Simulation time 145593785 ps
CPU time 0.85 seconds
Started Aug 06 08:01:44 PM PDT 24
Finished Aug 06 08:01:45 PM PDT 24
Peak memory 207328 kb
Host smart-1b40be03-e093-4c14-8603-990c541e749e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38606
9585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.386069585
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2307819051
Short name T1615
Test name
Test status
Simulation time 233793958 ps
CPU time 1.09 seconds
Started Aug 06 08:01:42 PM PDT 24
Finished Aug 06 08:01:43 PM PDT 24
Peak memory 207308 kb
Host smart-14ab2756-05ff-4091-b276-8a21940493d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23078
19051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2307819051
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1315508997
Short name T1194
Test name
Test status
Simulation time 2621527208 ps
CPU time 24.47 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:02:04 PM PDT 24
Peak memory 217884 kb
Host smart-f4be08a2-cf25-4191-8964-fd735cc1656f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1315508997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1315508997
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.13723395
Short name T2737
Test name
Test status
Simulation time 176176690 ps
CPU time 0.87 seconds
Started Aug 06 08:01:42 PM PDT 24
Finished Aug 06 08:01:43 PM PDT 24
Peak memory 207348 kb
Host smart-5f7e38ed-0c2d-4812-91bd-1601b2aedfea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13723
395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.13723395
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2116774637
Short name T2312
Test name
Test status
Simulation time 216282780 ps
CPU time 1.01 seconds
Started Aug 06 08:01:40 PM PDT 24
Finished Aug 06 08:01:41 PM PDT 24
Peak memory 207332 kb
Host smart-48ddf9b9-a103-437a-a435-4f52ed9f4429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21167
74637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2116774637
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.1826774429
Short name T2100
Test name
Test status
Simulation time 569995600 ps
CPU time 1.73 seconds
Started Aug 06 08:01:43 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 207292 kb
Host smart-58bfb112-3aa3-4141-a0a4-190ceb8639f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18267
74429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.1826774429
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.938438789
Short name T181
Test name
Test status
Simulation time 2382285178 ps
CPU time 23.67 seconds
Started Aug 06 08:01:42 PM PDT 24
Finished Aug 06 08:02:05 PM PDT 24
Peak memory 217500 kb
Host smart-d3ef4329-4339-4d45-a2cd-6e7eb210b4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93843
8789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.938438789
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.3331435347
Short name T2371
Test name
Test status
Simulation time 5648393984 ps
CPU time 36.15 seconds
Started Aug 06 08:01:39 PM PDT 24
Finished Aug 06 08:02:15 PM PDT 24
Peak memory 207736 kb
Host smart-0309b22f-f6fe-49bf-b12d-4243e8a511b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331435347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.3331435347
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.4166346859
Short name T15
Test name
Test status
Simulation time 19705789457 ps
CPU time 20.71 seconds
Started Aug 06 08:04:45 PM PDT 24
Finished Aug 06 08:05:06 PM PDT 24
Peak memory 207580 kb
Host smart-524f68fc-c0e5-4cc8-ab0e-7a057e334497
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166346859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.4166346859
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1921265748
Short name T2547
Test name
Test status
Simulation time 29551832791 ps
CPU time 32.26 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:05:21 PM PDT 24
Peak memory 207652 kb
Host smart-175ba61f-18c9-48f2-a9e1-ab29d926633d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921265748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.1921265748
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3758284943
Short name T512
Test name
Test status
Simulation time 200029069 ps
CPU time 0.91 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207416 kb
Host smart-afc61660-7dad-4bcd-89c0-9fd50f8c6c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37582
84943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3758284943
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.2253525711
Short name T2052
Test name
Test status
Simulation time 159658353 ps
CPU time 0.85 seconds
Started Aug 06 08:04:46 PM PDT 24
Finished Aug 06 08:04:47 PM PDT 24
Peak memory 207348 kb
Host smart-8c827eed-4e95-4864-9b7a-64a0b784baef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22535
25711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.2253525711
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3095693649
Short name T1513
Test name
Test status
Simulation time 464821377 ps
CPU time 1.62 seconds
Started Aug 06 08:04:50 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 207332 kb
Host smart-b648943f-87f6-40a2-84f4-98e0340bfe91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30956
93649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3095693649
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.3440359971
Short name T2061
Test name
Test status
Simulation time 908672338 ps
CPU time 2.62 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 207664 kb
Host smart-d6e70dde-0801-46c0-aea8-156087afbc30
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3440359971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.3440359971
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3484846829
Short name T189
Test name
Test status
Simulation time 51853301452 ps
CPU time 84.94 seconds
Started Aug 06 08:04:51 PM PDT 24
Finished Aug 06 08:06:16 PM PDT 24
Peak memory 207640 kb
Host smart-8ced83e5-f75f-4511-b653-2d827cc45c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34848
46829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3484846829
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.2574259048
Short name T1695
Test name
Test status
Simulation time 159532710 ps
CPU time 0.85 seconds
Started Aug 06 08:04:46 PM PDT 24
Finished Aug 06 08:04:47 PM PDT 24
Peak memory 207260 kb
Host smart-b341673b-c833-49a4-aa40-58cd86d75b18
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574259048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.2574259048
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3912757846
Short name T1494
Test name
Test status
Simulation time 950715590 ps
CPU time 2.25 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 207384 kb
Host smart-7eefbf6f-244d-47f7-9725-52c6cd98abbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39127
57846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3912757846
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.347401896
Short name T1788
Test name
Test status
Simulation time 156959596 ps
CPU time 0.84 seconds
Started Aug 06 08:04:51 PM PDT 24
Finished Aug 06 08:04:52 PM PDT 24
Peak memory 207340 kb
Host smart-6e273ea6-c115-4899-a3e5-1a536beb47a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34740
1896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.347401896
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.2978208614
Short name T553
Test name
Test status
Simulation time 89008827 ps
CPU time 0.73 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:49 PM PDT 24
Peak memory 207364 kb
Host smart-f7f5aa64-8bb9-4103-88ad-0d9b0e5e1368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29782
08614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.2978208614
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3626638638
Short name T648
Test name
Test status
Simulation time 1014961811 ps
CPU time 2.61 seconds
Started Aug 06 08:04:47 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207584 kb
Host smart-dad1736c-d944-4edd-a662-11b5d0abe569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36266
38638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3626638638
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_types.2315130487
Short name T2267
Test name
Test status
Simulation time 422749820 ps
CPU time 1.48 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207308 kb
Host smart-78fcc476-4107-40b1-a13d-a3d141428809
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2315130487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.2315130487
Directory /workspace/20.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1600737878
Short name T751
Test name
Test status
Simulation time 187861672 ps
CPU time 1.7 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207544 kb
Host smart-d784e328-e580-41b7-ab9c-54b180e9aef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16007
37878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1600737878
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2098439316
Short name T1773
Test name
Test status
Simulation time 203226482 ps
CPU time 1 seconds
Started Aug 06 08:04:46 PM PDT 24
Finished Aug 06 08:04:47 PM PDT 24
Peak memory 215712 kb
Host smart-0c4e9700-9390-4ab5-96d6-99850d2e56f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2098439316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2098439316
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3053255898
Short name T685
Test name
Test status
Simulation time 140149685 ps
CPU time 0.86 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207264 kb
Host smart-5670cf95-c82e-4263-ba07-1d062ffe852a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30532
55898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3053255898
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1720105346
Short name T2217
Test name
Test status
Simulation time 185361074 ps
CPU time 0.9 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:49 PM PDT 24
Peak memory 207356 kb
Host smart-c019c483-b1ee-4907-8ec1-1dbdddff0e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17201
05346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1720105346
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.1795092304
Short name T1548
Test name
Test status
Simulation time 4642455779 ps
CPU time 45.26 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:05:34 PM PDT 24
Peak memory 223996 kb
Host smart-dced5ad5-f037-4767-a431-2d2e4465c99e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1795092304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.1795092304
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.818722828
Short name T1242
Test name
Test status
Simulation time 13643316526 ps
CPU time 92.45 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:06:27 PM PDT 24
Peak memory 207620 kb
Host smart-d85dd1de-2a68-4d13-b138-40c1e520ea28
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=818722828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.818722828
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.1026282208
Short name T273
Test name
Test status
Simulation time 222017242 ps
CPU time 0.97 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:49 PM PDT 24
Peak memory 207400 kb
Host smart-4bf47fa6-3473-4218-a88d-3212a7eecefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10262
82208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.1026282208
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.382813224
Short name T1842
Test name
Test status
Simulation time 6692547148 ps
CPU time 10.75 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:05:00 PM PDT 24
Peak memory 215912 kb
Host smart-acf3b96d-266c-4fe0-89fd-637fd1689313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38281
3224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.382813224
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3191741127
Short name T1076
Test name
Test status
Simulation time 8479813617 ps
CPU time 11.29 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:59 PM PDT 24
Peak memory 207628 kb
Host smart-96c4a830-4fe2-464a-b0d9-9c45c875cdf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31917
41127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3191741127
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.2574575959
Short name T2894
Test name
Test status
Simulation time 4643124366 ps
CPU time 127.86 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:06:56 PM PDT 24
Peak memory 218492 kb
Host smart-a78aebc7-c44f-4fbc-a43c-2cfe1d0344d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25745
75959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.2574575959
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2840239000
Short name T2010
Test name
Test status
Simulation time 2695539443 ps
CPU time 73.89 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:06:02 PM PDT 24
Peak memory 223988 kb
Host smart-93ac88b4-373c-4a89-a902-3043a9e07826
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2840239000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2840239000
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.3743517830
Short name T2990
Test name
Test status
Simulation time 250378551 ps
CPU time 0.97 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207324 kb
Host smart-574591e3-9f07-4e47-9779-1d671df0b770
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3743517830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3743517830
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.432269458
Short name T2142
Test name
Test status
Simulation time 183438294 ps
CPU time 0.96 seconds
Started Aug 06 08:04:58 PM PDT 24
Finished Aug 06 08:04:59 PM PDT 24
Peak memory 207316 kb
Host smart-7a08e63a-aee2-4217-bcf0-e4f0ff0f31d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43226
9458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.432269458
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.2911907959
Short name T2855
Test name
Test status
Simulation time 2165222613 ps
CPU time 61.1 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:05:51 PM PDT 24
Peak memory 217452 kb
Host smart-9fe05f95-a90f-4346-abd6-d36db0d84160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29119
07959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.2911907959
Directory /workspace/20.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2187837563
Short name T2499
Test name
Test status
Simulation time 2025340433 ps
CPU time 60.19 seconds
Started Aug 06 08:04:52 PM PDT 24
Finished Aug 06 08:05:52 PM PDT 24
Peak memory 215760 kb
Host smart-a4d3d2cf-dfb8-444a-9ac9-e43c44a633a4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2187837563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2187837563
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1521990078
Short name T1834
Test name
Test status
Simulation time 150898373 ps
CPU time 0.84 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:04:56 PM PDT 24
Peak memory 207368 kb
Host smart-d5f07ed6-ebaa-467c-82c7-b7c5ff81cc30
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1521990078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1521990078
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.911287538
Short name T593
Test name
Test status
Simulation time 169354637 ps
CPU time 0.81 seconds
Started Aug 06 08:04:48 PM PDT 24
Finished Aug 06 08:04:49 PM PDT 24
Peak memory 207372 kb
Host smart-2692521f-0f17-46c4-9b29-b8fe2b35ba82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91128
7538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.911287538
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.4003269344
Short name T152
Test name
Test status
Simulation time 182933782 ps
CPU time 0.87 seconds
Started Aug 06 08:04:49 PM PDT 24
Finished Aug 06 08:04:50 PM PDT 24
Peak memory 207368 kb
Host smart-fda7c2ce-a581-4297-a703-4dc266cba0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40032
69344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.4003269344
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.792734509
Short name T550
Test name
Test status
Simulation time 169982221 ps
CPU time 0.92 seconds
Started Aug 06 08:04:50 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 207368 kb
Host smart-b86b9054-c60e-4dab-9207-85c868f22fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79273
4509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.792734509
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.86161006
Short name T1092
Test name
Test status
Simulation time 258012582 ps
CPU time 0.93 seconds
Started Aug 06 08:04:59 PM PDT 24
Finished Aug 06 08:05:00 PM PDT 24
Peak memory 207416 kb
Host smart-adcb38c4-f6e0-442e-ac3d-63370c862d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86161
006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.86161006
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1698727081
Short name T1930
Test name
Test status
Simulation time 169491602 ps
CPU time 0.87 seconds
Started Aug 06 08:05:00 PM PDT 24
Finished Aug 06 08:05:01 PM PDT 24
Peak memory 207324 kb
Host smart-690867b9-356d-4894-82cf-05a621d0e2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16987
27081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1698727081
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1250644489
Short name T2157
Test name
Test status
Simulation time 167557424 ps
CPU time 0.82 seconds
Started Aug 06 08:05:02 PM PDT 24
Finished Aug 06 08:05:03 PM PDT 24
Peak memory 207392 kb
Host smart-0f940e8b-c92f-412c-a724-5895d4419c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12506
44489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1250644489
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.4269760915
Short name T2758
Test name
Test status
Simulation time 189922417 ps
CPU time 0.95 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:04:56 PM PDT 24
Peak memory 207404 kb
Host smart-94733f84-4254-4cf4-bb24-2e0da6f5a8cf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4269760915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.4269760915
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3831622881
Short name T942
Test name
Test status
Simulation time 142631039 ps
CPU time 0.82 seconds
Started Aug 06 08:05:07 PM PDT 24
Finished Aug 06 08:05:08 PM PDT 24
Peak memory 207284 kb
Host smart-e0778b44-758a-4455-bb03-f886441ce804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38316
22881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3831622881
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3299329800
Short name T977
Test name
Test status
Simulation time 54605452 ps
CPU time 0.76 seconds
Started Aug 06 08:05:01 PM PDT 24
Finished Aug 06 08:05:02 PM PDT 24
Peak memory 207252 kb
Host smart-94a4be6d-c5ad-4ce0-9b19-42a7c50d9274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32993
29800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3299329800
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3252295266
Short name T2842
Test name
Test status
Simulation time 15643728603 ps
CPU time 41.85 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:05:37 PM PDT 24
Peak memory 224044 kb
Host smart-0775a199-8d2f-4e3e-9239-db439bec37cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32522
95266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3252295266
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2243354705
Short name T2288
Test name
Test status
Simulation time 175190159 ps
CPU time 0.89 seconds
Started Aug 06 08:05:03 PM PDT 24
Finished Aug 06 08:05:03 PM PDT 24
Peak memory 207320 kb
Host smart-946da4bb-dcd5-4466-956c-cde9e43a54b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22433
54705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2243354705
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3506799957
Short name T2683
Test name
Test status
Simulation time 159071578 ps
CPU time 0.87 seconds
Started Aug 06 08:05:07 PM PDT 24
Finished Aug 06 08:05:08 PM PDT 24
Peak memory 207436 kb
Host smart-10f2518c-8314-45a3-b21b-b362a8543038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35067
99957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3506799957
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3843692565
Short name T2760
Test name
Test status
Simulation time 233364830 ps
CPU time 1.02 seconds
Started Aug 06 08:05:08 PM PDT 24
Finished Aug 06 08:05:09 PM PDT 24
Peak memory 207300 kb
Host smart-e568bc41-e5b9-45ed-9a0f-dae058db9114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38436
92565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3843692565
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.2691390736
Short name T2572
Test name
Test status
Simulation time 172245598 ps
CPU time 0.91 seconds
Started Aug 06 08:05:10 PM PDT 24
Finished Aug 06 08:05:11 PM PDT 24
Peak memory 207320 kb
Host smart-53a2fb01-87ad-4adf-88c2-b809d10a3df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26913
90736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.2691390736
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.1645034943
Short name T83
Test name
Test status
Simulation time 149806051 ps
CPU time 0.79 seconds
Started Aug 06 08:05:10 PM PDT 24
Finished Aug 06 08:05:11 PM PDT 24
Peak memory 207308 kb
Host smart-531a443b-8412-402c-bac4-df61ab6627e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16450
34943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.1645034943
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_rx_full.4127937072
Short name T1551
Test name
Test status
Simulation time 258847986 ps
CPU time 1.13 seconds
Started Aug 06 08:05:01 PM PDT 24
Finished Aug 06 08:05:02 PM PDT 24
Peak memory 207372 kb
Host smart-25812d06-55bf-4ad8-9428-263fdb4a0557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41279
37072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.4127937072
Directory /workspace/20.usbdev_rx_full/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1660714855
Short name T1334
Test name
Test status
Simulation time 149154688 ps
CPU time 0.8 seconds
Started Aug 06 08:04:53 PM PDT 24
Finished Aug 06 08:04:54 PM PDT 24
Peak memory 207344 kb
Host smart-39533fa3-8d80-4e68-90ad-6f96562be2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16607
14855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1660714855
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.4003395253
Short name T2936
Test name
Test status
Simulation time 158080461 ps
CPU time 0.82 seconds
Started Aug 06 08:05:02 PM PDT 24
Finished Aug 06 08:05:03 PM PDT 24
Peak memory 207376 kb
Host smart-6807abac-97f2-45ea-bf85-e4d62eb9967b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033
95253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.4003395253
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2090908386
Short name T537
Test name
Test status
Simulation time 232844461 ps
CPU time 0.99 seconds
Started Aug 06 08:05:03 PM PDT 24
Finished Aug 06 08:05:04 PM PDT 24
Peak memory 207312 kb
Host smart-26a75a0c-07b0-4a73-8012-7a6e0f83c7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20909
08386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2090908386
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2142190830
Short name T1207
Test name
Test status
Simulation time 1923279230 ps
CPU time 53.53 seconds
Started Aug 06 08:05:09 PM PDT 24
Finished Aug 06 08:06:02 PM PDT 24
Peak memory 215736 kb
Host smart-d13dc0e1-045c-4463-801c-b65428242e28
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2142190830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2142190830
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3674727537
Short name T637
Test name
Test status
Simulation time 178622510 ps
CPU time 0.89 seconds
Started Aug 06 08:05:08 PM PDT 24
Finished Aug 06 08:05:09 PM PDT 24
Peak memory 207324 kb
Host smart-d7b36d83-b3be-4e20-9076-1833084add39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36747
27537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3674727537
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.693184050
Short name T795
Test name
Test status
Simulation time 178978542 ps
CPU time 0.88 seconds
Started Aug 06 08:05:07 PM PDT 24
Finished Aug 06 08:05:08 PM PDT 24
Peak memory 207300 kb
Host smart-6f5e308d-0cc0-4dd7-acec-89956b752221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69318
4050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.693184050
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2364253220
Short name T642
Test name
Test status
Simulation time 1183099265 ps
CPU time 2.54 seconds
Started Aug 06 08:05:08 PM PDT 24
Finished Aug 06 08:05:10 PM PDT 24
Peak memory 207536 kb
Host smart-944fc8b2-ac54-4c05-a718-274c048bfa5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23642
53220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2364253220
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.2648864989
Short name T2987
Test name
Test status
Simulation time 2649246142 ps
CPU time 76.5 seconds
Started Aug 06 08:05:07 PM PDT 24
Finished Aug 06 08:06:23 PM PDT 24
Peak memory 215908 kb
Host smart-948dfed2-cd10-410b-94a1-61c6ad80df6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26488
64989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2648864989
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.1212117664
Short name T793
Test name
Test status
Simulation time 5661090910 ps
CPU time 37.54 seconds
Started Aug 06 08:04:44 PM PDT 24
Finished Aug 06 08:05:22 PM PDT 24
Peak memory 207732 kb
Host smart-f0293c41-3200-49a4-9e6e-2e5dffd7107c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212117664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.1212117664
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.454841678
Short name T213
Test name
Test status
Simulation time 41900390 ps
CPU time 0.64 seconds
Started Aug 06 08:04:57 PM PDT 24
Finished Aug 06 08:04:58 PM PDT 24
Peak memory 207504 kb
Host smart-587a29ac-6288-4630-b7ba-41b059bb8c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=454841678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.454841678
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2005879238
Short name T1265
Test name
Test status
Simulation time 4751042458 ps
CPU time 7.23 seconds
Started Aug 06 08:05:06 PM PDT 24
Finished Aug 06 08:05:14 PM PDT 24
Peak memory 215916 kb
Host smart-faa3b44e-abe3-498a-9cab-4addcb654731
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005879238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.2005879238
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.4062739602
Short name T871
Test name
Test status
Simulation time 19442911714 ps
CPU time 23.97 seconds
Started Aug 06 08:05:09 PM PDT 24
Finished Aug 06 08:05:33 PM PDT 24
Peak memory 207628 kb
Host smart-9bc3a465-8569-4f3f-9da9-41c4ddd5e474
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062739602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.4062739602
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1982318155
Short name T2161
Test name
Test status
Simulation time 30047884792 ps
CPU time 36.51 seconds
Started Aug 06 08:05:09 PM PDT 24
Finished Aug 06 08:05:46 PM PDT 24
Peak memory 207596 kb
Host smart-ae3b9b8b-d91c-4394-9eec-f7826db7e4ae
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982318155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.1982318155
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2223286578
Short name T882
Test name
Test status
Simulation time 163696658 ps
CPU time 0.9 seconds
Started Aug 06 08:05:11 PM PDT 24
Finished Aug 06 08:05:12 PM PDT 24
Peak memory 207304 kb
Host smart-7b7f160b-586c-4bdf-95fd-6474ac333fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22232
86578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2223286578
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.1981861530
Short name T2669
Test name
Test status
Simulation time 147881921 ps
CPU time 0.82 seconds
Started Aug 06 08:04:59 PM PDT 24
Finished Aug 06 08:05:00 PM PDT 24
Peak memory 207372 kb
Host smart-d65fb552-c308-4bd1-b736-f3edc648248e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19818
61530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.1981861530
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1654570746
Short name T2309
Test name
Test status
Simulation time 342768960 ps
CPU time 1.25 seconds
Started Aug 06 08:05:07 PM PDT 24
Finished Aug 06 08:05:08 PM PDT 24
Peak memory 207448 kb
Host smart-a75db9e6-e3a6-49c2-9511-fa808f58772d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16545
70746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1654570746
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2195956574
Short name T961
Test name
Test status
Simulation time 348494242 ps
CPU time 1.22 seconds
Started Aug 06 08:05:07 PM PDT 24
Finished Aug 06 08:05:09 PM PDT 24
Peak memory 207328 kb
Host smart-636722f7-d754-4123-bacd-23981a9de661
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2195956574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2195956574
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.2673088146
Short name T2919
Test name
Test status
Simulation time 36379262179 ps
CPU time 53.29 seconds
Started Aug 06 08:05:07 PM PDT 24
Finished Aug 06 08:06:00 PM PDT 24
Peak memory 207604 kb
Host smart-0d1121a9-333e-41b7-9665-9685d5a65e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26730
88146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.2673088146
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.3629837121
Short name T2635
Test name
Test status
Simulation time 295368563 ps
CPU time 4.52 seconds
Started Aug 06 08:05:06 PM PDT 24
Finished Aug 06 08:05:11 PM PDT 24
Peak memory 207456 kb
Host smart-ca9cae1e-91b5-4c85-9a07-b65bb2015d02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629837121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.3629837121
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.2711225819
Short name T762
Test name
Test status
Simulation time 823747600 ps
CPU time 2.03 seconds
Started Aug 06 08:05:05 PM PDT 24
Finished Aug 06 08:05:08 PM PDT 24
Peak memory 207288 kb
Host smart-abdbe01d-6f7e-4fd0-8087-d05346c69ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27112
25819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.2711225819
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2676742216
Short name T2998
Test name
Test status
Simulation time 161925750 ps
CPU time 0.85 seconds
Started Aug 06 08:04:56 PM PDT 24
Finished Aug 06 08:04:57 PM PDT 24
Peak memory 207292 kb
Host smart-d36188d0-0093-4387-98bb-b942a8801fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26767
42216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2676742216
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1027474505
Short name T634
Test name
Test status
Simulation time 38083293 ps
CPU time 0.71 seconds
Started Aug 06 08:04:59 PM PDT 24
Finished Aug 06 08:04:59 PM PDT 24
Peak memory 207364 kb
Host smart-7be98dc5-a354-4033-8fa4-cd10811e49ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10274
74505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1027474505
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3290904584
Short name T2860
Test name
Test status
Simulation time 877230646 ps
CPU time 2.22 seconds
Started Aug 06 08:05:12 PM PDT 24
Finished Aug 06 08:05:14 PM PDT 24
Peak memory 207704 kb
Host smart-3ebfd65a-9acf-4c49-821c-7f30beb90109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32909
04584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3290904584
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_types.936388854
Short name T391
Test name
Test status
Simulation time 541279456 ps
CPU time 1.43 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:04:57 PM PDT 24
Peak memory 207324 kb
Host smart-21577bbc-09b3-4e44-b099-01e9d34f5e8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=936388854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.936388854
Directory /workspace/21.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1119354001
Short name T1444
Test name
Test status
Simulation time 176001568 ps
CPU time 1.61 seconds
Started Aug 06 08:05:08 PM PDT 24
Finished Aug 06 08:05:09 PM PDT 24
Peak memory 207516 kb
Host smart-85e6b314-c9c1-405e-aeac-b90bcbf2092b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11193
54001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1119354001
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3830337560
Short name T831
Test name
Test status
Simulation time 185554116 ps
CPU time 0.94 seconds
Started Aug 06 08:04:57 PM PDT 24
Finished Aug 06 08:04:58 PM PDT 24
Peak memory 207352 kb
Host smart-115eab5d-94a3-47e1-a9b3-c1899474607b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3830337560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3830337560
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3767080962
Short name T950
Test name
Test status
Simulation time 163056534 ps
CPU time 0.82 seconds
Started Aug 06 08:05:13 PM PDT 24
Finished Aug 06 08:05:14 PM PDT 24
Peak memory 207296 kb
Host smart-16db72bc-1fac-472b-80ef-3eb260f76ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37670
80962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3767080962
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1649511365
Short name T3021
Test name
Test status
Simulation time 174539180 ps
CPU time 0.87 seconds
Started Aug 06 08:04:57 PM PDT 24
Finished Aug 06 08:04:58 PM PDT 24
Peak memory 206644 kb
Host smart-9efba943-a6b7-46bc-8261-ff53988a85e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16495
11365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1649511365
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.3850275638
Short name T3070
Test name
Test status
Simulation time 5052847177 ps
CPU time 150.47 seconds
Started Aug 06 08:05:05 PM PDT 24
Finished Aug 06 08:07:35 PM PDT 24
Peak memory 215884 kb
Host smart-1d3f4d8d-d4b5-47e8-98f0-3fe317829764
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3850275638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.3850275638
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.2223229019
Short name T747
Test name
Test status
Simulation time 3897854597 ps
CPU time 49.23 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:05:44 PM PDT 24
Peak memory 207604 kb
Host smart-b3b6efd0-bc73-4347-9997-ffaba6a43d82
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2223229019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.2223229019
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1714257166
Short name T1345
Test name
Test status
Simulation time 164061317 ps
CPU time 0.86 seconds
Started Aug 06 08:04:54 PM PDT 24
Finished Aug 06 08:04:55 PM PDT 24
Peak memory 207392 kb
Host smart-5a9544e0-cbf1-4cf2-8d04-18a7f6e5b3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17142
57166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1714257166
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.3000281375
Short name T1303
Test name
Test status
Simulation time 27058589593 ps
CPU time 28.83 seconds
Started Aug 06 08:04:54 PM PDT 24
Finished Aug 06 08:05:23 PM PDT 24
Peak memory 215800 kb
Host smart-cd324323-37c4-4230-adab-7ad12b37cdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30002
81375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.3000281375
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1113545976
Short name T3051
Test name
Test status
Simulation time 8706888762 ps
CPU time 12.96 seconds
Started Aug 06 08:05:02 PM PDT 24
Finished Aug 06 08:05:15 PM PDT 24
Peak memory 207672 kb
Host smart-c18ec6c5-09dc-4785-8957-b25b216a9b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11135
45976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1113545976
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.3497978601
Short name T2194
Test name
Test status
Simulation time 2368837160 ps
CPU time 63.14 seconds
Started Aug 06 08:05:06 PM PDT 24
Finished Aug 06 08:06:09 PM PDT 24
Peak memory 218244 kb
Host smart-a931587f-975c-4060-9107-b32ae6de8a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34979
78601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.3497978601
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.4122542194
Short name T1777
Test name
Test status
Simulation time 3337533229 ps
CPU time 96.06 seconds
Started Aug 06 08:05:02 PM PDT 24
Finished Aug 06 08:06:38 PM PDT 24
Peak memory 217332 kb
Host smart-6d435dd7-1c14-4fd5-aa38-35cb36b17ad8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4122542194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.4122542194
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2293001318
Short name T1948
Test name
Test status
Simulation time 253436313 ps
CPU time 1.01 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:04:56 PM PDT 24
Peak memory 207308 kb
Host smart-1b3a2701-63d9-4b7e-98ac-cdba46913ae4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2293001318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2293001318
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1618737913
Short name T1532
Test name
Test status
Simulation time 214036918 ps
CPU time 0.99 seconds
Started Aug 06 08:05:08 PM PDT 24
Finished Aug 06 08:05:09 PM PDT 24
Peak memory 207384 kb
Host smart-77cc31f2-5533-442e-a7a4-4fa908c42fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16187
37913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1618737913
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.1390447744
Short name T817
Test name
Test status
Simulation time 1998246013 ps
CPU time 55.58 seconds
Started Aug 06 08:04:55 PM PDT 24
Finished Aug 06 08:05:51 PM PDT 24
Peak memory 215668 kb
Host smart-4e684c2f-4d07-4d8b-8fdb-5ebdf3b50fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13904
47744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.1390447744
Directory /workspace/21.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.4266352226
Short name T735
Test name
Test status
Simulation time 3143693413 ps
CPU time 31.26 seconds
Started Aug 06 08:05:05 PM PDT 24
Finished Aug 06 08:05:36 PM PDT 24
Peak memory 215872 kb
Host smart-20550916-a60e-4d16-936a-6abffbfd9236
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4266352226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.4266352226
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.375357823
Short name T2903
Test name
Test status
Simulation time 149219599 ps
CPU time 0.85 seconds
Started Aug 06 08:05:08 PM PDT 24
Finished Aug 06 08:05:09 PM PDT 24
Peak memory 207452 kb
Host smart-36d30e05-06d4-4b02-8dfb-d3390986290a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=375357823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.375357823
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3884365464
Short name T694
Test name
Test status
Simulation time 153709022 ps
CPU time 0.88 seconds
Started Aug 06 08:05:03 PM PDT 24
Finished Aug 06 08:05:04 PM PDT 24
Peak memory 207380 kb
Host smart-77cdbbe9-f662-457c-84a6-0c725da1fab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38843
65464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3884365464
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3985079504
Short name T133
Test name
Test status
Simulation time 197715961 ps
CPU time 0.93 seconds
Started Aug 06 08:05:00 PM PDT 24
Finished Aug 06 08:05:01 PM PDT 24
Peak memory 207332 kb
Host smart-0311679f-d9c2-4bc1-ac51-b490240e7d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39850
79504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3985079504
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2968315337
Short name T1158
Test name
Test status
Simulation time 175409843 ps
CPU time 0.89 seconds
Started Aug 06 08:04:54 PM PDT 24
Finished Aug 06 08:04:55 PM PDT 24
Peak memory 207412 kb
Host smart-bad36b0e-b475-4c9f-8e46-88205d790538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29683
15337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2968315337
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2914240189
Short name T2412
Test name
Test status
Simulation time 160230299 ps
CPU time 0.84 seconds
Started Aug 06 08:05:06 PM PDT 24
Finished Aug 06 08:05:07 PM PDT 24
Peak memory 207452 kb
Host smart-59ffd3a3-f106-40fb-8707-d5d7600de4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29142
40189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2914240189
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3662671915
Short name T2335
Test name
Test status
Simulation time 179078946 ps
CPU time 0.87 seconds
Started Aug 06 08:05:15 PM PDT 24
Finished Aug 06 08:05:16 PM PDT 24
Peak memory 207320 kb
Host smart-615a7cc2-d7ad-4a82-ac04-6020a1db820b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36626
71915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3662671915
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2463470313
Short name T2647
Test name
Test status
Simulation time 182194872 ps
CPU time 0.89 seconds
Started Aug 06 08:05:00 PM PDT 24
Finished Aug 06 08:05:01 PM PDT 24
Peak memory 207372 kb
Host smart-ca53870a-6626-450e-9770-350610c17af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24634
70313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2463470313
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2457807947
Short name T1274
Test name
Test status
Simulation time 228855282 ps
CPU time 1 seconds
Started Aug 06 08:05:02 PM PDT 24
Finished Aug 06 08:05:03 PM PDT 24
Peak memory 207360 kb
Host smart-47373b1d-1d1b-4e91-b07c-f9a09b4e869c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2457807947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2457807947
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.970993860
Short name T1594
Test name
Test status
Simulation time 153062889 ps
CPU time 0.84 seconds
Started Aug 06 08:05:00 PM PDT 24
Finished Aug 06 08:05:01 PM PDT 24
Peak memory 207348 kb
Host smart-0f90b123-0317-42d8-9041-afcfe7187577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97099
3860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.970993860
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.518041328
Short name T2957
Test name
Test status
Simulation time 66135511 ps
CPU time 0.75 seconds
Started Aug 06 08:05:08 PM PDT 24
Finished Aug 06 08:05:08 PM PDT 24
Peak memory 207304 kb
Host smart-3ceb41cf-96af-4e8d-b8d0-d64116f200b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51804
1328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.518041328
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2318505354
Short name T1509
Test name
Test status
Simulation time 22504162891 ps
CPU time 56.15 seconds
Started Aug 06 08:05:00 PM PDT 24
Finished Aug 06 08:05:56 PM PDT 24
Peak memory 215868 kb
Host smart-e92c94cc-2eb8-4cac-aaf9-7bcff3838d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23185
05354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2318505354
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3578356523
Short name T1573
Test name
Test status
Simulation time 154941422 ps
CPU time 0.89 seconds
Started Aug 06 08:05:08 PM PDT 24
Finished Aug 06 08:05:09 PM PDT 24
Peak memory 207360 kb
Host smart-f6ea599b-04c1-44c2-9b4c-ca39d2b903bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35783
56523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3578356523
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2587347217
Short name T1392
Test name
Test status
Simulation time 220781173 ps
CPU time 0.95 seconds
Started Aug 06 08:04:57 PM PDT 24
Finished Aug 06 08:04:58 PM PDT 24
Peak memory 207356 kb
Host smart-bd66c212-597b-4433-8b19-7ce765c8d4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25873
47217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2587347217
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.1798956014
Short name T1623
Test name
Test status
Simulation time 178054616 ps
CPU time 0.88 seconds
Started Aug 06 08:04:58 PM PDT 24
Finished Aug 06 08:04:59 PM PDT 24
Peak memory 207364 kb
Host smart-6392b756-1aa5-4eb7-9b42-1578ae443173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17989
56014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1798956014
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.1534123228
Short name T679
Test name
Test status
Simulation time 154649942 ps
CPU time 0.85 seconds
Started Aug 06 08:05:06 PM PDT 24
Finished Aug 06 08:05:07 PM PDT 24
Peak memory 207372 kb
Host smart-dabd0593-5295-41f3-aeca-78bc8e48ca36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15341
23228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.1534123228
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.1554969059
Short name T2704
Test name
Test status
Simulation time 155941376 ps
CPU time 0.86 seconds
Started Aug 06 08:05:03 PM PDT 24
Finished Aug 06 08:05:04 PM PDT 24
Peak memory 207340 kb
Host smart-c3938a94-cf6d-4134-b449-8c809b2627a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15549
69059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.1554969059
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_rx_full.1709015753
Short name T2522
Test name
Test status
Simulation time 404568893 ps
CPU time 1.35 seconds
Started Aug 06 08:05:01 PM PDT 24
Finished Aug 06 08:05:03 PM PDT 24
Peak memory 206624 kb
Host smart-b3a93f81-641a-4536-981a-476a3bde2e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17090
15753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.1709015753
Directory /workspace/21.usbdev_rx_full/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.3150339484
Short name T2169
Test name
Test status
Simulation time 144104816 ps
CPU time 0.83 seconds
Started Aug 06 08:05:14 PM PDT 24
Finished Aug 06 08:05:14 PM PDT 24
Peak memory 207276 kb
Host smart-c884872a-a76f-4517-8d7a-62f1bd50c201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31503
39484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3150339484
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3424337104
Short name T2385
Test name
Test status
Simulation time 168471191 ps
CPU time 0.84 seconds
Started Aug 06 08:05:04 PM PDT 24
Finished Aug 06 08:05:05 PM PDT 24
Peak memory 207308 kb
Host smart-54b0024a-ebe8-4f97-9e0d-cd2992475e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34243
37104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3424337104
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2984523322
Short name T2297
Test name
Test status
Simulation time 220931519 ps
CPU time 1.02 seconds
Started Aug 06 08:05:11 PM PDT 24
Finished Aug 06 08:05:12 PM PDT 24
Peak memory 207308 kb
Host smart-9ef3e573-e1ba-43a7-b9bc-17183790f576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29845
23322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2984523322
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.2072853452
Short name T94
Test name
Test status
Simulation time 3256941730 ps
CPU time 24.03 seconds
Started Aug 06 08:05:13 PM PDT 24
Finished Aug 06 08:05:37 PM PDT 24
Peak memory 215832 kb
Host smart-956cb576-8e4d-4be6-b631-6521fbc679fc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2072853452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.2072853452
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.645790450
Short name T2839
Test name
Test status
Simulation time 186210057 ps
CPU time 0.9 seconds
Started Aug 06 08:05:20 PM PDT 24
Finished Aug 06 08:05:21 PM PDT 24
Peak memory 207364 kb
Host smart-3ba36595-aef7-4da1-ae6b-3f06211197d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64579
0450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.645790450
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3881377687
Short name T276
Test name
Test status
Simulation time 181298661 ps
CPU time 0.95 seconds
Started Aug 06 08:05:18 PM PDT 24
Finished Aug 06 08:05:19 PM PDT 24
Peak memory 207356 kb
Host smart-b7f1f4a0-f13c-4c7f-ab33-640678696829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38813
77687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3881377687
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3290813395
Short name T1202
Test name
Test status
Simulation time 681354229 ps
CPU time 1.89 seconds
Started Aug 06 08:05:09 PM PDT 24
Finished Aug 06 08:05:11 PM PDT 24
Peak memory 207328 kb
Host smart-d6ccc161-d8cf-4d2f-9cd7-5f7a304e1645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32908
13395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3290813395
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.904408279
Short name T2867
Test name
Test status
Simulation time 2161614160 ps
CPU time 60.68 seconds
Started Aug 06 08:05:16 PM PDT 24
Finished Aug 06 08:06:17 PM PDT 24
Peak memory 223920 kb
Host smart-b880e01c-af3c-4c95-a98c-88c412c0c498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90440
8279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.904408279
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.1013024736
Short name T2158
Test name
Test status
Simulation time 2916626930 ps
CPU time 25.39 seconds
Started Aug 06 08:05:07 PM PDT 24
Finished Aug 06 08:05:33 PM PDT 24
Peak memory 207560 kb
Host smart-cfdf0c7c-e524-4106-9986-c1f1242abcd0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013024736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.1013024736
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.2220026605
Short name T3035
Test name
Test status
Simulation time 45032415 ps
CPU time 0.64 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:27 PM PDT 24
Peak memory 207480 kb
Host smart-63f208fe-1248-4c3f-bb88-a7e675ee8f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2220026605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2220026605
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.852660703
Short name T1407
Test name
Test status
Simulation time 6980207939 ps
CPU time 9.66 seconds
Started Aug 06 08:05:21 PM PDT 24
Finished Aug 06 08:05:30 PM PDT 24
Peak memory 215812 kb
Host smart-672f42cc-49f6-4e2f-8432-b305374041b7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852660703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ao
n_wake_disconnect.852660703
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1641755206
Short name T1243
Test name
Test status
Simulation time 13489969058 ps
CPU time 18.43 seconds
Started Aug 06 08:05:08 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 215844 kb
Host smart-4e973628-3d14-4958-a141-91353cc84571
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641755206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1641755206
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.3919544626
Short name T1429
Test name
Test status
Simulation time 24840019505 ps
CPU time 27.27 seconds
Started Aug 06 08:05:00 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 215808 kb
Host smart-2d81575c-46fd-488e-a57d-789343c8a4c5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919544626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_resume.3919544626
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1108179980
Short name T854
Test name
Test status
Simulation time 157114485 ps
CPU time 0.86 seconds
Started Aug 06 08:05:16 PM PDT 24
Finished Aug 06 08:05:17 PM PDT 24
Peak memory 207308 kb
Host smart-bc567ad0-5e03-4a95-a31e-a96dbc78aa3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11081
79980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1108179980
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.1865793174
Short name T1808
Test name
Test status
Simulation time 164110643 ps
CPU time 0.85 seconds
Started Aug 06 08:05:11 PM PDT 24
Finished Aug 06 08:05:12 PM PDT 24
Peak memory 207260 kb
Host smart-b0fc04ca-cf87-4b84-8d2a-9e5c0b311be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18657
93174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.1865793174
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.2382126178
Short name T1443
Test name
Test status
Simulation time 613270581 ps
CPU time 2.03 seconds
Started Aug 06 08:05:18 PM PDT 24
Finished Aug 06 08:05:20 PM PDT 24
Peak memory 207388 kb
Host smart-0cd12f98-6b35-4c30-8d28-c5285fd20767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23821
26178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.2382126178
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2233452722
Short name T607
Test name
Test status
Simulation time 660305878 ps
CPU time 1.88 seconds
Started Aug 06 08:05:08 PM PDT 24
Finished Aug 06 08:05:10 PM PDT 24
Peak memory 207364 kb
Host smart-58a8e3b2-dbe8-4d7a-84c6-0017ebe34a32
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2233452722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2233452722
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.3494819643
Short name T2587
Test name
Test status
Simulation time 19828443461 ps
CPU time 35.05 seconds
Started Aug 06 08:05:05 PM PDT 24
Finished Aug 06 08:05:40 PM PDT 24
Peak memory 207620 kb
Host smart-ba0defcc-cf13-4bf7-8990-595d0135ebcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34948
19643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.3494819643
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.4204312843
Short name T2739
Test name
Test status
Simulation time 998338481 ps
CPU time 22.64 seconds
Started Aug 06 08:05:11 PM PDT 24
Finished Aug 06 08:05:34 PM PDT 24
Peak memory 207584 kb
Host smart-c34a2882-0f1f-4b7a-90ca-09ffc8f095ec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204312843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.4204312843
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2991327991
Short name T329
Test name
Test status
Simulation time 795384987 ps
CPU time 1.88 seconds
Started Aug 06 08:05:29 PM PDT 24
Finished Aug 06 08:05:31 PM PDT 24
Peak memory 207308 kb
Host smart-ce0ce6e1-0fb3-4ab5-8f32-967a379e2532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29913
27991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2991327991
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.4023035933
Short name T984
Test name
Test status
Simulation time 161387684 ps
CPU time 0.8 seconds
Started Aug 06 08:05:30 PM PDT 24
Finished Aug 06 08:05:31 PM PDT 24
Peak memory 207304 kb
Host smart-efa9ceaf-45a9-4ae3-9502-6397ab71e377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40230
35933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.4023035933
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1721349650
Short name T2942
Test name
Test status
Simulation time 83522133 ps
CPU time 0.73 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:27 PM PDT 24
Peak memory 207300 kb
Host smart-1c096c31-fe4d-44bb-93aa-23da05f2f3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17213
49650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1721349650
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3474407517
Short name T2270
Test name
Test status
Simulation time 1023883968 ps
CPU time 2.44 seconds
Started Aug 06 08:05:25 PM PDT 24
Finished Aug 06 08:05:27 PM PDT 24
Peak memory 207528 kb
Host smart-0d79950e-fdc9-489d-a32e-e6d540c51ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34744
07517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3474407517
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_types.2711127649
Short name T388
Test name
Test status
Simulation time 531908609 ps
CPU time 1.32 seconds
Started Aug 06 08:05:21 PM PDT 24
Finished Aug 06 08:05:22 PM PDT 24
Peak memory 207316 kb
Host smart-450f8eb1-1dcf-4f31-91d5-60ddfe98c621
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2711127649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.2711127649
Directory /workspace/22.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.976764173
Short name T954
Test name
Test status
Simulation time 238603961 ps
CPU time 1.49 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207520 kb
Host smart-ba5e4d5d-a172-4398-b80c-9660a8934884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97676
4173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.976764173
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1934450775
Short name T2559
Test name
Test status
Simulation time 184131305 ps
CPU time 0.91 seconds
Started Aug 06 08:05:25 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 207356 kb
Host smart-85d445a5-b1e8-4e76-93ca-8205d7974eb6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1934450775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1934450775
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3545005627
Short name T3118
Test name
Test status
Simulation time 147801523 ps
CPU time 0.89 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207324 kb
Host smart-1da3682f-a3a8-4eb3-b37a-4097770b0fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35450
05627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3545005627
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.424184849
Short name T2992
Test name
Test status
Simulation time 168853564 ps
CPU time 0.88 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:23 PM PDT 24
Peak memory 207404 kb
Host smart-9ae4c402-3ed4-435f-8222-b194c80bd4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42418
4849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.424184849
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.2863565138
Short name T1671
Test name
Test status
Simulation time 4000479680 ps
CPU time 114.13 seconds
Started Aug 06 08:05:21 PM PDT 24
Finished Aug 06 08:07:15 PM PDT 24
Peak memory 224068 kb
Host smart-275240cc-e332-49b5-a2b8-dfaf44117b89
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2863565138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.2863565138
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.1766342446
Short name T2745
Test name
Test status
Simulation time 11050977142 ps
CPU time 83.26 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:06:45 PM PDT 24
Peak memory 207624 kb
Host smart-1915d79a-3d7b-4d42-a27f-6444f006b0e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1766342446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.1766342446
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3852898732
Short name T663
Test name
Test status
Simulation time 206532168 ps
CPU time 0.98 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 207400 kb
Host smart-6b0ad0e8-ad5e-45d6-ac0a-96a8b97337b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38528
98732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3852898732
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3925506970
Short name T3125
Test name
Test status
Simulation time 28853744651 ps
CPU time 50.34 seconds
Started Aug 06 08:05:25 PM PDT 24
Finished Aug 06 08:06:16 PM PDT 24
Peak memory 207656 kb
Host smart-dc1cd360-30d6-4e88-b3da-6e4848d043cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39255
06970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3925506970
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2375511905
Short name T816
Test name
Test status
Simulation time 5070145722 ps
CPU time 7.83 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:30 PM PDT 24
Peak memory 207608 kb
Host smart-e8b985ac-958a-43bc-ad44-6fd4b3864779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23755
11905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2375511905
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1660711362
Short name T3014
Test name
Test status
Simulation time 3203729512 ps
CPU time 93.24 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:06:56 PM PDT 24
Peak memory 218304 kb
Host smart-f180140c-2122-459b-88de-57d8c60e3470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16607
11362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1660711362
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1722818279
Short name T489
Test name
Test status
Simulation time 2888858751 ps
CPU time 28.21 seconds
Started Aug 06 08:05:18 PM PDT 24
Finished Aug 06 08:05:46 PM PDT 24
Peak memory 215832 kb
Host smart-04e7624e-a426-4f74-aae1-19d33ba282af
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1722818279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1722818279
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.2412981303
Short name T1067
Test name
Test status
Simulation time 262057266 ps
CPU time 1 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:24 PM PDT 24
Peak memory 207304 kb
Host smart-ccde1ce6-b6a4-4aec-b329-19393eba0ed1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2412981303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.2412981303
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3744335073
Short name T727
Test name
Test status
Simulation time 188479935 ps
CPU time 0.87 seconds
Started Aug 06 08:05:20 PM PDT 24
Finished Aug 06 08:05:21 PM PDT 24
Peak memory 207372 kb
Host smart-922469b4-b856-4637-ac19-cde197b47429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37443
35073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3744335073
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.1437282451
Short name T904
Test name
Test status
Simulation time 2249290222 ps
CPU time 22.33 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:45 PM PDT 24
Peak memory 223972 kb
Host smart-c2b83d17-829c-4055-a0ee-076fc46424ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14372
82451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.1437282451
Directory /workspace/22.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.2092043472
Short name T1246
Test name
Test status
Simulation time 1691256809 ps
CPU time 46.4 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:06:09 PM PDT 24
Peak memory 215564 kb
Host smart-77e078ca-6727-42ea-b730-a46ce1d5ce2f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2092043472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.2092043472
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2516970038
Short name T2067
Test name
Test status
Simulation time 208536407 ps
CPU time 0.96 seconds
Started Aug 06 08:05:21 PM PDT 24
Finished Aug 06 08:05:22 PM PDT 24
Peak memory 207332 kb
Host smart-f3b5b484-2221-4a98-9b7a-a8c6a0bc8fc8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2516970038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2516970038
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3309813315
Short name T1603
Test name
Test status
Simulation time 160584840 ps
CPU time 0.86 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 207428 kb
Host smart-4dde6e01-565f-4c4e-b80d-8b1e1c129621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33098
13315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3309813315
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.915786928
Short name T572
Test name
Test status
Simulation time 169054019 ps
CPU time 0.92 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:23 PM PDT 24
Peak memory 207200 kb
Host smart-b024321c-e412-4743-82c3-208bf420bd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91578
6928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.915786928
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1621181734
Short name T539
Test name
Test status
Simulation time 175223162 ps
CPU time 0.92 seconds
Started Aug 06 08:05:27 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 207288 kb
Host smart-deeeb483-a48c-4722-b6bf-183826585439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16211
81734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1621181734
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.221441480
Short name T2554
Test name
Test status
Simulation time 196276347 ps
CPU time 0.91 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:27 PM PDT 24
Peak memory 207336 kb
Host smart-c13bfa55-a2ee-428e-be45-e4b864d5215a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22144
1480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.221441480
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1560026803
Short name T2317
Test name
Test status
Simulation time 160319763 ps
CPU time 0.87 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:27 PM PDT 24
Peak memory 207420 kb
Host smart-77b34cea-8dcb-4080-b495-5b42539abe61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15600
26803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1560026803
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.3237841480
Short name T2553
Test name
Test status
Simulation time 246020631 ps
CPU time 1.02 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 207320 kb
Host smart-30ce8c59-c405-464e-9e08-fd502ae3cfa9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3237841480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.3237841480
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3314630187
Short name T1284
Test name
Test status
Simulation time 166065043 ps
CPU time 0.9 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:23 PM PDT 24
Peak memory 207396 kb
Host smart-3498a7b5-187a-4563-abc8-e908f9c330de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33146
30187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3314630187
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2320392599
Short name T1895
Test name
Test status
Simulation time 54517344 ps
CPU time 0.69 seconds
Started Aug 06 08:05:25 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 207344 kb
Host smart-6fe266cf-9c0f-4f4e-b51a-a201970488e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23203
92599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2320392599
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.4197319629
Short name T2416
Test name
Test status
Simulation time 19504729196 ps
CPU time 53.5 seconds
Started Aug 06 08:05:18 PM PDT 24
Finished Aug 06 08:06:12 PM PDT 24
Peak memory 215864 kb
Host smart-9a5c8368-4fea-43ee-9272-bf90a5090a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41973
19629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.4197319629
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1332482755
Short name T21
Test name
Test status
Simulation time 189166290 ps
CPU time 0.94 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:24 PM PDT 24
Peak memory 207348 kb
Host smart-c4fa0643-34ca-4d47-b4f5-dc06d2554950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13324
82755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1332482755
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3478719395
Short name T1790
Test name
Test status
Simulation time 201527803 ps
CPU time 0.97 seconds
Started Aug 06 08:05:19 PM PDT 24
Finished Aug 06 08:05:20 PM PDT 24
Peak memory 207368 kb
Host smart-52c2a3f7-571a-4475-8002-83ce64726eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34787
19395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3478719395
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2025778352
Short name T1761
Test name
Test status
Simulation time 160161561 ps
CPU time 0.88 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:27 PM PDT 24
Peak memory 207408 kb
Host smart-c3f8e5c6-331e-4b71-b2b3-4fb628400a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20257
78352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2025778352
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1532932442
Short name T502
Test name
Test status
Simulation time 187578433 ps
CPU time 0.88 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207240 kb
Host smart-ae6ff8be-00ba-4b5a-a63c-e749c4d28d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15329
32442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1532932442
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1881038849
Short name T1550
Test name
Test status
Simulation time 166376835 ps
CPU time 0.83 seconds
Started Aug 06 08:05:20 PM PDT 24
Finished Aug 06 08:05:21 PM PDT 24
Peak memory 207364 kb
Host smart-85f7789c-82ab-481c-9fff-ad05698679cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18810
38849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1881038849
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_rx_full.2155011668
Short name T1169
Test name
Test status
Simulation time 341021608 ps
CPU time 1.18 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:05:24 PM PDT 24
Peak memory 207352 kb
Host smart-4652ef3e-25b9-4abf-b1b8-eeacd74a6964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21550
11668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.2155011668
Directory /workspace/22.usbdev_rx_full/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3821306696
Short name T704
Test name
Test status
Simulation time 156703404 ps
CPU time 0.83 seconds
Started Aug 06 08:05:20 PM PDT 24
Finished Aug 06 08:05:21 PM PDT 24
Peak memory 207280 kb
Host smart-ec1136f2-b8e8-43ec-9798-568c1a49780e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38213
06696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3821306696
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1559622168
Short name T2741
Test name
Test status
Simulation time 165274136 ps
CPU time 0.84 seconds
Started Aug 06 08:05:31 PM PDT 24
Finished Aug 06 08:05:32 PM PDT 24
Peak memory 207320 kb
Host smart-36988e92-d404-45b8-adc2-b8af421b2fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15596
22168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1559622168
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3484633335
Short name T1937
Test name
Test status
Simulation time 220683990 ps
CPU time 0.99 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:24 PM PDT 24
Peak memory 207360 kb
Host smart-e67c5d79-422c-4828-b0b6-f7e027f286c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34846
33335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3484633335
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.2549467504
Short name T2588
Test name
Test status
Simulation time 2613723351 ps
CPU time 25.4 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:05:49 PM PDT 24
Peak memory 224016 kb
Host smart-ee39cd68-999c-4a08-bef4-75a75b847b0a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2549467504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.2549467504
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1773506644
Short name T1350
Test name
Test status
Simulation time 184379303 ps
CPU time 0.92 seconds
Started Aug 06 08:05:19 PM PDT 24
Finished Aug 06 08:05:20 PM PDT 24
Peak memory 207292 kb
Host smart-b1b2b4f0-5704-42bc-b5bd-4ba8dab79fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17735
06644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1773506644
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.123694200
Short name T1759
Test name
Test status
Simulation time 142402171 ps
CPU time 0.86 seconds
Started Aug 06 08:05:21 PM PDT 24
Finished Aug 06 08:05:22 PM PDT 24
Peak memory 207352 kb
Host smart-917112bf-3854-4b3f-89eb-b7cd6e056f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12369
4200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.123694200
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.2852116727
Short name T1487
Test name
Test status
Simulation time 1212758764 ps
CPU time 2.78 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 207384 kb
Host smart-2895b298-e369-4d03-82be-dbe48a965494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28521
16727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.2852116727
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2901557117
Short name T885
Test name
Test status
Simulation time 1863718393 ps
CPU time 54.21 seconds
Started Aug 06 08:05:21 PM PDT 24
Finished Aug 06 08:06:15 PM PDT 24
Peak memory 217172 kb
Host smart-41b7a6af-8563-4f40-80cd-1650ac58dae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29015
57117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2901557117
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.817266836
Short name T2008
Test name
Test status
Simulation time 6362235395 ps
CPU time 40.4 seconds
Started Aug 06 08:04:57 PM PDT 24
Finished Aug 06 08:05:37 PM PDT 24
Peak memory 207560 kb
Host smart-b9fb0992-e670-4451-839b-f0b257753ec5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817266836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_host
_handshake.817266836
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.3395748162
Short name T2423
Test name
Test status
Simulation time 47270223 ps
CPU time 0.67 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207348 kb
Host smart-7d3edb40-9a7c-4f00-8f5e-188e51736cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3395748162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.3395748162
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3920336933
Short name T2764
Test name
Test status
Simulation time 9518880089 ps
CPU time 11.15 seconds
Started Aug 06 08:05:15 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 207580 kb
Host smart-5566b952-214f-46b1-bb0c-55612b2710b2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920336933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.3920336933
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3290350852
Short name T1908
Test name
Test status
Simulation time 16391761650 ps
CPU time 22.58 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:48 PM PDT 24
Peak memory 215816 kb
Host smart-1ba691e3-60da-4eaf-9e05-9262b3d0faec
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290350852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3290350852
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1521024845
Short name T2215
Test name
Test status
Simulation time 24896148926 ps
CPU time 28.45 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:51 PM PDT 24
Peak memory 215760 kb
Host smart-b370c142-c872-4cc2-afac-d44a0e31cde0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521024845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.1521024845
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3731233485
Short name T1150
Test name
Test status
Simulation time 158794308 ps
CPU time 0.84 seconds
Started Aug 06 08:05:18 PM PDT 24
Finished Aug 06 08:05:18 PM PDT 24
Peak memory 207296 kb
Host smart-7bcb8d55-8e0a-4df7-be4c-57d51f21f082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37312
33485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3731233485
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.48336176
Short name T945
Test name
Test status
Simulation time 159218731 ps
CPU time 0.84 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:05:24 PM PDT 24
Peak memory 207324 kb
Host smart-ba6bcb37-dac0-4ce1-b7c8-9510ca1e6479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48336
176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.48336176
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.191704267
Short name T2277
Test name
Test status
Simulation time 480175357 ps
CPU time 1.56 seconds
Started Aug 06 08:05:19 PM PDT 24
Finished Aug 06 08:05:21 PM PDT 24
Peak memory 207380 kb
Host smart-64fda130-3d23-4bf4-b97a-ad3d7ed8e062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19170
4267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.191704267
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.3895901751
Short name T2656
Test name
Test status
Simulation time 1169857968 ps
CPU time 3.06 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 207544 kb
Host smart-b1f20e5f-1c3f-4d8b-bb64-e76224b04d6a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3895901751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3895901751
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.1759252639
Short name T3068
Test name
Test status
Simulation time 31296100726 ps
CPU time 47.06 seconds
Started Aug 06 08:05:21 PM PDT 24
Finished Aug 06 08:06:08 PM PDT 24
Peak memory 207664 kb
Host smart-d28101df-9384-419b-bd0b-bd954c321f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17592
52639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.1759252639
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.2998636722
Short name T587
Test name
Test status
Simulation time 1408088091 ps
CPU time 33.7 seconds
Started Aug 06 08:05:28 PM PDT 24
Finished Aug 06 08:06:02 PM PDT 24
Peak memory 207512 kb
Host smart-cd026c9b-c65b-46d6-9b25-75f8ce97714a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998636722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.2998636722
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2339184728
Short name T802
Test name
Test status
Simulation time 853025273 ps
CPU time 2.15 seconds
Started Aug 06 08:05:21 PM PDT 24
Finished Aug 06 08:05:23 PM PDT 24
Peak memory 207292 kb
Host smart-39097a42-88d6-4c12-8c12-68da44e68fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23391
84728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2339184728
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2216839264
Short name T1752
Test name
Test status
Simulation time 152596722 ps
CPU time 0.83 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:05:24 PM PDT 24
Peak memory 207296 kb
Host smart-29f5a988-9fe3-4e0b-88f1-4ef0336e1880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22168
39264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2216839264
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.1012308980
Short name T2014
Test name
Test status
Simulation time 54169095 ps
CPU time 0.74 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:23 PM PDT 24
Peak memory 207252 kb
Host smart-13bf98b5-9138-4365-b1ac-239db8bc2445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10123
08980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1012308980
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.1816298854
Short name T2852
Test name
Test status
Simulation time 789012607 ps
CPU time 2.01 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 207636 kb
Host smart-87debcd7-69cc-40ec-a5ce-4ee00ec85c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18162
98854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.1816298854
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_types.3610066116
Short name T2911
Test name
Test status
Simulation time 231472292 ps
CPU time 1.02 seconds
Started Aug 06 08:05:17 PM PDT 24
Finished Aug 06 08:05:19 PM PDT 24
Peak memory 207272 kb
Host smart-d7522157-7247-4ff6-92d3-33dcb875ffca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3610066116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.3610066116
Directory /workspace/23.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1333309384
Short name T1975
Test name
Test status
Simulation time 272053956 ps
CPU time 2.07 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 207580 kb
Host smart-bcec5bf5-6247-4fbd-8225-dc325bcf86f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13333
09384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1333309384
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3866464897
Short name T2986
Test name
Test status
Simulation time 155735176 ps
CPU time 0.87 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:23 PM PDT 24
Peak memory 207384 kb
Host smart-c60935c2-acbf-4ccd-8080-441583c3b042
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3866464897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3866464897
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2383086062
Short name T1976
Test name
Test status
Simulation time 141377228 ps
CPU time 0.81 seconds
Started Aug 06 08:05:27 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 207328 kb
Host smart-79c1d229-159a-46e7-8872-b6e7263e74c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23830
86062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2383086062
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3666334746
Short name T2627
Test name
Test status
Simulation time 175292681 ps
CPU time 0.91 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207360 kb
Host smart-c629b421-f58e-4f46-aca4-86df6e9e9d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36663
34746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3666334746
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.1887274415
Short name T1167
Test name
Test status
Simulation time 3510276765 ps
CPU time 103.13 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:07:12 PM PDT 24
Peak memory 223876 kb
Host smart-48a39974-ad8c-443f-bc04-95de399ce34b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1887274415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.1887274415
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.3910752489
Short name T2272
Test name
Test status
Simulation time 8923377308 ps
CPU time 100.84 seconds
Started Aug 06 08:05:27 PM PDT 24
Finished Aug 06 08:07:08 PM PDT 24
Peak memory 207660 kb
Host smart-8f0f65d1-e8f0-4ca2-99a9-d3084cfd4bfe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3910752489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.3910752489
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.4250928861
Short name T725
Test name
Test status
Simulation time 178094339 ps
CPU time 0.94 seconds
Started Aug 06 08:05:29 PM PDT 24
Finished Aug 06 08:05:30 PM PDT 24
Peak memory 207376 kb
Host smart-213880d8-1de2-46c7-a2a3-e9989a476043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42509
28861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.4250928861
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2766244850
Short name T1047
Test name
Test status
Simulation time 22874768383 ps
CPU time 38.73 seconds
Started Aug 06 08:05:29 PM PDT 24
Finished Aug 06 08:06:08 PM PDT 24
Peak memory 207508 kb
Host smart-ce39aae3-4118-4784-9666-b6e3145dd57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27662
44850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2766244850
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.2041527483
Short name T2225
Test name
Test status
Simulation time 6205891106 ps
CPU time 8.53 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:05:31 PM PDT 24
Peak memory 216564 kb
Host smart-5b31084c-05c9-4ef6-b1b2-4c2d9bfcf3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20415
27483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2041527483
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.1613610468
Short name T2082
Test name
Test status
Simulation time 4067834941 ps
CPU time 38 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:06:01 PM PDT 24
Peak memory 223960 kb
Host smart-b182fcdf-346d-4ee0-a1af-4634fd56d5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16136
10468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1613610468
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1613413539
Short name T3091
Test name
Test status
Simulation time 2219705084 ps
CPU time 16.69 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:41 PM PDT 24
Peak memory 223920 kb
Host smart-0ba3a74a-e2b9-4fee-9b07-d7dabada86b3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1613413539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1613413539
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.2816140429
Short name T2343
Test name
Test status
Simulation time 251473375 ps
CPU time 1.03 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:05:24 PM PDT 24
Peak memory 207360 kb
Host smart-3f2e49c3-6bbc-42e8-8937-9a7ca4c6cad3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2816140429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.2816140429
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1364076182
Short name T858
Test name
Test status
Simulation time 250098221 ps
CPU time 1.02 seconds
Started Aug 06 08:05:43 PM PDT 24
Finished Aug 06 08:05:44 PM PDT 24
Peak memory 207400 kb
Host smart-950d400d-dc81-403e-a9e4-1e78139db785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13640
76182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1364076182
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.2465720846
Short name T2525
Test name
Test status
Simulation time 1724965047 ps
CPU time 13.98 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:41 PM PDT 24
Peak memory 217476 kb
Host smart-9387d14b-df47-4320-94a7-fe1c586ab98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24657
20846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.2465720846
Directory /workspace/23.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2607295559
Short name T3123
Test name
Test status
Simulation time 2475497025 ps
CPU time 18.25 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207616 kb
Host smart-4898cc27-247d-450a-bc5e-d3f9e7ee862b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2607295559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2607295559
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1400721645
Short name T975
Test name
Test status
Simulation time 165655169 ps
CPU time 0.86 seconds
Started Aug 06 08:05:22 PM PDT 24
Finished Aug 06 08:05:23 PM PDT 24
Peak memory 207356 kb
Host smart-f07bd947-251d-4102-b1b4-45fbd7843f4f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1400721645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1400721645
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.56851550
Short name T1462
Test name
Test status
Simulation time 149703962 ps
CPU time 0.83 seconds
Started Aug 06 08:05:31 PM PDT 24
Finished Aug 06 08:05:32 PM PDT 24
Peak memory 207340 kb
Host smart-28251241-4723-4e2f-95a0-1118d440b1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56851
550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.56851550
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2615810216
Short name T2668
Test name
Test status
Simulation time 201674700 ps
CPU time 0.95 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:40 PM PDT 24
Peak memory 207344 kb
Host smart-77c2b458-6b1b-4c00-9631-b4ce589e0cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26158
10216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2615810216
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.2086405564
Short name T706
Test name
Test status
Simulation time 189657990 ps
CPU time 0.86 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:27 PM PDT 24
Peak memory 207412 kb
Host smart-979e2b61-65a5-4e8e-a550-78b084556fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20864
05564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.2086405564
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3665493283
Short name T1851
Test name
Test status
Simulation time 194214961 ps
CPU time 0.91 seconds
Started Aug 06 08:05:28 PM PDT 24
Finished Aug 06 08:05:29 PM PDT 24
Peak memory 207388 kb
Host smart-1fa831fb-4cf8-4396-931c-90e0a404e031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36654
93283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3665493283
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.743092832
Short name T806
Test name
Test status
Simulation time 182380517 ps
CPU time 0.85 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207376 kb
Host smart-e6cfdc03-71ec-402f-93c8-8764a04c4efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74309
2832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.743092832
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.219929381
Short name T2399
Test name
Test status
Simulation time 173766959 ps
CPU time 0.82 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:05:39 PM PDT 24
Peak memory 207296 kb
Host smart-9e9f6598-3bf3-4b43-825b-cd2a8502a238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21992
9381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.219929381
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.4105523197
Short name T1599
Test name
Test status
Simulation time 293395393 ps
CPU time 1.1 seconds
Started Aug 06 08:05:30 PM PDT 24
Finished Aug 06 08:05:31 PM PDT 24
Peak memory 207348 kb
Host smart-92fc7206-6c15-4aec-b5f3-461dcecc0995
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4105523197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.4105523197
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1590304690
Short name T1030
Test name
Test status
Simulation time 191125476 ps
CPU time 0.85 seconds
Started Aug 06 08:05:27 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 207348 kb
Host smart-bd59b3e5-6d63-4dcb-9174-0013315c97e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15903
04690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1590304690
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2306308325
Short name T1204
Test name
Test status
Simulation time 35886109 ps
CPU time 0.68 seconds
Started Aug 06 08:05:34 PM PDT 24
Finished Aug 06 08:05:34 PM PDT 24
Peak memory 207288 kb
Host smart-7be9aa89-95e5-4ad7-968e-1171551148d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23063
08325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2306308325
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.4260081442
Short name T2251
Test name
Test status
Simulation time 22621388616 ps
CPU time 55.32 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:06:19 PM PDT 24
Peak memory 215832 kb
Host smart-be40bebd-30e4-4d35-86dc-7ebe90c66270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42600
81442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.4260081442
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2075011241
Short name T2118
Test name
Test status
Simulation time 185108653 ps
CPU time 0.89 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207396 kb
Host smart-2ccb58f0-1706-4233-aa1c-d72651f97192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20750
11241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2075011241
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2824086652
Short name T1651
Test name
Test status
Simulation time 244260311 ps
CPU time 1.01 seconds
Started Aug 06 08:05:30 PM PDT 24
Finished Aug 06 08:05:31 PM PDT 24
Peak memory 207356 kb
Host smart-0d15e4e1-c1db-47fc-a136-395793a3e018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28240
86652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2824086652
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.3596465053
Short name T1305
Test name
Test status
Simulation time 198315979 ps
CPU time 1 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207380 kb
Host smart-274b9fb5-9199-4c3b-9691-05b34f431bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35964
65053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.3596465053
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.241733225
Short name T1151
Test name
Test status
Simulation time 158176001 ps
CPU time 0.86 seconds
Started Aug 06 08:05:32 PM PDT 24
Finished Aug 06 08:05:33 PM PDT 24
Peak memory 207328 kb
Host smart-8740616e-f53d-4636-92a9-32f3a17188b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24173
3225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.241733225
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_full.2858807868
Short name T323
Test name
Test status
Simulation time 276875097 ps
CPU time 1.15 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:27 PM PDT 24
Peak memory 207392 kb
Host smart-f89d6f94-7fb7-45e4-bd09-6a0c606bae86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28588
07868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.2858807868
Directory /workspace/23.usbdev_rx_full/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3706880633
Short name T1947
Test name
Test status
Simulation time 154899710 ps
CPU time 0.92 seconds
Started Aug 06 08:05:31 PM PDT 24
Finished Aug 06 08:05:32 PM PDT 24
Peak memory 207288 kb
Host smart-241d43fe-da6c-43f6-ac4e-7f06950da6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37068
80633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3706880633
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2346527482
Short name T325
Test name
Test status
Simulation time 150722164 ps
CPU time 0.89 seconds
Started Aug 06 08:05:25 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 207396 kb
Host smart-70b8d8c3-d923-4d3d-804f-0b222521119b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
27482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2346527482
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3179063322
Short name T1641
Test name
Test status
Simulation time 249769142 ps
CPU time 1.06 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207380 kb
Host smart-084a7929-68c3-4261-a33c-2f30bf9304ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31790
63322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3179063322
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.4081479401
Short name T1561
Test name
Test status
Simulation time 1781031073 ps
CPU time 47.11 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 215800 kb
Host smart-9fc977f3-25ec-43f0-a493-a7616f289974
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4081479401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.4081479401
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3416856975
Short name T2021
Test name
Test status
Simulation time 178265359 ps
CPU time 0.86 seconds
Started Aug 06 08:05:31 PM PDT 24
Finished Aug 06 08:05:32 PM PDT 24
Peak memory 207412 kb
Host smart-43f98220-8c55-47bf-b0f6-d6476ec52caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34168
56975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3416856975
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3567203963
Short name T2551
Test name
Test status
Simulation time 201730304 ps
CPU time 0.9 seconds
Started Aug 06 08:05:30 PM PDT 24
Finished Aug 06 08:05:31 PM PDT 24
Peak memory 207336 kb
Host smart-37ffc4cf-e98d-44dd-8b61-d898a27110d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35672
03963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3567203963
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.2187286063
Short name T522
Test name
Test status
Simulation time 1142539800 ps
CPU time 2.68 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:27 PM PDT 24
Peak memory 207572 kb
Host smart-a5f08451-51ca-48b3-99e2-865398966967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21872
86063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2187286063
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.4156075398
Short name T895
Test name
Test status
Simulation time 1811938228 ps
CPU time 50.05 seconds
Started Aug 06 08:05:33 PM PDT 24
Finished Aug 06 08:06:23 PM PDT 24
Peak memory 217032 kb
Host smart-5f42e0c0-9e52-405c-8cf1-55177ca42dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41560
75398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.4156075398
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.2033502463
Short name T1213
Test name
Test status
Simulation time 1622541976 ps
CPU time 36.74 seconds
Started Aug 06 08:05:45 PM PDT 24
Finished Aug 06 08:06:22 PM PDT 24
Peak memory 207492 kb
Host smart-e1bae119-28d8-455c-aab3-bc88feab4da9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033502463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.2033502463
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.3275217473
Short name T1519
Test name
Test status
Simulation time 81087936 ps
CPU time 0.72 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:05:39 PM PDT 24
Peak memory 207444 kb
Host smart-1f6d6e48-9cb6-4d9c-b8b9-07c886e20a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3275217473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.3275217473
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.1768822812
Short name T2261
Test name
Test status
Simulation time 10697237522 ps
CPU time 15.39 seconds
Started Aug 06 08:05:27 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207688 kb
Host smart-9cef2ecd-510a-49c9-99f8-4b3723f75e61
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768822812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_disconnect.1768822812
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.3465411019
Short name T1458
Test name
Test status
Simulation time 19033258992 ps
CPU time 21 seconds
Started Aug 06 08:05:31 PM PDT 24
Finished Aug 06 08:05:52 PM PDT 24
Peak memory 207592 kb
Host smart-16413527-024a-49b3-8dbf-344ff6fbee8d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465411019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3465411019
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1968786956
Short name T3057
Test name
Test status
Simulation time 28469408892 ps
CPU time 33.23 seconds
Started Aug 06 08:05:36 PM PDT 24
Finished Aug 06 08:06:09 PM PDT 24
Peak memory 207676 kb
Host smart-0c30d856-ece3-4ef4-bd93-6fad7aee0f16
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968786956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.1968786956
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1549611601
Short name T2866
Test name
Test status
Simulation time 150262047 ps
CPU time 0.82 seconds
Started Aug 06 08:05:47 PM PDT 24
Finished Aug 06 08:05:48 PM PDT 24
Peak memory 207320 kb
Host smart-88a31a10-0128-4e65-8e36-c500eab0d351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15496
11601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1549611601
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.1183828085
Short name T3002
Test name
Test status
Simulation time 155563338 ps
CPU time 0.83 seconds
Started Aug 06 08:05:30 PM PDT 24
Finished Aug 06 08:05:31 PM PDT 24
Peak memory 207336 kb
Host smart-00f5560c-49ef-460d-83ca-eeddc5d1d6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11838
28085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.1183828085
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.136610442
Short name T1059
Test name
Test status
Simulation time 217523941 ps
CPU time 1.09 seconds
Started Aug 06 08:05:37 PM PDT 24
Finished Aug 06 08:05:40 PM PDT 24
Peak memory 207332 kb
Host smart-99b87432-9095-4a23-9da9-8d2b9d58b3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13661
0442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.136610442
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1429764777
Short name T2609
Test name
Test status
Simulation time 760748415 ps
CPU time 2.14 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 207288 kb
Host smart-15eff4f3-fad5-48a4-b2d5-ee13375ad671
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1429764777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1429764777
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.1371757920
Short name T2707
Test name
Test status
Simulation time 42479610608 ps
CPU time 69.4 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:06:34 PM PDT 24
Peak memory 207556 kb
Host smart-47d1d192-1c23-43b1-a2fc-a9db6ae7fa6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13717
57920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.1371757920
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.1841673001
Short name T1974
Test name
Test status
Simulation time 2059563518 ps
CPU time 17.18 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207552 kb
Host smart-c3cdeceb-42da-41b8-905a-043acff1ffb5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841673001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.1841673001
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2794297022
Short name T343
Test name
Test status
Simulation time 628507557 ps
CPU time 1.51 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 207264 kb
Host smart-886a4ba7-5788-41d8-bc47-38bf6764986a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27942
97022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2794297022
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1295723414
Short name T650
Test name
Test status
Simulation time 143912965 ps
CPU time 0.79 seconds
Started Aug 06 08:05:29 PM PDT 24
Finished Aug 06 08:05:30 PM PDT 24
Peak memory 207348 kb
Host smart-1b85896d-203c-450e-bc59-091dda11bb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12957
23414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1295723414
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2789361442
Short name T2152
Test name
Test status
Simulation time 36693340 ps
CPU time 0.69 seconds
Started Aug 06 08:05:35 PM PDT 24
Finished Aug 06 08:05:36 PM PDT 24
Peak memory 207344 kb
Host smart-077303c8-cc3a-4588-80c1-10e09592a770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27893
61442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2789361442
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.3900935277
Short name T2825
Test name
Test status
Simulation time 878686095 ps
CPU time 2.44 seconds
Started Aug 06 08:05:29 PM PDT 24
Finished Aug 06 08:05:31 PM PDT 24
Peak memory 207536 kb
Host smart-16f361bb-1817-4b1a-a262-ad9ef77e77a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39009
35277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.3900935277
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_types.3980770331
Short name T420
Test name
Test status
Simulation time 275687385 ps
CPU time 1.08 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:05:24 PM PDT 24
Peak memory 207356 kb
Host smart-6fc36d55-8144-41e2-ad92-92664d2a6f7e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3980770331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.3980770331
Directory /workspace/24.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2608801880
Short name T2197
Test name
Test status
Simulation time 188372331 ps
CPU time 2.28 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 207528 kb
Host smart-40673cb4-736f-453a-8842-e0413d478912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26088
01880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2608801880
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2937663467
Short name T2740
Test name
Test status
Simulation time 235172436 ps
CPU time 1.19 seconds
Started Aug 06 08:05:25 PM PDT 24
Finished Aug 06 08:05:26 PM PDT 24
Peak memory 215700 kb
Host smart-600a2e70-f2db-4636-af20-8f36c1c01bcc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2937663467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2937663467
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.604070983
Short name T744
Test name
Test status
Simulation time 139853496 ps
CPU time 0.81 seconds
Started Aug 06 08:05:31 PM PDT 24
Finished Aug 06 08:05:32 PM PDT 24
Peak memory 207292 kb
Host smart-cfc2a1e6-513c-49c6-af8a-ebb37285b7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60407
0983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.604070983
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1725278804
Short name T1918
Test name
Test status
Simulation time 241486716 ps
CPU time 0.94 seconds
Started Aug 06 08:05:36 PM PDT 24
Finished Aug 06 08:05:37 PM PDT 24
Peak memory 207372 kb
Host smart-353296ff-bf8a-49e7-b4c3-78efcc31726b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17252
78804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1725278804
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.4170166467
Short name T1624
Test name
Test status
Simulation time 2530383410 ps
CPU time 22.77 seconds
Started Aug 06 08:05:41 PM PDT 24
Finished Aug 06 08:06:04 PM PDT 24
Peak memory 224112 kb
Host smart-fc11d181-f921-4597-a440-1e2f472753c3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4170166467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.4170166467
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3786569239
Short name T2498
Test name
Test status
Simulation time 205975030 ps
CPU time 0.94 seconds
Started Aug 06 08:05:29 PM PDT 24
Finished Aug 06 08:05:30 PM PDT 24
Peak memory 207316 kb
Host smart-1374ed16-bac4-4cd9-9f04-84c7c36844d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37865
69239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3786569239
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.743615606
Short name T2190
Test name
Test status
Simulation time 9257988579 ps
CPU time 12.94 seconds
Started Aug 06 08:05:30 PM PDT 24
Finished Aug 06 08:05:43 PM PDT 24
Peak memory 207664 kb
Host smart-3adcad71-be7c-4278-9bc6-0526b265ea60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74361
5606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.743615606
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.2632253607
Short name T3114
Test name
Test status
Simulation time 4489062940 ps
CPU time 32.93 seconds
Started Aug 06 08:05:33 PM PDT 24
Finished Aug 06 08:06:06 PM PDT 24
Peak memory 224016 kb
Host smart-016c9ad2-c2c2-4200-8378-008be4599a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26322
53607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.2632253607
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1043098623
Short name T2937
Test name
Test status
Simulation time 2520158408 ps
CPU time 20.03 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:59 PM PDT 24
Peak memory 217004 kb
Host smart-1bd3be88-ef31-4fff-beb7-b7e713716efa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1043098623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1043098623
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.2644787969
Short name T1999
Test name
Test status
Simulation time 252419938 ps
CPU time 1.03 seconds
Started Aug 06 08:05:33 PM PDT 24
Finished Aug 06 08:05:34 PM PDT 24
Peak memory 207332 kb
Host smart-ef8b1ddb-ff69-48a5-bdb8-c447c94fe41f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2644787969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.2644787969
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1197408687
Short name T574
Test name
Test status
Simulation time 211711601 ps
CPU time 0.98 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207356 kb
Host smart-a7b0a4da-5652-49a6-974d-697880206558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11974
08687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1197408687
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.988426764
Short name T2334
Test name
Test status
Simulation time 1738830647 ps
CPU time 16.63 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:41 PM PDT 24
Peak memory 223892 kb
Host smart-e2f6b046-f33d-4e7c-a1ac-30f79d9718c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98842
6764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.988426764
Directory /workspace/24.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3753939900
Short name T883
Test name
Test status
Simulation time 2289492920 ps
CPU time 21.96 seconds
Started Aug 06 08:05:33 PM PDT 24
Finished Aug 06 08:05:55 PM PDT 24
Peak memory 217212 kb
Host smart-5a127027-c251-43fb-b749-c6bfc38a8ca2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3753939900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3753939900
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.2933379424
Short name T2929
Test name
Test status
Simulation time 155946425 ps
CPU time 0.9 seconds
Started Aug 06 08:05:32 PM PDT 24
Finished Aug 06 08:05:33 PM PDT 24
Peak memory 207380 kb
Host smart-94288330-41f0-4759-ae86-a5d7d546c8cc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2933379424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.2933379424
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2443596886
Short name T1317
Test name
Test status
Simulation time 191263189 ps
CPU time 0.86 seconds
Started Aug 06 08:05:32 PM PDT 24
Finished Aug 06 08:05:33 PM PDT 24
Peak memory 207344 kb
Host smart-d6f84f47-d768-438d-aea8-6fd80a568176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24435
96886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2443596886
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3648183896
Short name T2811
Test name
Test status
Simulation time 212574774 ps
CPU time 0.96 seconds
Started Aug 06 08:05:33 PM PDT 24
Finished Aug 06 08:05:34 PM PDT 24
Peak memory 207368 kb
Host smart-8008a3dc-f317-4e21-80a2-bd5e8ef51089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36481
83896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3648183896
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.3461057562
Short name T872
Test name
Test status
Simulation time 161670197 ps
CPU time 0.88 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:27 PM PDT 24
Peak memory 207352 kb
Host smart-47b0a1c8-9f81-47d2-91e0-a81d5536dbba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34610
57562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3461057562
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.394151368
Short name T2661
Test name
Test status
Simulation time 182921040 ps
CPU time 0.9 seconds
Started Aug 06 08:05:23 PM PDT 24
Finished Aug 06 08:05:24 PM PDT 24
Peak memory 207352 kb
Host smart-93d30f11-508b-4631-b00c-2f4fc2eee792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39415
1368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.394151368
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3613435602
Short name T1356
Test name
Test status
Simulation time 222884542 ps
CPU time 0.93 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:27 PM PDT 24
Peak memory 207360 kb
Host smart-b9b6dbc9-7381-4283-abeb-fdaf29b54a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36134
35602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3613435602
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.270928613
Short name T2693
Test name
Test status
Simulation time 148675320 ps
CPU time 0.84 seconds
Started Aug 06 08:05:34 PM PDT 24
Finished Aug 06 08:05:35 PM PDT 24
Peak memory 207376 kb
Host smart-1c2b31bd-a45a-436a-bd18-7a18fff65c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27092
8613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.270928613
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1213022210
Short name T3108
Test name
Test status
Simulation time 309797393 ps
CPU time 1.12 seconds
Started Aug 06 08:05:27 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 207356 kb
Host smart-b8acae12-00d6-4d93-87b4-63df1cf0985d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1213022210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1213022210
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3027016317
Short name T1128
Test name
Test status
Simulation time 139918683 ps
CPU time 0.78 seconds
Started Aug 06 08:05:30 PM PDT 24
Finished Aug 06 08:05:31 PM PDT 24
Peak memory 207348 kb
Host smart-ce178509-14b4-4643-b0e1-6d2c9aa50604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30270
16317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3027016317
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2455626658
Short name T1401
Test name
Test status
Simulation time 26280857 ps
CPU time 0.65 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:05:39 PM PDT 24
Peak memory 207320 kb
Host smart-8d35d38c-3be5-4f0f-9e50-52dbf869245e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24556
26658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2455626658
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.48319811
Short name T2812
Test name
Test status
Simulation time 21776285944 ps
CPU time 53.34 seconds
Started Aug 06 08:05:33 PM PDT 24
Finished Aug 06 08:06:26 PM PDT 24
Peak memory 215848 kb
Host smart-4515c86f-6521-4cd8-9ea0-5ee96dd00e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48319
811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.48319811
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3950983519
Short name T2799
Test name
Test status
Simulation time 190728948 ps
CPU time 0.92 seconds
Started Aug 06 08:05:31 PM PDT 24
Finished Aug 06 08:05:32 PM PDT 24
Peak memory 207364 kb
Host smart-0fdc4d60-c816-4cf9-b1cd-dc4663b6fb52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39509
83519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3950983519
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1194466084
Short name T2316
Test name
Test status
Simulation time 167825957 ps
CPU time 0.9 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:40 PM PDT 24
Peak memory 207388 kb
Host smart-60991833-64e2-419a-9504-739031dbb318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11944
66084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1194466084
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.4249409503
Short name T2891
Test name
Test status
Simulation time 185331750 ps
CPU time 0.9 seconds
Started Aug 06 08:05:27 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 207244 kb
Host smart-d47b8dd1-c30a-4f90-81ea-293e2454aed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42494
09503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.4249409503
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.1917070786
Short name T2502
Test name
Test status
Simulation time 173870062 ps
CPU time 0.87 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:05:39 PM PDT 24
Peak memory 207400 kb
Host smart-275b1240-5e75-4301-bb36-6ec03b13a098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19170
70786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.1917070786
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3074651912
Short name T2918
Test name
Test status
Simulation time 245043519 ps
CPU time 0.96 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207288 kb
Host smart-eba6628b-7c81-4b06-acf8-9b7971dd304c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30746
51912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3074651912
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_rx_full.3164475626
Short name T55
Test name
Test status
Simulation time 258312465 ps
CPU time 1.11 seconds
Started Aug 06 08:05:31 PM PDT 24
Finished Aug 06 08:05:33 PM PDT 24
Peak memory 207360 kb
Host smart-c1723aaf-8225-490e-9111-541dd3306f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31644
75626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.3164475626
Directory /workspace/24.usbdev_rx_full/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1050657162
Short name T1420
Test name
Test status
Simulation time 185102501 ps
CPU time 0.84 seconds
Started Aug 06 08:05:35 PM PDT 24
Finished Aug 06 08:05:36 PM PDT 24
Peak memory 207364 kb
Host smart-9fcca0f5-0642-44b5-9dba-f95354ce481f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506
57162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1050657162
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.377681181
Short name T2823
Test name
Test status
Simulation time 162449920 ps
CPU time 0.84 seconds
Started Aug 06 08:05:24 PM PDT 24
Finished Aug 06 08:05:25 PM PDT 24
Peak memory 207404 kb
Host smart-9312bf5f-8472-4386-99c2-9a54a64fd1b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37768
1181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.377681181
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.61687272
Short name T1792
Test name
Test status
Simulation time 227583487 ps
CPU time 1.01 seconds
Started Aug 06 08:05:27 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 207400 kb
Host smart-2659d23b-30f1-4974-b2ec-b414692d775a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61687
272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.61687272
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.378925171
Short name T2386
Test name
Test status
Simulation time 2865740918 ps
CPU time 31.03 seconds
Started Aug 06 08:05:36 PM PDT 24
Finished Aug 06 08:06:08 PM PDT 24
Peak memory 224016 kb
Host smart-648762fc-240c-47f9-8fcb-64bf78ad613b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=378925171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.378925171
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.335342660
Short name T2548
Test name
Test status
Simulation time 152244003 ps
CPU time 0.87 seconds
Started Aug 06 08:05:33 PM PDT 24
Finished Aug 06 08:05:34 PM PDT 24
Peak memory 207340 kb
Host smart-92d418c3-f3d6-4d46-9753-07484497235d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33534
2660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.335342660
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1100970096
Short name T1328
Test name
Test status
Simulation time 178614446 ps
CPU time 0.86 seconds
Started Aug 06 08:05:27 PM PDT 24
Finished Aug 06 08:05:28 PM PDT 24
Peak memory 207364 kb
Host smart-5177d630-9302-467a-9cd3-80503b8df2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11009
70096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1100970096
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.4017464017
Short name T526
Test name
Test status
Simulation time 1389409656 ps
CPU time 3.3 seconds
Started Aug 06 08:05:58 PM PDT 24
Finished Aug 06 08:06:01 PM PDT 24
Peak memory 207568 kb
Host smart-b979a20f-122f-44c9-a580-5eeee5972233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40174
64017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.4017464017
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.2310021058
Short name T3067
Test name
Test status
Simulation time 3813223107 ps
CPU time 110.29 seconds
Started Aug 06 08:05:30 PM PDT 24
Finished Aug 06 08:07:20 PM PDT 24
Peak memory 217228 kb
Host smart-5286889a-105a-4868-8465-780ee0376bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23100
21058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2310021058
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.2606492746
Short name T1911
Test name
Test status
Simulation time 3001811645 ps
CPU time 26.32 seconds
Started Aug 06 08:05:26 PM PDT 24
Finished Aug 06 08:05:53 PM PDT 24
Peak memory 207664 kb
Host smart-bb14e421-6219-438c-be86-5285d6179451
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606492746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_hos
t_handshake.2606492746
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.1132292400
Short name T2809
Test name
Test status
Simulation time 37571388 ps
CPU time 0.68 seconds
Started Aug 06 08:05:47 PM PDT 24
Finished Aug 06 08:05:48 PM PDT 24
Peak memory 207440 kb
Host smart-c3251487-02ed-48c1-a7e2-56962dbb885e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1132292400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.1132292400
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2562250104
Short name T1423
Test name
Test status
Simulation time 5009106089 ps
CPU time 7.37 seconds
Started Aug 06 08:05:33 PM PDT 24
Finished Aug 06 08:05:40 PM PDT 24
Peak memory 215788 kb
Host smart-0189dc26-30a3-4aa0-a4a0-5069237dffb2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562250104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.2562250104
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1696069770
Short name T1472
Test name
Test status
Simulation time 16486639048 ps
CPU time 20.48 seconds
Started Aug 06 08:05:33 PM PDT 24
Finished Aug 06 08:05:59 PM PDT 24
Peak memory 215768 kb
Host smart-b31ac673-169b-44db-86ec-e944fdbbd9f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696069770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1696069770
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.3840047427
Short name T1541
Test name
Test status
Simulation time 24322410236 ps
CPU time 37.28 seconds
Started Aug 06 08:05:28 PM PDT 24
Finished Aug 06 08:06:06 PM PDT 24
Peak memory 215780 kb
Host smart-380a66d0-97e8-4f12-947c-4088a0ac49d0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840047427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.3840047427
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3963783260
Short name T1384
Test name
Test status
Simulation time 206280998 ps
CPU time 0.89 seconds
Started Aug 06 08:05:35 PM PDT 24
Finished Aug 06 08:05:36 PM PDT 24
Peak memory 207400 kb
Host smart-6e8e6d72-191c-45d8-9a35-26ee2986c4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39637
83260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3963783260
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.4251689873
Short name T3095
Test name
Test status
Simulation time 153909337 ps
CPU time 0.82 seconds
Started Aug 06 08:05:37 PM PDT 24
Finished Aug 06 08:05:38 PM PDT 24
Peak memory 207256 kb
Host smart-1546a5a6-cbb2-486e-a19c-3ce1a795fd98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42516
89873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.4251689873
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.2105738107
Short name T2558
Test name
Test status
Simulation time 199255193 ps
CPU time 0.95 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:40 PM PDT 24
Peak memory 207340 kb
Host smart-20a5ec55-31e3-4831-a2ec-df5ea4cac173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21057
38107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.2105738107
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.3450784524
Short name T3089
Test name
Test status
Simulation time 688944183 ps
CPU time 1.87 seconds
Started Aug 06 08:05:36 PM PDT 24
Finished Aug 06 08:05:38 PM PDT 24
Peak memory 207208 kb
Host smart-dbe5eef8-3a0b-4c07-b0bd-f30c26d4ae47
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3450784524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.3450784524
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.3062175784
Short name T1681
Test name
Test status
Simulation time 35738355416 ps
CPU time 50.71 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:06:29 PM PDT 24
Peak memory 207740 kb
Host smart-d6615aa1-a365-4fb4-8a86-6c674078ab52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30621
75784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.3062175784
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.2938757727
Short name T1969
Test name
Test status
Simulation time 735770114 ps
CPU time 5.52 seconds
Started Aug 06 08:06:05 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 207532 kb
Host smart-19b4ee79-eec7-4d29-b3e6-b065bad1d45b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938757727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.2938757727
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.730794655
Short name T1162
Test name
Test status
Simulation time 957974394 ps
CPU time 2.13 seconds
Started Aug 06 08:06:00 PM PDT 24
Finished Aug 06 08:06:02 PM PDT 24
Peak memory 207360 kb
Host smart-5bbad9f3-9713-4ffb-8543-a0f702169bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73079
4655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.730794655
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.415751921
Short name T2175
Test name
Test status
Simulation time 143426731 ps
CPU time 0.82 seconds
Started Aug 06 08:05:37 PM PDT 24
Finished Aug 06 08:05:38 PM PDT 24
Peak memory 207348 kb
Host smart-24c2df07-8e7e-4781-9785-03ed231457d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41575
1921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.415751921
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.2434068124
Short name T1316
Test name
Test status
Simulation time 37413872 ps
CPU time 0.76 seconds
Started Aug 06 08:05:52 PM PDT 24
Finished Aug 06 08:05:53 PM PDT 24
Peak memory 207336 kb
Host smart-48685609-0e2d-4a39-b690-61140b52b09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24340
68124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2434068124
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.289304481
Short name T1612
Test name
Test status
Simulation time 789503908 ps
CPU time 2.02 seconds
Started Aug 06 08:05:44 PM PDT 24
Finished Aug 06 08:05:47 PM PDT 24
Peak memory 207524 kb
Host smart-7d47bdda-e78a-4648-b840-50e463c9a316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28930
4481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.289304481
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_types.3536648328
Short name T2773
Test name
Test status
Simulation time 294439616 ps
CPU time 1.03 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:41 PM PDT 24
Peak memory 207328 kb
Host smart-320738f7-56b2-4cd0-9557-50f730718cfb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3536648328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.3536648328
Directory /workspace/25.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2642222029
Short name T898
Test name
Test status
Simulation time 156027372 ps
CPU time 1.53 seconds
Started Aug 06 08:06:01 PM PDT 24
Finished Aug 06 08:06:02 PM PDT 24
Peak memory 207516 kb
Host smart-d3bc03d9-b7c3-42f7-9b13-13f354513ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26422
22029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2642222029
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.328080713
Short name T3059
Test name
Test status
Simulation time 225703650 ps
CPU time 1.04 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:05:39 PM PDT 24
Peak memory 215716 kb
Host smart-a7fbf5f3-c75b-421c-bfde-37ab66a1fe8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=328080713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.328080713
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1886809890
Short name T243
Test name
Test status
Simulation time 133942596 ps
CPU time 0.83 seconds
Started Aug 06 08:05:49 PM PDT 24
Finished Aug 06 08:05:50 PM PDT 24
Peak memory 207284 kb
Host smart-3137116f-9df1-4852-b710-81df66cb2d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18868
09890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1886809890
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.274595984
Short name T639
Test name
Test status
Simulation time 231364808 ps
CPU time 0.95 seconds
Started Aug 06 08:05:36 PM PDT 24
Finished Aug 06 08:05:37 PM PDT 24
Peak memory 207364 kb
Host smart-7a6e5cf2-6d63-4c44-85db-5c701b9f2d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27459
5984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.274595984
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.4090052866
Short name T2876
Test name
Test status
Simulation time 2949869979 ps
CPU time 31.06 seconds
Started Aug 06 08:05:36 PM PDT 24
Finished Aug 06 08:06:07 PM PDT 24
Peak memory 223928 kb
Host smart-1a41e5e1-75e0-4b69-aa96-7f39c2a7faa0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4090052866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.4090052866
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.914110171
Short name T88
Test name
Test status
Simulation time 4708497860 ps
CPU time 51.63 seconds
Started Aug 06 08:05:57 PM PDT 24
Finished Aug 06 08:06:48 PM PDT 24
Peak memory 207636 kb
Host smart-a525a58f-9c2d-480d-a2ac-ebe6f0205e2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=914110171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.914110171
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3429591621
Short name T2864
Test name
Test status
Simulation time 234590484 ps
CPU time 0.99 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:05:39 PM PDT 24
Peak memory 207332 kb
Host smart-16fba5fb-1639-4b16-bd8d-56903cc140c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34295
91621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3429591621
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.1731198290
Short name T1466
Test name
Test status
Simulation time 7195581647 ps
CPU time 10.32 seconds
Started Aug 06 08:05:44 PM PDT 24
Finished Aug 06 08:05:54 PM PDT 24
Peak memory 215760 kb
Host smart-32a5395b-c282-468e-b386-d9daf55fb290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17311
98290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.1731198290
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.229529216
Short name T2792
Test name
Test status
Simulation time 5455643842 ps
CPU time 7.23 seconds
Started Aug 06 08:05:47 PM PDT 24
Finished Aug 06 08:05:54 PM PDT 24
Peak memory 207568 kb
Host smart-95a7ab9a-4d11-4b83-88b8-7099f7e85cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22952
9216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.229529216
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.1261938752
Short name T1820
Test name
Test status
Simulation time 3455831032 ps
CPU time 25.22 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:06:04 PM PDT 24
Peak memory 223992 kb
Host smart-c49ced17-bc83-406a-97fa-7fc6d1a6032b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12619
38752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.1261938752
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.657440816
Short name T1645
Test name
Test status
Simulation time 3932336308 ps
CPU time 43.47 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:06:22 PM PDT 24
Peak memory 217516 kb
Host smart-b9776353-883a-4bad-a58d-67296d95fba2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=657440816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.657440816
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2308396827
Short name T1476
Test name
Test status
Simulation time 276524005 ps
CPU time 1.06 seconds
Started Aug 06 08:05:40 PM PDT 24
Finished Aug 06 08:05:41 PM PDT 24
Peak memory 207380 kb
Host smart-8bf705f8-e010-4df4-8d58-ba178d78fee1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2308396827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2308396827
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2964956573
Short name T643
Test name
Test status
Simulation time 189709981 ps
CPU time 0.91 seconds
Started Aug 06 08:05:43 PM PDT 24
Finished Aug 06 08:05:44 PM PDT 24
Peak memory 207384 kb
Host smart-6460f708-2d9d-4210-8b34-90aed70b164c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29649
56573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2964956573
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2865757392
Short name T3069
Test name
Test status
Simulation time 3065473394 ps
CPU time 23.01 seconds
Started Aug 06 08:05:40 PM PDT 24
Finished Aug 06 08:06:03 PM PDT 24
Peak memory 215880 kb
Host smart-0b08ff44-bb52-441a-a596-6963c4bae95f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2865757392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2865757392
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.4042588867
Short name T2477
Test name
Test status
Simulation time 161970653 ps
CPU time 0.85 seconds
Started Aug 06 08:05:41 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207316 kb
Host smart-2425765a-5b75-49c8-a24d-139f9fad7c1e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4042588867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.4042588867
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1863631975
Short name T1525
Test name
Test status
Simulation time 162467061 ps
CPU time 0.85 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:40 PM PDT 24
Peak memory 207292 kb
Host smart-1912d29c-640e-41fd-ace5-c67adf2fd3dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18636
31975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1863631975
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.256502219
Short name T2610
Test name
Test status
Simulation time 184426463 ps
CPU time 0.91 seconds
Started Aug 06 08:05:41 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207420 kb
Host smart-fc48d410-0eff-4a5c-8335-26aa7d56073d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25650
2219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.256502219
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1305009736
Short name T1981
Test name
Test status
Simulation time 180956001 ps
CPU time 0.94 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:05:39 PM PDT 24
Peak memory 207304 kb
Host smart-65ac4f39-5af7-4002-9f17-911eba3da8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13050
09736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1305009736
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.898376321
Short name T647
Test name
Test status
Simulation time 158067202 ps
CPU time 0.85 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:40 PM PDT 24
Peak memory 207416 kb
Host smart-f31e7fec-50f6-4c22-b20e-7a82aec096c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89837
6321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.898376321
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3520529412
Short name T1398
Test name
Test status
Simulation time 187949131 ps
CPU time 0.89 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:40 PM PDT 24
Peak memory 207336 kb
Host smart-a56bb56b-2772-436a-887b-05e3f2023b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35205
29412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3520529412
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3075061066
Short name T200
Test name
Test status
Simulation time 167603733 ps
CPU time 0.91 seconds
Started Aug 06 08:05:52 PM PDT 24
Finished Aug 06 08:05:53 PM PDT 24
Peak memory 207380 kb
Host smart-e76bcb1a-d7f4-4346-a523-fa6b7ab6097e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30750
61066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3075061066
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.171907777
Short name T3046
Test name
Test status
Simulation time 221787394 ps
CPU time 0.94 seconds
Started Aug 06 08:05:58 PM PDT 24
Finished Aug 06 08:05:59 PM PDT 24
Peak memory 207376 kb
Host smart-fff7b2b7-35c5-4c1c-b5f3-0c6bc4d52c76
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=171907777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.171907777
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1846595833
Short name T2599
Test name
Test status
Simulation time 140778404 ps
CPU time 0.83 seconds
Started Aug 06 08:05:41 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207352 kb
Host smart-ce5fab82-347e-4c58-a970-5b2532018f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18465
95833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1846595833
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1271986227
Short name T1617
Test name
Test status
Simulation time 61923229 ps
CPU time 0.72 seconds
Started Aug 06 08:05:47 PM PDT 24
Finished Aug 06 08:05:47 PM PDT 24
Peak memory 207276 kb
Host smart-b3693dd1-7237-46be-9032-ef48e3b078a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12719
86227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1271986227
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.348663153
Short name T1962
Test name
Test status
Simulation time 9930414606 ps
CPU time 26.29 seconds
Started Aug 06 08:05:40 PM PDT 24
Finished Aug 06 08:06:07 PM PDT 24
Peak memory 215736 kb
Host smart-cdb712ba-dcff-451e-b3fb-d53b1c204794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34866
3153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.348663153
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2004301643
Short name T1536
Test name
Test status
Simulation time 189229339 ps
CPU time 0.89 seconds
Started Aug 06 08:05:36 PM PDT 24
Finished Aug 06 08:05:37 PM PDT 24
Peak memory 207380 kb
Host smart-3e524d7f-b14c-4902-ae51-7a5e6f6ce2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
01643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2004301643
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1929611578
Short name T16
Test name
Test status
Simulation time 172625413 ps
CPU time 0.94 seconds
Started Aug 06 08:05:41 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207352 kb
Host smart-6987da8d-76e4-4e80-bb1b-a85c26d9f97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19296
11578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1929611578
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.4070865362
Short name T2578
Test name
Test status
Simulation time 178353065 ps
CPU time 0.89 seconds
Started Aug 06 08:05:47 PM PDT 24
Finished Aug 06 08:05:48 PM PDT 24
Peak memory 207324 kb
Host smart-0b272d62-8b5a-4191-9d99-2429b808f246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40708
65362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.4070865362
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.819644735
Short name T1582
Test name
Test status
Simulation time 159591361 ps
CPU time 0.83 seconds
Started Aug 06 08:05:36 PM PDT 24
Finished Aug 06 08:05:37 PM PDT 24
Peak memory 207236 kb
Host smart-a54b3294-3f89-4c3c-b99e-dae7be53e554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81964
4735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.819644735
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1264963690
Short name T1174
Test name
Test status
Simulation time 195083369 ps
CPU time 0.87 seconds
Started Aug 06 08:05:37 PM PDT 24
Finished Aug 06 08:05:38 PM PDT 24
Peak memory 207316 kb
Host smart-fd524d34-7354-4ab2-b55e-44c13586a203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12649
63690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1264963690
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_rx_full.774020112
Short name T1485
Test name
Test status
Simulation time 259012707 ps
CPU time 1.11 seconds
Started Aug 06 08:05:42 PM PDT 24
Finished Aug 06 08:05:43 PM PDT 24
Peak memory 207352 kb
Host smart-3d0632e3-fa30-44ba-91a2-9505802fc4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77402
0112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.774020112
Directory /workspace/25.usbdev_rx_full/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3627863530
Short name T2223
Test name
Test status
Simulation time 149573149 ps
CPU time 0.83 seconds
Started Aug 06 08:05:45 PM PDT 24
Finished Aug 06 08:05:46 PM PDT 24
Peak memory 207320 kb
Host smart-2d48c541-dab8-4c40-9a1c-e80231080b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36278
63530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3627863530
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1009982285
Short name T2246
Test name
Test status
Simulation time 153491656 ps
CPU time 0.88 seconds
Started Aug 06 08:05:40 PM PDT 24
Finished Aug 06 08:05:41 PM PDT 24
Peak memory 207396 kb
Host smart-2ba1b506-183c-4da3-854f-4d53d88a8e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10099
82285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1009982285
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.4110911991
Short name T1239
Test name
Test status
Simulation time 243614260 ps
CPU time 1.01 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:40 PM PDT 24
Peak memory 207356 kb
Host smart-9891075c-b59e-47ca-9caa-1a2b26a385fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41109
11991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.4110911991
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3499620337
Short name T3101
Test name
Test status
Simulation time 2082920928 ps
CPU time 54.92 seconds
Started Aug 06 08:05:44 PM PDT 24
Finished Aug 06 08:06:39 PM PDT 24
Peak memory 223844 kb
Host smart-dd3c754c-56d7-4482-bc27-fe863df7d33d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3499620337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3499620337
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3903326619
Short name T1421
Test name
Test status
Simulation time 208080772 ps
CPU time 0.92 seconds
Started Aug 06 08:05:37 PM PDT 24
Finished Aug 06 08:05:38 PM PDT 24
Peak memory 207320 kb
Host smart-dc43b238-e7e8-4f62-80a6-d1ed47888ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39033
26619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3903326619
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3133737730
Short name T2315
Test name
Test status
Simulation time 157121751 ps
CPU time 0.87 seconds
Started Aug 06 08:05:50 PM PDT 24
Finished Aug 06 08:05:51 PM PDT 24
Peak memory 207292 kb
Host smart-587fc665-2ac7-42b5-8be9-acfe6a502379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31337
37730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3133737730
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.176689601
Short name T2480
Test name
Test status
Simulation time 448563114 ps
CPU time 1.41 seconds
Started Aug 06 08:05:41 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207336 kb
Host smart-86988ac1-bb5c-421b-b4e7-d74ef63a4a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17668
9601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.176689601
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.3374903761
Short name T2608
Test name
Test status
Simulation time 1675187779 ps
CPU time 11.83 seconds
Started Aug 06 08:05:36 PM PDT 24
Finished Aug 06 08:05:48 PM PDT 24
Peak memory 217160 kb
Host smart-9e2cae29-62ff-4735-a7ba-79fa1d281b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33749
03761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.3374903761
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.901740056
Short name T2917
Test name
Test status
Simulation time 290422009 ps
CPU time 4.35 seconds
Started Aug 06 08:05:36 PM PDT 24
Finished Aug 06 08:05:41 PM PDT 24
Peak memory 207620 kb
Host smart-521948c6-536e-4c2b-9d7d-3b8c1c2e8bf3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901740056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_host
_handshake.901740056
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.4154172210
Short name T1395
Test name
Test status
Simulation time 63926095 ps
CPU time 0.7 seconds
Started Aug 06 08:05:49 PM PDT 24
Finished Aug 06 08:05:50 PM PDT 24
Peak memory 207456 kb
Host smart-c79ceb52-6677-4829-af86-79a733a178c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4154172210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.4154172210
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3126122914
Short name T254
Test name
Test status
Simulation time 11010614332 ps
CPU time 13.89 seconds
Started Aug 06 08:05:35 PM PDT 24
Finished Aug 06 08:05:49 PM PDT 24
Peak memory 207636 kb
Host smart-21954d7b-3043-44ba-acbc-96ef990729b4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126122914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.3126122914
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3513527890
Short name T9
Test name
Test status
Simulation time 15215305886 ps
CPU time 20.95 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:06:00 PM PDT 24
Peak memory 215836 kb
Host smart-cbd34a1b-20d7-4e1e-82bf-f5bde465ce99
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513527890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3513527890
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.4231226595
Short name T1982
Test name
Test status
Simulation time 31423741005 ps
CPU time 37.43 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:06:16 PM PDT 24
Peak memory 207620 kb
Host smart-777a5066-b466-4972-928b-98ab8ef290b8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231226595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.4231226595
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3613978786
Short name T1637
Test name
Test status
Simulation time 191534820 ps
CPU time 0.9 seconds
Started Aug 06 08:05:41 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207256 kb
Host smart-c9e35e88-ece3-4b68-b4ca-6ab9b99c0d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36139
78786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3613978786
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3439941051
Short name T2690
Test name
Test status
Simulation time 150250551 ps
CPU time 0.86 seconds
Started Aug 06 08:05:48 PM PDT 24
Finished Aug 06 08:05:49 PM PDT 24
Peak memory 207380 kb
Host smart-ae0ed3c4-1df4-4d25-b4d6-c4888bcebb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34399
41051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3439941051
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.2966623724
Short name T1778
Test name
Test status
Simulation time 410676356 ps
CPU time 1.46 seconds
Started Aug 06 08:05:58 PM PDT 24
Finished Aug 06 08:06:00 PM PDT 24
Peak memory 207356 kb
Host smart-1536799d-f524-4f94-8b38-260022aa020f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29666
23724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.2966623724
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1671714351
Short name T1433
Test name
Test status
Simulation time 549726905 ps
CPU time 1.64 seconds
Started Aug 06 08:05:41 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207384 kb
Host smart-a426e3ab-3313-40e9-b69d-97421b3ba8c0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1671714351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1671714351
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.2248184828
Short name T2362
Test name
Test status
Simulation time 18357413943 ps
CPU time 29.05 seconds
Started Aug 06 08:05:42 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 207660 kb
Host smart-4430dc8f-f243-4632-944d-149ff6bd189c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22481
84828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.2248184828
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.2273606804
Short name T1290
Test name
Test status
Simulation time 878575953 ps
CPU time 20.02 seconds
Started Aug 06 08:05:40 PM PDT 24
Finished Aug 06 08:06:00 PM PDT 24
Peak memory 207568 kb
Host smart-fd8e857f-0ddd-4d93-a5a7-df6add986aa3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273606804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.2273606804
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.2965757334
Short name T2174
Test name
Test status
Simulation time 809408538 ps
CPU time 1.95 seconds
Started Aug 06 08:05:42 PM PDT 24
Finished Aug 06 08:05:44 PM PDT 24
Peak memory 207340 kb
Host smart-b6f3fd88-7730-4062-a81e-3d2b9c38c61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29657
57334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.2965757334
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2054924399
Short name T2454
Test name
Test status
Simulation time 159978919 ps
CPU time 0.85 seconds
Started Aug 06 08:05:42 PM PDT 24
Finished Aug 06 08:05:43 PM PDT 24
Peak memory 207316 kb
Host smart-6cb42cbd-dea9-4cdc-a216-75152a6c1aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20549
24399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2054924399
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3634732354
Short name T2026
Test name
Test status
Simulation time 48720563 ps
CPU time 0.7 seconds
Started Aug 06 08:05:40 PM PDT 24
Finished Aug 06 08:05:41 PM PDT 24
Peak memory 207408 kb
Host smart-5a6b81b2-e40a-487a-b4dd-6ae51b6a689b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36347
32354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3634732354
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2269646197
Short name T851
Test name
Test status
Simulation time 938662116 ps
CPU time 2.52 seconds
Started Aug 06 08:05:52 PM PDT 24
Finished Aug 06 08:05:55 PM PDT 24
Peak memory 206952 kb
Host smart-1ee7d2eb-9c8c-4f87-bccd-3ef4276de828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22696
46197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2269646197
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_types.1162013319
Short name T453
Test name
Test status
Simulation time 860129848 ps
CPU time 1.86 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:41 PM PDT 24
Peak memory 207328 kb
Host smart-51dbbfca-0da4-46c2-86dc-53a3ce919b8b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1162013319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.1162013319
Directory /workspace/26.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.4097804572
Short name T1686
Test name
Test status
Simulation time 187029018 ps
CPU time 1.98 seconds
Started Aug 06 08:05:40 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207588 kb
Host smart-40d73d5d-c73b-4a13-a147-9b062fb529fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40978
04572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.4097804572
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3814940132
Short name T2265
Test name
Test status
Simulation time 218978711 ps
CPU time 1.08 seconds
Started Aug 06 08:05:55 PM PDT 24
Finished Aug 06 08:05:56 PM PDT 24
Peak memory 207564 kb
Host smart-7b358a42-26ea-4311-9d6e-4d9a4674a108
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3814940132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3814940132
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3705276862
Short name T666
Test name
Test status
Simulation time 201872675 ps
CPU time 0.85 seconds
Started Aug 06 08:05:52 PM PDT 24
Finished Aug 06 08:05:53 PM PDT 24
Peak memory 206724 kb
Host smart-bb4c28f7-533c-4e37-8a61-fb58961e4e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37052
76862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3705276862
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3827603133
Short name T719
Test name
Test status
Simulation time 214139840 ps
CPU time 1.02 seconds
Started Aug 06 08:05:42 PM PDT 24
Finished Aug 06 08:05:43 PM PDT 24
Peak memory 207364 kb
Host smart-146a20f5-570c-4d7b-b70e-0d40113e0fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38276
03133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3827603133
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.1220841371
Short name T1145
Test name
Test status
Simulation time 2771116572 ps
CPU time 78.56 seconds
Started Aug 06 08:05:40 PM PDT 24
Finished Aug 06 08:06:59 PM PDT 24
Peak memory 217768 kb
Host smart-f9e71ac8-e30c-4275-a680-c1e6e8506deb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1220841371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.1220841371
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.4288543875
Short name T2415
Test name
Test status
Simulation time 12755447216 ps
CPU time 157.74 seconds
Started Aug 06 08:05:40 PM PDT 24
Finished Aug 06 08:08:18 PM PDT 24
Peak memory 207564 kb
Host smart-b35827ce-af3b-40f8-beaf-4cea95cdb96a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4288543875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.4288543875
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.2490639045
Short name T2121
Test name
Test status
Simulation time 176562334 ps
CPU time 0.88 seconds
Started Aug 06 08:05:55 PM PDT 24
Finished Aug 06 08:05:56 PM PDT 24
Peak memory 207352 kb
Host smart-a4061d30-3b6c-4f1a-8e75-8a3ad1458f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24906
39045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.2490639045
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2311380467
Short name T1874
Test name
Test status
Simulation time 4243309058 ps
CPU time 5.72 seconds
Started Aug 06 08:05:54 PM PDT 24
Finished Aug 06 08:06:00 PM PDT 24
Peak memory 207656 kb
Host smart-7ac333a4-2549-43c3-9352-2b56b14a0579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23113
80467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2311380467
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.3212971411
Short name T640
Test name
Test status
Simulation time 3533299324 ps
CPU time 33.56 seconds
Started Aug 06 08:05:40 PM PDT 24
Finished Aug 06 08:06:13 PM PDT 24
Peak memory 224040 kb
Host smart-04c7a12c-899f-438a-8b0c-50872a95cb85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32129
71411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.3212971411
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.572221873
Short name T2074
Test name
Test status
Simulation time 3956336496 ps
CPU time 30.03 seconds
Started Aug 06 08:05:42 PM PDT 24
Finished Aug 06 08:06:13 PM PDT 24
Peak memory 215892 kb
Host smart-cfd60df5-9265-4df4-a8c2-e109ed6b803c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=572221873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.572221873
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3609987325
Short name T2593
Test name
Test status
Simulation time 244216512 ps
CPU time 1.03 seconds
Started Aug 06 08:05:42 PM PDT 24
Finished Aug 06 08:05:43 PM PDT 24
Peak memory 207348 kb
Host smart-db36f250-6582-4e23-985e-dca5f50d1493
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3609987325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3609987325
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3563968818
Short name T2678
Test name
Test status
Simulation time 209600085 ps
CPU time 0.94 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:05:39 PM PDT 24
Peak memory 207348 kb
Host smart-794af53f-a763-4e87-9622-a4e7e25b5825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35639
68818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3563968818
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.3518214087
Short name T2914
Test name
Test status
Simulation time 1697653583 ps
CPU time 46.69 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:06:26 PM PDT 24
Peak memory 217224 kb
Host smart-4a55ab8d-cbe6-4b38-80e3-ce1b4c6de16a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3518214087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.3518214087
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3322524056
Short name T29
Test name
Test status
Simulation time 206729342 ps
CPU time 0.9 seconds
Started Aug 06 08:05:56 PM PDT 24
Finished Aug 06 08:05:57 PM PDT 24
Peak memory 207408 kb
Host smart-7266f23f-6493-498c-9876-6a652f61c2a7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3322524056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3322524056
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3347355531
Short name T783
Test name
Test status
Simulation time 143485423 ps
CPU time 0.81 seconds
Started Aug 06 08:06:04 PM PDT 24
Finished Aug 06 08:06:05 PM PDT 24
Peak memory 207336 kb
Host smart-78e5c18f-aa80-49d9-844e-76128732a5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33473
55531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3347355531
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3723576764
Short name T165
Test name
Test status
Simulation time 235499006 ps
CPU time 1 seconds
Started Aug 06 08:05:56 PM PDT 24
Finished Aug 06 08:05:57 PM PDT 24
Peak memory 207332 kb
Host smart-512c1960-eed3-4db5-8c4c-2eef05bc92eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37235
76764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3723576764
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.581554696
Short name T1775
Test name
Test status
Simulation time 168784255 ps
CPU time 0.85 seconds
Started Aug 06 08:05:40 PM PDT 24
Finished Aug 06 08:05:41 PM PDT 24
Peak memory 207444 kb
Host smart-f1fb0ab4-fcbc-422c-9d44-a71c6a6415b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58155
4696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.581554696
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1596038511
Short name T1748
Test name
Test status
Simulation time 155359954 ps
CPU time 0.85 seconds
Started Aug 06 08:05:37 PM PDT 24
Finished Aug 06 08:05:38 PM PDT 24
Peak memory 207332 kb
Host smart-1f58287e-00f1-4909-a2b3-63c5c69d30ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15960
38511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1596038511
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.128079650
Short name T2434
Test name
Test status
Simulation time 201527350 ps
CPU time 0.93 seconds
Started Aug 06 08:05:55 PM PDT 24
Finished Aug 06 08:05:56 PM PDT 24
Peak memory 207332 kb
Host smart-4cc0a2cc-61f0-4f4f-b168-f4b69ad1f396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12807
9650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.128079650
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.774121579
Short name T2532
Test name
Test status
Simulation time 151955350 ps
CPU time 0.82 seconds
Started Aug 06 08:05:55 PM PDT 24
Finished Aug 06 08:05:56 PM PDT 24
Peak memory 207340 kb
Host smart-64c8c0a9-7ff6-4f6f-82e9-fc0359a221a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77412
1579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.774121579
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.2115183440
Short name T1318
Test name
Test status
Simulation time 270072163 ps
CPU time 1.03 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:05:39 PM PDT 24
Peak memory 207368 kb
Host smart-ed1ff594-92e3-4d55-92d7-74d80a425c6c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2115183440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.2115183440
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.868442823
Short name T2300
Test name
Test status
Simulation time 145555397 ps
CPU time 0.85 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:40 PM PDT 24
Peak memory 207388 kb
Host smart-3db22580-b249-4e14-87c3-a0b13dd5fa6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86844
2823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.868442823
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3710064122
Short name T1709
Test name
Test status
Simulation time 36139379 ps
CPU time 0.7 seconds
Started Aug 06 08:05:39 PM PDT 24
Finished Aug 06 08:05:45 PM PDT 24
Peak memory 207368 kb
Host smart-97bba23e-276c-4787-a263-eed08fb82110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37100
64122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3710064122
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1448541750
Short name T280
Test name
Test status
Simulation time 19368752361 ps
CPU time 46.84 seconds
Started Aug 06 08:05:41 PM PDT 24
Finished Aug 06 08:06:28 PM PDT 24
Peak memory 215964 kb
Host smart-0154e981-c4bd-4ce0-9f5d-9b96f3d8d7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14485
41750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1448541750
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2100434033
Short name T2512
Test name
Test status
Simulation time 161815148 ps
CPU time 0.86 seconds
Started Aug 06 08:05:38 PM PDT 24
Finished Aug 06 08:05:39 PM PDT 24
Peak memory 207328 kb
Host smart-54f1725a-73dc-4a6f-ae1c-995e9cba9bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21004
34033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2100434033
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1527131240
Short name T900
Test name
Test status
Simulation time 184706403 ps
CPU time 0.92 seconds
Started Aug 06 08:05:46 PM PDT 24
Finished Aug 06 08:05:47 PM PDT 24
Peak memory 206644 kb
Host smart-94d4a806-438c-4d13-aa97-077dcdabc156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15271
31240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1527131240
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.3935365334
Short name T2307
Test name
Test status
Simulation time 243346939 ps
CPU time 0.93 seconds
Started Aug 06 08:05:45 PM PDT 24
Finished Aug 06 08:05:46 PM PDT 24
Peak memory 207300 kb
Host smart-38db91a2-ba47-42d7-bad4-4bfd73568be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39353
65334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3935365334
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.528682940
Short name T1929
Test name
Test status
Simulation time 205177735 ps
CPU time 0.93 seconds
Started Aug 06 08:06:03 PM PDT 24
Finished Aug 06 08:06:04 PM PDT 24
Peak memory 207316 kb
Host smart-6c5ec964-f084-44dc-970b-83c7b429ef4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52868
2940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.528682940
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1671365407
Short name T821
Test name
Test status
Simulation time 169510418 ps
CPU time 0.85 seconds
Started Aug 06 08:05:41 PM PDT 24
Finished Aug 06 08:05:42 PM PDT 24
Peak memory 207324 kb
Host smart-20dc7fe8-50df-4261-ae03-a15d7c17d2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16713
65407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1671365407
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_rx_full.3377315877
Short name T703
Test name
Test status
Simulation time 320408652 ps
CPU time 1.2 seconds
Started Aug 06 08:05:59 PM PDT 24
Finished Aug 06 08:06:01 PM PDT 24
Peak memory 207344 kb
Host smart-136291a7-7301-4f9f-b87f-7d26cb7dca9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33773
15877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.3377315877
Directory /workspace/26.usbdev_rx_full/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.60927687
Short name T1116
Test name
Test status
Simulation time 157035418 ps
CPU time 0.82 seconds
Started Aug 06 08:05:47 PM PDT 24
Finished Aug 06 08:05:48 PM PDT 24
Peak memory 207312 kb
Host smart-ba364816-50ca-49dd-81f3-d1edeaf67a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60927
687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.60927687
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3958580064
Short name T602
Test name
Test status
Simulation time 157143976 ps
CPU time 0.88 seconds
Started Aug 06 08:05:58 PM PDT 24
Finished Aug 06 08:05:59 PM PDT 24
Peak memory 207344 kb
Host smart-2a4af4bf-c36b-4ef6-88cd-14bb88e0211f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
80064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3958580064
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.389088406
Short name T1604
Test name
Test status
Simulation time 226735328 ps
CPU time 1.05 seconds
Started Aug 06 08:06:02 PM PDT 24
Finished Aug 06 08:06:03 PM PDT 24
Peak memory 207372 kb
Host smart-a0f6171c-1b54-459a-b848-a2c19cf107a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38908
8406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.389088406
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.4149720927
Short name T1531
Test name
Test status
Simulation time 1846786767 ps
CPU time 12.89 seconds
Started Aug 06 08:05:37 PM PDT 24
Finished Aug 06 08:05:50 PM PDT 24
Peak memory 215772 kb
Host smart-2cf4f09f-ba39-4eec-a868-628e8ec8459c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4149720927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.4149720927
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1646715360
Short name T1273
Test name
Test status
Simulation time 209773286 ps
CPU time 0.91 seconds
Started Aug 06 08:05:56 PM PDT 24
Finished Aug 06 08:05:57 PM PDT 24
Peak memory 207348 kb
Host smart-4ebea4d3-cbd8-4353-b419-2d976f50a728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16467
15360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1646715360
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.192171353
Short name T2192
Test name
Test status
Simulation time 220318978 ps
CPU time 0.96 seconds
Started Aug 06 08:06:03 PM PDT 24
Finished Aug 06 08:06:04 PM PDT 24
Peak memory 207344 kb
Host smart-1e1a0ebf-c1fc-4986-be42-dfceb930e896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19217
1353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.192171353
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.1132935878
Short name T3061
Test name
Test status
Simulation time 1086261356 ps
CPU time 2.54 seconds
Started Aug 06 08:06:05 PM PDT 24
Finished Aug 06 08:06:08 PM PDT 24
Peak memory 207516 kb
Host smart-70067559-cec9-4581-ace5-8f7ebaa6e062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11329
35878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.1132935878
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.3576513620
Short name T2078
Test name
Test status
Simulation time 2695431203 ps
CPU time 27.67 seconds
Started Aug 06 08:06:05 PM PDT 24
Finished Aug 06 08:06:33 PM PDT 24
Peak memory 217492 kb
Host smart-71108919-312f-44ca-85ba-c91cf23addf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35765
13620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.3576513620
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.1699189253
Short name T1434
Test name
Test status
Simulation time 1546956841 ps
CPU time 13.53 seconds
Started Aug 06 08:05:41 PM PDT 24
Finished Aug 06 08:05:55 PM PDT 24
Peak memory 207528 kb
Host smart-fdc7996d-192d-4a74-8ba2-f4a67e1434ad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699189253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.1699189253
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.1171722225
Short name T1085
Test name
Test status
Simulation time 79682154 ps
CPU time 0.75 seconds
Started Aug 06 08:06:02 PM PDT 24
Finished Aug 06 08:06:03 PM PDT 24
Peak memory 207460 kb
Host smart-37f80b0b-3c9a-4f87-8819-3bcdb19d5010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1171722225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.1171722225
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.3945281944
Short name T733
Test name
Test status
Simulation time 11453376325 ps
CPU time 16.81 seconds
Started Aug 06 08:06:04 PM PDT 24
Finished Aug 06 08:06:21 PM PDT 24
Peak memory 207852 kb
Host smart-72173601-f3a2-4845-ad5f-9878dc477302
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945281944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.3945281944
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2013208098
Short name T2110
Test name
Test status
Simulation time 21277039646 ps
CPU time 23.16 seconds
Started Aug 06 08:05:46 PM PDT 24
Finished Aug 06 08:06:10 PM PDT 24
Peak memory 207620 kb
Host smart-32edd02e-1174-4880-ad98-0803ab3ef12f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013208098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2013208098
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3545902758
Short name T1292
Test name
Test status
Simulation time 24973056347 ps
CPU time 36.73 seconds
Started Aug 06 08:05:44 PM PDT 24
Finished Aug 06 08:06:20 PM PDT 24
Peak memory 215776 kb
Host smart-e53234dc-c9fa-4c5f-bcc9-060cda5b3d04
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545902758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.3545902758
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1116906577
Short name T684
Test name
Test status
Simulation time 162948849 ps
CPU time 0.85 seconds
Started Aug 06 08:05:44 PM PDT 24
Finished Aug 06 08:05:45 PM PDT 24
Peak memory 207332 kb
Host smart-c54574e8-3c02-4617-b2f7-bedce286b3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11169
06577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1116906577
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.451895200
Short name T2682
Test name
Test status
Simulation time 153262293 ps
CPU time 0.83 seconds
Started Aug 06 08:06:06 PM PDT 24
Finished Aug 06 08:06:07 PM PDT 24
Peak memory 207312 kb
Host smart-8182f9c4-3243-4cf0-9928-d412fd65a4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45189
5200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.451895200
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.1310444990
Short name T2560
Test name
Test status
Simulation time 453431650 ps
CPU time 1.52 seconds
Started Aug 06 08:06:06 PM PDT 24
Finished Aug 06 08:06:07 PM PDT 24
Peak memory 207292 kb
Host smart-51a9d9f5-7c0a-4146-9381-dfce5dd59e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13104
44990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1310444990
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1945697586
Short name T3103
Test name
Test status
Simulation time 326112171 ps
CPU time 1.17 seconds
Started Aug 06 08:06:05 PM PDT 24
Finished Aug 06 08:06:06 PM PDT 24
Peak memory 207320 kb
Host smart-c5e0c2db-4a02-43af-be58-4ac3333af0b6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1945697586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1945697586
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.891967398
Short name T1925
Test name
Test status
Simulation time 51265924947 ps
CPU time 82.91 seconds
Started Aug 06 08:06:07 PM PDT 24
Finished Aug 06 08:07:30 PM PDT 24
Peak memory 207668 kb
Host smart-73e41dcc-bc3c-4607-a3ff-15de9b526a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89196
7398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.891967398
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.3325072824
Short name T1352
Test name
Test status
Simulation time 1054368864 ps
CPU time 9.44 seconds
Started Aug 06 08:05:56 PM PDT 24
Finished Aug 06 08:06:06 PM PDT 24
Peak memory 207620 kb
Host smart-74936787-3962-465c-bbf5-168cee50e8bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325072824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.3325072824
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.2207396770
Short name T2029
Test name
Test status
Simulation time 677175069 ps
CPU time 1.61 seconds
Started Aug 06 08:06:06 PM PDT 24
Finished Aug 06 08:06:08 PM PDT 24
Peak memory 207288 kb
Host smart-db1e10df-4905-4125-8dfb-8184bfde66a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22073
96770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.2207396770
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.2680999043
Short name T825
Test name
Test status
Simulation time 187748556 ps
CPU time 0.88 seconds
Started Aug 06 08:05:44 PM PDT 24
Finished Aug 06 08:05:45 PM PDT 24
Peak memory 207320 kb
Host smart-e97b4862-9fe0-4705-9217-6b580ddb5851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26809
99043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.2680999043
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1708333289
Short name T1787
Test name
Test status
Simulation time 34957259 ps
CPU time 0.7 seconds
Started Aug 06 08:06:01 PM PDT 24
Finished Aug 06 08:06:02 PM PDT 24
Peak memory 207416 kb
Host smart-b417647b-0989-4c0b-963f-b0b5401e63f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17083
33289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1708333289
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.315850538
Short name T768
Test name
Test status
Simulation time 691977691 ps
CPU time 2.05 seconds
Started Aug 06 08:06:03 PM PDT 24
Finished Aug 06 08:06:05 PM PDT 24
Peak memory 207776 kb
Host smart-7863139d-e3fb-4714-b5ba-6bb2431e847d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31585
0538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.315850538
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_types.3816571765
Short name T451
Test name
Test status
Simulation time 166519463 ps
CPU time 0.92 seconds
Started Aug 06 08:05:54 PM PDT 24
Finished Aug 06 08:05:55 PM PDT 24
Peak memory 207280 kb
Host smart-a9a51b67-012f-4567-8063-3061a66ba790
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3816571765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.3816571765
Directory /workspace/27.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.776238659
Short name T2988
Test name
Test status
Simulation time 286513113 ps
CPU time 1.81 seconds
Started Aug 06 08:05:43 PM PDT 24
Finished Aug 06 08:05:45 PM PDT 24
Peak memory 207504 kb
Host smart-b09df4fb-0f08-426b-8a37-e06a67c129c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77623
8659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.776238659
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.415805999
Short name T20
Test name
Test status
Simulation time 170166386 ps
CPU time 0.86 seconds
Started Aug 06 08:05:57 PM PDT 24
Finished Aug 06 08:05:58 PM PDT 24
Peak memory 207376 kb
Host smart-33fb6926-fc01-4cbe-8824-97f6e528c0a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=415805999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.415805999
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3053038745
Short name T1297
Test name
Test status
Simulation time 155927861 ps
CPU time 0.85 seconds
Started Aug 06 08:05:59 PM PDT 24
Finished Aug 06 08:06:00 PM PDT 24
Peak memory 207292 kb
Host smart-c7690cf6-51fe-45e7-b85c-3ec37a40f27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30530
38745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3053038745
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.4040160233
Short name T40
Test name
Test status
Simulation time 190020190 ps
CPU time 0.94 seconds
Started Aug 06 08:06:04 PM PDT 24
Finished Aug 06 08:06:05 PM PDT 24
Peak memory 206644 kb
Host smart-25d50d76-e017-4d8f-aa79-32bb60774923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40401
60233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.4040160233
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.1023503612
Short name T1938
Test name
Test status
Simulation time 4909380364 ps
CPU time 49.17 seconds
Started Aug 06 08:06:03 PM PDT 24
Finished Aug 06 08:06:52 PM PDT 24
Peak memory 223940 kb
Host smart-b68f7e57-605b-4aef-8526-1b89a7016bde
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1023503612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.1023503612
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.3605554996
Short name T1468
Test name
Test status
Simulation time 4416856570 ps
CPU time 34.74 seconds
Started Aug 06 08:05:49 PM PDT 24
Finished Aug 06 08:06:24 PM PDT 24
Peak memory 207696 kb
Host smart-0d46b285-7ba9-4b66-803c-5bf3b71a0a65
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3605554996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.3605554996
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2061022501
Short name T2579
Test name
Test status
Simulation time 201858969 ps
CPU time 0.88 seconds
Started Aug 06 08:06:00 PM PDT 24
Finished Aug 06 08:06:01 PM PDT 24
Peak memory 207372 kb
Host smart-802637a0-74e4-429e-b57c-4e274393ec03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20610
22501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2061022501
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3264213112
Short name T68
Test name
Test status
Simulation time 12359582019 ps
CPU time 15.06 seconds
Started Aug 06 08:05:55 PM PDT 24
Finished Aug 06 08:06:10 PM PDT 24
Peak memory 207648 kb
Host smart-699424e9-830e-4b0c-a888-504bc1b1810c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32642
13112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3264213112
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1040649428
Short name T911
Test name
Test status
Simulation time 5317397613 ps
CPU time 6.9 seconds
Started Aug 06 08:06:13 PM PDT 24
Finished Aug 06 08:06:20 PM PDT 24
Peak memory 215968 kb
Host smart-62d410d9-0474-4ccf-97ab-4a6a3ed74ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10406
49428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1040649428
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3488874274
Short name T949
Test name
Test status
Simulation time 5631100801 ps
CPU time 54.9 seconds
Started Aug 06 08:05:55 PM PDT 24
Finished Aug 06 08:06:50 PM PDT 24
Peak memory 223976 kb
Host smart-83f90961-1cd7-4598-92fc-1c9fd1cd747e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34888
74274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3488874274
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3782568434
Short name T171
Test name
Test status
Simulation time 2636128753 ps
CPU time 25.45 seconds
Started Aug 06 08:06:02 PM PDT 24
Finished Aug 06 08:06:27 PM PDT 24
Peak memory 224036 kb
Host smart-3fa249b8-e636-4fdd-be99-2110e6d3c0fb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3782568434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3782568434
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.3686398572
Short name T2299
Test name
Test status
Simulation time 241869308 ps
CPU time 1.1 seconds
Started Aug 06 08:06:03 PM PDT 24
Finished Aug 06 08:06:04 PM PDT 24
Peak memory 207368 kb
Host smart-dfabd75b-00eb-447a-bb0f-876081864def
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3686398572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.3686398572
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3710411298
Short name T1806
Test name
Test status
Simulation time 212642617 ps
CPU time 0.91 seconds
Started Aug 06 08:05:48 PM PDT 24
Finished Aug 06 08:05:49 PM PDT 24
Peak memory 207316 kb
Host smart-32f34740-f217-49b7-9b3f-f1c5a68ee152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37104
11298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3710411298
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.2080426260
Short name T1264
Test name
Test status
Simulation time 2753612658 ps
CPU time 76.69 seconds
Started Aug 06 08:06:09 PM PDT 24
Finished Aug 06 08:07:26 PM PDT 24
Peak memory 215856 kb
Host smart-838286c0-6107-407a-b562-19919f818d46
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2080426260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.2080426260
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3055448987
Short name T1776
Test name
Test status
Simulation time 150198764 ps
CPU time 0.88 seconds
Started Aug 06 08:06:06 PM PDT 24
Finished Aug 06 08:06:07 PM PDT 24
Peak memory 207384 kb
Host smart-05165279-2e2c-4b62-aa98-e9a54cbc7be8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3055448987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3055448987
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1372686580
Short name T1001
Test name
Test status
Simulation time 181631832 ps
CPU time 0.91 seconds
Started Aug 06 08:06:00 PM PDT 24
Finished Aug 06 08:06:01 PM PDT 24
Peak memory 207604 kb
Host smart-9405410f-7a05-45ce-bfa7-7126282bd326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13726
86580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1372686580
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.550926798
Short name T3073
Test name
Test status
Simulation time 156802916 ps
CPU time 0.87 seconds
Started Aug 06 08:06:02 PM PDT 24
Finished Aug 06 08:06:03 PM PDT 24
Peak memory 207376 kb
Host smart-c93dae88-87d2-4a3c-84e3-c9a65021e438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55092
6798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.550926798
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1960365054
Short name T680
Test name
Test status
Simulation time 272999929 ps
CPU time 0.94 seconds
Started Aug 06 08:05:44 PM PDT 24
Finished Aug 06 08:05:45 PM PDT 24
Peak memory 207332 kb
Host smart-740a4aa6-b0db-4833-be76-c9a3b1ccfc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19603
65054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1960365054
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1717057742
Short name T1005
Test name
Test status
Simulation time 200448810 ps
CPU time 0.9 seconds
Started Aug 06 08:06:00 PM PDT 24
Finished Aug 06 08:06:01 PM PDT 24
Peak memory 207604 kb
Host smart-7093b9bd-80f2-411b-9caf-c991ad6bd3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17170
57742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1717057742
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1634458081
Short name T2607
Test name
Test status
Simulation time 154625560 ps
CPU time 0.85 seconds
Started Aug 06 08:05:48 PM PDT 24
Finished Aug 06 08:05:49 PM PDT 24
Peak memory 207308 kb
Host smart-d1c740da-85fa-45b1-b241-b39184d16b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16344
58081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1634458081
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2726049567
Short name T529
Test name
Test status
Simulation time 236811852 ps
CPU time 1 seconds
Started Aug 06 08:06:05 PM PDT 24
Finished Aug 06 08:06:06 PM PDT 24
Peak memory 207328 kb
Host smart-e7b7d7f0-4f51-40fc-813d-fb410f184541
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2726049567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2726049567
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2436987287
Short name T834
Test name
Test status
Simulation time 156845953 ps
CPU time 0.83 seconds
Started Aug 06 08:05:53 PM PDT 24
Finished Aug 06 08:05:54 PM PDT 24
Peak memory 207324 kb
Host smart-b53e76fa-aff8-4f17-9aad-6bbd5cfddd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24369
87287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2436987287
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.762060492
Short name T2630
Test name
Test status
Simulation time 55268827 ps
CPU time 0.71 seconds
Started Aug 06 08:05:55 PM PDT 24
Finished Aug 06 08:05:56 PM PDT 24
Peak memory 207416 kb
Host smart-0d41f7cb-600a-4093-9e11-a4ea75a6bfb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76206
0492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.762060492
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2817165246
Short name T111
Test name
Test status
Simulation time 17874495358 ps
CPU time 47.99 seconds
Started Aug 06 08:06:04 PM PDT 24
Finished Aug 06 08:06:53 PM PDT 24
Peak memory 219812 kb
Host smart-089cf6fb-e2ae-4fff-be90-b224da3938e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171
65246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2817165246
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1084130846
Short name T2748
Test name
Test status
Simulation time 160856446 ps
CPU time 0.86 seconds
Started Aug 06 08:06:04 PM PDT 24
Finished Aug 06 08:06:05 PM PDT 24
Peak memory 207596 kb
Host smart-a77155d0-a70a-4c85-893d-9990062c2852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10841
30846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1084130846
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1895856778
Short name T1529
Test name
Test status
Simulation time 163371929 ps
CPU time 0.89 seconds
Started Aug 06 08:06:02 PM PDT 24
Finished Aug 06 08:06:03 PM PDT 24
Peak memory 207356 kb
Host smart-efb7bed9-5393-4b1a-941c-3ab673e59c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18958
56778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1895856778
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.2303663368
Short name T667
Test name
Test status
Simulation time 183452861 ps
CPU time 0.88 seconds
Started Aug 06 08:06:01 PM PDT 24
Finished Aug 06 08:06:02 PM PDT 24
Peak memory 207360 kb
Host smart-48ea1efb-f661-4d44-aad0-5d50858579ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23036
63368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2303663368
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3729466750
Short name T1295
Test name
Test status
Simulation time 151762958 ps
CPU time 0.89 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 207376 kb
Host smart-3f2da607-4a69-4e90-96e7-be0ea7798770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37294
66750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3729466750
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2371887292
Short name T2857
Test name
Test status
Simulation time 183768240 ps
CPU time 0.9 seconds
Started Aug 06 08:06:04 PM PDT 24
Finished Aug 06 08:06:05 PM PDT 24
Peak memory 207348 kb
Host smart-5cdbd538-834b-4b37-88c5-33b873c752f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23718
87292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2371887292
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_rx_full.3457033133
Short name T1889
Test name
Test status
Simulation time 394831279 ps
CPU time 1.43 seconds
Started Aug 06 08:06:01 PM PDT 24
Finished Aug 06 08:06:02 PM PDT 24
Peak memory 207372 kb
Host smart-4cf02882-e7ee-4a21-9f92-f420191f760a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34570
33133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.3457033133
Directory /workspace/27.usbdev_rx_full/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1725605716
Short name T96
Test name
Test status
Simulation time 156952021 ps
CPU time 0.85 seconds
Started Aug 06 08:06:00 PM PDT 24
Finished Aug 06 08:06:01 PM PDT 24
Peak memory 207340 kb
Host smart-47c5985a-ec33-405a-9f4c-bfd792e3bc21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17256
05716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1725605716
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.4223566981
Short name T1364
Test name
Test status
Simulation time 141163433 ps
CPU time 0.86 seconds
Started Aug 06 08:06:03 PM PDT 24
Finished Aug 06 08:06:04 PM PDT 24
Peak memory 207372 kb
Host smart-45f8dd13-4dbf-42bc-9d00-b79a51af29a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42235
66981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.4223566981
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3833292938
Short name T625
Test name
Test status
Simulation time 248017661 ps
CPU time 1.04 seconds
Started Aug 06 08:05:52 PM PDT 24
Finished Aug 06 08:05:53 PM PDT 24
Peak memory 207596 kb
Host smart-6d1efbe4-bb9d-47c3-a0c3-a945267a7986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38332
92938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3833292938
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.147583033
Short name T1864
Test name
Test status
Simulation time 2246485203 ps
CPU time 22.58 seconds
Started Aug 06 08:05:58 PM PDT 24
Finished Aug 06 08:06:20 PM PDT 24
Peak memory 217404 kb
Host smart-5b1499d7-db97-4249-8672-1225c59e2793
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=147583033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.147583033
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1901143165
Short name T612
Test name
Test status
Simulation time 209476946 ps
CPU time 0.89 seconds
Started Aug 06 08:06:09 PM PDT 24
Finished Aug 06 08:06:10 PM PDT 24
Peak memory 207380 kb
Host smart-8b6d718a-a933-494e-827f-baaf884fc517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19011
43165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1901143165
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3813411761
Short name T508
Test name
Test status
Simulation time 149239563 ps
CPU time 0.81 seconds
Started Aug 06 08:06:07 PM PDT 24
Finished Aug 06 08:06:08 PM PDT 24
Peak memory 207372 kb
Host smart-d37a9d01-05f8-4113-b306-62a29cdcc1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38134
11761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3813411761
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.450092920
Short name T500
Test name
Test status
Simulation time 1070084760 ps
CPU time 2.79 seconds
Started Aug 06 08:06:04 PM PDT 24
Finished Aug 06 08:06:07 PM PDT 24
Peak memory 207520 kb
Host smart-341c6161-e59a-4ec4-a0d4-9b989438bbc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45009
2920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.450092920
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.2722055565
Short name T958
Test name
Test status
Simulation time 2533438768 ps
CPU time 71.94 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:07:24 PM PDT 24
Peak memory 217396 kb
Host smart-bfc343e8-7490-410a-9260-f511bb3d048d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27220
55565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.2722055565
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.2750350756
Short name T1672
Test name
Test status
Simulation time 959829348 ps
CPU time 21.24 seconds
Started Aug 06 08:05:58 PM PDT 24
Finished Aug 06 08:06:20 PM PDT 24
Peak memory 207592 kb
Host smart-18c58d02-8065-4ca6-b1ac-364004fcc1be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750350756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.2750350756
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.3357947159
Short name T1740
Test name
Test status
Simulation time 39220893 ps
CPU time 0.67 seconds
Started Aug 06 08:06:07 PM PDT 24
Finished Aug 06 08:06:08 PM PDT 24
Peak memory 207504 kb
Host smart-4ee21006-6316-4595-b644-4efede08d748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3357947159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.3357947159
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3251781093
Short name T1197
Test name
Test status
Simulation time 11623602310 ps
CPU time 13.96 seconds
Started Aug 06 08:06:06 PM PDT 24
Finished Aug 06 08:06:20 PM PDT 24
Peak memory 207632 kb
Host smart-05271011-d02e-4cbc-82a3-09c23e0e8558
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251781093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.3251781093
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1486295281
Short name T1382
Test name
Test status
Simulation time 19104048520 ps
CPU time 22.91 seconds
Started Aug 06 08:06:04 PM PDT 24
Finished Aug 06 08:06:27 PM PDT 24
Peak memory 207644 kb
Host smart-1ad5e3a9-eccd-4346-a77b-69d9419f06bd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486295281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1486295281
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.749341883
Short name T2101
Test name
Test status
Simulation time 25466333658 ps
CPU time 33.43 seconds
Started Aug 06 08:06:08 PM PDT 24
Finished Aug 06 08:06:41 PM PDT 24
Peak memory 215824 kb
Host smart-2b9b975b-3d99-43ee-858e-b96e68bafe42
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749341883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_ao
n_wake_resume.749341883
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2748407531
Short name T576
Test name
Test status
Simulation time 162886543 ps
CPU time 0.89 seconds
Started Aug 06 08:06:07 PM PDT 24
Finished Aug 06 08:06:08 PM PDT 24
Peak memory 207372 kb
Host smart-1b470813-f17b-4045-b3f6-b863fc68dc3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27484
07531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2748407531
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.2401679986
Short name T2182
Test name
Test status
Simulation time 142505814 ps
CPU time 0.89 seconds
Started Aug 06 08:05:57 PM PDT 24
Finished Aug 06 08:05:58 PM PDT 24
Peak memory 207340 kb
Host smart-24243070-9167-4115-8293-887cac52c9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24016
79986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.2401679986
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2083151135
Short name T1827
Test name
Test status
Simulation time 282176784 ps
CPU time 1.09 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:12 PM PDT 24
Peak memory 207428 kb
Host smart-6221f364-e58d-4098-9ddb-0c4433bab153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20831
51135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2083151135
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1942999893
Short name T1774
Test name
Test status
Simulation time 335166454 ps
CPU time 1.19 seconds
Started Aug 06 08:06:03 PM PDT 24
Finished Aug 06 08:06:04 PM PDT 24
Peak memory 207328 kb
Host smart-fc9a755b-62f4-4595-a0d2-996ed6b8f7cc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1942999893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1942999893
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.3407763582
Short name T1187
Test name
Test status
Simulation time 54580619353 ps
CPU time 77.76 seconds
Started Aug 06 08:05:56 PM PDT 24
Finished Aug 06 08:07:14 PM PDT 24
Peak memory 207716 kb
Host smart-b409cd0c-f205-40c1-a758-354d8bb12623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34077
63582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.3407763582
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.2391563721
Short name T3041
Test name
Test status
Simulation time 5230371884 ps
CPU time 46.88 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:06:59 PM PDT 24
Peak memory 207660 kb
Host smart-ebfc0b9d-2d03-4b4a-8b56-bebfc8d51772
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391563721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.2391563721
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.417083798
Short name T1520
Test name
Test status
Simulation time 734394217 ps
CPU time 2.02 seconds
Started Aug 06 08:05:57 PM PDT 24
Finished Aug 06 08:05:59 PM PDT 24
Peak memory 207364 kb
Host smart-d190ae99-6043-4164-a34c-b203ad4ffb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41708
3798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.417083798
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3480355809
Short name T1211
Test name
Test status
Simulation time 137985413 ps
CPU time 0.92 seconds
Started Aug 06 08:05:53 PM PDT 24
Finished Aug 06 08:05:54 PM PDT 24
Peak memory 207288 kb
Host smart-1cc9d594-fbb6-4682-b0cd-d2837785ffed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34803
55809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3480355809
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3964880779
Short name T924
Test name
Test status
Simulation time 61277944 ps
CPU time 0.72 seconds
Started Aug 06 08:05:59 PM PDT 24
Finished Aug 06 08:06:00 PM PDT 24
Peak memory 207340 kb
Host smart-faa27e4b-ad05-49f2-b29d-ad4bcf94c4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39648
80779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3964880779
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2808522729
Short name T492
Test name
Test status
Simulation time 958137867 ps
CPU time 2.47 seconds
Started Aug 06 08:06:06 PM PDT 24
Finished Aug 06 08:06:09 PM PDT 24
Peak memory 207504 kb
Host smart-65c41e86-57fe-4e23-93db-ad088dc94374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28085
22729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2808522729
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_types.1187937719
Short name T454
Test name
Test status
Simulation time 149640582 ps
CPU time 0.85 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 207332 kb
Host smart-fba37591-134b-4f71-92d3-c28e9ceda993
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1187937719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.1187937719
Directory /workspace/28.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.4253300117
Short name T2679
Test name
Test status
Simulation time 236962758 ps
CPU time 1.49 seconds
Started Aug 06 08:06:02 PM PDT 24
Finished Aug 06 08:06:03 PM PDT 24
Peak memory 207452 kb
Host smart-e477be07-11c1-49e4-a821-da86c3b2b37d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42533
00117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.4253300117
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3464865585
Short name T2875
Test name
Test status
Simulation time 168104448 ps
CPU time 0.86 seconds
Started Aug 06 08:05:53 PM PDT 24
Finished Aug 06 08:05:54 PM PDT 24
Peak memory 207360 kb
Host smart-3a02abe9-af0c-4f23-801b-d2d0cec12e2b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3464865585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3464865585
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1834050329
Short name T241
Test name
Test status
Simulation time 153164262 ps
CPU time 0.85 seconds
Started Aug 06 08:05:46 PM PDT 24
Finished Aug 06 08:05:47 PM PDT 24
Peak memory 207344 kb
Host smart-6758585a-cd4a-4549-8726-7ed76a30db05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18340
50329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1834050329
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3050056459
Short name T536
Test name
Test status
Simulation time 218180508 ps
CPU time 1.01 seconds
Started Aug 06 08:05:46 PM PDT 24
Finished Aug 06 08:05:47 PM PDT 24
Peak memory 207376 kb
Host smart-b85bea6a-7b53-46d0-9832-55693742a810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500
56459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3050056459
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3278756233
Short name T2796
Test name
Test status
Simulation time 3878312024 ps
CPU time 110.74 seconds
Started Aug 06 08:06:02 PM PDT 24
Finished Aug 06 08:07:53 PM PDT 24
Peak memory 223996 kb
Host smart-0cc5f587-5524-42fa-9b10-167f081abc49
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3278756233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3278756233
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.2229286928
Short name T285
Test name
Test status
Simulation time 12131478417 ps
CPU time 82.65 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:07:33 PM PDT 24
Peak memory 207864 kb
Host smart-315fbaa2-0b6f-46be-b3df-26263f90532c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2229286928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.2229286928
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2352196442
Short name T1453
Test name
Test status
Simulation time 220490970 ps
CPU time 0.94 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 207356 kb
Host smart-02874225-0146-4af3-8b75-f398db604d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23521
96442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2352196442
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.4178874790
Short name T1960
Test name
Test status
Simulation time 27463177292 ps
CPU time 32.65 seconds
Started Aug 06 08:06:07 PM PDT 24
Finished Aug 06 08:06:40 PM PDT 24
Peak memory 207708 kb
Host smart-74d836e0-f0f6-4a90-9fd5-452c35b2b1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41788
74790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.4178874790
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.244671776
Short name T66
Test name
Test status
Simulation time 3436308592 ps
CPU time 5.88 seconds
Started Aug 06 08:06:15 PM PDT 24
Finished Aug 06 08:06:21 PM PDT 24
Peak memory 215812 kb
Host smart-84222dba-5162-4af8-9f6a-5ae9666f8706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24467
1776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.244671776
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.2296863053
Short name T1989
Test name
Test status
Simulation time 3273465986 ps
CPU time 30.98 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:06:43 PM PDT 24
Peak memory 224092 kb
Host smart-a326b72c-8f12-4405-b464-a767cebd91b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22968
63053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.2296863053
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2063500473
Short name T2475
Test name
Test status
Simulation time 3862007723 ps
CPU time 114.96 seconds
Started Aug 06 08:06:13 PM PDT 24
Finished Aug 06 08:08:08 PM PDT 24
Peak memory 217148 kb
Host smart-e82b6aba-9d47-4ac4-a47b-c77f57bddf25
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2063500473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2063500473
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.943814634
Short name T2090
Test name
Test status
Simulation time 236792899 ps
CPU time 0.97 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 207396 kb
Host smart-7e1d9701-3ed9-49b9-a794-30712c324fa1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=943814634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.943814634
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2318156589
Short name T1996
Test name
Test status
Simulation time 195523981 ps
CPU time 0.92 seconds
Started Aug 06 08:06:06 PM PDT 24
Finished Aug 06 08:06:07 PM PDT 24
Peak memory 207452 kb
Host smart-66894012-b2d0-4853-b55e-57f023e468ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23181
56589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2318156589
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.1478134913
Short name T1048
Test name
Test status
Simulation time 2540009336 ps
CPU time 18.78 seconds
Started Aug 06 08:06:04 PM PDT 24
Finished Aug 06 08:06:23 PM PDT 24
Peak memory 223948 kb
Host smart-4e1deff9-4e3e-4c7e-91e6-129beae0dff1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1478134913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.1478134913
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2430933151
Short name T681
Test name
Test status
Simulation time 160461341 ps
CPU time 0.84 seconds
Started Aug 06 08:06:17 PM PDT 24
Finished Aug 06 08:06:18 PM PDT 24
Peak memory 207396 kb
Host smart-ae218f47-83b6-4d15-9da6-c26f75582828
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2430933151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2430933151
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1744081127
Short name T1816
Test name
Test status
Simulation time 196362400 ps
CPU time 0.87 seconds
Started Aug 06 08:06:08 PM PDT 24
Finished Aug 06 08:06:09 PM PDT 24
Peak memory 207304 kb
Host smart-dd56be31-482c-49e2-95e5-1fbeb2d32bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17440
81127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1744081127
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.155752642
Short name T164
Test name
Test status
Simulation time 276774550 ps
CPU time 1.01 seconds
Started Aug 06 08:06:09 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 207352 kb
Host smart-44a42d80-bf80-45ac-9089-c6fa2390f522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15575
2642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.155752642
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2553098397
Short name T1646
Test name
Test status
Simulation time 193804539 ps
CPU time 0.95 seconds
Started Aug 06 08:06:07 PM PDT 24
Finished Aug 06 08:06:08 PM PDT 24
Peak memory 207324 kb
Host smart-f8284be3-cb1f-48b0-adae-dc8a76f95343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25530
98397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2553098397
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2430122391
Short name T1060
Test name
Test status
Simulation time 164034454 ps
CPU time 0.82 seconds
Started Aug 06 08:06:08 PM PDT 24
Finished Aug 06 08:06:09 PM PDT 24
Peak memory 207376 kb
Host smart-f5558b13-8935-4e77-8471-7311fdbae5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24301
22391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2430122391
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2518962632
Short name T2660
Test name
Test status
Simulation time 163603590 ps
CPU time 0.93 seconds
Started Aug 06 08:06:13 PM PDT 24
Finished Aug 06 08:06:14 PM PDT 24
Peak memory 207304 kb
Host smart-0f94db2d-97bf-46c6-95c5-1c2dae34886b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25189
62632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2518962632
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.884612757
Short name T2117
Test name
Test status
Simulation time 177887268 ps
CPU time 0.88 seconds
Started Aug 06 08:06:08 PM PDT 24
Finished Aug 06 08:06:09 PM PDT 24
Peak memory 207340 kb
Host smart-cd46ea69-6e89-40d6-89a4-c6580be4a811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88461
2757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.884612757
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.2525508247
Short name T618
Test name
Test status
Simulation time 227672771 ps
CPU time 1.1 seconds
Started Aug 06 08:06:05 PM PDT 24
Finished Aug 06 08:06:06 PM PDT 24
Peak memory 207424 kb
Host smart-9e3c6a40-66cf-412f-8bfe-a78e2e1470c7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2525508247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.2525508247
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3169786880
Short name T1890
Test name
Test status
Simulation time 150478817 ps
CPU time 0.84 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 207388 kb
Host smart-be39fd09-33e6-42dc-91bd-5b0cd9aafb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31697
86880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3169786880
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.589889282
Short name T1114
Test name
Test status
Simulation time 41885787 ps
CPU time 0.7 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 207264 kb
Host smart-dc4923e3-a06b-4b1c-b98b-0763e14d52b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58988
9282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.589889282
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3054961423
Short name T1141
Test name
Test status
Simulation time 8095094429 ps
CPU time 19.66 seconds
Started Aug 06 08:06:05 PM PDT 24
Finished Aug 06 08:06:25 PM PDT 24
Peak memory 215856 kb
Host smart-07b49778-3068-480e-94ae-db11d4bfb629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30549
61423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3054961423
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2643917097
Short name T1418
Test name
Test status
Simulation time 233259230 ps
CPU time 0.89 seconds
Started Aug 06 08:05:57 PM PDT 24
Finished Aug 06 08:05:58 PM PDT 24
Peak memory 207240 kb
Host smart-b6786805-3351-48eb-84aa-1c3ab9473ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26439
17097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2643917097
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3576561761
Short name T2211
Test name
Test status
Simulation time 259705611 ps
CPU time 1 seconds
Started Aug 06 08:06:08 PM PDT 24
Finished Aug 06 08:06:09 PM PDT 24
Peak memory 207356 kb
Host smart-ace09b80-5674-48cf-b83d-eb0467bef1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35765
61761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3576561761
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1867250085
Short name T1465
Test name
Test status
Simulation time 202735155 ps
CPU time 0.97 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:06:13 PM PDT 24
Peak memory 207320 kb
Host smart-9f2cd269-2d31-4092-906a-3d2ce44585c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18672
50085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1867250085
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.4119897698
Short name T2913
Test name
Test status
Simulation time 180449917 ps
CPU time 0.92 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:12 PM PDT 24
Peak memory 207368 kb
Host smart-cf01574d-b5e6-4bfb-9838-e10f55ab9796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41198
97698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.4119897698
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.1600325289
Short name T2135
Test name
Test status
Simulation time 183106353 ps
CPU time 0.83 seconds
Started Aug 06 08:06:04 PM PDT 24
Finished Aug 06 08:06:05 PM PDT 24
Peak memory 207308 kb
Host smart-737d3c32-be3b-4343-96d1-98c972aa41df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16003
25289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.1600325289
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_rx_full.2255254143
Short name T2314
Test name
Test status
Simulation time 383640789 ps
CPU time 1.26 seconds
Started Aug 06 08:06:05 PM PDT 24
Finished Aug 06 08:06:06 PM PDT 24
Peak memory 207356 kb
Host smart-c9d777d9-9345-497e-a698-c582eb3d0cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22552
54143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.2255254143
Directory /workspace/28.usbdev_rx_full/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3024006627
Short name T608
Test name
Test status
Simulation time 170401312 ps
CPU time 0.83 seconds
Started Aug 06 08:05:59 PM PDT 24
Finished Aug 06 08:06:00 PM PDT 24
Peak memory 207308 kb
Host smart-a8ff467e-c37e-4cd6-8df9-6083b7feb0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30240
06627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3024006627
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1943313705
Short name T2056
Test name
Test status
Simulation time 153312461 ps
CPU time 0.85 seconds
Started Aug 06 08:06:09 PM PDT 24
Finished Aug 06 08:06:10 PM PDT 24
Peak memory 207452 kb
Host smart-3e861418-2437-4121-817a-53eb533de959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19433
13705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1943313705
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.551907465
Short name T1703
Test name
Test status
Simulation time 225687745 ps
CPU time 0.99 seconds
Started Aug 06 08:06:09 PM PDT 24
Finished Aug 06 08:06:10 PM PDT 24
Peak memory 207400 kb
Host smart-0375f263-ada8-44d1-b4c6-c6d8948889c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55190
7465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.551907465
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.2310407507
Short name T2923
Test name
Test status
Simulation time 2860345298 ps
CPU time 22.96 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:34 PM PDT 24
Peak memory 223968 kb
Host smart-0c04da8b-e526-4af2-9b78-2571adb10ae4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2310407507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2310407507
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1870737257
Short name T2603
Test name
Test status
Simulation time 184095500 ps
CPU time 0.88 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:12 PM PDT 24
Peak memory 207448 kb
Host smart-19d8ee75-e321-478b-99d2-17c39e32d89a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18707
37257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1870737257
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3493010020
Short name T2734
Test name
Test status
Simulation time 225841699 ps
CPU time 0.88 seconds
Started Aug 06 08:06:07 PM PDT 24
Finished Aug 06 08:06:08 PM PDT 24
Peak memory 207356 kb
Host smart-6eb9f609-a36b-45cf-b0db-87b71f602802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34930
10020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3493010020
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.988604572
Short name T1591
Test name
Test status
Simulation time 766638258 ps
CPU time 2.23 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:13 PM PDT 24
Peak memory 207276 kb
Host smart-652e6cd1-a2ff-4265-9dcd-cdeacb21b9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98860
4572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.988604572
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.1254789611
Short name T599
Test name
Test status
Simulation time 2882058888 ps
CPU time 28.71 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:06:39 PM PDT 24
Peak memory 224068 kb
Host smart-db004a78-788d-4705-941c-bbf4d82989dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12547
89611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.1254789611
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.1807725096
Short name T2515
Test name
Test status
Simulation time 1993925684 ps
CPU time 16.87 seconds
Started Aug 06 08:06:02 PM PDT 24
Finished Aug 06 08:06:19 PM PDT 24
Peak memory 207532 kb
Host smart-7b87072d-d317-41ca-8d3b-c86cb8557b5e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807725096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.1807725096
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.2293786820
Short name T812
Test name
Test status
Simulation time 41219172 ps
CPU time 0.63 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 207344 kb
Host smart-049e2a9b-1675-42ee-9aeb-70e843468e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2293786820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.2293786820
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.631321460
Short name T940
Test name
Test status
Simulation time 11739656996 ps
CPU time 16.89 seconds
Started Aug 06 08:06:07 PM PDT 24
Finished Aug 06 08:06:24 PM PDT 24
Peak memory 207616 kb
Host smart-1a874bb6-dc1a-40c2-9b0f-fd26a0ad37d2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631321460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_disconnect.631321460
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2642013188
Short name T2037
Test name
Test status
Simulation time 19761140243 ps
CPU time 22.77 seconds
Started Aug 06 08:06:13 PM PDT 24
Finished Aug 06 08:06:35 PM PDT 24
Peak memory 207612 kb
Host smart-3ad285ae-f793-4e86-af9d-b191382ac499
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642013188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2642013188
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.1074650793
Short name T2583
Test name
Test status
Simulation time 29732020389 ps
CPU time 36.5 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:47 PM PDT 24
Peak memory 207644 kb
Host smart-98c3cf57-1e47-44f8-9494-cf7c29f088d6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074650793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.1074650793
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3370334731
Short name T2281
Test name
Test status
Simulation time 150119379 ps
CPU time 0.85 seconds
Started Aug 06 08:06:00 PM PDT 24
Finished Aug 06 08:06:01 PM PDT 24
Peak memory 207324 kb
Host smart-cd14ec52-1a2c-43f8-9f20-ccf7c5d40a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703
34731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3370334731
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2180617312
Short name T1134
Test name
Test status
Simulation time 167217275 ps
CPU time 0.84 seconds
Started Aug 06 08:06:14 PM PDT 24
Finished Aug 06 08:06:15 PM PDT 24
Peak memory 207416 kb
Host smart-d6d6809e-8d13-421e-b7bf-da2208661a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21806
17312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2180617312
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.2446500918
Short name T2500
Test name
Test status
Simulation time 358827731 ps
CPU time 1.34 seconds
Started Aug 06 08:05:59 PM PDT 24
Finished Aug 06 08:06:01 PM PDT 24
Peak memory 207372 kb
Host smart-ad073841-f353-4950-82b7-71d2010cd90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24465
00918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.2446500918
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.82302681
Short name T1023
Test name
Test status
Simulation time 580609366 ps
CPU time 1.68 seconds
Started Aug 06 08:06:16 PM PDT 24
Finished Aug 06 08:06:18 PM PDT 24
Peak memory 207380 kb
Host smart-2b7380d6-9af9-4448-be02-e8cdb228e0e5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=82302681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.82302681
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3514495333
Short name T1783
Test name
Test status
Simulation time 16503781587 ps
CPU time 26.31 seconds
Started Aug 06 08:06:15 PM PDT 24
Finished Aug 06 08:06:41 PM PDT 24
Peak memory 207536 kb
Host smart-c62ae473-b0b3-46de-be00-e4f1449ab800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35144
95333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3514495333
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.2616058923
Short name T2383
Test name
Test status
Simulation time 1992360687 ps
CPU time 15.76 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:27 PM PDT 24
Peak memory 207556 kb
Host smart-b2336220-9abb-403e-8028-6e11a0791118
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616058923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.2616058923
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.3689488354
Short name T1852
Test name
Test status
Simulation time 1005089563 ps
CPU time 2.31 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:06:14 PM PDT 24
Peak memory 207320 kb
Host smart-1553721f-3720-4bd9-b822-d304676e74db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36894
88354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.3689488354
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3722908253
Short name T1657
Test name
Test status
Simulation time 134559009 ps
CPU time 0.82 seconds
Started Aug 06 08:06:19 PM PDT 24
Finished Aug 06 08:06:19 PM PDT 24
Peak memory 207368 kb
Host smart-46bf26e3-a7fd-47c4-a7e0-2f2d716d150c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37229
08253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3722908253
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3694946363
Short name T2397
Test name
Test status
Simulation time 38314960 ps
CPU time 0.69 seconds
Started Aug 06 08:06:15 PM PDT 24
Finished Aug 06 08:06:16 PM PDT 24
Peak memory 207340 kb
Host smart-14387312-fd83-471a-85fe-21d4333cf744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36949
46363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3694946363
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.1978606241
Short name T1101
Test name
Test status
Simulation time 982055865 ps
CPU time 3.13 seconds
Started Aug 06 08:06:23 PM PDT 24
Finished Aug 06 08:06:26 PM PDT 24
Peak memory 207580 kb
Host smart-4db012da-e8c8-43e5-b742-05f7c6fac290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19786
06241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.1978606241
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_types.2675268624
Short name T321
Test name
Test status
Simulation time 195642596 ps
CPU time 0.89 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:06:13 PM PDT 24
Peak memory 207320 kb
Host smart-afa85248-d459-4357-98ba-b60e4599af6e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2675268624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.2675268624
Directory /workspace/29.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2279755360
Short name T1234
Test name
Test status
Simulation time 357797924 ps
CPU time 2.59 seconds
Started Aug 06 08:06:14 PM PDT 24
Finished Aug 06 08:06:16 PM PDT 24
Peak memory 207464 kb
Host smart-010734a2-117d-42b3-9e46-9fdff9c7d068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22797
55360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2279755360
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2229160426
Short name T1103
Test name
Test status
Simulation time 196303477 ps
CPU time 0.91 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:06:13 PM PDT 24
Peak memory 207388 kb
Host smart-efa5adac-4b87-4e5e-a5df-713613c8dc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22291
60426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2229160426
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3865890435
Short name T1035
Test name
Test status
Simulation time 218256713 ps
CPU time 1.01 seconds
Started Aug 06 08:06:09 PM PDT 24
Finished Aug 06 08:06:10 PM PDT 24
Peak memory 207324 kb
Host smart-d3905870-b0d0-4699-9072-0e71b48927e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38658
90435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3865890435
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.2667222071
Short name T1140
Test name
Test status
Simulation time 5576210893 ps
CPU time 42.09 seconds
Started Aug 06 08:06:16 PM PDT 24
Finished Aug 06 08:06:58 PM PDT 24
Peak memory 224060 kb
Host smart-ca5b0f44-4953-4b41-aff0-5fb1ab89e482
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2667222071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.2667222071
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.3859836128
Short name T1393
Test name
Test status
Simulation time 10896165195 ps
CPU time 78.82 seconds
Started Aug 06 08:06:07 PM PDT 24
Finished Aug 06 08:07:26 PM PDT 24
Peak memory 207720 kb
Host smart-5fdf9d06-aeac-4b35-8183-eb4db7774d02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3859836128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.3859836128
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.2072555508
Short name T868
Test name
Test status
Simulation time 229148144 ps
CPU time 1.19 seconds
Started Aug 06 08:06:18 PM PDT 24
Finished Aug 06 08:06:19 PM PDT 24
Peak memory 207288 kb
Host smart-dd4ef96e-1ae8-46db-8631-47e9ce296e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20725
55508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2072555508
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.2391843925
Short name T1161
Test name
Test status
Simulation time 9502849607 ps
CPU time 11.66 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:06:22 PM PDT 24
Peak memory 215800 kb
Host smart-c25d8aa8-0f04-4587-be96-014e8b131840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23918
43925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.2391843925
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.326235089
Short name T1971
Test name
Test status
Simulation time 5360704427 ps
CPU time 6.91 seconds
Started Aug 06 08:06:17 PM PDT 24
Finished Aug 06 08:06:24 PM PDT 24
Peak memory 207652 kb
Host smart-b612bf11-47f9-4eef-95bd-f259b5d00f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32623
5089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.326235089
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.2391846156
Short name T2173
Test name
Test status
Simulation time 2966649193 ps
CPU time 23.37 seconds
Started Aug 06 08:06:14 PM PDT 24
Finished Aug 06 08:06:37 PM PDT 24
Peak memory 223884 kb
Host smart-32686952-2b94-46d6-8c9d-6cb6096bd2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23918
46156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2391846156
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2062871757
Short name T1299
Test name
Test status
Simulation time 3481005490 ps
CPU time 27.23 seconds
Started Aug 06 08:06:17 PM PDT 24
Finished Aug 06 08:06:44 PM PDT 24
Peak memory 215904 kb
Host smart-79fed6b2-f2e9-49f7-9715-68075b7af49b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2062871757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2062871757
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1257943029
Short name T573
Test name
Test status
Simulation time 312883503 ps
CPU time 1.01 seconds
Started Aug 06 08:06:16 PM PDT 24
Finished Aug 06 08:06:17 PM PDT 24
Peak memory 207348 kb
Host smart-d5ba9ba2-22e4-40ff-b77b-c1c39d7fe26c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1257943029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1257943029
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3513909160
Short name T2456
Test name
Test status
Simulation time 200373626 ps
CPU time 0.93 seconds
Started Aug 06 08:06:16 PM PDT 24
Finished Aug 06 08:06:17 PM PDT 24
Peak memory 207356 kb
Host smart-1b2ed5d4-e0bb-46f1-b02d-a670d05f896e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35139
09160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3513909160
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.232508179
Short name T891
Test name
Test status
Simulation time 3959454965 ps
CPU time 40.22 seconds
Started Aug 06 08:06:17 PM PDT 24
Finished Aug 06 08:06:57 PM PDT 24
Peak memory 215956 kb
Host smart-7f34cf22-b6fe-4475-b7c4-d9cccda0503b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=232508179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.232508179
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.234987876
Short name T2752
Test name
Test status
Simulation time 182160509 ps
CPU time 0.86 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:12 PM PDT 24
Peak memory 207344 kb
Host smart-570eabb7-e77e-4879-8e4b-07c429328b2c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=234987876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.234987876
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2720500739
Short name T1696
Test name
Test status
Simulation time 174812626 ps
CPU time 0.85 seconds
Started Aug 06 08:06:18 PM PDT 24
Finished Aug 06 08:06:19 PM PDT 24
Peak memory 207360 kb
Host smart-0d6b1c2d-5ba0-4ee6-85d4-e03d8b1be43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27205
00739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2720500739
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3845899325
Short name T147
Test name
Test status
Simulation time 198539718 ps
CPU time 0.93 seconds
Started Aug 06 08:06:15 PM PDT 24
Finished Aug 06 08:06:16 PM PDT 24
Peak memory 207296 kb
Host smart-9b65b482-1d0f-4c07-a773-c8eff0716e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38458
99325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3845899325
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.138788062
Short name T1068
Test name
Test status
Simulation time 163588810 ps
CPU time 0.84 seconds
Started Aug 06 08:06:14 PM PDT 24
Finished Aug 06 08:06:15 PM PDT 24
Peak memory 207320 kb
Host smart-af2505d1-0f29-4a69-92eb-effbf005f6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13878
8062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.138788062
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.735013598
Short name T1636
Test name
Test status
Simulation time 242350886 ps
CPU time 0.98 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:12 PM PDT 24
Peak memory 207352 kb
Host smart-928b2cc6-ae34-48fb-a2d8-5ad8e5308ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73501
3598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.735013598
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1792010798
Short name T968
Test name
Test status
Simulation time 221364282 ps
CPU time 0.89 seconds
Started Aug 06 08:06:13 PM PDT 24
Finished Aug 06 08:06:14 PM PDT 24
Peak memory 207204 kb
Host smart-7d3d3732-f2c4-42c1-a493-f3a63f65a12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17920
10798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1792010798
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.777957978
Short name T1111
Test name
Test status
Simulation time 153912401 ps
CPU time 0.84 seconds
Started Aug 06 08:06:16 PM PDT 24
Finished Aug 06 08:06:17 PM PDT 24
Peak memory 207400 kb
Host smart-867a9013-1b5f-4344-bd93-418ecbbaf41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77795
7978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.777957978
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.3051695414
Short name T686
Test name
Test status
Simulation time 222596904 ps
CPU time 1.05 seconds
Started Aug 06 08:06:13 PM PDT 24
Finished Aug 06 08:06:14 PM PDT 24
Peak memory 207408 kb
Host smart-e8299803-4732-4c6a-a31c-79cecf0025da
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3051695414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.3051695414
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2427714353
Short name T865
Test name
Test status
Simulation time 152688299 ps
CPU time 0.84 seconds
Started Aug 06 08:06:17 PM PDT 24
Finished Aug 06 08:06:18 PM PDT 24
Peak memory 207320 kb
Host smart-fa558bfb-e269-4bd3-a856-7dc766f76144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24277
14353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2427714353
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1733533980
Short name T699
Test name
Test status
Simulation time 42042481 ps
CPU time 0.67 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:06:13 PM PDT 24
Peak memory 207320 kb
Host smart-e0489075-3ff5-463f-9e2e-c4959577d8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17335
33980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1733533980
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2434275084
Short name T1754
Test name
Test status
Simulation time 16099115065 ps
CPU time 36.93 seconds
Started Aug 06 08:06:15 PM PDT 24
Finished Aug 06 08:06:52 PM PDT 24
Peak memory 215888 kb
Host smart-1395b171-9547-4f45-b9b1-d144ef43a7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24342
75084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2434275084
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3252908873
Short name T3100
Test name
Test status
Simulation time 217312201 ps
CPU time 0.9 seconds
Started Aug 06 08:06:17 PM PDT 24
Finished Aug 06 08:06:18 PM PDT 24
Peak memory 207312 kb
Host smart-88d987d7-0aa6-4a4b-a4b5-2602edfdd15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32529
08873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3252908873
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1791832145
Short name T1285
Test name
Test status
Simulation time 186713726 ps
CPU time 0.96 seconds
Started Aug 06 08:06:19 PM PDT 24
Finished Aug 06 08:06:20 PM PDT 24
Peak memory 207332 kb
Host smart-c153f00e-2434-4614-9b3a-713512ef739e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17918
32145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1791832145
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2506342485
Short name T507
Test name
Test status
Simulation time 186257154 ps
CPU time 0.93 seconds
Started Aug 06 08:06:16 PM PDT 24
Finished Aug 06 08:06:17 PM PDT 24
Peak memory 207312 kb
Host smart-9302c785-2e9e-4b1a-90a0-281490848f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25063
42485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2506342485
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.2700361632
Short name T1922
Test name
Test status
Simulation time 167461487 ps
CPU time 0.87 seconds
Started Aug 06 08:06:20 PM PDT 24
Finished Aug 06 08:06:21 PM PDT 24
Peak memory 207448 kb
Host smart-f074bd44-881c-4253-b579-e0f022f8aaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27003
61632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.2700361632
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.1614137444
Short name T2189
Test name
Test status
Simulation time 162679424 ps
CPU time 0.79 seconds
Started Aug 06 08:06:16 PM PDT 24
Finished Aug 06 08:06:17 PM PDT 24
Peak memory 207304 kb
Host smart-99583cd4-45a2-410d-bf3c-9686de6c3df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16141
37444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1614137444
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_rx_full.2801695544
Short name T1263
Test name
Test status
Simulation time 340089143 ps
CPU time 1.21 seconds
Started Aug 06 08:06:13 PM PDT 24
Finished Aug 06 08:06:14 PM PDT 24
Peak memory 207400 kb
Host smart-049fa512-f612-49e5-bf49-43135d2938a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28016
95544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.2801695544
Directory /workspace/29.usbdev_rx_full/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2711724721
Short name T1360
Test name
Test status
Simulation time 148579597 ps
CPU time 0.85 seconds
Started Aug 06 08:06:21 PM PDT 24
Finished Aug 06 08:06:22 PM PDT 24
Peak memory 207320 kb
Host smart-d750605d-e95a-4825-8d6d-ca7983ffa7a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27117
24721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2711724721
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3788174510
Short name T2106
Test name
Test status
Simulation time 147332831 ps
CPU time 0.82 seconds
Started Aug 06 08:06:13 PM PDT 24
Finished Aug 06 08:06:13 PM PDT 24
Peak memory 207324 kb
Host smart-c642da90-9af6-4a82-855f-face09c98c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37881
74510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3788174510
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1812726786
Short name T1277
Test name
Test status
Simulation time 216125711 ps
CPU time 0.93 seconds
Started Aug 06 08:06:15 PM PDT 24
Finished Aug 06 08:06:16 PM PDT 24
Peak memory 207396 kb
Host smart-6669bf3c-5834-45c8-b23c-1cd85c38c8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18127
26786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1812726786
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3831812191
Short name T1175
Test name
Test status
Simulation time 2678524289 ps
CPU time 20.73 seconds
Started Aug 06 08:06:16 PM PDT 24
Finished Aug 06 08:06:37 PM PDT 24
Peak memory 217616 kb
Host smart-06edc4c5-45d8-42a7-8c56-0a13e3303c98
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3831812191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3831812191
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.586065006
Short name T2576
Test name
Test status
Simulation time 217371222 ps
CPU time 0.96 seconds
Started Aug 06 08:06:16 PM PDT 24
Finished Aug 06 08:06:17 PM PDT 24
Peak memory 207320 kb
Host smart-0f0fc1a8-1861-44b9-8ba2-459db96a4b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58606
5006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.586065006
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1573839604
Short name T960
Test name
Test status
Simulation time 173579217 ps
CPU time 0.84 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:06:13 PM PDT 24
Peak memory 207356 kb
Host smart-c48694b5-9cb6-46d5-a45e-d25ef18722c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15738
39604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1573839604
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.771463452
Short name T1674
Test name
Test status
Simulation time 1256958897 ps
CPU time 3.2 seconds
Started Aug 06 08:06:15 PM PDT 24
Finished Aug 06 08:06:18 PM PDT 24
Peak memory 207428 kb
Host smart-170d5dba-ac53-4160-bd01-72d205fcb18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77146
3452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.771463452
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.2802530944
Short name T2605
Test name
Test status
Simulation time 1931643097 ps
CPU time 55.91 seconds
Started Aug 06 08:06:14 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 223932 kb
Host smart-824c9e47-6479-4ee9-9558-375d2760bb6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28025
30944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.2802530944
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.1732319813
Short name T2107
Test name
Test status
Simulation time 1054338667 ps
CPU time 23.14 seconds
Started Aug 06 08:06:16 PM PDT 24
Finished Aug 06 08:06:39 PM PDT 24
Peak memory 207608 kb
Host smart-65051773-19f8-476f-8c6a-debffafb944a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732319813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_hos
t_handshake.1732319813
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.1305979152
Short name T2322
Test name
Test status
Simulation time 40607403 ps
CPU time 0.67 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:01:57 PM PDT 24
Peak memory 207384 kb
Host smart-927c54fb-1aab-4ab4-9df6-eb5b65aa7408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1305979152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.1305979152
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3432184007
Short name T655
Test name
Test status
Simulation time 4237456697 ps
CPU time 6.09 seconds
Started Aug 06 08:02:00 PM PDT 24
Finished Aug 06 08:02:07 PM PDT 24
Peak memory 215848 kb
Host smart-dbf1aae0-9bf4-4133-8811-22552ef08a29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432184007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.3432184007
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.88447695
Short name T803
Test name
Test status
Simulation time 18757603094 ps
CPU time 21.03 seconds
Started Aug 06 08:01:56 PM PDT 24
Finished Aug 06 08:02:17 PM PDT 24
Peak memory 207632 kb
Host smart-4bc1b258-75c2-487b-9247-3e97830cb55f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=88447695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.88447695
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.1726958549
Short name T1676
Test name
Test status
Simulation time 30565241555 ps
CPU time 34.42 seconds
Started Aug 06 08:01:56 PM PDT 24
Finished Aug 06 08:02:31 PM PDT 24
Peak memory 207664 kb
Host smart-0e4138f5-7677-4a67-bedb-02d1bd817915
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726958549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.1726958549
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1863969136
Short name T1887
Test name
Test status
Simulation time 186590159 ps
CPU time 0.9 seconds
Started Aug 06 08:01:56 PM PDT 24
Finished Aug 06 08:01:57 PM PDT 24
Peak memory 207304 kb
Host smart-596191d4-ebaa-4676-b5cd-0a8dcb92a529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18639
69136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1863969136
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1438952311
Short name T56
Test name
Test status
Simulation time 149449166 ps
CPU time 0.9 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:00 PM PDT 24
Peak memory 207352 kb
Host smart-daebfbc7-11fd-47c6-8cde-205ae74001bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14389
52311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1438952311
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.3631845367
Short name T62
Test name
Test status
Simulation time 129754001 ps
CPU time 0.85 seconds
Started Aug 06 08:01:54 PM PDT 24
Finished Aug 06 08:01:55 PM PDT 24
Peak memory 207160 kb
Host smart-482cb9a2-7d9c-4acc-85df-7251c96e9a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36318
45367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.3631845367
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.1253021151
Short name T559
Test name
Test status
Simulation time 196220443 ps
CPU time 0.88 seconds
Started Aug 06 08:01:55 PM PDT 24
Finished Aug 06 08:01:55 PM PDT 24
Peak memory 207316 kb
Host smart-4e5aac73-3042-4526-b718-575fa8f74daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12530
21151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.1253021151
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1054608833
Short name T2672
Test name
Test status
Simulation time 389884950 ps
CPU time 1.33 seconds
Started Aug 06 08:01:55 PM PDT 24
Finished Aug 06 08:01:56 PM PDT 24
Peak memory 207252 kb
Host smart-d19df89a-513c-4f17-9465-d842359f6871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10546
08833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1054608833
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.4001101368
Short name T636
Test name
Test status
Simulation time 1255187142 ps
CPU time 3.19 seconds
Started Aug 06 08:02:01 PM PDT 24
Finished Aug 06 08:02:04 PM PDT 24
Peak memory 207604 kb
Host smart-c82e115b-ec59-40fa-822a-4263c93d4a02
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4001101368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.4001101368
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.1603532906
Short name T1694
Test name
Test status
Simulation time 59898241192 ps
CPU time 107.43 seconds
Started Aug 06 08:01:55 PM PDT 24
Finished Aug 06 08:03:42 PM PDT 24
Peak memory 207652 kb
Host smart-4fa99f77-b16a-4fa4-9b45-adbb21524e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16035
32906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1603532906
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.3294760054
Short name T714
Test name
Test status
Simulation time 415902901 ps
CPU time 7.64 seconds
Started Aug 06 08:01:56 PM PDT 24
Finished Aug 06 08:02:03 PM PDT 24
Peak memory 207624 kb
Host smart-b26ca1e4-abc6-47d3-9f57-7d75e0db7830
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294760054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.3294760054
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.4265582832
Short name T1613
Test name
Test status
Simulation time 616945551 ps
CPU time 1.81 seconds
Started Aug 06 08:01:56 PM PDT 24
Finished Aug 06 08:01:58 PM PDT 24
Peak memory 207376 kb
Host smart-9eae4d7b-f6ce-4a16-83e0-3007973a44b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655
82832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.4265582832
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1920642901
Short name T1312
Test name
Test status
Simulation time 140457912 ps
CPU time 0.8 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:01:58 PM PDT 24
Peak memory 207280 kb
Host smart-d32b1b3d-48f9-49e1-8d78-8f8510f3b337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19206
42901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1920642901
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.4076907079
Short name T1306
Test name
Test status
Simulation time 65473018 ps
CPU time 0.75 seconds
Started Aug 06 08:01:55 PM PDT 24
Finished Aug 06 08:01:56 PM PDT 24
Peak memory 207368 kb
Host smart-65d35cf0-8b2f-48ed-87a0-d4cfce23cd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40769
07079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.4076907079
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.2169637095
Short name T483
Test name
Test status
Simulation time 808144075 ps
CPU time 2.2 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:02 PM PDT 24
Peak memory 207564 kb
Host smart-190b8c4c-553f-4d09-8718-d1b5886709a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21696
37095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2169637095
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_types.4087783517
Short name T2533
Test name
Test status
Simulation time 229255664 ps
CPU time 0.99 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:01:59 PM PDT 24
Peak memory 207388 kb
Host smart-2f3cf879-fbe9-485c-9abc-e5f65ddc5bd2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4087783517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.4087783517
Directory /workspace/3.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3186030859
Short name T2094
Test name
Test status
Simulation time 298614564 ps
CPU time 2.42 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:01:59 PM PDT 24
Peak memory 207588 kb
Host smart-c585cbdc-490b-47fe-930c-fd1627d002cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31860
30859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3186030859
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3933526873
Short name T1475
Test name
Test status
Simulation time 85209116812 ps
CPU time 143.42 seconds
Started Aug 06 08:01:56 PM PDT 24
Finished Aug 06 08:04:20 PM PDT 24
Peak memory 207712 kb
Host smart-feae2743-9d4d-4e0f-bbaf-bad53c5b64c8
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3933526873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3933526873
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.1008725077
Short name T1735
Test name
Test status
Simulation time 91105216395 ps
CPU time 164.53 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:04:42 PM PDT 24
Peak memory 207628 kb
Host smart-2ec15eef-69e4-4e05-8e5b-abcecbc35643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008725077 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.1008725077
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.2308317928
Short name T335
Test name
Test status
Simulation time 103114820657 ps
CPU time 161.6 seconds
Started Aug 06 08:01:56 PM PDT 24
Finished Aug 06 08:04:37 PM PDT 24
Peak memory 207668 kb
Host smart-0a9bba42-2261-4899-902f-b8de1fd20998
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2308317928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.2308317928
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.394883143
Short name T1592
Test name
Test status
Simulation time 117942282609 ps
CPU time 189.53 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:05:07 PM PDT 24
Peak memory 207612 kb
Host smart-a065bc18-a57a-4dbc-aa5b-63f876cd3ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394883143 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.394883143
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.3868836184
Short name T2290
Test name
Test status
Simulation time 93111025537 ps
CPU time 177.36 seconds
Started Aug 06 08:02:01 PM PDT 24
Finished Aug 06 08:04:59 PM PDT 24
Peak memory 207676 kb
Host smart-5e05d208-6b29-4496-89b6-94c4c028f625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38688
36184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.3868836184
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.2824173765
Short name T978
Test name
Test status
Simulation time 206269721 ps
CPU time 1.01 seconds
Started Aug 06 08:01:55 PM PDT 24
Finished Aug 06 08:01:57 PM PDT 24
Peak memory 215824 kb
Host smart-fef04416-c2f0-4d88-ae15-9ff03e4fcd5c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2824173765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2824173765
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3766879043
Short name T2821
Test name
Test status
Simulation time 148128942 ps
CPU time 0.82 seconds
Started Aug 06 08:01:54 PM PDT 24
Finished Aug 06 08:01:55 PM PDT 24
Peak memory 207280 kb
Host smart-508fcab8-467c-428c-97b3-c93df2306227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37668
79043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3766879043
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.450379214
Short name T2653
Test name
Test status
Simulation time 235997344 ps
CPU time 0.96 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:01:58 PM PDT 24
Peak memory 207308 kb
Host smart-5f9d4149-a940-4560-a9af-0754f6b50d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45037
9214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.450379214
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.4155250960
Short name T3033
Test name
Test status
Simulation time 4519271407 ps
CPU time 45.56 seconds
Started Aug 06 08:02:02 PM PDT 24
Finished Aug 06 08:02:48 PM PDT 24
Peak memory 224040 kb
Host smart-bb51df78-7684-40d3-b757-2ca40ed51512
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4155250960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.4155250960
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.602968131
Short name T905
Test name
Test status
Simulation time 9467065110 ps
CPU time 122.99 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:04:00 PM PDT 24
Peak memory 207600 kb
Host smart-a946489e-3b39-4135-8f9b-aaae65cfbbde
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=602968131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.602968131
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1232963355
Short name T2095
Test name
Test status
Simulation time 263529114 ps
CPU time 1.02 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:01:59 PM PDT 24
Peak memory 207340 kb
Host smart-185ae94e-c2d2-44e8-8aa6-664c2b7dd04e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12329
63355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1232963355
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.3746093889
Short name T2319
Test name
Test status
Simulation time 24745325712 ps
CPU time 27.31 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:02:25 PM PDT 24
Peak memory 215824 kb
Host smart-1d004724-39d8-4d76-9be3-055882894717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37460
93889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.3746093889
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.3691314108
Short name T930
Test name
Test status
Simulation time 10904313561 ps
CPU time 14.15 seconds
Started Aug 06 08:01:56 PM PDT 24
Finished Aug 06 08:02:10 PM PDT 24
Peak memory 207668 kb
Host smart-37bffc83-e9ce-4c72-bb4f-8076b397ca76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36913
14108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.3691314108
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1602133336
Short name T1665
Test name
Test status
Simulation time 3622445434 ps
CPU time 33.95 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 218232 kb
Host smart-2a8c7c4f-a97e-4a36-849e-8c93d193cf55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16021
33336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1602133336
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.3039286951
Short name T832
Test name
Test status
Simulation time 1946877509 ps
CPU time 15.58 seconds
Started Aug 06 08:01:55 PM PDT 24
Finished Aug 06 08:02:10 PM PDT 24
Peak memory 217144 kb
Host smart-27b6e0f1-0e9b-4499-bcbc-3300253e19ac
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3039286951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.3039286951
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.1164167858
Short name T605
Test name
Test status
Simulation time 232538601 ps
CPU time 0.92 seconds
Started Aug 06 08:01:55 PM PDT 24
Finished Aug 06 08:01:57 PM PDT 24
Peak memory 207380 kb
Host smart-6d95bece-0db6-4e30-be6a-448c84523e61
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1164167858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.1164167858
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2661699348
Short name T2952
Test name
Test status
Simulation time 187756747 ps
CPU time 0.9 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:01:59 PM PDT 24
Peak memory 207372 kb
Host smart-77e25272-c6cf-4dfb-9d5e-60ff2cd31db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26616
99348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2661699348
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.2560108022
Short name T2035
Test name
Test status
Simulation time 3144375655 ps
CPU time 94.91 seconds
Started Aug 06 08:01:55 PM PDT 24
Finished Aug 06 08:03:30 PM PDT 24
Peak memory 215796 kb
Host smart-444bb5f1-187e-4bb3-91ec-1879b5c443b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25601
08022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.2560108022
Directory /workspace/3.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1818878466
Short name T2836
Test name
Test status
Simulation time 2476509969 ps
CPU time 27.36 seconds
Started Aug 06 08:02:01 PM PDT 24
Finished Aug 06 08:02:29 PM PDT 24
Peak memory 224076 kb
Host smart-6f57514e-fe43-4a11-a036-a828d2271ab6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1818878466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1818878466
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.157908578
Short name T1002
Test name
Test status
Simulation time 1841534230 ps
CPU time 13.56 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:02:11 PM PDT 24
Peak memory 215712 kb
Host smart-d1285faa-2a42-417f-9f45-994c36a4e7ed
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=157908578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.157908578
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.4054682870
Short name T485
Test name
Test status
Simulation time 148665985 ps
CPU time 0.89 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:01:59 PM PDT 24
Peak memory 207364 kb
Host smart-69db61d6-06f2-418e-982c-c2149a94ed82
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4054682870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.4054682870
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2060338714
Short name T1781
Test name
Test status
Simulation time 147705751 ps
CPU time 0.84 seconds
Started Aug 06 08:01:55 PM PDT 24
Finished Aug 06 08:01:56 PM PDT 24
Peak memory 207376 kb
Host smart-57b9d4bd-370e-4327-91d9-4223ce0d4e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20603
38714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2060338714
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3479685322
Short name T2015
Test name
Test status
Simulation time 164906976 ps
CPU time 0.95 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:01:59 PM PDT 24
Peak memory 207304 kb
Host smart-847b4680-467e-4c3b-ae09-41c16e837ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34796
85322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3479685322
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.938126053
Short name T127
Test name
Test status
Simulation time 172951221 ps
CPU time 0.89 seconds
Started Aug 06 08:01:56 PM PDT 24
Finished Aug 06 08:01:57 PM PDT 24
Peak memory 207396 kb
Host smart-4422ad04-4684-40e1-9d05-a75f7043566a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93812
6053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.938126053
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.788142711
Short name T504
Test name
Test status
Simulation time 153271096 ps
CPU time 0.87 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:01:59 PM PDT 24
Peak memory 207304 kb
Host smart-e8c13dd7-679e-4c9c-9036-56c5d4845f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78814
2711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.788142711
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1274418352
Short name T2727
Test name
Test status
Simulation time 205059088 ps
CPU time 0.96 seconds
Started Aug 06 08:02:01 PM PDT 24
Finished Aug 06 08:02:02 PM PDT 24
Peak memory 207372 kb
Host smart-662dc084-ab4a-4284-8bab-fc36520781b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12744
18352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1274418352
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1560695253
Short name T203
Test name
Test status
Simulation time 191135082 ps
CPU time 0.9 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:01:58 PM PDT 24
Peak memory 207348 kb
Host smart-0ac52fb3-f13d-4012-89d4-6717c9ce9fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15606
95253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1560695253
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.3468219670
Short name T2154
Test name
Test status
Simulation time 243252011 ps
CPU time 1.06 seconds
Started Aug 06 08:02:01 PM PDT 24
Finished Aug 06 08:02:02 PM PDT 24
Peak memory 207388 kb
Host smart-91a44556-0d11-4a2c-a807-a2aa5f0e94dd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3468219670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.3468219670
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.1720126770
Short name T1057
Test name
Test status
Simulation time 220160532 ps
CPU time 0.97 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:00 PM PDT 24
Peak memory 207328 kb
Host smart-4577a239-5317-4ff0-ad5e-1b740debb20a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17201
26770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.1720126770
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2445070511
Short name T2039
Test name
Test status
Simulation time 139253171 ps
CPU time 0.8 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:01:59 PM PDT 24
Peak memory 207316 kb
Host smart-d5b6fc46-22e9-40e5-a55a-072a0cd0b601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24450
70511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2445070511
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2877574187
Short name T25
Test name
Test status
Simulation time 109718288 ps
CPU time 0.81 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:01:58 PM PDT 24
Peak memory 207316 kb
Host smart-eb8bf535-30e7-4153-aca0-1197c5d0e419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28775
74187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2877574187
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2764898513
Short name T2850
Test name
Test status
Simulation time 193629550 ps
CPU time 0.94 seconds
Started Aug 06 08:02:00 PM PDT 24
Finished Aug 06 08:02:02 PM PDT 24
Peak memory 207368 kb
Host smart-9f917b71-e762-45c1-9a76-a21b386249df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648
98513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2764898513
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2679836070
Short name T2022
Test name
Test status
Simulation time 221909586 ps
CPU time 1 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:01:58 PM PDT 24
Peak memory 207388 kb
Host smart-5bc97cfe-a2cf-4847-a7e2-8a1f1e46b577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26798
36070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2679836070
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2855444035
Short name T2853
Test name
Test status
Simulation time 10264328528 ps
CPU time 67.31 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:03:07 PM PDT 24
Peak memory 224024 kb
Host smart-453ece0d-8000-4819-aa75-73a5f88eea59
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2855444035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2855444035
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3258796604
Short name T759
Test name
Test status
Simulation time 7033975480 ps
CPU time 32.31 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:02:30 PM PDT 24
Peak memory 224032 kb
Host smart-122cbdb1-d4da-4d48-801b-90ed584aa194
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258796604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3258796604
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.1424745739
Short name T1848
Test name
Test status
Simulation time 241143815 ps
CPU time 1 seconds
Started Aug 06 08:01:56 PM PDT 24
Finished Aug 06 08:01:57 PM PDT 24
Peak memory 207304 kb
Host smart-040e27b4-aa50-4547-a9ee-5dd10e3c9937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14247
45739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.1424745739
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.2459065762
Short name T517
Test name
Test status
Simulation time 151218327 ps
CPU time 0.86 seconds
Started Aug 06 08:02:02 PM PDT 24
Finished Aug 06 08:02:03 PM PDT 24
Peak memory 207344 kb
Host smart-1bede2c3-7a6b-4a0d-8023-c38e52f05b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24590
65762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.2459065762
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_resume_link_active.2685621900
Short name T117
Test name
Test status
Simulation time 20181009918 ps
CPU time 23.45 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:22 PM PDT 24
Peak memory 207464 kb
Host smart-c9c5b7f5-d422-4c78-8d9a-eaef254aaf36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26856
21900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.2685621900
Directory /workspace/3.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1459981940
Short name T1063
Test name
Test status
Simulation time 153853005 ps
CPU time 0.86 seconds
Started Aug 06 08:02:02 PM PDT 24
Finished Aug 06 08:02:03 PM PDT 24
Peak memory 207336 kb
Host smart-03830178-be3e-48e4-874d-c41774b78fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14599
81940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1459981940
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_full.3339761658
Short name T319
Test name
Test status
Simulation time 261076331 ps
CPU time 1.13 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:01 PM PDT 24
Peak memory 207356 kb
Host smart-038e18d8-8d8d-4235-8691-2078e091afd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33397
61658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.3339761658
Directory /workspace/3.usbdev_rx_full/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.2835273180
Short name T78
Test name
Test status
Simulation time 177171685 ps
CPU time 0.87 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:01:58 PM PDT 24
Peak memory 207364 kb
Host smart-18685d14-98d6-4e7b-bdef-13d2cbc21d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28352
73180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2835273180
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3880289749
Short name T222
Test name
Test status
Simulation time 844375318 ps
CPU time 1.77 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:01 PM PDT 24
Peak memory 224464 kb
Host smart-a9583577-a44c-42cb-84ab-1c937e8e557b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3880289749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3880289749
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.2447577558
Short name T2818
Test name
Test status
Simulation time 392965874 ps
CPU time 1.43 seconds
Started Aug 06 08:02:01 PM PDT 24
Finished Aug 06 08:02:03 PM PDT 24
Peak memory 207380 kb
Host smart-0aaf7f32-6546-464a-a91b-fcc8beffb97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24475
77558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.2447577558
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.720727582
Short name T1544
Test name
Test status
Simulation time 226772663 ps
CPU time 0.97 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:01:58 PM PDT 24
Peak memory 207348 kb
Host smart-637b0e3a-d987-4744-bced-e362d8b928ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72072
7582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.720727582
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3675258159
Short name T716
Test name
Test status
Simulation time 148421603 ps
CPU time 0.8 seconds
Started Aug 06 08:02:00 PM PDT 24
Finished Aug 06 08:02:01 PM PDT 24
Peak memory 207340 kb
Host smart-cab56348-024f-4d32-b4a3-c28aa68c8e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36752
58159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3675258159
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1212254452
Short name T1625
Test name
Test status
Simulation time 153740982 ps
CPU time 0.85 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:01:59 PM PDT 24
Peak memory 207360 kb
Host smart-10a4a80d-ae7d-4f8c-96d7-c757e6343162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12122
54452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1212254452
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3314405841
Short name T2238
Test name
Test status
Simulation time 271468647 ps
CPU time 1.07 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:00 PM PDT 24
Peak memory 207352 kb
Host smart-994d3904-fe6a-4bed-853f-551c9df0129c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33144
05841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3314405841
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3411716863
Short name T2220
Test name
Test status
Simulation time 3256697632 ps
CPU time 94.63 seconds
Started Aug 06 08:02:00 PM PDT 24
Finished Aug 06 08:03:35 PM PDT 24
Peak memory 215868 kb
Host smart-a412214a-b880-4311-8987-4cab03ff1192
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3411716863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3411716863
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1706228781
Short name T2851
Test name
Test status
Simulation time 165022691 ps
CPU time 0.82 seconds
Started Aug 06 08:02:00 PM PDT 24
Finished Aug 06 08:02:00 PM PDT 24
Peak memory 207360 kb
Host smart-9218eda9-f3ac-45b7-97ff-c32714991e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17062
28781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1706228781
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1750549846
Short name T822
Test name
Test status
Simulation time 198355811 ps
CPU time 0.88 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:00 PM PDT 24
Peak memory 207336 kb
Host smart-8406d074-81fd-4d36-b380-be7544de0779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17505
49846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1750549846
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.3358313660
Short name T1564
Test name
Test status
Simulation time 965729979 ps
CPU time 2.36 seconds
Started Aug 06 08:02:03 PM PDT 24
Finished Aug 06 08:02:05 PM PDT 24
Peak memory 207564 kb
Host smart-30814eb4-12d2-4074-ad10-25e61643cb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33583
13660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3358313660
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.885456372
Short name T798
Test name
Test status
Simulation time 3552183942 ps
CPU time 26.64 seconds
Started Aug 06 08:02:01 PM PDT 24
Finished Aug 06 08:02:27 PM PDT 24
Peak memory 207636 kb
Host smart-de354cda-0c9d-448c-a5ca-cf278161e0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88545
6372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.885456372
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.3221251324
Short name T81
Test name
Test status
Simulation time 10936224340 ps
CPU time 56.67 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 223920 kb
Host smart-a20ffcc0-5e0a-40e6-b542-060402a0a76c
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221251324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.3221251324
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.3285038492
Short name T2742
Test name
Test status
Simulation time 2910976986 ps
CPU time 19.51 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:02:17 PM PDT 24
Peak memory 207668 kb
Host smart-7d0aec75-bc03-480a-afe3-26799b2e1e90
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285038492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.3285038492
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.767994006
Short name T1104
Test name
Test status
Simulation time 64685452 ps
CPU time 0.76 seconds
Started Aug 06 08:06:28 PM PDT 24
Finished Aug 06 08:06:28 PM PDT 24
Peak memory 207416 kb
Host smart-71cc4613-ff17-4620-8e4a-4ee08869626e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=767994006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.767994006
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3793634852
Short name T1530
Test name
Test status
Simulation time 12076579243 ps
CPU time 14.86 seconds
Started Aug 06 08:06:13 PM PDT 24
Finished Aug 06 08:06:28 PM PDT 24
Peak memory 207576 kb
Host smart-c28d6608-edfe-42c8-a005-458fd0fde7aa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793634852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.3793634852
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2947519374
Short name T2935
Test name
Test status
Simulation time 19664376966 ps
CPU time 24.49 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:35 PM PDT 24
Peak memory 207636 kb
Host smart-101d4060-c1d5-4cb4-8f77-c07b7dcd9c18
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947519374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2947519374
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.357547784
Short name T3047
Test name
Test status
Simulation time 24142809436 ps
CPU time 30.92 seconds
Started Aug 06 08:06:19 PM PDT 24
Finished Aug 06 08:06:50 PM PDT 24
Peak memory 215848 kb
Host smart-35328f1f-7aee-4960-9cb1-d6d614584d49
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357547784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ao
n_wake_resume.357547784
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.459954870
Short name T1728
Test name
Test status
Simulation time 193449717 ps
CPU time 0.93 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:06:13 PM PDT 24
Peak memory 207376 kb
Host smart-29abf8a5-791b-4bdc-b62c-cec75dfcbe13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45995
4870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.459954870
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.950808404
Short name T1824
Test name
Test status
Simulation time 172213059 ps
CPU time 0.82 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:12 PM PDT 24
Peak memory 207324 kb
Host smart-ca636daf-7d59-4450-8506-617682430ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95080
8404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.950808404
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1129519219
Short name T2083
Test name
Test status
Simulation time 377502704 ps
CPU time 1.3 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:06:13 PM PDT 24
Peak memory 207340 kb
Host smart-55749a07-84d8-4c3d-ae43-5dc4908a0d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11295
19219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1129519219
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3110446957
Short name T739
Test name
Test status
Simulation time 446048586 ps
CPU time 1.31 seconds
Started Aug 06 08:06:08 PM PDT 24
Finished Aug 06 08:06:09 PM PDT 24
Peak memory 207356 kb
Host smart-e933e75b-29f5-4c3d-826e-b6954126000d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3110446957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3110446957
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.2770168596
Short name T2650
Test name
Test status
Simulation time 58841165109 ps
CPU time 96.63 seconds
Started Aug 06 08:06:09 PM PDT 24
Finished Aug 06 08:07:46 PM PDT 24
Peak memory 207672 kb
Host smart-720e80ed-2c52-43f9-89a1-62b6d36df17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27701
68596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.2770168596
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.3448575375
Short name T800
Test name
Test status
Simulation time 1388936451 ps
CPU time 33.94 seconds
Started Aug 06 08:06:17 PM PDT 24
Finished Aug 06 08:06:51 PM PDT 24
Peak memory 207564 kb
Host smart-80d4bcf2-9f06-4f55-99d3-5b27ca1806a2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448575375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.3448575375
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1117566681
Short name T763
Test name
Test status
Simulation time 562413887 ps
CPU time 1.55 seconds
Started Aug 06 08:06:13 PM PDT 24
Finished Aug 06 08:06:14 PM PDT 24
Peak memory 207356 kb
Host smart-80d82d23-e7e0-41e5-b26b-ac8926570ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11175
66681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1117566681
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1391448447
Short name T584
Test name
Test status
Simulation time 138001988 ps
CPU time 0.8 seconds
Started Aug 06 08:06:11 PM PDT 24
Finished Aug 06 08:06:12 PM PDT 24
Peak memory 207304 kb
Host smart-4e2e685d-9105-4e1a-9178-3339d806804c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13914
48447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1391448447
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.1596020958
Short name T2767
Test name
Test status
Simulation time 96344416 ps
CPU time 0.77 seconds
Started Aug 06 08:06:18 PM PDT 24
Finished Aug 06 08:06:18 PM PDT 24
Peak memory 207320 kb
Host smart-496ec699-1c78-440a-a2bf-3cbd487a4f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15960
20958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1596020958
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.2879063125
Short name T1558
Test name
Test status
Simulation time 844842558 ps
CPU time 2.4 seconds
Started Aug 06 08:06:13 PM PDT 24
Finished Aug 06 08:06:16 PM PDT 24
Peak memory 207572 kb
Host smart-c185b624-f027-4a55-81e8-3942b908a59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28790
63125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.2879063125
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_types.2696514538
Short name T397
Test name
Test status
Simulation time 284310538 ps
CPU time 1.01 seconds
Started Aug 06 08:06:15 PM PDT 24
Finished Aug 06 08:06:16 PM PDT 24
Peak memory 207264 kb
Host smart-57e26a31-8882-49a7-b236-acef969f2c0e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2696514538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.2696514538
Directory /workspace/30.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3192651270
Short name T211
Test name
Test status
Simulation time 344639269 ps
CPU time 2.63 seconds
Started Aug 06 08:06:17 PM PDT 24
Finished Aug 06 08:06:20 PM PDT 24
Peak memory 207488 kb
Host smart-0c9f1184-1edc-4e24-9ae0-4db961408212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31926
51270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3192651270
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1588792869
Short name T3112
Test name
Test status
Simulation time 208407691 ps
CPU time 1.18 seconds
Started Aug 06 08:06:16 PM PDT 24
Finished Aug 06 08:06:17 PM PDT 24
Peak memory 207536 kb
Host smart-ef0e911b-dfec-4a5a-bc01-6678d5e7e833
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1588792869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1588792869
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.276430150
Short name T100
Test name
Test status
Simulation time 141438771 ps
CPU time 0.79 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:06:11 PM PDT 24
Peak memory 207260 kb
Host smart-b15e0d0f-ed29-4c67-a8ed-353261301bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27643
0150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.276430150
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.886753589
Short name T2053
Test name
Test status
Simulation time 262778287 ps
CPU time 1 seconds
Started Aug 06 08:06:17 PM PDT 24
Finished Aug 06 08:06:18 PM PDT 24
Peak memory 207352 kb
Host smart-8bdc4f0f-5b15-4f8f-a6d4-421b5172f5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88675
3589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.886753589
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.2811263858
Short name T1375
Test name
Test status
Simulation time 4878537288 ps
CPU time 143.22 seconds
Started Aug 06 08:06:10 PM PDT 24
Finished Aug 06 08:08:34 PM PDT 24
Peak memory 218172 kb
Host smart-e69e88ea-ae14-4905-a886-d5454436dc76
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2811263858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2811263858
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.1557992874
Short name T2561
Test name
Test status
Simulation time 9028178373 ps
CPU time 113.96 seconds
Started Aug 06 08:06:32 PM PDT 24
Finished Aug 06 08:08:26 PM PDT 24
Peak memory 207700 kb
Host smart-67f27da3-30af-47c6-8297-632bb9835126
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1557992874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.1557992874
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1447951857
Short name T1917
Test name
Test status
Simulation time 238390752 ps
CPU time 0.93 seconds
Started Aug 06 08:06:31 PM PDT 24
Finished Aug 06 08:06:32 PM PDT 24
Peak memory 207320 kb
Host smart-64000871-9af9-444b-b581-d0a25413668b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14479
51857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1447951857
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.2487150813
Short name T2932
Test name
Test status
Simulation time 13741608098 ps
CPU time 18.52 seconds
Started Aug 06 08:06:30 PM PDT 24
Finished Aug 06 08:06:49 PM PDT 24
Peak memory 207640 kb
Host smart-8a014148-2f73-4a30-9eb9-fb88b083f6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24871
50813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.2487150813
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3109031604
Short name T3042
Test name
Test status
Simulation time 10699011004 ps
CPU time 14.8 seconds
Started Aug 06 08:06:33 PM PDT 24
Finished Aug 06 08:06:48 PM PDT 24
Peak memory 207496 kb
Host smart-60be91f1-d7cb-49b2-9a07-b842a576477f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31090
31604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3109031604
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.4194111003
Short name T1329
Test name
Test status
Simulation time 3090108697 ps
CPU time 23.65 seconds
Started Aug 06 08:06:24 PM PDT 24
Finished Aug 06 08:06:48 PM PDT 24
Peak memory 215860 kb
Host smart-ba392817-4f35-4283-9ebe-34ef5bc7bd05
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4194111003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.4194111003
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.3477786855
Short name T1897
Test name
Test status
Simulation time 265420790 ps
CPU time 1.09 seconds
Started Aug 06 08:06:27 PM PDT 24
Finished Aug 06 08:06:29 PM PDT 24
Peak memory 207348 kb
Host smart-fa79f6eb-1a6b-4c82-9ace-ab36d3e51e09
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3477786855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.3477786855
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1083956121
Short name T2719
Test name
Test status
Simulation time 211921060 ps
CPU time 0.97 seconds
Started Aug 06 08:06:32 PM PDT 24
Finished Aug 06 08:06:33 PM PDT 24
Peak memory 207352 kb
Host smart-5984d88a-9628-4cd2-b5df-6eb5bf1840d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10839
56121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1083956121
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.19474644
Short name T1966
Test name
Test status
Simulation time 2473422226 ps
CPU time 69.07 seconds
Started Aug 06 08:06:31 PM PDT 24
Finished Aug 06 08:07:40 PM PDT 24
Peak memory 217532 kb
Host smart-7fd139ef-328f-4808-941c-18400aaef4a5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=19474644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.19474644
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3933143358
Short name T2807
Test name
Test status
Simulation time 158756335 ps
CPU time 0.87 seconds
Started Aug 06 08:06:33 PM PDT 24
Finished Aug 06 08:06:34 PM PDT 24
Peak memory 207396 kb
Host smart-5ab7bff5-d4bb-4660-9950-afbd731b98f0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3933143358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3933143358
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3424473708
Short name T603
Test name
Test status
Simulation time 142323735 ps
CPU time 0.86 seconds
Started Aug 06 08:06:19 PM PDT 24
Finished Aug 06 08:06:20 PM PDT 24
Peak memory 207296 kb
Host smart-41b4e114-277b-4f55-a647-1ffb5eacd378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34244
73708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3424473708
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3044018988
Short name T3081
Test name
Test status
Simulation time 192743975 ps
CPU time 0.95 seconds
Started Aug 06 08:06:27 PM PDT 24
Finished Aug 06 08:06:28 PM PDT 24
Peak memory 207396 kb
Host smart-d897e67b-20d8-4b95-8a7f-0fa58f19fc2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30440
18988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3044018988
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.530721438
Short name T748
Test name
Test status
Simulation time 166801601 ps
CPU time 0.95 seconds
Started Aug 06 08:06:28 PM PDT 24
Finished Aug 06 08:06:29 PM PDT 24
Peak memory 207356 kb
Host smart-3ba9c540-a82d-4579-b80d-3a43de512d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53072
1438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.530721438
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2296857909
Short name T2264
Test name
Test status
Simulation time 197726332 ps
CPU time 0.89 seconds
Started Aug 06 08:06:27 PM PDT 24
Finished Aug 06 08:06:28 PM PDT 24
Peak memory 207352 kb
Host smart-fbab1fdc-b22b-4c64-806d-33b8b9069733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22968
57909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2296857909
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.575387554
Short name T2514
Test name
Test status
Simulation time 187947513 ps
CPU time 0.92 seconds
Started Aug 06 08:06:29 PM PDT 24
Finished Aug 06 08:06:30 PM PDT 24
Peak memory 207372 kb
Host smart-88db10bd-619e-43e2-adae-c30ed69abd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57538
7554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.575387554
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3092632914
Short name T1389
Test name
Test status
Simulation time 160158568 ps
CPU time 0.86 seconds
Started Aug 06 08:06:34 PM PDT 24
Finished Aug 06 08:06:35 PM PDT 24
Peak memory 207404 kb
Host smart-9c0e3ef1-844c-4860-8002-1d81d1b0729a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30926
32914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3092632914
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.631775418
Short name T1100
Test name
Test status
Simulation time 266584876 ps
CPU time 1.07 seconds
Started Aug 06 08:06:27 PM PDT 24
Finished Aug 06 08:06:28 PM PDT 24
Peak memory 207356 kb
Host smart-a92ffb26-c73c-48e5-9393-963f0a71dd8f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=631775418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.631775418
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2537259348
Short name T2817
Test name
Test status
Simulation time 150066097 ps
CPU time 0.84 seconds
Started Aug 06 08:06:29 PM PDT 24
Finished Aug 06 08:06:30 PM PDT 24
Peak memory 207328 kb
Host smart-367b466b-489f-4b70-bfe0-6651611975cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25372
59348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2537259348
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2838330092
Short name T2970
Test name
Test status
Simulation time 67976548 ps
CPU time 0.78 seconds
Started Aug 06 08:06:37 PM PDT 24
Finished Aug 06 08:06:38 PM PDT 24
Peak memory 207360 kb
Host smart-a219f772-126b-4100-86ac-f5aa2c1eac42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28383
30092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2838330092
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3235670403
Short name T286
Test name
Test status
Simulation time 16386168752 ps
CPU time 41.67 seconds
Started Aug 06 08:06:30 PM PDT 24
Finished Aug 06 08:07:12 PM PDT 24
Peak memory 215872 kb
Host smart-5735b672-cae7-4627-a18a-5e70a6048ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32356
70403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3235670403
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2047531688
Short name T700
Test name
Test status
Simulation time 223438623 ps
CPU time 0.99 seconds
Started Aug 06 08:06:26 PM PDT 24
Finished Aug 06 08:06:27 PM PDT 24
Peak memory 207352 kb
Host smart-758e667a-5e76-49e9-b402-2c330bbcf962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20475
31688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2047531688
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3384615589
Short name T2530
Test name
Test status
Simulation time 289068503 ps
CPU time 1.08 seconds
Started Aug 06 08:06:31 PM PDT 24
Finished Aug 06 08:06:32 PM PDT 24
Peak memory 207292 kb
Host smart-ddd8508a-c814-420e-bf20-5caf8beede7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33846
15589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3384615589
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.905993134
Short name T92
Test name
Test status
Simulation time 274180267 ps
CPU time 1.13 seconds
Started Aug 06 08:06:31 PM PDT 24
Finished Aug 06 08:06:33 PM PDT 24
Peak memory 207352 kb
Host smart-3100eb19-afc5-4621-bdd9-a62d4d5354fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90599
3134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.905993134
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.1777988847
Short name T965
Test name
Test status
Simulation time 184842120 ps
CPU time 0.89 seconds
Started Aug 06 08:06:35 PM PDT 24
Finished Aug 06 08:06:36 PM PDT 24
Peak memory 207288 kb
Host smart-4571df86-c3dd-48d6-9739-dd2b9057f23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17779
88847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1777988847
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1868225629
Short name T771
Test name
Test status
Simulation time 192520986 ps
CPU time 0.92 seconds
Started Aug 06 08:06:29 PM PDT 24
Finished Aug 06 08:06:30 PM PDT 24
Peak memory 207332 kb
Host smart-6eb756b6-6d65-4232-ba1b-1c9083721a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18682
25629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1868225629
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_rx_full.1958475406
Short name T2320
Test name
Test status
Simulation time 276582964 ps
CPU time 1.05 seconds
Started Aug 06 08:06:20 PM PDT 24
Finished Aug 06 08:06:21 PM PDT 24
Peak memory 207372 kb
Host smart-4ded477a-d9be-4c09-83fe-e54a62dd410a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19584
75406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.1958475406
Directory /workspace/30.usbdev_rx_full/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.4089051845
Short name T928
Test name
Test status
Simulation time 163601595 ps
CPU time 0.89 seconds
Started Aug 06 08:06:32 PM PDT 24
Finished Aug 06 08:06:33 PM PDT 24
Peak memory 207344 kb
Host smart-a1957722-42fe-4a92-9ac1-b6f3a92a5311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40890
51845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.4089051845
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1068908555
Short name T482
Test name
Test status
Simulation time 159634757 ps
CPU time 0.86 seconds
Started Aug 06 08:06:26 PM PDT 24
Finished Aug 06 08:06:27 PM PDT 24
Peak memory 207308 kb
Host smart-680948f6-f9ef-4d3b-a36f-69fe0c1596e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10689
08555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1068908555
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1204021399
Short name T2348
Test name
Test status
Simulation time 243147500 ps
CPU time 1.09 seconds
Started Aug 06 08:06:31 PM PDT 24
Finished Aug 06 08:06:33 PM PDT 24
Peak memory 207356 kb
Host smart-8f024364-218c-40b7-961b-c9cb703fae7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12040
21399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1204021399
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2316406603
Short name T2701
Test name
Test status
Simulation time 2350498878 ps
CPU time 66.93 seconds
Started Aug 06 08:06:27 PM PDT 24
Finished Aug 06 08:07:34 PM PDT 24
Peak memory 217596 kb
Host smart-e57e9df0-728d-41c8-999b-76d36a804ae4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2316406603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2316406603
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1413559020
Short name T2645
Test name
Test status
Simulation time 157320995 ps
CPU time 0.86 seconds
Started Aug 06 08:06:26 PM PDT 24
Finished Aug 06 08:06:27 PM PDT 24
Peak memory 207404 kb
Host smart-6fa3a1ef-bff3-49a5-ae9c-86a4e1df7961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14135
59020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1413559020
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.387236166
Short name T994
Test name
Test status
Simulation time 190198746 ps
CPU time 0.9 seconds
Started Aug 06 08:06:20 PM PDT 24
Finished Aug 06 08:06:21 PM PDT 24
Peak memory 207340 kb
Host smart-044cbc95-6246-4edd-916a-576489655ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38723
6166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.387236166
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.3093177187
Short name T662
Test name
Test status
Simulation time 903510571 ps
CPU time 2.3 seconds
Started Aug 06 08:06:35 PM PDT 24
Finished Aug 06 08:06:38 PM PDT 24
Peak memory 207468 kb
Host smart-7c4e1144-685f-4bc0-8b81-d20832ad4ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30931
77187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3093177187
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.1202956943
Short name T1936
Test name
Test status
Simulation time 2351556591 ps
CPU time 17 seconds
Started Aug 06 08:06:34 PM PDT 24
Finished Aug 06 08:06:51 PM PDT 24
Peak memory 207692 kb
Host smart-dd591208-60d0-458e-8b1b-d58e22c22ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12029
56943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.1202956943
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.3772229093
Short name T2096
Test name
Test status
Simulation time 701446603 ps
CPU time 16.19 seconds
Started Aug 06 08:06:12 PM PDT 24
Finished Aug 06 08:06:28 PM PDT 24
Peak memory 207532 kb
Host smart-e3a1b059-ee0f-4d07-b19d-c6b73b9ce694
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772229093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.3772229093
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2940223882
Short name T2537
Test name
Test status
Simulation time 45901015 ps
CPU time 0.67 seconds
Started Aug 06 08:06:27 PM PDT 24
Finished Aug 06 08:06:28 PM PDT 24
Peak memory 207456 kb
Host smart-46a7eace-ef11-40fa-b0ee-a533d7569e0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2940223882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2940223882
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.367964322
Short name T1208
Test name
Test status
Simulation time 11792885912 ps
CPU time 14.71 seconds
Started Aug 06 08:06:39 PM PDT 24
Finished Aug 06 08:06:54 PM PDT 24
Peak memory 207624 kb
Host smart-2404d9c2-3ca5-4a93-a0cb-0e77271c90d6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367964322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_ao
n_wake_disconnect.367964322
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2598124330
Short name T2581
Test name
Test status
Simulation time 16196633148 ps
CPU time 19.27 seconds
Started Aug 06 08:06:34 PM PDT 24
Finished Aug 06 08:06:54 PM PDT 24
Peak memory 215848 kb
Host smart-1aafb6c0-14d1-48eb-be46-79d51d0be679
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598124330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2598124330
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.158633173
Short name T736
Test name
Test status
Simulation time 26158902663 ps
CPU time 32.65 seconds
Started Aug 06 08:06:28 PM PDT 24
Finished Aug 06 08:07:01 PM PDT 24
Peak memory 215776 kb
Host smart-4de60b49-94d2-4326-9019-911645b1f4d3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158633173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_ao
n_wake_resume.158633173
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1697141699
Short name T2889
Test name
Test status
Simulation time 156144785 ps
CPU time 0.9 seconds
Started Aug 06 08:06:30 PM PDT 24
Finished Aug 06 08:06:31 PM PDT 24
Peak memory 207352 kb
Host smart-62587909-02aa-4670-8715-83f5623b2a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16971
41699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1697141699
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1831110023
Short name T1741
Test name
Test status
Simulation time 141950601 ps
CPU time 0.82 seconds
Started Aug 06 08:06:25 PM PDT 24
Finished Aug 06 08:06:26 PM PDT 24
Peak memory 207288 kb
Host smart-f0aa0651-40e1-492a-bc22-9db309424f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18311
10023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1831110023
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.2727017711
Short name T2301
Test name
Test status
Simulation time 321400810 ps
CPU time 1.3 seconds
Started Aug 06 08:06:33 PM PDT 24
Finished Aug 06 08:06:34 PM PDT 24
Peak memory 207324 kb
Host smart-e9f86e6f-6355-44d6-b889-8fbd6969e9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27270
17711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2727017711
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2171673353
Short name T2869
Test name
Test status
Simulation time 1170763142 ps
CPU time 3.05 seconds
Started Aug 06 08:06:34 PM PDT 24
Finished Aug 06 08:06:37 PM PDT 24
Peak memory 207592 kb
Host smart-63a94775-f293-44d2-ab48-f3da852901cf
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2171673353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2171673353
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.4275676464
Short name T2352
Test name
Test status
Simulation time 52731747059 ps
CPU time 87.33 seconds
Started Aug 06 08:06:23 PM PDT 24
Finished Aug 06 08:07:50 PM PDT 24
Peak memory 207596 kb
Host smart-74bbe1f8-39f6-41af-8cf8-1d6da746a325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42756
76464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.4275676464
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.1349931042
Short name T1940
Test name
Test status
Simulation time 2498802291 ps
CPU time 21.71 seconds
Started Aug 06 08:06:21 PM PDT 24
Finished Aug 06 08:06:42 PM PDT 24
Peak memory 207664 kb
Host smart-30a464a1-4077-4a7c-9f44-f5465ebf63d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349931042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.1349931042
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.4060568564
Short name T359
Test name
Test status
Simulation time 825553543 ps
CPU time 1.86 seconds
Started Aug 06 08:06:21 PM PDT 24
Finished Aug 06 08:06:23 PM PDT 24
Peak memory 207288 kb
Host smart-f5a8b455-21e9-4ffe-816d-8bb5137d87b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40605
68564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.4060568564
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3552724065
Short name T2763
Test name
Test status
Simulation time 183152952 ps
CPU time 0.86 seconds
Started Aug 06 08:06:32 PM PDT 24
Finished Aug 06 08:06:33 PM PDT 24
Peak memory 207348 kb
Host smart-07963d26-27fd-45d7-906e-028ece0bf7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35527
24065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3552724065
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.408625156
Short name T267
Test name
Test status
Simulation time 81874120 ps
CPU time 0.73 seconds
Started Aug 06 08:06:33 PM PDT 24
Finished Aug 06 08:06:34 PM PDT 24
Peak memory 207344 kb
Host smart-6070e808-0c72-4cfc-b2ac-76cdd0a60588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40862
5156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.408625156
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.627216813
Short name T1473
Test name
Test status
Simulation time 885720814 ps
CPU time 2.47 seconds
Started Aug 06 08:06:27 PM PDT 24
Finished Aug 06 08:06:30 PM PDT 24
Peak memory 207536 kb
Host smart-467ac87d-32d7-416e-ae71-e2130c48ffef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62721
6813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.627216813
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_types.1547618865
Short name T369
Test name
Test status
Simulation time 441119058 ps
CPU time 1.37 seconds
Started Aug 06 08:06:26 PM PDT 24
Finished Aug 06 08:06:27 PM PDT 24
Peak memory 207392 kb
Host smart-1f48baa9-0b88-4568-a973-c154deb10011
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1547618865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.1547618865
Directory /workspace/31.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1032080320
Short name T107
Test name
Test status
Simulation time 311413459 ps
CPU time 2.25 seconds
Started Aug 06 08:06:23 PM PDT 24
Finished Aug 06 08:06:26 PM PDT 24
Peak memory 207472 kb
Host smart-deb3b780-5df0-423f-9f71-127c63fcf537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10320
80320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1032080320
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2801586323
Short name T917
Test name
Test status
Simulation time 293120773 ps
CPU time 1.37 seconds
Started Aug 06 08:06:29 PM PDT 24
Finished Aug 06 08:06:31 PM PDT 24
Peak memory 215780 kb
Host smart-6a279afa-ee94-4e32-a3e5-f595446862ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2801586323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2801586323
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.218314624
Short name T2119
Test name
Test status
Simulation time 136744911 ps
CPU time 0.85 seconds
Started Aug 06 08:06:34 PM PDT 24
Finished Aug 06 08:06:35 PM PDT 24
Peak memory 207280 kb
Host smart-986bd598-9752-45d9-ae0d-a901b9696698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21831
4624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.218314624
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.13621284
Short name T1894
Test name
Test status
Simulation time 168199738 ps
CPU time 0.95 seconds
Started Aug 06 08:06:31 PM PDT 24
Finished Aug 06 08:06:32 PM PDT 24
Peak memory 207380 kb
Host smart-dac38a59-39c0-4cef-a65e-069d1f1a22ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13621
284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.13621284
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.267433193
Short name T2569
Test name
Test status
Simulation time 4771682146 ps
CPU time 137.25 seconds
Started Aug 06 08:06:32 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 217644 kb
Host smart-9b570c91-fdaf-40cd-8adf-8f0d3166a926
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=267433193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.267433193
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.2190105973
Short name T1737
Test name
Test status
Simulation time 12471892400 ps
CPU time 87.39 seconds
Started Aug 06 08:06:35 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207692 kb
Host smart-ed1e6de0-eb9e-4c37-90f7-b46d33ed430c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2190105973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.2190105973
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1824792733
Short name T1181
Test name
Test status
Simulation time 178579514 ps
CPU time 0.92 seconds
Started Aug 06 08:06:29 PM PDT 24
Finished Aug 06 08:06:30 PM PDT 24
Peak memory 207400 kb
Host smart-b008db8e-c1c8-47ab-b969-5e80bb71d698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18247
92733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1824792733
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1547702370
Short name T2677
Test name
Test status
Simulation time 8371879549 ps
CPU time 11.39 seconds
Started Aug 06 08:06:33 PM PDT 24
Finished Aug 06 08:06:45 PM PDT 24
Peak memory 215904 kb
Host smart-0585a379-9c87-483b-b73d-8f5846a5b553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15477
02370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1547702370
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2855048972
Short name T1753
Test name
Test status
Simulation time 5973856267 ps
CPU time 8.87 seconds
Started Aug 06 08:06:29 PM PDT 24
Finished Aug 06 08:06:38 PM PDT 24
Peak memory 215872 kb
Host smart-113ae85d-af1c-4f56-890e-3a50fe36840e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28550
48972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2855048972
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.3899116918
Short name T2601
Test name
Test status
Simulation time 4485096347 ps
CPU time 35.7 seconds
Started Aug 06 08:06:33 PM PDT 24
Finished Aug 06 08:07:09 PM PDT 24
Peak memory 218248 kb
Host smart-3522a3c9-0a47-4af1-b8de-8cb9d2d556bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38991
16918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.3899116918
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.4233297017
Short name T2086
Test name
Test status
Simulation time 3725647355 ps
CPU time 37.09 seconds
Started Aug 06 08:06:31 PM PDT 24
Finished Aug 06 08:07:08 PM PDT 24
Peak memory 217568 kb
Host smart-e918d7f0-fdd1-4ddc-8bec-777efedcd296
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4233297017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.4233297017
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.712813786
Short name T2085
Test name
Test status
Simulation time 240432260 ps
CPU time 1.1 seconds
Started Aug 06 08:06:28 PM PDT 24
Finished Aug 06 08:06:29 PM PDT 24
Peak memory 207300 kb
Host smart-08584abb-edce-4c0a-87ad-c7da8351313f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=712813786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.712813786
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3693699060
Short name T2054
Test name
Test status
Simulation time 191741786 ps
CPU time 0.94 seconds
Started Aug 06 08:06:26 PM PDT 24
Finished Aug 06 08:06:27 PM PDT 24
Peak memory 207376 kb
Host smart-9d5b4b17-525b-4416-a16c-1f07ff43d431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36936
99060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3693699060
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.215013909
Short name T1021
Test name
Test status
Simulation time 2650257097 ps
CPU time 19.16 seconds
Started Aug 06 08:06:32 PM PDT 24
Finished Aug 06 08:06:51 PM PDT 24
Peak memory 217588 kb
Host smart-5d80729f-de47-4014-b9bf-c2e682ba766e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=215013909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.215013909
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.2214356774
Short name T1185
Test name
Test status
Simulation time 170025402 ps
CPU time 0.83 seconds
Started Aug 06 08:06:37 PM PDT 24
Finished Aug 06 08:06:38 PM PDT 24
Peak memory 207336 kb
Host smart-0679c978-85ed-4cc1-85d3-8b6c34b2febf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2214356774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.2214356774
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2290883833
Short name T2774
Test name
Test status
Simulation time 154304663 ps
CPU time 0.82 seconds
Started Aug 06 08:06:34 PM PDT 24
Finished Aug 06 08:06:35 PM PDT 24
Peak memory 207292 kb
Host smart-9bee24e0-fe36-404f-a601-c2870c599d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22908
83833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2290883833
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1750812839
Short name T1751
Test name
Test status
Simulation time 206123255 ps
CPU time 0.97 seconds
Started Aug 06 08:06:30 PM PDT 24
Finished Aug 06 08:06:31 PM PDT 24
Peak memory 207324 kb
Host smart-38724dec-1f34-486b-b1cf-07cc01c472a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17508
12839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1750812839
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.1268558653
Short name T745
Test name
Test status
Simulation time 151777841 ps
CPU time 0.86 seconds
Started Aug 06 08:06:37 PM PDT 24
Finished Aug 06 08:06:38 PM PDT 24
Peak memory 207380 kb
Host smart-f979178b-8e7a-4349-be25-d4ed3fcd2d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12685
58653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.1268558653
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2580495666
Short name T1987
Test name
Test status
Simulation time 194347216 ps
CPU time 0.91 seconds
Started Aug 06 08:06:31 PM PDT 24
Finished Aug 06 08:06:32 PM PDT 24
Peak memory 207396 kb
Host smart-a5ba278d-f4a9-416c-99c4-45be600bc298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25804
95666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2580495666
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3319341846
Short name T1235
Test name
Test status
Simulation time 174238308 ps
CPU time 0.9 seconds
Started Aug 06 08:06:30 PM PDT 24
Finished Aug 06 08:06:31 PM PDT 24
Peak memory 207372 kb
Host smart-7aedc257-c338-40cd-95c2-7c01b139a2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33193
41846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3319341846
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1855438208
Short name T2379
Test name
Test status
Simulation time 167009330 ps
CPU time 0.85 seconds
Started Aug 06 08:06:22 PM PDT 24
Finished Aug 06 08:06:23 PM PDT 24
Peak memory 207408 kb
Host smart-8574ca6d-9ecd-43ef-a03f-950125c1816f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18554
38208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1855438208
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.4161103975
Short name T2141
Test name
Test status
Simulation time 191956457 ps
CPU time 0.94 seconds
Started Aug 06 08:06:24 PM PDT 24
Finished Aug 06 08:06:25 PM PDT 24
Peak memory 207388 kb
Host smart-27747d14-2ecd-4e83-916d-c0d37dfc5aff
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4161103975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.4161103975
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.635077054
Short name T1886
Test name
Test status
Simulation time 167851161 ps
CPU time 0.9 seconds
Started Aug 06 08:06:29 PM PDT 24
Finished Aug 06 08:06:30 PM PDT 24
Peak memory 207324 kb
Host smart-4bc1addf-a955-43c0-96fb-6b756bd7680c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63507
7054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.635077054
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1335246
Short name T1324
Test name
Test status
Simulation time 34500339 ps
CPU time 0.69 seconds
Started Aug 06 08:06:35 PM PDT 24
Finished Aug 06 08:06:36 PM PDT 24
Peak memory 207320 kb
Host smart-de7eb5e9-6cb0-4793-9769-5847bbb74d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13352
46 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1335246
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.587226862
Short name T1385
Test name
Test status
Simulation time 11395409245 ps
CPU time 29.81 seconds
Started Aug 06 08:06:32 PM PDT 24
Finished Aug 06 08:07:02 PM PDT 24
Peak memory 215940 kb
Host smart-58d1022f-a9c5-4b88-92c7-b2ec909e5e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58722
6862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.587226862
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3307457907
Short name T530
Test name
Test status
Simulation time 208266138 ps
CPU time 0.93 seconds
Started Aug 06 08:06:35 PM PDT 24
Finished Aug 06 08:06:36 PM PDT 24
Peak memory 207364 kb
Host smart-25d7d080-a8c6-4ee0-bc93-da123e40d18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33074
57907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3307457907
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2894315221
Short name T2341
Test name
Test status
Simulation time 158072583 ps
CPU time 0.88 seconds
Started Aug 06 08:06:35 PM PDT 24
Finished Aug 06 08:06:41 PM PDT 24
Peak memory 207384 kb
Host smart-2fc2f5bb-ab29-4afe-aa7c-f49468622ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28943
15221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2894315221
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2510085642
Short name T2751
Test name
Test status
Simulation time 210357353 ps
CPU time 0.93 seconds
Started Aug 06 08:06:31 PM PDT 24
Finished Aug 06 08:06:37 PM PDT 24
Peak memory 207380 kb
Host smart-590d4550-f77c-42ba-adb4-c1ea2041fd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25100
85642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2510085642
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.2582856952
Short name T970
Test name
Test status
Simulation time 164393736 ps
CPU time 0.87 seconds
Started Aug 06 08:06:32 PM PDT 24
Finished Aug 06 08:06:33 PM PDT 24
Peak memory 207400 kb
Host smart-d5c72d3b-7ea6-4f22-9259-205178842bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25828
56952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.2582856952
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2431309364
Short name T1498
Test name
Test status
Simulation time 195353043 ps
CPU time 0.92 seconds
Started Aug 06 08:06:34 PM PDT 24
Finished Aug 06 08:06:35 PM PDT 24
Peak memory 207416 kb
Host smart-644ea22a-b661-407a-aff9-e71d1abed6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24313
09364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2431309364
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.3770847099
Short name T175
Test name
Test status
Simulation time 151542356 ps
CPU time 0.84 seconds
Started Aug 06 08:06:29 PM PDT 24
Finished Aug 06 08:06:30 PM PDT 24
Peak memory 207260 kb
Host smart-5018057d-5feb-42b5-959b-311badf3df77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37708
47099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.3770847099
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3558682132
Short name T1647
Test name
Test status
Simulation time 149390546 ps
CPU time 0.82 seconds
Started Aug 06 08:06:27 PM PDT 24
Finished Aug 06 08:06:28 PM PDT 24
Peak memory 207364 kb
Host smart-06962c3a-2fd7-4a7a-bbdd-b0144f14ea60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35586
82132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3558682132
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1318062107
Short name T701
Test name
Test status
Simulation time 221967433 ps
CPU time 1.04 seconds
Started Aug 06 08:06:32 PM PDT 24
Finished Aug 06 08:06:33 PM PDT 24
Peak memory 207292 kb
Host smart-28af6739-a63a-4a52-b870-de436c1b4f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13180
62107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1318062107
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1832098092
Short name T1344
Test name
Test status
Simulation time 2874792385 ps
CPU time 21.75 seconds
Started Aug 06 08:06:39 PM PDT 24
Finished Aug 06 08:07:01 PM PDT 24
Peak memory 215868 kb
Host smart-d11c6c7d-efec-4087-9a34-53e94943e00b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1832098092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1832098092
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3533892368
Short name T1659
Test name
Test status
Simulation time 195792379 ps
CPU time 0.95 seconds
Started Aug 06 08:06:25 PM PDT 24
Finished Aug 06 08:06:26 PM PDT 24
Peak memory 207448 kb
Host smart-68657585-09ec-42da-bdde-315dde4459e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35338
92368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3533892368
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.783023087
Short name T3098
Test name
Test status
Simulation time 202167333 ps
CPU time 0.96 seconds
Started Aug 06 08:06:30 PM PDT 24
Finished Aug 06 08:06:31 PM PDT 24
Peak memory 207396 kb
Host smart-d69414ac-2a92-45bb-aee6-f83b02bac1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78302
3087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.783023087
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2590746745
Short name T2409
Test name
Test status
Simulation time 267620853 ps
CPU time 1.11 seconds
Started Aug 06 08:06:30 PM PDT 24
Finished Aug 06 08:06:31 PM PDT 24
Peak memory 207368 kb
Host smart-b745ee90-7e7e-40ac-abeb-46155602fd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25907
46745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2590746745
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1846105604
Short name T1501
Test name
Test status
Simulation time 2153314689 ps
CPU time 62.22 seconds
Started Aug 06 08:06:35 PM PDT 24
Finished Aug 06 08:07:38 PM PDT 24
Peak memory 215912 kb
Host smart-9554fc1a-4a68-4934-a034-39196588d04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18461
05604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1846105604
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.969093665
Short name T2933
Test name
Test status
Simulation time 1599323920 ps
CPU time 9.88 seconds
Started Aug 06 08:06:25 PM PDT 24
Finished Aug 06 08:06:35 PM PDT 24
Peak memory 207508 kb
Host smart-c5f0c939-21aa-4f39-aaa7-e7c31dc3a364
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969093665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_host
_handshake.969093665
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.2702346267
Short name T2162
Test name
Test status
Simulation time 44834648 ps
CPU time 0.67 seconds
Started Aug 06 08:06:52 PM PDT 24
Finished Aug 06 08:06:53 PM PDT 24
Peak memory 207412 kb
Host smart-15e00fd8-817f-41a8-8703-9fe5b9be0053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2702346267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.2702346267
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3125730039
Short name T3065
Test name
Test status
Simulation time 7053188239 ps
CPU time 9.08 seconds
Started Aug 06 08:06:30 PM PDT 24
Finished Aug 06 08:06:39 PM PDT 24
Peak memory 215852 kb
Host smart-c0a4c53b-80bb-413e-84c5-d5c6c64766c9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125730039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.3125730039
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3351675855
Short name T1572
Test name
Test status
Simulation time 21442557965 ps
CPU time 24.44 seconds
Started Aug 06 08:06:27 PM PDT 24
Finished Aug 06 08:06:51 PM PDT 24
Peak memory 207608 kb
Host smart-d796ca0b-d553-4379-bea2-3c311db652aa
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351675855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3351675855
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.1183586744
Short name T756
Test name
Test status
Simulation time 24092742152 ps
CPU time 29.55 seconds
Started Aug 06 08:06:29 PM PDT 24
Finished Aug 06 08:06:59 PM PDT 24
Peak memory 215804 kb
Host smart-fcdc7e17-0ec4-4c81-bd53-40f9cd46b9a0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183586744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.1183586744
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3309531340
Short name T2531
Test name
Test status
Simulation time 145772823 ps
CPU time 0.85 seconds
Started Aug 06 08:07:00 PM PDT 24
Finished Aug 06 08:07:01 PM PDT 24
Peak memory 207300 kb
Host smart-c2941b4a-06f2-4ff8-8f75-ed6da35438ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33095
31340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3309531340
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.1058333296
Short name T2594
Test name
Test status
Simulation time 162304824 ps
CPU time 0.85 seconds
Started Aug 06 08:06:40 PM PDT 24
Finished Aug 06 08:06:42 PM PDT 24
Peak memory 207320 kb
Host smart-5ab3b3b9-d844-485c-888a-08127b4dc9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10583
33296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.1058333296
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1181322123
Short name T2000
Test name
Test status
Simulation time 499982620 ps
CPU time 1.55 seconds
Started Aug 06 08:06:42 PM PDT 24
Finished Aug 06 08:06:44 PM PDT 24
Peak memory 207424 kb
Host smart-afcd42fd-8b75-4e1f-9475-0facd925924b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11813
22123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1181322123
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.518440139
Short name T1854
Test name
Test status
Simulation time 647059210 ps
CPU time 1.89 seconds
Started Aug 06 08:06:41 PM PDT 24
Finished Aug 06 08:06:43 PM PDT 24
Peak memory 207368 kb
Host smart-c43f8c0e-d583-4a8f-9d93-c25c30e0ac3c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=518440139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.518440139
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.3201733201
Short name T204
Test name
Test status
Simulation time 24430530099 ps
CPU time 44.05 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207668 kb
Host smart-b46d4b5c-5811-41dc-b092-95c47d9656e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32017
33201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3201733201
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.3420507089
Short name T1298
Test name
Test status
Simulation time 1076890948 ps
CPU time 9.05 seconds
Started Aug 06 08:06:51 PM PDT 24
Finished Aug 06 08:07:00 PM PDT 24
Peak memory 207580 kb
Host smart-79d9f2cd-8a79-47b6-8b0c-13f5052205ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420507089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.3420507089
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.1939108474
Short name T2160
Test name
Test status
Simulation time 657146224 ps
CPU time 1.62 seconds
Started Aug 06 08:06:56 PM PDT 24
Finished Aug 06 08:06:58 PM PDT 24
Peak memory 207288 kb
Host smart-8cd88413-6f2d-48c7-8d33-2a591c493ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19391
08474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.1939108474
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3483873176
Short name T1865
Test name
Test status
Simulation time 180198333 ps
CPU time 0.84 seconds
Started Aug 06 08:06:39 PM PDT 24
Finished Aug 06 08:06:41 PM PDT 24
Peak memory 207348 kb
Host smart-cb80e044-be2b-4cb5-bda7-44a23a57303e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34838
73176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3483873176
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.531261705
Short name T2844
Test name
Test status
Simulation time 64651463 ps
CPU time 0.7 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:06:46 PM PDT 24
Peak memory 207340 kb
Host smart-c876c4fe-fbe5-44e7-a91b-5662932adba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53126
1705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.531261705
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1793342481
Short name T1844
Test name
Test status
Simulation time 807982821 ps
CPU time 2.41 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:06:57 PM PDT 24
Peak memory 207504 kb
Host smart-bf0ab022-d167-4a29-b20f-62110e82199e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17933
42481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1793342481
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_types.3544376891
Short name T367
Test name
Test status
Simulation time 860333853 ps
CPU time 1.98 seconds
Started Aug 06 08:06:41 PM PDT 24
Finished Aug 06 08:06:43 PM PDT 24
Peak memory 207328 kb
Host smart-5a43869b-7a61-4fbe-b9bd-da961256e5bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3544376891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.3544376891
Directory /workspace/32.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.217090424
Short name T2016
Test name
Test status
Simulation time 184642367 ps
CPU time 1.36 seconds
Started Aug 06 08:06:59 PM PDT 24
Finished Aug 06 08:07:00 PM PDT 24
Peak memory 207640 kb
Host smart-f69442a5-d93f-405c-b7aa-a4b349daae21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21709
0424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.217090424
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.999166727
Short name T499
Test name
Test status
Simulation time 231776161 ps
CPU time 1.16 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:06:46 PM PDT 24
Peak memory 215740 kb
Host smart-b07ec603-38af-4851-b357-f58d33e38d80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=999166727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.999166727
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1593767063
Short name T546
Test name
Test status
Simulation time 143935747 ps
CPU time 0.79 seconds
Started Aug 06 08:06:43 PM PDT 24
Finished Aug 06 08:06:44 PM PDT 24
Peak memory 207336 kb
Host smart-4a4a88be-ca4f-463e-aa53-b929ad664092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
67063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1593767063
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1486732783
Short name T746
Test name
Test status
Simulation time 228080487 ps
CPU time 1 seconds
Started Aug 06 08:06:40 PM PDT 24
Finished Aug 06 08:06:42 PM PDT 24
Peak memory 207448 kb
Host smart-68c807d3-8b77-4679-9c4d-3495aa449061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14867
32783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1486732783
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.242764373
Short name T732
Test name
Test status
Simulation time 3587294644 ps
CPU time 101.51 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:08:26 PM PDT 24
Peak memory 218404 kb
Host smart-f346ecde-be2a-4240-8c75-d39c9dfefbab
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=242764373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.242764373
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.709044101
Short name T939
Test name
Test status
Simulation time 7901311021 ps
CPU time 56.81 seconds
Started Aug 06 08:06:44 PM PDT 24
Finished Aug 06 08:07:41 PM PDT 24
Peak memory 207644 kb
Host smart-d15719e8-7a29-44d8-a618-79d6c347a6e1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=709044101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.709044101
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1860678573
Short name T624
Test name
Test status
Simulation time 174537630 ps
CPU time 0.88 seconds
Started Aug 06 08:06:41 PM PDT 24
Finished Aug 06 08:06:42 PM PDT 24
Peak memory 207196 kb
Host smart-51079d48-497f-4539-baac-09e62d75857e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18606
78573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1860678573
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.3449416143
Short name T720
Test name
Test status
Simulation time 31613016495 ps
CPU time 44.95 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:07:30 PM PDT 24
Peak memory 207632 kb
Host smart-cd90060d-e8ad-4124-a632-d4e8981e3c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34494
16143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3449416143
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3579532851
Short name T2577
Test name
Test status
Simulation time 10086433151 ps
CPU time 12.4 seconds
Started Aug 06 08:06:44 PM PDT 24
Finished Aug 06 08:06:56 PM PDT 24
Peak memory 207632 kb
Host smart-96634029-192d-4df7-9bf2-f4fcaf6de56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35795
32851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3579532851
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.1274592155
Short name T1135
Test name
Test status
Simulation time 4481689387 ps
CPU time 45.65 seconds
Started Aug 06 08:06:49 PM PDT 24
Finished Aug 06 08:07:35 PM PDT 24
Peak memory 218496 kb
Host smart-8f33182f-0a32-46cf-b9eb-8d5c44a5ec49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12745
92155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1274592155
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.1161842144
Short name T3023
Test name
Test status
Simulation time 2421881750 ps
CPU time 24.84 seconds
Started Aug 06 08:06:52 PM PDT 24
Finished Aug 06 08:07:17 PM PDT 24
Peak memory 217292 kb
Host smart-ce37c772-74ba-41c1-8bd7-7ad6546a79b4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1161842144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.1161842144
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3059275862
Short name T2048
Test name
Test status
Simulation time 245903648 ps
CPU time 1.01 seconds
Started Aug 06 08:06:48 PM PDT 24
Finished Aug 06 08:06:49 PM PDT 24
Peak memory 207304 kb
Host smart-857d6ff3-3ca2-445b-ad17-8e24c94b6251
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3059275862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3059275862
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3271093110
Short name T1538
Test name
Test status
Simulation time 191867862 ps
CPU time 0.95 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:06:46 PM PDT 24
Peak memory 207360 kb
Host smart-3dd935d9-feb4-4f40-bcdf-4a4de8cb499e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32710
93110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3271093110
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.2421034027
Short name T2043
Test name
Test status
Simulation time 3820052969 ps
CPU time 109.53 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:08:35 PM PDT 24
Peak memory 215864 kb
Host smart-9fde14a6-e536-4edd-86e5-2b0311af0fa2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2421034027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.2421034027
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.913545139
Short name T1064
Test name
Test status
Simulation time 170605492 ps
CPU time 0.83 seconds
Started Aug 06 08:06:44 PM PDT 24
Finished Aug 06 08:06:46 PM PDT 24
Peak memory 207332 kb
Host smart-3ef4e526-6bc6-4d66-bb4a-bc80ed07f70b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=913545139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.913545139
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1673104798
Short name T1995
Test name
Test status
Simulation time 144034877 ps
CPU time 0.84 seconds
Started Aug 06 08:06:48 PM PDT 24
Finished Aug 06 08:06:49 PM PDT 24
Peak memory 207328 kb
Host smart-b9ee62fa-28d5-424c-a212-387bde7ed94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16731
04798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1673104798
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3467861857
Short name T167
Test name
Test status
Simulation time 206760655 ps
CPU time 0.91 seconds
Started Aug 06 08:06:44 PM PDT 24
Finished Aug 06 08:06:45 PM PDT 24
Peak memory 207308 kb
Host smart-6451f940-3ff3-4650-9188-dc62ea079600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34678
61857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3467861857
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.530301564
Short name T592
Test name
Test status
Simulation time 187437029 ps
CPU time 0.93 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:06:46 PM PDT 24
Peak memory 207292 kb
Host smart-861f1bc1-e577-4c61-bfde-cc1c1414ecc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53030
1564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.530301564
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1499903027
Short name T669
Test name
Test status
Simulation time 212026047 ps
CPU time 0.94 seconds
Started Aug 06 08:06:44 PM PDT 24
Finished Aug 06 08:06:45 PM PDT 24
Peak memory 207324 kb
Host smart-acee7b03-4b11-414b-be9f-f6e8b50eda18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14999
03027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1499903027
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1782070219
Short name T1017
Test name
Test status
Simulation time 183267013 ps
CPU time 0.96 seconds
Started Aug 06 08:06:53 PM PDT 24
Finished Aug 06 08:06:55 PM PDT 24
Peak memory 207356 kb
Host smart-31e88628-80a6-4d60-9b74-cf639a1d33e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17820
70219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1782070219
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.208542104
Short name T188
Test name
Test status
Simulation time 151442790 ps
CPU time 0.87 seconds
Started Aug 06 08:06:57 PM PDT 24
Finished Aug 06 08:06:58 PM PDT 24
Peak memory 207388 kb
Host smart-08792398-b1de-4038-981c-2ce4b626dc98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20854
2104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.208542104
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.193733558
Short name T2403
Test name
Test status
Simulation time 223887480 ps
CPU time 0.95 seconds
Started Aug 06 08:06:52 PM PDT 24
Finished Aug 06 08:06:53 PM PDT 24
Peak memory 207388 kb
Host smart-581f0c74-1bfc-43b1-9fd3-38489ef18549
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=193733558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.193733558
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3291447031
Short name T1008
Test name
Test status
Simulation time 145836561 ps
CPU time 0.83 seconds
Started Aug 06 08:06:58 PM PDT 24
Finished Aug 06 08:06:59 PM PDT 24
Peak memory 207352 kb
Host smart-5d2ab870-f110-447d-b500-703a781075d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32914
47031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3291447031
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2711006228
Short name T2684
Test name
Test status
Simulation time 59063133 ps
CPU time 0.71 seconds
Started Aug 06 08:07:03 PM PDT 24
Finished Aug 06 08:07:04 PM PDT 24
Peak memory 207336 kb
Host smart-11cbc94c-f589-44af-b47d-d569d67c6b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27110
06228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2711006228
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2017593474
Short name T1673
Test name
Test status
Simulation time 21134432680 ps
CPU time 54.32 seconds
Started Aug 06 08:06:46 PM PDT 24
Finished Aug 06 08:07:40 PM PDT 24
Peak memory 216068 kb
Host smart-b3eca6d9-fb1b-45ac-a43b-3ea4fb2ae6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20175
93474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2017593474
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.437651991
Short name T2313
Test name
Test status
Simulation time 202016848 ps
CPU time 0.94 seconds
Started Aug 06 08:07:05 PM PDT 24
Finished Aug 06 08:07:06 PM PDT 24
Peak memory 207372 kb
Host smart-9702348d-cb01-4118-ac30-c716ba8fab8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43765
1991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.437651991
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2001135096
Short name T2372
Test name
Test status
Simulation time 214877917 ps
CPU time 1.09 seconds
Started Aug 06 08:06:46 PM PDT 24
Finished Aug 06 08:06:48 PM PDT 24
Peak memory 207596 kb
Host smart-885a7273-eff4-4e02-8dbb-e7a857905f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20011
35096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2001135096
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.3781689992
Short name T2063
Test name
Test status
Simulation time 198218526 ps
CPU time 0.9 seconds
Started Aug 06 08:06:56 PM PDT 24
Finished Aug 06 08:06:57 PM PDT 24
Peak memory 207380 kb
Host smart-e60327ff-d353-4151-80a5-c8638243d0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37816
89992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3781689992
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1928659059
Short name T1733
Test name
Test status
Simulation time 163275640 ps
CPU time 0.81 seconds
Started Aug 06 08:06:51 PM PDT 24
Finished Aug 06 08:06:52 PM PDT 24
Peak memory 207320 kb
Host smart-278ebdf8-4a3e-40cb-9443-578246073b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19286
59059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1928659059
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1601492272
Short name T1723
Test name
Test status
Simulation time 157021093 ps
CPU time 0.83 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:06:46 PM PDT 24
Peak memory 207320 kb
Host smart-684610f9-eb5e-4e87-91c9-f89c3e500f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16014
92272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1601492272
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_rx_full.61491066
Short name T1762
Test name
Test status
Simulation time 247500871 ps
CPU time 1.13 seconds
Started Aug 06 08:06:42 PM PDT 24
Finished Aug 06 08:06:44 PM PDT 24
Peak memory 207368 kb
Host smart-c8784dc2-80d0-4b44-a85c-1424a5c159d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61491
066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.61491066
Directory /workspace/32.usbdev_rx_full/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2583416917
Short name T95
Test name
Test status
Simulation time 151091050 ps
CPU time 0.88 seconds
Started Aug 06 08:06:50 PM PDT 24
Finished Aug 06 08:06:51 PM PDT 24
Peak memory 207340 kb
Host smart-7806c66f-0f03-43ba-b66b-338f6bcafc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25834
16917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2583416917
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3744634185
Short name T1898
Test name
Test status
Simulation time 174265697 ps
CPU time 0.87 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:06:55 PM PDT 24
Peak memory 207396 kb
Host smart-86551798-ff3b-418f-a918-b9064929a98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37446
34185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3744634185
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1546585340
Short name T2295
Test name
Test status
Simulation time 216447450 ps
CPU time 1.04 seconds
Started Aug 06 08:06:43 PM PDT 24
Finished Aug 06 08:06:44 PM PDT 24
Peak memory 207428 kb
Host smart-74e7274f-fe42-4210-b2ca-14f13ab95480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15465
85340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1546585340
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3402925663
Short name T1367
Test name
Test status
Simulation time 2707030643 ps
CPU time 22.16 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:07:16 PM PDT 24
Peak memory 207688 kb
Host smart-00aaac8e-d54f-42ef-90a7-ba845d4f93a8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3402925663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3402925663
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1035121570
Short name T1503
Test name
Test status
Simulation time 164168340 ps
CPU time 0.87 seconds
Started Aug 06 08:06:58 PM PDT 24
Finished Aug 06 08:06:59 PM PDT 24
Peak memory 207368 kb
Host smart-f9826d2b-b7fc-4e36-a9b8-ef4b1a96f4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10351
21570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1035121570
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.564865566
Short name T2303
Test name
Test status
Simulation time 170660361 ps
CPU time 0.84 seconds
Started Aug 06 08:06:51 PM PDT 24
Finished Aug 06 08:06:52 PM PDT 24
Peak memory 207288 kb
Host smart-93d2c60c-a3e0-4cd6-b75b-862931bbaeab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56486
5566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.564865566
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.2998054624
Short name T2001
Test name
Test status
Simulation time 599190133 ps
CPU time 1.68 seconds
Started Aug 06 08:06:44 PM PDT 24
Finished Aug 06 08:06:45 PM PDT 24
Peak memory 207324 kb
Host smart-56d202a0-3538-4999-8cf8-f1e53a452de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29980
54624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.2998054624
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3866221105
Short name T3013
Test name
Test status
Simulation time 3809186399 ps
CPU time 28.03 seconds
Started Aug 06 08:06:43 PM PDT 24
Finished Aug 06 08:07:11 PM PDT 24
Peak memory 215756 kb
Host smart-0a67fb1f-0858-406e-bbbc-8fa1834af2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38662
21105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3866221105
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.2450718151
Short name T1772
Test name
Test status
Simulation time 884896284 ps
CPU time 18.12 seconds
Started Aug 06 08:06:40 PM PDT 24
Finished Aug 06 08:06:58 PM PDT 24
Peak memory 207480 kb
Host smart-90356e60-4463-4788-8e8e-f17782560cb9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450718151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.2450718151
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.245356108
Short name T3105
Test name
Test status
Simulation time 44254404 ps
CPU time 0.69 seconds
Started Aug 06 08:06:55 PM PDT 24
Finished Aug 06 08:06:56 PM PDT 24
Peak memory 207444 kb
Host smart-c50d535c-0fd9-4c1c-9789-342db524b9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=245356108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.245356108
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.647303779
Short name T1632
Test name
Test status
Simulation time 4395672021 ps
CPU time 6.34 seconds
Started Aug 06 08:06:52 PM PDT 24
Finished Aug 06 08:06:58 PM PDT 24
Peak memory 215764 kb
Host smart-d5289e5f-97b3-40d9-af77-67d318250d5e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647303779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_ao
n_wake_disconnect.647303779
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.2699534329
Short name T2779
Test name
Test status
Simulation time 21278085272 ps
CPU time 30.39 seconds
Started Aug 06 08:06:40 PM PDT 24
Finished Aug 06 08:07:11 PM PDT 24
Peak memory 207640 kb
Host smart-14b70ac4-f283-47c7-9e34-3a6919488aa2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699534329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.2699534329
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1224872593
Short name T2509
Test name
Test status
Simulation time 29917973341 ps
CPU time 34.65 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:07:28 PM PDT 24
Peak memory 207620 kb
Host smart-ddcc9fe7-c997-4f08-8cab-8876da10ee93
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224872593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.1224872593
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3079560405
Short name T1254
Test name
Test status
Simulation time 151682855 ps
CPU time 0.88 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:06:55 PM PDT 24
Peak memory 207348 kb
Host smart-c623308e-4dc7-4a63-8dcb-a384f8f50d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30795
60405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3079560405
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2092389762
Short name T1276
Test name
Test status
Simulation time 137750764 ps
CPU time 0.82 seconds
Started Aug 06 08:06:39 PM PDT 24
Finished Aug 06 08:06:40 PM PDT 24
Peak memory 207364 kb
Host smart-3ea476f9-f6ec-4b53-80d2-795faf2890d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20923
89762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2092389762
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.1856267328
Short name T1992
Test name
Test status
Simulation time 513623929 ps
CPU time 1.68 seconds
Started Aug 06 08:06:41 PM PDT 24
Finished Aug 06 08:06:43 PM PDT 24
Peak memory 207452 kb
Host smart-2f5c112c-e3fc-41b4-a105-ba57f0f5b423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18562
67328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.1856267328
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1910655893
Short name T1698
Test name
Test status
Simulation time 865446901 ps
CPU time 2.76 seconds
Started Aug 06 08:06:56 PM PDT 24
Finished Aug 06 08:06:59 PM PDT 24
Peak memory 207588 kb
Host smart-a3b9c0b2-53aa-4abb-a9e7-46c3076e0566
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1910655893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1910655893
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.1053938361
Short name T91
Test name
Test status
Simulation time 50965355051 ps
CPU time 77.81 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:08:12 PM PDT 24
Peak memory 207632 kb
Host smart-5cd063c0-0d6a-4b7d-86aa-cc63e7834edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10539
38361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1053938361
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.1561076787
Short name T2753
Test name
Test status
Simulation time 3390673591 ps
CPU time 27.48 seconds
Started Aug 06 08:06:49 PM PDT 24
Finished Aug 06 08:07:17 PM PDT 24
Peak memory 207656 kb
Host smart-5e02db70-2e43-4601-83f1-b1b785685cb4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561076787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.1561076787
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.4041760946
Short name T1124
Test name
Test status
Simulation time 659449026 ps
CPU time 1.73 seconds
Started Aug 06 08:06:49 PM PDT 24
Finished Aug 06 08:06:51 PM PDT 24
Peak memory 207316 kb
Host smart-c975995b-e547-4589-b39f-c9a5902f8f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40417
60946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.4041760946
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.673783471
Short name T2702
Test name
Test status
Simulation time 140710957 ps
CPU time 0.83 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:06:46 PM PDT 24
Peak memory 207324 kb
Host smart-a2d6beb5-b23d-497d-a0bb-709d0fbfc3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67378
3471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.673783471
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.155525018
Short name T705
Test name
Test status
Simulation time 69035654 ps
CPU time 0.76 seconds
Started Aug 06 08:07:01 PM PDT 24
Finished Aug 06 08:07:02 PM PDT 24
Peak memory 207336 kb
Host smart-133b6115-4ea1-42fd-b91c-ae4a3cf08357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15552
5018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.155525018
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.4267005159
Short name T660
Test name
Test status
Simulation time 855935945 ps
CPU time 2.24 seconds
Started Aug 06 08:06:53 PM PDT 24
Finished Aug 06 08:06:56 PM PDT 24
Peak memory 207472 kb
Host smart-5147f9d8-1f55-4548-85d7-50bb6675ef9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42670
05159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.4267005159
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3880716661
Short name T212
Test name
Test status
Simulation time 172611729 ps
CPU time 1.94 seconds
Started Aug 06 08:06:53 PM PDT 24
Finished Aug 06 08:06:55 PM PDT 24
Peak memory 207504 kb
Host smart-dc713048-caff-4964-a1b4-37405d02fd6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38807
16661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3880716661
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3342404047
Short name T3087
Test name
Test status
Simulation time 222091881 ps
CPU time 1.12 seconds
Started Aug 06 08:06:43 PM PDT 24
Finished Aug 06 08:06:44 PM PDT 24
Peak memory 207536 kb
Host smart-863de77e-c99c-4835-96fb-9ff6b4521a9e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3342404047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3342404047
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1122052638
Short name T2098
Test name
Test status
Simulation time 172113361 ps
CPU time 0.89 seconds
Started Aug 06 08:06:41 PM PDT 24
Finished Aug 06 08:06:42 PM PDT 24
Peak memory 207332 kb
Host smart-f21741f0-a111-48c2-9de9-6a1d1ea0ca16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11220
52638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1122052638
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2974372632
Short name T2953
Test name
Test status
Simulation time 206688108 ps
CPU time 0.94 seconds
Started Aug 06 08:06:46 PM PDT 24
Finished Aug 06 08:06:47 PM PDT 24
Peak memory 207372 kb
Host smart-01f68134-0e89-412c-883b-6cc74a053f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29743
72632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2974372632
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.2314119819
Short name T2402
Test name
Test status
Simulation time 2568599211 ps
CPU time 71.78 seconds
Started Aug 06 08:06:44 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 224012 kb
Host smart-e63c4792-cec6-4008-b9a5-96dfd8ce8a3a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2314119819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.2314119819
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2614695751
Short name T1570
Test name
Test status
Simulation time 9109482320 ps
CPU time 66.45 seconds
Started Aug 06 08:06:42 PM PDT 24
Finished Aug 06 08:07:49 PM PDT 24
Peak memory 207616 kb
Host smart-f761085e-4d96-42eb-9701-ee38528e9c04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2614695751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2614695751
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3236993143
Short name T3110
Test name
Test status
Simulation time 198312418 ps
CPU time 0.91 seconds
Started Aug 06 08:06:42 PM PDT 24
Finished Aug 06 08:06:43 PM PDT 24
Peak memory 207344 kb
Host smart-9d55507b-24e7-4fe7-9d4c-516e3c96dad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32369
93143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3236993143
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.883793259
Short name T857
Test name
Test status
Simulation time 11242625089 ps
CPU time 14.89 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:07:09 PM PDT 24
Peak memory 207616 kb
Host smart-b0c6b762-de07-44d4-980e-1be598e2f0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88379
3259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.883793259
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1774509070
Short name T912
Test name
Test status
Simulation time 8589049224 ps
CPU time 10.37 seconds
Started Aug 06 08:06:44 PM PDT 24
Finished Aug 06 08:06:55 PM PDT 24
Peak memory 207588 kb
Host smart-5ef11808-2a29-417f-a9f0-59101a99e388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17745
09070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1774509070
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.2348120746
Short name T1179
Test name
Test status
Simulation time 4403790628 ps
CPU time 31.51 seconds
Started Aug 06 08:07:03 PM PDT 24
Finished Aug 06 08:07:35 PM PDT 24
Peak memory 217576 kb
Host smart-e2f6450d-57e4-4adf-a927-981d59747388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23481
20746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.2348120746
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.3009029556
Short name T1217
Test name
Test status
Simulation time 3313101659 ps
CPU time 88.53 seconds
Started Aug 06 08:06:44 PM PDT 24
Finished Aug 06 08:08:13 PM PDT 24
Peak memory 215820 kb
Host smart-34c0aeb7-2d38-48f3-813e-720503dad5a8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3009029556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.3009029556
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1076332092
Short name T2452
Test name
Test status
Simulation time 237692205 ps
CPU time 0.99 seconds
Started Aug 06 08:06:44 PM PDT 24
Finished Aug 06 08:06:45 PM PDT 24
Peak memory 207312 kb
Host smart-5cc11cd0-05fb-44b4-afe9-62d741dc662d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1076332092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1076332092
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1628914353
Short name T1097
Test name
Test status
Simulation time 197416712 ps
CPU time 0.89 seconds
Started Aug 06 08:06:46 PM PDT 24
Finished Aug 06 08:06:47 PM PDT 24
Peak memory 207380 kb
Host smart-5b11366d-25b0-4806-92dc-51d4d097f3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16289
14353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1628914353
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.3213266156
Short name T1736
Test name
Test status
Simulation time 2202348318 ps
CPU time 20.55 seconds
Started Aug 06 08:06:46 PM PDT 24
Finished Aug 06 08:07:07 PM PDT 24
Peak memory 217296 kb
Host smart-5883f415-88a8-4769-ba73-7bffe5a55d59
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3213266156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3213266156
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3578605982
Short name T1602
Test name
Test status
Simulation time 153753914 ps
CPU time 0.8 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:06:54 PM PDT 24
Peak memory 207336 kb
Host smart-e3db677b-c9ae-4a64-9894-711cb3ddac5c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3578605982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3578605982
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.4143205678
Short name T1693
Test name
Test status
Simulation time 174897143 ps
CPU time 0.82 seconds
Started Aug 06 08:06:46 PM PDT 24
Finished Aug 06 08:06:47 PM PDT 24
Peak memory 207380 kb
Host smart-b55c125f-423c-4e6a-8578-e4fef4a8b2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41432
05678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.4143205678
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2436287871
Short name T2203
Test name
Test status
Simulation time 208540477 ps
CPU time 0.98 seconds
Started Aug 06 08:06:53 PM PDT 24
Finished Aug 06 08:06:54 PM PDT 24
Peak memory 207372 kb
Host smart-d95f3159-9ecb-4ada-9b58-f34f478b1b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24362
87871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2436287871
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.1559077609
Short name T948
Test name
Test status
Simulation time 171024697 ps
CPU time 0.88 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:06:46 PM PDT 24
Peak memory 207288 kb
Host smart-c98dd8b3-55db-4c3f-b5b3-a18879237b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15590
77609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.1559077609
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2923522927
Short name T932
Test name
Test status
Simulation time 222844625 ps
CPU time 0.94 seconds
Started Aug 06 08:06:45 PM PDT 24
Finished Aug 06 08:06:47 PM PDT 24
Peak memory 207596 kb
Host smart-b46cde7e-43bf-4524-919a-3c8991ca39db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29235
22927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2923522927
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.101449246
Short name T3107
Test name
Test status
Simulation time 155291909 ps
CPU time 0.87 seconds
Started Aug 06 08:06:46 PM PDT 24
Finished Aug 06 08:06:47 PM PDT 24
Peak memory 207604 kb
Host smart-c2cf19c3-ce8c-49f6-81de-1739d9589c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10144
9246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.101449246
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1262753368
Short name T2598
Test name
Test status
Simulation time 170217754 ps
CPU time 0.87 seconds
Started Aug 06 08:06:52 PM PDT 24
Finished Aug 06 08:06:53 PM PDT 24
Peak memory 207308 kb
Host smart-5596ef92-64cc-4a36-88e3-ce9bb982e126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12627
53368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1262753368
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.1441813204
Short name T2947
Test name
Test status
Simulation time 226238667 ps
CPU time 0.96 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:06:55 PM PDT 24
Peak memory 207372 kb
Host smart-a3e59338-9c2b-4adc-a9a5-570f4aab8a15
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1441813204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.1441813204
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3888925235
Short name T985
Test name
Test status
Simulation time 146576192 ps
CPU time 0.83 seconds
Started Aug 06 08:06:52 PM PDT 24
Finished Aug 06 08:06:53 PM PDT 24
Peak memory 207368 kb
Host smart-e45c7c0c-e51c-4912-8b94-ff2018ce6259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38889
25235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3888925235
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1092481705
Short name T36
Test name
Test status
Simulation time 37698860 ps
CPU time 0.68 seconds
Started Aug 06 08:06:53 PM PDT 24
Finished Aug 06 08:06:54 PM PDT 24
Peak memory 207560 kb
Host smart-57668141-b39c-471d-bbc2-3a96fcce106a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10924
81705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1092481705
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.441526357
Short name T2595
Test name
Test status
Simulation time 12103797088 ps
CPU time 31.12 seconds
Started Aug 06 08:06:51 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 215848 kb
Host smart-7801d363-df21-4cc5-a776-fac24771df6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44152
6357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.441526357
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1771449565
Short name T1780
Test name
Test status
Simulation time 170946320 ps
CPU time 0.91 seconds
Started Aug 06 08:06:56 PM PDT 24
Finished Aug 06 08:06:57 PM PDT 24
Peak memory 207352 kb
Host smart-f24db97b-461c-4e4c-a7ab-c2de7686f97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17714
49565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1771449565
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2745616447
Short name T1180
Test name
Test status
Simulation time 248697531 ps
CPU time 1 seconds
Started Aug 06 08:06:56 PM PDT 24
Finished Aug 06 08:06:57 PM PDT 24
Peak memory 207344 kb
Host smart-490f9f89-177e-4531-9418-c46e0a642fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27456
16447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2745616447
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2155439936
Short name T1339
Test name
Test status
Simulation time 231123363 ps
CPU time 0.92 seconds
Started Aug 06 08:06:46 PM PDT 24
Finished Aug 06 08:06:47 PM PDT 24
Peak memory 207380 kb
Host smart-03c2c48b-6680-424f-b733-9b0e889698cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21554
39936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2155439936
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.1627411992
Short name T2920
Test name
Test status
Simulation time 185826239 ps
CPU time 0.92 seconds
Started Aug 06 08:06:44 PM PDT 24
Finished Aug 06 08:06:45 PM PDT 24
Peak memory 207396 kb
Host smart-a643432a-74a7-41e1-9e10-ff84e6f26365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16274
11992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.1627411992
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.649160414
Short name T3045
Test name
Test status
Simulation time 148871461 ps
CPU time 0.84 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:06:55 PM PDT 24
Peak memory 207360 kb
Host smart-eba6efa9-b4f0-4bf8-9626-ae0b51706a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64916
0414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.649160414
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_rx_full.3530374771
Short name T318
Test name
Test status
Simulation time 313448708 ps
CPU time 1.19 seconds
Started Aug 06 08:06:47 PM PDT 24
Finished Aug 06 08:06:49 PM PDT 24
Peak memory 207304 kb
Host smart-787e834c-a491-49be-b962-388494022afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35303
74771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.3530374771
Directory /workspace/33.usbdev_rx_full/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.4247192421
Short name T2255
Test name
Test status
Simulation time 175195579 ps
CPU time 0.9 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:06:55 PM PDT 24
Peak memory 207252 kb
Host smart-93d14712-71c5-4c95-a796-4e35701aacb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42471
92421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.4247192421
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3802366051
Short name T2790
Test name
Test status
Simulation time 154563843 ps
CPU time 0.87 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:06:55 PM PDT 24
Peak memory 207356 kb
Host smart-1f4a643e-4672-4ff4-a126-704a5424552a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38023
66051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3802366051
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1619295858
Short name T2571
Test name
Test status
Simulation time 315965483 ps
CPU time 1.12 seconds
Started Aug 06 08:06:46 PM PDT 24
Finished Aug 06 08:06:47 PM PDT 24
Peak memory 207396 kb
Host smart-9ebdd944-a3f6-413b-9d69-8dd5b7e5ff65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16192
95858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1619295858
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.197808539
Short name T916
Test name
Test status
Simulation time 1824041285 ps
CPU time 18.26 seconds
Started Aug 06 08:07:14 PM PDT 24
Finished Aug 06 08:07:33 PM PDT 24
Peak memory 223908 kb
Host smart-022f8a01-3422-4fdb-ba04-4cacbe91f4ef
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=197808539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.197808539
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.4113636393
Short name T1301
Test name
Test status
Simulation time 177249339 ps
CPU time 0.88 seconds
Started Aug 06 08:06:55 PM PDT 24
Finished Aug 06 08:06:56 PM PDT 24
Peak memory 207304 kb
Host smart-d1d30c59-6761-44ae-91e9-ab92d865d654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41136
36393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.4113636393
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3641590248
Short name T2662
Test name
Test status
Simulation time 195079516 ps
CPU time 0.88 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:06:55 PM PDT 24
Peak memory 207348 kb
Host smart-602b42c7-170a-440c-ae4d-03585e8db995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36415
90248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3641590248
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.3793215393
Short name T1157
Test name
Test status
Simulation time 1258662491 ps
CPU time 2.84 seconds
Started Aug 06 08:07:02 PM PDT 24
Finished Aug 06 08:07:05 PM PDT 24
Peak memory 207596 kb
Host smart-d926ed3f-be04-4481-9167-7ad318d6a70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37932
15393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.3793215393
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.2013927031
Short name T665
Test name
Test status
Simulation time 2687620934 ps
CPU time 78.57 seconds
Started Aug 06 08:07:00 PM PDT 24
Finished Aug 06 08:08:19 PM PDT 24
Peak memory 217388 kb
Host smart-98209f60-b0bb-432f-ab2b-14e016df26d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20139
27031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.2013927031
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.196176377
Short name T1307
Test name
Test status
Simulation time 1461867151 ps
CPU time 33.51 seconds
Started Aug 06 08:06:40 PM PDT 24
Finished Aug 06 08:07:14 PM PDT 24
Peak memory 207680 kb
Host smart-95f75a1b-e1ff-4c85-8400-ddcdeec3d15f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196176377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_host
_handshake.196176377
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.710602731
Short name T2901
Test name
Test status
Simulation time 37267657 ps
CPU time 0.66 seconds
Started Aug 06 08:07:08 PM PDT 24
Finished Aug 06 08:07:09 PM PDT 24
Peak memory 207424 kb
Host smart-54056e85-d2f8-404c-a459-8e099400a385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=710602731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.710602731
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2981850423
Short name T1380
Test name
Test status
Simulation time 5626141389 ps
CPU time 9.15 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:07:03 PM PDT 24
Peak memory 215828 kb
Host smart-e8dd7401-6e91-40fe-a5a4-fd240fecc547
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981850423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.2981850423
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.229842072
Short name T1164
Test name
Test status
Simulation time 18897909920 ps
CPU time 26.39 seconds
Started Aug 06 08:07:20 PM PDT 24
Finished Aug 06 08:07:47 PM PDT 24
Peak memory 207692 kb
Host smart-e243fe7c-8c75-4896-859d-256dc0abf492
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=229842072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.229842072
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.2578309209
Short name T119
Test name
Test status
Simulation time 26012437496 ps
CPU time 30.59 seconds
Started Aug 06 08:07:16 PM PDT 24
Finished Aug 06 08:07:47 PM PDT 24
Peak memory 215852 kb
Host smart-12566b22-d824-4b45-b773-1a4bb6c2f024
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578309209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.2578309209
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1268525368
Short name T726
Test name
Test status
Simulation time 207663507 ps
CPU time 0.87 seconds
Started Aug 06 08:07:02 PM PDT 24
Finished Aug 06 08:07:02 PM PDT 24
Peak memory 207416 kb
Host smart-df848202-4300-4b78-beb0-af64ba2a3175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12685
25368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1268525368
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.3814227976
Short name T1108
Test name
Test status
Simulation time 147090677 ps
CPU time 0.86 seconds
Started Aug 06 08:07:10 PM PDT 24
Finished Aug 06 08:07:11 PM PDT 24
Peak memory 207288 kb
Host smart-7e16b191-eb52-4067-93cc-db954e455b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38142
27976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.3814227976
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2835383476
Short name T1020
Test name
Test status
Simulation time 583935797 ps
CPU time 1.89 seconds
Started Aug 06 08:06:55 PM PDT 24
Finished Aug 06 08:06:58 PM PDT 24
Peak memory 207416 kb
Host smart-16638a1f-f4a6-4a5f-b60b-9a0b2f1392d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28353
83476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2835383476
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2432454500
Short name T1426
Test name
Test status
Simulation time 391712405 ps
CPU time 1.34 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207324 kb
Host smart-3b9332d2-2bf4-4086-b6a0-1cd36f1aeadf
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2432454500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2432454500
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.1316810741
Short name T2880
Test name
Test status
Simulation time 45516428253 ps
CPU time 64.18 seconds
Started Aug 06 08:06:55 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207660 kb
Host smart-db771fb4-3745-41c5-8c12-05cc3db99227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13168
10741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.1316810741
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.957980590
Short name T899
Test name
Test status
Simulation time 4361641114 ps
CPU time 27.34 seconds
Started Aug 06 08:06:51 PM PDT 24
Finished Aug 06 08:07:18 PM PDT 24
Peak memory 207712 kb
Host smart-24035840-a2f2-4051-93d0-1cfee7b7b1ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957980590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.957980590
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.140165139
Short name T122
Test name
Test status
Simulation time 1005265702 ps
CPU time 2.22 seconds
Started Aug 06 08:06:55 PM PDT 24
Finished Aug 06 08:06:57 PM PDT 24
Peak memory 207420 kb
Host smart-79a14e12-035f-4299-86cf-340af2dede1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14016
5139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.140165139
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1637365162
Short name T2557
Test name
Test status
Simulation time 131496661 ps
CPU time 0.83 seconds
Started Aug 06 08:07:01 PM PDT 24
Finished Aug 06 08:07:02 PM PDT 24
Peak memory 207364 kb
Host smart-bd0effc6-2c74-41cd-8633-c7ea7c7b177c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16373
65162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1637365162
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1825085356
Short name T804
Test name
Test status
Simulation time 37657461 ps
CPU time 0.7 seconds
Started Aug 06 08:06:53 PM PDT 24
Finished Aug 06 08:06:54 PM PDT 24
Peak memory 207360 kb
Host smart-d606d2d2-2f33-4f6e-84a4-53cce1fe2bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18250
85356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1825085356
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.48447407
Short name T2332
Test name
Test status
Simulation time 834490722 ps
CPU time 2.37 seconds
Started Aug 06 08:07:14 PM PDT 24
Finished Aug 06 08:07:16 PM PDT 24
Peak memory 207560 kb
Host smart-73862699-22b2-4baf-88ca-87245055bab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48447
407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.48447407
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_types.2889871768
Short name T2496
Test name
Test status
Simulation time 510846539 ps
CPU time 1.38 seconds
Started Aug 06 08:06:58 PM PDT 24
Finished Aug 06 08:07:00 PM PDT 24
Peak memory 207372 kb
Host smart-3a151dc6-4976-4074-9864-af01f057ea3b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2889871768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.2889871768
Directory /workspace/34.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2348178404
Short name T2505
Test name
Test status
Simulation time 180249299 ps
CPU time 2.23 seconds
Started Aug 06 08:07:03 PM PDT 24
Finished Aug 06 08:07:05 PM PDT 24
Peak memory 207456 kb
Host smart-bd605ec0-76e2-45bc-a883-5f7a177a43fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23481
78404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2348178404
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3525329599
Short name T3093
Test name
Test status
Simulation time 208185568 ps
CPU time 1.07 seconds
Started Aug 06 08:06:58 PM PDT 24
Finished Aug 06 08:06:59 PM PDT 24
Peak memory 215620 kb
Host smart-bc1967cf-25f2-49a1-a46f-34f901dbdbf0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3525329599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3525329599
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2215593610
Short name T2956
Test name
Test status
Simulation time 143472623 ps
CPU time 0.86 seconds
Started Aug 06 08:06:59 PM PDT 24
Finished Aug 06 08:07:00 PM PDT 24
Peak memory 207372 kb
Host smart-5529b864-2812-4557-847a-156833d26c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22155
93610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2215593610
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2510547863
Short name T1163
Test name
Test status
Simulation time 237003485 ps
CPU time 1.08 seconds
Started Aug 06 08:07:08 PM PDT 24
Finished Aug 06 08:07:09 PM PDT 24
Peak memory 207364 kb
Host smart-0de31519-c0e9-4d51-8df5-c0dfba7e775e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25105
47863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2510547863
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.3504395016
Short name T1856
Test name
Test status
Simulation time 5114607231 ps
CPU time 149.11 seconds
Started Aug 06 08:06:59 PM PDT 24
Finished Aug 06 08:09:29 PM PDT 24
Peak memory 218244 kb
Host smart-0eeb8546-8650-4e48-8e73-530e6b3adbbd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3504395016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.3504395016
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.1286440928
Short name T2468
Test name
Test status
Simulation time 13798415017 ps
CPU time 99.01 seconds
Started Aug 06 08:07:04 PM PDT 24
Finished Aug 06 08:08:43 PM PDT 24
Peak memory 207644 kb
Host smart-9cf3df29-dace-4d62-b237-b89c631cfaea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1286440928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.1286440928
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.458488659
Short name T1939
Test name
Test status
Simulation time 240068375 ps
CPU time 1.01 seconds
Started Aug 06 08:06:56 PM PDT 24
Finished Aug 06 08:06:57 PM PDT 24
Peak memory 207312 kb
Host smart-6ee11e7d-873f-4f16-9a31-302e19199b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45848
8659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.458488659
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1637471983
Short name T1366
Test name
Test status
Simulation time 7594387913 ps
CPU time 12.14 seconds
Started Aug 06 08:06:58 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207520 kb
Host smart-1f4fdcf5-389b-43b2-a3b8-8fcb7b966489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16374
71983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1637471983
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3118904556
Short name T1991
Test name
Test status
Simulation time 5651528025 ps
CPU time 8.15 seconds
Started Aug 06 08:07:11 PM PDT 24
Finished Aug 06 08:07:19 PM PDT 24
Peak memory 215808 kb
Host smart-2f975070-3069-4025-b49b-f224f1eb2fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31189
04556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3118904556
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.4254871788
Short name T2417
Test name
Test status
Simulation time 4819226385 ps
CPU time 45.7 seconds
Started Aug 06 08:07:12 PM PDT 24
Finished Aug 06 08:07:58 PM PDT 24
Peak memory 217584 kb
Host smart-2922eec5-1ac1-4fce-8792-6d4b3c25062b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42548
71788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.4254871788
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3417705996
Short name T1879
Test name
Test status
Simulation time 3219446256 ps
CPU time 24.01 seconds
Started Aug 06 08:06:56 PM PDT 24
Finished Aug 06 08:07:20 PM PDT 24
Peak memory 215868 kb
Host smart-de714ec0-8741-49ae-8e96-c5936baf4951
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3417705996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3417705996
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.717752127
Short name T1511
Test name
Test status
Simulation time 244112299 ps
CPU time 1.01 seconds
Started Aug 06 08:07:16 PM PDT 24
Finished Aug 06 08:07:17 PM PDT 24
Peak memory 207344 kb
Host smart-ba764b9c-9d75-434a-aba4-a33c54e9ddc4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=717752127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.717752127
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3058237273
Short name T2418
Test name
Test status
Simulation time 194416622 ps
CPU time 0.92 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207348 kb
Host smart-db6839fd-5321-47c0-91c0-e0024ae9f9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30582
37273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3058237273
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.2119872296
Short name T3090
Test name
Test status
Simulation time 2045738668 ps
CPU time 20.82 seconds
Started Aug 06 08:07:01 PM PDT 24
Finished Aug 06 08:07:22 PM PDT 24
Peak memory 217084 kb
Host smart-89ac7039-b4a4-44ba-8ab6-e3c0a3f6db45
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2119872296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2119872296
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1511560914
Short name T525
Test name
Test status
Simulation time 210562321 ps
CPU time 0.94 seconds
Started Aug 06 08:07:02 PM PDT 24
Finished Aug 06 08:07:03 PM PDT 24
Peak memory 207332 kb
Host smart-7595493e-525a-443f-a9ff-94157451a674
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1511560914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1511560914
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2582932968
Short name T2539
Test name
Test status
Simulation time 151335941 ps
CPU time 0.83 seconds
Started Aug 06 08:07:12 PM PDT 24
Finished Aug 06 08:07:13 PM PDT 24
Peak memory 207348 kb
Host smart-037e0113-052d-4c47-8af8-2e0e324df5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25829
32968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2582932968
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3217926351
Short name T2775
Test name
Test status
Simulation time 215398499 ps
CPU time 0.93 seconds
Started Aug 06 08:07:04 PM PDT 24
Finished Aug 06 08:07:05 PM PDT 24
Peak memory 207356 kb
Host smart-b2c55320-c053-42a7-bdab-bb1ac5111e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32179
26351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3217926351
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3202547778
Short name T897
Test name
Test status
Simulation time 192795630 ps
CPU time 0.92 seconds
Started Aug 06 08:07:00 PM PDT 24
Finished Aug 06 08:07:01 PM PDT 24
Peak memory 207356 kb
Host smart-8d866dae-3bfb-4d49-b2c8-d5f84c314cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32025
47778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3202547778
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3279004578
Short name T1510
Test name
Test status
Simulation time 156237644 ps
CPU time 0.88 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:11 PM PDT 24
Peak memory 207340 kb
Host smart-53968371-07b9-44cc-b5eb-e8b4a1668986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32790
04578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3279004578
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3927368424
Short name T2713
Test name
Test status
Simulation time 164823746 ps
CPU time 0.94 seconds
Started Aug 06 08:06:59 PM PDT 24
Finished Aug 06 08:07:01 PM PDT 24
Peak memory 207308 kb
Host smart-7746d49d-2913-4633-8299-c786ebbd2ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39273
68424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3927368424
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2488126547
Short name T1016
Test name
Test status
Simulation time 159154628 ps
CPU time 0.86 seconds
Started Aug 06 08:06:57 PM PDT 24
Finished Aug 06 08:07:02 PM PDT 24
Peak memory 207392 kb
Host smart-aed63091-ca99-4ea2-aa02-e2ce7397dfd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24881
26547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2488126547
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1721238946
Short name T2749
Test name
Test status
Simulation time 231484618 ps
CPU time 1.03 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207324 kb
Host smart-0a1b3721-5cc7-4666-beed-8af27ea1e15c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1721238946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1721238946
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1586663544
Short name T982
Test name
Test status
Simulation time 142418786 ps
CPU time 0.8 seconds
Started Aug 06 08:07:03 PM PDT 24
Finished Aug 06 08:07:04 PM PDT 24
Peak memory 207320 kb
Host smart-2b318f35-bb2a-4ba5-b5ef-4547760c969d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15866
63544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1586663544
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.4032219573
Short name T38
Test name
Test status
Simulation time 34215422 ps
CPU time 0.7 seconds
Started Aug 06 08:06:57 PM PDT 24
Finished Aug 06 08:06:58 PM PDT 24
Peak memory 207216 kb
Host smart-cf9f8de1-efed-4d71-b610-022f158f9b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40322
19573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.4032219573
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.928479817
Short name T306
Test name
Test status
Simulation time 17939586513 ps
CPU time 45.76 seconds
Started Aug 06 08:06:54 PM PDT 24
Finished Aug 06 08:07:40 PM PDT 24
Peak memory 215812 kb
Host smart-798b5dfb-774c-4745-b631-2fb24c2eabb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92847
9817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.928479817
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1004408531
Short name T2724
Test name
Test status
Simulation time 187149923 ps
CPU time 1.01 seconds
Started Aug 06 08:07:05 PM PDT 24
Finished Aug 06 08:07:06 PM PDT 24
Peak memory 207444 kb
Host smart-63d95501-5844-47c9-a8e3-7e182678cf65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10044
08531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1004408531
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2741575141
Short name T533
Test name
Test status
Simulation time 205298242 ps
CPU time 0.98 seconds
Started Aug 06 08:07:00 PM PDT 24
Finished Aug 06 08:07:01 PM PDT 24
Peak memory 207392 kb
Host smart-594a1d8b-4201-4eec-a18f-600fbd3451de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27415
75141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2741575141
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.1046500556
Short name T1867
Test name
Test status
Simulation time 264729391 ps
CPU time 0.99 seconds
Started Aug 06 08:06:55 PM PDT 24
Finished Aug 06 08:06:56 PM PDT 24
Peak memory 207320 kb
Host smart-a9adfbaf-6e49-4c05-a76c-d0a3563a517a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10465
00556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1046500556
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2948335071
Short name T833
Test name
Test status
Simulation time 158943012 ps
CPU time 0.83 seconds
Started Aug 06 08:06:49 PM PDT 24
Finished Aug 06 08:06:50 PM PDT 24
Peak memory 207396 kb
Host smart-7f9f7b44-83ea-4825-adb8-2582d8b32a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29483
35071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2948335071
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1506119787
Short name T919
Test name
Test status
Simulation time 148127073 ps
CPU time 0.84 seconds
Started Aug 06 08:06:59 PM PDT 24
Finished Aug 06 08:07:00 PM PDT 24
Peak memory 207316 kb
Host smart-af313208-2502-43f8-a3db-74259c139082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15061
19787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1506119787
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_rx_full.2827190315
Short name T764
Test name
Test status
Simulation time 252508217 ps
CPU time 1.1 seconds
Started Aug 06 08:07:02 PM PDT 24
Finished Aug 06 08:07:04 PM PDT 24
Peak memory 207372 kb
Host smart-b1c67a4a-0517-4e82-9193-1ce8d47cb45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28271
90315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.2827190315
Directory /workspace/34.usbdev_rx_full/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.2103980451
Short name T596
Test name
Test status
Simulation time 149921687 ps
CPU time 0.86 seconds
Started Aug 06 08:06:57 PM PDT 24
Finished Aug 06 08:06:58 PM PDT 24
Peak memory 207252 kb
Host smart-01c131da-7991-4670-8800-4bd4f69fba86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039
80451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2103980451
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3239588337
Short name T1029
Test name
Test status
Simulation time 151841205 ps
CPU time 0.82 seconds
Started Aug 06 08:06:46 PM PDT 24
Finished Aug 06 08:06:47 PM PDT 24
Peak memory 207356 kb
Host smart-94b9a71d-b385-494e-b510-02125a3455a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32395
88337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3239588337
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1241303715
Short name T1905
Test name
Test status
Simulation time 222377196 ps
CPU time 0.97 seconds
Started Aug 06 08:07:10 PM PDT 24
Finished Aug 06 08:07:11 PM PDT 24
Peak memory 207404 kb
Host smart-b353b404-f36e-4925-abc5-4369033f1a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12413
03715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1241303715
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1482379805
Short name T178
Test name
Test status
Simulation time 1871749585 ps
CPU time 48.73 seconds
Started Aug 06 08:07:01 PM PDT 24
Finished Aug 06 08:07:50 PM PDT 24
Peak memory 217124 kb
Host smart-54b59504-b2f6-4eb5-96bf-2d83c49d5202
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1482379805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1482379805
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2839779478
Short name T702
Test name
Test status
Simulation time 169171535 ps
CPU time 0.84 seconds
Started Aug 06 08:06:48 PM PDT 24
Finished Aug 06 08:06:49 PM PDT 24
Peak memory 207404 kb
Host smart-dce1026d-e51e-4bf8-9ea8-d41d90922b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28397
79478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2839779478
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3932035220
Short name T818
Test name
Test status
Simulation time 201939534 ps
CPU time 0.95 seconds
Started Aug 06 08:06:56 PM PDT 24
Finished Aug 06 08:06:57 PM PDT 24
Peak memory 207288 kb
Host smart-3281c277-e469-44b2-8f37-d43c6268f66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39320
35220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3932035220
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.2394218025
Short name T102
Test name
Test status
Simulation time 440930182 ps
CPU time 1.35 seconds
Started Aug 06 08:07:19 PM PDT 24
Finished Aug 06 08:07:20 PM PDT 24
Peak memory 207288 kb
Host smart-93222c93-ed67-4b83-8ebb-0b155b8ee1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23942
18025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.2394218025
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.4228532921
Short name T1069
Test name
Test status
Simulation time 3690698333 ps
CPU time 26.29 seconds
Started Aug 06 08:07:10 PM PDT 24
Finished Aug 06 08:07:36 PM PDT 24
Peak memory 215884 kb
Host smart-5078fb4e-9270-4063-9cee-d8107eb855ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42285
32921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.4228532921
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.1373373302
Short name T964
Test name
Test status
Simulation time 498021972 ps
CPU time 8.2 seconds
Started Aug 06 08:06:53 PM PDT 24
Finished Aug 06 08:07:01 PM PDT 24
Peak memory 207556 kb
Host smart-5c2f3ee5-6173-45de-ad23-65f3eb36b64e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373373302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.1373373302
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.2916543413
Short name T2144
Test name
Test status
Simulation time 50854449 ps
CPU time 0.66 seconds
Started Aug 06 08:07:03 PM PDT 24
Finished Aug 06 08:07:03 PM PDT 24
Peak memory 207400 kb
Host smart-e1a299ed-5b93-40f8-b2d2-d1c651253567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2916543413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2916543413
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2204766638
Short name T1079
Test name
Test status
Simulation time 9738495275 ps
CPU time 13.73 seconds
Started Aug 06 08:06:53 PM PDT 24
Finished Aug 06 08:07:07 PM PDT 24
Peak memory 207688 kb
Host smart-22cb6e8e-6f3a-4498-8e53-10154e32a393
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204766638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.2204766638
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.1540507698
Short name T115
Test name
Test status
Simulation time 31221959159 ps
CPU time 46.39 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:55 PM PDT 24
Peak memory 207600 kb
Host smart-d4f7df22-c9f3-4181-b47f-1178e07e8bf0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540507698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.1540507698
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2187731169
Short name T1944
Test name
Test status
Simulation time 191634744 ps
CPU time 0.92 seconds
Started Aug 06 08:07:15 PM PDT 24
Finished Aug 06 08:07:16 PM PDT 24
Peak memory 207336 kb
Host smart-92d18b23-befd-4804-8a85-7e068558ca91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21877
31169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2187731169
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.128777565
Short name T1439
Test name
Test status
Simulation time 140539420 ps
CPU time 0.84 seconds
Started Aug 06 08:06:53 PM PDT 24
Finished Aug 06 08:06:55 PM PDT 24
Peak memory 207380 kb
Host smart-5f5513cc-e1a1-4d1d-9b17-6daa2b6189c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12877
7565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.128777565
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.1486462225
Short name T2886
Test name
Test status
Simulation time 217873897 ps
CPU time 1 seconds
Started Aug 06 08:06:48 PM PDT 24
Finished Aug 06 08:06:50 PM PDT 24
Peak memory 207392 kb
Host smart-1941bb30-ef40-4a05-b501-b2d292835b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14864
62225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1486462225
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.413883012
Short name T3106
Test name
Test status
Simulation time 597264424 ps
CPU time 1.67 seconds
Started Aug 06 08:06:58 PM PDT 24
Finished Aug 06 08:07:00 PM PDT 24
Peak memory 207408 kb
Host smart-b228d57e-bbaa-4913-afbf-488f0388d0c9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=413883012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.413883012
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3704567795
Short name T986
Test name
Test status
Simulation time 24968503723 ps
CPU time 46.01 seconds
Started Aug 06 08:07:01 PM PDT 24
Finished Aug 06 08:07:47 PM PDT 24
Peak memory 207632 kb
Host smart-5381d32e-fd06-43ed-9e8b-22e58c123306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37045
67795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3704567795
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.257484157
Short name T1219
Test name
Test status
Simulation time 1059829984 ps
CPU time 8.99 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:18 PM PDT 24
Peak memory 207592 kb
Host smart-a69c7bf3-c888-4ef4-b840-2da7913d8956
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257484157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.257484157
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.606363542
Short name T2969
Test name
Test status
Simulation time 840678528 ps
CPU time 1.96 seconds
Started Aug 06 08:07:00 PM PDT 24
Finished Aug 06 08:07:02 PM PDT 24
Peak memory 207308 kb
Host smart-4375d15c-9997-4745-a5a2-4461a96ad20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60636
3542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.606363542
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.2207887018
Short name T1025
Test name
Test status
Simulation time 146993721 ps
CPU time 0.84 seconds
Started Aug 06 08:07:02 PM PDT 24
Finished Aug 06 08:07:03 PM PDT 24
Peak memory 207300 kb
Host smart-9897f93b-10d7-4945-989c-bd319330d919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22078
87018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.2207887018
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1140861247
Short name T1148
Test name
Test status
Simulation time 34833528 ps
CPU time 0.75 seconds
Started Aug 06 08:07:12 PM PDT 24
Finished Aug 06 08:07:13 PM PDT 24
Peak memory 207312 kb
Host smart-fad63e6f-d43f-4f71-862d-bfeed39f2c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11408
61247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1140861247
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1796303501
Short name T1793
Test name
Test status
Simulation time 809693994 ps
CPU time 2.22 seconds
Started Aug 06 08:07:14 PM PDT 24
Finished Aug 06 08:07:16 PM PDT 24
Peak memory 207512 kb
Host smart-2ba000b6-8eea-426d-9492-daf331e90e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17963
03501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1796303501
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_types.3287254614
Short name T351
Test name
Test status
Simulation time 698768015 ps
CPU time 1.72 seconds
Started Aug 06 08:06:56 PM PDT 24
Finished Aug 06 08:06:58 PM PDT 24
Peak memory 207348 kb
Host smart-45991a63-cfde-48a2-a714-4af5488c9e03
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3287254614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.3287254614
Directory /workspace/35.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.551166493
Short name T758
Test name
Test status
Simulation time 209271794 ps
CPU time 2.21 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:11 PM PDT 24
Peak memory 207500 kb
Host smart-78ba484d-5629-4941-9e9d-8c3757ffcccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55116
6493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.551166493
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2863545896
Short name T1512
Test name
Test status
Simulation time 230490410 ps
CPU time 0.95 seconds
Started Aug 06 08:07:04 PM PDT 24
Finished Aug 06 08:07:05 PM PDT 24
Peak memory 207312 kb
Host smart-a93ba132-502c-4c72-aaaa-40fff0062648
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2863545896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2863545896
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1268395823
Short name T610
Test name
Test status
Simulation time 213739392 ps
CPU time 0.96 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207340 kb
Host smart-48e05ebd-8172-44bf-8801-ebb774bf4a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12683
95823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1268395823
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1855676436
Short name T2843
Test name
Test status
Simulation time 251665138 ps
CPU time 1.01 seconds
Started Aug 06 08:06:58 PM PDT 24
Finished Aug 06 08:07:00 PM PDT 24
Peak memory 207384 kb
Host smart-533c9389-4af6-446d-b016-7c4b8de00c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18556
76436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1855676436
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.3128732351
Short name T2113
Test name
Test status
Simulation time 3334924030 ps
CPU time 25.14 seconds
Started Aug 06 08:07:01 PM PDT 24
Finished Aug 06 08:07:26 PM PDT 24
Peak memory 217660 kb
Host smart-a98ba61a-ecdf-4f15-bfb5-a22bcffab346
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3128732351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.3128732351
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.2220362158
Short name T2186
Test name
Test status
Simulation time 6357950585 ps
CPU time 44.62 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:54 PM PDT 24
Peak memory 207588 kb
Host smart-5e02ea73-0568-4673-981c-96814bdb608a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2220362158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.2220362158
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1412893927
Short name T1537
Test name
Test status
Simulation time 259859100 ps
CPU time 0.96 seconds
Started Aug 06 08:07:07 PM PDT 24
Finished Aug 06 08:07:08 PM PDT 24
Peak memory 207356 kb
Host smart-48a97343-fa6a-4984-8be4-a840a8e09a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14128
93927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1412893927
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1599106552
Short name T990
Test name
Test status
Simulation time 13363792675 ps
CPU time 21.78 seconds
Started Aug 06 08:07:07 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207600 kb
Host smart-9e68158f-8e4b-49ee-80f7-298fa2ce1449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15991
06552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1599106552
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2474117738
Short name T523
Test name
Test status
Simulation time 10217961499 ps
CPU time 13.12 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207480 kb
Host smart-c4d1eb93-92b9-46bc-8cb6-6389c85553bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24741
17738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2474117738
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.3847536360
Short name T1818
Test name
Test status
Simulation time 3305384799 ps
CPU time 24.19 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:34 PM PDT 24
Peak memory 217904 kb
Host smart-9b05dd8d-d2c3-4734-a6b6-43235f92046e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38475
36360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.3847536360
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2007209265
Short name T2975
Test name
Test status
Simulation time 3185493170 ps
CPU time 92.29 seconds
Started Aug 06 08:07:00 PM PDT 24
Finished Aug 06 08:08:33 PM PDT 24
Peak memory 215824 kb
Host smart-ced1bd90-9c2b-4a68-b1c3-a5876702c5e9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2007209265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2007209265
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.232458441
Short name T2777
Test name
Test status
Simulation time 274661088 ps
CPU time 1 seconds
Started Aug 06 08:07:10 PM PDT 24
Finished Aug 06 08:07:11 PM PDT 24
Peak memory 207348 kb
Host smart-e24c55ee-126b-44bd-aab7-5544a0e5b9f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=232458441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.232458441
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1625082011
Short name T3088
Test name
Test status
Simulation time 225910879 ps
CPU time 1.01 seconds
Started Aug 06 08:07:02 PM PDT 24
Finished Aug 06 08:07:03 PM PDT 24
Peak memory 207400 kb
Host smart-768eb814-178b-43ed-94b0-1bd83622f5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16250
82011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1625082011
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.564038722
Short name T2589
Test name
Test status
Simulation time 2574095857 ps
CPU time 20.61 seconds
Started Aug 06 08:07:11 PM PDT 24
Finished Aug 06 08:07:32 PM PDT 24
Peak memory 217476 kb
Host smart-b0ee3a05-2ace-4bba-a3ad-ecd18c27ea74
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=564038722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.564038722
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3302363108
Short name T2283
Test name
Test status
Simulation time 160283140 ps
CPU time 0.87 seconds
Started Aug 06 08:07:13 PM PDT 24
Finished Aug 06 08:07:14 PM PDT 24
Peak memory 207404 kb
Host smart-2ddba80b-1def-45fc-a2d2-f768662f12be
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3302363108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3302363108
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1077786384
Short name T1497
Test name
Test status
Simulation time 147643200 ps
CPU time 0.84 seconds
Started Aug 06 08:06:58 PM PDT 24
Finished Aug 06 08:06:59 PM PDT 24
Peak memory 207452 kb
Host smart-86a0744a-bcb6-48c1-9904-b895c8a15b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10777
86384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1077786384
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2403712084
Short name T156
Test name
Test status
Simulation time 181683505 ps
CPU time 0.96 seconds
Started Aug 06 08:07:13 PM PDT 24
Finished Aug 06 08:07:14 PM PDT 24
Peak memory 207364 kb
Host smart-f4a19c03-6bde-4821-98b0-7b9beb729e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24037
12084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2403712084
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.895117417
Short name T1959
Test name
Test status
Simulation time 206675544 ps
CPU time 0.93 seconds
Started Aug 06 08:07:17 PM PDT 24
Finished Aug 06 08:07:18 PM PDT 24
Peak memory 207324 kb
Host smart-ea6027a0-5ccc-4eef-84f1-ec91d1409166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89511
7417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.895117417
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1850795521
Short name T1424
Test name
Test status
Simulation time 169437854 ps
CPU time 0.84 seconds
Started Aug 06 08:06:53 PM PDT 24
Finished Aug 06 08:06:54 PM PDT 24
Peak memory 207356 kb
Host smart-ed693b9d-307b-4b05-a3e5-b2fafc5a8b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18507
95521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1850795521
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2711341733
Short name T3005
Test name
Test status
Simulation time 172345702 ps
CPU time 0.93 seconds
Started Aug 06 08:06:55 PM PDT 24
Finished Aug 06 08:06:56 PM PDT 24
Peak memory 207308 kb
Host smart-568eb862-976a-4553-bc78-67edf03c5c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27113
41733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2711341733
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1284397563
Short name T998
Test name
Test status
Simulation time 145120279 ps
CPU time 0.84 seconds
Started Aug 06 08:07:12 PM PDT 24
Finished Aug 06 08:07:13 PM PDT 24
Peak memory 207368 kb
Host smart-6fdc95ca-6ece-405c-b05b-22d894d502e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12843
97563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1284397563
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.3025478617
Short name T1405
Test name
Test status
Simulation time 234382284 ps
CPU time 0.98 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207424 kb
Host smart-6de80c4f-3e26-409d-b3fc-9f23fce7fca8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3025478617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.3025478617
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3433194985
Short name T1846
Test name
Test status
Simulation time 143965897 ps
CPU time 0.9 seconds
Started Aug 06 08:07:01 PM PDT 24
Finished Aug 06 08:07:02 PM PDT 24
Peak memory 207344 kb
Host smart-23c8937b-b1ad-40d8-a253-9b3d2a9d3c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34331
94985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3433194985
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3681049363
Short name T1683
Test name
Test status
Simulation time 76697913 ps
CPU time 0.74 seconds
Started Aug 06 08:07:02 PM PDT 24
Finished Aug 06 08:07:03 PM PDT 24
Peak memory 207364 kb
Host smart-0dac55de-f5a0-4c36-ad83-3a35626ca204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36810
49363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3681049363
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1690658970
Short name T2446
Test name
Test status
Simulation time 16168215171 ps
CPU time 43.24 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:53 PM PDT 24
Peak memory 220064 kb
Host smart-26e1d1f5-bec1-4056-9c68-ec947ace28f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16906
58970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1690658970
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3980527214
Short name T980
Test name
Test status
Simulation time 181944233 ps
CPU time 0.92 seconds
Started Aug 06 08:07:15 PM PDT 24
Finished Aug 06 08:07:16 PM PDT 24
Peak memory 207208 kb
Host smart-2426ee8d-0937-4292-83c1-b13ce2e7c80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39805
27214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3980527214
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3784866161
Short name T1555
Test name
Test status
Simulation time 240838178 ps
CPU time 1.06 seconds
Started Aug 06 08:07:02 PM PDT 24
Finished Aug 06 08:07:03 PM PDT 24
Peak memory 207344 kb
Host smart-710c009e-9235-4218-8d77-557ce2f61146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37848
66161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3784866161
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1913216964
Short name T1664
Test name
Test status
Simulation time 178917589 ps
CPU time 0.91 seconds
Started Aug 06 08:07:08 PM PDT 24
Finished Aug 06 08:07:09 PM PDT 24
Peak memory 207364 kb
Host smart-d80e187d-88cf-4240-8175-629106dfbdd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19132
16964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1913216964
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2808763080
Short name T1182
Test name
Test status
Simulation time 149871350 ps
CPU time 0.85 seconds
Started Aug 06 08:07:08 PM PDT 24
Finished Aug 06 08:07:09 PM PDT 24
Peak memory 207288 kb
Host smart-773b0aae-441f-4496-bc4a-c3118925d7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28087
63080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2808763080
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.1182863150
Short name T1113
Test name
Test status
Simulation time 133932538 ps
CPU time 0.81 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:11 PM PDT 24
Peak memory 207388 kb
Host smart-d6494579-fdae-4e4d-91ed-ef7311e1a60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11828
63150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.1182863150
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_rx_full.3430864789
Short name T2411
Test name
Test status
Simulation time 247062373 ps
CPU time 1.15 seconds
Started Aug 06 08:07:21 PM PDT 24
Finished Aug 06 08:07:22 PM PDT 24
Peak memory 207352 kb
Host smart-49a02be2-de9e-4b68-b842-44b500dc8e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34308
64789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.3430864789
Directory /workspace/35.usbdev_rx_full/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2306259729
Short name T1193
Test name
Test status
Simulation time 152953856 ps
CPU time 0.81 seconds
Started Aug 06 08:07:16 PM PDT 24
Finished Aug 06 08:07:17 PM PDT 24
Peak memory 207388 kb
Host smart-df93a015-5e3a-4f4a-9185-f902b813854a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23062
59729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2306259729
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3355320570
Short name T2486
Test name
Test status
Simulation time 161109680 ps
CPU time 0.87 seconds
Started Aug 06 08:06:53 PM PDT 24
Finished Aug 06 08:06:54 PM PDT 24
Peak memory 207296 kb
Host smart-2f4432f3-bb6b-4217-b78d-ccaddeacdabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33553
20570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3355320570
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1909365486
Short name T2011
Test name
Test status
Simulation time 202099444 ps
CPU time 0.98 seconds
Started Aug 06 08:07:11 PM PDT 24
Finished Aug 06 08:07:12 PM PDT 24
Peak memory 207288 kb
Host smart-c1e937f7-12ea-445f-a21d-fcd5ecbe06c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19093
65486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1909365486
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2312622320
Short name T2921
Test name
Test status
Simulation time 1742046833 ps
CPU time 17.73 seconds
Started Aug 06 08:07:11 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 217252 kb
Host smart-38478459-169f-435a-aa2c-d24a3a0853c3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2312622320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2312622320
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3488544686
Short name T2770
Test name
Test status
Simulation time 174563282 ps
CPU time 0.87 seconds
Started Aug 06 08:07:08 PM PDT 24
Finished Aug 06 08:07:09 PM PDT 24
Peak memory 207376 kb
Host smart-5c840587-f372-474c-9956-8baab4c92590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34885
44686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3488544686
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.2197901997
Short name T1661
Test name
Test status
Simulation time 177134031 ps
CPU time 0.86 seconds
Started Aug 06 08:06:58 PM PDT 24
Finished Aug 06 08:06:59 PM PDT 24
Peak memory 207288 kb
Host smart-34509714-c5b1-4ca1-91df-ef6c181ecf57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21979
01997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2197901997
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.2903961244
Short name T2573
Test name
Test status
Simulation time 710835344 ps
CPU time 1.81 seconds
Started Aug 06 08:07:11 PM PDT 24
Finished Aug 06 08:07:13 PM PDT 24
Peak memory 207348 kb
Host smart-37d2af3c-2156-446c-a6e4-9ef45776f455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29039
61244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.2903961244
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2032818767
Short name T1953
Test name
Test status
Simulation time 3726426343 ps
CPU time 105.9 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:08:55 PM PDT 24
Peak memory 217160 kb
Host smart-e1774710-08ba-4086-b6bf-52665f18d174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20328
18767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2032818767
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.163069919
Short name T1415
Test name
Test status
Simulation time 4408520659 ps
CPU time 29.89 seconds
Started Aug 06 08:06:56 PM PDT 24
Finished Aug 06 08:07:26 PM PDT 24
Peak memory 207648 kb
Host smart-de15c4fe-306a-4936-b552-dcb979bd7052
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163069919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_host
_handshake.163069919
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.3584628140
Short name T214
Test name
Test status
Simulation time 71714512 ps
CPU time 0.72 seconds
Started Aug 06 08:07:24 PM PDT 24
Finished Aug 06 08:07:25 PM PDT 24
Peak memory 207412 kb
Host smart-268b27fe-bca0-4242-83c8-4279867e9b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3584628140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.3584628140
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2318397327
Short name T2298
Test name
Test status
Simulation time 9225411319 ps
CPU time 11.75 seconds
Started Aug 06 08:07:01 PM PDT 24
Finished Aug 06 08:07:13 PM PDT 24
Peak memory 207624 kb
Host smart-ac1cc3e9-ab1d-4531-9834-ed2a5a0d3d79
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318397327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.2318397327
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.676037772
Short name T3119
Test name
Test status
Simulation time 19660319739 ps
CPU time 25.26 seconds
Started Aug 06 08:07:08 PM PDT 24
Finished Aug 06 08:07:33 PM PDT 24
Peak memory 207672 kb
Host smart-2a8d54e9-8b3d-4f84-9182-56041df1faad
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=676037772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.676037772
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.536674777
Short name T2545
Test name
Test status
Simulation time 31288950868 ps
CPU time 41.26 seconds
Started Aug 06 08:06:58 PM PDT 24
Finished Aug 06 08:07:40 PM PDT 24
Peak memory 207596 kb
Host smart-68c9a119-e7e8-4098-89a2-4ae9b8f3d263
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536674777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_ao
n_wake_resume.536674777
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2211281956
Short name T2136
Test name
Test status
Simulation time 207516150 ps
CPU time 0.89 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207300 kb
Host smart-36000e7c-1f4f-4063-95df-22890080264b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22112
81956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2211281956
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.139367691
Short name T577
Test name
Test status
Simulation time 137004981 ps
CPU time 0.81 seconds
Started Aug 06 08:07:08 PM PDT 24
Finished Aug 06 08:07:09 PM PDT 24
Peak memory 207268 kb
Host smart-7b7b216d-7476-4520-99a0-4ef46fa1bf9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13936
7691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.139367691
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3769751286
Short name T1308
Test name
Test status
Simulation time 515179608 ps
CPU time 1.65 seconds
Started Aug 06 08:07:11 PM PDT 24
Finished Aug 06 08:07:12 PM PDT 24
Peak memory 207264 kb
Host smart-7f38c8f1-8740-485f-a6ba-2ba3ce159074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37697
51286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3769751286
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.453161552
Short name T2524
Test name
Test status
Simulation time 745937584 ps
CPU time 2.05 seconds
Started Aug 06 08:07:08 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207360 kb
Host smart-4bfd1c82-ee49-439c-b426-7ffd65e3590b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=453161552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.453161552
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.3741591580
Short name T415
Test name
Test status
Simulation time 30478033751 ps
CPU time 46.43 seconds
Started Aug 06 08:07:03 PM PDT 24
Finished Aug 06 08:07:50 PM PDT 24
Peak memory 207572 kb
Host smart-ab4bb9e1-c6a4-4a85-8ef0-cc2a8c373ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37415
91580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.3741591580
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.1199824475
Short name T2896
Test name
Test status
Simulation time 652615030 ps
CPU time 12.34 seconds
Started Aug 06 08:07:03 PM PDT 24
Finished Aug 06 08:07:15 PM PDT 24
Peak memory 207508 kb
Host smart-21f1306d-7643-43dd-93a9-036db4d58d8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199824475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.1199824475
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.60117008
Short name T3104
Test name
Test status
Simulation time 629147454 ps
CPU time 1.66 seconds
Started Aug 06 08:07:02 PM PDT 24
Finished Aug 06 08:07:04 PM PDT 24
Peak memory 207320 kb
Host smart-349e6a04-7cb7-4974-9fa8-865ff4687c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60117
008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.60117008
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.57931566
Short name T837
Test name
Test status
Simulation time 157251237 ps
CPU time 0.91 seconds
Started Aug 06 08:07:03 PM PDT 24
Finished Aug 06 08:07:04 PM PDT 24
Peak memory 207280 kb
Host smart-c5b6dbeb-ada9-45e9-b360-33360361a586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57931
566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.57931566
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.1972789650
Short name T2285
Test name
Test status
Simulation time 72857792 ps
CPU time 0.73 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:09 PM PDT 24
Peak memory 207276 kb
Host smart-1a82e1eb-53a8-429b-bcb2-30d226396c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19727
89650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1972789650
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3295145407
Short name T535
Test name
Test status
Simulation time 957557042 ps
CPU time 2.46 seconds
Started Aug 06 08:07:00 PM PDT 24
Finished Aug 06 08:07:02 PM PDT 24
Peak memory 207516 kb
Host smart-545872b9-0778-4457-908d-07e2750160b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32951
45407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3295145407
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_types.1208695904
Short name T353
Test name
Test status
Simulation time 477239379 ps
CPU time 1.49 seconds
Started Aug 06 08:07:15 PM PDT 24
Finished Aug 06 08:07:17 PM PDT 24
Peak memory 207212 kb
Host smart-184b9ab1-5f3f-42eb-9638-67673bb4c9d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1208695904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.1208695904
Directory /workspace/36.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.168560694
Short name T1143
Test name
Test status
Simulation time 268622311 ps
CPU time 1.5 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207504 kb
Host smart-2e2347c8-0529-43f3-b7ce-004d91f4ac50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16856
0694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.168560694
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.828026157
Short name T923
Test name
Test status
Simulation time 224143218 ps
CPU time 1.2 seconds
Started Aug 06 08:07:06 PM PDT 24
Finished Aug 06 08:07:07 PM PDT 24
Peak memory 215708 kb
Host smart-0d17f0e0-353e-4139-bbca-8bc7800a5b69
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=828026157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.828026157
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4278011342
Short name T2503
Test name
Test status
Simulation time 194036617 ps
CPU time 0.85 seconds
Started Aug 06 08:07:17 PM PDT 24
Finished Aug 06 08:07:18 PM PDT 24
Peak memory 207356 kb
Host smart-363be8ce-57d2-45b9-99e7-b9bbfe5e48b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42780
11342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4278011342
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.18025789
Short name T1840
Test name
Test status
Simulation time 173467788 ps
CPU time 0.9 seconds
Started Aug 06 08:07:08 PM PDT 24
Finished Aug 06 08:07:09 PM PDT 24
Peak memory 207380 kb
Host smart-8142a1d4-3939-4e47-8051-3e062a07f8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18025
789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.18025789
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.3969269220
Short name T1280
Test name
Test status
Simulation time 3334707891 ps
CPU time 93.89 seconds
Started Aug 06 08:07:15 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 217308 kb
Host smart-6866d003-8978-404e-869e-7d4a3b1bafb1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3969269220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.3969269220
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.3788064369
Short name T2455
Test name
Test status
Simulation time 207409180 ps
CPU time 0.95 seconds
Started Aug 06 08:07:17 PM PDT 24
Finished Aug 06 08:07:18 PM PDT 24
Peak memory 207368 kb
Host smart-0ab6472d-d54f-4bcb-b61f-4caa6edac68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37880
64369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.3788064369
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1824979378
Short name T931
Test name
Test status
Simulation time 27021841498 ps
CPU time 49.74 seconds
Started Aug 06 08:07:21 PM PDT 24
Finished Aug 06 08:08:11 PM PDT 24
Peak memory 207496 kb
Host smart-54bf4c1e-1219-46a2-a150-03ad49fac40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18249
79378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1824979378
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1895200401
Short name T1795
Test name
Test status
Simulation time 10978654258 ps
CPU time 13.28 seconds
Started Aug 06 08:07:06 PM PDT 24
Finished Aug 06 08:07:19 PM PDT 24
Peak memory 207576 kb
Host smart-4afcd0c6-8c3d-4e59-8440-ab2f87b449a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18952
00401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1895200401
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2268171858
Short name T2623
Test name
Test status
Simulation time 3387301601 ps
CPU time 33.67 seconds
Started Aug 06 08:06:58 PM PDT 24
Finished Aug 06 08:07:32 PM PDT 24
Peak memory 218252 kb
Host smart-67b2c34d-8520-494a-bb48-f7db056fe6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22681
71858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2268171858
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1769608358
Short name T2776
Test name
Test status
Simulation time 1639206864 ps
CPU time 16.19 seconds
Started Aug 06 08:07:15 PM PDT 24
Finished Aug 06 08:07:31 PM PDT 24
Peak memory 215652 kb
Host smart-5187dfbb-6a38-43c1-8196-69cb5bc6e345
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1769608358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1769608358
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2150050839
Short name T2893
Test name
Test status
Simulation time 254710173 ps
CPU time 1.05 seconds
Started Aug 06 08:07:02 PM PDT 24
Finished Aug 06 08:07:03 PM PDT 24
Peak memory 207356 kb
Host smart-c88ad28f-f244-4162-a319-f235c3bf84e3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2150050839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2150050839
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.831254798
Short name T2765
Test name
Test status
Simulation time 200865072 ps
CPU time 0.93 seconds
Started Aug 06 08:07:19 PM PDT 24
Finished Aug 06 08:07:20 PM PDT 24
Peak memory 207396 kb
Host smart-0903a098-80e5-4a23-9f94-bfe4ca2e99a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83125
4798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.831254798
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.977377553
Short name T1406
Test name
Test status
Simulation time 2660328689 ps
CPU time 19.05 seconds
Started Aug 06 08:07:14 PM PDT 24
Finished Aug 06 08:07:34 PM PDT 24
Peak memory 217572 kb
Host smart-1f875aac-132b-428d-9f9a-cc3d1435d91b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=977377553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.977377553
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.627361863
Short name T2691
Test name
Test status
Simulation time 162004675 ps
CPU time 0.87 seconds
Started Aug 06 08:07:13 PM PDT 24
Finished Aug 06 08:07:14 PM PDT 24
Peak memory 207356 kb
Host smart-fb6a8c70-175d-442e-85ab-107d0d52651c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=627361863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.627361863
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.706845360
Short name T1288
Test name
Test status
Simulation time 166146761 ps
CPU time 0.84 seconds
Started Aug 06 08:07:19 PM PDT 24
Finished Aug 06 08:07:20 PM PDT 24
Peak memory 207396 kb
Host smart-fd3be97f-f231-4f10-9c75-68957698e21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70684
5360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.706845360
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2917336823
Short name T2338
Test name
Test status
Simulation time 175092179 ps
CPU time 0.87 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207388 kb
Host smart-7c4ee620-867d-473b-a234-9aa21bd630f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29173
36823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2917336823
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.2070680758
Short name T1065
Test name
Test status
Simulation time 186796001 ps
CPU time 0.92 seconds
Started Aug 06 08:07:02 PM PDT 24
Finished Aug 06 08:07:03 PM PDT 24
Peak memory 207360 kb
Host smart-6ce5bb54-d0fe-411d-99e4-8b81d9d74814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20706
80758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.2070680758
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2408469163
Short name T2148
Test name
Test status
Simulation time 138655377 ps
CPU time 0.81 seconds
Started Aug 06 08:07:20 PM PDT 24
Finished Aug 06 08:07:20 PM PDT 24
Peak memory 207376 kb
Host smart-fc8122aa-ece8-4948-ad97-72e0c3011d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24084
69163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2408469163
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1631587312
Short name T2831
Test name
Test status
Simulation time 174923670 ps
CPU time 0.87 seconds
Started Aug 06 08:06:57 PM PDT 24
Finished Aug 06 08:06:58 PM PDT 24
Peak memory 207312 kb
Host smart-1aa5f1f4-9bfd-486f-9d77-5bd884ec3c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16315
87312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1631587312
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2040887662
Short name T2191
Test name
Test status
Simulation time 167692277 ps
CPU time 0.86 seconds
Started Aug 06 08:07:04 PM PDT 24
Finished Aug 06 08:07:05 PM PDT 24
Peak memory 207408 kb
Host smart-00982b35-1660-4fbd-b3bd-cb248319c902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20408
87662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2040887662
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1759639557
Short name T959
Test name
Test status
Simulation time 241743219 ps
CPU time 1.03 seconds
Started Aug 06 08:07:14 PM PDT 24
Finished Aug 06 08:07:16 PM PDT 24
Peak memory 207360 kb
Host smart-43ae0857-1b94-4cff-9ef2-700e534a4e31
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1759639557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1759639557
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3882770293
Short name T1952
Test name
Test status
Simulation time 149152033 ps
CPU time 0.85 seconds
Started Aug 06 08:07:15 PM PDT 24
Finished Aug 06 08:07:16 PM PDT 24
Peak memory 207352 kb
Host smart-cbb26e1f-5e79-4ade-bc55-2fc89dd19844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38827
70293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3882770293
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3639097135
Short name T1469
Test name
Test status
Simulation time 36839885 ps
CPU time 0.68 seconds
Started Aug 06 08:07:06 PM PDT 24
Finished Aug 06 08:07:07 PM PDT 24
Peak memory 207292 kb
Host smart-6c9f1a7f-0847-4434-b305-e6a0807a3eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36390
97135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3639097135
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2808463977
Short name T283
Test name
Test status
Simulation time 9895058650 ps
CPU time 25.95 seconds
Started Aug 06 08:07:14 PM PDT 24
Finished Aug 06 08:07:40 PM PDT 24
Peak memory 215944 kb
Host smart-a90bda8f-4cf6-435a-bff2-bcdbed773885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28084
63977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2808463977
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1703495374
Short name T692
Test name
Test status
Simulation time 175310763 ps
CPU time 0.97 seconds
Started Aug 06 08:07:16 PM PDT 24
Finished Aug 06 08:07:17 PM PDT 24
Peak memory 207360 kb
Host smart-aee9dfb9-47fc-4699-ae3e-1b4bc7f79c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17034
95374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1703495374
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2575853895
Short name T1909
Test name
Test status
Simulation time 245047172 ps
CPU time 0.96 seconds
Started Aug 06 08:07:12 PM PDT 24
Finished Aug 06 08:07:13 PM PDT 24
Peak memory 207412 kb
Host smart-526fa4ef-ed3c-4d8c-9da7-da3f5088d051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25758
53895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2575853895
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.25841547
Short name T2252
Test name
Test status
Simulation time 172472779 ps
CPU time 0.86 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:15 PM PDT 24
Peak memory 207288 kb
Host smart-d99c9c81-5857-4da3-88cd-2b2fa1328d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25841
547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.25841547
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.4087607452
Short name T2474
Test name
Test status
Simulation time 163667260 ps
CPU time 0.87 seconds
Started Aug 06 08:07:07 PM PDT 24
Finished Aug 06 08:07:08 PM PDT 24
Peak memory 207320 kb
Host smart-cc8b1ffb-8b5e-4cb1-8d7d-23ce3424e288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40876
07452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.4087607452
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.223555636
Short name T74
Test name
Test status
Simulation time 167410642 ps
CPU time 0.9 seconds
Started Aug 06 08:07:17 PM PDT 24
Finished Aug 06 08:07:18 PM PDT 24
Peak memory 207376 kb
Host smart-8ad48af4-c9ef-437a-ba09-2d95c4285f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22355
5636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.223555636
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_rx_full.3644156278
Short name T2199
Test name
Test status
Simulation time 340248117 ps
CPU time 1.2 seconds
Started Aug 06 08:07:19 PM PDT 24
Finished Aug 06 08:07:20 PM PDT 24
Peak memory 207356 kb
Host smart-a1c7d01f-672f-4604-b1bc-68478c4c7808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36441
56278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.3644156278
Directory /workspace/36.usbdev_rx_full/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1622774873
Short name T1359
Test name
Test status
Simulation time 154211266 ps
CPU time 0.88 seconds
Started Aug 06 08:07:14 PM PDT 24
Finished Aug 06 08:07:15 PM PDT 24
Peak memory 207324 kb
Host smart-2065faa3-96ee-4e9b-82b9-220660a6d71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16227
74873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1622774873
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2717341531
Short name T761
Test name
Test status
Simulation time 152616798 ps
CPU time 0.87 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207356 kb
Host smart-52ee414a-18a2-44a3-bbe3-6b415db386bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27173
41531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2717341531
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2635649056
Short name T847
Test name
Test status
Simulation time 200941643 ps
CPU time 1.01 seconds
Started Aug 06 08:07:23 PM PDT 24
Finished Aug 06 08:07:24 PM PDT 24
Peak memory 207400 kb
Host smart-512338c4-3b38-4721-9b4a-b4fe688a427a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26356
49056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2635649056
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.959538264
Short name T876
Test name
Test status
Simulation time 3656442802 ps
CPU time 26.69 seconds
Started Aug 06 08:07:17 PM PDT 24
Finished Aug 06 08:07:44 PM PDT 24
Peak memory 215884 kb
Host smart-4e35b57b-0f2f-4b66-af6b-8498ef3eba6b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=959538264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.959538264
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.679282487
Short name T1692
Test name
Test status
Simulation time 195186490 ps
CPU time 0.92 seconds
Started Aug 06 08:07:23 PM PDT 24
Finished Aug 06 08:07:24 PM PDT 24
Peak memory 207336 kb
Host smart-06540ac3-8b2d-4dab-9fab-4fd5f897243c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67928
2487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.679282487
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2679091953
Short name T2692
Test name
Test status
Simulation time 182923121 ps
CPU time 0.85 seconds
Started Aug 06 08:07:24 PM PDT 24
Finished Aug 06 08:07:24 PM PDT 24
Peak memory 207348 kb
Host smart-38fa7d41-fda3-47dc-aa2e-21623a65bb70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26790
91953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2679091953
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.1983910106
Short name T2208
Test name
Test status
Simulation time 392567805 ps
CPU time 1.36 seconds
Started Aug 06 08:07:25 PM PDT 24
Finished Aug 06 08:07:27 PM PDT 24
Peak memory 207316 kb
Host smart-03e0e767-62b5-4b99-901e-2d2013b38be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19839
10106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.1983910106
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1752397111
Short name T2800
Test name
Test status
Simulation time 3965781427 ps
CPU time 117.31 seconds
Started Aug 06 08:07:23 PM PDT 24
Finished Aug 06 08:09:21 PM PDT 24
Peak memory 217208 kb
Host smart-de4658c0-0573-4f27-b97b-ba322b178ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17523
97111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1752397111
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.2976895474
Short name T2364
Test name
Test status
Simulation time 3631990000 ps
CPU time 23.71 seconds
Started Aug 06 08:07:24 PM PDT 24
Finished Aug 06 08:07:48 PM PDT 24
Peak memory 207524 kb
Host smart-eb306208-e79a-446a-a613-eabff14a288c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976895474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.2976895474
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3628501992
Short name T1229
Test name
Test status
Simulation time 70816440 ps
CPU time 0.72 seconds
Started Aug 06 08:07:17 PM PDT 24
Finished Aug 06 08:07:17 PM PDT 24
Peak memory 207460 kb
Host smart-f987a2b0-91a1-4a0a-a080-3b79eb4b3056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3628501992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3628501992
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3463054828
Short name T1554
Test name
Test status
Simulation time 10102516690 ps
CPU time 14.22 seconds
Started Aug 06 08:07:26 PM PDT 24
Finished Aug 06 08:07:40 PM PDT 24
Peak memory 207604 kb
Host smart-5a7cf70c-0a00-40c1-97db-988a4e59756d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463054828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.3463054828
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3680625634
Short name T2858
Test name
Test status
Simulation time 21157123339 ps
CPU time 24.07 seconds
Started Aug 06 08:07:18 PM PDT 24
Finished Aug 06 08:07:42 PM PDT 24
Peak memory 207672 kb
Host smart-9cd0802e-6ef9-49f5-bfd1-ef0599f41ede
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680625634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3680625634
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2815505075
Short name T1734
Test name
Test status
Simulation time 24578728224 ps
CPU time 30.39 seconds
Started Aug 06 08:07:21 PM PDT 24
Finished Aug 06 08:07:52 PM PDT 24
Peak memory 215904 kb
Host smart-1a3664b3-1d81-404e-8ead-f19314f62ec1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815505075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_resume.2815505075
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2529334519
Short name T2580
Test name
Test status
Simulation time 146059250 ps
CPU time 0.84 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207372 kb
Host smart-e32ab506-7c69-4917-8110-647807bbac72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25293
34519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2529334519
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.4153692532
Short name T2670
Test name
Test status
Simulation time 152031171 ps
CPU time 0.82 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207320 kb
Host smart-da1e9ad1-295e-4175-968c-9e5b848b01aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41536
92532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.4153692532
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2379955627
Short name T2243
Test name
Test status
Simulation time 325855477 ps
CPU time 1.25 seconds
Started Aug 06 08:07:24 PM PDT 24
Finished Aug 06 08:07:25 PM PDT 24
Peak memory 207292 kb
Host smart-4995766f-16cf-4dbb-80cc-07e50119809a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23799
55627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2379955627
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2813526031
Short name T2080
Test name
Test status
Simulation time 444316653 ps
CPU time 1.41 seconds
Started Aug 06 08:07:20 PM PDT 24
Finished Aug 06 08:07:22 PM PDT 24
Peak memory 207332 kb
Host smart-17a4cdf9-0644-4510-840c-90ba3008cfd8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2813526031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2813526031
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.2671609638
Short name T206
Test name
Test status
Simulation time 45805254952 ps
CPU time 69.54 seconds
Started Aug 06 08:07:23 PM PDT 24
Finished Aug 06 08:08:33 PM PDT 24
Peak memory 207584 kb
Host smart-fa3b7547-0d14-4653-b667-4fdf04b51d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26716
09638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.2671609638
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.4272995803
Short name T1830
Test name
Test status
Simulation time 597052577 ps
CPU time 11.57 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:33 PM PDT 24
Peak memory 207476 kb
Host smart-4c451c9c-0f25-4116-812b-eb080f19d43f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272995803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.4272995803
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.1468044045
Short name T2274
Test name
Test status
Simulation time 1061857413 ps
CPU time 2.1 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:24 PM PDT 24
Peak memory 207288 kb
Host smart-47d18134-dfa4-4ed9-9fda-23c1afb347b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14680
44045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.1468044045
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1890779997
Short name T1349
Test name
Test status
Simulation time 164426160 ps
CPU time 0.84 seconds
Started Aug 06 08:07:23 PM PDT 24
Finished Aug 06 08:07:24 PM PDT 24
Peak memory 207340 kb
Host smart-e37bb76b-c77a-432e-b4bf-e253128e3dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18907
79997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1890779997
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.830669866
Short name T2019
Test name
Test status
Simulation time 85477683 ps
CPU time 0.72 seconds
Started Aug 06 08:07:17 PM PDT 24
Finished Aug 06 08:07:18 PM PDT 24
Peak memory 207376 kb
Host smart-e2297e65-b4cc-4144-b2a4-820d832b15c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83066
9866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.830669866
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.4146521094
Short name T2176
Test name
Test status
Simulation time 863305976 ps
CPU time 2.45 seconds
Started Aug 06 08:07:10 PM PDT 24
Finished Aug 06 08:07:13 PM PDT 24
Peak memory 207568 kb
Host smart-c544fbaf-b000-4e02-bbf4-15510a740e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41465
21094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.4146521094
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_types.469422100
Short name T2789
Test name
Test status
Simulation time 613321863 ps
CPU time 1.55 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207364 kb
Host smart-680d5c5c-abf3-42da-a168-73478ca2b432
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=469422100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.469422100
Directory /workspace/37.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1890976370
Short name T1260
Test name
Test status
Simulation time 203253700 ps
CPU time 1.43 seconds
Started Aug 06 08:07:21 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207476 kb
Host smart-e54e8333-5d2e-478b-93ad-d7e29804701e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18909
76370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1890976370
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3683125866
Short name T1505
Test name
Test status
Simulation time 169432817 ps
CPU time 0.96 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207320 kb
Host smart-5e39d30c-da56-41bf-be05-625267d50180
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3683125866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3683125866
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2677606648
Short name T1699
Test name
Test status
Simulation time 152950546 ps
CPU time 0.83 seconds
Started Aug 06 08:07:19 PM PDT 24
Finished Aug 06 08:07:20 PM PDT 24
Peak memory 207340 kb
Host smart-c1bd3222-13a7-460f-8fa9-97d5a57832fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26776
06648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2677606648
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1849748360
Short name T46
Test name
Test status
Simulation time 221612029 ps
CPU time 0.97 seconds
Started Aug 06 08:07:23 PM PDT 24
Finished Aug 06 08:07:24 PM PDT 24
Peak memory 207316 kb
Host smart-9971bef7-5732-441f-be20-07c35c7aa65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18497
48360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1849748360
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.851582094
Short name T2354
Test name
Test status
Simulation time 4296438333 ps
CPU time 121.36 seconds
Started Aug 06 08:07:17 PM PDT 24
Finished Aug 06 08:09:19 PM PDT 24
Peak memory 218124 kb
Host smart-960d5bf8-4bb5-4d3c-a97f-6366ceb3a6ff
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=851582094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.851582094
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.825785726
Short name T2543
Test name
Test status
Simulation time 10527737404 ps
CPU time 74.69 seconds
Started Aug 06 08:07:17 PM PDT 24
Finished Aug 06 08:08:32 PM PDT 24
Peak memory 207600 kb
Host smart-1da2f0b7-f6b6-4abe-8942-fb988935c271
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=825785726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.825785726
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3385751372
Short name T1595
Test name
Test status
Simulation time 200382135 ps
CPU time 0.91 seconds
Started Aug 06 08:07:12 PM PDT 24
Finished Aug 06 08:07:13 PM PDT 24
Peak memory 207320 kb
Host smart-7f375d77-f8ae-4bc1-af28-546f6aca0b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33857
51372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3385751372
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.4289722679
Short name T69
Test name
Test status
Simulation time 23842994540 ps
CPU time 33.2 seconds
Started Aug 06 08:07:21 PM PDT 24
Finished Aug 06 08:07:54 PM PDT 24
Peak memory 216052 kb
Host smart-280f5ce3-2891-4f97-9320-47deb059a571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42897
22679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.4289722679
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1502904078
Short name T910
Test name
Test status
Simulation time 8344283221 ps
CPU time 9.68 seconds
Started Aug 06 08:07:21 PM PDT 24
Finished Aug 06 08:07:31 PM PDT 24
Peak memory 207588 kb
Host smart-89b6e9dd-c727-46b7-87a7-15a6023ba02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15029
04078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1502904078
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.3778199769
Short name T1031
Test name
Test status
Simulation time 4522851880 ps
CPU time 33.39 seconds
Started Aug 06 08:07:24 PM PDT 24
Finished Aug 06 08:07:57 PM PDT 24
Peak memory 215956 kb
Host smart-a24f39fd-9669-4cc2-bab9-62094375075a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37781
99769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.3778199769
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3181387536
Short name T109
Test name
Test status
Simulation time 2853091328 ps
CPU time 27.52 seconds
Started Aug 06 08:07:25 PM PDT 24
Finished Aug 06 08:07:52 PM PDT 24
Peak memory 217536 kb
Host smart-a1651771-9b2c-4e90-910b-8d78ef05b65c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3181387536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3181387536
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.2361381943
Short name T2885
Test name
Test status
Simulation time 241653306 ps
CPU time 0.95 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207356 kb
Host smart-a7d68f87-06d5-47ae-8d07-a230129fb0bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2361381943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.2361381943
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1507555071
Short name T1833
Test name
Test status
Simulation time 228459082 ps
CPU time 0.99 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207392 kb
Host smart-6f5c5a58-b75a-4582-aee2-2b7add3b8c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15075
55071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1507555071
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1863025387
Short name T1640
Test name
Test status
Simulation time 2446374340 ps
CPU time 18.44 seconds
Started Aug 06 08:07:24 PM PDT 24
Finished Aug 06 08:07:42 PM PDT 24
Peak memory 207656 kb
Host smart-53eacc88-4022-4f86-8059-5589469ec927
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1863025387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1863025387
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.2108273234
Short name T853
Test name
Test status
Simulation time 172114480 ps
CPU time 0.9 seconds
Started Aug 06 08:07:09 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 207456 kb
Host smart-fb677aff-0596-426a-bc49-d9fa837ab714
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2108273234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.2108273234
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.525342349
Short name T1408
Test name
Test status
Simulation time 143697838 ps
CPU time 0.87 seconds
Started Aug 06 08:07:18 PM PDT 24
Finished Aug 06 08:07:19 PM PDT 24
Peak memory 207352 kb
Host smart-835a06a1-1eda-4752-a560-62097318cdbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52534
2349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.525342349
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.861095846
Short name T159
Test name
Test status
Simulation time 188319391 ps
CPU time 0.89 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:28 PM PDT 24
Peak memory 207376 kb
Host smart-0cdaad26-d1dc-4aa0-acbf-a3edfb1442e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86109
5846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.861095846
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3954348983
Short name T1609
Test name
Test status
Simulation time 193278728 ps
CPU time 0.91 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207372 kb
Host smart-f03529aa-afe5-408f-89a0-7f7670ee79ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39543
48983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3954348983
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.743135292
Short name T859
Test name
Test status
Simulation time 230353921 ps
CPU time 0.97 seconds
Started Aug 06 08:07:20 PM PDT 24
Finished Aug 06 08:07:21 PM PDT 24
Peak memory 207368 kb
Host smart-716d336d-fd55-4469-be38-2b46aaae854b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74313
5292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.743135292
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1626494314
Short name T691
Test name
Test status
Simulation time 163738026 ps
CPU time 0.82 seconds
Started Aug 06 08:07:23 PM PDT 24
Finished Aug 06 08:07:24 PM PDT 24
Peak memory 207400 kb
Host smart-717f6cc7-0735-425f-8a56-febb2b9e1e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16264
94314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1626494314
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.544239063
Short name T920
Test name
Test status
Simulation time 161589014 ps
CPU time 0.88 seconds
Started Aug 06 08:07:20 PM PDT 24
Finished Aug 06 08:07:21 PM PDT 24
Peak memory 207312 kb
Host smart-f9359943-1cde-415b-a881-f003edad9bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54423
9063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.544239063
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.510859561
Short name T2050
Test name
Test status
Simulation time 248011731 ps
CPU time 1.02 seconds
Started Aug 06 08:07:11 PM PDT 24
Finished Aug 06 08:07:13 PM PDT 24
Peak memory 207360 kb
Host smart-babc4d80-cc50-42b5-99e2-fb9d2efbc2b8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=510859561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.510859561
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3778795714
Short name T1091
Test name
Test status
Simulation time 143307965 ps
CPU time 0.8 seconds
Started Aug 06 08:07:20 PM PDT 24
Finished Aug 06 08:07:21 PM PDT 24
Peak memory 207340 kb
Host smart-6e3e12c3-5abb-45f1-99d3-876fdbdad480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37787
95714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3778795714
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.110995829
Short name T1912
Test name
Test status
Simulation time 45247142 ps
CPU time 0.69 seconds
Started Aug 06 08:07:21 PM PDT 24
Finished Aug 06 08:07:22 PM PDT 24
Peak memory 207316 kb
Host smart-fe522450-d690-4d1b-885a-f079fc59ba09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11099
5829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.110995829
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3980822369
Short name T2968
Test name
Test status
Simulation time 10848863481 ps
CPU time 29.29 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:51 PM PDT 24
Peak memory 215896 kb
Host smart-b13fca47-1154-46e9-a7f4-cdfc89247444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39808
22369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3980822369
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.4138104899
Short name T2289
Test name
Test status
Simulation time 198951059 ps
CPU time 0.97 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207372 kb
Host smart-c2276088-a5e5-46ec-8be0-7606c9c2d9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41381
04899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.4138104899
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2070501875
Short name T1238
Test name
Test status
Simulation time 260063221 ps
CPU time 0.97 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207372 kb
Host smart-c6eb1f1a-cee5-4b22-bb6d-22c45230e3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20705
01875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2070501875
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1812361763
Short name T682
Test name
Test status
Simulation time 216532237 ps
CPU time 0.94 seconds
Started Aug 06 08:07:16 PM PDT 24
Finished Aug 06 08:07:17 PM PDT 24
Peak memory 207356 kb
Host smart-285070b4-60d3-4fc1-8a63-dbefed210b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18123
61763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1812361763
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2237630159
Short name T635
Test name
Test status
Simulation time 192114573 ps
CPU time 0.88 seconds
Started Aug 06 08:07:23 PM PDT 24
Finished Aug 06 08:07:24 PM PDT 24
Peak memory 207348 kb
Host smart-bc740699-1b58-4de5-b4ca-c3adb732911b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22376
30159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2237630159
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2062303189
Short name T75
Test name
Test status
Simulation time 170733710 ps
CPU time 0.87 seconds
Started Aug 06 08:07:14 PM PDT 24
Finished Aug 06 08:07:15 PM PDT 24
Peak memory 207292 kb
Host smart-7ce004b2-7edf-47fa-88e9-22faa012f244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20623
03189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2062303189
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_rx_full.739635386
Short name T2296
Test name
Test status
Simulation time 289626281 ps
CPU time 1.11 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:24 PM PDT 24
Peak memory 207376 kb
Host smart-0a8293f0-7a01-4ad8-bc9a-a5043d99c265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73963
5386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.739635386
Directory /workspace/37.usbdev_rx_full/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3677861904
Short name T1829
Test name
Test status
Simulation time 182172206 ps
CPU time 0.83 seconds
Started Aug 06 08:07:18 PM PDT 24
Finished Aug 06 08:07:18 PM PDT 24
Peak memory 207368 kb
Host smart-45eb2634-4789-4dc5-82a1-53a2ba81b4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36778
61904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3677861904
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2977764114
Short name T2139
Test name
Test status
Simulation time 160244215 ps
CPU time 0.86 seconds
Started Aug 06 08:07:20 PM PDT 24
Finished Aug 06 08:07:21 PM PDT 24
Peak memory 207400 kb
Host smart-a3301c90-1e79-440c-8bbd-2e51170b3db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29777
64114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2977764114
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3566544665
Short name T819
Test name
Test status
Simulation time 268168991 ps
CPU time 1.09 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:28 PM PDT 24
Peak memory 207356 kb
Host smart-6c38b79e-f815-4490-9296-c0d336ab491f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35665
44665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3566544665
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.491631291
Short name T2980
Test name
Test status
Simulation time 2185506798 ps
CPU time 59.71 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:08:27 PM PDT 24
Peak memory 217468 kb
Host smart-575a1d56-44ac-47e3-bc00-5a931bd8a9f1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=491631291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.491631291
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1575112785
Short name T2131
Test name
Test status
Simulation time 157826002 ps
CPU time 0.86 seconds
Started Aug 06 08:07:10 PM PDT 24
Finished Aug 06 08:07:11 PM PDT 24
Peak memory 207360 kb
Host smart-d776bff0-ce10-4d9e-81e9-9c91795cf652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15751
12785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1575112785
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.4070593484
Short name T481
Test name
Test status
Simulation time 159379419 ps
CPU time 0.86 seconds
Started Aug 06 08:07:23 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207332 kb
Host smart-7f4e15e9-435b-4582-ba45-a3ce7fa19694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40705
93484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.4070593484
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.4218993340
Short name T2961
Test name
Test status
Simulation time 1385569622 ps
CPU time 3.13 seconds
Started Aug 06 08:07:20 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207520 kb
Host smart-8eb494d4-4a70-4558-9189-b4c42e2c19c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42189
93340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.4218993340
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3993465331
Short name T1957
Test name
Test status
Simulation time 2975834561 ps
CPU time 81.49 seconds
Started Aug 06 08:07:24 PM PDT 24
Finished Aug 06 08:08:45 PM PDT 24
Peak memory 223932 kb
Host smart-534a989d-b813-4642-8280-404b888e80d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39934
65331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3993465331
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.3384317045
Short name T1205
Test name
Test status
Simulation time 2434373266 ps
CPU time 22.38 seconds
Started Aug 06 08:07:20 PM PDT 24
Finished Aug 06 08:07:43 PM PDT 24
Peak memory 207648 kb
Host smart-b4d72e8f-80b2-44ab-bd06-452647cf0108
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384317045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.3384317045
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.3693826594
Short name T989
Test name
Test status
Simulation time 92054226 ps
CPU time 0.74 seconds
Started Aug 06 08:07:31 PM PDT 24
Finished Aug 06 08:07:32 PM PDT 24
Peak memory 207460 kb
Host smart-a8198394-08db-4fed-a623-92e1f1404dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3693826594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.3693826594
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.825278475
Short name T1470
Test name
Test status
Simulation time 9468195590 ps
CPU time 11.75 seconds
Started Aug 06 08:07:21 PM PDT 24
Finished Aug 06 08:07:33 PM PDT 24
Peak memory 207608 kb
Host smart-eba7b23b-5c52-4d82-952b-fdbae4fef93b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825278475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ao
n_wake_disconnect.825278475
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1043369879
Short name T2508
Test name
Test status
Simulation time 20542131129 ps
CPU time 21.57 seconds
Started Aug 06 08:07:16 PM PDT 24
Finished Aug 06 08:07:38 PM PDT 24
Peak memory 207676 kb
Host smart-af741992-7da9-4046-80f9-326aca1e0bb7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043369879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1043369879
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1960251342
Short name T772
Test name
Test status
Simulation time 29504197705 ps
CPU time 35.23 seconds
Started Aug 06 08:07:24 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207700 kb
Host smart-164182c5-384c-428c-a534-e24ff44da418
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960251342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_resume.1960251342
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3815801103
Short name T2542
Test name
Test status
Simulation time 153856795 ps
CPU time 0.83 seconds
Started Aug 06 08:07:15 PM PDT 24
Finished Aug 06 08:07:16 PM PDT 24
Peak memory 207380 kb
Host smart-c3434916-cab4-42da-96bd-f4a25eab9f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38158
01103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3815801103
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2848593437
Short name T2273
Test name
Test status
Simulation time 146757537 ps
CPU time 0.82 seconds
Started Aug 06 08:07:22 PM PDT 24
Finished Aug 06 08:07:23 PM PDT 24
Peak memory 207320 kb
Host smart-172621ef-86ae-41e0-94f5-7bafa7feb59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28485
93437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2848593437
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2168342568
Short name T2762
Test name
Test status
Simulation time 475126831 ps
CPU time 1.51 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:30 PM PDT 24
Peak memory 207404 kb
Host smart-166c6b12-f69d-4e6e-a5d2-df04b869435d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21683
42568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2168342568
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1364495780
Short name T2979
Test name
Test status
Simulation time 527903193 ps
CPU time 1.75 seconds
Started Aug 06 08:07:32 PM PDT 24
Finished Aug 06 08:07:34 PM PDT 24
Peak memory 207404 kb
Host smart-03563963-34f7-4c1b-a119-0084cdd5cf5b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1364495780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1364495780
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.4010796051
Short name T2125
Test name
Test status
Simulation time 29312233879 ps
CPU time 45.82 seconds
Started Aug 06 08:07:26 PM PDT 24
Finished Aug 06 08:08:12 PM PDT 24
Peak memory 207756 kb
Host smart-b76cc163-1878-4eea-95ac-4527c77f2d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40107
96051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.4010796051
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.2100575263
Short name T1178
Test name
Test status
Simulation time 730250763 ps
CPU time 14.68 seconds
Started Aug 06 08:07:26 PM PDT 24
Finished Aug 06 08:07:41 PM PDT 24
Peak memory 207552 kb
Host smart-f171f240-3c16-4460-8d03-d1f7e4724882
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100575263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.2100575263
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2145283099
Short name T1713
Test name
Test status
Simulation time 1167743189 ps
CPU time 2.67 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:31 PM PDT 24
Peak memory 207380 kb
Host smart-99696892-53d9-4a16-89d4-cd0489e8e23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21452
83099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2145283099
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3609787942
Short name T1556
Test name
Test status
Simulation time 140115777 ps
CPU time 0.8 seconds
Started Aug 06 08:07:34 PM PDT 24
Finished Aug 06 08:07:35 PM PDT 24
Peak memory 207288 kb
Host smart-9aef27d7-49a5-4040-8bef-574502cdef50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36097
87942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3609787942
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.311894956
Short name T2586
Test name
Test status
Simulation time 33282019 ps
CPU time 0.72 seconds
Started Aug 06 08:07:29 PM PDT 24
Finished Aug 06 08:07:30 PM PDT 24
Peak memory 207252 kb
Host smart-386c0ca0-126e-48b2-8df8-0d3021fe3fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31189
4956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.311894956
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2463460085
Short name T1049
Test name
Test status
Simulation time 994165210 ps
CPU time 2.37 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207632 kb
Host smart-0769cb82-0294-486e-80e3-a8e396126f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24634
60085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2463460085
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_types.1708756718
Short name T386
Test name
Test status
Simulation time 630946362 ps
CPU time 1.62 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:30 PM PDT 24
Peak memory 207368 kb
Host smart-9f04907e-2c45-45c5-a744-1652a69ee05a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1708756718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.1708756718
Directory /workspace/38.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1631721900
Short name T3054
Test name
Test status
Simulation time 224630108 ps
CPU time 2.42 seconds
Started Aug 06 08:07:44 PM PDT 24
Finished Aug 06 08:07:47 PM PDT 24
Peak memory 207592 kb
Host smart-7c4953dd-8aef-4927-b3e3-3790529828d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16317
21900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1631721900
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3178267722
Short name T2206
Test name
Test status
Simulation time 243394675 ps
CPU time 1.22 seconds
Started Aug 06 08:07:31 PM PDT 24
Finished Aug 06 08:07:32 PM PDT 24
Peak memory 215688 kb
Host smart-dac1bde2-12e5-4933-98ea-a7540e785df0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3178267722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3178267722
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1499244530
Short name T1634
Test name
Test status
Simulation time 184442800 ps
CPU time 0.84 seconds
Started Aug 06 08:07:45 PM PDT 24
Finished Aug 06 08:07:46 PM PDT 24
Peak memory 207320 kb
Host smart-7cbcb3e5-e701-47f6-944b-ef1c94f35cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14992
44530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1499244530
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3018070317
Short name T715
Test name
Test status
Simulation time 213210916 ps
CPU time 0.94 seconds
Started Aug 06 08:07:26 PM PDT 24
Finished Aug 06 08:07:27 PM PDT 24
Peak memory 207396 kb
Host smart-fbb20dec-9d7c-45b7-946b-ec2f4a77be71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30180
70317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3018070317
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.1050599444
Short name T2984
Test name
Test status
Simulation time 4817372975 ps
CPU time 35.62 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:08:02 PM PDT 24
Peak memory 215884 kb
Host smart-8fc12df3-b73b-44c7-abd9-5c14d3413e9c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1050599444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.1050599444
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.401179829
Short name T903
Test name
Test status
Simulation time 12147158231 ps
CPU time 149.77 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:09:58 PM PDT 24
Peak memory 207676 kb
Host smart-77e77122-138b-432e-a8a6-987c69a5a446
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=401179829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.401179829
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3113983043
Short name T2459
Test name
Test status
Simulation time 204407815 ps
CPU time 0.9 seconds
Started Aug 06 08:07:24 PM PDT 24
Finished Aug 06 08:07:25 PM PDT 24
Peak memory 207288 kb
Host smart-9ca1df2c-7fbf-49c5-be8f-42b4919b58e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31139
83043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3113983043
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.3066691459
Short name T2109
Test name
Test status
Simulation time 7616718065 ps
CPU time 9.92 seconds
Started Aug 06 08:07:21 PM PDT 24
Finished Aug 06 08:07:31 PM PDT 24
Peak memory 215784 kb
Host smart-40750e31-436f-4fe1-86b3-7ba681b634d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30666
91459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.3066691459
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2958186872
Short name T2510
Test name
Test status
Simulation time 6009721354 ps
CPU time 7.92 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:36 PM PDT 24
Peak memory 215956 kb
Host smart-4a2e03cd-dec6-4170-9787-250e5f51941e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29581
86872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2958186872
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1554699044
Short name T1597
Test name
Test status
Simulation time 4022107090 ps
CPU time 30.28 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:58 PM PDT 24
Peak memory 217348 kb
Host smart-4d3de125-c88c-4a70-ad58-f63f3409c123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15546
99044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1554699044
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2915576915
Short name T182
Test name
Test status
Simulation time 1680372599 ps
CPU time 47.34 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:08:16 PM PDT 24
Peak memory 215808 kb
Host smart-49fcb048-01b7-40d1-8553-ba52e20de7c9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2915576915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2915576915
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.2453961110
Short name T983
Test name
Test status
Simulation time 254641024 ps
CPU time 1.12 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:28 PM PDT 24
Peak memory 207380 kb
Host smart-9c16495b-7e9d-46c2-a26e-761a4fe7eeab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2453961110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.2453961110
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3765594053
Short name T2710
Test name
Test status
Simulation time 200435028 ps
CPU time 0.93 seconds
Started Aug 06 08:07:33 PM PDT 24
Finished Aug 06 08:07:34 PM PDT 24
Peak memory 207452 kb
Host smart-0d78e398-d3d8-4c0c-b253-2fa6df9c795c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37655
94053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3765594053
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.3443720802
Short name T542
Test name
Test status
Simulation time 3185445503 ps
CPU time 31.18 seconds
Started Aug 06 08:07:35 PM PDT 24
Finished Aug 06 08:08:06 PM PDT 24
Peak memory 217348 kb
Host smart-17d28dfd-c983-402d-8ffc-23bd392e9ca2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3443720802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.3443720802
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.3984099901
Short name T2813
Test name
Test status
Simulation time 182614120 ps
CPU time 0.93 seconds
Started Aug 06 08:07:26 PM PDT 24
Finished Aug 06 08:07:27 PM PDT 24
Peak memory 207200 kb
Host smart-5947e9e1-745f-45eb-ac4f-37a437c5a5f4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3984099901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3984099901
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2776754065
Short name T1682
Test name
Test status
Simulation time 186042151 ps
CPU time 0.82 seconds
Started Aug 06 08:07:26 PM PDT 24
Finished Aug 06 08:07:26 PM PDT 24
Peak memory 207296 kb
Host smart-ce8f24a7-4d1e-4393-a220-c7248cb008f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27767
54065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2776754065
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.4265441549
Short name T1779
Test name
Test status
Simulation time 195390870 ps
CPU time 0.9 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207420 kb
Host smart-d802b5ee-6c72-4062-ab37-389fa9c123be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42654
41549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.4265441549
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1427661702
Short name T671
Test name
Test status
Simulation time 179915249 ps
CPU time 0.92 seconds
Started Aug 06 08:07:26 PM PDT 24
Finished Aug 06 08:07:32 PM PDT 24
Peak memory 207440 kb
Host smart-99a146aa-400d-445a-84be-8bccb2fe855d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14276
61702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1427661702
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1830010117
Short name T698
Test name
Test status
Simulation time 211060562 ps
CPU time 0.97 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:30 PM PDT 24
Peak memory 207452 kb
Host smart-0f71ffb5-4e1b-4847-87a9-aee2abd4d40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18300
10117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1830010117
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1892362541
Short name T1412
Test name
Test status
Simulation time 155297722 ps
CPU time 0.84 seconds
Started Aug 06 08:07:37 PM PDT 24
Finished Aug 06 08:07:38 PM PDT 24
Peak memory 207396 kb
Host smart-c415e7a1-04b4-4aa1-b0d4-a4916f80f9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18923
62541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1892362541
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2432767413
Short name T695
Test name
Test status
Simulation time 226450886 ps
CPU time 1.01 seconds
Started Aug 06 08:07:25 PM PDT 24
Finished Aug 06 08:07:26 PM PDT 24
Peak memory 207356 kb
Host smart-e5339e17-a186-4bd8-9ed9-f2f43ccb75a2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2432767413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2432767413
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.127076303
Short name T1768
Test name
Test status
Simulation time 199458468 ps
CPU time 0.91 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:28 PM PDT 24
Peak memory 207372 kb
Host smart-064cf506-e442-4e56-b271-12cda5e4dc74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12707
6303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.127076303
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.902281848
Short name T1710
Test name
Test status
Simulation time 62570199 ps
CPU time 0.71 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:28 PM PDT 24
Peak memory 207368 kb
Host smart-46f9bea8-e74b-4359-9fa0-d7919e6ec384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90228
1848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.902281848
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.3251196320
Short name T1757
Test name
Test status
Simulation time 17208282571 ps
CPU time 47.51 seconds
Started Aug 06 08:07:52 PM PDT 24
Finished Aug 06 08:08:40 PM PDT 24
Peak memory 215856 kb
Host smart-b4793bc9-6593-4882-b65c-4440176f12a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32511
96320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.3251196320
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2991150944
Short name T2027
Test name
Test status
Simulation time 179660683 ps
CPU time 0.93 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:34 PM PDT 24
Peak memory 207356 kb
Host smart-cf1ffd6e-e41e-47e4-bedf-fc5bf4edc09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29911
50944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2991150944
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1188340715
Short name T2419
Test name
Test status
Simulation time 236479500 ps
CPU time 1.02 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:28 PM PDT 24
Peak memory 207304 kb
Host smart-dd5c66ef-3b74-427b-8fa1-8fcbe467f7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11883
40715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1188340715
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.1234411569
Short name T1319
Test name
Test status
Simulation time 190258712 ps
CPU time 0.94 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207448 kb
Host smart-eabd71f0-eaec-4073-a5bd-0aff7a68c375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12344
11569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.1234411569
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1112796678
Short name T2247
Test name
Test status
Simulation time 192075147 ps
CPU time 0.91 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207320 kb
Host smart-fb7857c6-f284-4271-841e-4827dd940c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11127
96678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1112796678
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1612941998
Short name T1800
Test name
Test status
Simulation time 143063807 ps
CPU time 0.84 seconds
Started Aug 06 08:07:34 PM PDT 24
Finished Aug 06 08:07:35 PM PDT 24
Peak memory 207344 kb
Host smart-80468fb4-355f-43b0-b0b6-806df30f9502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16129
41998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1612941998
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_rx_full.3467060742
Short name T2280
Test name
Test status
Simulation time 260564026 ps
CPU time 1.05 seconds
Started Aug 06 08:07:26 PM PDT 24
Finished Aug 06 08:07:27 PM PDT 24
Peak memory 207376 kb
Host smart-3d6e8894-8668-4e38-a7e5-4b98fb7febd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34670
60742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.3467060742
Directory /workspace/38.usbdev_rx_full/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2273588686
Short name T1272
Test name
Test status
Simulation time 179720074 ps
CPU time 0.84 seconds
Started Aug 06 08:07:35 PM PDT 24
Finished Aug 06 08:07:35 PM PDT 24
Peak memory 207324 kb
Host smart-5febb360-0fd7-42c0-82de-535845eb9a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22735
88686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2273588686
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2747312650
Short name T902
Test name
Test status
Simulation time 164041678 ps
CPU time 0.81 seconds
Started Aug 06 08:07:29 PM PDT 24
Finished Aug 06 08:07:30 PM PDT 24
Peak memory 207356 kb
Host smart-7a96bb61-9b23-4362-bd88-a7c3507ba83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27473
12650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2747312650
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1203172071
Short name T711
Test name
Test status
Simulation time 235342920 ps
CPU time 1.01 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207356 kb
Host smart-a3c01db3-9302-4c14-a54e-3f7f3991fc69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12031
72071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1203172071
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.4015038968
Short name T1571
Test name
Test status
Simulation time 2363839763 ps
CPU time 23.61 seconds
Started Aug 06 08:07:24 PM PDT 24
Finished Aug 06 08:07:47 PM PDT 24
Peak memory 217836 kb
Host smart-c1a789aa-2527-4b31-97f2-21dcbfbae3fb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4015038968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.4015038968
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1176453902
Short name T1702
Test name
Test status
Simulation time 150110033 ps
CPU time 0.82 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:28 PM PDT 24
Peak memory 207356 kb
Host smart-ffa4b368-c41c-4f74-8781-d3c8ecdeccf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11764
53902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1176453902
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3110621687
Short name T515
Test name
Test status
Simulation time 164372781 ps
CPU time 0.86 seconds
Started Aug 06 08:07:29 PM PDT 24
Finished Aug 06 08:07:30 PM PDT 24
Peak memory 207372 kb
Host smart-85618512-6a6e-47fe-9dc0-a49420afb175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31106
21687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3110621687
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.3773737992
Short name T906
Test name
Test status
Simulation time 1089032582 ps
CPU time 2.61 seconds
Started Aug 06 08:07:29 PM PDT 24
Finished Aug 06 08:07:32 PM PDT 24
Peak memory 207508 kb
Host smart-2b094341-8359-4303-9ce3-74591bb0db29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37737
37992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.3773737992
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.3732280085
Short name T1802
Test name
Test status
Simulation time 2050945110 ps
CPU time 20.37 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:48 PM PDT 24
Peak memory 217140 kb
Host smart-cdfe4a0e-86a0-4254-bb9a-979ba4742799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37322
80085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3732280085
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.1423615544
Short name T1000
Test name
Test status
Simulation time 1148881323 ps
CPU time 26.82 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:54 PM PDT 24
Peak memory 207592 kb
Host smart-2f170d44-c60a-4eaf-8d20-9bb00fd1b769
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423615544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.1423615544
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.4165076543
Short name T1192
Test name
Test status
Simulation time 84057366 ps
CPU time 0.78 seconds
Started Aug 06 08:07:52 PM PDT 24
Finished Aug 06 08:07:53 PM PDT 24
Peak memory 207504 kb
Host smart-c038dd93-353e-4323-813d-b14fc15e616a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4165076543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.4165076543
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1422248624
Short name T2977
Test name
Test status
Simulation time 5114165271 ps
CPU time 6.6 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:34 PM PDT 24
Peak memory 215788 kb
Host smart-7ca8a375-4b2b-4940-8bc0-09e80dc2f4fd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422248624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.1422248624
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.173084592
Short name T1574
Test name
Test status
Simulation time 16177659961 ps
CPU time 22.4 seconds
Started Aug 06 08:07:34 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 215884 kb
Host smart-587f25ed-265a-4a27-afb2-4276620ee650
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=173084592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.173084592
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1281597825
Short name T2376
Test name
Test status
Simulation time 24770760014 ps
CPU time 35.74 seconds
Started Aug 06 08:07:31 PM PDT 24
Finished Aug 06 08:08:07 PM PDT 24
Peak memory 215848 kb
Host smart-8dfb0f39-6382-4265-bc4a-dd1ef44d0382
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281597825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.1281597825
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1389555515
Short name T2329
Test name
Test status
Simulation time 166032154 ps
CPU time 0.93 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207400 kb
Host smart-8e2f5f1e-4f40-482a-b4fa-41bf483a5d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13895
55515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1389555515
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.871242221
Short name T3009
Test name
Test status
Simulation time 147958208 ps
CPU time 0.88 seconds
Started Aug 06 08:07:34 PM PDT 24
Finished Aug 06 08:07:35 PM PDT 24
Peak memory 207364 kb
Host smart-074b490f-f9bd-400e-9b74-be7cd429ab28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87124
2221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.871242221
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.3972501692
Short name T619
Test name
Test status
Simulation time 305003203 ps
CPU time 1.14 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207600 kb
Host smart-e9754fab-6b71-4504-aa66-8c6e641b0227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725
01692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.3972501692
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.520394452
Short name T2826
Test name
Test status
Simulation time 675474275 ps
CPU time 1.91 seconds
Started Aug 06 08:07:38 PM PDT 24
Finished Aug 06 08:07:40 PM PDT 24
Peak memory 207364 kb
Host smart-5764f96a-bfb7-474b-85ef-29301bed07c0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=520394452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.520394452
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.610771756
Short name T2204
Test name
Test status
Simulation time 51103157145 ps
CPU time 78.85 seconds
Started Aug 06 08:07:30 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 207692 kb
Host smart-ea970122-5b14-48cd-b82b-7149d0646418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61077
1756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.610771756
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.2779216194
Short name T2460
Test name
Test status
Simulation time 271927328 ps
CPU time 4.41 seconds
Started Aug 06 08:07:32 PM PDT 24
Finished Aug 06 08:07:36 PM PDT 24
Peak memory 207604 kb
Host smart-179b05e3-7513-47f9-80fc-7c437198d815
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779216194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.2779216194
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.3742142862
Short name T1457
Test name
Test status
Simulation time 728767128 ps
CPU time 1.7 seconds
Started Aug 06 08:07:36 PM PDT 24
Finished Aug 06 08:07:38 PM PDT 24
Peak memory 207384 kb
Host smart-2e72f6b1-1fda-4ef6-84dd-bac0786c64c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37421
42862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.3742142862
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2448837105
Short name T2895
Test name
Test status
Simulation time 158830778 ps
CPU time 0.88 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207348 kb
Host smart-e7aeb683-8c0e-4326-af85-7d14b5546769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24488
37105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2448837105
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.2921178640
Short name T272
Test name
Test status
Simulation time 48319767 ps
CPU time 0.69 seconds
Started Aug 06 08:07:25 PM PDT 24
Finished Aug 06 08:07:26 PM PDT 24
Peak memory 207580 kb
Host smart-47634894-7e3e-474c-a207-002099f204c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29211
78640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2921178640
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.3979157262
Short name T773
Test name
Test status
Simulation time 746293945 ps
CPU time 1.96 seconds
Started Aug 06 08:07:36 PM PDT 24
Finished Aug 06 08:07:38 PM PDT 24
Peak memory 207652 kb
Host smart-018b349d-f7e5-4dc4-b0e1-804330845a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39791
57262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.3979157262
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2815734274
Short name T1294
Test name
Test status
Simulation time 182767183 ps
CPU time 2.42 seconds
Started Aug 06 08:07:57 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207444 kb
Host smart-f4b3e73b-322c-477d-8c0a-28eb1a8e665f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28157
34274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2815734274
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.919083921
Short name T3086
Test name
Test status
Simulation time 233614184 ps
CPU time 1.11 seconds
Started Aug 06 08:07:25 PM PDT 24
Finished Aug 06 08:07:26 PM PDT 24
Peak memory 215668 kb
Host smart-3f6f9af4-15a5-4e05-a62c-fcbed3a1bff3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=919083921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.919083921
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2778891694
Short name T1631
Test name
Test status
Simulation time 137364147 ps
CPU time 0.81 seconds
Started Aug 06 08:07:30 PM PDT 24
Finished Aug 06 08:07:31 PM PDT 24
Peak memory 207332 kb
Host smart-5c290dc5-256f-4b94-82a3-e874be65780a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27788
91694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2778891694
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.912427948
Short name T2848
Test name
Test status
Simulation time 210669770 ps
CPU time 0.98 seconds
Started Aug 06 08:07:25 PM PDT 24
Finished Aug 06 08:07:26 PM PDT 24
Peak memory 207292 kb
Host smart-392298e7-d1f1-44d9-9074-9bf8d52ad7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91242
7948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.912427948
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.2705019061
Short name T743
Test name
Test status
Simulation time 3558232436 ps
CPU time 103.58 seconds
Started Aug 06 08:07:46 PM PDT 24
Finished Aug 06 08:09:30 PM PDT 24
Peak memory 223952 kb
Host smart-d7d089a8-8086-44cf-aa8b-db3c6d6fff78
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2705019061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.2705019061
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.2058717284
Short name T1117
Test name
Test status
Simulation time 7649835619 ps
CPU time 55.76 seconds
Started Aug 06 08:07:46 PM PDT 24
Finished Aug 06 08:08:42 PM PDT 24
Peak memory 207652 kb
Host smart-3fada359-d640-49e4-8a26-edd9d1f17380
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2058717284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.2058717284
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.2336720860
Short name T2797
Test name
Test status
Simulation time 183967890 ps
CPU time 0.88 seconds
Started Aug 06 08:07:29 PM PDT 24
Finished Aug 06 08:07:30 PM PDT 24
Peak memory 207380 kb
Host smart-445c9c7b-f01e-4923-b894-104b96b23ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23367
20860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2336720860
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.3408756721
Short name T2736
Test name
Test status
Simulation time 24354336279 ps
CPU time 32.36 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:08:00 PM PDT 24
Peak memory 215800 kb
Host smart-5b3b70eb-f94d-4c00-b40c-ba08345ef1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
56721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.3408756721
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3651419360
Short name T675
Test name
Test status
Simulation time 3715465068 ps
CPU time 5.41 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:34 PM PDT 24
Peak memory 215752 kb
Host smart-db76db14-f767-4a07-9fbb-463993b12465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36514
19360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3651419360
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2014293135
Short name T2730
Test name
Test status
Simulation time 3729252248 ps
CPU time 103.46 seconds
Started Aug 06 08:07:50 PM PDT 24
Finished Aug 06 08:09:34 PM PDT 24
Peak memory 215852 kb
Host smart-22424eed-68ba-4182-8ed7-f72874847394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20142
93135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2014293135
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.81972059
Short name T2768
Test name
Test status
Simulation time 3735471911 ps
CPU time 36.53 seconds
Started Aug 06 08:07:44 PM PDT 24
Finished Aug 06 08:08:21 PM PDT 24
Peak memory 215716 kb
Host smart-fccc7f6d-b7c1-4b03-8e91-fc9475dd9daa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=81972059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.81972059
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.3806123843
Short name T1054
Test name
Test status
Simulation time 277962047 ps
CPU time 1.02 seconds
Started Aug 06 08:07:44 PM PDT 24
Finished Aug 06 08:07:45 PM PDT 24
Peak memory 207232 kb
Host smart-1b440b89-d3fe-4190-bd56-c778f81aa125
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3806123843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3806123843
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2250530455
Short name T1003
Test name
Test status
Simulation time 191740778 ps
CPU time 0.93 seconds
Started Aug 06 08:07:54 PM PDT 24
Finished Aug 06 08:07:55 PM PDT 24
Peak memory 207256 kb
Host smart-ac8c581c-e908-4075-8812-80d575997090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22505
30455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2250530455
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3136060900
Short name T842
Test name
Test status
Simulation time 1783462233 ps
CPU time 13.21 seconds
Started Aug 06 08:07:27 PM PDT 24
Finished Aug 06 08:07:41 PM PDT 24
Peak memory 217320 kb
Host smart-e46b89aa-fe14-420b-8e34-7a23e789d028
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3136060900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3136060900
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.1133416822
Short name T518
Test name
Test status
Simulation time 148776539 ps
CPU time 0.83 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207232 kb
Host smart-a93acef6-44da-4fbe-9161-75bb15c5ad6b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1133416822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.1133416822
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.4113679642
Short name T2084
Test name
Test status
Simulation time 146324938 ps
CPU time 0.8 seconds
Started Aug 06 08:07:47 PM PDT 24
Finished Aug 06 08:07:47 PM PDT 24
Peak memory 207256 kb
Host smart-9dd2ddc7-9da9-41b3-88bd-fd3b29fcd4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41136
79642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.4113679642
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.364493889
Short name T1291
Test name
Test status
Simulation time 229492553 ps
CPU time 0.98 seconds
Started Aug 06 08:07:29 PM PDT 24
Finished Aug 06 08:07:30 PM PDT 24
Peak memory 207344 kb
Host smart-2d632924-0a53-4e19-99c0-92992194e06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36449
3889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.364493889
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2229978304
Short name T597
Test name
Test status
Simulation time 165607955 ps
CPU time 0.84 seconds
Started Aug 06 08:07:44 PM PDT 24
Finished Aug 06 08:07:45 PM PDT 24
Peak memory 207228 kb
Host smart-97a99d16-e30e-4a9d-a8b2-51d00b5d0763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22299
78304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2229978304
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3513484834
Short name T2641
Test name
Test status
Simulation time 160321556 ps
CPU time 0.82 seconds
Started Aug 06 08:07:57 PM PDT 24
Finished Aug 06 08:07:58 PM PDT 24
Peak memory 207248 kb
Host smart-79ca0f04-5fa3-4c47-9b52-a772edb4d0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35134
84834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3513484834
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1425461200
Short name T2912
Test name
Test status
Simulation time 156452394 ps
CPU time 0.82 seconds
Started Aug 06 08:07:28 PM PDT 24
Finished Aug 06 08:07:29 PM PDT 24
Peak memory 207340 kb
Host smart-d6cbd8f4-0360-4bd0-ae31-33ad40201916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14254
61200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1425461200
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2778110856
Short name T201
Test name
Test status
Simulation time 164805487 ps
CPU time 0.84 seconds
Started Aug 06 08:07:31 PM PDT 24
Finished Aug 06 08:07:32 PM PDT 24
Peak memory 207212 kb
Host smart-0e35ea20-adfd-439b-9996-8490afe8a34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27781
10856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2778110856
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3781354066
Short name T1869
Test name
Test status
Simulation time 203686575 ps
CPU time 0.98 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207232 kb
Host smart-72e18856-832d-4437-ac4b-6f2e68e856e9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3781354066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3781354066
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.944420577
Short name T862
Test name
Test status
Simulation time 211496954 ps
CPU time 0.92 seconds
Started Aug 06 08:07:44 PM PDT 24
Finished Aug 06 08:07:45 PM PDT 24
Peak memory 207416 kb
Host smart-f8929baa-1d32-4da8-9bc1-35bd4942e476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94442
0577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.944420577
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1047827570
Short name T1935
Test name
Test status
Simulation time 33922623 ps
CPU time 0.67 seconds
Started Aug 06 08:07:43 PM PDT 24
Finished Aug 06 08:07:43 PM PDT 24
Peak memory 207332 kb
Host smart-3fda9f4a-ab8a-48f1-b2b9-96df4b7f31a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10478
27570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1047827570
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3938196150
Short name T2350
Test name
Test status
Simulation time 17379806697 ps
CPU time 45.45 seconds
Started Aug 06 08:07:55 PM PDT 24
Finished Aug 06 08:08:40 PM PDT 24
Peak memory 215800 kb
Host smart-a285a8a9-d9f7-4067-919f-d3ed381bc004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39381
96150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3938196150
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2966054443
Short name T44
Test name
Test status
Simulation time 143544488 ps
CPU time 0.88 seconds
Started Aug 06 08:07:55 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 207348 kb
Host smart-fb2aade3-5d01-4e67-ad91-0dd7d388abf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29660
54443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2966054443
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.941994940
Short name T2180
Test name
Test status
Simulation time 270086819 ps
CPU time 1.02 seconds
Started Aug 06 08:07:54 PM PDT 24
Finished Aug 06 08:07:55 PM PDT 24
Peak memory 207388 kb
Host smart-66cd913a-57c3-4db1-bb72-1509df79b763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94199
4940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.941994940
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.2300015124
Short name T3012
Test name
Test status
Simulation time 168361912 ps
CPU time 0.96 seconds
Started Aug 06 08:07:54 PM PDT 24
Finished Aug 06 08:07:55 PM PDT 24
Peak memory 207340 kb
Host smart-d6d38345-f093-485f-a573-1bce1153311c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23000
15124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.2300015124
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.1822796744
Short name T2884
Test name
Test status
Simulation time 147832398 ps
CPU time 0.84 seconds
Started Aug 06 08:07:41 PM PDT 24
Finished Aug 06 08:07:42 PM PDT 24
Peak memory 207360 kb
Host smart-f67208bf-7033-44b4-84fa-1271f111db70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18227
96744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.1822796744
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.677526956
Short name T644
Test name
Test status
Simulation time 137223300 ps
CPU time 0.82 seconds
Started Aug 06 08:07:49 PM PDT 24
Finished Aug 06 08:07:49 PM PDT 24
Peak memory 207340 kb
Host smart-4cdc3905-80bb-4177-9096-c5c310b9390f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67752
6956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.677526956
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_rx_full.3558969389
Short name T1249
Test name
Test status
Simulation time 377494364 ps
CPU time 1.35 seconds
Started Aug 06 08:07:47 PM PDT 24
Finished Aug 06 08:07:49 PM PDT 24
Peak memory 207324 kb
Host smart-e9e14db0-50c9-4f04-944e-b049a7f562bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35589
69389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.3558969389
Directory /workspace/39.usbdev_rx_full/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1117103716
Short name T1979
Test name
Test status
Simulation time 194246925 ps
CPU time 0.87 seconds
Started Aug 06 08:07:45 PM PDT 24
Finished Aug 06 08:07:46 PM PDT 24
Peak memory 207324 kb
Host smart-bddd8144-742b-4b98-85b9-d15b1f0cf15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11171
03716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1117103716
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.103557387
Short name T1346
Test name
Test status
Simulation time 163896162 ps
CPU time 0.87 seconds
Started Aug 06 08:07:37 PM PDT 24
Finished Aug 06 08:07:38 PM PDT 24
Peak memory 207292 kb
Host smart-ad81af1b-f8e8-4515-972a-b2789cbd3595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10355
7387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.103557387
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.934101368
Short name T1662
Test name
Test status
Simulation time 235967495 ps
CPU time 0.98 seconds
Started Aug 06 08:07:44 PM PDT 24
Finished Aug 06 08:07:45 PM PDT 24
Peak memory 207396 kb
Host smart-aa2697f6-e30d-41e9-9e39-55f949bbd443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93410
1368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.934101368
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.1049983463
Short name T1484
Test name
Test status
Simulation time 3904167759 ps
CPU time 114.82 seconds
Started Aug 06 08:07:49 PM PDT 24
Finished Aug 06 08:09:43 PM PDT 24
Peak memory 223788 kb
Host smart-0a86dcd1-916a-4cf0-8a33-0f152960fed7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1049983463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.1049983463
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.963236703
Short name T2841
Test name
Test status
Simulation time 161875684 ps
CPU time 0.87 seconds
Started Aug 06 08:07:48 PM PDT 24
Finished Aug 06 08:07:49 PM PDT 24
Peak memory 207296 kb
Host smart-81d67c53-d3ae-4487-aa4a-94515524ae6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96323
6703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.963236703
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.46807480
Short name T3003
Test name
Test status
Simulation time 205081547 ps
CPU time 0.97 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207324 kb
Host smart-9e0a45cb-1a2b-4fd0-a4cd-3234dd5a4e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46807
480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.46807480
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3410479817
Short name T708
Test name
Test status
Simulation time 223907724 ps
CPU time 0.98 seconds
Started Aug 06 08:07:46 PM PDT 24
Finished Aug 06 08:07:47 PM PDT 24
Peak memory 207348 kb
Host smart-ec77c8bc-19d4-4a4f-b98f-4ed7bd8d1439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34104
79817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3410479817
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.64566069
Short name T480
Test name
Test status
Simulation time 1908976935 ps
CPU time 15.08 seconds
Started Aug 06 08:07:40 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 215724 kb
Host smart-0e18b6f5-e2da-471a-a8a0-8aeef88b42db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64566
069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.64566069
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.1531402664
Short name T2150
Test name
Test status
Simulation time 4408104433 ps
CPU time 28.82 seconds
Started Aug 06 08:07:34 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207760 kb
Host smart-3e52f0cb-1cdd-4dff-8c0a-6ec9b9564788
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531402664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.1531402664
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.270211103
Short name T873
Test name
Test status
Simulation time 41194393 ps
CPU time 0.67 seconds
Started Aug 06 08:02:15 PM PDT 24
Finished Aug 06 08:02:15 PM PDT 24
Peak memory 207396 kb
Host smart-f4c8ab10-2a64-4fbc-bc36-c34237488f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=270211103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.270211103
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.289078657
Short name T601
Test name
Test status
Simulation time 9419203244 ps
CPU time 12.38 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:11 PM PDT 24
Peak memory 207612 kb
Host smart-3a659a86-d509-4f97-9c0b-2681930465d1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289078657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon
_wake_disconnect.289078657
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.3617870574
Short name T2951
Test name
Test status
Simulation time 13848817174 ps
CPU time 17.68 seconds
Started Aug 06 08:02:00 PM PDT 24
Finished Aug 06 08:02:18 PM PDT 24
Peak memory 215776 kb
Host smart-59e2dd56-71d9-4f8b-b94a-663f4051e2be
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617870574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.3617870574
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.1352474768
Short name T604
Test name
Test status
Simulation time 31182653069 ps
CPU time 35.48 seconds
Started Aug 06 08:02:03 PM PDT 24
Finished Aug 06 08:02:38 PM PDT 24
Peak memory 207676 kb
Host smart-572be936-fe74-4a53-97a5-76353b59374c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352474768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.1352474768
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1099087543
Short name T1250
Test name
Test status
Simulation time 150661988 ps
CPU time 0.84 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:00 PM PDT 24
Peak memory 207372 kb
Host smart-e697506f-58ec-4703-a930-b7e10c6b8500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10990
87543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1099087543
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.2850450882
Short name T47
Test name
Test status
Simulation time 156875342 ps
CPU time 0.87 seconds
Started Aug 06 08:02:03 PM PDT 24
Finished Aug 06 08:02:04 PM PDT 24
Peak memory 207412 kb
Host smart-8c069129-dfd2-4110-8504-c7fbd17d9009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28504
50882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.2850450882
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2332790027
Short name T63
Test name
Test status
Simulation time 138996728 ps
CPU time 0.83 seconds
Started Aug 06 08:02:02 PM PDT 24
Finished Aug 06 08:02:03 PM PDT 24
Peak memory 207356 kb
Host smart-73ee8c7a-acc2-4fcc-b3da-8ff6e6a7b1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23327
90027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2332790027
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1661760205
Short name T2347
Test name
Test status
Simulation time 212002613 ps
CPU time 0.92 seconds
Started Aug 06 08:02:02 PM PDT 24
Finished Aug 06 08:02:03 PM PDT 24
Peak memory 207380 kb
Host smart-f0503682-028a-4661-b1ef-9cc9d6d9c084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16617
60205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1661760205
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2758206213
Short name T2346
Test name
Test status
Simulation time 548913836 ps
CPU time 1.7 seconds
Started Aug 06 08:02:00 PM PDT 24
Finished Aug 06 08:02:01 PM PDT 24
Peak memory 207376 kb
Host smart-eb4320a5-eae9-450b-ab80-9ddb553d6508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27582
06213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2758206213
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.3695643872
Short name T2431
Test name
Test status
Simulation time 784699280 ps
CPU time 2.15 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:02 PM PDT 24
Peak memory 207496 kb
Host smart-09452a46-e495-42e9-8940-de515494258b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3695643872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.3695643872
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.1372856640
Short name T2738
Test name
Test status
Simulation time 19307320885 ps
CPU time 32.57 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:02:30 PM PDT 24
Peak memory 207636 kb
Host smart-f04bd693-0bdf-484c-a689-01e955f8a27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13728
56640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1372856640
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.1907770695
Short name T567
Test name
Test status
Simulation time 491857153 ps
CPU time 7.85 seconds
Started Aug 06 08:02:02 PM PDT 24
Finished Aug 06 08:02:10 PM PDT 24
Peak memory 207604 kb
Host smart-9d7bcc1a-e98f-4523-a9c6-41661e2777b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907770695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.1907770695
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1440090929
Short name T888
Test name
Test status
Simulation time 745470219 ps
CPU time 1.68 seconds
Started Aug 06 08:02:03 PM PDT 24
Finished Aug 06 08:02:05 PM PDT 24
Peak memory 207232 kb
Host smart-5d47a9c0-38a9-456e-a946-99297065adc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14400
90929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1440090929
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3191193173
Short name T3079
Test name
Test status
Simulation time 176769961 ps
CPU time 0.86 seconds
Started Aug 06 08:02:02 PM PDT 24
Finished Aug 06 08:02:03 PM PDT 24
Peak memory 207204 kb
Host smart-f1d9e3bb-f36a-4e4d-b176-7e92404aae14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31911
93173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3191193173
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.184889950
Short name T510
Test name
Test status
Simulation time 41262213 ps
CPU time 0.68 seconds
Started Aug 06 08:01:57 PM PDT 24
Finished Aug 06 08:01:57 PM PDT 24
Peak memory 207312 kb
Host smart-1fc18421-d866-425a-8f67-bfb4b741c976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18488
9950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.184889950
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3981966795
Short name T785
Test name
Test status
Simulation time 928226209 ps
CPU time 2.61 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:02:00 PM PDT 24
Peak memory 207556 kb
Host smart-043e3535-8fab-48cd-b212-faeebf9b1e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39819
66795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3981966795
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_types.1127587305
Short name T464
Test name
Test status
Simulation time 187300106 ps
CPU time 0.88 seconds
Started Aug 06 08:01:58 PM PDT 24
Finished Aug 06 08:01:59 PM PDT 24
Peak memory 207224 kb
Host smart-3980c373-49eb-4490-8759-af52e6ae6c4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1127587305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.1127587305
Directory /workspace/4.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3307711519
Short name T2879
Test name
Test status
Simulation time 245037955 ps
CPU time 2.35 seconds
Started Aug 06 08:01:59 PM PDT 24
Finished Aug 06 08:02:01 PM PDT 24
Peak memory 207464 kb
Host smart-99b82661-b29c-4543-b563-2fa6a8532829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33077
11519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3307711519
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2456727375
Short name T1321
Test name
Test status
Simulation time 118197525669 ps
CPU time 169.08 seconds
Started Aug 06 08:02:00 PM PDT 24
Finished Aug 06 08:04:49 PM PDT 24
Peak memory 207660 kb
Host smart-bbde1673-6ba3-451c-ace7-4335d29bd8fa
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2456727375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2456727375
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.2635788371
Short name T1764
Test name
Test status
Simulation time 86160000570 ps
CPU time 133.24 seconds
Started Aug 06 08:02:02 PM PDT 24
Finished Aug 06 08:04:15 PM PDT 24
Peak memory 207576 kb
Host smart-15e9f857-a435-4218-8374-73e110fd0e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635788371 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.2635788371
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.3455628175
Short name T333
Test name
Test status
Simulation time 101117769213 ps
CPU time 168.24 seconds
Started Aug 06 08:02:03 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 207572 kb
Host smart-7ff898ae-c91b-4141-b08e-f0e71f868903
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3455628175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.3455628175
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.205242297
Short name T2041
Test name
Test status
Simulation time 106293240941 ps
CPU time 168.59 seconds
Started Aug 06 08:02:23 PM PDT 24
Finished Aug 06 08:05:12 PM PDT 24
Peak memory 207716 kb
Host smart-e28583b6-ddb2-4b03-b5a7-2870e8484387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205242297 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.205242297
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.4249024848
Short name T1112
Test name
Test status
Simulation time 110161405984 ps
CPU time 164.11 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:04:56 PM PDT 24
Peak memory 207648 kb
Host smart-937d6d76-36e4-41cd-8f54-cb9392f381fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42490
24848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.4249024848
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.4262408529
Short name T1678
Test name
Test status
Simulation time 244872152 ps
CPU time 1.09 seconds
Started Aug 06 08:02:10 PM PDT 24
Finished Aug 06 08:02:11 PM PDT 24
Peak memory 215708 kb
Host smart-7362a8e8-7f37-4ead-9554-2f6005224718
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4262408529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.4262408529
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.218358883
Short name T814
Test name
Test status
Simulation time 159673583 ps
CPU time 0.85 seconds
Started Aug 06 08:02:13 PM PDT 24
Finished Aug 06 08:02:14 PM PDT 24
Peak memory 207364 kb
Host smart-9e46e3fb-f117-48ef-a5f0-7e5d4af976e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21835
8883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.218358883
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1865269112
Short name T1721
Test name
Test status
Simulation time 239216847 ps
CPU time 1.01 seconds
Started Aug 06 08:02:14 PM PDT 24
Finished Aug 06 08:02:15 PM PDT 24
Peak memory 207372 kb
Host smart-dc56d8da-d373-4a98-ab28-433c6ba0f3eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18652
69112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1865269112
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.3565581948
Short name T1413
Test name
Test status
Simulation time 4919826528 ps
CPU time 36.98 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:02:49 PM PDT 24
Peak memory 215904 kb
Host smart-b1dda6c3-45fc-47db-8733-97aa883b48dc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3565581948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3565581948
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.3664724333
Short name T112
Test name
Test status
Simulation time 8735233297 ps
CPU time 64.26 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207612 kb
Host smart-98b5ea51-675d-405c-b972-31ac9e727be8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3664724333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.3664724333
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1794144992
Short name T935
Test name
Test status
Simulation time 182723227 ps
CPU time 0.93 seconds
Started Aug 06 08:02:21 PM PDT 24
Finished Aug 06 08:02:23 PM PDT 24
Peak memory 207444 kb
Host smart-8cc3d045-85be-470b-8914-c07c20ea7b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17941
44992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1794144992
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.1695655985
Short name T2062
Test name
Test status
Simulation time 10357042197 ps
CPU time 15.62 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:02:27 PM PDT 24
Peak memory 207688 kb
Host smart-5b15ead0-e092-4f34-92e1-9f4bd23881ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16956
55985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.1695655985
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3920201707
Short name T1327
Test name
Test status
Simulation time 11172944269 ps
CPU time 13.21 seconds
Started Aug 06 08:02:16 PM PDT 24
Finished Aug 06 08:02:30 PM PDT 24
Peak memory 207512 kb
Host smart-f87d22ae-909c-40cb-a490-f07daf719dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39202
01707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3920201707
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.1437122038
Short name T1973
Test name
Test status
Simulation time 4835979762 ps
CPU time 35.12 seconds
Started Aug 06 08:02:19 PM PDT 24
Finished Aug 06 08:02:54 PM PDT 24
Peak memory 224012 kb
Host smart-271a5298-5597-4469-88d4-3cc9858bc978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14371
22038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.1437122038
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.3624009345
Short name T966
Test name
Test status
Simulation time 2163352839 ps
CPU time 16.81 seconds
Started Aug 06 08:02:19 PM PDT 24
Finished Aug 06 08:02:36 PM PDT 24
Peak memory 217272 kb
Host smart-1fc1267f-6f0b-4a9f-a62a-89482e069c93
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3624009345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.3624009345
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.206068570
Short name T2271
Test name
Test status
Simulation time 240604572 ps
CPU time 1 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:02:13 PM PDT 24
Peak memory 207364 kb
Host smart-61417680-21bf-4898-9b8c-d0c7bffe76f9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=206068570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.206068570
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.354834975
Short name T503
Test name
Test status
Simulation time 203040577 ps
CPU time 1 seconds
Started Aug 06 08:02:20 PM PDT 24
Finished Aug 06 08:02:21 PM PDT 24
Peak memory 207344 kb
Host smart-90747f17-85c5-4292-a123-683f87b022ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35483
4975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.354834975
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.1629606578
Short name T170
Test name
Test status
Simulation time 2852583711 ps
CPU time 28.84 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:02:41 PM PDT 24
Peak memory 217508 kb
Host smart-565385b7-1cb8-46b5-9432-cd7a674a5f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16296
06578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.1629606578
Directory /workspace/4.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2566764750
Short name T683
Test name
Test status
Simulation time 4036367991 ps
CPU time 29.91 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:02:42 PM PDT 24
Peak memory 224040 kb
Host smart-1d7a535e-39e9-4560-8435-8d85ec92f7ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2566764750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2566764750
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3110386969
Short name T750
Test name
Test status
Simulation time 4017216958 ps
CPU time 118.64 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:04:11 PM PDT 24
Peak memory 217304 kb
Host smart-4c47b472-51ea-4ee6-b6cc-297b20a057ad
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3110386969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3110386969
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.2382483009
Short name T2854
Test name
Test status
Simulation time 174674323 ps
CPU time 0.93 seconds
Started Aug 06 08:02:21 PM PDT 24
Finished Aug 06 08:02:22 PM PDT 24
Peak memory 207444 kb
Host smart-1360a979-97c9-461f-96c5-017f97a5fbe9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2382483009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.2382483009
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3242607994
Short name T2795
Test name
Test status
Simulation time 163752770 ps
CPU time 0.83 seconds
Started Aug 06 08:02:10 PM PDT 24
Finished Aug 06 08:02:11 PM PDT 24
Peak memory 207344 kb
Host smart-487bb268-5a4d-465a-aa27-d8b1e5549cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32426
07994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3242607994
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1878223212
Short name T153
Test name
Test status
Simulation time 227261627 ps
CPU time 0.97 seconds
Started Aug 06 08:02:14 PM PDT 24
Finished Aug 06 08:02:15 PM PDT 24
Peak memory 207316 kb
Host smart-08e6fd8c-429e-4dd4-a0be-bfc119a2ae3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18782
23212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1878223212
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2900803998
Short name T2239
Test name
Test status
Simulation time 163426898 ps
CPU time 0.9 seconds
Started Aug 06 08:02:15 PM PDT 24
Finished Aug 06 08:02:16 PM PDT 24
Peak memory 207336 kb
Host smart-ac5d80c5-dcf6-44eb-905b-987f538ec0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29008
03998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2900803998
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2292668425
Short name T2481
Test name
Test status
Simulation time 213460868 ps
CPU time 0.91 seconds
Started Aug 06 08:02:20 PM PDT 24
Finished Aug 06 08:02:21 PM PDT 24
Peak memory 207444 kb
Host smart-b0d1e226-23c4-4f1e-a914-774d57449f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22926
68425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2292668425
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.4008988503
Short name T723
Test name
Test status
Simulation time 188102444 ps
CPU time 0.94 seconds
Started Aug 06 08:02:11 PM PDT 24
Finished Aug 06 08:02:12 PM PDT 24
Peak memory 207408 kb
Host smart-fd463ada-1572-4d87-ba4e-b9622e4d9f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40089
88503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.4008988503
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1300761540
Short name T734
Test name
Test status
Simulation time 171109970 ps
CPU time 0.86 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:02:13 PM PDT 24
Peak memory 207388 kb
Host smart-641e0229-3285-456a-bdcc-9286e8ceaf18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13007
61540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1300761540
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.3820085234
Short name T2310
Test name
Test status
Simulation time 198310588 ps
CPU time 0.89 seconds
Started Aug 06 08:02:09 PM PDT 24
Finished Aug 06 08:02:10 PM PDT 24
Peak memory 207372 kb
Host smart-8f6b2872-f6e0-4457-af2c-f8e10530c55e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3820085234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.3820085234
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2202279850
Short name T1447
Test name
Test status
Simulation time 196065831 ps
CPU time 0.98 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:02:13 PM PDT 24
Peak memory 207356 kb
Host smart-84273a9d-8d3c-4ed2-ad25-5d2c6c3e81e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22022
79850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2202279850
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.697097187
Short name T2805
Test name
Test status
Simulation time 171893691 ps
CPU time 0.81 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:02:13 PM PDT 24
Peak memory 207324 kb
Host smart-c9ba78a1-8b25-4db7-b4cc-ad13ebdb4d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69709
7187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.697097187
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3471479546
Short name T24
Test name
Test status
Simulation time 51880199 ps
CPU time 0.7 seconds
Started Aug 06 08:02:20 PM PDT 24
Finished Aug 06 08:02:21 PM PDT 24
Peak memory 207304 kb
Host smart-b678a7c7-a205-4aab-845e-c47371087e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34714
79546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3471479546
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1137559047
Short name T1241
Test name
Test status
Simulation time 7862847910 ps
CPU time 19.84 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 215884 kb
Host smart-699c5f1e-3c9b-443a-ab61-8e7ab20710f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11375
59047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1137559047
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3499678719
Short name T2435
Test name
Test status
Simulation time 172726469 ps
CPU time 0.91 seconds
Started Aug 06 08:02:14 PM PDT 24
Finished Aug 06 08:02:15 PM PDT 24
Peak memory 207304 kb
Host smart-01c57061-d63e-4f59-ac90-8c0e68bfe5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34996
78719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3499678719
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.328400907
Short name T3036
Test name
Test status
Simulation time 187532182 ps
CPU time 0.98 seconds
Started Aug 06 08:02:15 PM PDT 24
Finished Aug 06 08:02:16 PM PDT 24
Peak memory 207364 kb
Host smart-7a867cdf-d2d3-4c5f-9811-668e2117fd9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32840
0907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.328400907
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1961536823
Short name T2437
Test name
Test status
Simulation time 6996462220 ps
CPU time 31.6 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:02:43 PM PDT 24
Peak memory 224044 kb
Host smart-b848f600-8aa0-46af-b312-0904f634967c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961536823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1961536823
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3029356423
Short name T2165
Test name
Test status
Simulation time 6578571564 ps
CPU time 75.24 seconds
Started Aug 06 08:02:15 PM PDT 24
Finished Aug 06 08:03:30 PM PDT 24
Peak memory 224056 kb
Host smart-ea59d6e0-ec2f-46d1-a24f-90b55e925023
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3029356423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3029356423
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.986880478
Short name T1341
Test name
Test status
Simulation time 6501806007 ps
CPU time 74.49 seconds
Started Aug 06 08:02:33 PM PDT 24
Finished Aug 06 08:03:47 PM PDT 24
Peak memory 224084 kb
Host smart-44d87b70-0362-4df1-918e-98b7ad0ef4cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=986880478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.986880478
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1148582097
Short name T505
Test name
Test status
Simulation time 219355307 ps
CPU time 1 seconds
Started Aug 06 08:02:21 PM PDT 24
Finished Aug 06 08:02:22 PM PDT 24
Peak memory 207444 kb
Host smart-d81d83c0-88b2-4828-a2a1-788a55fc727d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11485
82097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1148582097
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1805809573
Short name T1534
Test name
Test status
Simulation time 172406429 ps
CPU time 0.91 seconds
Started Aug 06 08:02:14 PM PDT 24
Finished Aug 06 08:02:15 PM PDT 24
Peak memory 207372 kb
Host smart-55133d6d-68e3-41c8-a7d1-b4bed55abfc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18058
09573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1805809573
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_resume_link_active.4067318572
Short name T1144
Test name
Test status
Simulation time 20169800853 ps
CPU time 22.96 seconds
Started Aug 06 08:02:14 PM PDT 24
Finished Aug 06 08:02:37 PM PDT 24
Peak memory 207420 kb
Host smart-617b7be4-d9b3-4933-83fb-6dd36bf9b834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40673
18572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.4067318572
Directory /workspace/4.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3701596566
Short name T1086
Test name
Test status
Simulation time 178557478 ps
CPU time 0.86 seconds
Started Aug 06 08:02:19 PM PDT 24
Finished Aug 06 08:02:19 PM PDT 24
Peak memory 207352 kb
Host smart-24b9a38c-7d0d-4505-8cb5-464b2e355018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37015
96566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3701596566
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_full.3380837540
Short name T3008
Test name
Test status
Simulation time 310151815 ps
CPU time 1.14 seconds
Started Aug 06 08:02:24 PM PDT 24
Finished Aug 06 08:02:25 PM PDT 24
Peak memory 207412 kb
Host smart-be37e748-387a-41ab-8e8d-3002ac0cfe8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33808
37540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.3380837540
Directory /workspace/4.usbdev_rx_full/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.2841270060
Short name T79
Test name
Test status
Simulation time 190283238 ps
CPU time 0.88 seconds
Started Aug 06 08:02:13 PM PDT 24
Finished Aug 06 08:02:14 PM PDT 24
Peak memory 207320 kb
Host smart-50bf8250-4cb7-42c3-a098-b92346161f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28412
70060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.2841270060
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2032696529
Short name T237
Test name
Test status
Simulation time 401726720 ps
CPU time 1.23 seconds
Started Aug 06 08:02:11 PM PDT 24
Finished Aug 06 08:02:12 PM PDT 24
Peak memory 223972 kb
Host smart-90926e62-c03c-4780-9021-9e2d011c02e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2032696529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2032696529
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.4286498670
Short name T2636
Test name
Test status
Simulation time 387664012 ps
CPU time 1.42 seconds
Started Aug 06 08:02:22 PM PDT 24
Finished Aug 06 08:02:24 PM PDT 24
Peak memory 207424 kb
Host smart-034d8732-e162-4f15-a82e-639fe72e571b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42864
98670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.4286498670
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.2392672987
Short name T1635
Test name
Test status
Simulation time 191662628 ps
CPU time 0.95 seconds
Started Aug 06 08:02:13 PM PDT 24
Finished Aug 06 08:02:14 PM PDT 24
Peak memory 207596 kb
Host smart-e3617016-3345-4ea7-9f1b-38684dcc6540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23926
72987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.2392672987
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.4052062773
Short name T1357
Test name
Test status
Simulation time 171669215 ps
CPU time 0.87 seconds
Started Aug 06 08:02:16 PM PDT 24
Finished Aug 06 08:02:18 PM PDT 24
Peak memory 207204 kb
Host smart-45eeb433-79d6-4aee-9f1b-8113b036ed48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40520
62773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.4052062773
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.133224079
Short name T2077
Test name
Test status
Simulation time 151400229 ps
CPU time 0.82 seconds
Started Aug 06 08:02:14 PM PDT 24
Finished Aug 06 08:02:15 PM PDT 24
Peak memory 207312 kb
Host smart-419467c2-fc85-4c23-b7a3-064542bbe6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13322
4079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.133224079
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.608803238
Short name T2240
Test name
Test status
Simulation time 209756830 ps
CPU time 0.97 seconds
Started Aug 06 08:02:24 PM PDT 24
Finished Aug 06 08:02:26 PM PDT 24
Peak memory 207376 kb
Host smart-7c3ab814-b7d9-4be8-ad33-4e54124f1c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60880
3238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.608803238
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.3349615961
Short name T1904
Test name
Test status
Simulation time 3271641784 ps
CPU time 90.85 seconds
Started Aug 06 08:02:18 PM PDT 24
Finished Aug 06 08:03:48 PM PDT 24
Peak memory 217584 kb
Host smart-858bd056-3cd4-41fe-af6c-ea3f9f0bfed2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3349615961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.3349615961
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.4256565221
Short name T1115
Test name
Test status
Simulation time 155652873 ps
CPU time 0.85 seconds
Started Aug 06 08:02:10 PM PDT 24
Finished Aug 06 08:02:11 PM PDT 24
Peak memory 207384 kb
Host smart-426bfe3b-da05-4366-a2b7-5f3541a8c038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42565
65221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.4256565221
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2052611150
Short name T2671
Test name
Test status
Simulation time 178326939 ps
CPU time 0.86 seconds
Started Aug 06 08:02:12 PM PDT 24
Finished Aug 06 08:02:13 PM PDT 24
Peak memory 207352 kb
Host smart-124f0b03-6d63-421e-83d3-9aafa25959c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20526
11150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2052611150
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.1382117238
Short name T2729
Test name
Test status
Simulation time 261221225 ps
CPU time 1.08 seconds
Started Aug 06 08:02:23 PM PDT 24
Finished Aug 06 08:02:25 PM PDT 24
Peak memory 207376 kb
Host smart-b72fcf0f-ef27-4035-81ac-b6eb699e8903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13821
17238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.1382117238
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.48647241
Short name T1823
Test name
Test status
Simulation time 3172296339 ps
CPU time 25.37 seconds
Started Aug 06 08:02:13 PM PDT 24
Finished Aug 06 08:02:38 PM PDT 24
Peak memory 217568 kb
Host smart-9992a7d1-52d2-404f-a70e-1293a6b072a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48647
241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.48647241
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1455800486
Short name T257
Test name
Test status
Simulation time 7124159412 ps
CPU time 65 seconds
Started Aug 06 08:02:24 PM PDT 24
Finished Aug 06 08:03:29 PM PDT 24
Peak memory 218744 kb
Host smart-344d2fe3-c44f-4a37-9c32-321c6f93ddb6
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455800486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1455800486
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.3652973290
Short name T907
Test name
Test status
Simulation time 3713083378 ps
CPU time 25.17 seconds
Started Aug 06 08:02:03 PM PDT 24
Finished Aug 06 08:02:28 PM PDT 24
Peak memory 207524 kb
Host smart-feea4350-86d6-4088-a4d0-02a5800009d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652973290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.3652973290
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.2421066138
Short name T2325
Test name
Test status
Simulation time 64116917 ps
CPU time 0.69 seconds
Started Aug 06 08:07:56 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 207488 kb
Host smart-e2f46ea5-ae2b-4231-9ce4-bed2f356ffd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2421066138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.2421066138
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1487494419
Short name T6
Test name
Test status
Simulation time 4337050843 ps
CPU time 6.77 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 216048 kb
Host smart-51d3d2a6-8ba9-487d-b939-33f0edaefdf2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487494419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.1487494419
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1235337039
Short name T1803
Test name
Test status
Simulation time 14892084792 ps
CPU time 17.79 seconds
Started Aug 06 08:07:48 PM PDT 24
Finished Aug 06 08:08:06 PM PDT 24
Peak memory 215824 kb
Host smart-7e2ac347-a36f-407b-a485-962aaed59d3e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235337039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1235337039
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.1123827198
Short name T1946
Test name
Test status
Simulation time 26260923918 ps
CPU time 31.33 seconds
Started Aug 06 08:07:57 PM PDT 24
Finished Aug 06 08:08:29 PM PDT 24
Peak memory 215796 kb
Host smart-a284990a-3d7d-4b52-a4f0-5300ffaadf28
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123827198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.1123827198
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1200924375
Short name T2033
Test name
Test status
Simulation time 160525212 ps
CPU time 0.86 seconds
Started Aug 06 08:07:46 PM PDT 24
Finished Aug 06 08:07:47 PM PDT 24
Peak memory 207356 kb
Host smart-c4e3e783-b538-4629-a434-07fb586b9031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12009
24375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1200924375
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3823419931
Short name T1983
Test name
Test status
Simulation time 154713884 ps
CPU time 0.85 seconds
Started Aug 06 08:07:43 PM PDT 24
Finished Aug 06 08:07:43 PM PDT 24
Peak memory 207288 kb
Host smart-7ff57fb5-cd13-437e-b952-59684b692dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38234
19931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3823419931
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.348351556
Short name T1195
Test name
Test status
Simulation time 223977665 ps
CPU time 0.99 seconds
Started Aug 06 08:07:55 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 207252 kb
Host smart-1d279498-64bc-481b-af94-c5d5f0e2b6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34835
1556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.348351556
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2454625816
Short name T488
Test name
Test status
Simulation time 1365334859 ps
CPU time 3.52 seconds
Started Aug 06 08:07:51 PM PDT 24
Finished Aug 06 08:07:55 PM PDT 24
Peak memory 207384 kb
Host smart-2f840ce3-7fc7-4037-913a-3c9f4ff10210
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2454625816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2454625816
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1432092744
Short name T195
Test name
Test status
Simulation time 33795062973 ps
CPU time 53.13 seconds
Started Aug 06 08:07:50 PM PDT 24
Finished Aug 06 08:08:43 PM PDT 24
Peak memory 207712 kb
Host smart-cb33bba9-4056-4bf4-9a4d-2bc8302d1d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14320
92744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1432092744
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.4072843456
Short name T2871
Test name
Test status
Simulation time 1417573673 ps
CPU time 33.19 seconds
Started Aug 06 08:07:46 PM PDT 24
Finished Aug 06 08:08:19 PM PDT 24
Peak memory 207608 kb
Host smart-bc828a2c-53c4-48e3-b204-b38751ec0015
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072843456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.4072843456
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.1940416319
Short name T1481
Test name
Test status
Simulation time 1177396580 ps
CPU time 2.51 seconds
Started Aug 06 08:07:50 PM PDT 24
Finished Aug 06 08:07:52 PM PDT 24
Peak memory 207380 kb
Host smart-1884a0a2-4173-4478-b0e9-8b64e32a871c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19404
16319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.1940416319
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.4195793364
Short name T1934
Test name
Test status
Simulation time 153700037 ps
CPU time 0.88 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207324 kb
Host smart-3fa422fe-9b8d-4e7f-a380-f59e16951aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41957
93364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.4195793364
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1905462508
Short name T997
Test name
Test status
Simulation time 35824904 ps
CPU time 0.7 seconds
Started Aug 06 08:08:06 PM PDT 24
Finished Aug 06 08:08:07 PM PDT 24
Peak memory 207340 kb
Host smart-dff00452-d78d-4460-b4a6-20bb0767b26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19054
62508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1905462508
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.1505709257
Short name T630
Test name
Test status
Simulation time 997108638 ps
CPU time 2.34 seconds
Started Aug 06 08:08:03 PM PDT 24
Finished Aug 06 08:08:06 PM PDT 24
Peak memory 207592 kb
Host smart-2e8c1e71-792b-4017-a9c5-fb85456578ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15057
09257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.1505709257
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_types.664775415
Short name T448
Test name
Test status
Simulation time 494331453 ps
CPU time 1.46 seconds
Started Aug 06 08:07:52 PM PDT 24
Finished Aug 06 08:07:53 PM PDT 24
Peak memory 207396 kb
Host smart-74fd3511-e25e-4c01-9447-698822609785
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=664775415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.664775415
Directory /workspace/40.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.279645078
Short name T2861
Test name
Test status
Simulation time 310026199 ps
CPU time 2.17 seconds
Started Aug 06 08:07:47 PM PDT 24
Finished Aug 06 08:07:50 PM PDT 24
Peak memory 207460 kb
Host smart-61aa9d95-478c-4295-b75f-cda808aeb1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27964
5078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.279645078
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3852170729
Short name T501
Test name
Test status
Simulation time 234239472 ps
CPU time 1.21 seconds
Started Aug 06 08:07:53 PM PDT 24
Finished Aug 06 08:07:54 PM PDT 24
Peak memory 215696 kb
Host smart-971cf29a-7b62-4e25-9054-8db96b8e2f1d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3852170729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3852170729
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.589080039
Short name T841
Test name
Test status
Simulation time 193826269 ps
CPU time 0.85 seconds
Started Aug 06 08:07:34 PM PDT 24
Finished Aug 06 08:07:35 PM PDT 24
Peak memory 207284 kb
Host smart-4c953934-791b-4947-9a25-c005f968a637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58908
0039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.589080039
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.4188578437
Short name T2611
Test name
Test status
Simulation time 211114156 ps
CPU time 1 seconds
Started Aug 06 08:07:45 PM PDT 24
Finished Aug 06 08:07:46 PM PDT 24
Peak memory 207312 kb
Host smart-e8d753d5-d053-49f0-ad58-866876bf6440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41885
78437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.4188578437
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.4182832040
Short name T2772
Test name
Test status
Simulation time 2581401584 ps
CPU time 73.02 seconds
Started Aug 06 08:07:40 PM PDT 24
Finished Aug 06 08:08:54 PM PDT 24
Peak memory 215912 kb
Host smart-e3673b29-f471-4d2b-b317-91ea489df537
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4182832040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.4182832040
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.4154065784
Short name T1813
Test name
Test status
Simulation time 11837056418 ps
CPU time 146.27 seconds
Started Aug 06 08:07:50 PM PDT 24
Finished Aug 06 08:10:16 PM PDT 24
Peak memory 207616 kb
Host smart-5c7b3d5e-8932-4cc2-8bbf-b4528e6f0d27
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4154065784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.4154065784
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.785899420
Short name T1137
Test name
Test status
Simulation time 222350903 ps
CPU time 0.99 seconds
Started Aug 06 08:07:53 PM PDT 24
Finished Aug 06 08:07:55 PM PDT 24
Peak memory 207396 kb
Host smart-ec7061a9-30ea-4ead-92a2-9fe2d8495867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78589
9420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.785899420
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3966966550
Short name T1012
Test name
Test status
Simulation time 12521280411 ps
CPU time 16.09 seconds
Started Aug 06 08:07:45 PM PDT 24
Finished Aug 06 08:08:01 PM PDT 24
Peak memory 207868 kb
Host smart-2b4f0c2b-d08d-47b5-aa61-8763c734b38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39669
66550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3966966550
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2231311409
Short name T2368
Test name
Test status
Simulation time 8350638941 ps
CPU time 10.14 seconds
Started Aug 06 08:07:50 PM PDT 24
Finished Aug 06 08:08:00 PM PDT 24
Peak memory 207708 kb
Host smart-0a2bb688-636b-4666-8139-687230e81f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22313
11409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2231311409
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1266922209
Short name T1479
Test name
Test status
Simulation time 4389603268 ps
CPU time 42.51 seconds
Started Aug 06 08:07:56 PM PDT 24
Finished Aug 06 08:08:39 PM PDT 24
Peak memory 224040 kb
Host smart-e41be57e-0f76-416e-b45b-4a33a98c2053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12669
22209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1266922209
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.3495527741
Short name T2051
Test name
Test status
Simulation time 1393570915 ps
CPU time 13.53 seconds
Started Aug 06 08:07:45 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 215724 kb
Host smart-dd5319c5-4bb6-4cb4-88c2-a69bd7d10ac7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3495527741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.3495527741
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.814823840
Short name T2305
Test name
Test status
Simulation time 268305820 ps
CPU time 0.97 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207380 kb
Host smart-5a06a74e-dd5d-4239-97f3-34683742b34b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=814823840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.814823840
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.342100650
Short name T1870
Test name
Test status
Simulation time 196458730 ps
CPU time 0.95 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:08:02 PM PDT 24
Peak memory 207376 kb
Host smart-7d796be6-e8b6-444c-8e15-c7e09a96b293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34210
0650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.342100650
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1367088483
Short name T2497
Test name
Test status
Simulation time 2629583375 ps
CPU time 25.62 seconds
Started Aug 06 08:07:46 PM PDT 24
Finished Aug 06 08:08:12 PM PDT 24
Peak memory 215768 kb
Host smart-9cefd805-71f6-4a8d-8d03-511f97a88a6e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1367088483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1367088483
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.562873958
Short name T3055
Test name
Test status
Simulation time 171492743 ps
CPU time 0.83 seconds
Started Aug 06 08:07:47 PM PDT 24
Finished Aug 06 08:07:48 PM PDT 24
Peak memory 207444 kb
Host smart-db837173-aa4d-4505-98d5-965299898c91
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=562873958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.562873958
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3458033565
Short name T2279
Test name
Test status
Simulation time 149849113 ps
CPU time 0.85 seconds
Started Aug 06 08:07:48 PM PDT 24
Finished Aug 06 08:07:49 PM PDT 24
Peak memory 207344 kb
Host smart-fcc45b0e-e881-4acf-b2b2-5fa4c2798264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34580
33565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3458033565
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3794048718
Short name T2023
Test name
Test status
Simulation time 203857814 ps
CPU time 0.96 seconds
Started Aug 06 08:07:54 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 207380 kb
Host smart-22147a5e-b492-4d06-906b-dca185616cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37940
48718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3794048718
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3305232193
Short name T2245
Test name
Test status
Simulation time 170634897 ps
CPU time 0.89 seconds
Started Aug 06 08:07:43 PM PDT 24
Finished Aug 06 08:07:44 PM PDT 24
Peak memory 207384 kb
Host smart-c0b5dcc6-2101-4418-b19d-8aa47b92c66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33052
32193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3305232193
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.4096872232
Short name T1835
Test name
Test status
Simulation time 152662473 ps
CPU time 0.84 seconds
Started Aug 06 08:07:47 PM PDT 24
Finished Aug 06 08:07:48 PM PDT 24
Peak memory 207308 kb
Host smart-36655ec6-a29e-4d58-acdd-1fbd2a3d4a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40968
72232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.4096872232
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1141620240
Short name T1825
Test name
Test status
Simulation time 194278798 ps
CPU time 0.9 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207336 kb
Host smart-9554ca40-c72a-4d24-8db4-56ebecaf1c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11416
20240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1141620240
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1660803479
Short name T2728
Test name
Test status
Simulation time 201079543 ps
CPU time 0.89 seconds
Started Aug 06 08:07:59 PM PDT 24
Finished Aug 06 08:08:00 PM PDT 24
Peak memory 207324 kb
Host smart-02676d3a-15a6-4e9b-9560-ec6514d4a588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16608
03479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1660803479
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.1245299140
Short name T972
Test name
Test status
Simulation time 267302476 ps
CPU time 1.14 seconds
Started Aug 06 08:07:40 PM PDT 24
Finished Aug 06 08:07:42 PM PDT 24
Peak memory 207300 kb
Host smart-d455302b-59f2-4155-95c7-19bd23405b16
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1245299140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.1245299140
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1681778150
Short name T2546
Test name
Test status
Simulation time 156350089 ps
CPU time 0.86 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207348 kb
Host smart-d2da083c-3a34-47e6-b011-4794dca7dcd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16817
78150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1681778150
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2379441272
Short name T2958
Test name
Test status
Simulation time 79508344 ps
CPU time 0.76 seconds
Started Aug 06 08:07:43 PM PDT 24
Finished Aug 06 08:07:44 PM PDT 24
Peak memory 207256 kb
Host smart-ac8bdaee-60cc-4fa1-9c42-08b13ed40e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23794
41272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2379441272
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.647493592
Short name T2282
Test name
Test status
Simulation time 18849795342 ps
CPU time 47.56 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:08:45 PM PDT 24
Peak memory 215844 kb
Host smart-2b6e60c5-1f93-40c6-af23-84db8cb3b8cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64749
3592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.647493592
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2799714439
Short name T2200
Test name
Test status
Simulation time 188801322 ps
CPU time 0.91 seconds
Started Aug 06 08:07:42 PM PDT 24
Finished Aug 06 08:07:43 PM PDT 24
Peak memory 207356 kb
Host smart-1eeaf4d3-1352-472e-8f96-9e0559cc23d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27997
14439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2799714439
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.138594095
Short name T794
Test name
Test status
Simulation time 230828715 ps
CPU time 0.96 seconds
Started Aug 06 08:07:52 PM PDT 24
Finished Aug 06 08:07:53 PM PDT 24
Peak memory 207312 kb
Host smart-965d5470-bb0d-46e6-bb07-c7d3233b61ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13859
4095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.138594095
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.3806896539
Short name T1807
Test name
Test status
Simulation time 178359471 ps
CPU time 0.88 seconds
Started Aug 06 08:07:49 PM PDT 24
Finished Aug 06 08:07:50 PM PDT 24
Peak memory 207204 kb
Host smart-34a58de3-d87e-4aa8-b133-ec2211eec670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38068
96539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.3806896539
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.78885017
Short name T2628
Test name
Test status
Simulation time 180367868 ps
CPU time 0.93 seconds
Started Aug 06 08:07:52 PM PDT 24
Finished Aug 06 08:07:53 PM PDT 24
Peak memory 207400 kb
Host smart-7456e35b-a523-4f31-8744-c9f443e9fcde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78885
017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.78885017
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.4128200874
Short name T1138
Test name
Test status
Simulation time 139671239 ps
CPU time 0.81 seconds
Started Aug 06 08:07:53 PM PDT 24
Finished Aug 06 08:07:54 PM PDT 24
Peak memory 207288 kb
Host smart-289b5b6f-f417-4a00-b717-8eaf4170c883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41282
00874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.4128200874
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_rx_full.2987855447
Short name T780
Test name
Test status
Simulation time 415881374 ps
CPU time 1.41 seconds
Started Aug 06 08:07:47 PM PDT 24
Finished Aug 06 08:07:49 PM PDT 24
Peak memory 207324 kb
Host smart-a5fb44ca-c0b2-4fa4-aaa7-c20046acf43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29878
55447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.2987855447
Directory /workspace/40.usbdev_rx_full/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.3794467837
Short name T1739
Test name
Test status
Simulation time 155674656 ps
CPU time 0.89 seconds
Started Aug 06 08:07:45 PM PDT 24
Finished Aug 06 08:07:46 PM PDT 24
Peak memory 207348 kb
Host smart-dd21b513-9e8d-4493-b4cd-c7d3b4b20cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37944
67837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.3794467837
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.644202934
Short name T1222
Test name
Test status
Simulation time 149631813 ps
CPU time 0.83 seconds
Started Aug 06 08:07:44 PM PDT 24
Finished Aug 06 08:07:45 PM PDT 24
Peak memory 207360 kb
Host smart-e0fef85b-dbd2-4757-b16e-0aa7f7f43a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64420
2934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.644202934
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2079279505
Short name T568
Test name
Test status
Simulation time 305032128 ps
CPU time 1.12 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:08:00 PM PDT 24
Peak memory 207340 kb
Host smart-e44ea246-4a3c-4198-bc00-4b85b89abb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20792
79505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2079279505
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.3651514614
Short name T1855
Test name
Test status
Simulation time 1976093555 ps
CPU time 57.6 seconds
Started Aug 06 08:07:42 PM PDT 24
Finished Aug 06 08:08:39 PM PDT 24
Peak memory 217212 kb
Host smart-b950b835-5461-4380-9d05-0faf7cb8bca6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3651514614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.3651514614
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.406575187
Short name T2390
Test name
Test status
Simulation time 149957569 ps
CPU time 0.85 seconds
Started Aug 06 08:07:50 PM PDT 24
Finished Aug 06 08:07:51 PM PDT 24
Peak memory 207312 kb
Host smart-43271453-a290-4752-bbe2-fd8cc791b8bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40657
5187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.406575187
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.3133112489
Short name T1448
Test name
Test status
Simulation time 183265164 ps
CPU time 0.94 seconds
Started Aug 06 08:07:53 PM PDT 24
Finished Aug 06 08:07:54 PM PDT 24
Peak memory 207304 kb
Host smart-fa8567cb-9996-4659-8a7c-ad4aa25e9475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31331
12489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3133112489
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.3788297600
Short name T2717
Test name
Test status
Simulation time 647227205 ps
CPU time 1.96 seconds
Started Aug 06 08:07:51 PM PDT 24
Finished Aug 06 08:07:53 PM PDT 24
Peak memory 207300 kb
Host smart-11d5a63c-d3c6-41f6-b741-bbee8daa1119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37882
97600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3788297600
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2484556175
Short name T1831
Test name
Test status
Simulation time 2616381482 ps
CPU time 19.94 seconds
Started Aug 06 08:07:49 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 215916 kb
Host smart-4ba78ef3-d3d1-4962-b897-ac7cc70465a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24845
56175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2484556175
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.1406495564
Short name T1040
Test name
Test status
Simulation time 726646863 ps
CPU time 11.76 seconds
Started Aug 06 08:07:59 PM PDT 24
Finished Aug 06 08:08:11 PM PDT 24
Peak memory 207472 kb
Host smart-40484aaa-f564-49cb-b023-46808adccd93
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406495564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.1406495564
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3246884720
Short name T797
Test name
Test status
Simulation time 58339303 ps
CPU time 0.73 seconds
Started Aug 06 08:08:13 PM PDT 24
Finished Aug 06 08:08:14 PM PDT 24
Peak memory 207428 kb
Host smart-81b47478-a990-481b-bb53-1300bc909205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3246884720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3246884720
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2390443445
Short name T742
Test name
Test status
Simulation time 11002001242 ps
CPU time 12.93 seconds
Started Aug 06 08:07:47 PM PDT 24
Finished Aug 06 08:08:00 PM PDT 24
Peak memory 207656 kb
Host smart-773ea9cc-e56e-4040-a56b-edf71ed71d74
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390443445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.2390443445
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1516354651
Short name T244
Test name
Test status
Simulation time 19016151939 ps
CPU time 21.4 seconds
Started Aug 06 08:07:48 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 207632 kb
Host smart-05cde025-0428-4b25-b448-fa25f0ff3c3d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516354651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1516354651
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2570388649
Short name T7
Test name
Test status
Simulation time 25819533896 ps
CPU time 28.79 seconds
Started Aug 06 08:07:55 PM PDT 24
Finished Aug 06 08:08:24 PM PDT 24
Peak memory 215648 kb
Host smart-d29f2736-ffe9-48a1-9df9-21938390991a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570388649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.2570388649
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3312625674
Short name T933
Test name
Test status
Simulation time 146458500 ps
CPU time 0.83 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207396 kb
Host smart-17362019-b8f5-4b6a-b912-880d5fc4697f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33126
25674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3312625674
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.3324512174
Short name T1336
Test name
Test status
Simulation time 160386941 ps
CPU time 0.8 seconds
Started Aug 06 08:07:49 PM PDT 24
Finished Aug 06 08:07:50 PM PDT 24
Peak memory 207328 kb
Host smart-a034d406-8b06-4fe7-b586-9194d0498252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33245
12174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.3324512174
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3419059916
Short name T782
Test name
Test status
Simulation time 467816535 ps
CPU time 1.58 seconds
Started Aug 06 08:08:07 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 207356 kb
Host smart-f1aef3fc-c9f3-4fce-aa24-78c2c191614b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34190
59916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3419059916
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3164393863
Short name T1043
Test name
Test status
Simulation time 566209441 ps
CPU time 1.6 seconds
Started Aug 06 08:07:52 PM PDT 24
Finished Aug 06 08:07:54 PM PDT 24
Peak memory 207372 kb
Host smart-d2229b1e-0ab6-44e9-8461-db15f97e47f3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3164393863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3164393863
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.948091354
Short name T202
Test name
Test status
Simulation time 20013471484 ps
CPU time 29.21 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:31 PM PDT 24
Peak memory 207588 kb
Host smart-7673c22f-9171-4ec9-ae84-d9eaad72103e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94809
1354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.948091354
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.2159162696
Short name T2457
Test name
Test status
Simulation time 549911577 ps
CPU time 11.48 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:19 PM PDT 24
Peak memory 207568 kb
Host smart-6c8c575a-bf67-4545-9699-c838dad71385
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159162696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.2159162696
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.2455416854
Short name T2345
Test name
Test status
Simulation time 747408228 ps
CPU time 1.83 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:10 PM PDT 24
Peak memory 207264 kb
Host smart-75c8d11d-e3f3-4ab5-97fa-786c55352f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24554
16854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2455416854
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.2038227179
Short name T1416
Test name
Test status
Simulation time 154412259 ps
CPU time 0.85 seconds
Started Aug 06 08:08:06 PM PDT 24
Finished Aug 06 08:08:07 PM PDT 24
Peak memory 207320 kb
Host smart-0cb3d67b-f685-4269-a75f-2ad7c449d4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20382
27179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.2038227179
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.1912086740
Short name T1880
Test name
Test status
Simulation time 37566613 ps
CPU time 0.71 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207284 kb
Host smart-b34e476a-23a9-4ebd-99c3-9940e5b35dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19120
86740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1912086740
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.371611083
Short name T1225
Test name
Test status
Simulation time 1012476524 ps
CPU time 2.72 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207596 kb
Host smart-ba6c4c01-fb89-42d1-ab5e-a677a84a8169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37161
1083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.371611083
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_types.1015942979
Short name T2529
Test name
Test status
Simulation time 176567042 ps
CPU time 0.89 seconds
Started Aug 06 08:08:03 PM PDT 24
Finished Aug 06 08:08:04 PM PDT 24
Peak memory 207320 kb
Host smart-0810cb74-8c11-4bf5-b054-68e9b784d3e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1015942979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.1015942979
Directory /workspace/41.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1050640630
Short name T2834
Test name
Test status
Simulation time 313558303 ps
CPU time 2.53 seconds
Started Aug 06 08:08:03 PM PDT 24
Finished Aug 06 08:08:06 PM PDT 24
Peak memory 207520 kb
Host smart-0e40fa7e-4d5e-4dd0-9273-f3824a99f9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506
40630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1050640630
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3409869367
Short name T1024
Test name
Test status
Simulation time 212054945 ps
CPU time 1.07 seconds
Started Aug 06 08:07:54 PM PDT 24
Finished Aug 06 08:07:55 PM PDT 24
Peak memory 215708 kb
Host smart-8faf7f62-f062-4a3c-8709-299f1f056f6b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3409869367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3409869367
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1504395908
Short name T1039
Test name
Test status
Simulation time 140055744 ps
CPU time 0.8 seconds
Started Aug 06 08:08:14 PM PDT 24
Finished Aug 06 08:08:15 PM PDT 24
Peak memory 207316 kb
Host smart-9f11e971-0b66-415f-93db-2f3de6875042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15043
95908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1504395908
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2941564532
Short name T1061
Test name
Test status
Simulation time 166569438 ps
CPU time 0.88 seconds
Started Aug 06 08:08:05 PM PDT 24
Finished Aug 06 08:08:05 PM PDT 24
Peak memory 207416 kb
Host smart-5119e2ed-4cda-41f1-b88b-1ad06c05a0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29415
64532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2941564532
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.325933358
Short name T2395
Test name
Test status
Simulation time 4354537914 ps
CPU time 124.32 seconds
Started Aug 06 08:08:05 PM PDT 24
Finished Aug 06 08:10:09 PM PDT 24
Peak memory 215724 kb
Host smart-9aaab737-a0e5-4647-8a98-dfa8aaa32551
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=325933358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.325933358
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.413529009
Short name T284
Test name
Test status
Simulation time 14549921640 ps
CPU time 91.32 seconds
Started Aug 06 08:08:00 PM PDT 24
Finished Aug 06 08:09:31 PM PDT 24
Peak memory 207572 kb
Host smart-bbe2238c-6d60-4ab8-8e56-4003f0b25a31
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=413529009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.413529009
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.235333611
Short name T1942
Test name
Test status
Simulation time 233123862 ps
CPU time 1.07 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:10 PM PDT 24
Peak memory 207372 kb
Host smart-cecba571-9e75-4a44-be91-54a1ce68044d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23533
3611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.235333611
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.703049034
Short name T2883
Test name
Test status
Simulation time 28259384854 ps
CPU time 43.26 seconds
Started Aug 06 08:08:03 PM PDT 24
Finished Aug 06 08:08:46 PM PDT 24
Peak memory 207628 kb
Host smart-e353cad9-5ed9-4575-ab67-a90939f620ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70304
9034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.703049034
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1824229964
Short name T3022
Test name
Test status
Simulation time 10700350553 ps
CPU time 13.24 seconds
Started Aug 06 08:08:04 PM PDT 24
Finished Aug 06 08:08:18 PM PDT 24
Peak memory 207552 kb
Host smart-54292cda-0abf-4b1e-862a-bdd2ffda6522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18242
29964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1824229964
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.2866799986
Short name T327
Test name
Test status
Simulation time 3534026370 ps
CPU time 34.09 seconds
Started Aug 06 08:07:53 PM PDT 24
Finished Aug 06 08:08:28 PM PDT 24
Peak memory 218456 kb
Host smart-14a17082-758e-4152-8d65-378ce4347593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28667
99986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.2866799986
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.677631913
Short name T731
Test name
Test status
Simulation time 1840098784 ps
CPU time 17.98 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:08:20 PM PDT 24
Peak memory 216732 kb
Host smart-10bfe781-0250-447a-abea-7fa5f0eb1f55
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=677631913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.677631913
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.4126418239
Short name T1670
Test name
Test status
Simulation time 281430705 ps
CPU time 1.06 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207324 kb
Host smart-a5be1baa-eef1-4a4f-a184-bec776a93cde
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4126418239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.4126418239
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3016987568
Short name T1244
Test name
Test status
Simulation time 182641237 ps
CPU time 0.95 seconds
Started Aug 06 08:08:07 PM PDT 24
Finished Aug 06 08:08:08 PM PDT 24
Peak memory 207360 kb
Host smart-9ca8c14a-da62-4ac7-a6fc-150072d292b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30169
87568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3016987568
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.3851789928
Short name T3010
Test name
Test status
Simulation time 2358611244 ps
CPU time 24.37 seconds
Started Aug 06 08:08:00 PM PDT 24
Finished Aug 06 08:08:24 PM PDT 24
Peak memory 217468 kb
Host smart-b221c399-1011-493e-90d6-f0511130859c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3851789928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.3851789928
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.222122912
Short name T1120
Test name
Test status
Simulation time 156275611 ps
CPU time 0.86 seconds
Started Aug 06 08:08:00 PM PDT 24
Finished Aug 06 08:08:01 PM PDT 24
Peak memory 207384 kb
Host smart-5e5611ce-24bf-4bf9-acda-442b0999339c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=222122912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.222122912
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1094367017
Short name T1915
Test name
Test status
Simulation time 157826792 ps
CPU time 0.87 seconds
Started Aug 06 08:07:59 PM PDT 24
Finished Aug 06 08:08:00 PM PDT 24
Peak memory 207304 kb
Host smart-a9320bd8-bbd6-4cf1-9b78-f1b147eba1bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
67017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1094367017
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2546970044
Short name T2210
Test name
Test status
Simulation time 272924308 ps
CPU time 0.97 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:08:02 PM PDT 24
Peak memory 207308 kb
Host smart-df9798ce-7ea0-4974-879e-610fe17abcd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25469
70044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2546970044
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.914197970
Short name T2633
Test name
Test status
Simulation time 195154277 ps
CPU time 0.94 seconds
Started Aug 06 08:08:12 PM PDT 24
Finished Aug 06 08:08:13 PM PDT 24
Peak memory 207412 kb
Host smart-28db6327-393b-4493-bfab-ea9d0b185523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91419
7970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.914197970
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1145006404
Short name T616
Test name
Test status
Simulation time 193407699 ps
CPU time 0.94 seconds
Started Aug 06 08:07:57 PM PDT 24
Finished Aug 06 08:07:58 PM PDT 24
Peak memory 207344 kb
Host smart-01c69fca-dd83-443a-b6e3-42da1fe8c96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11450
06404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1145006404
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.534014869
Short name T1580
Test name
Test status
Simulation time 150524493 ps
CPU time 0.8 seconds
Started Aug 06 08:07:55 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 207372 kb
Host smart-d071d20d-3297-41e8-9fcb-141562c652cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53401
4869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.534014869
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1910454723
Short name T2663
Test name
Test status
Simulation time 213056751 ps
CPU time 0.95 seconds
Started Aug 06 08:07:56 PM PDT 24
Finished Aug 06 08:07:57 PM PDT 24
Peak memory 207364 kb
Host smart-6c1412c7-03c2-44c0-a5e3-573a84e02151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19104
54723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1910454723
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.329485510
Short name T1746
Test name
Test status
Simulation time 222872946 ps
CPU time 0.99 seconds
Started Aug 06 08:07:57 PM PDT 24
Finished Aug 06 08:07:58 PM PDT 24
Peak memory 207380 kb
Host smart-488275f5-42fb-4fe8-9873-88ab6cead92c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=329485510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.329485510
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2961993302
Short name T944
Test name
Test status
Simulation time 155497468 ps
CPU time 0.83 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207420 kb
Host smart-d63dfdec-b836-466d-8437-55b483feaf7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29619
93302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2961993302
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.476773960
Short name T1215
Test name
Test status
Simulation time 44894977 ps
CPU time 0.71 seconds
Started Aug 06 08:08:13 PM PDT 24
Finished Aug 06 08:08:14 PM PDT 24
Peak memory 207380 kb
Host smart-cd0d8d71-ee36-448f-bac2-16d1a450bea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47677
3960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.476773960
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.4071955244
Short name T2837
Test name
Test status
Simulation time 13273543563 ps
CPU time 33.83 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:36 PM PDT 24
Peak memory 215792 kb
Host smart-4dc5240d-31f5-45f1-9aa0-a67353c7f08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40719
55244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.4071955244
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.712549763
Short name T1221
Test name
Test status
Simulation time 172216183 ps
CPU time 0.91 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207372 kb
Host smart-2d25f190-96c2-48f1-815a-d86ccd56d42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71254
9763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.712549763
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2436743076
Short name T2485
Test name
Test status
Simulation time 201893486 ps
CPU time 0.98 seconds
Started Aug 06 08:07:54 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 207416 kb
Host smart-b90141e1-933a-436a-8a58-962b97fef8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24367
43076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2436743076
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.152101768
Short name T1858
Test name
Test status
Simulation time 190987092 ps
CPU time 0.94 seconds
Started Aug 06 08:08:09 PM PDT 24
Finished Aug 06 08:08:10 PM PDT 24
Peak memory 207400 kb
Host smart-38b102de-4c01-4d43-aa1f-da93afb5eae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15210
1768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.152101768
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1175609678
Short name T2147
Test name
Test status
Simulation time 198628133 ps
CPU time 0.97 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207312 kb
Host smart-5dcb84a2-622e-4949-9eca-53e3fb217392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11756
09678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1175609678
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.3316451583
Short name T770
Test name
Test status
Simulation time 174559283 ps
CPU time 0.83 seconds
Started Aug 06 08:08:17 PM PDT 24
Finished Aug 06 08:08:18 PM PDT 24
Peak memory 207340 kb
Host smart-eeca3763-d4c7-437d-b17e-b019560b81bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33164
51583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.3316451583
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_rx_full.576109133
Short name T1311
Test name
Test status
Simulation time 289675598 ps
CPU time 1.08 seconds
Started Aug 06 08:07:59 PM PDT 24
Finished Aug 06 08:08:01 PM PDT 24
Peak memory 207312 kb
Host smart-ac78456a-8bb5-41b7-b192-707e5051dba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57610
9133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.576109133
Directory /workspace/41.usbdev_rx_full/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3950881407
Short name T1899
Test name
Test status
Simulation time 157468618 ps
CPU time 0.81 seconds
Started Aug 06 08:08:05 PM PDT 24
Finished Aug 06 08:08:06 PM PDT 24
Peak memory 207256 kb
Host smart-788dedae-b866-412c-b25a-0313d449858e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39508
81407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3950881407
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3615960973
Short name T2049
Test name
Test status
Simulation time 169479480 ps
CPU time 0.87 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207372 kb
Host smart-254845f7-8717-4d77-90be-288c21c2bbb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36159
60973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3615960973
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2484993306
Short name T1626
Test name
Test status
Simulation time 244659081 ps
CPU time 1.01 seconds
Started Aug 06 08:07:59 PM PDT 24
Finished Aug 06 08:08:00 PM PDT 24
Peak memory 207332 kb
Host smart-1e70e6dd-aac1-480a-9978-9cd4b7b9fa50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24849
93306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2484993306
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3553281579
Short name T1760
Test name
Test status
Simulation time 2906836300 ps
CPU time 84.86 seconds
Started Aug 06 08:08:03 PM PDT 24
Finished Aug 06 08:09:28 PM PDT 24
Peak memory 217696 kb
Host smart-20d27c42-b597-476f-a61b-6acf1f7554f9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3553281579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3553281579
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2704200152
Short name T2359
Test name
Test status
Simulation time 171217912 ps
CPU time 0.89 seconds
Started Aug 06 08:08:00 PM PDT 24
Finished Aug 06 08:08:01 PM PDT 24
Peak memory 207356 kb
Host smart-ebc72982-d1a0-49f0-a7e9-4ff2f5e84334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27042
00152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2704200152
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2695888103
Short name T1794
Test name
Test status
Simulation time 201208421 ps
CPU time 0.87 seconds
Started Aug 06 08:08:00 PM PDT 24
Finished Aug 06 08:08:06 PM PDT 24
Peak memory 207312 kb
Host smart-dcac4da0-0fbf-4666-a933-e612864fb2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26958
88103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2695888103
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.1781820580
Short name T554
Test name
Test status
Simulation time 200795596 ps
CPU time 0.98 seconds
Started Aug 06 08:07:55 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 207320 kb
Host smart-cc107786-0504-42d8-a19f-a50948109c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17818
20580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.1781820580
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.1721505946
Short name T2905
Test name
Test status
Simulation time 2199913267 ps
CPU time 17.57 seconds
Started Aug 06 08:08:10 PM PDT 24
Finished Aug 06 08:08:28 PM PDT 24
Peak memory 217568 kb
Host smart-90f7d643-a4ee-4e64-a167-61c69f17a0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17215
05946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.1721505946
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.1110225297
Short name T894
Test name
Test status
Simulation time 4298426513 ps
CPU time 27.67 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:08:26 PM PDT 24
Peak memory 207624 kb
Host smart-b6bcf0c2-c377-4675-80eb-ea905cb4e411
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110225297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.1110225297
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2023665834
Short name T1565
Test name
Test status
Simulation time 49717007 ps
CPU time 0.64 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 207304 kb
Host smart-de83b465-3878-4534-a727-aeba92ba11aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2023665834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2023665834
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.909318415
Short name T1977
Test name
Test status
Simulation time 6096041103 ps
CPU time 9.79 seconds
Started Aug 06 08:07:57 PM PDT 24
Finished Aug 06 08:08:07 PM PDT 24
Peak memory 215884 kb
Host smart-9cd243c1-e21c-4a93-b41e-3ebf24a01308
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909318415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_ao
n_wake_disconnect.909318415
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1107269664
Short name T3060
Test name
Test status
Simulation time 20330387436 ps
CPU time 27.81 seconds
Started Aug 06 08:08:00 PM PDT 24
Finished Aug 06 08:08:28 PM PDT 24
Peak memory 207644 kb
Host smart-d703d930-433d-4241-9396-c6c3adcd7e62
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107269664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1107269664
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3600513689
Short name T839
Test name
Test status
Simulation time 30491725557 ps
CPU time 35.35 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:38 PM PDT 24
Peak memory 207692 kb
Host smart-5882f3f5-72ac-4ea8-a049-fdb7c7eef8c5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600513689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.3600513689
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3507605571
Short name T896
Test name
Test status
Simulation time 207261874 ps
CPU time 0.97 seconds
Started Aug 06 08:08:05 PM PDT 24
Finished Aug 06 08:08:06 PM PDT 24
Peak memory 207336 kb
Host smart-48334af1-0dc0-4f5b-b5b6-4e2f1bf0aaa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35076
05571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3507605571
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3407189811
Short name T1606
Test name
Test status
Simulation time 146275270 ps
CPU time 0.85 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:07:59 PM PDT 24
Peak memory 207268 kb
Host smart-bfffae20-548b-4b5a-bfec-1e81bd4e3430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34071
89811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3407189811
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.3052626913
Short name T1170
Test name
Test status
Simulation time 177045989 ps
CPU time 0.9 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207376 kb
Host smart-57c25f88-3623-4f08-a4a3-88d69660f921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30526
26913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.3052626913
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.23201450
Short name T85
Test name
Test status
Simulation time 986089746 ps
CPU time 2.7 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:11 PM PDT 24
Peak memory 207568 kb
Host smart-e4035a6f-661c-4b20-bf5a-d74dbeccab8b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=23201450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.23201450
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.1987117067
Short name T531
Test name
Test status
Simulation time 2968592031 ps
CPU time 25.06 seconds
Started Aug 06 08:08:05 PM PDT 24
Finished Aug 06 08:08:31 PM PDT 24
Peak memory 207688 kb
Host smart-7c3913f8-e397-458e-b47d-716aec508e57
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987117067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.1987117067
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3319825430
Short name T1209
Test name
Test status
Simulation time 756421815 ps
CPU time 1.88 seconds
Started Aug 06 08:07:58 PM PDT 24
Finished Aug 06 08:08:00 PM PDT 24
Peak memory 207308 kb
Host smart-9c35e317-2e30-4481-b07c-59bed2e99cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33198
25430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3319825430
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.11982863
Short name T3031
Test name
Test status
Simulation time 143056183 ps
CPU time 0.84 seconds
Started Aug 06 08:07:53 PM PDT 24
Finished Aug 06 08:07:54 PM PDT 24
Peak memory 207348 kb
Host smart-232e7424-de0e-49ef-9284-8420a9a8c813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11982
863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.11982863
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.3050242647
Short name T2201
Test name
Test status
Simulation time 38960050 ps
CPU time 0.71 seconds
Started Aug 06 08:08:04 PM PDT 24
Finished Aug 06 08:08:04 PM PDT 24
Peak memory 207316 kb
Host smart-657d8e90-20aa-438c-8e4e-6d2dd0e279cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30502
42647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3050242647
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2714481991
Short name T1845
Test name
Test status
Simulation time 781502354 ps
CPU time 2.36 seconds
Started Aug 06 08:07:59 PM PDT 24
Finished Aug 06 08:08:01 PM PDT 24
Peak memory 207520 kb
Host smart-bed5553e-8ad8-4976-8ca7-28a83adab85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27144
81991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2714481991
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_types.3935629714
Short name T3020
Test name
Test status
Simulation time 689481413 ps
CPU time 1.64 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:10 PM PDT 24
Peak memory 207256 kb
Host smart-68157218-357a-4c39-bfb0-1c86aa13e21e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3935629714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.3935629714
Directory /workspace/42.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3786329996
Short name T3011
Test name
Test status
Simulation time 314007334 ps
CPU time 2.16 seconds
Started Aug 06 08:07:49 PM PDT 24
Finished Aug 06 08:07:51 PM PDT 24
Peak memory 207444 kb
Host smart-5ea53a8d-f6f9-4665-b7de-4d0dc2f96cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37863
29996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3786329996
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3272614187
Short name T1036
Test name
Test status
Simulation time 188484552 ps
CPU time 0.96 seconds
Started Aug 06 08:07:54 PM PDT 24
Finished Aug 06 08:07:55 PM PDT 24
Peak memory 215676 kb
Host smart-aa1e3b5d-dcb4-4189-9dc2-d464b6b30a9b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3272614187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3272614187
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3059396327
Short name T1608
Test name
Test status
Simulation time 161275810 ps
CPU time 0.84 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 207416 kb
Host smart-d5a80091-6685-4292-b759-c93925db3948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30593
96327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3059396327
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2815655483
Short name T566
Test name
Test status
Simulation time 256378336 ps
CPU time 0.98 seconds
Started Aug 06 08:08:09 PM PDT 24
Finished Aug 06 08:08:10 PM PDT 24
Peak memory 207360 kb
Host smart-20a2759e-1122-45ae-aca2-fb972b1a9c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28156
55483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2815655483
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.3642878089
Short name T1427
Test name
Test status
Simulation time 4133147473 ps
CPU time 42.29 seconds
Started Aug 06 08:08:05 PM PDT 24
Finished Aug 06 08:08:47 PM PDT 24
Peak memory 224092 kb
Host smart-738f959e-f62b-4042-812c-5eca8ee4a680
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3642878089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.3642878089
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.1993237812
Short name T2207
Test name
Test status
Simulation time 162656836 ps
CPU time 0.89 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 207352 kb
Host smart-b6d881e9-2277-470a-a2c8-a334c7602439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19932
37812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1993237812
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.2616710246
Short name T1019
Test name
Test status
Simulation time 30370886975 ps
CPU time 47.12 seconds
Started Aug 06 08:07:54 PM PDT 24
Finished Aug 06 08:08:41 PM PDT 24
Peak memory 207632 kb
Host smart-c457c4b9-a478-47c1-8d8e-f48189e25b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26167
10246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.2616710246
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1811039217
Short name T1514
Test name
Test status
Simulation time 10882410836 ps
CPU time 13.36 seconds
Started Aug 06 08:08:09 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207604 kb
Host smart-dae3179c-2c5f-4f27-a50d-5d59b2a49c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18110
39217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1811039217
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.3514150308
Short name T2757
Test name
Test status
Simulation time 3127271187 ps
CPU time 30.44 seconds
Started Aug 06 08:08:06 PM PDT 24
Finished Aug 06 08:08:36 PM PDT 24
Peak memory 224028 kb
Host smart-857338e3-7c17-42bf-8be4-937c38158846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35141
50308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.3514150308
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.2325299596
Short name T3064
Test name
Test status
Simulation time 2410171046 ps
CPU time 65.3 seconds
Started Aug 06 08:08:07 PM PDT 24
Finished Aug 06 08:09:12 PM PDT 24
Peak memory 215840 kb
Host smart-0860e458-5249-4832-b1bc-1cb03fa099ec
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2325299596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.2325299596
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.1478291534
Short name T2072
Test name
Test status
Simulation time 247290830 ps
CPU time 1.03 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207364 kb
Host smart-9a487497-484f-4d26-becb-6396d869a9b2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1478291534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.1478291534
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3038378931
Short name T2064
Test name
Test status
Simulation time 201329382 ps
CPU time 0.93 seconds
Started Aug 06 08:08:03 PM PDT 24
Finished Aug 06 08:08:05 PM PDT 24
Peak memory 207404 kb
Host smart-b440727f-3243-4742-8667-480553491906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30383
78931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3038378931
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.1240559114
Short name T1766
Test name
Test status
Simulation time 2971505909 ps
CPU time 85.48 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:09:27 PM PDT 24
Peak memory 217244 kb
Host smart-c56bbc50-0091-4098-a90f-4ae282bc234d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1240559114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.1240559114
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.2360371499
Short name T2897
Test name
Test status
Simulation time 160306069 ps
CPU time 0.85 seconds
Started Aug 06 08:07:57 PM PDT 24
Finished Aug 06 08:07:58 PM PDT 24
Peak memory 207360 kb
Host smart-16ffcb16-30c7-4714-84ac-705c4c60b9c2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2360371499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.2360371499
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1770890413
Short name T2278
Test name
Test status
Simulation time 175815220 ps
CPU time 0.87 seconds
Started Aug 06 08:08:09 PM PDT 24
Finished Aug 06 08:08:10 PM PDT 24
Peak memory 207224 kb
Host smart-a9087a44-a545-4fa1-b92f-af7d7a9494a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17708
90413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1770890413
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.4185669956
Short name T2260
Test name
Test status
Simulation time 218686278 ps
CPU time 0.95 seconds
Started Aug 06 08:07:57 PM PDT 24
Finished Aug 06 08:07:58 PM PDT 24
Peak memory 207348 kb
Host smart-0cf7c6fa-8f38-44da-9132-6ae623570e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41856
69956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.4185669956
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1188950405
Short name T2258
Test name
Test status
Simulation time 156373268 ps
CPU time 0.84 seconds
Started Aug 06 08:08:03 PM PDT 24
Finished Aug 06 08:08:04 PM PDT 24
Peak memory 207296 kb
Host smart-1bd19268-6d7e-4a20-a9c9-f0b71a20f3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11889
50405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1188950405
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1619810352
Short name T1183
Test name
Test status
Simulation time 223313984 ps
CPU time 0.94 seconds
Started Aug 06 08:08:05 PM PDT 24
Finished Aug 06 08:08:06 PM PDT 24
Peak memory 207420 kb
Host smart-5358b14e-9097-4f0a-ba92-c637e2ba96cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16198
10352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1619810352
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2339764916
Short name T914
Test name
Test status
Simulation time 225046297 ps
CPU time 0.89 seconds
Started Aug 06 08:07:55 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 207348 kb
Host smart-108e9b20-d7d7-4ea2-a5d8-b930f20d6fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23397
64916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2339764916
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2951329409
Short name T3063
Test name
Test status
Simulation time 158590461 ps
CPU time 0.86 seconds
Started Aug 06 08:08:05 PM PDT 24
Finished Aug 06 08:08:06 PM PDT 24
Peak memory 207356 kb
Host smart-d4fed96c-882f-4fcb-9381-f2d27b7a3543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29513
29409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2951329409
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.912659595
Short name T1495
Test name
Test status
Simulation time 207090527 ps
CPU time 0.91 seconds
Started Aug 06 08:07:52 PM PDT 24
Finished Aug 06 08:07:53 PM PDT 24
Peak memory 207296 kb
Host smart-8c767e1c-dfe1-4365-b490-de967462ca89
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=912659595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.912659595
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1170330267
Short name T2697
Test name
Test status
Simulation time 144906052 ps
CPU time 0.8 seconds
Started Aug 06 08:07:56 PM PDT 24
Finished Aug 06 08:07:57 PM PDT 24
Peak memory 207324 kb
Host smart-d06d52c2-5a90-47fe-a27d-a6856f1a9c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11703
30267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1170330267
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.193099399
Short name T2462
Test name
Test status
Simulation time 60912880 ps
CPU time 0.72 seconds
Started Aug 06 08:07:55 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 207312 kb
Host smart-73d2b659-0104-4eaf-a43b-d9743c167c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19309
9399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.193099399
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.531246033
Short name T2938
Test name
Test status
Simulation time 8951803206 ps
CPU time 23.17 seconds
Started Aug 06 08:08:00 PM PDT 24
Finished Aug 06 08:08:23 PM PDT 24
Peak memory 215920 kb
Host smart-179643e7-fabf-4969-9caf-46d2c630be10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53124
6033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.531246033
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3452029333
Short name T799
Test name
Test status
Simulation time 194977134 ps
CPU time 0.98 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:08:02 PM PDT 24
Peak memory 207352 kb
Host smart-8057e242-0de4-4ffc-bd1c-2dd22ad5901d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34520
29333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3452029333
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3139791708
Short name T1841
Test name
Test status
Simulation time 220434745 ps
CPU time 0.99 seconds
Started Aug 06 08:08:06 PM PDT 24
Finished Aug 06 08:08:07 PM PDT 24
Peak memory 207320 kb
Host smart-17721e28-0a56-4e75-ac4e-288a8f1a7dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31397
91708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3139791708
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.3981183234
Short name T1248
Test name
Test status
Simulation time 215235823 ps
CPU time 0.99 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207416 kb
Host smart-4616872c-ba04-4348-ae83-f6654983748c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39811
83234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.3981183234
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.2008707466
Short name T2040
Test name
Test status
Simulation time 210840384 ps
CPU time 0.94 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:04 PM PDT 24
Peak memory 207352 kb
Host smart-8bcdeb5c-2650-461f-96c8-4686ef6ceec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20087
07466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.2008707466
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3825193687
Short name T1679
Test name
Test status
Simulation time 138592879 ps
CPU time 0.79 seconds
Started Aug 06 08:08:04 PM PDT 24
Finished Aug 06 08:08:05 PM PDT 24
Peak memory 207320 kb
Host smart-c6abe8be-cffd-4c3b-ab47-e0e290a3a3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38251
93687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3825193687
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_rx_full.3067898930
Short name T3113
Test name
Test status
Simulation time 289124221 ps
CPU time 1.08 seconds
Started Aug 06 08:08:04 PM PDT 24
Finished Aug 06 08:08:05 PM PDT 24
Peak memory 207320 kb
Host smart-d0a5567e-3768-461e-b7f1-e870e72c44bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30678
98930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.3067898930
Directory /workspace/42.usbdev_rx_full/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.419398176
Short name T3062
Test name
Test status
Simulation time 168692706 ps
CPU time 0.93 seconds
Started Aug 06 08:07:55 PM PDT 24
Finished Aug 06 08:07:56 PM PDT 24
Peak memory 207288 kb
Host smart-dfa1e98c-4bb2-480d-95e8-1bcd7532be2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41939
8176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.419398176
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3049216147
Short name T2492
Test name
Test status
Simulation time 154904110 ps
CPU time 0.86 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207324 kb
Host smart-f7da786e-e992-4d37-a8fc-50c4adde050a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30492
16147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3049216147
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.607634977
Short name T1701
Test name
Test status
Simulation time 263509690 ps
CPU time 1.1 seconds
Started Aug 06 08:08:03 PM PDT 24
Finished Aug 06 08:08:05 PM PDT 24
Peak memory 207440 kb
Host smart-971d8b83-cce1-44bb-9d17-3ff402bec8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60763
4977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.607634977
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2907103788
Short name T1809
Test name
Test status
Simulation time 3058629970 ps
CPU time 22.85 seconds
Started Aug 06 08:08:09 PM PDT 24
Finished Aug 06 08:08:32 PM PDT 24
Peak memory 224052 kb
Host smart-eff1bb7d-21ec-4f7e-97c2-f8d53fb5ce10
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2907103788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2907103788
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3623520039
Short name T2373
Test name
Test status
Simulation time 167926468 ps
CPU time 0.89 seconds
Started Aug 06 08:08:10 PM PDT 24
Finished Aug 06 08:08:11 PM PDT 24
Peak memory 207348 kb
Host smart-64fc88d9-b57a-408f-b50b-f0d16a7b85b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36235
20039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3623520039
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2118463322
Short name T687
Test name
Test status
Simulation time 161844037 ps
CPU time 0.94 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 207372 kb
Host smart-05fd17be-3034-47d9-89cc-e45161753b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21184
63322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2118463322
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.4147641787
Short name T2982
Test name
Test status
Simulation time 215165187 ps
CPU time 0.92 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 207316 kb
Host smart-90f09c08-e508-431a-b9c1-ec3efe589569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41476
41787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.4147641787
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.1774564510
Short name T2694
Test name
Test status
Simulation time 2137966203 ps
CPU time 59.5 seconds
Started Aug 06 08:08:04 PM PDT 24
Finished Aug 06 08:09:04 PM PDT 24
Peak memory 215604 kb
Host smart-e4c700e7-248e-4d9a-9991-a91577e40a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17745
64510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1774564510
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.2837461589
Short name T266
Test name
Test status
Simulation time 154277997 ps
CPU time 0.94 seconds
Started Aug 06 08:07:57 PM PDT 24
Finished Aug 06 08:07:58 PM PDT 24
Peak memory 207396 kb
Host smart-29095bbe-ee9b-4525-87bd-ea588889d319
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837461589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.2837461589
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.2159322333
Short name T2219
Test name
Test status
Simulation time 68575055 ps
CPU time 0.67 seconds
Started Aug 06 08:08:27 PM PDT 24
Finished Aug 06 08:08:27 PM PDT 24
Peak memory 207404 kb
Host smart-172e9121-94a6-4969-a066-c7e951fa4f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2159322333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.2159322333
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.671646498
Short name T638
Test name
Test status
Simulation time 6618641113 ps
CPU time 10 seconds
Started Aug 06 08:08:04 PM PDT 24
Finished Aug 06 08:08:14 PM PDT 24
Peak memory 215104 kb
Host smart-bb823b4b-22f3-44e1-8236-66aed0075f69
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671646498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_ao
n_wake_disconnect.671646498
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.116264814
Short name T2556
Test name
Test status
Simulation time 14411704339 ps
CPU time 17.54 seconds
Started Aug 06 08:08:12 PM PDT 24
Finished Aug 06 08:08:30 PM PDT 24
Peak memory 215892 kb
Host smart-c18f5bb4-920f-4ac0-ae64-168998510ed7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=116264814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.116264814
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.4276440122
Short name T2333
Test name
Test status
Simulation time 25852083832 ps
CPU time 31.07 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:39 PM PDT 24
Peak memory 215824 kb
Host smart-3056f902-27ef-41c0-b744-9e1a2e5fbf9e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276440122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.4276440122
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2342495281
Short name T2020
Test name
Test status
Simulation time 193067596 ps
CPU time 0.92 seconds
Started Aug 06 08:08:10 PM PDT 24
Finished Aug 06 08:08:11 PM PDT 24
Peak memory 207348 kb
Host smart-810e1055-11a5-4cb4-8846-98f942d86fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23424
95281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2342495281
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2182075303
Short name T2484
Test name
Test status
Simulation time 144183541 ps
CPU time 0.8 seconds
Started Aug 06 08:08:10 PM PDT 24
Finished Aug 06 08:08:11 PM PDT 24
Peak memory 207320 kb
Host smart-083f53b4-9f9c-4834-a2ab-15008eebb121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21820
75303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2182075303
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.230348210
Short name T2722
Test name
Test status
Simulation time 271407416 ps
CPU time 1.07 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:04 PM PDT 24
Peak memory 207292 kb
Host smart-cec8882d-884a-40de-be26-4443b4f0822d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23034
8210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.230348210
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1228055389
Short name T2585
Test name
Test status
Simulation time 749961818 ps
CPU time 1.97 seconds
Started Aug 06 08:08:16 PM PDT 24
Finished Aug 06 08:08:18 PM PDT 24
Peak memory 207588 kb
Host smart-9be024d7-b418-438c-be88-7648e17ffa9f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1228055389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1228055389
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.3119561225
Short name T2214
Test name
Test status
Simulation time 3405063044 ps
CPU time 30.64 seconds
Started Aug 06 08:08:00 PM PDT 24
Finished Aug 06 08:08:31 PM PDT 24
Peak memory 207636 kb
Host smart-d8ea5902-9704-4756-be67-a86124b272af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119561225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.3119561225
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.310742820
Short name T2230
Test name
Test status
Simulation time 709021924 ps
CPU time 1.74 seconds
Started Aug 06 08:08:13 PM PDT 24
Finished Aug 06 08:08:15 PM PDT 24
Peak memory 207428 kb
Host smart-e3817dc8-f61b-4b9c-a0ef-756002f3bdca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31074
2820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.310742820
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.963987036
Short name T1545
Test name
Test status
Simulation time 173773126 ps
CPU time 0.83 seconds
Started Aug 06 08:08:30 PM PDT 24
Finished Aug 06 08:08:31 PM PDT 24
Peak memory 207260 kb
Host smart-01952e6a-05bc-4855-b741-8aa56086940d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96398
7036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.963987036
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.2675969674
Short name T1464
Test name
Test status
Simulation time 33610914 ps
CPU time 0.7 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207276 kb
Host smart-84bfd064-4db4-4310-915d-ec2900eb8424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26759
69674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2675969674
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.200940006
Short name T2196
Test name
Test status
Simulation time 882962458 ps
CPU time 2.41 seconds
Started Aug 06 08:08:07 PM PDT 24
Finished Aug 06 08:08:10 PM PDT 24
Peak memory 207652 kb
Host smart-61e54040-ffc7-4e1c-976a-567d60b0a919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20094
0006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.200940006
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.645026248
Short name T1535
Test name
Test status
Simulation time 307245574 ps
CPU time 2.42 seconds
Started Aug 06 08:08:26 PM PDT 24
Finished Aug 06 08:08:28 PM PDT 24
Peak memory 206828 kb
Host smart-0d897967-6fa1-4896-b75e-c71c181b774e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64502
6248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.645026248
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3108561536
Short name T2229
Test name
Test status
Simulation time 183490401 ps
CPU time 0.98 seconds
Started Aug 06 08:08:12 PM PDT 24
Finished Aug 06 08:08:13 PM PDT 24
Peak memory 215776 kb
Host smart-b58dc6f9-838e-4877-8da3-f849150919fc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3108561536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3108561536
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.217100712
Short name T3030
Test name
Test status
Simulation time 146630830 ps
CPU time 0.83 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207352 kb
Host smart-53575be9-b0d8-47a5-a9c7-540338163d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21710
0712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.217100712
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1693677511
Short name T836
Test name
Test status
Simulation time 192487212 ps
CPU time 0.93 seconds
Started Aug 06 08:08:13 PM PDT 24
Finished Aug 06 08:08:14 PM PDT 24
Peak memory 207332 kb
Host smart-00d90abc-502e-44bf-8ebb-602e32a482fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16936
77511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1693677511
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.542795947
Short name T121
Test name
Test status
Simulation time 3515100645 ps
CPU time 94.39 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:09:35 PM PDT 24
Peak memory 224040 kb
Host smart-96452f6e-575e-4752-9a1a-f62607febada
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=542795947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.542795947
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.4131353388
Short name T738
Test name
Test status
Simulation time 11748477060 ps
CPU time 150.68 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:10:32 PM PDT 24
Peak memory 207556 kb
Host smart-cd2caf40-7d4a-43d3-b7fe-71c44e92c5f9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4131353388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.4131353388
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2962688384
Short name T1391
Test name
Test status
Simulation time 210019565 ps
CPU time 1 seconds
Started Aug 06 08:08:10 PM PDT 24
Finished Aug 06 08:08:11 PM PDT 24
Peak memory 207312 kb
Host smart-a6252511-ec96-4794-b1ba-bd9e65445667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29626
88384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2962688384
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.2034154957
Short name T1018
Test name
Test status
Simulation time 29913500970 ps
CPU time 47.01 seconds
Started Aug 06 08:08:17 PM PDT 24
Finished Aug 06 08:09:04 PM PDT 24
Peak memory 207636 kb
Host smart-4a0f137e-58b1-4dbe-bd10-6e254e1ae62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20341
54957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.2034154957
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.2422850054
Short name T2060
Test name
Test status
Simulation time 3963968804 ps
CPU time 5.94 seconds
Started Aug 06 08:08:09 PM PDT 24
Finished Aug 06 08:08:15 PM PDT 24
Peak memory 215916 kb
Host smart-565315b0-ad3f-4148-bfe4-69aef4308d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24228
50054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.2422850054
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.1394632058
Short name T2129
Test name
Test status
Simulation time 3702001090 ps
CPU time 36.28 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:44 PM PDT 24
Peak memory 224124 kb
Host smart-acf3a781-2636-4f4a-98ee-b32c61d74e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13946
32058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.1394632058
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.28959077
Short name T2928
Test name
Test status
Simulation time 3895434198 ps
CPU time 38.88 seconds
Started Aug 06 08:08:07 PM PDT 24
Finished Aug 06 08:08:46 PM PDT 24
Peak memory 216716 kb
Host smart-fbf5b4b2-47ff-4752-929c-1b3d81c02fa9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=28959077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.28959077
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.3940015887
Short name T2079
Test name
Test status
Simulation time 240114361 ps
CPU time 1.03 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207352 kb
Host smart-9fe922a5-ae99-42c5-9698-f818e5f21617
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3940015887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3940015887
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2102235191
Short name T2126
Test name
Test status
Simulation time 189934065 ps
CPU time 0.94 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207356 kb
Host smart-0321b43a-3018-422e-9ba7-5d8ad5c4d43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21022
35191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2102235191
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.215593893
Short name T952
Test name
Test status
Simulation time 3290091430 ps
CPU time 89.43 seconds
Started Aug 06 08:08:06 PM PDT 24
Finished Aug 06 08:09:36 PM PDT 24
Peak memory 217232 kb
Host smart-de098137-b6f1-4854-8806-d2c1b87fe6fc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=215593893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.215593893
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1057490909
Short name T1598
Test name
Test status
Simulation time 189268621 ps
CPU time 0.91 seconds
Started Aug 06 08:08:07 PM PDT 24
Finished Aug 06 08:08:08 PM PDT 24
Peak memory 207368 kb
Host smart-e4404b81-18ac-40fd-8f32-cde8cd747d27
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1057490909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1057490909
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2255697135
Short name T1654
Test name
Test status
Simulation time 146147389 ps
CPU time 0.91 seconds
Started Aug 06 08:08:12 PM PDT 24
Finished Aug 06 08:08:13 PM PDT 24
Peak memory 207420 kb
Host smart-23570a8a-7c6e-4903-8494-397523922edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22556
97135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2255697135
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3531702737
Short name T168
Test name
Test status
Simulation time 279758078 ps
CPU time 1.03 seconds
Started Aug 06 08:08:14 PM PDT 24
Finished Aug 06 08:08:15 PM PDT 24
Peak memory 207412 kb
Host smart-3d671cad-80c0-43ab-9423-e348d18b7f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35317
02737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3531702737
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2679154858
Short name T2915
Test name
Test status
Simulation time 168930574 ps
CPU time 0.84 seconds
Started Aug 06 08:08:19 PM PDT 24
Finished Aug 06 08:08:20 PM PDT 24
Peak memory 207316 kb
Host smart-dc178c67-9e4b-4539-a334-912298986848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26791
54858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2679154858
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.4107980391
Short name T544
Test name
Test status
Simulation time 154697168 ps
CPU time 0.83 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:08:02 PM PDT 24
Peak memory 207364 kb
Host smart-21ebcd5c-1965-4791-a0d1-cfe48fc05a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41079
80391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.4107980391
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3150866084
Short name T2433
Test name
Test status
Simulation time 179423363 ps
CPU time 0.87 seconds
Started Aug 06 08:08:02 PM PDT 24
Finished Aug 06 08:08:03 PM PDT 24
Peak memory 207400 kb
Host smart-6dae8cb2-4c99-400d-9741-0a85835723f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31508
66084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3150866084
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2748882755
Short name T1508
Test name
Test status
Simulation time 146002666 ps
CPU time 0.85 seconds
Started Aug 06 08:08:03 PM PDT 24
Finished Aug 06 08:08:04 PM PDT 24
Peak memory 207384 kb
Host smart-64e442c5-3a2a-4693-a12c-62b3fc05557e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27488
82755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2748882755
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3923555041
Short name T1727
Test name
Test status
Simulation time 229211350 ps
CPU time 0.99 seconds
Started Aug 06 08:08:07 PM PDT 24
Finished Aug 06 08:08:08 PM PDT 24
Peak memory 207388 kb
Host smart-d4d5d677-ea06-41e6-ad2b-b81c8a633298
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3923555041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3923555041
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2259856119
Short name T796
Test name
Test status
Simulation time 154769146 ps
CPU time 0.89 seconds
Started Aug 06 08:08:14 PM PDT 24
Finished Aug 06 08:08:15 PM PDT 24
Peak memory 207312 kb
Host smart-05365537-2cee-4164-bddc-58ebee1c9a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22598
56119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2259856119
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1801207428
Short name T35
Test name
Test status
Simulation time 38625317 ps
CPU time 0.7 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 207312 kb
Host smart-86fc58d7-f32d-4993-aa8f-e063479902a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18012
07428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1801207428
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1520491324
Short name T1650
Test name
Test status
Simulation time 17583577586 ps
CPU time 45 seconds
Started Aug 06 08:08:11 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 219976 kb
Host smart-f55080a2-5dda-40cd-86a7-3ef7351f1eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15204
91324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1520491324
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.622060418
Short name T1355
Test name
Test status
Simulation time 214193001 ps
CPU time 0.98 seconds
Started Aug 06 08:08:14 PM PDT 24
Finished Aug 06 08:08:15 PM PDT 24
Peak memory 207236 kb
Host smart-95e55fc0-d749-41ff-b316-f18a740bb9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62206
0418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.622060418
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3497058193
Short name T2308
Test name
Test status
Simulation time 224234040 ps
CPU time 0.93 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 207300 kb
Host smart-4722e368-2d37-41cd-8fd5-f3f1a560da3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34970
58193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3497058193
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.830387088
Short name T1850
Test name
Test status
Simulation time 241967975 ps
CPU time 1 seconds
Started Aug 06 08:08:15 PM PDT 24
Finished Aug 06 08:08:16 PM PDT 24
Peak memory 207376 kb
Host smart-cee757f0-a807-48ed-98b3-c5fc3c9cf91b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83038
7088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.830387088
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2866897883
Short name T2493
Test name
Test status
Simulation time 154477473 ps
CPU time 0.9 seconds
Started Aug 06 08:08:04 PM PDT 24
Finished Aug 06 08:08:05 PM PDT 24
Peak memory 207300 kb
Host smart-3621e8fc-af99-49c3-92bc-f653bd667243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28668
97883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2866897883
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2199498471
Short name T591
Test name
Test status
Simulation time 192686672 ps
CPU time 0.85 seconds
Started Aug 06 08:08:03 PM PDT 24
Finished Aug 06 08:08:04 PM PDT 24
Peak memory 207304 kb
Host smart-e16a5d26-652b-4eeb-881f-799e5596daf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21994
98471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2199498471
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1812290352
Short name T1546
Test name
Test status
Simulation time 188229518 ps
CPU time 0.88 seconds
Started Aug 06 08:08:09 PM PDT 24
Finished Aug 06 08:08:10 PM PDT 24
Peak memory 207280 kb
Host smart-de87e699-7a0f-4810-8d1e-9c30e812c6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18122
90352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1812290352
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3573716201
Short name T769
Test name
Test status
Simulation time 152337564 ps
CPU time 0.84 seconds
Started Aug 06 08:08:17 PM PDT 24
Finished Aug 06 08:08:18 PM PDT 24
Peak memory 207240 kb
Host smart-53914a93-4b81-4e7a-a70b-e38bdfaec97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35737
16201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3573716201
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1740035836
Short name T1451
Test name
Test status
Simulation time 216940342 ps
CPU time 0.97 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 207344 kb
Host smart-acb89288-78b9-4c88-b2a9-7520346cda95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17400
35836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1740035836
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.3193777691
Short name T1730
Test name
Test status
Simulation time 1583974781 ps
CPU time 43.55 seconds
Started Aug 06 08:08:15 PM PDT 24
Finished Aug 06 08:08:59 PM PDT 24
Peak memory 217212 kb
Host smart-377f6fd0-ef5f-43d0-9ac2-815ddb07730d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3193777691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.3193777691
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2874375095
Short name T951
Test name
Test status
Simulation time 191370924 ps
CPU time 0.94 seconds
Started Aug 06 08:08:01 PM PDT 24
Finished Aug 06 08:08:02 PM PDT 24
Peak memory 207368 kb
Host smart-07014d04-0326-402b-824c-73af6f5b23c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28743
75095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2874375095
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.1183140742
Short name T1368
Test name
Test status
Simulation time 200788137 ps
CPU time 0.92 seconds
Started Aug 06 08:08:06 PM PDT 24
Finished Aug 06 08:08:07 PM PDT 24
Peak memory 207368 kb
Host smart-9cc81e0a-13f5-4467-8d74-dd18ae018e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11831
40742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1183140742
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.519743723
Short name T1147
Test name
Test status
Simulation time 1312926422 ps
CPU time 3.04 seconds
Started Aug 06 08:08:15 PM PDT 24
Finished Aug 06 08:08:18 PM PDT 24
Peak memory 207520 kb
Host smart-caabcbc3-d1e9-4332-9c8a-6c3b525c0e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51974
3723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.519743723
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3022652316
Short name T2582
Test name
Test status
Simulation time 3883489461 ps
CPU time 29.28 seconds
Started Aug 06 08:08:15 PM PDT 24
Finished Aug 06 08:08:45 PM PDT 24
Peak memory 215904 kb
Host smart-761b605a-3873-466b-9647-bf3fb8a289fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30226
52316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3022652316
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.1852627384
Short name T1240
Test name
Test status
Simulation time 860104568 ps
CPU time 5.35 seconds
Started Aug 06 08:08:09 PM PDT 24
Finished Aug 06 08:08:14 PM PDT 24
Peak memory 207532 kb
Host smart-00a25c18-295b-441d-a5c1-9313abf36090
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852627384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.1852627384
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.1333863290
Short name T1326
Test name
Test status
Simulation time 33597256 ps
CPU time 0.7 seconds
Started Aug 06 08:08:23 PM PDT 24
Finished Aug 06 08:08:23 PM PDT 24
Peak memory 207512 kb
Host smart-37b13c7b-43e4-4a89-add6-9fbb3f5e73e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1333863290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.1333863290
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2023306959
Short name T1610
Test name
Test status
Simulation time 12220286568 ps
CPU time 15.54 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:24 PM PDT 24
Peak memory 207628 kb
Host smart-1054c963-1b62-4601-8d3b-bc706d5dfcba
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023306959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.2023306959
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.4245535928
Short name T13
Test name
Test status
Simulation time 20176858256 ps
CPU time 21.69 seconds
Started Aug 06 08:08:12 PM PDT 24
Finished Aug 06 08:08:34 PM PDT 24
Peak memory 207664 kb
Host smart-386cd564-3716-4f81-8d85-087e89314b41
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245535928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.4245535928
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.169961449
Short name T1684
Test name
Test status
Simulation time 30681129279 ps
CPU time 36.36 seconds
Started Aug 06 08:08:03 PM PDT 24
Finished Aug 06 08:08:39 PM PDT 24
Peak memory 206932 kb
Host smart-9787c3b3-ef44-4275-ad34-b31dba546365
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169961449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_ao
n_wake_resume.169961449
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2821376243
Short name T1920
Test name
Test status
Simulation time 154432364 ps
CPU time 0.88 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:08:21 PM PDT 24
Peak memory 207308 kb
Host smart-81f0e2d6-ba0a-49c3-a70f-b26cd6878505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28213
76243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2821376243
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.397599608
Short name T1226
Test name
Test status
Simulation time 163853259 ps
CPU time 0.86 seconds
Started Aug 06 08:08:06 PM PDT 24
Finished Aug 06 08:08:07 PM PDT 24
Peak memory 207336 kb
Host smart-82ba9b79-d5fe-41d1-a416-98eea33f6b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39759
9608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.397599608
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.2038983522
Short name T1907
Test name
Test status
Simulation time 184649064 ps
CPU time 0.89 seconds
Started Aug 06 08:08:18 PM PDT 24
Finished Aug 06 08:08:19 PM PDT 24
Peak memory 207372 kb
Host smart-8317e09a-9f91-4551-ade2-ff3cb446441b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20389
83522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.2038983522
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.4006327077
Short name T2521
Test name
Test status
Simulation time 454852488 ps
CPU time 1.36 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:08:21 PM PDT 24
Peak memory 207376 kb
Host smart-6966b0f0-2943-46eb-8433-a03dfee354e8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4006327077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.4006327077
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1023077395
Short name T852
Test name
Test status
Simulation time 20623064538 ps
CPU time 34.55 seconds
Started Aug 06 08:08:15 PM PDT 24
Finished Aug 06 08:08:50 PM PDT 24
Peak memory 207632 kb
Host smart-5779f198-ed5d-4513-a8b1-16045cf41c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10230
77395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1023077395
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.2950392650
Short name T2945
Test name
Test status
Simulation time 1687248728 ps
CPU time 40.85 seconds
Started Aug 06 08:08:06 PM PDT 24
Finished Aug 06 08:08:47 PM PDT 24
Peak memory 207568 kb
Host smart-55e5c0ac-51a3-4fb2-a1d7-944d9aebcb7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950392650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.2950392650
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.4181062562
Short name T1493
Test name
Test status
Simulation time 786224343 ps
CPU time 1.97 seconds
Started Aug 06 08:08:06 PM PDT 24
Finished Aug 06 08:08:08 PM PDT 24
Peak memory 207344 kb
Host smart-0f40567b-05a4-4d3f-941d-545ee781f432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41810
62562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.4181062562
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.70241607
Short name T42
Test name
Test status
Simulation time 184276863 ps
CPU time 0.88 seconds
Started Aug 06 08:08:06 PM PDT 24
Finished Aug 06 08:08:07 PM PDT 24
Peak memory 207336 kb
Host smart-061a33a8-9edf-4d76-a11a-3164fa0ae4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70241
607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.70241607
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1879589447
Short name T260
Test name
Test status
Simulation time 42676894 ps
CPU time 0.74 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:09 PM PDT 24
Peak memory 207316 kb
Host smart-0896222b-80f2-45ff-bec2-eabd7a62c5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18795
89447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1879589447
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1860194519
Short name T1381
Test name
Test status
Simulation time 784282841 ps
CPU time 2.3 seconds
Started Aug 06 08:08:17 PM PDT 24
Finished Aug 06 08:08:20 PM PDT 24
Peak memory 207576 kb
Host smart-fb15a301-f67b-48c9-a11d-b6da7dea524d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18601
94519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1860194519
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2407261779
Short name T1251
Test name
Test status
Simulation time 419477634 ps
CPU time 2.56 seconds
Started Aug 06 08:08:09 PM PDT 24
Finished Aug 06 08:08:11 PM PDT 24
Peak memory 207512 kb
Host smart-36406e7c-2ab8-4517-9798-97de4560712e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24072
61779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2407261779
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.4133098957
Short name T1075
Test name
Test status
Simulation time 238395282 ps
CPU time 1.22 seconds
Started Aug 06 08:08:17 PM PDT 24
Finished Aug 06 08:08:19 PM PDT 24
Peak memory 215736 kb
Host smart-cf15de1c-f159-41b3-8130-585f9765ef90
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4133098957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.4133098957
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3234480124
Short name T1568
Test name
Test status
Simulation time 173811052 ps
CPU time 0.86 seconds
Started Aug 06 08:08:00 PM PDT 24
Finished Aug 06 08:08:01 PM PDT 24
Peak memory 207372 kb
Host smart-7cd5b7e0-a6c0-4b2a-aa86-5aa6fb234b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32344
80124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3234480124
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1395406554
Short name T2658
Test name
Test status
Simulation time 190353598 ps
CPU time 0.99 seconds
Started Aug 06 08:08:40 PM PDT 24
Finished Aug 06 08:08:41 PM PDT 24
Peak memory 207292 kb
Host smart-9b84534e-e9ce-4134-b688-f36e326cfa6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13954
06554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1395406554
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1363894377
Short name T1331
Test name
Test status
Simulation time 4401479790 ps
CPU time 43.39 seconds
Started Aug 06 08:08:07 PM PDT 24
Finished Aug 06 08:08:50 PM PDT 24
Peak memory 218320 kb
Host smart-89b55b0b-b72f-428f-b521-38b545fc7637
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1363894377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1363894377
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.2220035836
Short name T2783
Test name
Test status
Simulation time 11687737056 ps
CPU time 88.91 seconds
Started Aug 06 08:08:11 PM PDT 24
Finished Aug 06 08:09:40 PM PDT 24
Peak memory 207600 kb
Host smart-0c6d12a3-6d65-41bd-b8d8-3d2c6c6bba98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2220035836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.2220035836
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1519397759
Short name T815
Test name
Test status
Simulation time 239166380 ps
CPU time 0.96 seconds
Started Aug 06 08:08:19 PM PDT 24
Finished Aug 06 08:08:20 PM PDT 24
Peak memory 207376 kb
Host smart-59e40b10-4677-4f31-9a73-c80a09864344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15193
97759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1519397759
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.2674677367
Short name T246
Test name
Test status
Simulation time 15851965941 ps
CPU time 21.51 seconds
Started Aug 06 08:08:13 PM PDT 24
Finished Aug 06 08:08:35 PM PDT 24
Peak memory 207660 kb
Host smart-265b2791-c86c-4f08-afc8-41bb73250546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26746
77367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2674677367
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1030884527
Short name T2057
Test name
Test status
Simulation time 10712588221 ps
CPU time 13.71 seconds
Started Aug 06 08:08:19 PM PDT 24
Finished Aug 06 08:08:33 PM PDT 24
Peak memory 207624 kb
Host smart-02830c75-051b-4515-a25e-e3e9da2cbbcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10308
84527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1030884527
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.3965606761
Short name T176
Test name
Test status
Simulation time 3981916383 ps
CPU time 29.8 seconds
Started Aug 06 08:08:12 PM PDT 24
Finished Aug 06 08:08:42 PM PDT 24
Peak memory 224116 kb
Host smart-cc2d6ff6-4378-4c2e-ac41-f1c16ea9ab41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39656
06761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.3965606761
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1918647739
Short name T4
Test name
Test status
Simulation time 2277702563 ps
CPU time 16.95 seconds
Started Aug 06 08:08:14 PM PDT 24
Finished Aug 06 08:08:31 PM PDT 24
Peak memory 217532 kb
Host smart-0486e9e1-ad38-46ca-aa55-326d8853b2b4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1918647739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1918647739
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.3077907197
Short name T1857
Test name
Test status
Simulation time 245846069 ps
CPU time 0.98 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:08:21 PM PDT 24
Peak memory 207348 kb
Host smart-2eaf15ad-8dde-47cf-a527-e9099d07adaa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3077907197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.3077907197
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2164163740
Short name T2997
Test name
Test status
Simulation time 191146900 ps
CPU time 0.95 seconds
Started Aug 06 08:08:23 PM PDT 24
Finished Aug 06 08:08:24 PM PDT 24
Peak memory 207360 kb
Host smart-aab5d9fe-a52b-4067-b416-339f7de13924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21641
63740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2164163740
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.949776836
Short name T710
Test name
Test status
Simulation time 1979790253 ps
CPU time 18.77 seconds
Started Aug 06 08:08:14 PM PDT 24
Finished Aug 06 08:08:33 PM PDT 24
Peak memory 215688 kb
Host smart-09fe04fb-c941-46e5-b9d9-0e622454f786
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=949776836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.949776836
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.3311894119
Short name T1459
Test name
Test status
Simulation time 159267222 ps
CPU time 0.88 seconds
Started Aug 06 08:08:15 PM PDT 24
Finished Aug 06 08:08:16 PM PDT 24
Peak memory 207380 kb
Host smart-8a66a4ec-57f2-4364-a31c-d6a377e82cb4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3311894119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.3311894119
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.4227159522
Short name T1342
Test name
Test status
Simulation time 157060950 ps
CPU time 0.9 seconds
Started Aug 06 08:08:15 PM PDT 24
Finished Aug 06 08:08:16 PM PDT 24
Peak memory 207344 kb
Host smart-66ba7b59-5e77-487e-b542-6a441065ac18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42271
59522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.4227159522
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.732007519
Short name T151
Test name
Test status
Simulation time 216315956 ps
CPU time 0.93 seconds
Started Aug 06 08:08:22 PM PDT 24
Finished Aug 06 08:08:23 PM PDT 24
Peak memory 207292 kb
Host smart-7429d34a-9f20-4e4d-8408-ed489cae0a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73200
7519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.732007519
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.1144334219
Short name T129
Test name
Test status
Simulation time 175036850 ps
CPU time 0.88 seconds
Started Aug 06 08:08:33 PM PDT 24
Finished Aug 06 08:08:34 PM PDT 24
Peak memory 207340 kb
Host smart-8aeeaf01-9052-4456-a989-92c584f81b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11443
34219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.1144334219
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3547328960
Short name T1105
Test name
Test status
Simulation time 174321970 ps
CPU time 0.91 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:08:21 PM PDT 24
Peak memory 207216 kb
Host smart-057744ba-1ae3-4d0c-9f40-acb3ee9f5fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35473
28960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3547328960
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3887360313
Short name T465
Test name
Test status
Simulation time 181499370 ps
CPU time 0.9 seconds
Started Aug 06 08:08:22 PM PDT 24
Finished Aug 06 08:08:23 PM PDT 24
Peak memory 207372 kb
Host smart-286984f2-1513-4a9c-b0d3-38b41144be03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38873
60313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3887360313
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2424735507
Short name T3039
Test name
Test status
Simulation time 153116191 ps
CPU time 0.82 seconds
Started Aug 06 08:08:22 PM PDT 24
Finished Aug 06 08:08:23 PM PDT 24
Peak memory 207388 kb
Host smart-03bc936d-297e-484f-a3a6-b575b178c994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24247
35507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2424735507
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.762857516
Short name T1132
Test name
Test status
Simulation time 223457734 ps
CPU time 1.02 seconds
Started Aug 06 08:08:36 PM PDT 24
Finished Aug 06 08:08:37 PM PDT 24
Peak memory 207360 kb
Host smart-5c3a7b60-97da-4586-92cc-eaeb465ccb1d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=762857516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.762857516
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3883813776
Short name T2803
Test name
Test status
Simulation time 169510693 ps
CPU time 0.92 seconds
Started Aug 06 08:08:16 PM PDT 24
Finished Aug 06 08:08:17 PM PDT 24
Peak memory 207340 kb
Host smart-b8548ca2-47d5-4d7b-9223-ca829938efa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38838
13776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3883813776
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3848990759
Short name T2387
Test name
Test status
Simulation time 39453402 ps
CPU time 0.69 seconds
Started Aug 06 08:08:18 PM PDT 24
Finished Aug 06 08:08:19 PM PDT 24
Peak memory 207364 kb
Host smart-9b3ee8b9-3d6a-40a3-9a4a-1cff5e964960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38489
90759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3848990759
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.861149296
Short name T2420
Test name
Test status
Simulation time 8290748473 ps
CPU time 19.9 seconds
Started Aug 06 08:08:37 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 215784 kb
Host smart-8dec50fa-5c1c-4e38-87e5-4e9142d2c032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86114
9296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.861149296
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.209702234
Short name T1677
Test name
Test status
Simulation time 213176263 ps
CPU time 0.95 seconds
Started Aug 06 08:08:19 PM PDT 24
Finished Aug 06 08:08:20 PM PDT 24
Peak memory 207364 kb
Host smart-d736f8c8-ca96-4460-a5e2-9bb65954d9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20970
2234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.209702234
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2903417419
Short name T1877
Test name
Test status
Simulation time 176660240 ps
CPU time 0.86 seconds
Started Aug 06 08:08:27 PM PDT 24
Finished Aug 06 08:08:28 PM PDT 24
Peak memory 207352 kb
Host smart-b87e572a-5fb4-4c99-9cc1-ef846c4acec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034
17419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2903417419
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.1336344597
Short name T1980
Test name
Test status
Simulation time 218312484 ps
CPU time 1.02 seconds
Started Aug 06 08:08:36 PM PDT 24
Finished Aug 06 08:08:37 PM PDT 24
Peak memory 207352 kb
Host smart-865e94b2-7418-4b81-805f-11cc27381114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13363
44597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1336344597
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3999862208
Short name T2384
Test name
Test status
Simulation time 171652796 ps
CPU time 0.88 seconds
Started Aug 06 08:08:17 PM PDT 24
Finished Aug 06 08:08:18 PM PDT 24
Peak memory 207316 kb
Host smart-55e30279-d22c-40f1-9db2-a2782e673990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39998
62208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3999862208
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.972069196
Short name T2058
Test name
Test status
Simulation time 219857504 ps
CPU time 0.92 seconds
Started Aug 06 08:08:18 PM PDT 24
Finished Aug 06 08:08:19 PM PDT 24
Peak memory 207452 kb
Host smart-b550c533-e5eb-4a94-96d8-cbb0a20c824c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97206
9196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.972069196
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_rx_full.3899072744
Short name T322
Test name
Test status
Simulation time 241296630 ps
CPU time 1.08 seconds
Started Aug 06 08:08:08 PM PDT 24
Finished Aug 06 08:08:10 PM PDT 24
Peak memory 207412 kb
Host smart-adc62fe6-fcf2-425f-9405-8447683c87be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38990
72744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.3899072744
Directory /workspace/44.usbdev_rx_full/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.648563592
Short name T1372
Test name
Test status
Simulation time 192929083 ps
CPU time 0.86 seconds
Started Aug 06 08:08:18 PM PDT 24
Finished Aug 06 08:08:19 PM PDT 24
Peak memory 207380 kb
Host smart-180b47cb-3593-491b-8114-005736b118f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64856
3592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.648563592
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3823389524
Short name T1639
Test name
Test status
Simulation time 149995183 ps
CPU time 0.86 seconds
Started Aug 06 08:08:19 PM PDT 24
Finished Aug 06 08:08:19 PM PDT 24
Peak memory 207372 kb
Host smart-70b0744c-271c-4909-addb-a42613f78ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38233
89524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3823389524
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.991662855
Short name T184
Test name
Test status
Simulation time 228335932 ps
CPU time 1.06 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207356 kb
Host smart-212d840c-5ed7-4e51-86a1-d17a30556605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99166
2855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.991662855
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.1769145717
Short name T1883
Test name
Test status
Simulation time 2516856200 ps
CPU time 71.6 seconds
Started Aug 06 08:08:23 PM PDT 24
Finished Aug 06 08:09:34 PM PDT 24
Peak memory 215856 kb
Host smart-cb3ed2a4-aeb4-4078-abb4-43c2eb89785f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1769145717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1769145717
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3108076139
Short name T722
Test name
Test status
Simulation time 194135514 ps
CPU time 0.9 seconds
Started Aug 06 08:08:24 PM PDT 24
Finished Aug 06 08:08:25 PM PDT 24
Peak memory 207356 kb
Host smart-62b47f0b-7617-4f03-b50d-4f3676d68082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31080
76139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3108076139
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.36150530
Short name T1614
Test name
Test status
Simulation time 175143284 ps
CPU time 0.92 seconds
Started Aug 06 08:08:34 PM PDT 24
Finished Aug 06 08:08:35 PM PDT 24
Peak memory 207372 kb
Host smart-4566d15d-990c-4033-805a-06929e63299c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36150
530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.36150530
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.135958491
Short name T2898
Test name
Test status
Simulation time 1228718497 ps
CPU time 3.12 seconds
Started Aug 06 08:08:17 PM PDT 24
Finished Aug 06 08:08:20 PM PDT 24
Peak memory 207500 kb
Host smart-fe4e54e2-92a4-4085-8d25-511edc59265a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13595
8491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.135958491
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1370495723
Short name T1125
Test name
Test status
Simulation time 3444106576 ps
CPU time 100.93 seconds
Started Aug 06 08:08:31 PM PDT 24
Finished Aug 06 08:10:12 PM PDT 24
Peak memory 217228 kb
Host smart-1f0069b9-5166-40ce-b476-574fd86d163a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13704
95723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1370495723
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.139130886
Short name T2361
Test name
Test status
Simulation time 1458971492 ps
CPU time 33.57 seconds
Started Aug 06 08:08:24 PM PDT 24
Finished Aug 06 08:08:58 PM PDT 24
Peak memory 207572 kb
Host smart-a874d43e-e3f6-48d5-a33f-cb66cf9bc41b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139130886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_host
_handshake.139130886
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.327092685
Short name T1055
Test name
Test status
Simulation time 54091151 ps
CPU time 0.68 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207488 kb
Host smart-80a811ee-02e2-42af-b88d-51e98cad1e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=327092685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.327092685
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2458975879
Short name T118
Test name
Test status
Simulation time 5357121259 ps
CPU time 7.47 seconds
Started Aug 06 08:08:16 PM PDT 24
Finished Aug 06 08:08:23 PM PDT 24
Peak memory 216048 kb
Host smart-c55b16ef-293d-4458-9e41-14df794c146f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458975879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.2458975879
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1974856215
Short name T2111
Test name
Test status
Simulation time 18463064267 ps
CPU time 23.18 seconds
Started Aug 06 08:08:19 PM PDT 24
Finished Aug 06 08:08:47 PM PDT 24
Peak memory 207676 kb
Host smart-f98978fd-9094-404a-b81f-36dedac390cb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974856215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1974856215
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3490829983
Short name T2746
Test name
Test status
Simulation time 31198317119 ps
CPU time 36.47 seconds
Started Aug 06 08:08:25 PM PDT 24
Finished Aug 06 08:09:02 PM PDT 24
Peak memory 207584 kb
Host smart-d00cabee-fae6-4232-bded-ab5f0eb6b0c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490829983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.3490829983
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.4198824739
Short name T2137
Test name
Test status
Simulation time 160526804 ps
CPU time 0.91 seconds
Started Aug 06 08:08:14 PM PDT 24
Finished Aug 06 08:08:16 PM PDT 24
Peak memory 207312 kb
Host smart-287e724e-f6c8-4c84-8755-1873685ce5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41988
24739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.4198824739
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.400287557
Short name T1258
Test name
Test status
Simulation time 146063149 ps
CPU time 0.86 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207316 kb
Host smart-04aa6eff-4247-4f78-b632-cc16990c6c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40028
7557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.400287557
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2129230662
Short name T1750
Test name
Test status
Simulation time 169756580 ps
CPU time 0.86 seconds
Started Aug 06 08:08:19 PM PDT 24
Finished Aug 06 08:08:20 PM PDT 24
Peak memory 207380 kb
Host smart-d1470500-7f8a-4366-af6f-91e04ab26890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21292
30662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2129230662
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3530967678
Short name T2268
Test name
Test status
Simulation time 337549110 ps
CPU time 1.21 seconds
Started Aug 06 08:08:28 PM PDT 24
Finished Aug 06 08:08:30 PM PDT 24
Peak memory 207308 kb
Host smart-52338434-b712-4f19-a586-34974b766709
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3530967678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3530967678
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.3612616671
Short name T1146
Test name
Test status
Simulation time 22401046239 ps
CPU time 38.57 seconds
Started Aug 06 08:08:19 PM PDT 24
Finished Aug 06 08:08:58 PM PDT 24
Peak memory 207700 kb
Host smart-f85ab02c-838f-41d8-b234-85f56121fb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36126
16671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3612616671
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.238584634
Short name T2168
Test name
Test status
Simulation time 1567518282 ps
CPU time 36.86 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:58 PM PDT 24
Peak memory 207576 kb
Host smart-2e53781d-7d80-47b7-85aa-fdd507b136c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238584634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.238584634
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.793371754
Short name T1843
Test name
Test status
Simulation time 700173715 ps
CPU time 1.84 seconds
Started Aug 06 08:08:30 PM PDT 24
Finished Aug 06 08:08:32 PM PDT 24
Peak memory 207332 kb
Host smart-e56910db-d99f-4842-bcc6-1a9d637d70a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79337
1754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.793371754
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1208405529
Short name T1050
Test name
Test status
Simulation time 140329447 ps
CPU time 0.84 seconds
Started Aug 06 08:08:11 PM PDT 24
Finished Aug 06 08:08:12 PM PDT 24
Peak memory 207260 kb
Host smart-fa1837cd-877c-4c04-b589-b91353953804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12084
05529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1208405529
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.618764731
Short name T1791
Test name
Test status
Simulation time 56437303 ps
CPU time 0.7 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207324 kb
Host smart-916e4079-6a01-48dd-981f-681c1a20a9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61876
4731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.618764731
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.4007420618
Short name T1785
Test name
Test status
Simulation time 815361271 ps
CPU time 2.16 seconds
Started Aug 06 08:08:37 PM PDT 24
Finished Aug 06 08:08:39 PM PDT 24
Peak memory 207508 kb
Host smart-06d8babf-54a8-4456-9484-f0b03ce4aeb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40074
20618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.4007420618
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_types.1660396046
Short name T364
Test name
Test status
Simulation time 743135979 ps
CPU time 1.88 seconds
Started Aug 06 08:08:17 PM PDT 24
Finished Aug 06 08:08:18 PM PDT 24
Peak memory 207340 kb
Host smart-d00dc12c-bec5-403f-a9ba-77b3ed97d126
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1660396046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.1660396046
Directory /workspace/45.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.4277149228
Short name T2487
Test name
Test status
Simulation time 211316619 ps
CPU time 1.47 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207492 kb
Host smart-9ff133e3-5f96-4b62-a0af-5be3de0c7db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42771
49228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.4277149228
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.1100924343
Short name T1811
Test name
Test status
Simulation time 229511827 ps
CPU time 1.19 seconds
Started Aug 06 08:08:17 PM PDT 24
Finished Aug 06 08:08:18 PM PDT 24
Peak memory 215732 kb
Host smart-2d355a29-3d48-4853-af0a-72e293eb0ef2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1100924343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.1100924343
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1835376784
Short name T2422
Test name
Test status
Simulation time 138645931 ps
CPU time 0.8 seconds
Started Aug 06 08:08:26 PM PDT 24
Finished Aug 06 08:08:27 PM PDT 24
Peak memory 207340 kb
Host smart-79766ec1-60eb-457b-9d86-7a87d3bb476c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18353
76784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1835376784
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3793146765
Short name T1688
Test name
Test status
Simulation time 236034738 ps
CPU time 1.03 seconds
Started Aug 06 08:08:25 PM PDT 24
Finished Aug 06 08:08:26 PM PDT 24
Peak memory 207372 kb
Host smart-02772341-33bc-4cc5-92e8-924337198f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37931
46765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3793146765
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.2679863305
Short name T2275
Test name
Test status
Simulation time 3868616578 ps
CPU time 108 seconds
Started Aug 06 08:08:34 PM PDT 24
Finished Aug 06 08:10:22 PM PDT 24
Peak memory 218172 kb
Host smart-6d227725-ee48-42bd-b081-966df990370c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2679863305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2679863305
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.3167050474
Short name T1804
Test name
Test status
Simulation time 6536278008 ps
CPU time 49.23 seconds
Started Aug 06 08:08:29 PM PDT 24
Finished Aug 06 08:09:19 PM PDT 24
Peak memory 207592 kb
Host smart-e83f4389-4b9f-44f1-b65d-8e1e8b44414b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3167050474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.3167050474
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1050063271
Short name T953
Test name
Test status
Simulation time 232836795 ps
CPU time 0.94 seconds
Started Aug 06 08:08:19 PM PDT 24
Finished Aug 06 08:08:20 PM PDT 24
Peak memory 207300 kb
Host smart-f3d79fcd-d03e-41d9-9a8d-6eedeabecfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10500
63271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1050063271
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.3401025146
Short name T946
Test name
Test status
Simulation time 29254589002 ps
CPU time 44.42 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:09:06 PM PDT 24
Peak memory 207608 kb
Host smart-0d800d35-988b-4a9b-bcaa-c4e0eafb1f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34010
25146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.3401025146
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2475434159
Short name T889
Test name
Test status
Simulation time 4634535673 ps
CPU time 7.45 seconds
Started Aug 06 08:08:22 PM PDT 24
Finished Aug 06 08:08:30 PM PDT 24
Peak memory 215992 kb
Host smart-37bdfc0d-3799-4bcf-93c0-07f78d52d2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
34159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2475434159
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.3164116361
Short name T1620
Test name
Test status
Simulation time 4936678879 ps
CPU time 37.23 seconds
Started Aug 06 08:08:18 PM PDT 24
Finished Aug 06 08:08:55 PM PDT 24
Peak memory 224008 kb
Host smart-3d9f91fc-59c3-4ec7-9ce7-3e9d76f93855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31641
16361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.3164116361
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.1038524598
Short name T2927
Test name
Test status
Simulation time 2744304223 ps
CPU time 21.53 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:08:42 PM PDT 24
Peak memory 224016 kb
Host smart-a4b59751-6cc7-4c57-9e8f-bf039214dd83
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1038524598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.1038524598
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.1455232255
Short name T1810
Test name
Test status
Simulation time 239224385 ps
CPU time 0.97 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:08:21 PM PDT 24
Peak memory 207324 kb
Host smart-58a4532c-d7fe-4563-9338-1d962b75b41c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1455232255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.1455232255
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3409899000
Short name T1578
Test name
Test status
Simulation time 220490683 ps
CPU time 1 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:27 PM PDT 24
Peak memory 207384 kb
Host smart-265f33a8-a975-4e3f-a682-705c22cdbe54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34098
99000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3409899000
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.1994973876
Short name T208
Test name
Test status
Simulation time 2754657422 ps
CPU time 79.28 seconds
Started Aug 06 08:08:37 PM PDT 24
Finished Aug 06 08:09:56 PM PDT 24
Peak memory 215812 kb
Host smart-ee05206b-d60b-4fb4-811c-5895c9e6070f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1994973876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1994973876
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1492768987
Short name T2781
Test name
Test status
Simulation time 227557707 ps
CPU time 0.93 seconds
Started Aug 06 08:08:34 PM PDT 24
Finished Aug 06 08:08:35 PM PDT 24
Peak memory 207320 kb
Host smart-2f26c5cf-1b2a-489d-9163-f364224a6d03
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1492768987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1492768987
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1825652055
Short name T1436
Test name
Test status
Simulation time 150804547 ps
CPU time 0.82 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207384 kb
Host smart-bc2d8a83-57f2-453f-89a4-9657116e930c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18256
52055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1825652055
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2072601926
Short name T166
Test name
Test status
Simulation time 246034620 ps
CPU time 1.01 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207376 kb
Host smart-0e0fecc7-5baf-4166-8ed9-4aec3af6cc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20726
01926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2072601926
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.342769545
Short name T2066
Test name
Test status
Simulation time 216636086 ps
CPU time 0.94 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207360 kb
Host smart-ce42bb1f-50eb-4f6a-b5e7-c31233479292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34276
9545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.342769545
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3458950189
Short name T2073
Test name
Test status
Simulation time 149387067 ps
CPU time 0.81 seconds
Started Aug 06 08:08:44 PM PDT 24
Finished Aug 06 08:08:45 PM PDT 24
Peak memory 207388 kb
Host smart-fdf41416-f7be-4178-b323-227d304bd853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34589
50189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3458950189
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1269149551
Short name T856
Test name
Test status
Simulation time 175130499 ps
CPU time 0.88 seconds
Started Aug 06 08:08:15 PM PDT 24
Finished Aug 06 08:08:16 PM PDT 24
Peak memory 207320 kb
Host smart-455d42f8-0630-4e2a-9ccc-f9b0fc006154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12691
49551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1269149551
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1819618106
Short name T1173
Test name
Test status
Simulation time 181181578 ps
CPU time 0.88 seconds
Started Aug 06 08:08:16 PM PDT 24
Finished Aug 06 08:08:17 PM PDT 24
Peak memory 207388 kb
Host smart-8e6f1611-8299-41bd-8c06-7fc45e75d44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18196
18106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1819618106
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.320723668
Short name T1875
Test name
Test status
Simulation time 258355583 ps
CPU time 1.03 seconds
Started Aug 06 08:08:31 PM PDT 24
Finished Aug 06 08:08:32 PM PDT 24
Peak memory 207316 kb
Host smart-c6538c37-a3fc-464d-989c-b3bd269dfead
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=320723668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.320723668
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2838179904
Short name T1136
Test name
Test status
Simulation time 173468738 ps
CPU time 0.84 seconds
Started Aug 06 08:08:45 PM PDT 24
Finished Aug 06 08:08:46 PM PDT 24
Peak memory 207280 kb
Host smart-8be7c569-5f81-4e8f-af4b-c46cb903da23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28381
79904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2838179904
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1814238156
Short name T2465
Test name
Test status
Simulation time 39505342 ps
CPU time 0.68 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:08:21 PM PDT 24
Peak memory 207336 kb
Host smart-40f41091-0ed0-457d-9961-ba62e37abb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18142
38156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1814238156
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1709165734
Short name T1460
Test name
Test status
Simulation time 18303438684 ps
CPU time 41.4 seconds
Started Aug 06 08:08:35 PM PDT 24
Finished Aug 06 08:09:16 PM PDT 24
Peak memory 215868 kb
Host smart-adaaff3b-365d-4f8a-a072-5bbb95ea8fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17091
65734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1709165734
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3144860494
Short name T2584
Test name
Test status
Simulation time 162150454 ps
CPU time 0.86 seconds
Started Aug 06 08:08:30 PM PDT 24
Finished Aug 06 08:08:31 PM PDT 24
Peak memory 207324 kb
Host smart-e69dfbfa-98c9-49f1-a973-85e3e9bf5a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31448
60494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3144860494
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2054426218
Short name T3071
Test name
Test status
Simulation time 208137760 ps
CPU time 0.97 seconds
Started Aug 06 08:08:15 PM PDT 24
Finished Aug 06 08:08:16 PM PDT 24
Peak memory 207320 kb
Host smart-a33806ea-451a-41d3-ab50-67cf56745550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20544
26218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2054426218
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3866391259
Short name T791
Test name
Test status
Simulation time 249704428 ps
CPU time 0.93 seconds
Started Aug 06 08:08:23 PM PDT 24
Finished Aug 06 08:08:24 PM PDT 24
Peak memory 207324 kb
Host smart-4909bced-c6a1-4886-b110-716121a7bc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38663
91259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3866391259
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.4265806191
Short name T752
Test name
Test status
Simulation time 186792685 ps
CPU time 0.97 seconds
Started Aug 06 08:08:23 PM PDT 24
Finished Aug 06 08:08:24 PM PDT 24
Peak memory 207324 kb
Host smart-c43d8c90-2998-4e75-beea-d0d6aa7ef9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42658
06191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.4265806191
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2833778690
Short name T2440
Test name
Test status
Simulation time 179257939 ps
CPU time 0.94 seconds
Started Aug 06 08:08:43 PM PDT 24
Finished Aug 06 08:08:44 PM PDT 24
Peak memory 207372 kb
Host smart-abb1fd10-9998-4c7b-98dd-551f552dbc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28337
78690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2833778690
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_rx_full.3396730877
Short name T2006
Test name
Test status
Simulation time 342222303 ps
CPU time 1.11 seconds
Started Aug 06 08:08:44 PM PDT 24
Finished Aug 06 08:08:45 PM PDT 24
Peak memory 207356 kb
Host smart-0896b197-d44a-4432-bd6a-4a980887bde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33967
30877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.3396730877
Directory /workspace/45.usbdev_rx_full/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2828540014
Short name T2448
Test name
Test status
Simulation time 153063222 ps
CPU time 0.83 seconds
Started Aug 06 08:08:32 PM PDT 24
Finished Aug 06 08:08:33 PM PDT 24
Peak memory 207164 kb
Host smart-c4d08904-1a4b-4913-924c-d86126846640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285
40014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2828540014
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2731569746
Short name T2218
Test name
Test status
Simulation time 187315375 ps
CPU time 0.87 seconds
Started Aug 06 08:08:22 PM PDT 24
Finished Aug 06 08:08:23 PM PDT 24
Peak memory 207380 kb
Host smart-4bce8e07-121a-4255-9a05-dbfbc3a41a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
69746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2731569746
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3488530741
Short name T569
Test name
Test status
Simulation time 216278182 ps
CPU time 0.99 seconds
Started Aug 06 08:08:45 PM PDT 24
Finished Aug 06 08:08:46 PM PDT 24
Peak memory 207364 kb
Host smart-ddc52e8c-3c03-4c62-9104-60a47beabcce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34885
30741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3488530741
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.14439719
Short name T2276
Test name
Test status
Simulation time 2448703065 ps
CPU time 24.62 seconds
Started Aug 06 08:08:44 PM PDT 24
Finished Aug 06 08:09:14 PM PDT 24
Peak memory 217632 kb
Host smart-18aafd08-6552-445f-a056-608e7b5fc6fb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=14439719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.14439719
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1268916253
Short name T826
Test name
Test status
Simulation time 175062280 ps
CPU time 0.86 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:08:21 PM PDT 24
Peak memory 207244 kb
Host smart-78e94ade-b234-429f-8f34-d06a3d2546b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12689
16253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1268916253
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1829645719
Short name T2863
Test name
Test status
Simulation time 215025396 ps
CPU time 0.93 seconds
Started Aug 06 08:08:35 PM PDT 24
Finished Aug 06 08:08:36 PM PDT 24
Peak memory 207352 kb
Host smart-5489a895-f506-4fbe-b467-9b311d41c4a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18296
45719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1829645719
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.700802262
Short name T548
Test name
Test status
Simulation time 782212324 ps
CPU time 2.02 seconds
Started Aug 06 08:08:43 PM PDT 24
Finished Aug 06 08:08:45 PM PDT 24
Peak memory 207348 kb
Host smart-fabff393-2148-45d4-ac7f-48a3edf5e895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70080
2262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.700802262
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.2007545241
Short name T3004
Test name
Test status
Simulation time 2881508162 ps
CPU time 28.73 seconds
Started Aug 06 08:08:24 PM PDT 24
Finished Aug 06 08:08:53 PM PDT 24
Peak memory 217660 kb
Host smart-2a0aecfb-78ba-4c4d-ad60-4adb5787b937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20075
45241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.2007545241
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.1124231653
Short name T1540
Test name
Test status
Simulation time 1623409143 ps
CPU time 13.35 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:08:34 PM PDT 24
Peak memory 207548 kb
Host smart-0cab16c1-6795-4eb0-9474-aefce5052f4b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124231653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_hos
t_handshake.1124231653
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.2563466567
Short name T2606
Test name
Test status
Simulation time 33785796 ps
CPU time 0.67 seconds
Started Aug 06 08:08:44 PM PDT 24
Finished Aug 06 08:08:45 PM PDT 24
Peak memory 207404 kb
Host smart-0f8d9960-e7cd-4f56-807b-a4061c68dc85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2563466567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.2563466567
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.4136969254
Short name T2030
Test name
Test status
Simulation time 12158495673 ps
CPU time 15.14 seconds
Started Aug 06 08:08:25 PM PDT 24
Finished Aug 06 08:08:40 PM PDT 24
Peak memory 207632 kb
Host smart-1e6c6866-6d22-4e70-9e2d-3cb2871a5418
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136969254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.4136969254
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3422099543
Short name T1945
Test name
Test status
Simulation time 14795019717 ps
CPU time 16.51 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:37 PM PDT 24
Peak memory 215792 kb
Host smart-5fa4bec1-577d-418c-9d19-4d9c8a515ed0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422099543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3422099543
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3332849129
Short name T3109
Test name
Test status
Simulation time 25078666053 ps
CPU time 28.96 seconds
Started Aug 06 08:08:45 PM PDT 24
Finished Aug 06 08:09:14 PM PDT 24
Peak memory 215880 kb
Host smart-485cea8d-a921-4c5a-9a39-c5ebb8b357c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332849129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.3332849129
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1615036187
Short name T2899
Test name
Test status
Simulation time 150215024 ps
CPU time 0.86 seconds
Started Aug 06 08:08:25 PM PDT 24
Finished Aug 06 08:08:26 PM PDT 24
Peak memory 207388 kb
Host smart-4511aad1-3913-4f16-b769-502218240cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16150
36187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1615036187
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2449627158
Short name T2973
Test name
Test status
Simulation time 189865615 ps
CPU time 0.94 seconds
Started Aug 06 08:08:38 PM PDT 24
Finished Aug 06 08:08:39 PM PDT 24
Peak memory 207288 kb
Host smart-813532bf-bf86-47b6-a8f6-c2cddd800ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24496
27158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2449627158
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3513743477
Short name T2664
Test name
Test status
Simulation time 376694176 ps
CPU time 1.31 seconds
Started Aug 06 08:08:46 PM PDT 24
Finished Aug 06 08:08:48 PM PDT 24
Peak memory 207404 kb
Host smart-d3e146e6-3b99-49bf-aad1-4290cde1f4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35137
43477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3513743477
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.591058585
Short name T2366
Test name
Test status
Simulation time 557030013 ps
CPU time 1.58 seconds
Started Aug 06 08:08:22 PM PDT 24
Finished Aug 06 08:08:23 PM PDT 24
Peak memory 207376 kb
Host smart-3713c16f-87ba-4750-98f8-b81102083ff3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=591058585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.591058585
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.1194920490
Short name T1474
Test name
Test status
Simulation time 21454743946 ps
CPU time 36.87 seconds
Started Aug 06 08:08:44 PM PDT 24
Finished Aug 06 08:09:21 PM PDT 24
Peak memory 207712 kb
Host smart-9d14d3f4-b466-4128-a3e4-11e20c41fb99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11949
20490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.1194920490
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.1673692823
Short name T1758
Test name
Test status
Simulation time 2509863164 ps
CPU time 17.3 seconds
Started Aug 06 08:08:25 PM PDT 24
Finished Aug 06 08:08:43 PM PDT 24
Peak memory 207680 kb
Host smart-4e7e2250-4f3b-456d-aefb-1e9fa8112584
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673692823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.1673692823
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.2554964163
Short name T2654
Test name
Test status
Simulation time 769533313 ps
CPU time 1.6 seconds
Started Aug 06 08:08:46 PM PDT 24
Finished Aug 06 08:08:47 PM PDT 24
Peak memory 207324 kb
Host smart-1c34725a-64b3-44c5-8cac-91a9f6092f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25549
64163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.2554964163
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3059561279
Short name T581
Test name
Test status
Simulation time 191157312 ps
CPU time 0.86 seconds
Started Aug 06 08:08:42 PM PDT 24
Finished Aug 06 08:08:43 PM PDT 24
Peak memory 207340 kb
Host smart-509bb292-622a-4f63-82f6-8b5ae99a9980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30595
61279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3059561279
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.1316463369
Short name T1353
Test name
Test status
Simulation time 48288768 ps
CPU time 0.71 seconds
Started Aug 06 08:08:21 PM PDT 24
Finished Aug 06 08:08:22 PM PDT 24
Peak memory 207360 kb
Host smart-47fae24b-85b2-414d-b1d3-0a9e3d2d6ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13164
63369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1316463369
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.1840328300
Short name T495
Test name
Test status
Simulation time 777469628 ps
CPU time 2.53 seconds
Started Aug 06 08:08:37 PM PDT 24
Finished Aug 06 08:08:39 PM PDT 24
Peak memory 207604 kb
Host smart-9d89a000-d919-43f8-972e-8fe3ebb9a79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18403
28300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.1840328300
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_types.1715549286
Short name T361
Test name
Test status
Simulation time 421313050 ps
CPU time 1.23 seconds
Started Aug 06 08:08:47 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 207328 kb
Host smart-b935da24-8336-4ed5-a0e6-68b062b1f0e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1715549286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.1715549286
Directory /workspace/46.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3968122270
Short name T1259
Test name
Test status
Simulation time 198699346 ps
CPU time 2.17 seconds
Started Aug 06 08:08:22 PM PDT 24
Finished Aug 06 08:08:24 PM PDT 24
Peak memory 207512 kb
Host smart-d9ca2f54-dc6f-4168-a482-98460f7a7db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39681
22270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3968122270
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.368818315
Short name T749
Test name
Test status
Simulation time 235357086 ps
CPU time 0.99 seconds
Started Aug 06 08:08:45 PM PDT 24
Finished Aug 06 08:08:46 PM PDT 24
Peak memory 207380 kb
Host smart-40adf70c-c767-4bbd-9e49-abd74abdbb3a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=368818315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.368818315
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.4161838573
Short name T606
Test name
Test status
Simulation time 145146195 ps
CPU time 0.84 seconds
Started Aug 06 08:08:48 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 207352 kb
Host smart-d132d9e2-dad9-4d31-83b3-f274cca377d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41618
38573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.4161838573
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1850171349
Short name T1630
Test name
Test status
Simulation time 220510240 ps
CPU time 1.04 seconds
Started Aug 06 08:08:32 PM PDT 24
Finished Aug 06 08:08:33 PM PDT 24
Peak memory 207420 kb
Host smart-26b8d490-8284-405f-88c2-66b0d6637a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18501
71349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1850171349
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.1890482700
Short name T1045
Test name
Test status
Simulation time 5177210562 ps
CPU time 39.69 seconds
Started Aug 06 08:08:20 PM PDT 24
Finished Aug 06 08:09:00 PM PDT 24
Peak memory 218100 kb
Host smart-f199fcf9-8954-4a6f-a54f-ff55261a4f63
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1890482700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.1890482700
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.2162613280
Short name T2483
Test name
Test status
Simulation time 3777057373 ps
CPU time 46.28 seconds
Started Aug 06 08:08:41 PM PDT 24
Finished Aug 06 08:09:27 PM PDT 24
Peak memory 207628 kb
Host smart-1993a0bf-a8da-4253-bfb8-9ff9702ccc80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2162613280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.2162613280
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2766346430
Short name T3053
Test name
Test status
Simulation time 199785869 ps
CPU time 0.95 seconds
Started Aug 06 08:08:44 PM PDT 24
Finished Aug 06 08:08:45 PM PDT 24
Peak memory 207448 kb
Host smart-1968080e-5817-4479-8c8e-2f4768ac1b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27663
46430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2766346430
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2650687999
Short name T893
Test name
Test status
Simulation time 11603989020 ps
CPU time 19.19 seconds
Started Aug 06 08:08:39 PM PDT 24
Finished Aug 06 08:08:59 PM PDT 24
Peak memory 207632 kb
Host smart-bfeef865-8dff-4a89-b38f-f267ded0b195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26506
87999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2650687999
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.666750016
Short name T516
Test name
Test status
Simulation time 3859517462 ps
CPU time 5.65 seconds
Started Aug 06 08:08:49 PM PDT 24
Finished Aug 06 08:08:55 PM PDT 24
Peak memory 215900 kb
Host smart-2fb97c29-c2b5-4007-916c-c4e161743b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66675
0016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.666750016
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.114144420
Short name T490
Test name
Test status
Simulation time 3178998669 ps
CPU time 87.79 seconds
Started Aug 06 08:08:37 PM PDT 24
Finished Aug 06 08:10:04 PM PDT 24
Peak memory 223988 kb
Host smart-9d6a92c2-ed84-49b0-bf17-81161e4e7abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11414
4420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.114144420
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.4012614646
Short name T1077
Test name
Test status
Simulation time 3958529883 ps
CPU time 29.57 seconds
Started Aug 06 08:08:43 PM PDT 24
Finished Aug 06 08:09:12 PM PDT 24
Peak memory 215836 kb
Host smart-86e8a775-2cba-4e1d-85ee-2b7f51bdd2be
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4012614646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.4012614646
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.54061545
Short name T1993
Test name
Test status
Simulation time 272131171 ps
CPU time 1.02 seconds
Started Aug 06 08:08:48 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 207384 kb
Host smart-231e154a-3b46-4139-8681-8339ba16c499
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=54061545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.54061545
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2960446241
Short name T2527
Test name
Test status
Simulation time 190150465 ps
CPU time 0.92 seconds
Started Aug 06 08:08:44 PM PDT 24
Finished Aug 06 08:08:45 PM PDT 24
Peak memory 207380 kb
Host smart-7f4976ac-859d-426f-8308-bf9d0ed16d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29604
46241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2960446241
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.3397146237
Short name T1028
Test name
Test status
Simulation time 2580974379 ps
CPU time 24.68 seconds
Started Aug 06 08:08:22 PM PDT 24
Finished Aug 06 08:08:47 PM PDT 24
Peak memory 217816 kb
Host smart-ec895daf-f0d5-4e04-b47f-10b18378d12c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3397146237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.3397146237
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.3927127644
Short name T1131
Test name
Test status
Simulation time 190875368 ps
CPU time 0.89 seconds
Started Aug 06 08:08:26 PM PDT 24
Finished Aug 06 08:08:27 PM PDT 24
Peak memory 207332 kb
Host smart-a592f206-4927-4a47-a4b9-485e6aa4ba16
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3927127644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.3927127644
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.7027807
Short name T1539
Test name
Test status
Simulation time 152837197 ps
CPU time 0.84 seconds
Started Aug 06 08:08:32 PM PDT 24
Finished Aug 06 08:08:33 PM PDT 24
Peak memory 207296 kb
Host smart-58483d6b-115b-4ce1-ae0e-dc1bbd815f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70278
07 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.7027807
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2927233884
Short name T2674
Test name
Test status
Simulation time 226758183 ps
CPU time 1.03 seconds
Started Aug 06 08:08:45 PM PDT 24
Finished Aug 06 08:08:46 PM PDT 24
Peak memory 207356 kb
Host smart-5ee7574f-b08c-4cde-8760-c3fdb4cc3e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29272
33884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2927233884
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3854087453
Short name T2506
Test name
Test status
Simulation time 176679088 ps
CPU time 0.94 seconds
Started Aug 06 08:08:27 PM PDT 24
Finished Aug 06 08:08:28 PM PDT 24
Peak memory 207196 kb
Host smart-833e69d0-4806-4968-b88f-f665866e99b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38540
87453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3854087453
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.4252150161
Short name T628
Test name
Test status
Simulation time 177927607 ps
CPU time 0.85 seconds
Started Aug 06 08:08:24 PM PDT 24
Finished Aug 06 08:08:25 PM PDT 24
Peak memory 207412 kb
Host smart-5529c8aa-3955-443e-ae50-82612fafd3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42521
50161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.4252150161
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1250843164
Short name T2389
Test name
Test status
Simulation time 178226473 ps
CPU time 0.88 seconds
Started Aug 06 08:08:23 PM PDT 24
Finished Aug 06 08:08:24 PM PDT 24
Peak memory 207380 kb
Host smart-96fc4bfd-ec2a-4b92-864f-d93c6294554e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12508
43164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1250843164
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1889576186
Short name T2429
Test name
Test status
Simulation time 171320310 ps
CPU time 0.81 seconds
Started Aug 06 08:08:29 PM PDT 24
Finished Aug 06 08:08:29 PM PDT 24
Peak memory 207336 kb
Host smart-bc6c0b33-70ec-4970-90c2-2027bf01de7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18895
76186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1889576186
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.1074051266
Short name T1837
Test name
Test status
Simulation time 227431789 ps
CPU time 1.01 seconds
Started Aug 06 08:08:42 PM PDT 24
Finished Aug 06 08:08:43 PM PDT 24
Peak memory 207296 kb
Host smart-543d5a62-5710-47d2-bdbc-d11e67abe7ae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1074051266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.1074051266
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3656114350
Short name T2407
Test name
Test status
Simulation time 150477128 ps
CPU time 0.81 seconds
Started Aug 06 08:08:41 PM PDT 24
Finished Aug 06 08:08:42 PM PDT 24
Peak memory 207324 kb
Host smart-fcace951-e0ac-42a3-840a-d83a4499f0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36561
14350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3656114350
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.37947838
Short name T1566
Test name
Test status
Simulation time 50607963 ps
CPU time 0.68 seconds
Started Aug 06 08:08:40 PM PDT 24
Finished Aug 06 08:08:40 PM PDT 24
Peak memory 207256 kb
Host smart-6707a649-5add-472f-bf99-86e1e2743afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37947
838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.37947838
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.198598122
Short name T279
Test name
Test status
Simulation time 15033104442 ps
CPU time 37.14 seconds
Started Aug 06 08:08:34 PM PDT 24
Finished Aug 06 08:09:11 PM PDT 24
Peak memory 224060 kb
Host smart-f9d09852-e4e4-4f53-b1cd-097c43d52266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19859
8122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.198598122
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1205414560
Short name T2451
Test name
Test status
Simulation time 158724994 ps
CPU time 0.93 seconds
Started Aug 06 08:08:24 PM PDT 24
Finished Aug 06 08:08:25 PM PDT 24
Peak memory 207372 kb
Host smart-bbebaf05-0d64-4da9-8aed-9a802e78ec1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12054
14560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1205414560
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3291351617
Short name T1786
Test name
Test status
Simulation time 197884638 ps
CPU time 0.92 seconds
Started Aug 06 08:08:24 PM PDT 24
Finished Aug 06 08:08:25 PM PDT 24
Peak memory 207312 kb
Host smart-efe252d1-cc8e-4c62-85a4-3cba2969156e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32913
51617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3291351617
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3551948424
Short name T1517
Test name
Test status
Simulation time 200043794 ps
CPU time 0.92 seconds
Started Aug 06 08:08:41 PM PDT 24
Finished Aug 06 08:08:42 PM PDT 24
Peak memory 207344 kb
Host smart-3534d96f-7eef-440e-8b9b-b1725de8683e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35519
48424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3551948424
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.2953837464
Short name T2944
Test name
Test status
Simulation time 162398910 ps
CPU time 0.87 seconds
Started Aug 06 08:08:43 PM PDT 24
Finished Aug 06 08:08:44 PM PDT 24
Peak memory 207400 kb
Host smart-b35217e2-6277-4c87-9300-f70ab234c78f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29538
37464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.2953837464
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2713102483
Short name T915
Test name
Test status
Simulation time 198880349 ps
CPU time 0.92 seconds
Started Aug 06 08:08:23 PM PDT 24
Finished Aug 06 08:08:24 PM PDT 24
Peak memory 207316 kb
Host smart-1c955264-0fea-4c97-a954-49257483d5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27131
02483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2713102483
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_rx_full.2687323682
Short name T2224
Test name
Test status
Simulation time 267532850 ps
CPU time 1.18 seconds
Started Aug 06 08:08:51 PM PDT 24
Finished Aug 06 08:08:52 PM PDT 24
Peak memory 207440 kb
Host smart-297d9a5e-63bf-4947-a9f5-df4f256d9ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26873
23682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.2687323682
Directory /workspace/46.usbdev_rx_full/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3948265908
Short name T1189
Test name
Test status
Simulation time 199698234 ps
CPU time 0.91 seconds
Started Aug 06 08:08:28 PM PDT 24
Finished Aug 06 08:08:29 PM PDT 24
Peak memory 207256 kb
Host smart-65a35f17-7452-4b0d-b588-898ee91d9ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39482
65908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3948265908
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2789454384
Short name T1026
Test name
Test status
Simulation time 152947371 ps
CPU time 0.83 seconds
Started Aug 06 08:08:35 PM PDT 24
Finished Aug 06 08:08:35 PM PDT 24
Peak memory 207320 kb
Host smart-6fef7eb5-de21-4d27-9c05-9e34850e539f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27894
54384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2789454384
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2137325333
Short name T2443
Test name
Test status
Simulation time 256500312 ps
CPU time 1.12 seconds
Started Aug 06 08:08:47 PM PDT 24
Finished Aug 06 08:08:48 PM PDT 24
Peak memory 207320 kb
Host smart-14d69ae3-18f2-45c8-9db6-1870ca633830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21373
25333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2137325333
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.737619014
Short name T1747
Test name
Test status
Simulation time 2378901539 ps
CPU time 24.24 seconds
Started Aug 06 08:08:43 PM PDT 24
Finished Aug 06 08:09:07 PM PDT 24
Peak memory 217600 kb
Host smart-0a221607-96ee-4651-a4cd-e0f6a47997a7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=737619014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.737619014
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2787459525
Short name T1323
Test name
Test status
Simulation time 192907156 ps
CPU time 0.96 seconds
Started Aug 06 08:08:24 PM PDT 24
Finished Aug 06 08:08:25 PM PDT 24
Peak memory 207356 kb
Host smart-914acf59-7830-4c63-99f0-712971a08862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27874
59525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2787459525
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1865205980
Short name T2940
Test name
Test status
Simulation time 157590494 ps
CPU time 0.81 seconds
Started Aug 06 08:08:36 PM PDT 24
Finished Aug 06 08:08:37 PM PDT 24
Peak memory 207288 kb
Host smart-ea943909-7652-4cdd-8c39-77f3c2ed2e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18652
05980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1865205980
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.503624667
Short name T2104
Test name
Test status
Simulation time 1281161466 ps
CPU time 2.98 seconds
Started Aug 06 08:08:29 PM PDT 24
Finished Aug 06 08:08:32 PM PDT 24
Peak memory 207436 kb
Host smart-921464dc-807d-402f-b159-2770742672ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50362
4667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.503624667
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.1149708934
Short name T693
Test name
Test status
Simulation time 2270650547 ps
CPU time 22.58 seconds
Started Aug 06 08:08:41 PM PDT 24
Finished Aug 06 08:09:03 PM PDT 24
Peak memory 215880 kb
Host smart-d476b8e7-5c3b-41dd-8695-1421160f14ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11497
08934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.1149708934
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.3850999890
Short name T1738
Test name
Test status
Simulation time 573355332 ps
CPU time 11.57 seconds
Started Aug 06 08:08:41 PM PDT 24
Finished Aug 06 08:08:52 PM PDT 24
Peak memory 207524 kb
Host smart-bc2f9812-00d2-42b8-8a35-9547af77450e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850999890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.3850999890
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.1600918695
Short name T2421
Test name
Test status
Simulation time 42834121 ps
CPU time 0.71 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 207468 kb
Host smart-2e112c63-d78c-4ce2-954c-0dffcbf2282b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1600918695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.1600918695
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2391671311
Short name T10
Test name
Test status
Simulation time 4119849182 ps
CPU time 5.48 seconds
Started Aug 06 08:08:37 PM PDT 24
Finished Aug 06 08:08:43 PM PDT 24
Peak memory 215744 kb
Host smart-29156003-d8bf-4d36-af47-6147a08c2e9a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391671311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.2391671311
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.684045252
Short name T767
Test name
Test status
Simulation time 14328883531 ps
CPU time 17.09 seconds
Started Aug 06 08:08:42 PM PDT 24
Finished Aug 06 08:08:59 PM PDT 24
Peak memory 215820 kb
Host smart-c26ad7c7-9578-44db-a1ea-88783460bb51
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=684045252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.684045252
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.2287670628
Short name T1931
Test name
Test status
Simulation time 29699937561 ps
CPU time 36.71 seconds
Started Aug 06 08:08:41 PM PDT 24
Finished Aug 06 08:09:18 PM PDT 24
Peak memory 207576 kb
Host smart-658debc9-b428-4174-9e17-440040f0cdbe
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287670628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.2287670628
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3538752655
Short name T1919
Test name
Test status
Simulation time 184042854 ps
CPU time 0.93 seconds
Started Aug 06 08:08:34 PM PDT 24
Finished Aug 06 08:08:35 PM PDT 24
Peak memory 207364 kb
Host smart-97230859-fc2f-4b49-999b-be6db3fbe98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35387
52655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3538752655
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.3280480666
Short name T76
Test name
Test status
Simulation time 149770082 ps
CPU time 0.83 seconds
Started Aug 06 08:08:26 PM PDT 24
Finished Aug 06 08:08:27 PM PDT 24
Peak memory 207320 kb
Host smart-503d7570-ec9a-4e50-9c4d-6fecf59bfe7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32804
80666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.3280480666
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.1139545647
Short name T1653
Test name
Test status
Simulation time 157213694 ps
CPU time 0.86 seconds
Started Aug 06 08:08:34 PM PDT 24
Finished Aug 06 08:08:35 PM PDT 24
Peak memory 207292 kb
Host smart-243700c7-5e9c-4ee9-a566-cde554837eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11395
45647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.1139545647
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1852130993
Short name T1782
Test name
Test status
Simulation time 684470004 ps
CPU time 1.76 seconds
Started Aug 06 08:08:25 PM PDT 24
Finished Aug 06 08:08:27 PM PDT 24
Peak memory 207360 kb
Host smart-6f20510d-bdec-4bcc-8f27-79663e0236b4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1852130993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1852130993
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.1950673135
Short name T1821
Test name
Test status
Simulation time 18043328645 ps
CPU time 31.26 seconds
Started Aug 06 08:08:42 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207552 kb
Host smart-976c4303-73ca-4fa5-94d4-f5d488b05b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19506
73135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.1950673135
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.3496362776
Short name T2538
Test name
Test status
Simulation time 4313607149 ps
CPU time 27.88 seconds
Started Aug 06 08:08:40 PM PDT 24
Finished Aug 06 08:09:08 PM PDT 24
Peak memory 207624 kb
Host smart-bb7f071d-8ea0-4e51-8165-807377ffb8ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496362776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.3496362776
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.551074143
Short name T1861
Test name
Test status
Simulation time 789844085 ps
CPU time 1.76 seconds
Started Aug 06 08:08:24 PM PDT 24
Finished Aug 06 08:08:26 PM PDT 24
Peak memory 207340 kb
Host smart-d287f9c9-31ad-47a7-a821-9c8af531f536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55107
4143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.551074143
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1876633979
Short name T1066
Test name
Test status
Simulation time 140097476 ps
CPU time 0.82 seconds
Started Aug 06 08:08:33 PM PDT 24
Finished Aug 06 08:08:34 PM PDT 24
Peak memory 207292 kb
Host smart-1dc78e44-0c7a-42b4-b1a4-769925cb6710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18766
33979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1876633979
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.224901146
Short name T629
Test name
Test status
Simulation time 40051338 ps
CPU time 0.68 seconds
Started Aug 06 08:08:32 PM PDT 24
Finished Aug 06 08:08:33 PM PDT 24
Peak memory 207204 kb
Host smart-ea6bd1e6-5e24-4d70-b421-7d79696d1ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22490
1146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.224901146
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2316259443
Short name T494
Test name
Test status
Simulation time 750502265 ps
CPU time 2.11 seconds
Started Aug 06 08:08:47 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 207588 kb
Host smart-8a5e20b2-1c65-4688-a2d8-07f35ee1d73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23162
59443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2316259443
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_types.1405460381
Short name T382
Test name
Test status
Simulation time 574946957 ps
CPU time 1.57 seconds
Started Aug 06 08:08:40 PM PDT 24
Finished Aug 06 08:08:42 PM PDT 24
Peak memory 207300 kb
Host smart-de3c9cea-75fa-46dd-adca-3aee9439c079
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1405460381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.1405460381
Directory /workspace/47.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.741718187
Short name T2849
Test name
Test status
Simulation time 200350747 ps
CPU time 1.68 seconds
Started Aug 06 08:08:39 PM PDT 24
Finished Aug 06 08:08:41 PM PDT 24
Peak memory 207520 kb
Host smart-f8df220e-b315-4fb8-9add-5f0dc213373c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74171
8187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.741718187
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3973138888
Short name T1483
Test name
Test status
Simulation time 284425648 ps
CPU time 1.32 seconds
Started Aug 06 08:08:52 PM PDT 24
Finished Aug 06 08:08:53 PM PDT 24
Peak memory 215804 kb
Host smart-aa83599e-245d-4635-9951-03dff7bdec3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3973138888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3973138888
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2764454353
Short name T2680
Test name
Test status
Simulation time 205230583 ps
CPU time 0.87 seconds
Started Aug 06 08:08:45 PM PDT 24
Finished Aug 06 08:08:46 PM PDT 24
Peak memory 207272 kb
Host smart-03691dca-1350-4038-bb29-f559a62e9e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27644
54353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2764454353
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2640412965
Short name T1009
Test name
Test status
Simulation time 242031053 ps
CPU time 1.04 seconds
Started Aug 06 08:08:41 PM PDT 24
Finished Aug 06 08:08:42 PM PDT 24
Peak memory 207412 kb
Host smart-c0e30c45-a62d-443d-87d6-595f99f2bfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26404
12965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2640412965
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.2723118490
Short name T493
Test name
Test status
Simulation time 4293249958 ps
CPU time 121.37 seconds
Started Aug 06 08:08:33 PM PDT 24
Finished Aug 06 08:10:34 PM PDT 24
Peak memory 224016 kb
Host smart-bdd2d8dd-ee3b-40b6-b98d-0bbf004f4e1f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2723118490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.2723118490
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.275568983
Short name T1073
Test name
Test status
Simulation time 13163199698 ps
CPU time 163.39 seconds
Started Aug 06 08:08:47 PM PDT 24
Finished Aug 06 08:11:30 PM PDT 24
Peak memory 207652 kb
Host smart-db26fd78-ef50-4479-a75f-2d3e215b899a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=275568983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.275568983
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.322129247
Short name T2562
Test name
Test status
Simulation time 211670911 ps
CPU time 0.96 seconds
Started Aug 06 08:08:36 PM PDT 24
Finished Aug 06 08:08:37 PM PDT 24
Peak memory 207372 kb
Host smart-919d83f0-8063-408f-9ed5-4e52e7cb859a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32212
9247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.322129247
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.2777068164
Short name T866
Test name
Test status
Simulation time 29306687693 ps
CPU time 41.3 seconds
Started Aug 06 08:08:46 PM PDT 24
Finished Aug 06 08:09:27 PM PDT 24
Peak memory 207612 kb
Host smart-e515494b-430a-4850-a766-ccd4953195bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27770
68164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.2777068164
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1426663187
Short name T2266
Test name
Test status
Simulation time 9310797750 ps
CPU time 11.59 seconds
Started Aug 06 08:08:53 PM PDT 24
Finished Aug 06 08:09:04 PM PDT 24
Peak memory 207596 kb
Host smart-2f87f0ca-e965-44e2-8f85-24b142755ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14266
63187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1426663187
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.2835390163
Short name T988
Test name
Test status
Simulation time 3120720553 ps
CPU time 29.45 seconds
Started Aug 06 08:08:48 PM PDT 24
Finished Aug 06 08:09:17 PM PDT 24
Peak memory 215844 kb
Host smart-bb7e0a0e-35fe-4dad-a3d1-ae4bb396cc23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28353
90163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.2835390163
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.882027339
Short name T1378
Test name
Test status
Simulation time 2784172395 ps
CPU time 27.01 seconds
Started Aug 06 08:08:51 PM PDT 24
Finished Aug 06 08:09:18 PM PDT 24
Peak memory 215972 kb
Host smart-1e4805d1-e484-43ad-a4ff-2ba5c86d018e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=882027339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.882027339
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3861065337
Short name T93
Test name
Test status
Simulation time 252425291 ps
CPU time 0.97 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 207336 kb
Host smart-0de531bb-d7b3-467d-9978-0b4f653549fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3861065337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3861065337
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3576493169
Short name T2922
Test name
Test status
Simulation time 195269093 ps
CPU time 0.97 seconds
Started Aug 06 08:08:46 PM PDT 24
Finished Aug 06 08:08:47 PM PDT 24
Peak memory 207360 kb
Host smart-60493acb-1d3c-487f-86eb-73e06f946791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35764
93169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3576493169
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3147658168
Short name T1743
Test name
Test status
Simulation time 2665706063 ps
CPU time 76 seconds
Started Aug 06 08:08:57 PM PDT 24
Finished Aug 06 08:10:13 PM PDT 24
Peak memory 223952 kb
Host smart-3ed706d5-7c88-45dd-8030-7b8aaf0178b5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3147658168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3147658168
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.90412004
Short name T1257
Test name
Test status
Simulation time 209753778 ps
CPU time 0.9 seconds
Started Aug 06 08:08:52 PM PDT 24
Finished Aug 06 08:08:53 PM PDT 24
Peak memory 207444 kb
Host smart-f9031dc4-90c2-4d8c-8278-bd3cf6597376
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=90412004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.90412004
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.4109094515
Short name T1928
Test name
Test status
Simulation time 147732530 ps
CPU time 0.83 seconds
Started Aug 06 08:08:42 PM PDT 24
Finished Aug 06 08:08:43 PM PDT 24
Peak memory 207308 kb
Host smart-0684223c-b6bf-4f14-82c5-2f718a4fca80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41090
94515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.4109094515
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3274495502
Short name T1954
Test name
Test status
Simulation time 163731777 ps
CPU time 0.83 seconds
Started Aug 06 08:08:51 PM PDT 24
Finished Aug 06 08:08:52 PM PDT 24
Peak memory 207248 kb
Host smart-1538acae-fd7d-4acc-8c0b-c066c35e7df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32744
95502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3274495502
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.154139112
Short name T707
Test name
Test status
Simulation time 168860278 ps
CPU time 0.83 seconds
Started Aug 06 08:08:48 PM PDT 24
Finished Aug 06 08:08:48 PM PDT 24
Peak memory 207360 kb
Host smart-8085d013-a2a7-4151-ae4f-0e9fb1579eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15413
9112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.154139112
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1593679452
Short name T1269
Test name
Test status
Simulation time 171253472 ps
CPU time 0.91 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 207312 kb
Host smart-bb68bb0c-398c-4ed6-adc2-e8fd6b84a850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15936
79452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1593679452
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1477182778
Short name T2221
Test name
Test status
Simulation time 200828165 ps
CPU time 0.91 seconds
Started Aug 06 08:09:04 PM PDT 24
Finished Aug 06 08:09:05 PM PDT 24
Peak memory 207292 kb
Host smart-85b7bf50-524c-4981-bcc3-bd6ab141aaf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14771
82778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1477182778
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.256145297
Short name T1396
Test name
Test status
Simulation time 180323287 ps
CPU time 0.85 seconds
Started Aug 06 08:08:46 PM PDT 24
Finished Aug 06 08:08:47 PM PDT 24
Peak memory 207428 kb
Host smart-48fa1893-9317-4e01-b87a-d41da7c42b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25614
5297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.256145297
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.3016281439
Short name T1184
Test name
Test status
Simulation time 190816189 ps
CPU time 0.91 seconds
Started Aug 06 08:08:50 PM PDT 24
Finished Aug 06 08:08:51 PM PDT 24
Peak memory 207328 kb
Host smart-2eae476c-0ce0-44b9-b30d-8557d51cca44
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3016281439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.3016281439
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2912325588
Short name T820
Test name
Test status
Simulation time 139872885 ps
CPU time 0.79 seconds
Started Aug 06 08:08:31 PM PDT 24
Finished Aug 06 08:08:32 PM PDT 24
Peak memory 207312 kb
Host smart-2e109c4d-7014-4885-8a8f-a241c34aec21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29123
25588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2912325588
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3835524085
Short name T967
Test name
Test status
Simulation time 41411485 ps
CPU time 0.67 seconds
Started Aug 06 08:08:50 PM PDT 24
Finished Aug 06 08:08:50 PM PDT 24
Peak memory 207284 kb
Host smart-74a407a8-ac0a-441b-bd79-4e2966f73578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38355
24085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3835524085
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1274015684
Short name T829
Test name
Test status
Simulation time 7700842140 ps
CPU time 21.02 seconds
Started Aug 06 08:08:44 PM PDT 24
Finished Aug 06 08:09:05 PM PDT 24
Peak memory 215708 kb
Host smart-3aac14ae-32f9-4814-b64e-951df05d3e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12740
15684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1274015684
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3323443
Short name T2028
Test name
Test status
Simulation time 168231774 ps
CPU time 0.89 seconds
Started Aug 06 08:08:39 PM PDT 24
Finished Aug 06 08:08:40 PM PDT 24
Peak memory 207356 kb
Host smart-3977db28-7138-4da2-b3d6-4811313066ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33234
43 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3323443
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2861908253
Short name T2044
Test name
Test status
Simulation time 238090976 ps
CPU time 0.94 seconds
Started Aug 06 08:08:45 PM PDT 24
Finished Aug 06 08:08:46 PM PDT 24
Peak memory 207400 kb
Host smart-7e073da2-ba0a-42ea-9e77-87b97612471a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28619
08253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2861908253
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.3348426209
Short name T2476
Test name
Test status
Simulation time 233565529 ps
CPU time 1.05 seconds
Started Aug 06 08:08:49 PM PDT 24
Finished Aug 06 08:08:51 PM PDT 24
Peak memory 207244 kb
Host smart-702deb26-c7bb-4bab-91be-ccfff9cf8413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33484
26209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.3348426209
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3924826607
Short name T1648
Test name
Test status
Simulation time 200855942 ps
CPU time 0.94 seconds
Started Aug 06 08:08:42 PM PDT 24
Finished Aug 06 08:08:43 PM PDT 24
Peak memory 207356 kb
Host smart-71eb609d-ec2b-46ab-afcc-c726a4746bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39248
26607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3924826607
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.2763402227
Short name T3082
Test name
Test status
Simulation time 151011270 ps
CPU time 0.81 seconds
Started Aug 06 08:08:48 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 207332 kb
Host smart-6cd7cb40-d6df-430c-9ae3-b0b0beb390b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27634
02227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.2763402227
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_rx_full.2000573842
Short name T2715
Test name
Test status
Simulation time 288657699 ps
CPU time 1.15 seconds
Started Aug 06 08:08:42 PM PDT 24
Finished Aug 06 08:08:43 PM PDT 24
Peak memory 207308 kb
Host smart-af178044-c509-4101-bb80-0a210a48e41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20005
73842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.2000573842
Directory /workspace/47.usbdev_rx_full/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.752392623
Short name T1888
Test name
Test status
Simulation time 152187564 ps
CPU time 0.84 seconds
Started Aug 06 08:08:52 PM PDT 24
Finished Aug 06 08:08:53 PM PDT 24
Peak memory 207412 kb
Host smart-bbb44b13-82e6-42f7-841b-1ce78189568f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75239
2623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.752392623
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1141340731
Short name T1011
Test name
Test status
Simulation time 183636716 ps
CPU time 0.87 seconds
Started Aug 06 08:08:53 PM PDT 24
Finished Aug 06 08:08:54 PM PDT 24
Peak memory 207404 kb
Host smart-36f90740-10f4-46a5-a0e2-d5eb3df2dbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11413
40731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1141340731
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3757953506
Short name T861
Test name
Test status
Simulation time 206147905 ps
CPU time 1.06 seconds
Started Aug 06 08:09:03 PM PDT 24
Finished Aug 06 08:09:04 PM PDT 24
Peak memory 207348 kb
Host smart-63db3d3d-d85c-4d71-8412-e9e4343b4d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37579
53506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3757953506
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.1705081526
Short name T2172
Test name
Test status
Simulation time 2894823789 ps
CPU time 30.04 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:09:25 PM PDT 24
Peak memory 224060 kb
Host smart-56d35549-5694-4020-a29c-3086442432d4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1705081526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.1705081526
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3738203327
Short name T1142
Test name
Test status
Simulation time 174205033 ps
CPU time 0.86 seconds
Started Aug 06 08:08:49 PM PDT 24
Finished Aug 06 08:08:50 PM PDT 24
Peak memory 207364 kb
Host smart-ec067bdd-fa0c-49d5-826e-3b5f9d677ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37382
03327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3738203327
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3160822434
Short name T696
Test name
Test status
Simulation time 161061242 ps
CPU time 0.83 seconds
Started Aug 06 08:08:45 PM PDT 24
Finished Aug 06 08:08:45 PM PDT 24
Peak memory 207320 kb
Host smart-1cfa179f-fa1b-4bb7-8ed6-92378f61d68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31608
22434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3160822434
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.4072441715
Short name T659
Test name
Test status
Simulation time 327615297 ps
CPU time 1.28 seconds
Started Aug 06 08:08:42 PM PDT 24
Finished Aug 06 08:08:43 PM PDT 24
Peak memory 207348 kb
Host smart-4bd7f91a-dd35-44b8-9855-e0f61f4f37c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40724
41715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.4072441715
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.241350117
Short name T1642
Test name
Test status
Simulation time 1875815853 ps
CPU time 53.05 seconds
Started Aug 06 08:08:47 PM PDT 24
Finished Aug 06 08:09:40 PM PDT 24
Peak memory 217080 kb
Host smart-aaf1e17a-9b58-4c5d-8970-39ff1c44cc53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24135
0117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.241350117
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.2333746196
Short name T547
Test name
Test status
Simulation time 2053739975 ps
CPU time 17.89 seconds
Started Aug 06 08:08:42 PM PDT 24
Finished Aug 06 08:09:00 PM PDT 24
Peak memory 207632 kb
Host smart-c37113ce-aa04-461d-aef9-ec865d7bb4dc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333746196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.2333746196
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.966126762
Short name T2965
Test name
Test status
Simulation time 61163928 ps
CPU time 0.68 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:08:55 PM PDT 24
Peak memory 207416 kb
Host smart-02134657-f77d-40e2-aa4a-31f2c76b072f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=966126762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.966126762
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.4276790694
Short name T1817
Test name
Test status
Simulation time 11614056377 ps
CPU time 13.6 seconds
Started Aug 06 08:08:49 PM PDT 24
Finished Aug 06 08:09:02 PM PDT 24
Peak memory 207616 kb
Host smart-b7e34165-e928-45dc-86eb-1ff96844c131
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276790694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.4276790694
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1519719693
Short name T1486
Test name
Test status
Simulation time 20462263706 ps
CPU time 23.06 seconds
Started Aug 06 08:08:45 PM PDT 24
Finished Aug 06 08:09:09 PM PDT 24
Peak memory 207620 kb
Host smart-e4e0af9e-3661-42a4-829d-8b564e1fbeb2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519719693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1519719693
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.4015524308
Short name T3116
Test name
Test status
Simulation time 26113820486 ps
CPU time 30.35 seconds
Started Aug 06 08:08:41 PM PDT 24
Finished Aug 06 08:09:11 PM PDT 24
Peak memory 216876 kb
Host smart-c99b2884-f7f5-4ab5-be06-6b384d27c9a1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015524308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.4015524308
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3291173677
Short name T2447
Test name
Test status
Simulation time 156970661 ps
CPU time 0.9 seconds
Started Aug 06 08:08:52 PM PDT 24
Finished Aug 06 08:08:53 PM PDT 24
Peak memory 207596 kb
Host smart-4bcddc1e-fc2e-44e6-9ad4-968456ff2d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32911
73677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3291173677
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.4035125397
Short name T926
Test name
Test status
Simulation time 153350693 ps
CPU time 0.82 seconds
Started Aug 06 08:08:44 PM PDT 24
Finished Aug 06 08:08:45 PM PDT 24
Peak memory 207348 kb
Host smart-f1625bb0-b4cf-41af-8a37-41eab76bbc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40351
25397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.4035125397
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2097876033
Short name T887
Test name
Test status
Simulation time 332240235 ps
CPU time 1.25 seconds
Started Aug 06 08:08:59 PM PDT 24
Finished Aug 06 08:09:00 PM PDT 24
Peak memory 207360 kb
Host smart-033c97e6-02ee-490d-82bd-612fa2d8be95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20978
76033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2097876033
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3611178492
Short name T1984
Test name
Test status
Simulation time 675002474 ps
CPU time 1.79 seconds
Started Aug 06 08:08:47 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 207304 kb
Host smart-bb50df84-8fe9-44a6-b66d-09f2eaaff9fa
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3611178492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3611178492
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.2446805120
Short name T2374
Test name
Test status
Simulation time 36309676290 ps
CPU time 53.73 seconds
Started Aug 06 08:08:42 PM PDT 24
Finished Aug 06 08:09:36 PM PDT 24
Peak memory 207536 kb
Host smart-7fdce3d4-a8b5-4c27-91ce-f252c31c45d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24468
05120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.2446805120
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.2385672138
Short name T1106
Test name
Test status
Simulation time 3606147199 ps
CPU time 23.36 seconds
Started Aug 06 08:08:34 PM PDT 24
Finished Aug 06 08:08:58 PM PDT 24
Peak memory 207684 kb
Host smart-04831cde-2a87-416e-9ea7-995de47f05a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385672138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.2385672138
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.3439058100
Short name T1313
Test name
Test status
Simulation time 1239563686 ps
CPU time 2.62 seconds
Started Aug 06 08:08:48 PM PDT 24
Finished Aug 06 08:08:51 PM PDT 24
Peak memory 207588 kb
Host smart-6e6e2384-b3c1-4c0f-b1f8-bf7b7e123ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34390
58100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.3439058100
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.62565097
Short name T661
Test name
Test status
Simulation time 173421970 ps
CPU time 0.84 seconds
Started Aug 06 08:08:47 PM PDT 24
Finished Aug 06 08:08:47 PM PDT 24
Peak memory 207324 kb
Host smart-87c2a72e-f846-4adf-bf92-97cac6a50e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62565
097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.62565097
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1486931967
Short name T943
Test name
Test status
Simulation time 52366137 ps
CPU time 0.73 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 207368 kb
Host smart-a192275f-e00d-45cb-a38b-eb4d4f531882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14869
31967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1486931967
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1728257081
Short name T2999
Test name
Test status
Simulation time 869903625 ps
CPU time 2.19 seconds
Started Aug 06 08:08:48 PM PDT 24
Finished Aug 06 08:08:50 PM PDT 24
Peak memory 207600 kb
Host smart-ca8aa410-817f-4b19-a84d-8eefb93a5a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17282
57081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1728257081
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_types.4026570207
Short name T2644
Test name
Test status
Simulation time 764658247 ps
CPU time 1.95 seconds
Started Aug 06 08:08:50 PM PDT 24
Finished Aug 06 08:08:52 PM PDT 24
Peak memory 207320 kb
Host smart-7e3151d3-c18b-45fe-804b-7ef4a39231fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4026570207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.4026570207
Directory /workspace/48.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1800340466
Short name T2926
Test name
Test status
Simulation time 272322013 ps
CPU time 2.19 seconds
Started Aug 06 08:08:44 PM PDT 24
Finished Aug 06 08:08:46 PM PDT 24
Peak memory 207564 kb
Host smart-022df0c5-3b02-4405-b0db-8c3fde65f9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18003
40466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1800340466
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2774337644
Short name T1004
Test name
Test status
Simulation time 218919095 ps
CPU time 0.94 seconds
Started Aug 06 08:08:52 PM PDT 24
Finished Aug 06 08:08:53 PM PDT 24
Peak memory 207236 kb
Host smart-b113f5a8-946f-4ccd-ba53-a97351a25836
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2774337644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2774337644
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3494370925
Short name T3015
Test name
Test status
Simulation time 205074099 ps
CPU time 0.89 seconds
Started Aug 06 08:08:46 PM PDT 24
Finished Aug 06 08:08:47 PM PDT 24
Peak memory 207264 kb
Host smart-71c5fe43-f093-4b54-a1ad-0966cca0da0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34943
70925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3494370925
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3277428761
Short name T2673
Test name
Test status
Simulation time 259483579 ps
CPU time 1.03 seconds
Started Aug 06 08:08:51 PM PDT 24
Finished Aug 06 08:08:52 PM PDT 24
Peak memory 207368 kb
Host smart-f26759fc-b944-47a5-af7c-1a0bec7a1dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32774
28761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3277428761
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.3739185278
Short name T209
Test name
Test status
Simulation time 4598176144 ps
CPU time 135.18 seconds
Started Aug 06 08:08:39 PM PDT 24
Finished Aug 06 08:10:54 PM PDT 24
Peak memory 218056 kb
Host smart-1d492ba3-a973-445d-a8ed-e06632945675
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3739185278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.3739185278
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.4213774270
Short name T2962
Test name
Test status
Simulation time 13669890402 ps
CPU time 84.95 seconds
Started Aug 06 08:08:50 PM PDT 24
Finished Aug 06 08:10:15 PM PDT 24
Peak memory 207552 kb
Host smart-f4f6ab87-45da-4042-81c3-d8003ddd8b8c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4213774270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.4213774270
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.646441484
Short name T2178
Test name
Test status
Simulation time 219683500 ps
CPU time 0.92 seconds
Started Aug 06 08:08:48 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 207368 kb
Host smart-477fb906-3a40-43f8-a923-69ca0058e17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64644
1484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.646441484
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3661373875
Short name T2622
Test name
Test status
Simulation time 29165522702 ps
CPU time 45.79 seconds
Started Aug 06 08:08:48 PM PDT 24
Finished Aug 06 08:09:33 PM PDT 24
Peak memory 215904 kb
Host smart-1583378a-5c5c-44e5-b763-f7c4145c1c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36613
73875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3661373875
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.804207139
Short name T1283
Test name
Test status
Simulation time 5815787546 ps
CPU time 7.53 seconds
Started Aug 06 08:08:41 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 215860 kb
Host smart-5fb52f56-10ab-49ca-be51-32410fdda624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80420
7139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.804207139
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.3199896672
Short name T1267
Test name
Test status
Simulation time 4590168009 ps
CPU time 128.88 seconds
Started Aug 06 08:08:43 PM PDT 24
Finished Aug 06 08:10:52 PM PDT 24
Peak memory 215832 kb
Host smart-7d9bf883-9631-4506-ba6d-d271ad981300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31998
96672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.3199896672
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2008883932
Short name T2438
Test name
Test status
Simulation time 2478462372 ps
CPU time 72.32 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:10:08 PM PDT 24
Peak memory 224028 kb
Host smart-24067d21-9b6f-4321-aa8c-a9c75522de9c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2008883932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2008883932
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1586873598
Short name T2116
Test name
Test status
Simulation time 277351923 ps
CPU time 1.02 seconds
Started Aug 06 08:08:50 PM PDT 24
Finished Aug 06 08:08:51 PM PDT 24
Peak memory 207372 kb
Host smart-fed9c1c4-c694-4beb-9d70-2aef1623c729
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1586873598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1586873598
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1678888683
Short name T2025
Test name
Test status
Simulation time 214129747 ps
CPU time 0.98 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 207360 kb
Host smart-3375950c-a270-4240-ac18-f3f6a27149ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16788
88683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1678888683
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.596829600
Short name T2943
Test name
Test status
Simulation time 2908628612 ps
CPU time 84.7 seconds
Started Aug 06 08:08:57 PM PDT 24
Finished Aug 06 08:10:22 PM PDT 24
Peak memory 215840 kb
Host smart-a436a923-f21f-4b1c-ac41-14c0b09eab0d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=596829600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.596829600
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2870250654
Short name T1237
Test name
Test status
Simulation time 157477562 ps
CPU time 0.89 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 207428 kb
Host smart-dbd81f98-d5f3-471f-94a1-0edf47c6d94e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2870250654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2870250654
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2949832053
Short name T2413
Test name
Test status
Simulation time 146931337 ps
CPU time 0.82 seconds
Started Aug 06 08:08:57 PM PDT 24
Finished Aug 06 08:08:58 PM PDT 24
Peak memory 207384 kb
Host smart-852f9254-786d-4cfd-bcc8-fe3e5ede6fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29498
32053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2949832053
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1670111420
Short name T144
Test name
Test status
Simulation time 204599872 ps
CPU time 0.94 seconds
Started Aug 06 08:08:53 PM PDT 24
Finished Aug 06 08:08:54 PM PDT 24
Peak memory 207312 kb
Host smart-906c6fd4-36e1-4154-afb8-933d8d0f6398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16701
11420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1670111420
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3283979772
Short name T2703
Test name
Test status
Simulation time 187413319 ps
CPU time 0.95 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 207320 kb
Host smart-aedd8f17-9504-42ca-85b1-e6e019467897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32839
79772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3283979772
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3807481260
Short name T1801
Test name
Test status
Simulation time 145432970 ps
CPU time 0.94 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207364 kb
Host smart-57215ac1-850d-4c8d-beed-957e9fb6f0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38074
81260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3807481260
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1265363396
Short name T2318
Test name
Test status
Simulation time 162898037 ps
CPU time 0.84 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:08:55 PM PDT 24
Peak memory 207344 kb
Host smart-904dc118-aa71-4d8b-a366-a38bd26d4cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12653
63396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1265363396
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.281805850
Short name T2231
Test name
Test status
Simulation time 162311672 ps
CPU time 0.89 seconds
Started Aug 06 08:09:00 PM PDT 24
Finished Aug 06 08:09:01 PM PDT 24
Peak memory 207416 kb
Host smart-d7f71da0-37b5-4d36-925e-8015c54258cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28180
5850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.281805850
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3714463335
Short name T1666
Test name
Test status
Simulation time 227177587 ps
CPU time 0.98 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 207340 kb
Host smart-4a9e011c-a950-4f2d-932b-2e36e024f02f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3714463335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3714463335
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3379602064
Short name T1724
Test name
Test status
Simulation time 152042179 ps
CPU time 0.81 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 207304 kb
Host smart-3401a781-15f8-422a-ae7d-d6b702b8c1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33796
02064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3379602064
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.288917434
Short name T2832
Test name
Test status
Simulation time 42740105 ps
CPU time 0.68 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:08:55 PM PDT 24
Peak memory 207316 kb
Host smart-d0d15636-7ebf-482e-87e8-9c9d43d6d746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28891
7434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.288917434
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2491066784
Short name T110
Test name
Test status
Simulation time 21094370806 ps
CPU time 55.67 seconds
Started Aug 06 08:08:58 PM PDT 24
Finished Aug 06 08:09:54 PM PDT 24
Peak memory 215868 kb
Host smart-753adca9-85f1-429c-82c8-b73189fdc3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24910
66784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2491066784
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.802613
Short name T551
Test name
Test status
Simulation time 182645471 ps
CPU time 0.94 seconds
Started Aug 06 08:08:47 PM PDT 24
Finished Aug 06 08:08:48 PM PDT 24
Peak memory 207320 kb
Host smart-3fa881bb-41a5-40d6-9b96-f3cda1a8b81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80261
3 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.802613
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2111877581
Short name T506
Test name
Test status
Simulation time 251901845 ps
CPU time 1 seconds
Started Aug 06 08:09:03 PM PDT 24
Finished Aug 06 08:09:04 PM PDT 24
Peak memory 207348 kb
Host smart-0f1cfefa-1fa9-4f0e-89fb-ed5a64527c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21118
77581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2111877581
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1078006323
Short name T2089
Test name
Test status
Simulation time 214116313 ps
CPU time 0.97 seconds
Started Aug 06 08:08:50 PM PDT 24
Finished Aug 06 08:08:51 PM PDT 24
Peak memory 207360 kb
Host smart-39398ec4-ac1c-489a-a903-a78dd8ede727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10780
06323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1078006323
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1233286214
Short name T776
Test name
Test status
Simulation time 169891700 ps
CPU time 0.87 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 207340 kb
Host smart-029a0145-2d99-4ba5-9999-bca344137921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12332
86214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1233286214
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1988041826
Short name T2490
Test name
Test status
Simulation time 217237522 ps
CPU time 0.92 seconds
Started Aug 06 08:08:58 PM PDT 24
Finished Aug 06 08:08:59 PM PDT 24
Peak memory 207416 kb
Host smart-1bfba61d-6658-464d-b19b-094aa58731cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19880
41826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1988041826
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_rx_full.910027806
Short name T28
Test name
Test status
Simulation time 331814198 ps
CPU time 1.14 seconds
Started Aug 06 08:09:07 PM PDT 24
Finished Aug 06 08:09:08 PM PDT 24
Peak memory 207348 kb
Host smart-0a053210-e943-41ff-9ede-5c0cf48e6869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91002
7806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.910027806
Directory /workspace/48.usbdev_rx_full/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3088626811
Short name T560
Test name
Test status
Simulation time 150883881 ps
CPU time 0.85 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 207324 kb
Host smart-a9d2a6dd-d046-4e0d-9d67-758b8f565984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30886
26811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3088626811
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1861818410
Short name T1507
Test name
Test status
Simulation time 144087827 ps
CPU time 0.79 seconds
Started Aug 06 08:08:48 PM PDT 24
Finished Aug 06 08:08:49 PM PDT 24
Peak memory 207352 kb
Host smart-f3053ffe-4f95-4340-baaf-212a768f7ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18618
18410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1861818410
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3819709744
Short name T2130
Test name
Test status
Simulation time 207589986 ps
CPU time 0.99 seconds
Started Aug 06 08:08:53 PM PDT 24
Finished Aug 06 08:08:54 PM PDT 24
Peak memory 207308 kb
Host smart-493504d1-edb3-4e80-a64d-e19bdf51d113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38197
09744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3819709744
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1500345062
Short name T3000
Test name
Test status
Simulation time 3087853745 ps
CPU time 29.84 seconds
Started Aug 06 08:09:02 PM PDT 24
Finished Aug 06 08:09:32 PM PDT 24
Peak memory 224076 kb
Host smart-29bc1a65-2f05-4fb8-8647-2988fb3482c5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1500345062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1500345062
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2764335982
Short name T2342
Test name
Test status
Simulation time 177509855 ps
CPU time 0.9 seconds
Started Aug 06 08:09:07 PM PDT 24
Finished Aug 06 08:09:08 PM PDT 24
Peak memory 207292 kb
Host smart-f2b4fb76-7728-47e3-8da8-b50a5208f0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27643
35982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2764335982
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1324732185
Short name T657
Test name
Test status
Simulation time 176911027 ps
CPU time 0.85 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:08:55 PM PDT 24
Peak memory 207352 kb
Host smart-b586af91-00be-4bd3-95a0-3da39f565788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13247
32185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1324732185
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.3364186437
Short name T2659
Test name
Test status
Simulation time 1368457258 ps
CPU time 3.13 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:08:58 PM PDT 24
Peak memory 207472 kb
Host smart-53d15b48-ce30-42d4-9726-0f050d6631d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33641
86437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.3364186437
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.4265228494
Short name T823
Test name
Test status
Simulation time 2202743215 ps
CPU time 16.98 seconds
Started Aug 06 08:09:09 PM PDT 24
Finished Aug 06 08:09:26 PM PDT 24
Peak memory 215912 kb
Host smart-aa146551-35b8-464a-9f9c-eb330459e3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42652
28494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.4265228494
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.1656965072
Short name T974
Test name
Test status
Simulation time 887368817 ps
CPU time 18.68 seconds
Started Aug 06 08:08:51 PM PDT 24
Finished Aug 06 08:09:10 PM PDT 24
Peak memory 207520 kb
Host smart-fff037d0-9928-45a9-bef0-a82a4fb1c11b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656965072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.1656965072
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.229137066
Short name T1402
Test name
Test status
Simulation time 90818358 ps
CPU time 0.72 seconds
Started Aug 06 08:08:59 PM PDT 24
Finished Aug 06 08:09:00 PM PDT 24
Peak memory 207508 kb
Host smart-a2772914-cf06-49b8-823a-addd6f5855b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=229137066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.229137066
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2619393062
Short name T1660
Test name
Test status
Simulation time 8827765628 ps
CPU time 11.96 seconds
Started Aug 06 08:09:02 PM PDT 24
Finished Aug 06 08:09:14 PM PDT 24
Peak memory 207584 kb
Host smart-ca4c3cde-9db1-497b-90bb-8346eb79caca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619393062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.2619393062
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.789612975
Short name T1872
Test name
Test status
Simulation time 16070459255 ps
CPU time 19.62 seconds
Started Aug 06 08:09:02 PM PDT 24
Finished Aug 06 08:09:22 PM PDT 24
Peak memory 215788 kb
Host smart-5d5c7135-c161-479c-92e5-05109f8b2990
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=789612975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.789612975
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1387470781
Short name T227
Test name
Test status
Simulation time 25832931443 ps
CPU time 32.41 seconds
Started Aug 06 08:09:01 PM PDT 24
Finished Aug 06 08:09:33 PM PDT 24
Peak memory 216044 kb
Host smart-4fda0b92-8119-4d18-a121-cf0363b33a3f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387470781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.1387470781
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.9285475
Short name T1042
Test name
Test status
Simulation time 164690375 ps
CPU time 0.82 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 207348 kb
Host smart-3ffebfbc-caab-4155-88f8-8ca050bf2a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92854
75 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.9285475
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.4009117207
Short name T1863
Test name
Test status
Simulation time 152316976 ps
CPU time 0.81 seconds
Started Aug 06 08:08:49 PM PDT 24
Finished Aug 06 08:08:50 PM PDT 24
Peak memory 207380 kb
Host smart-fb926f1b-efcb-43e6-8179-c0a9e15413c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40091
17207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.4009117207
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.1150830947
Short name T835
Test name
Test status
Simulation time 379893470 ps
CPU time 1.44 seconds
Started Aug 06 08:08:57 PM PDT 24
Finished Aug 06 08:08:59 PM PDT 24
Peak memory 207344 kb
Host smart-df28273c-ad5a-479a-81bd-55531f0df40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11508
30947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.1150830947
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2813593339
Short name T538
Test name
Test status
Simulation time 645237402 ps
CPU time 1.76 seconds
Started Aug 06 08:09:02 PM PDT 24
Finished Aug 06 08:09:04 PM PDT 24
Peak memory 207396 kb
Host smart-a053d451-0d90-4d98-929e-d4436d81ce49
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2813593339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2813593339
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.4229148705
Short name T326
Test name
Test status
Simulation time 459194443 ps
CPU time 8.49 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:09:04 PM PDT 24
Peak memory 207600 kb
Host smart-c27baeb0-16c9-4bd9-9ff0-d05b0a985071
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229148705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.4229148705
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.3600515744
Short name T956
Test name
Test status
Simulation time 987701548 ps
CPU time 2.07 seconds
Started Aug 06 08:08:52 PM PDT 24
Finished Aug 06 08:08:54 PM PDT 24
Peak memory 207376 kb
Host smart-8a127f5a-d3a4-4e3f-a1d8-5feaa301005d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36005
15744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.3600515744
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.80944938
Short name T2442
Test name
Test status
Simulation time 169707660 ps
CPU time 0.84 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 207320 kb
Host smart-b07933b3-d32e-4f4c-b6bd-3b45ea0918ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80944
938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.80944938
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3419619203
Short name T1822
Test name
Test status
Simulation time 37589954 ps
CPU time 0.69 seconds
Started Aug 06 08:09:13 PM PDT 24
Finished Aug 06 08:09:14 PM PDT 24
Peak memory 207360 kb
Host smart-e46017b1-2e14-40cb-a045-93ff48607ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34196
19203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3419619203
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2807345561
Short name T2624
Test name
Test status
Simulation time 862001914 ps
CPU time 2.22 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 207480 kb
Host smart-cb9a6751-84a6-4768-a7c4-b73bbdfd6835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28073
45561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2807345561
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_types.3544619698
Short name T3096
Test name
Test status
Simulation time 448654144 ps
CPU time 1.38 seconds
Started Aug 06 08:09:01 PM PDT 24
Finished Aug 06 08:09:02 PM PDT 24
Peak memory 207332 kb
Host smart-8979da8e-8f14-4313-8f17-77b8c0c01027
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3544619698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.3544619698
Directory /workspace/49.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.876528057
Short name T1815
Test name
Test status
Simulation time 249179699 ps
CPU time 1.93 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 207560 kb
Host smart-3f0e95ab-99d6-4095-a2a2-6e920e299271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87652
8057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.876528057
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1697163574
Short name T2426
Test name
Test status
Simulation time 229279490 ps
CPU time 1.15 seconds
Started Aug 06 08:08:52 PM PDT 24
Finished Aug 06 08:08:54 PM PDT 24
Peak memory 215824 kb
Host smart-63942c43-b6f6-477b-a1c7-312673b5d530
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1697163574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1697163574
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2944032760
Short name T2263
Test name
Test status
Simulation time 218679363 ps
CPU time 0.92 seconds
Started Aug 06 08:09:02 PM PDT 24
Finished Aug 06 08:09:03 PM PDT 24
Peak memory 207352 kb
Host smart-af89f9a3-0f0e-40b0-bc0e-35fb4b092c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29440
32760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2944032760
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.279665644
Short name T2520
Test name
Test status
Simulation time 228101590 ps
CPU time 0.96 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:08:55 PM PDT 24
Peak memory 207352 kb
Host smart-aad4f858-d804-4a58-b9d3-3950b9b15ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27966
5644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.279665644
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.3047657874
Short name T1370
Test name
Test status
Simulation time 3829008267 ps
CPU time 112.52 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:10:49 PM PDT 24
Peak memory 224036 kb
Host smart-7672e593-fe37-44e7-9b05-6d0b60c6e098
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3047657874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3047657874
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.3192213283
Short name T2187
Test name
Test status
Simulation time 5012861102 ps
CPU time 56.47 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:09:57 PM PDT 24
Peak memory 207624 kb
Host smart-7f584e20-a8a0-4957-bf65-2179b43182b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3192213283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.3192213283
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.4096947725
Short name T670
Test name
Test status
Simulation time 168353995 ps
CPU time 0.86 seconds
Started Aug 06 08:08:58 PM PDT 24
Finished Aug 06 08:09:00 PM PDT 24
Peak memory 207348 kb
Host smart-a87de5ce-6a07-467d-b318-097a1f381d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40969
47725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.4096947725
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.2031480409
Short name T2294
Test name
Test status
Simulation time 30234257303 ps
CPU time 46.11 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:09:41 PM PDT 24
Peak memory 207872 kb
Host smart-69ced83f-ed26-49d9-ada1-965ad3bb48d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20314
80409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.2031480409
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.576350590
Short name T2234
Test name
Test status
Simulation time 4662678161 ps
CPU time 6.63 seconds
Started Aug 06 08:09:03 PM PDT 24
Finished Aug 06 08:09:09 PM PDT 24
Peak memory 215768 kb
Host smart-993f7756-57d8-409f-a427-b97c22c59ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57635
0590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.576350590
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.3055814822
Short name T2004
Test name
Test status
Simulation time 3218592125 ps
CPU time 90.33 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:10:27 PM PDT 24
Peak memory 215856 kb
Host smart-c1d26195-06ca-4c08-a2ad-71a13773d6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30558
14822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.3055814822
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.1318536036
Short name T1862
Test name
Test status
Simulation time 2570134493 ps
CPU time 74.5 seconds
Started Aug 06 08:08:57 PM PDT 24
Finished Aug 06 08:10:12 PM PDT 24
Peak memory 215944 kb
Host smart-2f950352-94ad-460e-9b1c-b8f35f8b4d4a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1318536036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.1318536036
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1202659495
Short name T2242
Test name
Test status
Simulation time 259708347 ps
CPU time 1.03 seconds
Started Aug 06 08:08:58 PM PDT 24
Finished Aug 06 08:08:59 PM PDT 24
Peak memory 207324 kb
Host smart-149b8a51-89ad-4efe-997b-f2210b804166
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1202659495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1202659495
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3098281695
Short name T1798
Test name
Test status
Simulation time 186440248 ps
CPU time 0.94 seconds
Started Aug 06 08:08:57 PM PDT 24
Finished Aug 06 08:08:58 PM PDT 24
Peak memory 207372 kb
Host smart-480a8f61-1278-41a0-9272-ac39a90c4af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30982
81695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3098281695
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.1337437308
Short name T674
Test name
Test status
Simulation time 1484407371 ps
CPU time 14.98 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:09:09 PM PDT 24
Peak memory 217076 kb
Host smart-3adf6d74-f849-45c7-895e-6dad2a5373ef
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1337437308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.1337437308
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.345654872
Short name T1967
Test name
Test status
Simulation time 161502166 ps
CPU time 0.86 seconds
Started Aug 06 08:09:04 PM PDT 24
Finished Aug 06 08:09:05 PM PDT 24
Peak memory 207360 kb
Host smart-a0f26138-46c7-4ae4-9db4-d7937891bf44
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=345654872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.345654872
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1035398253
Short name T108
Test name
Test status
Simulation time 161897429 ps
CPU time 0.94 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 207356 kb
Host smart-f5163770-e4e4-4622-8106-14c201f3f9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10353
98253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1035398253
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2513719387
Short name T155
Test name
Test status
Simulation time 188436536 ps
CPU time 0.88 seconds
Started Aug 06 08:08:57 PM PDT 24
Finished Aug 06 08:08:58 PM PDT 24
Peak memory 207332 kb
Host smart-d146b8cb-aca1-4fd0-90a1-073953d712b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25137
19387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2513719387
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.4164381656
Short name T1015
Test name
Test status
Simulation time 213870843 ps
CPU time 1 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 207316 kb
Host smart-80c80565-ab25-4645-bd37-d2ea7a4f440e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41643
81656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.4164381656
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.296303554
Short name T498
Test name
Test status
Simulation time 197875098 ps
CPU time 0.96 seconds
Started Aug 06 08:08:50 PM PDT 24
Finished Aug 06 08:08:51 PM PDT 24
Peak memory 207348 kb
Host smart-4ca39e4a-b972-4934-b287-b89263183c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29630
3554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.296303554
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.781199683
Short name T955
Test name
Test status
Simulation time 201072436 ps
CPU time 0.89 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:08:55 PM PDT 24
Peak memory 207372 kb
Host smart-f1402005-7bce-4c01-8372-a4eeeb6f7671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78119
9683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.781199683
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2906648843
Short name T210
Test name
Test status
Simulation time 210328336 ps
CPU time 0.97 seconds
Started Aug 06 08:09:06 PM PDT 24
Finished Aug 06 08:09:07 PM PDT 24
Peak memory 207420 kb
Host smart-51d0d36e-6f0e-4a72-9a63-aa7a29c1fceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29066
48843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2906648843
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.831380823
Short name T114
Test name
Test status
Simulation time 190643358 ps
CPU time 0.93 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 207296 kb
Host smart-921c429f-2d14-4751-a287-cafba3d7b48d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=831380823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.831380823
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3861545033
Short name T2115
Test name
Test status
Simulation time 180276130 ps
CPU time 0.87 seconds
Started Aug 06 08:08:58 PM PDT 24
Finished Aug 06 08:08:59 PM PDT 24
Peak memory 207324 kb
Host smart-f06e88a9-191c-4305-8db1-7c488b37bcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38615
45033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3861545033
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1773934887
Short name T2904
Test name
Test status
Simulation time 112872489 ps
CPU time 0.76 seconds
Started Aug 06 08:08:58 PM PDT 24
Finished Aug 06 08:08:59 PM PDT 24
Peak memory 207316 kb
Host smart-c3668446-5727-4652-9dd8-c4facb8f99ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17739
34887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1773934887
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.422339227
Short name T2436
Test name
Test status
Simulation time 18599335080 ps
CPU time 51.93 seconds
Started Aug 06 08:09:10 PM PDT 24
Finished Aug 06 08:10:02 PM PDT 24
Peak memory 224020 kb
Host smart-323c329d-e0f0-42e2-87ab-4080bfa3b101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42233
9227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.422339227
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2520192810
Short name T557
Test name
Test status
Simulation time 158269909 ps
CPU time 0.88 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 207372 kb
Host smart-bb928504-4410-44d7-8fb3-ca82e85829d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
92810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2520192810
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2561241174
Short name T1156
Test name
Test status
Simulation time 235213583 ps
CPU time 0.96 seconds
Started Aug 06 08:09:08 PM PDT 24
Finished Aug 06 08:09:09 PM PDT 24
Peak memory 207324 kb
Host smart-870bb1c4-400a-4473-92a0-906e96bae755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25612
41174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2561241174
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.1881782055
Short name T509
Test name
Test status
Simulation time 163543473 ps
CPU time 0.9 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:08:55 PM PDT 24
Peak memory 207372 kb
Host smart-1aa0ba42-e8cd-4162-b846-fa1344e03919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18817
82055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.1881782055
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.3055185126
Short name T1062
Test name
Test status
Simulation time 245064469 ps
CPU time 0.99 seconds
Started Aug 06 08:08:53 PM PDT 24
Finished Aug 06 08:08:54 PM PDT 24
Peak memory 207396 kb
Host smart-62580136-0987-4d8e-b1ca-9ed379b2fe7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30551
85126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.3055185126
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3736912518
Short name T2344
Test name
Test status
Simulation time 160052958 ps
CPU time 0.83 seconds
Started Aug 06 08:09:00 PM PDT 24
Finished Aug 06 08:09:01 PM PDT 24
Peak memory 207392 kb
Host smart-30175e60-1f03-4d66-923b-5ea595076f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37369
12518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3736912518
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_rx_full.2897101918
Short name T1478
Test name
Test status
Simulation time 257620432 ps
CPU time 1.23 seconds
Started Aug 06 08:09:07 PM PDT 24
Finished Aug 06 08:09:08 PM PDT 24
Peak memory 207320 kb
Host smart-c1584099-5122-4225-af34-265d4cc24fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28971
01918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.2897101918
Directory /workspace/49.usbdev_rx_full/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.3456731354
Short name T1080
Test name
Test status
Simulation time 192745140 ps
CPU time 0.9 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 207288 kb
Host smart-74c2c931-fee1-4619-9cf4-03e52ae0d335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34567
31354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3456731354
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.957948072
Short name T766
Test name
Test status
Simulation time 148859057 ps
CPU time 0.88 seconds
Started Aug 06 08:08:54 PM PDT 24
Finished Aug 06 08:08:55 PM PDT 24
Peak memory 207344 kb
Host smart-11629f05-0e78-4f14-899a-da366335a6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95794
8072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.957948072
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.998268540
Short name T1152
Test name
Test status
Simulation time 252461832 ps
CPU time 1.04 seconds
Started Aug 06 08:08:58 PM PDT 24
Finished Aug 06 08:08:59 PM PDT 24
Peak memory 207400 kb
Host smart-d0ffacee-8d03-4698-a533-279be3747af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99826
8540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.998268540
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.2858346073
Short name T2550
Test name
Test status
Simulation time 2759229711 ps
CPU time 79.08 seconds
Started Aug 06 08:08:56 PM PDT 24
Finished Aug 06 08:10:16 PM PDT 24
Peak memory 217440 kb
Host smart-9b8da0a8-b32b-4f60-b13d-13b11be095bd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2858346073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.2858346073
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2741773509
Short name T521
Test name
Test status
Simulation time 187732592 ps
CPU time 0.9 seconds
Started Aug 06 08:09:16 PM PDT 24
Finished Aug 06 08:09:17 PM PDT 24
Peak memory 207316 kb
Host smart-fc86f738-795e-42af-b8a3-5ab63158db54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27417
73509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2741773509
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1313510899
Short name T1231
Test name
Test status
Simulation time 181872623 ps
CPU time 0.94 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:12 PM PDT 24
Peak memory 207312 kb
Host smart-284f2af8-e270-4859-9ef8-36aee12b8300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13135
10899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1313510899
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.4224805625
Short name T3121
Test name
Test status
Simulation time 952378358 ps
CPU time 2.66 seconds
Started Aug 06 08:09:09 PM PDT 24
Finished Aug 06 08:09:12 PM PDT 24
Peak memory 207556 kb
Host smart-188402a1-2224-4152-82cd-bcdacbe32c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42248
05625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.4224805625
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2516002147
Short name T622
Test name
Test status
Simulation time 2367906980 ps
CPU time 18.26 seconds
Started Aug 06 08:09:13 PM PDT 24
Finished Aug 06 08:09:31 PM PDT 24
Peak memory 224004 kb
Host smart-4613c119-4de6-493f-921d-bdf29415b1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25160
02147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2516002147
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.3484465793
Short name T2954
Test name
Test status
Simulation time 436155223 ps
CPU time 8.23 seconds
Started Aug 06 08:08:52 PM PDT 24
Finished Aug 06 08:09:00 PM PDT 24
Peak memory 207572 kb
Host smart-182bdd65-03d6-4c24-82ca-d388377da9b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484465793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.3484465793
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.435689344
Short name T215
Test name
Test status
Simulation time 44534508 ps
CPU time 0.68 seconds
Started Aug 06 08:02:34 PM PDT 24
Finished Aug 06 08:02:35 PM PDT 24
Peak memory 207476 kb
Host smart-b9444609-1c27-4fa2-b642-d6ec0b8b0bdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=435689344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.435689344
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1927904597
Short name T1387
Test name
Test status
Simulation time 4980556281 ps
CPU time 7.03 seconds
Started Aug 06 08:02:18 PM PDT 24
Finished Aug 06 08:02:25 PM PDT 24
Peak memory 215816 kb
Host smart-846885e4-4bf7-4406-a7fb-5eec1c6ed2ea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927904597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.1927904597
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3722436837
Short name T651
Test name
Test status
Simulation time 15705685394 ps
CPU time 17.61 seconds
Started Aug 06 08:02:20 PM PDT 24
Finished Aug 06 08:02:38 PM PDT 24
Peak memory 215884 kb
Host smart-e0163cae-71cd-48be-a11f-91fa70d5e164
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722436837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3722436837
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1113434890
Short name T1410
Test name
Test status
Simulation time 25360398262 ps
CPU time 28.21 seconds
Started Aug 06 08:02:19 PM PDT 24
Finished Aug 06 08:02:47 PM PDT 24
Peak memory 215832 kb
Host smart-1a2788c6-6d93-482a-aaae-babebc82e022
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113434890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.1113434890
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.288952156
Short name T870
Test name
Test status
Simulation time 161578592 ps
CPU time 0.86 seconds
Started Aug 06 08:02:25 PM PDT 24
Finished Aug 06 08:02:26 PM PDT 24
Peak memory 207408 kb
Host smart-f167db4d-1c25-44ff-bbc2-7f0a6f3da641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28895
2156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.288952156
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3533820245
Short name T82
Test name
Test status
Simulation time 156153916 ps
CPU time 0.84 seconds
Started Aug 06 08:02:24 PM PDT 24
Finished Aug 06 08:02:25 PM PDT 24
Peak memory 207388 kb
Host smart-ce1f02d6-8ec6-4789-9629-253cd534aafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35338
20245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3533820245
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.1184221783
Short name T1933
Test name
Test status
Simulation time 203961231 ps
CPU time 0.92 seconds
Started Aug 06 08:02:13 PM PDT 24
Finished Aug 06 08:02:14 PM PDT 24
Peak memory 207380 kb
Host smart-4e5ccbcc-dbe2-4cd1-9aa2-0eeed2bfa941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11842
21783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.1184221783
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.806812551
Short name T1619
Test name
Test status
Simulation time 592746777 ps
CPU time 1.86 seconds
Started Aug 06 08:02:24 PM PDT 24
Finished Aug 06 08:02:26 PM PDT 24
Peak memory 207428 kb
Host smart-dd4bbcb3-5401-4300-9ed8-522f34a0eb20
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=806812551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.806812551
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3705471202
Short name T2445
Test name
Test status
Simulation time 53234759719 ps
CPU time 78.08 seconds
Started Aug 06 08:02:20 PM PDT 24
Finished Aug 06 08:03:39 PM PDT 24
Peak memory 207604 kb
Host smart-422f0c2f-1f13-4750-b453-a2caaf4b5ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37054
71202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3705471202
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.3389227451
Short name T1482
Test name
Test status
Simulation time 5658929490 ps
CPU time 35.52 seconds
Started Aug 06 08:02:13 PM PDT 24
Finished Aug 06 08:02:49 PM PDT 24
Peak memory 207692 kb
Host smart-f544bb20-47de-47cc-ac5e-505204cbecc2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389227451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.3389227451
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.1845302397
Short name T2873
Test name
Test status
Simulation time 831643430 ps
CPU time 2.14 seconds
Started Aug 06 08:02:28 PM PDT 24
Finished Aug 06 08:02:31 PM PDT 24
Peak memory 207284 kb
Host smart-d3b75c84-adb2-4988-9fa3-bffafbd2b421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18453
02397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.1845302397
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3323910516
Short name T64
Test name
Test status
Simulation time 166019396 ps
CPU time 0.87 seconds
Started Aug 06 08:02:29 PM PDT 24
Finished Aug 06 08:02:30 PM PDT 24
Peak memory 207348 kb
Host smart-424a3bc4-9f6e-4665-a83f-36d28db6f5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33239
10516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3323910516
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.392298439
Short name T239
Test name
Test status
Simulation time 61467273 ps
CPU time 0.73 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207312 kb
Host smart-82b06c2b-8a99-4a40-a3e3-f6e3b5720428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39229
8439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.392298439
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.295499566
Short name T2430
Test name
Test status
Simulation time 727368152 ps
CPU time 2.26 seconds
Started Aug 06 08:02:33 PM PDT 24
Finished Aug 06 08:02:35 PM PDT 24
Peak memory 207620 kb
Host smart-7452c37a-5c62-4c9d-8553-7350297a8bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29549
9566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.295499566
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3241311077
Short name T1119
Test name
Test status
Simulation time 296695753 ps
CPU time 2.45 seconds
Started Aug 06 08:02:29 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207564 kb
Host smart-d11dcd1b-4422-43bb-a2fa-c620de5e008c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32413
11077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3241311077
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2926707204
Short name T1027
Test name
Test status
Simulation time 176549609 ps
CPU time 0.98 seconds
Started Aug 06 08:02:32 PM PDT 24
Finished Aug 06 08:02:33 PM PDT 24
Peak memory 215968 kb
Host smart-56d76d3c-5200-4dcd-9f9b-e40bf5e64ba9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2926707204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2926707204
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.878316045
Short name T2835
Test name
Test status
Simulation time 136827621 ps
CPU time 0.81 seconds
Started Aug 06 08:02:38 PM PDT 24
Finished Aug 06 08:02:39 PM PDT 24
Peak memory 207336 kb
Host smart-61ae8ad8-0963-499b-91ab-567fb91708cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87831
6045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.878316045
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1852866273
Short name T3043
Test name
Test status
Simulation time 226213122 ps
CPU time 1.03 seconds
Started Aug 06 08:02:28 PM PDT 24
Finished Aug 06 08:02:29 PM PDT 24
Peak memory 207376 kb
Host smart-735e5883-8a19-4d9d-ad13-9f2bc21557f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18528
66273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1852866273
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.3054508986
Short name T3034
Test name
Test status
Simulation time 3514658997 ps
CPU time 35.05 seconds
Started Aug 06 08:02:36 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 224052 kb
Host smart-335871a1-2c1f-4193-81c7-4a80df86144f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3054508986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.3054508986
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.3862839589
Short name T1832
Test name
Test status
Simulation time 4655481229 ps
CPU time 56.59 seconds
Started Aug 06 08:02:38 PM PDT 24
Finished Aug 06 08:03:35 PM PDT 24
Peak memory 207640 kb
Host smart-54dd6878-997f-40f4-84f0-22c3af031528
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3862839589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.3862839589
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.91328559
Short name T2887
Test name
Test status
Simulation time 221782115 ps
CPU time 0.95 seconds
Started Aug 06 08:02:28 PM PDT 24
Finished Aug 06 08:02:30 PM PDT 24
Peak memory 207332 kb
Host smart-e8de8124-a590-4a95-be55-7cf20740ad94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91328
559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.91328559
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.570335840
Short name T627
Test name
Test status
Simulation time 28132261030 ps
CPU time 40.69 seconds
Started Aug 06 08:02:32 PM PDT 24
Finished Aug 06 08:03:12 PM PDT 24
Peak memory 207864 kb
Host smart-c31263f5-e427-46fc-a9c1-e416ea39088d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57033
5840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.570335840
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1291333118
Short name T1236
Test name
Test status
Simulation time 9550036767 ps
CPU time 12.44 seconds
Started Aug 06 08:02:36 PM PDT 24
Finished Aug 06 08:02:48 PM PDT 24
Peak memory 207572 kb
Host smart-70e5653e-f167-4a8c-b04b-f6c5e5de01a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12913
33118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1291333118
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.667387054
Short name T328
Test name
Test status
Simulation time 3674716329 ps
CPU time 26.03 seconds
Started Aug 06 08:02:34 PM PDT 24
Finished Aug 06 08:03:00 PM PDT 24
Peak memory 224164 kb
Host smart-20ea9dd4-ed7b-48fd-a862-7640d44d164a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66738
7054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.667387054
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2085676032
Short name T2424
Test name
Test status
Simulation time 3108381145 ps
CPU time 24.37 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 215836 kb
Host smart-a18b4ef4-3ce6-4520-bfb3-19e635b7bdf9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2085676032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2085676032
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.1123418539
Short name T2890
Test name
Test status
Simulation time 251708896 ps
CPU time 0.97 seconds
Started Aug 06 08:02:30 PM PDT 24
Finished Aug 06 08:02:31 PM PDT 24
Peak memory 207300 kb
Host smart-881c1edb-eef0-4cba-8950-3c2231c86027
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1123418539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1123418539
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3442263134
Short name T1720
Test name
Test status
Simulation time 186594658 ps
CPU time 0.93 seconds
Started Aug 06 08:02:29 PM PDT 24
Finished Aug 06 08:02:30 PM PDT 24
Peak memory 207376 kb
Host smart-8ba53b5a-635b-4b6c-a158-0b40213e90f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34422
63134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3442263134
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.1504667744
Short name T2794
Test name
Test status
Simulation time 2640485516 ps
CPU time 72.15 seconds
Started Aug 06 08:02:34 PM PDT 24
Finished Aug 06 08:03:46 PM PDT 24
Peak memory 217648 kb
Host smart-3727afe7-8e91-4677-b935-e59c45abaf7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15046
67744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.1504667744
Directory /workspace/5.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1592627322
Short name T1102
Test name
Test status
Simulation time 3416709922 ps
CPU time 40.06 seconds
Started Aug 06 08:02:27 PM PDT 24
Finished Aug 06 08:03:08 PM PDT 24
Peak memory 223976 kb
Host smart-96521b2e-f77f-4961-8f05-77bd8558cf8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1592627322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1592627322
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.940858971
Short name T190
Test name
Test status
Simulation time 3035170450 ps
CPU time 28.28 seconds
Started Aug 06 08:02:33 PM PDT 24
Finished Aug 06 08:03:01 PM PDT 24
Peak memory 215900 kb
Host smart-bed85f19-bb9e-4086-bd7e-be0089b2f0ae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=940858971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.940858971
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.862995123
Short name T1446
Test name
Test status
Simulation time 151091158 ps
CPU time 0.87 seconds
Started Aug 06 08:02:30 PM PDT 24
Finished Aug 06 08:02:31 PM PDT 24
Peak memory 207308 kb
Host smart-bb4b377b-f5ca-459a-a6e0-bdd3dee45e7f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=862995123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.862995123
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2717584782
Short name T938
Test name
Test status
Simulation time 209123486 ps
CPU time 0.94 seconds
Started Aug 06 08:02:35 PM PDT 24
Finished Aug 06 08:02:36 PM PDT 24
Peak memory 207404 kb
Host smart-f54f141e-5353-4924-88b7-f0b4cac732b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27175
84782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2717584782
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3058625793
Short name T2909
Test name
Test status
Simulation time 206572380 ps
CPU time 0.92 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207324 kb
Host smart-1db7ac65-0b2a-45ef-8495-44c6d5ac1fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30586
25793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3058625793
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.187400154
Short name T2127
Test name
Test status
Simulation time 169866706 ps
CPU time 0.97 seconds
Started Aug 06 08:02:38 PM PDT 24
Finished Aug 06 08:02:39 PM PDT 24
Peak memory 207356 kb
Host smart-a4eb4661-f639-42e2-b518-61b81263a39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18740
0154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.187400154
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2303599395
Short name T2732
Test name
Test status
Simulation time 152319997 ps
CPU time 0.85 seconds
Started Aug 06 08:02:34 PM PDT 24
Finished Aug 06 08:02:35 PM PDT 24
Peak memory 207380 kb
Host smart-4c54bf71-e854-4d54-88f7-b95ac1905385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23035
99395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2303599395
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3628088377
Short name T2012
Test name
Test status
Simulation time 158735657 ps
CPU time 0.86 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207372 kb
Host smart-055acd5d-dd74-4f35-95a3-6081f73073b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36280
88377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3628088377
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.960270129
Short name T1943
Test name
Test status
Simulation time 254436274 ps
CPU time 1.07 seconds
Started Aug 06 08:02:29 PM PDT 24
Finished Aug 06 08:02:30 PM PDT 24
Peak memory 207380 kb
Host smart-35bb4fa0-e8cd-414a-b738-dd4185dbf5a4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=960270129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.960270129
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3348324486
Short name T811
Test name
Test status
Simulation time 152089938 ps
CPU time 0.84 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207284 kb
Host smart-a101159a-6797-4fa7-af7a-68e4277aac95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33483
24486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3348324486
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.4248465038
Short name T1168
Test name
Test status
Simulation time 34667052 ps
CPU time 0.67 seconds
Started Aug 06 08:02:30 PM PDT 24
Finished Aug 06 08:02:31 PM PDT 24
Peak memory 207316 kb
Host smart-36bbe9fb-5fe8-4308-a08a-f074e43357d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42484
65038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.4248465038
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3019518117
Short name T1300
Test name
Test status
Simulation time 7234112979 ps
CPU time 19.27 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:51 PM PDT 24
Peak memory 223812 kb
Host smart-e6a26a36-ac2e-46ae-a11b-036cdc4a6f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30195
18117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3019518117
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.332007894
Short name T524
Test name
Test status
Simulation time 195225613 ps
CPU time 0.94 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207320 kb
Host smart-269b4b23-57e4-4019-8b96-d374b14148aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33200
7894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.332007894
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1191853063
Short name T2427
Test name
Test status
Simulation time 185098553 ps
CPU time 0.92 seconds
Started Aug 06 08:02:36 PM PDT 24
Finished Aug 06 08:02:38 PM PDT 24
Peak memory 207332 kb
Host smart-ced383c6-0f09-4f1d-9d63-cb9a157d5b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11918
53063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1191853063
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.3515226171
Short name T193
Test name
Test status
Simulation time 4334760888 ps
CPU time 107.89 seconds
Started Aug 06 08:02:39 PM PDT 24
Finished Aug 06 08:04:27 PM PDT 24
Peak memory 215876 kb
Host smart-296292dc-70af-4dc6-8bf7-19e7783c7771
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515226171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.3515226171
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1688394465
Short name T2351
Test name
Test status
Simulation time 2594414059 ps
CPU time 50.12 seconds
Started Aug 06 08:02:33 PM PDT 24
Finished Aug 06 08:03:24 PM PDT 24
Peak memory 215872 kb
Host smart-59e39bf1-8b93-4653-8c5a-3626e9186cf9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1688394465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1688394465
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.307106246
Short name T1901
Test name
Test status
Simulation time 6378237737 ps
CPU time 74.66 seconds
Started Aug 06 08:02:34 PM PDT 24
Finished Aug 06 08:03:49 PM PDT 24
Peak memory 219104 kb
Host smart-a9ef925b-b479-46d0-9102-20b397887648
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=307106246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.307106246
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2136772159
Short name T2907
Test name
Test status
Simulation time 213379623 ps
CPU time 0.99 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207296 kb
Host smart-9a2caad5-0be4-4b86-af95-2cc26661a2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21367
72159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2136772159
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.853939148
Short name T1373
Test name
Test status
Simulation time 166740813 ps
CPU time 0.89 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207376 kb
Host smart-5143af34-e752-4992-97d8-468a6d8558ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85393
9148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.853939148
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_resume_link_active.2784844718
Short name T2504
Test name
Test status
Simulation time 20230952508 ps
CPU time 21.71 seconds
Started Aug 06 08:02:39 PM PDT 24
Finished Aug 06 08:03:00 PM PDT 24
Peak memory 207528 kb
Host smart-8d21c97e-cefb-4256-bbe7-a88a1070f0e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27848
44718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.2784844718
Directory /workspace/5.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.411489640
Short name T1440
Test name
Test status
Simulation time 149654817 ps
CPU time 0.83 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207380 kb
Host smart-dbdb72f2-e803-4915-867c-dec2acdc4903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41148
9640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.411489640
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_rx_full.4150866971
Short name T2370
Test name
Test status
Simulation time 356069170 ps
CPU time 1.27 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:33 PM PDT 24
Peak memory 207312 kb
Host smart-0c2fb04f-4f51-45a4-a108-9d69b59af442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41508
66971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.4150866971
Directory /workspace/5.usbdev_rx_full/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3249895765
Short name T1266
Test name
Test status
Simulation time 166286940 ps
CPU time 0.85 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207204 kb
Host smart-5bfad0ef-8968-40ee-b652-2aaf1ac67890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32498
95765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3249895765
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.130272364
Short name T1814
Test name
Test status
Simulation time 168436066 ps
CPU time 0.86 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:33 PM PDT 24
Peak memory 207400 kb
Host smart-202e7507-7c9c-4db6-8b82-e9b69f5ddd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13027
2364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.130272364
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2664513778
Short name T2989
Test name
Test status
Simulation time 221480485 ps
CPU time 1.03 seconds
Started Aug 06 08:02:27 PM PDT 24
Finished Aug 06 08:02:29 PM PDT 24
Peak memory 207352 kb
Host smart-458530e3-69d9-4d95-adc8-e04a8760d205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26645
13778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2664513778
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.2829129137
Short name T177
Test name
Test status
Simulation time 2175383549 ps
CPU time 17.78 seconds
Started Aug 06 08:02:35 PM PDT 24
Finished Aug 06 08:02:53 PM PDT 24
Peak memory 224048 kb
Host smart-d620cf09-de6f-4dc9-8865-9d467ba0d3c3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2829129137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.2829129137
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2842605877
Short name T2046
Test name
Test status
Simulation time 240159964 ps
CPU time 0.93 seconds
Started Aug 06 08:02:27 PM PDT 24
Finished Aug 06 08:02:28 PM PDT 24
Peak memory 207360 kb
Host smart-370c90c4-26b8-4f5f-8646-8ad0cad84490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28426
05877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2842605877
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3475893855
Short name T513
Test name
Test status
Simulation time 171634807 ps
CPU time 0.84 seconds
Started Aug 06 08:02:37 PM PDT 24
Finished Aug 06 08:02:38 PM PDT 24
Peak memory 207344 kb
Host smart-d745a50a-4b38-40b9-902c-af990c475bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34758
93855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3475893855
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.3317396394
Short name T2621
Test name
Test status
Simulation time 269220446 ps
CPU time 1.09 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:33 PM PDT 24
Peak memory 207316 kb
Host smart-621a95ac-c5f6-41b9-a6ec-b44cfdb11f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33173
96394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.3317396394
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.3418122226
Short name T1110
Test name
Test status
Simulation time 2196970647 ps
CPU time 22.2 seconds
Started Aug 06 08:02:30 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 215844 kb
Host smart-93f2b7f0-7f0a-4fb4-a2ff-fb4a350d58cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34181
22226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3418122226
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.974523702
Short name T867
Test name
Test status
Simulation time 142199984 ps
CPU time 0.88 seconds
Started Aug 06 08:02:20 PM PDT 24
Finished Aug 06 08:02:21 PM PDT 24
Peak memory 207336 kb
Host smart-6a4d9a53-444c-4715-84f6-490e2ae1d989
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974523702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host_
handshake.974523702
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/50.usbdev_endpoint_types.3688053294
Short name T248
Test name
Test status
Simulation time 430798410 ps
CPU time 1.27 seconds
Started Aug 06 08:09:08 PM PDT 24
Finished Aug 06 08:09:09 PM PDT 24
Peak memory 207288 kb
Host smart-3cc9b4b0-c12c-4f24-9cc7-d03f7ecd7a73
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3688053294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.3688053294
Directory /workspace/50.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/51.usbdev_endpoint_types.3374332650
Short name T331
Test name
Test status
Simulation time 586769066 ps
CPU time 1.58 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207320 kb
Host smart-a60f754f-bea4-4668-9d39-9c251c9afb79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3374332650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.3374332650
Directory /workspace/51.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/52.usbdev_endpoint_types.1844506099
Short name T355
Test name
Test status
Simulation time 342366465 ps
CPU time 1.13 seconds
Started Aug 06 08:09:14 PM PDT 24
Finished Aug 06 08:09:16 PM PDT 24
Peak memory 207280 kb
Host smart-ab570005-8ba0-404c-a5b9-0540cd3f2cae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1844506099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.1844506099
Directory /workspace/52.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/53.usbdev_endpoint_types.3543800617
Short name T875
Test name
Test status
Simulation time 337271432 ps
CPU time 1.02 seconds
Started Aug 06 08:09:01 PM PDT 24
Finished Aug 06 08:09:02 PM PDT 24
Peak memory 207284 kb
Host smart-b0ab9fef-beb7-4d1d-b47c-cd1aed0c7c70
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3543800617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.3543800617
Directory /workspace/53.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/54.usbdev_endpoint_types.3680624309
Short name T2819
Test name
Test status
Simulation time 507531902 ps
CPU time 1.42 seconds
Started Aug 06 08:09:17 PM PDT 24
Finished Aug 06 08:09:19 PM PDT 24
Peak memory 207288 kb
Host smart-b3d721a4-eed4-49cb-9d55-478334c799af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3680624309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.3680624309
Directory /workspace/54.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/55.usbdev_endpoint_types.1285636657
Short name T381
Test name
Test status
Simulation time 693546929 ps
CPU time 1.72 seconds
Started Aug 06 08:09:09 PM PDT 24
Finished Aug 06 08:09:11 PM PDT 24
Peak memory 207376 kb
Host smart-c9b150af-6e4d-4a0f-900f-bcd92c72f140
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1285636657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.1285636657
Directory /workspace/55.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/56.usbdev_endpoint_types.249738812
Short name T373
Test name
Test status
Simulation time 794310556 ps
CPU time 1.76 seconds
Started Aug 06 08:09:02 PM PDT 24
Finished Aug 06 08:09:04 PM PDT 24
Peak memory 207296 kb
Host smart-6cb68db8-5dbb-490f-8637-f14f22fc4132
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=249738812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.249738812
Directory /workspace/56.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/57.usbdev_endpoint_types.2399129644
Short name T2311
Test name
Test status
Simulation time 243916843 ps
CPU time 0.92 seconds
Started Aug 06 08:09:04 PM PDT 24
Finished Aug 06 08:09:05 PM PDT 24
Peak memory 207328 kb
Host smart-1f83160d-54b3-46fa-9688-0d51579a908b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2399129644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.2399129644
Directory /workspace/57.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/59.usbdev_endpoint_types.1123112626
Short name T466
Test name
Test status
Simulation time 180137006 ps
CPU time 0.87 seconds
Started Aug 06 08:09:16 PM PDT 24
Finished Aug 06 08:09:17 PM PDT 24
Peak memory 207356 kb
Host smart-5e569c87-8c00-4a81-94be-9b0cb03873b4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1123112626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.1123112626
Directory /workspace/59.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.4058088612
Short name T1417
Test name
Test status
Simulation time 48144980 ps
CPU time 0.71 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:02:53 PM PDT 24
Peak memory 207416 kb
Host smart-9c6b2837-a9c5-491b-9c4a-8ab220bf3973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4058088612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.4058088612
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.4144118803
Short name T8
Test name
Test status
Simulation time 10752360912 ps
CPU time 15.89 seconds
Started Aug 06 08:02:33 PM PDT 24
Finished Aug 06 08:02:49 PM PDT 24
Peak memory 207720 kb
Host smart-ec9732b7-4269-4019-a436-8b2270674a08
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144118803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.4144118803
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.4026372172
Short name T2428
Test name
Test status
Simulation time 21204118060 ps
CPU time 24.44 seconds
Started Aug 06 08:02:30 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 207668 kb
Host smart-0193bad7-cb51-4f58-bcc6-16f04ddad3b5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026372172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.4026372172
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3225091066
Short name T253
Test name
Test status
Simulation time 24110925497 ps
CPU time 34.8 seconds
Started Aug 06 08:02:30 PM PDT 24
Finished Aug 06 08:03:05 PM PDT 24
Peak memory 215844 kb
Host smart-a815e00f-fdde-4933-b8b9-0d37698d0dae
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225091066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.3225091066
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.4107970722
Short name T718
Test name
Test status
Simulation time 164561859 ps
CPU time 0.91 seconds
Started Aug 06 08:02:31 PM PDT 24
Finished Aug 06 08:02:32 PM PDT 24
Peak memory 207036 kb
Host smart-11a2a532-7311-44a9-9983-4f823ac16d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41079
70722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.4107970722
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.4226848733
Short name T846
Test name
Test status
Simulation time 148009190 ps
CPU time 0.82 seconds
Started Aug 06 08:02:29 PM PDT 24
Finished Aug 06 08:02:30 PM PDT 24
Peak memory 207320 kb
Host smart-b7bf3795-a59c-4373-91d0-89c48d588968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42268
48733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.4226848733
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.2096891180
Short name T2153
Test name
Test status
Simulation time 434851876 ps
CPU time 1.52 seconds
Started Aug 06 08:02:25 PM PDT 24
Finished Aug 06 08:02:26 PM PDT 24
Peak memory 207296 kb
Host smart-4047e6f3-5d4c-4b21-8418-d7497996c0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20968
91180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.2096891180
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1617227175
Short name T3006
Test name
Test status
Simulation time 590297851 ps
CPU time 1.86 seconds
Started Aug 06 08:02:32 PM PDT 24
Finished Aug 06 08:02:34 PM PDT 24
Peak memory 207328 kb
Host smart-4ce53581-f943-4525-8d1a-ea0391d47827
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1617227175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1617227175
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.1948615576
Short name T2059
Test name
Test status
Simulation time 48283895729 ps
CPU time 80.81 seconds
Started Aug 06 08:02:49 PM PDT 24
Finished Aug 06 08:04:10 PM PDT 24
Peak memory 207668 kb
Host smart-dee14814-160b-40c9-9526-212bcbabd3a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19486
15576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.1948615576
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.1743444257
Short name T2723
Test name
Test status
Simulation time 908535640 ps
CPU time 19.16 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:03:14 PM PDT 24
Peak memory 207536 kb
Host smart-3a5a1e9a-7e54-4249-a82a-c56b3811beb4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743444257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.1743444257
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.4059467779
Short name T2450
Test name
Test status
Simulation time 1254223547 ps
CPU time 2.24 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:57 PM PDT 24
Peak memory 207344 kb
Host smart-3c6b4f16-1e05-4905-984f-b2fb13475340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40594
67779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.4059467779
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.781337674
Short name T2076
Test name
Test status
Simulation time 141392444 ps
CPU time 0.81 seconds
Started Aug 06 08:02:50 PM PDT 24
Finished Aug 06 08:02:50 PM PDT 24
Peak memory 207364 kb
Host smart-05c7ae62-81c5-4c15-878d-a39a2b8a3ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78133
7674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.781337674
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3806333710
Short name T1262
Test name
Test status
Simulation time 92459666 ps
CPU time 0.87 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207316 kb
Host smart-1ee112a4-d53d-4780-a6e8-25efafa1f60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38063
33710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3806333710
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1018193097
Short name T1489
Test name
Test status
Simulation time 921285810 ps
CPU time 2.47 seconds
Started Aug 06 08:02:50 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207576 kb
Host smart-e565ccb4-88eb-4066-b155-457b206ec227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10181
93097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1018193097
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_types.2409135760
Short name T2856
Test name
Test status
Simulation time 327282070 ps
CPU time 1.15 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207324 kb
Host smart-682f79c6-1449-4da1-9c15-d36009bfa651
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2409135760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.2409135760
Directory /workspace/6.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1723818751
Short name T2501
Test name
Test status
Simulation time 242708702 ps
CPU time 1.56 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:53 PM PDT 24
Peak memory 207572 kb
Host smart-8eba8142-5339-4213-8cd8-14017605dd1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17238
18751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1723818751
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3966044354
Short name T976
Test name
Test status
Simulation time 206739364 ps
CPU time 1.14 seconds
Started Aug 06 08:02:50 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 215796 kb
Host smart-032b2265-d00e-48ea-9f7d-b1df99f7d2d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3966044354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3966044354
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2385968730
Short name T792
Test name
Test status
Simulation time 138779089 ps
CPU time 0.81 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207304 kb
Host smart-fa4fbeb7-6401-4bfc-a68e-54a727ec86dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23859
68730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2385968730
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1408589446
Short name T1763
Test name
Test status
Simulation time 166859098 ps
CPU time 0.95 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207316 kb
Host smart-efc99ec5-6b71-455c-82ec-ec233e36fcad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14085
89446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1408589446
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.686945229
Short name T809
Test name
Test status
Simulation time 2645472207 ps
CPU time 75.49 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:04:09 PM PDT 24
Peak memory 223804 kb
Host smart-dc9a4177-2eae-464b-b058-a8096ae14214
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=686945229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.686945229
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.632534456
Short name T1868
Test name
Test status
Simulation time 216285383 ps
CPU time 0.9 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207396 kb
Host smart-fb22ff52-d5dc-4e70-86ea-351fef0a22b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63253
4456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.632534456
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2821751871
Short name T2983
Test name
Test status
Simulation time 32817269026 ps
CPU time 47.48 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:03:41 PM PDT 24
Peak memory 207648 kb
Host smart-f39c8dce-23cf-4469-afba-3f64a1882d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28217
51871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2821751871
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3072524367
Short name T3085
Test name
Test status
Simulation time 4526437502 ps
CPU time 6.96 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:58 PM PDT 24
Peak memory 215752 kb
Host smart-df97a74e-ecb5-483a-8f9e-8671ad903e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30725
24367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3072524367
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.4270307370
Short name T2971
Test name
Test status
Simulation time 2472570322 ps
CPU time 71.55 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:04:02 PM PDT 24
Peak memory 218316 kb
Host smart-f3149c95-fdd8-4836-a2c6-d479b64b591c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42703
07370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.4270307370
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.1260791649
Short name T1715
Test name
Test status
Simulation time 2290562074 ps
CPU time 17.28 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:03:09 PM PDT 24
Peak memory 215808 kb
Host smart-dbda2569-3a67-475a-8b89-cad6a8d8d9d9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1260791649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.1260791649
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2080313834
Short name T1223
Test name
Test status
Simulation time 245321189 ps
CPU time 1.01 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 207300 kb
Host smart-b79e0017-ae7b-4d38-a431-53fbc6b82644
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2080313834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2080313834
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3575586377
Short name T2381
Test name
Test status
Simulation time 197344742 ps
CPU time 0.95 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 207372 kb
Host smart-ae5f8c3c-bf21-46a8-89da-2d646ae1c688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35755
86377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3575586377
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.2371455195
Short name T1859
Test name
Test status
Simulation time 4020041574 ps
CPU time 29.44 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:03:21 PM PDT 24
Peak memory 215876 kb
Host smart-8970d604-1f07-464d-81a5-a7c97e86ee7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23714
55195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.2371455195
Directory /workspace/6.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2768790852
Short name T125
Test name
Test status
Simulation time 2433588551 ps
CPU time 69.7 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:04:04 PM PDT 24
Peak memory 218092 kb
Host smart-7f067be0-672d-43e2-9f96-37f8c18363bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2768790852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2768790852
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.947917040
Short name T2780
Test name
Test status
Simulation time 4019245534 ps
CPU time 116.03 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:04:48 PM PDT 24
Peak memory 217364 kb
Host smart-ffcb32a9-6799-43b6-a813-8db342b2c933
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=947917040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.947917040
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.1525589419
Short name T1547
Test name
Test status
Simulation time 173424510 ps
CPU time 0.92 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:02:53 PM PDT 24
Peak memory 207348 kb
Host smart-e40ca87b-0ea2-4892-8ddd-2a6a2b7d1e3f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1525589419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.1525589419
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1431390232
Short name T2209
Test name
Test status
Simulation time 172792712 ps
CPU time 0.89 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 207356 kb
Host smart-8cfab85e-0174-425e-a562-82ada4733396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14313
90232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1431390232
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.412575562
Short name T162
Test name
Test status
Simulation time 192100715 ps
CPU time 0.99 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207352 kb
Host smart-3f135b06-21ab-4a89-a492-fa6fedf6134f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257
5562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.412575562
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3334020005
Short name T2995
Test name
Test status
Simulation time 182532389 ps
CPU time 0.96 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207324 kb
Host smart-51d6151a-34e2-4a68-ac80-0099ac3d2d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33340
20005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3334020005
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.4280267634
Short name T2619
Test name
Test status
Simulation time 196327357 ps
CPU time 0.97 seconds
Started Aug 06 08:02:50 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207400 kb
Host smart-da51ed5e-e661-4c78-a68a-1374d5b2bc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42802
67634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.4280267634
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1765406274
Short name T2306
Test name
Test status
Simulation time 187600258 ps
CPU time 0.87 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:02:53 PM PDT 24
Peak memory 207400 kb
Host smart-f5d8b936-3750-4a10-b13d-83332e1f4b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17654
06274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1765406274
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2325900375
Short name T999
Test name
Test status
Simulation time 162176319 ps
CPU time 0.85 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 207316 kb
Host smart-69c073d3-ed14-401b-b4ef-4aabf2d70c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23259
00375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2325900375
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.4042222424
Short name T1965
Test name
Test status
Simulation time 228671983 ps
CPU time 0.93 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 207352 kb
Host smart-fecc1fb5-2ab4-4026-9717-4d7e71a5bf2d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4042222424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.4042222424
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3839875757
Short name T1343
Test name
Test status
Simulation time 146592988 ps
CPU time 0.81 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207272 kb
Host smart-98014548-d623-4042-8349-74abf9e04dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38398
75757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3839875757
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.564250698
Short name T1627
Test name
Test status
Simulation time 45892286 ps
CPU time 0.72 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:02:53 PM PDT 24
Peak memory 207316 kb
Host smart-9d75fa77-7289-4d12-b9ef-9c181929866a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56425
0698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.564250698
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1786848927
Short name T1552
Test name
Test status
Simulation time 11051066828 ps
CPU time 27.34 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 215876 kb
Host smart-68d7b175-bdfa-446e-bfad-4d23d8e975c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17868
48927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1786848927
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2561274273
Short name T1188
Test name
Test status
Simulation time 162788759 ps
CPU time 0.95 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207596 kb
Host smart-a621c616-f3cf-46cf-94c4-d7c14680e4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25612
74273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2561274273
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.433011887
Short name T843
Test name
Test status
Simulation time 213112217 ps
CPU time 0.94 seconds
Started Aug 06 08:02:48 PM PDT 24
Finished Aug 06 08:02:49 PM PDT 24
Peak memory 207168 kb
Host smart-76ec9f05-eb1f-4adf-85b7-e8d8ba0e78ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43301
1887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.433011887
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3313769236
Short name T2321
Test name
Test status
Simulation time 5101957408 ps
CPU time 17.99 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:03:09 PM PDT 24
Peak memory 215812 kb
Host smart-a5a851cf-2f41-4335-9450-1ca43bd57668
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313769236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3313769236
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2838013643
Short name T1411
Test name
Test status
Simulation time 14359646237 ps
CPU time 326.01 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:08:19 PM PDT 24
Peak memory 223920 kb
Host smart-9693b9bb-aee7-4437-a329-4affcc19121e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2838013643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2838013643
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2642056951
Short name T2829
Test name
Test status
Simulation time 13960110019 ps
CPU time 85.7 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:04:18 PM PDT 24
Peak memory 224052 kb
Host smart-3c5585dd-bf21-4f70-8a5d-c4e235fde503
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642056951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2642056951
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.1915789779
Short name T2801
Test name
Test status
Simulation time 254956695 ps
CPU time 0.98 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207300 kb
Host smart-922486f4-9d81-46ce-bb89-7477fa18f777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19157
89779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.1915789779
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1247843051
Short name T1296
Test name
Test status
Simulation time 171239273 ps
CPU time 0.92 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 206492 kb
Host smart-848944b9-e541-49e2-b1d9-02156a137d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12478
43051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1247843051
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_resume_link_active.3877812517
Short name T116
Test name
Test status
Simulation time 20180665874 ps
CPU time 23.81 seconds
Started Aug 06 08:02:49 PM PDT 24
Finished Aug 06 08:03:13 PM PDT 24
Peak memory 207684 kb
Host smart-407dc79b-c7d5-4093-a1b3-14e55e092f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38778
12517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.3877812517
Directory /workspace/6.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3587430231
Short name T2930
Test name
Test status
Simulation time 235423547 ps
CPU time 0.95 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:02:53 PM PDT 24
Peak memory 207372 kb
Host smart-18e5b619-131a-47f2-bce2-2f88a07761c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35874
30231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3587430231
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_rx_full.1654321092
Short name T49
Test name
Test status
Simulation time 273680644 ps
CPU time 1.05 seconds
Started Aug 06 08:02:55 PM PDT 24
Finished Aug 06 08:02:56 PM PDT 24
Peak memory 207288 kb
Host smart-3cc12e86-7bff-4769-8343-43ab1566d0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16543
21092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.1654321092
Directory /workspace/6.usbdev_rx_full/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2677591610
Short name T179
Test name
Test status
Simulation time 149912888 ps
CPU time 0.84 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:02:54 PM PDT 24
Peak memory 207280 kb
Host smart-5cc4d150-f57d-4737-9f66-cd782f21ffec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26775
91610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2677591610
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1283882500
Short name T1765
Test name
Test status
Simulation time 187813025 ps
CPU time 0.91 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207360 kb
Host smart-6a267556-a209-46ba-937f-1bb1b1541a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12838
82500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1283882500
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1428885537
Short name T3050
Test name
Test status
Simulation time 239178596 ps
CPU time 1.05 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:02:54 PM PDT 24
Peak memory 207176 kb
Host smart-c89d81b3-c964-4296-9194-913fba6c2de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14288
85537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1428885537
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1276637415
Short name T487
Test name
Test status
Simulation time 1726296661 ps
CPU time 16.67 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:03:09 PM PDT 24
Peak memory 217376 kb
Host smart-e05bb141-5782-4705-8359-aa2bb011dc22
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1276637415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1276637415
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2325432519
Short name T468
Test name
Test status
Simulation time 179713993 ps
CPU time 0.82 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:52 PM PDT 24
Peak memory 207452 kb
Host smart-27bf5aad-ab9b-47e1-b883-b60d69033f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23254
32519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2325432519
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.673694553
Short name T590
Test name
Test status
Simulation time 212237846 ps
CPU time 1.02 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:02:54 PM PDT 24
Peak memory 207332 kb
Host smart-a3456b0a-701d-414c-ad3c-ad2561a93769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67369
4553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.673694553
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.158442672
Short name T3094
Test name
Test status
Simulation time 1295133397 ps
CPU time 3.08 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:02:54 PM PDT 24
Peak memory 207556 kb
Host smart-4a4f6e8b-bf73-48b5-8116-06e3112b84dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
2672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.158442672
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.1637555540
Short name T936
Test name
Test status
Simulation time 3120067456 ps
CPU time 25.06 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 217656 kb
Host smart-7bb65b40-4745-498b-be9b-2c9f56450df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16375
55540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.1637555540
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.199734779
Short name T1394
Test name
Test status
Simulation time 581241452 ps
CPU time 12.02 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:03:06 PM PDT 24
Peak memory 207512 kb
Host smart-2cede229-86ee-4134-bb85-7c94212ebdb8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199734779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host_
handshake.199734779
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/60.usbdev_endpoint_types.1988090635
Short name T375
Test name
Test status
Simulation time 439518050 ps
CPU time 1.28 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:08:57 PM PDT 24
Peak memory 207332 kb
Host smart-a367963c-bbc4-470b-a5f5-e333660e0d61
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1988090635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.1988090635
Directory /workspace/60.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/61.usbdev_endpoint_types.280097144
Short name T356
Test name
Test status
Simulation time 425781726 ps
CPU time 1.25 seconds
Started Aug 06 08:09:13 PM PDT 24
Finished Aug 06 08:09:14 PM PDT 24
Peak memory 207356 kb
Host smart-6ee4543f-def6-420c-85ab-3262f1f78b63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=280097144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.280097144
Directory /workspace/61.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/62.usbdev_endpoint_types.2325488086
Short name T360
Test name
Test status
Simulation time 526638734 ps
CPU time 1.34 seconds
Started Aug 06 08:09:13 PM PDT 24
Finished Aug 06 08:09:14 PM PDT 24
Peak memory 207328 kb
Host smart-2d305c19-50ae-4d6a-b5f8-a847ca6c0948
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2325488086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.2325488086
Directory /workspace/62.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/63.usbdev_endpoint_types.1593909189
Short name T2112
Test name
Test status
Simulation time 350361923 ps
CPU time 1.28 seconds
Started Aug 06 08:09:12 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207328 kb
Host smart-36c14810-f424-4426-b214-6c02768af14f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1593909189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.1593909189
Directory /workspace/63.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/64.usbdev_endpoint_types.150068773
Short name T2567
Test name
Test status
Simulation time 471200806 ps
CPU time 1.29 seconds
Started Aug 06 08:09:15 PM PDT 24
Finished Aug 06 08:09:17 PM PDT 24
Peak memory 207232 kb
Host smart-58ce6c66-0cde-4ab0-87b1-7df2af814adc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=150068773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.150068773
Directory /workspace/64.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/65.usbdev_endpoint_types.1917381562
Short name T646
Test name
Test status
Simulation time 532329266 ps
CPU time 1.33 seconds
Started Aug 06 08:09:16 PM PDT 24
Finished Aug 06 08:09:18 PM PDT 24
Peak memory 207332 kb
Host smart-49733fc7-dd91-4e76-94f1-d1bf497bcceb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1917381562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.1917381562
Directory /workspace/65.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/66.usbdev_endpoint_types.233511433
Short name T3078
Test name
Test status
Simulation time 320510833 ps
CPU time 1.1 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:12 PM PDT 24
Peak memory 207288 kb
Host smart-354b7456-5e3b-4232-b643-ec5fc2c60f4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=233511433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.233511433
Directory /workspace/66.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/67.usbdev_endpoint_types.1127914439
Short name T277
Test name
Test status
Simulation time 616438944 ps
CPU time 1.69 seconds
Started Aug 06 08:09:11 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207320 kb
Host smart-2aaa0f0e-039d-48d7-96c5-542df36316d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1127914439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.1127914439
Directory /workspace/67.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/68.usbdev_endpoint_types.3228070778
Short name T2878
Test name
Test status
Simulation time 240216202 ps
CPU time 1.05 seconds
Started Aug 06 08:09:12 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207328 kb
Host smart-08eacbf3-ca67-40fd-afc8-d5007e4916cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3228070778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.3228070778
Directory /workspace/68.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/69.usbdev_endpoint_types.3105827127
Short name T2146
Test name
Test status
Simulation time 377694365 ps
CPU time 1.28 seconds
Started Aug 06 08:09:15 PM PDT 24
Finished Aug 06 08:09:16 PM PDT 24
Peak memory 207172 kb
Host smart-f977d630-46bf-48ce-b506-29f43e9eeb51
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3105827127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.3105827127
Directory /workspace/69.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.1471023841
Short name T2840
Test name
Test status
Simulation time 35324776 ps
CPU time 0.69 seconds
Started Aug 06 08:03:06 PM PDT 24
Finished Aug 06 08:03:07 PM PDT 24
Peak memory 207384 kb
Host smart-9aad9e0a-0dc2-4af6-b820-d19b94cf9236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1471023841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1471023841
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3585798426
Short name T2810
Test name
Test status
Simulation time 5847507988 ps
CPU time 7.8 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:03:00 PM PDT 24
Peak memory 215788 kb
Host smart-fc907c4f-9e4d-4fe6-bbcd-7ae3ee60be16
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585798426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.3585798426
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1625706758
Short name T1419
Test name
Test status
Simulation time 13363988287 ps
CPU time 15.48 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:03:07 PM PDT 24
Peak memory 215864 kb
Host smart-13aaf72f-2996-4f68-b13e-f57e7e2fc2bd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625706758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1625706758
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2834638553
Short name T1333
Test name
Test status
Simulation time 31040247965 ps
CPU time 37.07 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:03:30 PM PDT 24
Peak memory 207492 kb
Host smart-11ca1dd6-a9c3-4ba9-9d85-115705d4eab4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834638553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.2834638553
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.4047754072
Short name T1906
Test name
Test status
Simulation time 181761127 ps
CPU time 0.91 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 207292 kb
Host smart-682b1bb5-4c7f-4f4e-8c4e-28fd33d67eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40477
54072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.4047754072
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1501683970
Short name T1270
Test name
Test status
Simulation time 152702813 ps
CPU time 0.84 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:02:53 PM PDT 24
Peak memory 207272 kb
Host smart-9540f663-5d41-4f9e-af6e-20a116f38beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15016
83970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1501683970
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.2907245158
Short name T3099
Test name
Test status
Simulation time 393082798 ps
CPU time 1.58 seconds
Started Aug 06 08:02:52 PM PDT 24
Finished Aug 06 08:02:54 PM PDT 24
Peak memory 207324 kb
Host smart-41d9c81b-af18-4c49-89a2-ebc636947851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29072
45158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2907245158
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.662151993
Short name T844
Test name
Test status
Simulation time 708995671 ps
CPU time 1.9 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:56 PM PDT 24
Peak memory 207396 kb
Host smart-dea40372-f1f4-4f38-96e1-7708ff8fa676
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=662151993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.662151993
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.3451946683
Short name T1576
Test name
Test status
Simulation time 21862236887 ps
CPU time 33.85 seconds
Started Aug 06 08:02:50 PM PDT 24
Finished Aug 06 08:03:24 PM PDT 24
Peak memory 207584 kb
Host smart-bd1b1fec-005c-474f-a17a-e3a9806647d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34519
46683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.3451946683
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.2187330030
Short name T2408
Test name
Test status
Simulation time 730647580 ps
CPU time 5.08 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:02:58 PM PDT 24
Peak memory 207540 kb
Host smart-5c2db77f-8c38-4658-ad1f-b844df7c8969
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187330030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.2187330030
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.440833057
Short name T2357
Test name
Test status
Simulation time 546484671 ps
CPU time 1.6 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:56 PM PDT 24
Peak memory 207320 kb
Host smart-13c7b82e-dc69-41ac-acda-e262e4ce37b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44083
3057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.440833057
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.457544442
Short name T2425
Test name
Test status
Simulation time 145100889 ps
CPU time 0.86 seconds
Started Aug 06 08:02:57 PM PDT 24
Finished Aug 06 08:02:58 PM PDT 24
Peak memory 207348 kb
Host smart-ac39de03-8fa6-49e1-a77e-60491bc9e51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45754
4442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.457544442
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.50161389
Short name T2634
Test name
Test status
Simulation time 73239524 ps
CPU time 0.76 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 207348 kb
Host smart-c4ddd7cd-c00c-4878-99e6-34ab0be39623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50161
389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.50161389
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_types.1208050382
Short name T2138
Test name
Test status
Simulation time 349672535 ps
CPU time 1.25 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:56 PM PDT 24
Peak memory 207356 kb
Host smart-4153ecbe-4064-4c31-ba96-d0a1d8bce501
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1208050382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.1208050382
Directory /workspace/7.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.780445466
Short name T1322
Test name
Test status
Simulation time 213503577 ps
CPU time 1.54 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 207508 kb
Host smart-54192110-53ef-4906-a71a-edf975708c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78044
5466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.780445466
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.979058180
Short name T2453
Test name
Test status
Simulation time 224125533 ps
CPU time 0.96 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:56 PM PDT 24
Peak memory 207292 kb
Host smart-75a60a7c-fc06-4e4e-9cf9-e502468f787d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=979058180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.979058180
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2156198622
Short name T1351
Test name
Test status
Simulation time 154824344 ps
CPU time 0.87 seconds
Started Aug 06 08:02:55 PM PDT 24
Finished Aug 06 08:02:56 PM PDT 24
Peak memory 207340 kb
Host smart-4329cd72-1fb4-413d-9356-fe4aa86869f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21561
98622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2156198622
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.99179344
Short name T2575
Test name
Test status
Simulation time 170345025 ps
CPU time 0.92 seconds
Started Aug 06 08:02:57 PM PDT 24
Finished Aug 06 08:02:58 PM PDT 24
Peak memory 207380 kb
Host smart-5e93fe29-a8e2-4e99-bd46-d3f3563bccb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99179
344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.99179344
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.2985891096
Short name T2353
Test name
Test status
Simulation time 3783183893 ps
CPU time 37.62 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:03:31 PM PDT 24
Peak memory 223992 kb
Host smart-d7391d63-291b-475d-b77d-100bacd5b86a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2985891096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.2985891096
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.65417277
Short name T1629
Test name
Test status
Simulation time 7480182809 ps
CPU time 48.83 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:03:42 PM PDT 24
Peak memory 207584 kb
Host smart-46367d3b-e63a-4ba2-ae98-520712117123
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=65417277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.65417277
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1916982513
Short name T1916
Test name
Test status
Simulation time 179682434 ps
CPU time 0.9 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:02:54 PM PDT 24
Peak memory 207328 kb
Host smart-ebc1f695-8d8f-47c6-9766-5fac9ea6ee92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19169
82513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1916982513
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.3618759930
Short name T1502
Test name
Test status
Simulation time 28705704377 ps
CPU time 48.59 seconds
Started Aug 06 08:02:55 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 207656 kb
Host smart-2ae0f871-1a74-47dd-af8e-75b607a83e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36187
59930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3618759930
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1050126582
Short name T2108
Test name
Test status
Simulation time 11217396742 ps
CPU time 15.09 seconds
Started Aug 06 08:02:55 PM PDT 24
Finished Aug 06 08:03:10 PM PDT 24
Peak memory 207648 kb
Host smart-257ac446-ac0a-46ac-81fc-cecf3173ec49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10501
26582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1050126582
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.3231400603
Short name T2756
Test name
Test status
Simulation time 2625571097 ps
CPU time 26.28 seconds
Started Aug 06 08:02:55 PM PDT 24
Finished Aug 06 08:03:21 PM PDT 24
Peak memory 217796 kb
Host smart-79d224b4-ab9e-4d12-8224-a7af23ea2c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32314
00603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3231400603
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.1718330312
Short name T1611
Test name
Test status
Simulation time 3293359831 ps
CPU time 90.05 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:04:24 PM PDT 24
Peak memory 215860 kb
Host smart-71429418-9919-4c39-b698-48e195be2704
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1718330312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.1718330312
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2066138733
Short name T1892
Test name
Test status
Simulation time 287749396 ps
CPU time 1.08 seconds
Started Aug 06 08:02:56 PM PDT 24
Finished Aug 06 08:02:57 PM PDT 24
Peak memory 207420 kb
Host smart-55e4b98f-7bcf-442a-be80-058a12c948cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2066138733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2066138733
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2954756207
Short name T3040
Test name
Test status
Simulation time 274542975 ps
CPU time 1.08 seconds
Started Aug 06 08:02:56 PM PDT 24
Finished Aug 06 08:02:57 PM PDT 24
Peak memory 207392 kb
Host smart-6cc989a9-f882-4798-b1bd-dbbd2f064ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29547
56207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2954756207
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.2098771717
Short name T1687
Test name
Test status
Simulation time 2235167142 ps
CPU time 20.9 seconds
Started Aug 06 08:02:55 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 224052 kb
Host smart-ee609897-3e4c-48be-bb7e-90c8eaa0f2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20987
71717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.2098771717
Directory /workspace/7.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.295051516
Short name T3052
Test name
Test status
Simulation time 2893132618 ps
CPU time 32.25 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:03:25 PM PDT 24
Peak memory 223884 kb
Host smart-7fbe3247-5e70-40b6-bc3a-ad1402678ead
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=295051516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.295051516
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.3284391341
Short name T1649
Test name
Test status
Simulation time 2738227535 ps
CPU time 21.04 seconds
Started Aug 06 08:02:56 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207728 kb
Host smart-30a04de1-9a84-4abc-8b23-f599573d26fe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3284391341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3284391341
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.3145696189
Short name T1847
Test name
Test status
Simulation time 206212616 ps
CPU time 0.89 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:56 PM PDT 24
Peak memory 207392 kb
Host smart-45e6cbc4-ddbf-4164-931a-eb5b9c4abac1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3145696189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.3145696189
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3101145796
Short name T1362
Test name
Test status
Simulation time 154353068 ps
CPU time 0.88 seconds
Started Aug 06 08:02:59 PM PDT 24
Finished Aug 06 08:03:00 PM PDT 24
Peak memory 207372 kb
Host smart-837214b3-81bd-458e-b210-bdc6f8d46553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31011
45796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3101145796
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3507531283
Short name T145
Test name
Test status
Simulation time 194232060 ps
CPU time 0.99 seconds
Started Aug 06 08:02:59 PM PDT 24
Finished Aug 06 08:03:00 PM PDT 24
Peak memory 207368 kb
Host smart-874539af-3016-4b46-b4da-ea62bb74ce6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35075
31283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3507531283
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1707992436
Short name T1549
Test name
Test status
Simulation time 160329978 ps
CPU time 0.83 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:02:54 PM PDT 24
Peak memory 207332 kb
Host smart-2639e4ba-8141-42c3-a003-d8506130ba17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17079
92436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1707992436
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.578595997
Short name T579
Test name
Test status
Simulation time 200073444 ps
CPU time 0.93 seconds
Started Aug 06 08:02:58 PM PDT 24
Finished Aug 06 08:02:59 PM PDT 24
Peak memory 207372 kb
Host smart-afe20d3a-6b7b-4625-a48c-5f836e03fe24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57859
5997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.578595997
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1784410630
Short name T880
Test name
Test status
Simulation time 179020292 ps
CPU time 0.93 seconds
Started Aug 06 08:02:55 PM PDT 24
Finished Aug 06 08:02:56 PM PDT 24
Peak memory 207320 kb
Host smart-db6603bf-9b60-48a9-9125-b07b427477fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17844
10630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1784410630
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.479253061
Short name T3026
Test name
Test status
Simulation time 154483822 ps
CPU time 0.84 seconds
Started Aug 06 08:02:55 PM PDT 24
Finished Aug 06 08:02:56 PM PDT 24
Peak memory 207320 kb
Host smart-7911b21b-14df-4719-9a56-6a3f5743590e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47925
3061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.479253061
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.3170473910
Short name T2394
Test name
Test status
Simulation time 246227100 ps
CPU time 1.04 seconds
Started Aug 06 08:02:58 PM PDT 24
Finished Aug 06 08:02:59 PM PDT 24
Peak memory 207376 kb
Host smart-08eda51c-da2c-442a-99c2-da3daa46f046
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3170473910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.3170473910
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2791289397
Short name T775
Test name
Test status
Simulation time 145474188 ps
CPU time 0.83 seconds
Started Aug 06 08:02:55 PM PDT 24
Finished Aug 06 08:02:56 PM PDT 24
Peak memory 207368 kb
Host smart-9dfe56c7-ff74-4d88-9bf0-1d3ce9184825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27912
89397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2791289397
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3406844896
Short name T1557
Test name
Test status
Simulation time 106259791 ps
CPU time 0.76 seconds
Started Aug 06 08:02:59 PM PDT 24
Finished Aug 06 08:03:00 PM PDT 24
Peak memory 207332 kb
Host smart-019f1acf-29e6-4784-97e4-41829c985bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34068
44896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3406844896
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1617493476
Short name T282
Test name
Test status
Simulation time 21089378458 ps
CPU time 52.07 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:03:46 PM PDT 24
Peak memory 215932 kb
Host smart-ad7c1765-b9c4-4206-ad0c-628624b15b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16174
93476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1617493476
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2101675163
Short name T1275
Test name
Test status
Simulation time 222637827 ps
CPU time 0.97 seconds
Started Aug 06 08:02:53 PM PDT 24
Finished Aug 06 08:02:54 PM PDT 24
Peak memory 207304 kb
Host smart-96ca478b-f8b5-405b-acfb-f2fea9da959f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21016
75163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2101675163
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2579457112
Short name T2444
Test name
Test status
Simulation time 243149995 ps
CPU time 1.04 seconds
Started Aug 06 08:02:54 PM PDT 24
Finished Aug 06 08:02:55 PM PDT 24
Peak memory 207344 kb
Host smart-89a1697c-d812-4d0a-8918-169e0de8655e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25794
57112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2579457112
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1153186519
Short name T2212
Test name
Test status
Simulation time 6083799205 ps
CPU time 53.73 seconds
Started Aug 06 08:03:06 PM PDT 24
Finished Aug 06 08:04:00 PM PDT 24
Peak memory 223956 kb
Host smart-b2d9d7cd-dc83-41da-a441-c5aaa5be6d62
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1153186519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1153186519
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.3240952439
Short name T2401
Test name
Test status
Simulation time 9579777428 ps
CPU time 47.38 seconds
Started Aug 06 08:03:06 PM PDT 24
Finished Aug 06 08:03:53 PM PDT 24
Peak memory 224036 kb
Host smart-d7c51c6c-0c73-4961-b6a0-95aa8d2a2cef
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240952439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.3240952439
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.977665253
Short name T2966
Test name
Test status
Simulation time 216364754 ps
CPU time 0.95 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207364 kb
Host smart-56f4966c-e3b5-4a84-8715-1f9472adbbb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97766
5253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.977665253
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1507869019
Short name T1376
Test name
Test status
Simulation time 165737486 ps
CPU time 0.89 seconds
Started Aug 06 08:03:06 PM PDT 24
Finished Aug 06 08:03:07 PM PDT 24
Peak memory 207336 kb
Host smart-6425ee37-cdc0-4461-92ab-6a49c4d23fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15078
69019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1507869019
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_resume_link_active.4143433374
Short name T2250
Test name
Test status
Simulation time 20177089825 ps
CPU time 23.12 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:30 PM PDT 24
Peak memory 207480 kb
Host smart-571f49e6-b44f-4c90-b4aa-266a280f8fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41434
33374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.4143433374
Directory /workspace/7.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2600331162
Short name T1123
Test name
Test status
Simulation time 163306694 ps
CPU time 0.89 seconds
Started Aug 06 08:03:02 PM PDT 24
Finished Aug 06 08:03:03 PM PDT 24
Peak memory 207364 kb
Host smart-8a1110dd-4be0-4313-983d-0576477f7755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26003
31162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2600331162
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_rx_full.3377049110
Short name T2128
Test name
Test status
Simulation time 401779801 ps
CPU time 1.36 seconds
Started Aug 06 08:03:03 PM PDT 24
Finished Aug 06 08:03:04 PM PDT 24
Peak memory 207400 kb
Host smart-c7bab718-63bf-4fc4-9ffd-0aee1e43bc0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33770
49110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.3377049110
Directory /workspace/7.usbdev_rx_full/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.646871400
Short name T688
Test name
Test status
Simulation time 151548767 ps
CPU time 0.83 seconds
Started Aug 06 08:03:03 PM PDT 24
Finished Aug 06 08:03:04 PM PDT 24
Peak memory 207380 kb
Host smart-63ca10bd-660d-48b7-b2e1-0213cc481982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64687
1400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.646871400
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.528994198
Short name T774
Test name
Test status
Simulation time 187894999 ps
CPU time 0.88 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:08 PM PDT 24
Peak memory 207356 kb
Host smart-7af0086d-89a4-4484-bd64-3c14a3a395e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52899
4198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.528994198
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.662635742
Short name T1449
Test name
Test status
Simulation time 210080214 ps
CPU time 0.98 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:08 PM PDT 24
Peak memory 207384 kb
Host smart-df8a1e8c-475e-47f6-a840-0c52d8e39044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66263
5742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.662635742
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.1096489090
Short name T1093
Test name
Test status
Simulation time 1677751962 ps
CPU time 14.8 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:26 PM PDT 24
Peak memory 223936 kb
Host smart-ff7c0c26-ec92-4ccf-ad29-669ecaf4d77d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1096489090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.1096489090
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.956544896
Short name T1767
Test name
Test status
Simulation time 184490095 ps
CPU time 0.86 seconds
Started Aug 06 08:03:09 PM PDT 24
Finished Aug 06 08:03:10 PM PDT 24
Peak memory 207348 kb
Host smart-4190c639-3e81-418d-87d3-2bf31419a708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95654
4896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.956544896
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2680132535
Short name T3120
Test name
Test status
Simulation time 188248148 ps
CPU time 0.92 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:08 PM PDT 24
Peak memory 207392 kb
Host smart-a799b621-cfa0-44b9-a550-ad5bbbf97357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26801
32535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2680132535
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.148849802
Short name T3
Test name
Test status
Simulation time 510942719 ps
CPU time 1.55 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:09 PM PDT 24
Peak memory 207320 kb
Host smart-1f33bdde-f1c8-4d05-b755-2b0fe929340d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14884
9802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.148849802
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.710527205
Short name T805
Test name
Test status
Simulation time 1808049133 ps
CPU time 51.63 seconds
Started Aug 06 08:03:09 PM PDT 24
Finished Aug 06 08:04:01 PM PDT 24
Peak memory 215708 kb
Host smart-8102593b-ba63-46d4-bece-75ca7290ab90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71052
7205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.710527205
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.977152248
Short name T649
Test name
Test status
Simulation time 3885157940 ps
CPU time 34.48 seconds
Started Aug 06 08:02:51 PM PDT 24
Finished Aug 06 08:03:26 PM PDT 24
Peak memory 207704 kb
Host smart-8e1231e9-2f17-495a-b059-75129eae8861
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977152248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host_
handshake.977152248
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/70.usbdev_endpoint_types.1782354690
Short name T1228
Test name
Test status
Simulation time 267823162 ps
CPU time 1.06 seconds
Started Aug 06 08:09:14 PM PDT 24
Finished Aug 06 08:09:15 PM PDT 24
Peak memory 207404 kb
Host smart-57524db0-50d5-4577-b9a1-8c0bc45fb4ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1782354690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.1782354690
Directory /workspace/70.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/71.usbdev_endpoint_types.1398887831
Short name T2166
Test name
Test status
Simulation time 273660111 ps
CPU time 1.07 seconds
Started Aug 06 08:09:10 PM PDT 24
Finished Aug 06 08:09:11 PM PDT 24
Peak memory 207320 kb
Host smart-1aeab7ba-dd84-4e1d-967f-8c8e57947e9c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1398887831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.1398887831
Directory /workspace/71.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/72.usbdev_endpoint_types.2920202862
Short name T2337
Test name
Test status
Simulation time 155140643 ps
CPU time 0.95 seconds
Started Aug 06 08:08:58 PM PDT 24
Finished Aug 06 08:09:00 PM PDT 24
Peak memory 207328 kb
Host smart-7c12c16e-10f9-4c96-ac5a-99d3d4462e7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2920202862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.2920202862
Directory /workspace/72.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/73.usbdev_endpoint_types.4042473537
Short name T346
Test name
Test status
Simulation time 275352056 ps
CPU time 1.05 seconds
Started Aug 06 08:09:05 PM PDT 24
Finished Aug 06 08:09:07 PM PDT 24
Peak memory 207424 kb
Host smart-e739a005-62fd-4f74-84f6-868d3531dd05
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4042473537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.4042473537
Directory /workspace/73.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/77.usbdev_endpoint_types.2650101741
Short name T445
Test name
Test status
Simulation time 259753001 ps
CPU time 0.96 seconds
Started Aug 06 08:09:08 PM PDT 24
Finished Aug 06 08:09:09 PM PDT 24
Peak memory 207320 kb
Host smart-6384950e-5126-4178-8e57-9a9fb77089e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2650101741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.2650101741
Directory /workspace/77.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/78.usbdev_endpoint_types.2203347184
Short name T456
Test name
Test status
Simulation time 402368521 ps
CPU time 1.18 seconds
Started Aug 06 08:09:09 PM PDT 24
Finished Aug 06 08:09:10 PM PDT 24
Peak memory 207344 kb
Host smart-e166190f-60fc-4975-8306-b5a52b8e128a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2203347184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.2203347184
Directory /workspace/78.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/79.usbdev_endpoint_types.3806567142
Short name T418
Test name
Test status
Simulation time 527730331 ps
CPU time 1.37 seconds
Started Aug 06 08:09:12 PM PDT 24
Finished Aug 06 08:09:14 PM PDT 24
Peak memory 207328 kb
Host smart-63c513d0-fcd2-483a-9523-bc0f61174265
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3806567142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.3806567142
Directory /workspace/79.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.3329251439
Short name T2782
Test name
Test status
Simulation time 70865354 ps
CPU time 0.71 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:08 PM PDT 24
Peak memory 207472 kb
Host smart-3723df12-61fe-411c-8e33-8999ae066419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3329251439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.3329251439
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.49190543
Short name T1518
Test name
Test status
Simulation time 11239070632 ps
CPU time 13.57 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:23 PM PDT 24
Peak memory 207612 kb
Host smart-8e811583-51bc-4983-85a0-e724eadfe1e9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49190543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_
wake_disconnect.49190543
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.477578247
Short name T12
Test name
Test status
Simulation time 15448089724 ps
CPU time 18.06 seconds
Started Aug 06 08:03:04 PM PDT 24
Finished Aug 06 08:03:22 PM PDT 24
Peak memory 215776 kb
Host smart-30734585-36fe-4ab3-b54e-b0d10321cf9a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=477578247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.477578247
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3525308796
Short name T2134
Test name
Test status
Simulation time 30785605468 ps
CPU time 41.29 seconds
Started Aug 06 08:03:05 PM PDT 24
Finished Aug 06 08:03:46 PM PDT 24
Peak memory 207656 kb
Host smart-0d737cd7-8c19-4a16-8e8c-6e4c85e41bfb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525308796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.3525308796
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3052389643
Short name T1755
Test name
Test status
Simulation time 186723145 ps
CPU time 0.87 seconds
Started Aug 06 08:03:03 PM PDT 24
Finished Aug 06 08:03:04 PM PDT 24
Peak memory 207596 kb
Host smart-2420f7c4-708d-4e4c-900a-7a4a49bee145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30523
89643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3052389643
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3831197168
Short name T892
Test name
Test status
Simulation time 146866944 ps
CPU time 0.85 seconds
Started Aug 06 08:03:09 PM PDT 24
Finished Aug 06 08:03:10 PM PDT 24
Peak memory 207244 kb
Host smart-267dcd68-2e42-4fa2-b682-dc7a3f135544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38311
97168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3831197168
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3433046347
Short name T1196
Test name
Test status
Simulation time 382419668 ps
CPU time 1.33 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:12 PM PDT 24
Peak memory 207380 kb
Host smart-d64043bb-532e-45e8-a22b-947d733ccc05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34330
46347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3433046347
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.429126653
Short name T22
Test name
Test status
Simulation time 523597205 ps
CPU time 1.49 seconds
Started Aug 06 08:03:05 PM PDT 24
Finished Aug 06 08:03:07 PM PDT 24
Peak memory 207376 kb
Host smart-fbf78271-371f-4b02-bfe5-100261c4b41e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=429126653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.429126653
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.37575219
Short name T1304
Test name
Test status
Simulation time 18422463960 ps
CPU time 25.6 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:36 PM PDT 24
Peak memory 207628 kb
Host smart-6605bf01-304d-4873-896a-2106a8ed1a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37575
219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.37575219
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.1589503228
Short name T1293
Test name
Test status
Simulation time 3390609132 ps
CPU time 31.31 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:38 PM PDT 24
Peak memory 207660 kb
Host smart-4644ccf3-d7c7-44bf-9986-e2212bbd1ceb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589503228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.1589503228
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.3083426418
Short name T864
Test name
Test status
Simulation time 633262761 ps
CPU time 1.62 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207396 kb
Host smart-df612ced-e38b-455c-a5f4-1621386d4e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30834
26418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.3083426418
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2840530441
Short name T2735
Test name
Test status
Simulation time 140659539 ps
CPU time 0.85 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:12 PM PDT 24
Peak memory 207368 kb
Host smart-d4a897ce-89ed-4eb6-9d22-80e771a7482c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28405
30441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2840530441
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3915325075
Short name T2068
Test name
Test status
Simulation time 30234236 ps
CPU time 0.69 seconds
Started Aug 06 08:03:09 PM PDT 24
Finished Aug 06 08:03:10 PM PDT 24
Peak memory 207216 kb
Host smart-aa8bedbb-b0c7-417d-b7ef-101147676612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39153
25075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3915325075
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.2969237010
Short name T496
Test name
Test status
Simulation time 974316523 ps
CPU time 2.46 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:14 PM PDT 24
Peak memory 207564 kb
Host smart-b05b60f4-832c-4c5c-9896-f0d6022dc359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29692
37010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.2969237010
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_types.2954955393
Short name T430
Test name
Test status
Simulation time 736256387 ps
CPU time 1.67 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:08 PM PDT 24
Peak memory 207316 kb
Host smart-d040c74c-d552-4bdd-9503-3884225ed038
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2954955393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.2954955393
Directory /workspace/8.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.4045895316
Short name T1233
Test name
Test status
Simulation time 288584851 ps
CPU time 2.24 seconds
Started Aug 06 08:03:05 PM PDT 24
Finished Aug 06 08:03:08 PM PDT 24
Peak memory 207456 kb
Host smart-8d4a6320-c0eb-4882-8fb6-60a39321af5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40458
95316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.4045895316
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2592261500
Short name T2358
Test name
Test status
Simulation time 203387860 ps
CPU time 1.04 seconds
Started Aug 06 08:03:05 PM PDT 24
Finished Aug 06 08:03:07 PM PDT 24
Peak memory 215680 kb
Host smart-a6fe87d9-bcb0-4171-b601-89d74d2cd981
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2592261500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2592261500
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1053107806
Short name T1860
Test name
Test status
Simulation time 159637779 ps
CPU time 0.85 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207344 kb
Host smart-c97389a0-c423-4d27-8634-f15ed355a458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10531
07806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1053107806
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.4227003076
Short name T2613
Test name
Test status
Simulation time 240849178 ps
CPU time 0.96 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:12 PM PDT 24
Peak memory 207360 kb
Host smart-b86b3771-639a-4968-9358-446dd17690b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42270
03076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.4227003076
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.767416828
Short name T2091
Test name
Test status
Simulation time 3284469916 ps
CPU time 98.26 seconds
Started Aug 06 08:03:04 PM PDT 24
Finished Aug 06 08:04:42 PM PDT 24
Peak memory 217660 kb
Host smart-008f6bb8-8a93-4ac2-b2c7-7a5718b30445
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=767416828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.767416828
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.3671206060
Short name T1526
Test name
Test status
Simulation time 9650897377 ps
CPU time 117.88 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:05:09 PM PDT 24
Peak memory 207692 kb
Host smart-bf21aad4-0d68-499c-b7e7-060c4089b668
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3671206060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.3671206060
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1461896830
Short name T874
Test name
Test status
Simulation time 198999301 ps
CPU time 1.02 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:08 PM PDT 24
Peak memory 207312 kb
Host smart-29233d7f-b8a9-4c00-a93a-7099d59c90d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14618
96830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1461896830
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.3441593082
Short name T808
Test name
Test status
Simulation time 32602277619 ps
CPU time 52.55 seconds
Started Aug 06 08:03:05 PM PDT 24
Finished Aug 06 08:03:57 PM PDT 24
Peak memory 207656 kb
Host smart-f23fb88b-1d4f-4d63-96ce-a8a49a436be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34415
93082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3441593082
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1632415816
Short name T741
Test name
Test status
Simulation time 9540064995 ps
CPU time 12.14 seconds
Started Aug 06 08:03:09 PM PDT 24
Finished Aug 06 08:03:22 PM PDT 24
Peak memory 207664 kb
Host smart-fc4a172b-3a16-4c3b-92ea-34ceb29bfb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16324
15816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1632415816
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3289820666
Short name T2398
Test name
Test status
Simulation time 2822092391 ps
CPU time 21.63 seconds
Started Aug 06 08:03:06 PM PDT 24
Finished Aug 06 08:03:28 PM PDT 24
Peak memory 223956 kb
Host smart-3d24c6eb-bd82-4a46-86a2-78740673c1ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32898
20666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3289820666
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.129928041
Short name T2590
Test name
Test status
Simulation time 1639160430 ps
CPU time 16.14 seconds
Started Aug 06 08:03:06 PM PDT 24
Finished Aug 06 08:03:22 PM PDT 24
Peak memory 217048 kb
Host smart-f0aec0fd-433f-4d88-9ddc-530a6085c29a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=129928041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.129928041
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.4228105124
Short name T1718
Test name
Test status
Simulation time 276978726 ps
CPU time 1.06 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207356 kb
Host smart-14134b08-af79-44b4-9208-dcd5ef7630c2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4228105124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.4228105124
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1945399712
Short name T562
Test name
Test status
Simulation time 184233496 ps
CPU time 0.94 seconds
Started Aug 06 08:03:09 PM PDT 24
Finished Aug 06 08:03:10 PM PDT 24
Peak memory 207316 kb
Host smart-b7f37d89-7b72-47b6-804d-d4d115c003b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453
99712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1945399712
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.1423474798
Short name T1056
Test name
Test status
Simulation time 2231237047 ps
CPU time 21.67 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:38 PM PDT 24
Peak memory 224024 kb
Host smart-0437217e-348b-421a-b5fa-f3dfaefca371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14234
74798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.1423474798
Directory /workspace/8.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.3294132607
Short name T2479
Test name
Test status
Simulation time 3255083664 ps
CPU time 33.07 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:50 PM PDT 24
Peak memory 217680 kb
Host smart-f0517ed6-d891-4b33-bb71-69e58d689a5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3294132607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.3294132607
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.3069918999
Short name T2862
Test name
Test status
Simulation time 3040508801 ps
CPU time 86.66 seconds
Started Aug 06 08:03:09 PM PDT 24
Finished Aug 06 08:04:36 PM PDT 24
Peak memory 217224 kb
Host smart-9984b5fa-b3ae-4d3b-bd8c-902f7fbd7951
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3069918999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.3069918999
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.2200135868
Short name T2233
Test name
Test status
Simulation time 154717950 ps
CPU time 0.86 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207352 kb
Host smart-66854e92-a835-4acf-b82f-dca7884a782b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2200135868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.2200135868
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1692248996
Short name T1089
Test name
Test status
Simulation time 202926512 ps
CPU time 0.95 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:12 PM PDT 24
Peak memory 207428 kb
Host smart-3f5d89b8-dba8-4516-a524-7f41c048a0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16922
48996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1692248996
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3423787619
Short name T161
Test name
Test status
Simulation time 203567674 ps
CPU time 0.9 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:12 PM PDT 24
Peak memory 207376 kb
Host smart-4cc249cb-45c0-4975-90a2-652d827697c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34237
87619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3423787619
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.2188441056
Short name T1358
Test name
Test status
Simulation time 187021129 ps
CPU time 0.87 seconds
Started Aug 06 08:03:04 PM PDT 24
Finished Aug 06 08:03:05 PM PDT 24
Peak memory 207364 kb
Host smart-b9713e89-7b09-4752-b576-e73a07911c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21884
41056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2188441056
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.164661003
Short name T138
Test name
Test status
Simulation time 194791310 ps
CPU time 0.86 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207448 kb
Host smart-579c499f-051d-4b66-882e-530d3a0c5930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16466
1003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.164661003
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.27451180
Short name T2721
Test name
Test status
Simulation time 200070730 ps
CPU time 0.91 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207356 kb
Host smart-7e4afb59-2088-4373-99d5-5d8d8483ead8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27451
180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.27451180
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1411846458
Short name T2972
Test name
Test status
Simulation time 149084487 ps
CPU time 0.86 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207424 kb
Host smart-119e503c-75fd-4c95-aafe-bd09ef932af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14118
46458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1411846458
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.1300421780
Short name T2865
Test name
Test status
Simulation time 270062933 ps
CPU time 1.16 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:12 PM PDT 24
Peak memory 207440 kb
Host smart-292862c9-5b33-436a-95fc-4495f8543f7f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1300421780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.1300421780
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2641464718
Short name T2814
Test name
Test status
Simulation time 159743711 ps
CPU time 0.9 seconds
Started Aug 06 08:03:08 PM PDT 24
Finished Aug 06 08:03:09 PM PDT 24
Peak memory 207284 kb
Host smart-edaf7c8f-113e-4567-b0ed-068557dd9987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26414
64718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2641464718
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2685793088
Short name T1348
Test name
Test status
Simulation time 51212252 ps
CPU time 0.74 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:12 PM PDT 24
Peak memory 207368 kb
Host smart-5f74baa1-476b-42ac-b2d1-78e41a45c257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26857
93088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2685793088
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.661463192
Short name T308
Test name
Test status
Simulation time 15153773196 ps
CPU time 38.68 seconds
Started Aug 06 08:03:09 PM PDT 24
Finished Aug 06 08:03:48 PM PDT 24
Peak memory 215888 kb
Host smart-c78dedb5-8c4a-4204-9c90-7ea07d958731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66146
3192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.661463192
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.792840737
Short name T1354
Test name
Test status
Simulation time 199675074 ps
CPU time 0.9 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:12 PM PDT 24
Peak memory 207396 kb
Host smart-6d8bb8dc-6489-44a7-b64c-6ec0fca9daed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79284
0737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.792840737
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1534637808
Short name T1542
Test name
Test status
Simulation time 240056956 ps
CPU time 1 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207420 kb
Host smart-88a400fe-7c4b-448e-a00d-16ff467ef9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15346
37808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1534637808
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.230594241
Short name T2439
Test name
Test status
Simulation time 9092066803 ps
CPU time 171.35 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:06:01 PM PDT 24
Peak memory 218604 kb
Host smart-3db6fb74-4200-48d2-bbd9-36b37210ac6d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=230594241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.230594241
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.230709054
Short name T3027
Test name
Test status
Simulation time 2557359071 ps
CPU time 21.78 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:38 PM PDT 24
Peak memory 218004 kb
Host smart-25de13a5-ea48-46b3-9e33-5732ca7263e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=230709054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.230709054
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.510163635
Short name T180
Test name
Test status
Simulation time 9173153792 ps
CPU time 57.33 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:04:14 PM PDT 24
Peak memory 224024 kb
Host smart-da9f2656-eae6-4ee4-a866-f74f6c25282b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=510163635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.510163635
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.4050390896
Short name T1302
Test name
Test status
Simulation time 225550658 ps
CPU time 0.96 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:08 PM PDT 24
Peak memory 207252 kb
Host smart-55896d2e-175d-4fcc-9d2b-40c640adba21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40503
90896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.4050390896
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.1104504776
Short name T1227
Test name
Test status
Simulation time 158414824 ps
CPU time 0.9 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:12 PM PDT 24
Peak memory 207396 kb
Host smart-e03d27ce-1cb7-444e-a5d5-066a9e1a68c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11045
04776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.1104504776
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_resume_link_active.795786648
Short name T1722
Test name
Test status
Simulation time 20172159372 ps
CPU time 26.45 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 207440 kb
Host smart-f6d0d015-de3b-4346-8b96-9f96095fd2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79578
6648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.795786648
Directory /workspace/8.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1225696183
Short name T1492
Test name
Test status
Simulation time 145062969 ps
CPU time 0.88 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207412 kb
Host smart-3cd2a945-4e20-48a4-a546-0aaa4750205e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12256
96183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1225696183
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_rx_full.3154176929
Short name T2874
Test name
Test status
Simulation time 263319138 ps
CPU time 1.1 seconds
Started Aug 06 08:03:04 PM PDT 24
Finished Aug 06 08:03:05 PM PDT 24
Peak memory 207356 kb
Host smart-39c70574-3f6a-4276-83d3-c0f9d054b730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31541
76929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.3154176929
Directory /workspace/8.usbdev_rx_full/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1130376481
Short name T3024
Test name
Test status
Simulation time 144138851 ps
CPU time 0.83 seconds
Started Aug 06 08:03:04 PM PDT 24
Finished Aug 06 08:03:05 PM PDT 24
Peak memory 207364 kb
Host smart-7b9d0b5f-9434-4ab3-ad7b-5b837b140c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11303
76481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1130376481
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2468163161
Short name T1961
Test name
Test status
Simulation time 168767734 ps
CPU time 0.93 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207360 kb
Host smart-feaeffed-724c-4f5d-a55b-6bb5d259fab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24681
63161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2468163161
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2137630959
Short name T2382
Test name
Test status
Simulation time 247674206 ps
CPU time 1.01 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207440 kb
Host smart-5df849cc-19b6-4080-8785-c10511dee34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21376
30959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2137630959
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.516193165
Short name T1176
Test name
Test status
Simulation time 1964910469 ps
CPU time 19.46 seconds
Started Aug 06 08:03:04 PM PDT 24
Finished Aug 06 08:03:24 PM PDT 24
Peak memory 223884 kb
Host smart-c7bfb623-22fb-4075-89d4-185edd085961
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=516193165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.516193165
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.127763477
Short name T807
Test name
Test status
Simulation time 190413047 ps
CPU time 0.97 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 207312 kb
Host smart-472ab4b2-c348-45cf-ac32-edbbbadcaae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12776
3477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.127763477
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3228877463
Short name T3077
Test name
Test status
Simulation time 197670907 ps
CPU time 0.9 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 207308 kb
Host smart-811fcd4d-44e2-4cf3-8fd7-2f72a1a4c948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32288
77463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3228877463
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.3350964739
Short name T1218
Test name
Test status
Simulation time 200998233 ps
CPU time 0.94 seconds
Started Aug 06 08:03:14 PM PDT 24
Finished Aug 06 08:03:15 PM PDT 24
Peak memory 207276 kb
Host smart-8afcfa1d-794a-4886-989c-0736b8b585ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33509
64739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.3350964739
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2062297796
Short name T1705
Test name
Test status
Simulation time 3344174771 ps
CPU time 100.77 seconds
Started Aug 06 08:03:04 PM PDT 24
Finished Aug 06 08:04:45 PM PDT 24
Peak memory 217500 kb
Host smart-d3e1f59d-9b7a-450f-8edf-c7b7dc3397e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20622
97796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2062297796
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.2581134176
Short name T2473
Test name
Test status
Simulation time 1979910865 ps
CPU time 18.01 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:25 PM PDT 24
Peak memory 207544 kb
Host smart-7f7d2339-6917-44b9-809e-c24763292114
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581134176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.2581134176
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/80.usbdev_endpoint_types.3062439747
Short name T467
Test name
Test status
Simulation time 161638902 ps
CPU time 0.88 seconds
Started Aug 06 08:08:55 PM PDT 24
Finished Aug 06 08:08:56 PM PDT 24
Peak memory 207272 kb
Host smart-74dea94a-d341-454e-b9ca-f94fc703f80b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3062439747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.3062439747
Directory /workspace/80.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/81.usbdev_endpoint_types.2823587166
Short name T435
Test name
Test status
Simulation time 477356223 ps
CPU time 1.45 seconds
Started Aug 06 08:09:12 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207424 kb
Host smart-5674935f-9a6c-4b40-a8b4-1321c89eaab3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2823587166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.2823587166
Directory /workspace/81.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/82.usbdev_endpoint_types.229955007
Short name T330
Test name
Test status
Simulation time 513798853 ps
CPU time 1.48 seconds
Started Aug 06 08:09:05 PM PDT 24
Finished Aug 06 08:09:07 PM PDT 24
Peak memory 207236 kb
Host smart-c9eec06e-08b9-4474-9b91-767b5471183d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=229955007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.229955007
Directory /workspace/82.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/83.usbdev_endpoint_types.1422546576
Short name T136
Test name
Test status
Simulation time 262524719 ps
CPU time 1 seconds
Started Aug 06 08:09:12 PM PDT 24
Finished Aug 06 08:09:13 PM PDT 24
Peak memory 207296 kb
Host smart-9181580f-c3a2-4299-bf34-b6020a1f1e77
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1422546576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.1422546576
Directory /workspace/83.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/85.usbdev_endpoint_types.1917251505
Short name T2331
Test name
Test status
Simulation time 539561156 ps
CPU time 1.39 seconds
Started Aug 06 08:09:08 PM PDT 24
Finished Aug 06 08:09:09 PM PDT 24
Peak memory 207288 kb
Host smart-c09e6d38-9467-4097-bec8-40e7871968f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1917251505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.1917251505
Directory /workspace/85.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/86.usbdev_endpoint_types.3752411680
Short name T242
Test name
Test status
Simulation time 764796317 ps
CPU time 1.88 seconds
Started Aug 06 08:08:58 PM PDT 24
Finished Aug 06 08:09:00 PM PDT 24
Peak memory 207372 kb
Host smart-388d2576-cf7c-4d02-be71-e3e14f79937a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3752411680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.3752411680
Directory /workspace/86.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/87.usbdev_endpoint_types.2837480363
Short name T395
Test name
Test status
Simulation time 384686581 ps
CPU time 1.18 seconds
Started Aug 06 08:09:09 PM PDT 24
Finished Aug 06 08:09:11 PM PDT 24
Peak memory 207404 kb
Host smart-a2e0d0b2-50c5-42b1-9352-95df62193bbd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2837480363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.2837480363
Directory /workspace/87.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/88.usbdev_endpoint_types.2706321200
Short name T2824
Test name
Test status
Simulation time 502085681 ps
CPU time 1.33 seconds
Started Aug 06 08:09:14 PM PDT 24
Finished Aug 06 08:09:16 PM PDT 24
Peak memory 207324 kb
Host smart-23a27333-e422-4052-9b79-21c722d96d40
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2706321200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.2706321200
Directory /workspace/88.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/89.usbdev_endpoint_types.940437868
Short name T580
Test name
Test status
Simulation time 169683141 ps
CPU time 0.99 seconds
Started Aug 06 08:09:07 PM PDT 24
Finished Aug 06 08:09:08 PM PDT 24
Peak memory 207348 kb
Host smart-75b97671-2606-4baa-ab65-3d3ad490f8ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=940437868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.940437868
Directory /workspace/89.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.2979527242
Short name T2087
Test name
Test status
Simulation time 35834852 ps
CPU time 0.66 seconds
Started Aug 06 08:03:22 PM PDT 24
Finished Aug 06 08:03:23 PM PDT 24
Peak memory 207432 kb
Host smart-8814b271-611a-4531-88ea-fe8d93bc2212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2979527242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.2979527242
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1849075252
Short name T1707
Test name
Test status
Simulation time 5736805381 ps
CPU time 7.66 seconds
Started Aug 06 08:03:09 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 215828 kb
Host smart-36470cc7-9271-4de1-952e-0f23fe03c47d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849075252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.1849075252
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.2094762451
Short name T2974
Test name
Test status
Simulation time 15096920381 ps
CPU time 18.16 seconds
Started Aug 06 08:03:08 PM PDT 24
Finished Aug 06 08:03:27 PM PDT 24
Peak memory 215864 kb
Host smart-26cea128-5033-404c-acdc-135e576a02ae
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094762451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.2094762451
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1746548289
Short name T217
Test name
Test status
Simulation time 23861322286 ps
CPU time 32.09 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:48 PM PDT 24
Peak memory 215792 kb
Host smart-43d504c7-a7cb-45a5-9364-67f69f5a50c5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746548289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.1746548289
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.4135052654
Short name T1853
Test name
Test status
Simulation time 195745431 ps
CPU time 0.91 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207312 kb
Host smart-cec09b3c-8815-4d9c-93ae-3978e2df7d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41350
52654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.4135052654
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1553118706
Short name T673
Test name
Test status
Simulation time 172298469 ps
CPU time 0.9 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207320 kb
Host smart-21b62b25-044e-43c2-a699-871e207eb608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15531
18706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1553118706
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.831333509
Short name T2827
Test name
Test status
Simulation time 505168206 ps
CPU time 1.72 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207316 kb
Host smart-502106ec-69a9-4a71-93a0-2db411d662a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83133
3509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.831333509
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1181031004
Short name T2120
Test name
Test status
Simulation time 340890620 ps
CPU time 1.17 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207380 kb
Host smart-3a364d6d-5ef9-48ec-861b-9b0102e75306
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1181031004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1181031004
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.3771857836
Short name T2188
Test name
Test status
Simulation time 25973246239 ps
CPU time 40.68 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:56 PM PDT 24
Peak memory 207572 kb
Host smart-e6e9d958-3f53-42d5-b262-a1051c47b4a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37718
57836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.3771857836
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.966693592
Short name T1044
Test name
Test status
Simulation time 862897118 ps
CPU time 19.55 seconds
Started Aug 06 08:03:06 PM PDT 24
Finished Aug 06 08:03:25 PM PDT 24
Peak memory 207536 kb
Host smart-2141d430-80d2-42d9-81bd-b66ef98f6b9e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966693592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.966693592
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.504121578
Short name T1041
Test name
Test status
Simulation time 709768063 ps
CPU time 1.64 seconds
Started Aug 06 08:03:14 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 207284 kb
Host smart-fb7b6995-dd9f-48ea-a520-005ee559f30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50412
1578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.504121578
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.195282839
Short name T2540
Test name
Test status
Simulation time 153608324 ps
CPU time 0.83 seconds
Started Aug 06 08:03:07 PM PDT 24
Finished Aug 06 08:03:08 PM PDT 24
Peak memory 207316 kb
Host smart-c70fcc4d-c418-4722-9b19-324711b76978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19528
2839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.195282839
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.118502252
Short name T1139
Test name
Test status
Simulation time 69487222 ps
CPU time 0.72 seconds
Started Aug 06 08:03:06 PM PDT 24
Finished Aug 06 08:03:07 PM PDT 24
Peak memory 207336 kb
Host smart-a83170cb-0a22-465b-b614-2f6026cfd1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11850
2252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.118502252
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2783550455
Short name T828
Test name
Test status
Simulation time 938217348 ps
CPU time 2.47 seconds
Started Aug 06 08:03:08 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 206868 kb
Host smart-7ffb894c-43c3-4824-9cf2-05f75ef8868f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27835
50455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2783550455
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.195406253
Short name T1261
Test name
Test status
Simulation time 419974351 ps
CPU time 2.65 seconds
Started Aug 06 08:03:06 PM PDT 24
Finished Aug 06 08:03:09 PM PDT 24
Peak memory 207480 kb
Host smart-2d986f29-f049-499b-8465-f1f6897b7fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19540
6253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.195406253
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1786601201
Short name T2614
Test name
Test status
Simulation time 173766983 ps
CPU time 0.94 seconds
Started Aug 06 08:03:08 PM PDT 24
Finished Aug 06 08:03:09 PM PDT 24
Peak memory 207500 kb
Host smart-501d2e5d-8f8f-46b3-96ce-4a7451bbeac9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1786601201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1786601201
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2648997884
Short name T1704
Test name
Test status
Simulation time 145565268 ps
CPU time 0.81 seconds
Started Aug 06 08:03:09 PM PDT 24
Finished Aug 06 08:03:10 PM PDT 24
Peak memory 207344 kb
Host smart-c2bc6d18-010a-4ee4-8975-4fff2f2ec16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26489
97884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2648997884
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2215027391
Short name T979
Test name
Test status
Simulation time 224354268 ps
CPU time 0.99 seconds
Started Aug 06 08:03:09 PM PDT 24
Finished Aug 06 08:03:10 PM PDT 24
Peak memory 206644 kb
Host smart-e55692fb-abbc-47ff-83f7-93fdfe8f62d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22150
27391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2215027391
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.3176722891
Short name T2202
Test name
Test status
Simulation time 2642488880 ps
CPU time 19.8 seconds
Started Aug 06 08:03:12 PM PDT 24
Finished Aug 06 08:03:32 PM PDT 24
Peak memory 223992 kb
Host smart-def3513b-1125-4d77-b385-cb29311b60ea
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3176722891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.3176722891
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.3590855780
Short name T2336
Test name
Test status
Simulation time 13398980499 ps
CPU time 169.77 seconds
Started Aug 06 08:03:08 PM PDT 24
Finished Aug 06 08:05:58 PM PDT 24
Peak memory 206984 kb
Host smart-a8e6f5aa-4b83-442c-8ed8-f60c15372c34
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3590855780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.3590855780
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3970195617
Short name T1579
Test name
Test status
Simulation time 191811206 ps
CPU time 0.95 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:11 PM PDT 24
Peak memory 207372 kb
Host smart-d6c3f8bb-6777-4070-a4fc-e50c8a8fa1ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39701
95617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3970195617
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.280272655
Short name T1155
Test name
Test status
Simulation time 25992670590 ps
CPU time 29.33 seconds
Started Aug 06 08:03:08 PM PDT 24
Finished Aug 06 08:03:37 PM PDT 24
Peak memory 215796 kb
Host smart-f7173d63-c192-4f51-a9c5-647746b70181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28027
2655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.280272655
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.293326515
Short name T1902
Test name
Test status
Simulation time 4329986017 ps
CPU time 5.94 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 215956 kb
Host smart-04325742-8b5e-4e0d-9785-64f63a7431f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29332
6515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.293326515
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.1134339506
Short name T878
Test name
Test status
Simulation time 3745983524 ps
CPU time 32.09 seconds
Started Aug 06 08:03:11 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 218444 kb
Host smart-69b01067-8ff1-4461-b9d7-280b4f324850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11343
39506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1134339506
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3264200528
Short name T929
Test name
Test status
Simulation time 2161858657 ps
CPU time 20.97 seconds
Started Aug 06 08:03:10 PM PDT 24
Finished Aug 06 08:03:31 PM PDT 24
Peak memory 215880 kb
Host smart-ae270e38-f213-4a34-88a6-ac8a94637515
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3264200528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3264200528
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3920529330
Short name T1964
Test name
Test status
Simulation time 254669239 ps
CPU time 1.04 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207332 kb
Host smart-3c5ecd76-822b-433c-ba1c-47a6baca7cb4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3920529330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3920529330
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2717734308
Short name T1186
Test name
Test status
Simulation time 248507715 ps
CPU time 1 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 207392 kb
Host smart-c3d6e4ea-f7fd-4dee-8ddb-a1b3b05f0e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27177
34308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2717734308
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.4124721096
Short name T2466
Test name
Test status
Simulation time 2844716607 ps
CPU time 21.04 seconds
Started Aug 06 08:03:22 PM PDT 24
Finished Aug 06 08:03:43 PM PDT 24
Peak memory 223988 kb
Host smart-17338a11-562d-4611-b16e-a5bb707640b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41247
21096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.4124721096
Directory /workspace/9.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3256186315
Short name T2688
Test name
Test status
Simulation time 3330331862 ps
CPU time 38.93 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:55 PM PDT 24
Peak memory 224256 kb
Host smart-cb73357d-cc48-496c-992e-4d7ea35d3395
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3256186315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3256186315
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.263897992
Short name T2494
Test name
Test status
Simulation time 3918899962 ps
CPU time 29.49 seconds
Started Aug 06 08:03:21 PM PDT 24
Finished Aug 06 08:03:51 PM PDT 24
Peak memory 215876 kb
Host smart-890f7c63-61dc-4eab-999d-f156949663d4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=263897992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.263897992
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2103037655
Short name T2216
Test name
Test status
Simulation time 163354086 ps
CPU time 0.9 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207596 kb
Host smart-569d4b45-5ddd-484f-8437-9d62e686aa10
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2103037655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2103037655
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2740217487
Short name T545
Test name
Test status
Simulation time 142067017 ps
CPU time 0.86 seconds
Started Aug 06 08:03:13 PM PDT 24
Finished Aug 06 08:03:14 PM PDT 24
Peak memory 207316 kb
Host smart-4aca2daa-3ebf-4441-8506-350140421c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27402
17487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2740217487
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2968830806
Short name T140
Test name
Test status
Simulation time 206387299 ps
CPU time 0.96 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207376 kb
Host smart-42a25ea5-475d-4b06-a60d-854a7fd00ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29688
30806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2968830806
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2304152948
Short name T724
Test name
Test status
Simulation time 210636946 ps
CPU time 0.91 seconds
Started Aug 06 08:03:21 PM PDT 24
Finished Aug 06 08:03:22 PM PDT 24
Peak memory 207320 kb
Host smart-7fc4e196-5cfc-4718-b1e0-0b876bcad984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23041
52948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2304152948
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.214961894
Short name T1638
Test name
Test status
Simulation time 148174912 ps
CPU time 0.84 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207240 kb
Host smart-d2951098-f29d-45ed-8ea0-f01850de4668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21496
1894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.214961894
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.185787715
Short name T2555
Test name
Test status
Simulation time 170717663 ps
CPU time 0.89 seconds
Started Aug 06 08:03:14 PM PDT 24
Finished Aug 06 08:03:15 PM PDT 24
Peak memory 207352 kb
Host smart-f6b4af10-232f-4272-8b7e-758ae002b75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18578
7715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.185787715
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2188963240
Short name T1190
Test name
Test status
Simulation time 189651730 ps
CPU time 0.91 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 207408 kb
Host smart-f80f7abc-6048-483d-aaee-68932c97f4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21889
63240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2188963240
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.2658852246
Short name T1070
Test name
Test status
Simulation time 219978695 ps
CPU time 1 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 207328 kb
Host smart-7dbb6a94-5732-46f2-84a4-5f2deb97065d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2658852246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2658852246
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1123157642
Short name T690
Test name
Test status
Simulation time 147124827 ps
CPU time 0.88 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 207292 kb
Host smart-73a22c9f-926a-455a-8632-7ebb25840666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11231
57642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1123157642
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3201688980
Short name T2632
Test name
Test status
Simulation time 49529887 ps
CPU time 0.7 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207344 kb
Host smart-cb70026a-aa02-47cb-a1ea-3f960a74c235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32016
88980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3201688980
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3927299529
Short name T1656
Test name
Test status
Simulation time 18452139647 ps
CPU time 46.36 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:04:02 PM PDT 24
Peak memory 220900 kb
Host smart-f3c0106e-8162-46ea-92c1-d1f71c5c319d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39272
99529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3927299529
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.247172782
Short name T877
Test name
Test status
Simulation time 186054863 ps
CPU time 0.9 seconds
Started Aug 06 08:03:14 PM PDT 24
Finished Aug 06 08:03:15 PM PDT 24
Peak memory 207392 kb
Host smart-ab052cf7-c7aa-4343-8116-ab918ee4cf56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24717
2782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.247172782
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1826676747
Short name T571
Test name
Test status
Simulation time 275691922 ps
CPU time 0.97 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207320 kb
Host smart-5ce9c1bf-8553-48c8-988c-76352a8337f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18266
76747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1826676747
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2282959624
Short name T2820
Test name
Test status
Simulation time 4376342299 ps
CPU time 34.51 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:51 PM PDT 24
Peak memory 218208 kb
Host smart-649c2c52-cb25-481a-831b-c465f86c978c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282959624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2282959624
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.2626101912
Short name T2946
Test name
Test status
Simulation time 6700500231 ps
CPU time 28.45 seconds
Started Aug 06 08:03:14 PM PDT 24
Finished Aug 06 08:03:42 PM PDT 24
Peak memory 224072 kb
Host smart-821b06c2-1f1d-4987-b26c-3977515ad1b2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626101912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.2626101912
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.1203225
Short name T1515
Test name
Test status
Simulation time 202473712 ps
CPU time 0.92 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207236 kb
Host smart-cf3dccc4-f50e-4e93-87e9-a1a55f737bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12032
25 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.1203225
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1523207771
Short name T613
Test name
Test status
Simulation time 170051801 ps
CPU time 0.89 seconds
Started Aug 06 08:03:18 PM PDT 24
Finished Aug 06 08:03:19 PM PDT 24
Peak memory 207344 kb
Host smart-b29974d9-b37a-444a-a5a5-65a4dbc9b945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15232
07771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1523207771
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_resume_link_active.3284201832
Short name T1903
Test name
Test status
Simulation time 20164699021 ps
CPU time 31.68 seconds
Started Aug 06 08:03:14 PM PDT 24
Finished Aug 06 08:03:46 PM PDT 24
Peak memory 207432 kb
Host smart-7e2b8700-1ab8-4bd8-98a2-45943faa7250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32842
01832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.3284201832
Directory /workspace/9.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3488247217
Short name T1154
Test name
Test status
Simulation time 154023424 ps
CPU time 0.84 seconds
Started Aug 06 08:03:18 PM PDT 24
Finished Aug 06 08:03:19 PM PDT 24
Peak memory 207364 kb
Host smart-350294e5-6d3e-4d4e-bf80-ddd541e79d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34882
47217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3488247217
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_rx_full.3853018730
Short name T1878
Test name
Test status
Simulation time 301840626 ps
CPU time 1.13 seconds
Started Aug 06 08:03:31 PM PDT 24
Finished Aug 06 08:03:32 PM PDT 24
Peak memory 207324 kb
Host smart-315e4f55-05dc-4839-acaa-9542ff18025b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38530
18730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.3853018730
Directory /workspace/9.usbdev_rx_full/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2752703280
Short name T1133
Test name
Test status
Simulation time 156457851 ps
CPU time 0.84 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 207348 kb
Host smart-5f54bb2a-7083-40f2-8ab2-3ac3173512ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27527
03280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2752703280
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1460073615
Short name T2804
Test name
Test status
Simulation time 149008030 ps
CPU time 0.84 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:16 PM PDT 24
Peak memory 207400 kb
Host smart-423387cc-91fb-444b-8a40-d9d864109e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14600
73615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1460073615
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1480108475
Short name T2472
Test name
Test status
Simulation time 236768724 ps
CPU time 1.05 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:17 PM PDT 24
Peak memory 207364 kb
Host smart-769a6a77-bb30-41bb-acf0-496478f8ac1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14801
08475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1480108475
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.3391017313
Short name T1454
Test name
Test status
Simulation time 2740669772 ps
CPU time 22.12 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:38 PM PDT 24
Peak memory 215816 kb
Host smart-3053eb81-93d2-48a5-a1e5-fd29bd2804e4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3391017313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.3391017313
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1825687407
Short name T2714
Test name
Test status
Simulation time 151238679 ps
CPU time 0.86 seconds
Started Aug 06 08:03:18 PM PDT 24
Finished Aug 06 08:03:19 PM PDT 24
Peak memory 207384 kb
Host smart-9a343872-81a5-4d0a-bf08-a4fc254da5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18256
87407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1825687407
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2291370441
Short name T1052
Test name
Test status
Simulation time 171529344 ps
CPU time 0.89 seconds
Started Aug 06 08:03:17 PM PDT 24
Finished Aug 06 08:03:18 PM PDT 24
Peak memory 207364 kb
Host smart-167c08f2-6f70-4ff4-81b7-5562c4179251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22913
70441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2291370441
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.502956792
Short name T2523
Test name
Test status
Simulation time 1060146738 ps
CPU time 2.71 seconds
Started Aug 06 08:03:16 PM PDT 24
Finished Aug 06 08:03:19 PM PDT 24
Peak memory 207468 kb
Host smart-2e0f9ab5-bae9-4913-92de-042835665872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50295
6792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.502956792
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.3611521241
Short name T2908
Test name
Test status
Simulation time 3225674334 ps
CPU time 25.43 seconds
Started Aug 06 08:03:15 PM PDT 24
Finished Aug 06 08:03:41 PM PDT 24
Peak memory 217060 kb
Host smart-54f574b8-c8a7-4c41-8db7-4073d34925f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36115
21241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.3611521241
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.677354539
Short name T2003
Test name
Test status
Simulation time 3872159421 ps
CPU time 34.41 seconds
Started Aug 06 08:03:06 PM PDT 24
Finished Aug 06 08:03:41 PM PDT 24
Peak memory 207524 kb
Host smart-4ae9a82a-fdf6-4b10-8326-32db6c406776
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677354539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host_
handshake.677354539
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/90.usbdev_endpoint_types.490774167
Short name T462
Test name
Test status
Simulation time 802071810 ps
CPU time 1.83 seconds
Started Aug 06 08:09:04 PM PDT 24
Finished Aug 06 08:09:06 PM PDT 24
Peak memory 207268 kb
Host smart-06cba301-5b2a-4b00-8e27-3c928157b4b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=490774167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.490774167
Directory /workspace/90.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/91.usbdev_endpoint_types.2415612937
Short name T1528
Test name
Test status
Simulation time 694026704 ps
CPU time 1.61 seconds
Started Aug 06 08:09:15 PM PDT 24
Finished Aug 06 08:09:17 PM PDT 24
Peak memory 207368 kb
Host smart-18248654-cd67-4682-9c28-8059bbbc00f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2415612937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.2415612937
Directory /workspace/91.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/92.usbdev_endpoint_types.1204228270
Short name T349
Test name
Test status
Simulation time 570156707 ps
CPU time 1.49 seconds
Started Aug 06 08:09:09 PM PDT 24
Finished Aug 06 08:09:11 PM PDT 24
Peak memory 207296 kb
Host smart-4c2109a2-a7d9-4cd7-9d09-a8046e5708b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1204228270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.1204228270
Directory /workspace/92.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/93.usbdev_endpoint_types.2240261513
Short name T2193
Test name
Test status
Simulation time 256538970 ps
CPU time 1.04 seconds
Started Aug 06 08:09:06 PM PDT 24
Finished Aug 06 08:09:07 PM PDT 24
Peak memory 207372 kb
Host smart-58ca4b23-cd64-4398-ad33-2e1e1ecfa834
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2240261513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.2240261513
Directory /workspace/93.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/94.usbdev_endpoint_types.3885188462
Short name T458
Test name
Test status
Simulation time 171858759 ps
CPU time 0.92 seconds
Started Aug 06 08:09:16 PM PDT 24
Finished Aug 06 08:09:17 PM PDT 24
Peak memory 207572 kb
Host smart-ae31430a-b51d-4027-a716-6e3c8ce822f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3885188462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.3885188462
Directory /workspace/94.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/95.usbdev_endpoint_types.1047295821
Short name T2625
Test name
Test status
Simulation time 486706617 ps
CPU time 1.43 seconds
Started Aug 06 08:09:05 PM PDT 24
Finished Aug 06 08:09:07 PM PDT 24
Peak memory 207300 kb
Host smart-afec5f48-6d98-4a4e-94aa-0b9d08ed0dc4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1047295821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.1047295821
Directory /workspace/95.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/96.usbdev_endpoint_types.3064883550
Short name T436
Test name
Test status
Simulation time 458436870 ps
CPU time 1.36 seconds
Started Aug 06 08:09:07 PM PDT 24
Finished Aug 06 08:09:09 PM PDT 24
Peak memory 207352 kb
Host smart-14b910a4-9eea-47c2-8ed4-8090462a35e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3064883550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.3064883550
Directory /workspace/96.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/97.usbdev_endpoint_types.652199968
Short name T443
Test name
Test status
Simulation time 283516657 ps
CPU time 1.07 seconds
Started Aug 06 08:09:03 PM PDT 24
Finished Aug 06 08:09:04 PM PDT 24
Peak memory 207232 kb
Host smart-708166dc-3a2f-4876-a426-c585b0f08520
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=652199968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.652199968
Directory /workspace/97.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/98.usbdev_endpoint_types.1456035536
Short name T1618
Test name
Test status
Simulation time 350233314 ps
CPU time 1.21 seconds
Started Aug 06 08:09:08 PM PDT 24
Finished Aug 06 08:09:09 PM PDT 24
Peak memory 207296 kb
Host smart-05609341-3da3-4330-a7c6-7730020363d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1456035536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.1456035536
Directory /workspace/98.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/99.usbdev_endpoint_types.2930203659
Short name T432
Test name
Test status
Simulation time 270752253 ps
CPU time 1.02 seconds
Started Aug 06 08:09:17 PM PDT 24
Finished Aug 06 08:09:18 PM PDT 24
Peak memory 207320 kb
Host smart-691328cc-dce5-4496-8df1-ff6edc32afd3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2930203659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.2930203659
Directory /workspace/99.usbdev_endpoint_types/latest
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