Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	169067	1		T1	14		T2	3		T3	2
all_values[1]	169067	1		T1	14		T2	3		T3	2
all_values[2]	169067	1		T1	14		T2	3		T3	2
all_values[3]	169067	1		T1	14		T2	3		T3	2
all_values[4]	169067	1		T1	14		T2	3		T3	2
all_values[5]	169067	1		T1	14		T2	3		T3	2
all_values[6]	169067	1		T1	14		T2	3		T3	2
all_values[7]	169067	1		T1	14		T2	3		T3	2
all_values[8]	169067	1		T1	14		T2	3		T3	2
all_values[9]	169067	1		T1	14		T2	3		T3	2
all_values[10]	169067	1		T1	14		T2	3		T3	2
all_values[11]	169067	1		T1	14		T2	3		T3	2
all_values[12]	169067	1		T1	14		T2	3		T3	2
all_values[13]	169067	1		T1	14		T2	3		T3	2
all_values[14]	169067	1		T1	14		T2	3		T3	2
all_values[15]	169067	1		T1	14		T2	3		T3	2
all_values[16]	169067	1		T1	14		T2	3		T3	2
all_values[17]	169067	1		T1	14		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5402913	1		T1	434		T2	96		T3	64
auto[1]	7231	1		T1	14		T27	3		T21	5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4638512	1		T1	369		T2	78		T3	55
auto[1]	771632	1		T1	79		T2	18		T3	9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142959	1		T1	14		T27	3		T7	3
all_values[0]	auto[0]	auto[1]	25271	1		T2	3		T3	2		T17	1
all_values[0]	auto[1]	auto[0]	725	1		T31	3		T39	3		T40	3
all_values[0]	auto[1]	auto[1]	112	1		T39	1		T41	1		T341	1
all_values[1]	auto[0]	auto[0]	166077	1		T3	2		T7	3		T17	4
all_values[1]	auto[0]	auto[1]	1588	1		T2	3		T4	2		T30	2
all_values[1]	auto[1]	auto[0]	523	1		T1	2		T27	2		T9	1
all_values[1]	auto[1]	auto[1]	879	1		T1	12		T27	1		T9	1
all_values[2]	auto[0]	auto[0]	3743	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	165076	1		T1	13		T2	2		T3	1
all_values[2]	auto[1]	auto[0]	138	1		T37	1		T60	1		T61	1
all_values[2]	auto[1]	auto[1]	110	1		T37	1		T60	1		T61	1
all_values[3]	auto[0]	auto[0]	167201	1		T1	14		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	313	1		T5	1		T30	1		T55	1
all_values[3]	auto[1]	auto[0]	1492	1		T62	1407		T224	1		T225	4
all_values[3]	auto[1]	auto[1]	61	1		T62	1		T223	1		T224	1
all_values[4]	auto[0]	auto[0]	3702	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	165189	1		T1	13		T2	2		T3	1
all_values[4]	auto[1]	auto[0]	112	1		T63	1		T223	1		T224	2
all_values[4]	auto[1]	auto[1]	64	1		T63	1		T223	3		T224	2
all_values[5]	auto[0]	auto[0]	168550	1		T1	14		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	340	1		T7	1		T8	1		T9	1
all_values[5]	auto[1]	auto[0]	111	1		T223	1		T224	4		T225	1
all_values[5]	auto[1]	auto[1]	66	1		T223	2		T225	2		T226	2
all_values[6]	auto[0]	auto[0]	168640	1		T1	14		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	238	1		T7	1		T8	1		T70	1
all_values[6]	auto[1]	auto[0]	78	1		T223	1		T225	1		T227	1
all_values[6]	auto[1]	auto[1]	111	1		T36	1		T38	1		T64	1
all_values[7]	auto[0]	auto[0]	114915	1		T7	2		T18	2		T4	2
all_values[7]	auto[0]	auto[1]	53987	1		T1	14		T2	3		T3	2
all_values[7]	auto[1]	auto[0]	101	1		T42	1		T43	1		T224	2
all_values[7]	auto[1]	auto[1]	64	1		T42	1		T43	1		T223	1
all_values[8]	auto[0]	auto[0]	168306	1		T1	14		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	64	1		T223	1		T224	1		T226	1
all_values[8]	auto[1]	auto[0]	605	1		T46	10		T47	10		T48	10
all_values[8]	auto[1]	auto[1]	92	1		T49	1		T50	1		T51	1
all_values[9]	auto[0]	auto[0]	168815	1		T1	14		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	62	1		T224	3		T225	1		T226	1
all_values[9]	auto[1]	auto[0]	119	1		T21	3		T58	3		T59	3
all_values[9]	auto[1]	auto[1]	71	1		T21	2		T58	2		T59	2
all_values[10]	auto[0]	auto[0]	168600	1		T1	14		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	293	1		T55	1		T56	1		T57	1
all_values[10]	auto[1]	auto[0]	102	1		T223	2		T224	4		T331	2
all_values[10]	auto[1]	auto[1]	72	1		T223	2		T226	1		T227	1
all_values[11]	auto[0]	auto[0]	168672	1		T1	14		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	130	1		T70	1		T71	1		T74	1
all_values[11]	auto[1]	auto[0]	153	1		T69	1		T72	1		T73	1
all_values[11]	auto[1]	auto[1]	112	1		T69	1		T72	1		T73	1
all_values[12]	auto[0]	auto[0]	168830	1		T1	14		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	72	1		T70	1		T76	1		T79	1
all_values[12]	auto[1]	auto[0]	107	1		T75	2		T77	2		T78	2
all_values[12]	auto[1]	auto[1]	58	1		T75	1		T77	1		T78	1
all_values[13]	auto[0]	auto[0]	168734	1		T1	14		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	56	1		T70	1		T76	1		T79	1
all_values[13]	auto[1]	auto[0]	149	1		T71	1		T74	1		T80	1
all_values[13]	auto[1]	auto[1]	128	1		T71	1		T74	1		T80	1
all_values[14]	auto[0]	auto[0]	32922	1		T1	14		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	135970	1		T7	2		T4	1		T5	1
all_values[14]	auto[1]	auto[0]	116	1		T223	1		T225	3		T226	1
all_values[14]	auto[1]	auto[1]	59	1		T225	3		T228	2		T332	1
all_values[15]	auto[0]	auto[0]	3761	1		T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	165144	1		T1	13		T2	2		T3	1
all_values[15]	auto[1]	auto[0]	102	1		T223	1		T224	1		T225	3
all_values[15]	auto[1]	auto[1]	60	1		T223	3		T224	1		T225	3
all_values[16]	auto[0]	auto[0]	168403	1		T1	14		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	459	1		T18	1		T29	1		T65	1
all_values[16]	auto[1]	auto[0]	122	1		T66	4		T67	4		T68	4
all_values[16]	auto[1]	auto[1]	83	1		T66	4		T67	4		T68	4
all_values[17]	auto[0]	auto[0]	113773	1		T7	2		T4	2		T20	2
all_values[17]	auto[0]	auto[1]	55120	1		T1	14		T2	3		T3	2
all_values[17]	auto[1]	auto[0]	116	1		T52	1		T53	1		T54	1
all_values[17]	auto[1]	auto[1]	58	1		T52	1		T53	1		T54	1