Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::crc5_cg

Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	6	0	6	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_crc5	3	0	3	100.00	100	1	1	0
cp_dir	2	0	2	100.00	100	1	1	2

Crosses for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_crc5_X_dir	6	0	6	100.00	100	1	1	0

Summary for Variable cp_crc5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_crc5

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	6311	1		T30	22		T121	1		T165	2
leading_zero	5875	1		T1	2		T86	41		T495	2
trailing_zero	7645	1		T1	2		T6	19		T81	2

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Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	113216	1		T1	12		T2	1		T3	1
auto[1]	58891	1		T1	12		T2	1		T27	1

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Summary for Cross cr_crc5_X_dir

Samples crossed: cp_crc5 cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	6	0	6	100.00

Automatically Generated Cross Bins for cr_crc5_X_dir

Bins

cp_crc5	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	auto[0]	4497	1		T30	9		T121	1		T165	1
all_ones	auto[1]	1814	1		T30	13		T165	1		T86	2
leading_zero	auto[0]	3786	1		T1	1		T86	33		T495	1
leading_zero	auto[1]	2089	1		T1	1		T86	8		T495	1
trailing_zero	auto[0]	5694	1		T1	1		T6	9		T81	2
trailing_zero	auto[1]	1951	1		T1	1		T6	10		T94	1