Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	113197	1		T1	12		T2	1		T3	1
auto[1]	42138	1		T1	12		T2	1		T27	1

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	28579	1		T2	2		T5	130		T6	2
max_len_m1	768	1		T30	3		T65	1		T183	8
max_len_m2	861	1		T4	2		T6	6		T30	3
max_len_m3	719	1		T30	2		T92	2		T70	5
five	1103	1		T6	4		T30	5		T44	1
four	1011	1		T6	4		T30	12		T44	1
three	724	1		T29	1		T30	5		T45	1
one	795	1		T1	2		T30	12		T166	2
zero	11063	1		T17	1		T5	15		T6	2

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24207	1		T2	1		T6	1		T28	800
max_len	auto[1]	4372	1		T2	1		T5	130		T6	1
max_len_m1	auto[0]	521	1		T30	3		T65	1		T183	4
max_len_m1	auto[1]	247	1		T183	4		T167	2		T166	2
max_len_m2	auto[0]	588	1		T4	1		T6	3		T30	3
max_len_m2	auto[1]	273	1		T4	1		T6	3		T183	2
max_len_m3	auto[0]	499	1		T30	2		T92	1		T70	3
max_len_m3	auto[1]	220	1		T92	1		T70	2		T496	2
five	auto[0]	590	1		T6	2		T30	2		T44	1
five	auto[1]	513	1		T6	2		T30	3		T183	1
four	auto[0]	518	1		T6	2		T30	8		T44	1
four	auto[1]	493	1		T6	2		T30	4		T164	1
three	auto[0]	366	1		T29	1		T30	2		T45	1
three	auto[1]	358	1		T30	3		T292	12		T220	1
one	auto[0]	366	1		T1	1		T30	5		T166	2
one	auto[1]	429	1		T1	1		T30	7		T292	12
zero	auto[0]	511	1		T17	1		T30	7		T497	1
zero	auto[1]	10552	1		T5	15		T6	2		T30	110