Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
56.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	96	48	48	50.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	48	48	50.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	66422	1		T1	12		T2	1		T3	1
auto[1]	37595	1		T1	12		T2	1		T27	1

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	8938	1		T1	2		T4	10		T29	1
endpoints[0x1]	9697	1		T1	2		T27	2		T4	10
endpoints[0x2]	7650	1		T1	2		T30	41		T99	1
endpoints[0x3]	10307	1		T1	2		T3	1		T4	10
endpoints[0x4]	8041	1		T1	2		T2	2		T4	10
endpoints[0x5]	7768	1		T1	2		T17	1		T4	10
endpoints[0x6]	7236	1		T1	2		T30	35		T93	1
endpoints[0x7]	9131	1		T1	2		T18	1		T4	10
endpoints[0x8]	9263	1		T1	2		T6	18		T30	40
endpoints[0x9]	11237	1		T1	2		T30	33		T100	1
endpoints[0xa]	8322	1		T1	2		T6	10		T30	22
endpoints[0xb]	6427	1		T1	2		T4	10		T22	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
nak	0	1	1
ack	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	47888	1		T4	32		T6	29		T28	400
data0	56118	1		T1	24		T2	2		T3	1

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	48	48	50.00	48

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER
[nak , ack]	*	*	--	--	48

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	endpoints[0x0]	2390	1		T4	2		T30	9		T170	4
data1	auto[0]	endpoints[0x1]	2882	1		T4	1		T29	4		T30	9
data1	auto[0]	endpoints[0x2]	1775	1		T30	10		T92	22		T124	2
data1	auto[0]	endpoints[0x3]	3374	1		T4	1		T28	400		T30	8
data1	auto[0]	endpoints[0x4]	1940	1		T4	2		T30	12		T31	1
data1	auto[0]	endpoints[0x5]	1946	1		T4	2		T6	3		T30	10
data1	auto[0]	endpoints[0x6]	1827	1		T30	10		T164	2		T170	4
data1	auto[0]	endpoints[0x7]	2710	1		T4	2		T6	4		T30	5
data1	auto[0]	endpoints[0x8]	2329	1		T6	3		T30	10		T164	1
data1	auto[0]	endpoints[0x9]	3566	1		T30	6		T96	3		T164	2
data1	auto[0]	endpoints[0xa]	2342	1		T30	4		T46	3		T164	2
data1	auto[0]	endpoints[0xb]	1320	1		T4	1		T30	7		T47	3
data1	auto[1]	endpoints[0x0]	1724	1		T4	3		T30	8		T124	3
data1	auto[1]	endpoints[0x1]	1618	1		T4	3		T30	8		T86	3
data1	auto[1]	endpoints[0x2]	1662	1		T30	10		T92	22		T55	9
data1	auto[1]	endpoints[0x3]	1508	1		T4	3		T30	10		T86	5
data1	auto[1]	endpoints[0x4]	1740	1		T4	2		T30	6		T31	1
data1	auto[1]	endpoints[0x5]	1620	1		T4	3		T6	5		T30	9
data1	auto[1]	endpoints[0x6]	1484	1		T30	7		T86	4		T164	2
data1	auto[1]	endpoints[0x7]	1490	1		T4	3		T6	5		T30	6
data1	auto[1]	endpoints[0x8]	1898	1		T6	5		T30	9		T164	4
data1	auto[1]	endpoints[0x9]	1746	1		T30	10		T96	1		T164	2
data1	auto[1]	endpoints[0xa]	1435	1		T30	6		T164	2		T170	4
data1	auto[1]	endpoints[0xb]	1562	1		T4	4		T6	4		T30	10
data0	auto[0]	endpoints[0x0]	3223	1		T1	1		T4	3		T29	1
data0	auto[0]	endpoints[0x1]	3747	1		T1	1		T27	1		T4	4
data0	auto[0]	endpoints[0x2]	2627	1		T1	1		T30	11		T99	1
data0	auto[0]	endpoints[0x3]	3940	1		T1	1		T3	1		T4	4
data0	auto[0]	endpoints[0x4]	2830	1		T1	1		T2	1		T4	3
data0	auto[0]	endpoints[0x5]	2686	1		T1	1		T17	1		T4	3
data0	auto[0]	endpoints[0x6]	2527	1		T1	1		T30	11		T93	1
data0	auto[0]	endpoints[0x7]	3519	1		T1	1		T18	1		T4	3
data0	auto[0]	endpoints[0x8]	3325	1		T1	1		T6	6		T30	11
data0	auto[0]	endpoints[0x9]	4339	1		T1	1		T30	6		T100	1
data0	auto[0]	endpoints[0xa]	3135	1		T1	1		T6	10		T30	5
data0	auto[0]	endpoints[0xb]	2112	1		T1	1		T4	4		T22	1
data0	auto[1]	endpoints[0x0]	1598	1		T1	1		T4	2		T30	8
data0	auto[1]	endpoints[0x1]	1445	1		T1	1		T27	1		T4	2
data0	auto[1]	endpoints[0x2]	1584	1		T1	1		T30	10		T92	23
data0	auto[1]	endpoints[0x3]	1485	1		T1	1		T4	2		T30	10
data0	auto[1]	endpoints[0x4]	1531	1		T1	1		T2	1		T4	3
data0	auto[1]	endpoints[0x5]	1515	1		T1	1		T4	2		T6	4
data0	auto[1]	endpoints[0x6]	1398	1		T1	1		T30	7		T86	2
data0	auto[1]	endpoints[0x7]	1412	1		T1	1		T4	2		T6	4
data0	auto[1]	endpoints[0x8]	1711	1		T1	1		T6	4		T30	10
data0	auto[1]	endpoints[0x9]	1586	1		T1	1		T30	11		T96	4
data0	auto[1]	endpoints[0xa]	1410	1		T1	1		T30	7		T38	1
data0	auto[1]	endpoints[0xb]	1433	1		T1	1		T4	1		T6	5