Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	6	10	62.50

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	6	10	62.50	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6520	1		T81	1		T120	2		T86	67
auto[1]	48427	1		T1	12		T2	1		T27	1

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	50027	1		T1	12		T2	1		T27	1
auto[1]	4920	1		T5	145		T6	20		T81	2

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	49876	1		T1	12		T2	1		T27	1
auto[1]	5071	1		T81	2		T94	1		T86	67

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
ignore_pre[PidTypePre]	319	1		T166	7		T317	6		T318	4
pkt_types[PidTypeInToken]	54628	1		T1	12		T2	1		T27	1

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	6	10	62.50	6

Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes

cp_pid	cp_in_enable	cp_in_iso	cp_in_stall	COUNT	AT LEAST	NUMBER
[ignore_pre[PidTypePre]]	*	[auto[0]]	[auto[1]]	--	--	2
[ignore_pre[PidTypePre]]	*	[auto[1]]	*	--	--	4

Covered bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

160

1

T166

4

T317

5

T318

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

159

1

T166

3

T317

1

T318

3

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3749

1

T86

40

T70

1

T89

66

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2520

1

T86

27

T87

1

T89

49

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

50

1

T120

2

T319

1

T320

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

41

1

T81

1

T321

1

T322

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

40977

1

T1

12

T2

1

T27

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2462

1

T81

1

T94

1

T86

40

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

4781

1

T5

145

T6

20

T81

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

48

1

T323

4

T324

1

T325

1