Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	169067	1		T1	14		T2	3		T3	2
all_pins[1]	169067	1		T1	14		T2	3		T3	2
all_pins[2]	169067	1		T1	14		T2	3		T3	2
all_pins[3]	169067	1		T1	14		T2	3		T3	2
all_pins[4]	169067	1		T1	14		T2	3		T3	2
all_pins[5]	169067	1		T1	14		T2	3		T3	2
all_pins[6]	169067	1		T1	14		T2	3		T3	2
all_pins[7]	169067	1		T1	14		T2	3		T3	2
all_pins[8]	169067	1		T1	14		T2	3		T3	2
all_pins[9]	169067	1		T1	14		T2	3		T3	2
all_pins[10]	169067	1		T1	14		T2	3		T3	2
all_pins[11]	169067	1		T1	14		T2	3		T3	2
all_pins[12]	169067	1		T1	14		T2	3		T3	2
all_pins[13]	169067	1		T1	14		T2	3		T3	2
all_pins[14]	169067	1		T1	14		T2	3		T3	2
all_pins[15]	169067	1		T1	14		T2	3		T3	2
all_pins[16]	169067	1		T1	14		T2	3		T3	2
all_pins[17]	169067	1		T1	14		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5407884	1		T1	436		T2	96		T3	64
values[0x1]	2260	1		T1	12		T27	1		T21	2
transitions[0x0=>0x1]	2008	1		T1	12		T27	1		T21	2
transitions[0x1=>0x0]	2008	1		T1	12		T27	1		T21	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	168955	1		T1	14		T2	3		T3	2
all_pins[0]	values[0x1]	112	1		T39	1		T41	1		T341	1
all_pins[0]	transitions[0x0=>0x1]	97	1		T39	1		T41	1		T341	1
all_pins[0]	transitions[0x1=>0x0]	864	1		T1	12		T27	1		T9	1
all_pins[1]	values[0x0]	168188	1		T1	2		T2	3		T3	2
all_pins[1]	values[0x1]	879	1		T1	12		T27	1		T9	1
all_pins[1]	transitions[0x0=>0x1]	868	1		T1	12		T27	1		T9	1
all_pins[1]	transitions[0x1=>0x0]	99	1		T37	1		T60	1		T61	1
all_pins[2]	values[0x0]	168957	1		T1	14		T2	3		T3	2
all_pins[2]	values[0x1]	110	1		T37	1		T60	1		T61	1
all_pins[2]	transitions[0x0=>0x1]	98	1		T37	1		T60	1		T61	1
all_pins[2]	transitions[0x1=>0x0]	49	1		T62	1		T224	1		T226	1
all_pins[3]	values[0x0]	169006	1		T1	14		T2	3		T3	2
all_pins[3]	values[0x1]	61	1		T62	1		T223	1		T224	1
all_pins[3]	transitions[0x0=>0x1]	38	1		T62	1		T224	1		T331	2
all_pins[3]	transitions[0x1=>0x0]	41	1		T63	1		T223	2		T224	2
all_pins[4]	values[0x0]	169003	1		T1	14		T2	3		T3	2
all_pins[4]	values[0x1]	64	1		T63	1		T223	3		T224	2
all_pins[4]	transitions[0x0=>0x1]	49	1		T63	1		T223	1		T224	2
all_pins[4]	transitions[0x1=>0x0]	51	1		T225	2		T226	1		T227	1
all_pins[5]	values[0x0]	169001	1		T1	14		T2	3		T3	2
all_pins[5]	values[0x1]	66	1		T223	2		T225	2		T226	2
all_pins[5]	transitions[0x0=>0x1]	52	1		T223	2		T225	2		T226	2
all_pins[5]	transitions[0x1=>0x0]	97	1		T36	1		T38	1		T64	1
all_pins[6]	values[0x0]	168956	1		T1	14		T2	3		T3	2
all_pins[6]	values[0x1]	111	1		T36	1		T38	1		T64	1
all_pins[6]	transitions[0x0=>0x1]	95	1		T36	1		T38	1		T64	1
all_pins[6]	transitions[0x1=>0x0]	48	1		T42	1		T43	1		T223	1
all_pins[7]	values[0x0]	169003	1		T1	14		T2	3		T3	2
all_pins[7]	values[0x1]	64	1		T42	1		T43	1		T223	1
all_pins[7]	transitions[0x0=>0x1]	48	1		T42	1		T43	1		T223	1
all_pins[7]	transitions[0x1=>0x0]	76	1		T49	1		T50	1		T51	1
all_pins[8]	values[0x0]	168975	1		T1	14		T2	3		T3	2
all_pins[8]	values[0x1]	92	1		T49	1		T50	1		T51	1
all_pins[8]	transitions[0x0=>0x1]	79	1		T49	1		T50	1		T51	1
all_pins[8]	transitions[0x1=>0x0]	58	1		T21	2		T58	2		T59	2
all_pins[9]	values[0x0]	168996	1		T1	14		T2	3		T3	2
all_pins[9]	values[0x1]	71	1		T21	2		T58	2		T59	2
all_pins[9]	transitions[0x0=>0x1]	51	1		T21	2		T58	2		T59	2
all_pins[9]	transitions[0x1=>0x0]	52	1		T223	2		T331	2		T228	2
all_pins[10]	values[0x0]	168995	1		T1	14		T2	3		T3	2
all_pins[10]	values[0x1]	72	1		T223	2		T226	1		T227	1
all_pins[10]	transitions[0x0=>0x1]	52	1		T223	2		T226	1		T227	1
all_pins[10]	transitions[0x1=>0x0]	92	1		T69	1		T72	1		T73	1
all_pins[11]	values[0x0]	168955	1		T1	14		T2	3		T3	2
all_pins[11]	values[0x1]	112	1		T69	1		T72	1		T73	1
all_pins[11]	transitions[0x0=>0x1]	104	1		T69	1		T72	1		T73	1
all_pins[11]	transitions[0x1=>0x0]	50	1		T75	1		T77	1		T78	1
all_pins[12]	values[0x0]	169009	1		T1	14		T2	3		T3	2
all_pins[12]	values[0x1]	58	1		T75	1		T77	1		T78	1
all_pins[12]	transitions[0x0=>0x1]	47	1		T75	1		T77	1		T78	1
all_pins[12]	transitions[0x1=>0x0]	117	1		T71	1		T74	1		T80	1
all_pins[13]	values[0x0]	168939	1		T1	14		T2	3		T3	2
all_pins[13]	values[0x1]	128	1		T71	1		T74	1		T80	1
all_pins[13]	transitions[0x0=>0x1]	110	1		T71	1		T74	1		T80	1
all_pins[13]	transitions[0x1=>0x0]	41	1		T225	1		T332	1		T307	1
all_pins[14]	values[0x0]	169008	1		T1	14		T2	3		T3	2
all_pins[14]	values[0x1]	59	1		T225	3		T228	2		T332	1
all_pins[14]	transitions[0x0=>0x1]	43	1		T225	1		T228	2		T308	2
all_pins[14]	transitions[0x1=>0x0]	44	1		T223	3		T224	1		T225	1
all_pins[15]	values[0x0]	169007	1		T1	14		T2	3		T3	2
all_pins[15]	values[0x1]	60	1		T223	3		T224	1		T225	3
all_pins[15]	transitions[0x0=>0x1]	46	1		T223	3		T225	1		T227	1
all_pins[15]	transitions[0x1=>0x0]	69	1		T66	4		T67	4		T68	4
all_pins[16]	values[0x0]	168984	1		T1	14		T2	3		T3	2
all_pins[16]	values[0x1]	83	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x0=>0x1]	73	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x1=>0x0]	48	1		T52	1		T53	1		T54	1
all_pins[17]	values[0x0]	169009	1		T1	14		T2	3		T3	2
all_pins[17]	values[0x1]	58	1		T52	1		T53	1		T54	1
all_pins[17]	transitions[0x0=>0x1]	58	1		T52	1		T53	1		T54	1