Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4516	1		T81	1		T120	1		T86	50
invalid_ep[0xd]	4670	1		T121	1		T86	54		T87	1
invalid_ep[0xe]	4694	1		T86	58		T348	1		T70	2
invalid_ep[0xf]	4544	1		T81	2		T86	57		T87	2
endpoints[0x0]	12927	1		T1	2		T4	11		T29	1
endpoints[0x1]	14292	1		T1	2		T27	2		T4	11
endpoints[0x2]	12276	1		T1	2		T30	41		T99	1
endpoints[0x3]	14508	1		T1	2		T3	1		T4	11
endpoints[0x4]	12124	1		T1	2		T2	2		T4	11
endpoints[0x5]	11877	1		T1	2		T17	1		T4	11
endpoints[0x6]	11184	1		T1	2		T30	35		T81	2
endpoints[0x7]	13246	1		T1	2		T18	1		T4	11
endpoints[0x8]	13413	1		T1	2		T6	19		T30	40
endpoints[0x9]	15281	1		T1	2		T30	33		T100	1
endpoints[0xa]	12353	1		T1	2		T6	20		T30	22
endpoints[0xb]	10202	1		T1	2		T4	11		T5	145

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	21353	1		T3	1		T4	15		T6	11
pkt_types[PidTypeOutToken]	74605	1		T1	12		T2	1		T27	1
pkt_types[PidTypeInToken]	58572	1		T1	12		T2	1		T27	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	963	1		T86	11		T348	1		T89	14
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1025	1		T121	1		T86	14		T87	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1019	1		T86	16		T89	20		T90	25
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	985	1		T86	17		T348	1		T89	11
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1441	1		T4	2		T29	1		T86	15
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1577	1		T4	2		T86	8		T87	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1530	1		T124	3		T86	12		T168	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1297	1		T3	1		T4	2		T86	15
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1598	1		T31	1		T102	1		T86	15
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1400	1		T4	3		T6	4		T124	4
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1380	1		T81	2		T121	1		T86	15
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1377	1		T4	2		T6	4		T81	1
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1466	1		T6	3		T86	14		T87	1
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1562	1		T86	14		T89	18		T166	5
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1315	1		T86	11		T348	1		T172	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1418	1		T4	4		T124	3		T86	15
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1541	1		T81	1		T86	17		T70	3
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1642	1		T86	14		T70	2		T89	21
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1658	1		T86	17		T348	1		T70	2
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1577	1		T81	2		T86	11		T87	2
pkt_types[PidTypeOutToken]	endpoints[0x0]	5758	1		T1	1		T4	3		T30	19
pkt_types[PidTypeOutToken]	endpoints[0x1]	6820	1		T1	1		T27	1		T4	3
pkt_types[PidTypeOutToken]	endpoints[0x2]	4592	1		T1	1		T30	21		T99	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	7613	1		T1	1		T4	3		T28	800
pkt_types[PidTypeOutToken]	endpoints[0x4]	4756	1		T1	1		T2	1		T4	5
pkt_types[PidTypeOutToken]	endpoints[0x5]	4775	1		T1	1		T17	1		T4	2
pkt_types[PidTypeOutToken]	endpoints[0x6]	4640	1		T1	1		T30	21		T93	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	6378	1		T1	1		T18	1		T4	3
pkt_types[PidTypeOutToken]	endpoints[0x8]	5598	1		T1	1		T6	6		T30	21
pkt_types[PidTypeOutToken]	endpoints[0x9]	8029	1		T1	1		T30	12		T100	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	5730	1		T1	1		T6	10		T30	9
pkt_types[PidTypeOutToken]	endpoints[0xb]	3498	1		T1	1		T4	1		T22	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1027	1		T120	1		T86	14		T87	3
pkt_types[PidTypeInToken]	invalid_ep[0xd]	957	1		T86	12		T89	15		T90	16
pkt_types[PidTypeInToken]	invalid_ep[0xe]	983	1		T86	15		T89	22		T90	21
pkt_types[PidTypeInToken]	invalid_ep[0xf]	977	1		T86	17		T89	15		T90	22
pkt_types[PidTypeInToken]	endpoints[0x0]	4565	1		T1	1		T4	6		T30	16
pkt_types[PidTypeInToken]	endpoints[0x1]	4806	1		T1	1		T27	1		T4	6
pkt_types[PidTypeInToken]	endpoints[0x2]	5019	1		T1	1		T30	20		T92	46
pkt_types[PidTypeInToken]	endpoints[0x3]	4502	1		T1	1		T4	6		T30	20
pkt_types[PidTypeInToken]	endpoints[0x4]	4583	1		T1	1		T2	1		T4	6
pkt_types[PidTypeInToken]	endpoints[0x5]	4545	1		T1	1		T4	6		T6	10
pkt_types[PidTypeInToken]	endpoints[0x6]	4044	1		T1	1		T30	14		T93	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4346	1		T1	1		T4	6		T6	10
pkt_types[PidTypeInToken]	endpoints[0x8]	5217	1		T1	1		T6	10		T30	19
pkt_types[PidTypeInToken]	endpoints[0x9]	4590	1		T1	1		T30	21		T120	2
pkt_types[PidTypeInToken]	endpoints[0xa]	4211	1		T1	1		T6	10		T30	13
pkt_types[PidTypeInToken]	endpoints[0xb]	4200	1		T1	1		T4	6		T5	145