Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T223	4		T224	4		T225	7
all_values[1]	278	1		T223	4		T224	4		T225	7
all_values[2]	278	1		T223	4		T224	4		T225	7
all_values[3]	278	1		T223	4		T224	4		T225	7
all_values[4]	278	1		T223	4		T224	4		T225	7
all_values[5]	278	1		T223	4		T224	4		T225	7
all_values[6]	278	1		T223	4		T224	4		T225	7
all_values[7]	278	1		T223	4		T224	4		T225	7
all_values[8]	278	1		T223	4		T224	4		T225	7
all_values[9]	278	1		T223	4		T224	4		T225	7
all_values[10]	278	1		T223	4		T224	4		T225	7
all_values[11]	278	1		T223	4		T224	4		T225	7
all_values[12]	278	1		T223	4		T224	4		T225	7
all_values[13]	278	1		T223	4		T224	4		T225	7
all_values[14]	278	1		T223	4		T224	4		T225	7
all_values[15]	278	1		T223	4		T224	4		T225	7
all_values[16]	278	1		T223	4		T224	4		T225	7
all_values[17]	278	1		T223	4		T224	4		T225	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6575	1		T223	108		T224	103		T225	170
auto[1]	2321	1		T223	20		T224	25		T225	54

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6092	1		T223	78		T224	81		T225	163
auto[1]	2804	1		T223	50		T224	47		T225	61

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5180	1		T223	73		T224	74		T225	135
auto[1]	3716	1		T223	55		T224	54		T225	89

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	86	1		T223	1		T224	1		T225	4
all_values[0]	auto[0]	auto[1]	auto[0]	76	1		T223	1		T225	2		T226	1
all_values[0]	auto[1]	auto[0]	auto[1]	58	1		T223	2		T224	2		T225	1
all_values[0]	auto[1]	auto[1]	auto[1]	58	1		T224	1		T226	1		T228	1
all_values[1]	auto[0]	auto[0]	auto[0]	87	1		T223	3		T225	2		T227	1
all_values[1]	auto[0]	auto[1]	auto[0]	75	1		T224	1		T225	4		T226	3
all_values[1]	auto[1]	auto[0]	auto[1]	67	1		T224	2		T227	2		T331	1
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T223	1		T224	1		T225	1
all_values[2]	auto[0]	auto[0]	auto[0]	53	1		T224	3		T225	3		T226	2
all_values[2]	auto[0]	auto[0]	auto[1]	37	1		T223	1		T224	1		T225	1
all_values[2]	auto[0]	auto[1]	auto[0]	40	1		T306	3		T332	2		T333	2
all_values[2]	auto[0]	auto[1]	auto[1]	32	1		T223	1		T225	1		T227	1
all_values[2]	auto[1]	auto[0]	auto[1]	71	1		T223	2		T225	2		T226	2
all_values[2]	auto[1]	auto[1]	auto[1]	45	1		T227	1		T228	1		T306	3
all_values[3]	auto[0]	auto[0]	auto[0]	64	1		T224	1		T225	3		T226	1
all_values[3]	auto[0]	auto[0]	auto[1]	32	1		T223	1		T224	2		T226	1
all_values[3]	auto[0]	auto[1]	auto[0]	39	1		T225	2		T306	2		T333	2
all_values[3]	auto[0]	auto[1]	auto[1]	25	1		T223	1		T331	2		T332	1
all_values[3]	auto[1]	auto[0]	auto[1]	63	1		T223	2		T225	2		T226	1
all_values[3]	auto[1]	auto[1]	auto[1]	55	1		T224	1		T226	1		T331	2
all_values[4]	auto[0]	auto[0]	auto[0]	58	1		T224	1		T225	3		T226	1
all_values[4]	auto[0]	auto[0]	auto[1]	25	1		T225	1		T226	1		T227	1
all_values[4]	auto[0]	auto[1]	auto[0]	56	1		T227	1		T331	2		T306	1
all_values[4]	auto[0]	auto[1]	auto[1]	25	1		T223	1		T224	1		T225	2
all_values[4]	auto[1]	auto[0]	auto[1]	60	1		T223	1		T224	1		T225	1
all_values[4]	auto[1]	auto[1]	auto[1]	54	1		T223	2		T224	1		T226	1
all_values[5]	auto[0]	auto[0]	auto[0]	55	1		T223	1		T224	1		T225	2
all_values[5]	auto[0]	auto[0]	auto[1]	26	1		T225	1		T331	1		T332	2
all_values[5]	auto[0]	auto[1]	auto[0]	56	1		T224	2		T226	1		T227	1
all_values[5]	auto[0]	auto[1]	auto[1]	27	1		T223	1		T226	1		T331	1
all_values[5]	auto[1]	auto[0]	auto[1]	59	1		T223	1		T224	1		T225	1
all_values[5]	auto[1]	auto[1]	auto[1]	55	1		T223	1		T225	3		T226	2
all_values[6]	auto[0]	auto[0]	auto[0]	52	1		T223	1		T225	2		T331	2
all_values[6]	auto[0]	auto[0]	auto[1]	40	1		T223	1		T224	1		T225	2
all_values[6]	auto[0]	auto[1]	auto[0]	31	1		T331	1		T228	1		T332	1
all_values[6]	auto[0]	auto[1]	auto[1]	27	1		T227	1		T331	1		T307	4
all_values[6]	auto[1]	auto[0]	auto[1]	72	1		T223	1		T224	3		T225	3
all_values[6]	auto[1]	auto[1]	auto[1]	56	1		T223	1		T227	2		T331	1
all_values[7]	auto[0]	auto[0]	auto[0]	89	1		T223	1		T225	2		T226	2
all_values[7]	auto[0]	auto[1]	auto[0]	69	1		T223	1		T224	1		T225	2
all_values[7]	auto[1]	auto[0]	auto[1]	62	1		T223	2		T224	1		T225	3
all_values[7]	auto[1]	auto[1]	auto[1]	58	1		T224	2		T227	1		T331	2
all_values[8]	auto[0]	auto[0]	auto[0]	70	1		T223	1		T224	1		T225	1
all_values[8]	auto[0]	auto[1]	auto[0]	77	1		T223	1		T225	5		T226	2
all_values[8]	auto[1]	auto[0]	auto[1]	75	1		T224	2		T226	1		T227	1
all_values[8]	auto[1]	auto[1]	auto[1]	56	1		T223	2		T224	1		T225	1
all_values[9]	auto[0]	auto[0]	auto[0]	63	1		T223	2		T225	3		T331	4
all_values[9]	auto[0]	auto[0]	auto[1]	21	1		T224	1		T307	1		T334	3
all_values[9]	auto[0]	auto[1]	auto[0]	45	1		T225	1		T227	1		T228	1
all_values[9]	auto[0]	auto[1]	auto[1]	27	1		T223	1		T226	2		T331	1
all_values[9]	auto[1]	auto[0]	auto[1]	71	1		T223	1		T224	3		T225	2
all_values[9]	auto[1]	auto[1]	auto[1]	51	1		T225	1		T226	1		T227	3
all_values[10]	auto[0]	auto[0]	auto[0]	67	1		T223	1		T225	4		T226	1
all_values[10]	auto[0]	auto[0]	auto[1]	20	1		T226	1		T227	1		T332	1
all_values[10]	auto[0]	auto[1]	auto[0]	52	1		T223	1		T224	3		T331	1
all_values[10]	auto[0]	auto[1]	auto[1]	31	1		T223	1		T331	2		T228	1
all_values[10]	auto[1]	auto[0]	auto[1]	54	1		T224	1		T225	3		T226	1
all_values[10]	auto[1]	auto[1]	auto[1]	54	1		T223	1		T226	1		T227	1
all_values[11]	auto[0]	auto[0]	auto[0]	56	1		T224	2		T225	2		T226	1
all_values[11]	auto[0]	auto[0]	auto[1]	25	1		T223	2		T226	1		T331	1
all_values[11]	auto[0]	auto[1]	auto[0]	49	1		T225	3		T227	4		T332	2
all_values[11]	auto[0]	auto[1]	auto[1]	28	1		T224	1		T225	1		T331	1
all_values[11]	auto[1]	auto[0]	auto[1]	65	1		T223	2		T225	1		T226	2
all_values[11]	auto[1]	auto[1]	auto[1]	55	1		T224	1		T331	2		T228	1
all_values[12]	auto[0]	auto[0]	auto[0]	70	1		T225	1		T331	2		T306	2
all_values[12]	auto[0]	auto[0]	auto[1]	29	1		T223	1		T331	2		T333	1
all_values[12]	auto[0]	auto[1]	auto[0]	53	1		T224	2		T225	2		T226	1
all_values[12]	auto[0]	auto[1]	auto[1]	23	1		T224	1		T225	1		T226	1
all_values[12]	auto[1]	auto[0]	auto[1]	65	1		T223	3		T224	1		T225	1
all_values[12]	auto[1]	auto[1]	auto[1]	38	1		T225	2		T226	1		T227	2
all_values[13]	auto[0]	auto[0]	auto[0]	63	1		T223	1		T224	1		T333	1
all_values[13]	auto[0]	auto[0]	auto[1]	25	1		T223	1		T225	2		T331	2
all_values[13]	auto[0]	auto[1]	auto[0]	41	1		T226	1		T227	2		T331	2
all_values[13]	auto[0]	auto[1]	auto[1]	31	1		T224	1		T225	1		T226	2
all_values[13]	auto[1]	auto[0]	auto[1]	58	1		T223	2		T224	1		T225	2
all_values[13]	auto[1]	auto[1]	auto[1]	60	1		T224	1		T225	2		T226	1
all_values[14]	auto[0]	auto[0]	auto[0]	63	1		T223	3		T226	3		T227	1
all_values[14]	auto[0]	auto[0]	auto[1]	20	1		T224	1		T331	1		T228	1
all_values[14]	auto[0]	auto[1]	auto[0]	57	1		T226	1		T227	1		T331	1
all_values[14]	auto[0]	auto[1]	auto[1]	22	1		T225	1		T228	1		T307	1
all_values[14]	auto[1]	auto[0]	auto[1]	60	1		T223	1		T224	3		T225	3
all_values[14]	auto[1]	auto[1]	auto[1]	56	1		T225	3		T227	2		T306	1
all_values[15]	auto[0]	auto[0]	auto[0]	56	1		T224	3		T225	2		T226	1
all_values[15]	auto[0]	auto[0]	auto[1]	36	1		T223	1		T226	2		T333	1
all_values[15]	auto[0]	auto[1]	auto[0]	62	1		T227	1		T228	4		T306	1
all_values[15]	auto[0]	auto[1]	auto[1]	32	1		T223	2		T225	1		T306	2
all_values[15]	auto[1]	auto[0]	auto[1]	52	1		T223	1		T225	1		T226	1
all_values[15]	auto[1]	auto[1]	auto[1]	40	1		T224	1		T225	3		T227	1
all_values[16]	auto[0]	auto[0]	auto[0]	49	1		T223	1		T228	1		T332	1
all_values[16]	auto[0]	auto[0]	auto[1]	26	1		T223	1		T225	1		T331	2
all_values[16]	auto[0]	auto[1]	auto[0]	57	1		T225	3		T226	4		T227	1
all_values[16]	auto[0]	auto[1]	auto[1]	34	1		T224	2		T225	1		T227	2
all_values[16]	auto[1]	auto[0]	auto[1]	53	1		T223	2		T224	2		T225	1
all_values[16]	auto[1]	auto[1]	auto[1]	59	1		T225	1		T227	1		T331	1
all_values[17]	auto[0]	auto[0]	auto[0]	88	1		T223	2		T224	2		T225	3
all_values[17]	auto[0]	auto[1]	auto[0]	76	1		T225	4		T226	1		T227	2
all_values[17]	auto[1]	auto[0]	auto[1]	67	1		T223	2		T224	2		T331	1
all_values[17]	auto[1]	auto[1]	auto[1]	47	1		T226	2		T227	1		T331	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal