Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.59 97.96 93.95 97.44 81.25 96.42 98.17 89.95


Total test records in report: 3232
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html | tests63.html | tests64.html | tests65.html | tests66.html | tests67.html | tests68.html
T3071 /workspace/coverage/default/86.usbdev_endpoint_types.1515928222 Aug 07 06:12:54 PM PDT 24 Aug 07 06:12:55 PM PDT 24 279935755 ps
T3072 /workspace/coverage/default/21.usbdev_phy_pins_sense.3290853463 Aug 07 06:03:03 PM PDT 24 Aug 07 06:03:04 PM PDT 24 46014045 ps
T3073 /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.3587971321 Aug 07 06:11:13 PM PDT 24 Aug 07 06:11:44 PM PDT 24 2953615324 ps
T3074 /workspace/coverage/default/8.usbdev_fifo_rst.2888197054 Aug 07 06:00:27 PM PDT 24 Aug 07 06:00:29 PM PDT 24 181044950 ps
T3075 /workspace/coverage/default/120.usbdev_endpoint_types.1247638900 Aug 07 06:13:03 PM PDT 24 Aug 07 06:13:05 PM PDT 24 569285659 ps
T3076 /workspace/coverage/default/6.usbdev_max_length_out_transaction.1474452015 Aug 07 06:00:01 PM PDT 24 Aug 07 06:00:02 PM PDT 24 199490220 ps
T3077 /workspace/coverage/default/39.usbdev_stream_len_max.3354934754 Aug 07 06:10:08 PM PDT 24 Aug 07 06:10:11 PM PDT 24 915559625 ps
T3078 /workspace/coverage/default/33.usbdev_alert_test.1222599803 Aug 07 06:06:32 PM PDT 24 Aug 07 06:06:33 PM PDT 24 41678888 ps
T3079 /workspace/coverage/default/48.usbdev_stall_trans.4171982194 Aug 07 06:12:27 PM PDT 24 Aug 07 06:12:28 PM PDT 24 155149147 ps
T3080 /workspace/coverage/default/12.usbdev_random_length_out_transaction.1140686476 Aug 07 06:01:23 PM PDT 24 Aug 07 06:01:24 PM PDT 24 175138342 ps
T3081 /workspace/coverage/default/15.usbdev_aon_wake_resume.4137550214 Aug 07 06:01:51 PM PDT 24 Aug 07 06:02:22 PM PDT 24 25247741277 ps
T3082 /workspace/coverage/default/28.usbdev_max_length_in_transaction.2823672728 Aug 07 06:04:38 PM PDT 24 Aug 07 06:04:39 PM PDT 24 250450006 ps
T3083 /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2086772034 Aug 07 06:08:01 PM PDT 24 Aug 07 06:08:08 PM PDT 24 5144539969 ps
T3084 /workspace/coverage/default/10.usbdev_disable_endpoint.1778478253 Aug 07 06:00:57 PM PDT 24 Aug 07 06:00:59 PM PDT 24 581674568 ps
T3085 /workspace/coverage/default/5.usbdev_phy_config_pinflip.3452673255 Aug 07 05:59:48 PM PDT 24 Aug 07 05:59:49 PM PDT 24 222141102 ps
T3086 /workspace/coverage/default/12.usbdev_rx_full.1285327347 Aug 07 06:01:23 PM PDT 24 Aug 07 06:01:24 PM PDT 24 302398356 ps
T3087 /workspace/coverage/default/1.usbdev_random_length_out_transaction.1723496850 Aug 07 05:58:40 PM PDT 24 Aug 07 05:58:41 PM PDT 24 169813449 ps
T3088 /workspace/coverage/default/5.usbdev_pending_in_trans.2467189482 Aug 07 05:59:49 PM PDT 24 Aug 07 05:59:50 PM PDT 24 155813717 ps
T3089 /workspace/coverage/default/3.usbdev_out_trans_nak.3573003178 Aug 07 05:59:18 PM PDT 24 Aug 07 05:59:19 PM PDT 24 172180999 ps
T3090 /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2711716366 Aug 07 05:58:07 PM PDT 24 Aug 07 05:58:08 PM PDT 24 161260605 ps
T3091 /workspace/coverage/default/43.usbdev_enable.1777735187 Aug 07 06:11:06 PM PDT 24 Aug 07 06:11:07 PM PDT 24 106182857 ps
T3092 /workspace/coverage/default/47.usbdev_device_timeout.2367146507 Aug 07 06:12:02 PM PDT 24 Aug 07 06:12:07 PM PDT 24 744912782 ps
T3093 /workspace/coverage/default/49.usbdev_streaming_out.2525605229 Aug 07 06:12:43 PM PDT 24 Aug 07 06:13:38 PM PDT 24 1909896631 ps
T3094 /workspace/coverage/default/141.usbdev_endpoint_types.855380343 Aug 07 06:13:18 PM PDT 24 Aug 07 06:13:19 PM PDT 24 255375348 ps
T3095 /workspace/coverage/default/25.usbdev_out_trans_nak.4018370787 Aug 07 06:03:35 PM PDT 24 Aug 07 06:03:36 PM PDT 24 193970923 ps
T3096 /workspace/coverage/default/6.usbdev_pkt_buffer.588875614 Aug 07 05:59:59 PM PDT 24 Aug 07 06:00:24 PM PDT 24 9681147984 ps
T3097 /workspace/coverage/default/32.usbdev_pkt_sent.2008809597 Aug 07 06:06:00 PM PDT 24 Aug 07 06:06:02 PM PDT 24 237495974 ps
T3098 /workspace/coverage/default/22.usbdev_data_toggle_clear.341260352 Aug 07 06:03:04 PM PDT 24 Aug 07 06:03:06 PM PDT 24 686324800 ps
T3099 /workspace/coverage/default/22.usbdev_stall_trans.252983449 Aug 07 06:03:04 PM PDT 24 Aug 07 06:03:05 PM PDT 24 193012009 ps
T3100 /workspace/coverage/default/6.usbdev_aon_wake_resume.1741508131 Aug 07 05:59:55 PM PDT 24 Aug 07 06:00:40 PM PDT 24 30232473126 ps
T3101 /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1307863979 Aug 07 05:58:29 PM PDT 24 Aug 07 05:59:02 PM PDT 24 3175714135 ps
T3102 /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2986163557 Aug 07 06:09:00 PM PDT 24 Aug 07 06:10:35 PM PDT 24 3343735044 ps
T3103 /workspace/coverage/default/33.usbdev_out_stall.915524200 Aug 07 06:06:22 PM PDT 24 Aug 07 06:06:23 PM PDT 24 160953194 ps
T3104 /workspace/coverage/default/24.usbdev_random_length_out_transaction.2036257524 Aug 07 06:03:18 PM PDT 24 Aug 07 06:03:19 PM PDT 24 171302623 ps
T3105 /workspace/coverage/default/23.usbdev_out_trans_nak.3576759448 Aug 07 06:03:05 PM PDT 24 Aug 07 06:03:06 PM PDT 24 245051164 ps
T3106 /workspace/coverage/default/48.usbdev_random_length_in_transaction.955807689 Aug 07 06:12:26 PM PDT 24 Aug 07 06:12:27 PM PDT 24 229271272 ps
T3107 /workspace/coverage/default/5.usbdev_random_length_out_transaction.2975546349 Aug 07 05:59:49 PM PDT 24 Aug 07 05:59:50 PM PDT 24 147225285 ps
T3108 /workspace/coverage/default/29.usbdev_rx_full.3057734846 Aug 07 06:04:55 PM PDT 24 Aug 07 06:04:56 PM PDT 24 267982997 ps
T3109 /workspace/coverage/default/3.usbdev_min_length_in_transaction.87971312 Aug 07 05:59:08 PM PDT 24 Aug 07 05:59:09 PM PDT 24 153838444 ps
T3110 /workspace/coverage/default/31.usbdev_pkt_received.607357601 Aug 07 06:05:31 PM PDT 24 Aug 07 06:05:32 PM PDT 24 194877419 ps
T3111 /workspace/coverage/default/42.usbdev_rx_full.739711404 Aug 07 06:11:10 PM PDT 24 Aug 07 06:11:12 PM PDT 24 244113143 ps
T3112 /workspace/coverage/default/25.usbdev_alert_test.3700588593 Aug 07 06:03:41 PM PDT 24 Aug 07 06:03:42 PM PDT 24 33920651 ps
T3113 /workspace/coverage/default/7.usbdev_rand_bus_resets.1519942973 Aug 07 06:00:23 PM PDT 24 Aug 07 06:01:15 PM PDT 24 2055770907 ps
T3114 /workspace/coverage/default/23.usbdev_disconnected.145128878 Aug 07 06:03:00 PM PDT 24 Aug 07 06:03:01 PM PDT 24 138098051 ps
T3115 /workspace/coverage/default/3.usbdev_stall_trans.2042417304 Aug 07 05:59:18 PM PDT 24 Aug 07 05:59:19 PM PDT 24 151122305 ps
T3116 /workspace/coverage/default/29.usbdev_setup_stage.3328337100 Aug 07 06:04:55 PM PDT 24 Aug 07 06:04:56 PM PDT 24 175635185 ps
T3117 /workspace/coverage/default/11.usbdev_pkt_buffer.2786768898 Aug 07 06:01:11 PM PDT 24 Aug 07 06:01:49 PM PDT 24 15776533285 ps
T3118 /workspace/coverage/default/26.usbdev_low_speed_traffic.892586620 Aug 07 06:03:43 PM PDT 24 Aug 07 06:04:12 PM PDT 24 3829779469 ps
T3119 /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2208601648 Aug 07 06:02:24 PM PDT 24 Aug 07 06:02:25 PM PDT 24 170450606 ps
T3120 /workspace/coverage/default/10.usbdev_rx_full.703767203 Aug 07 06:01:02 PM PDT 24 Aug 07 06:01:03 PM PDT 24 364692348 ps
T3121 /workspace/coverage/default/20.usbdev_alert_test.1600448728 Aug 07 06:02:51 PM PDT 24 Aug 07 06:02:52 PM PDT 24 43024118 ps
T3122 /workspace/coverage/default/43.usbdev_setup_trans_ignored.3425904547 Aug 07 06:11:14 PM PDT 24 Aug 07 06:11:15 PM PDT 24 175858272 ps
T3123 /workspace/coverage/default/10.usbdev_endpoint_types.877829673 Aug 07 06:01:49 PM PDT 24 Aug 07 06:01:51 PM PDT 24 603998565 ps
T3124 /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.394368878 Aug 07 06:11:25 PM PDT 24 Aug 07 06:13:07 PM PDT 24 3733775517 ps
T3125 /workspace/coverage/default/17.usbdev_data_toggle_restore.1542071223 Aug 07 06:02:08 PM PDT 24 Aug 07 06:02:10 PM PDT 24 816310005 ps
T3126 /workspace/coverage/default/14.usbdev_in_iso.4171232653 Aug 07 06:01:45 PM PDT 24 Aug 07 06:01:47 PM PDT 24 160574683 ps
T3127 /workspace/coverage/default/10.usbdev_alert_test.1351244064 Aug 07 06:01:03 PM PDT 24 Aug 07 06:01:04 PM PDT 24 34892735 ps
T270 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1964248304 Aug 07 04:58:50 PM PDT 24 Aug 07 04:58:51 PM PDT 24 104816723 ps
T223 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.954807150 Aug 07 04:59:24 PM PDT 24 Aug 07 04:59:24 PM PDT 24 43298825 ps
T224 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.41894268 Aug 07 04:59:12 PM PDT 24 Aug 07 04:59:13 PM PDT 24 105069951 ps
T225 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3027204767 Aug 07 04:59:15 PM PDT 24 Aug 07 04:59:16 PM PDT 24 42665429 ps
T215 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2903496224 Aug 07 04:59:01 PM PDT 24 Aug 07 04:59:02 PM PDT 24 77321935 ps
T216 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.351727125 Aug 07 04:58:57 PM PDT 24 Aug 07 04:58:59 PM PDT 24 100141858 ps
T226 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2836103271 Aug 07 04:59:35 PM PDT 24 Aug 07 04:59:36 PM PDT 24 62690603 ps
T3128 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4197178698 Aug 07 04:59:05 PM PDT 24 Aug 07 04:59:08 PM PDT 24 275489262 ps
T227 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4093894117 Aug 07 04:59:26 PM PDT 24 Aug 07 04:59:27 PM PDT 24 77463404 ps
T218 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.418965233 Aug 07 04:59:16 PM PDT 24 Aug 07 04:59:18 PM PDT 24 449791346 ps
T331 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3979269717 Aug 07 04:58:49 PM PDT 24 Aug 07 04:58:50 PM PDT 24 49482704 ps
T228 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1091718795 Aug 07 04:59:11 PM PDT 24 Aug 07 04:59:12 PM PDT 24 83392297 ps
T217 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2143453349 Aug 07 04:59:14 PM PDT 24 Aug 07 04:59:17 PM PDT 24 97585561 ps
T219 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1823549847 Aug 07 04:58:52 PM PDT 24 Aug 07 04:58:57 PM PDT 24 1113190225 ps
T306 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3348664863 Aug 07 04:59:20 PM PDT 24 Aug 07 04:59:21 PM PDT 24 44578363 ps
T244 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1948000273 Aug 07 04:59:20 PM PDT 24 Aug 07 04:59:23 PM PDT 24 206143560 ps
T332 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1611741005 Aug 07 04:59:09 PM PDT 24 Aug 07 04:59:10 PM PDT 24 40953563 ps
T288 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.176189876 Aug 07 04:58:46 PM PDT 24 Aug 07 04:58:57 PM PDT 24 103813983 ps
T289 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2792514367 Aug 07 04:58:55 PM PDT 24 Aug 07 04:58:56 PM PDT 24 100043630 ps
T245 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.433733163 Aug 07 04:59:23 PM PDT 24 Aug 07 04:59:26 PM PDT 24 90308337 ps
T241 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3367382291 Aug 07 04:59:04 PM PDT 24 Aug 07 04:59:06 PM PDT 24 303510005 ps
T333 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3073462115 Aug 07 04:59:10 PM PDT 24 Aug 07 04:59:11 PM PDT 24 94855656 ps
T261 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.892433483 Aug 07 04:59:19 PM PDT 24 Aug 07 04:59:21 PM PDT 24 80374678 ps
T3129 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3541787683 Aug 07 04:59:46 PM PDT 24 Aug 07 04:59:47 PM PDT 24 51052134 ps
T307 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3197194535 Aug 07 04:59:21 PM PDT 24 Aug 07 04:59:22 PM PDT 24 63532857 ps
T3130 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2537605479 Aug 07 04:59:37 PM PDT 24 Aug 07 04:59:38 PM PDT 24 34351941 ps
T308 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.497626947 Aug 07 04:59:21 PM PDT 24 Aug 07 04:59:22 PM PDT 24 63677404 ps
T309 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3939845811 Aug 07 04:59:28 PM PDT 24 Aug 07 04:59:29 PM PDT 24 45178330 ps
T3131 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.428347711 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:54 PM PDT 24 380696292 ps
T242 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3377700764 Aug 07 04:58:52 PM PDT 24 Aug 07 04:58:55 PM PDT 24 161762099 ps
T3132 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1978992839 Aug 07 04:59:20 PM PDT 24 Aug 07 04:59:21 PM PDT 24 67202907 ps
T290 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3490273273 Aug 07 04:59:18 PM PDT 24 Aug 07 04:59:20 PM PDT 24 143569760 ps
T257 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2672035353 Aug 07 04:58:50 PM PDT 24 Aug 07 04:58:57 PM PDT 24 139656794 ps
T262 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1231313395 Aug 07 04:58:55 PM PDT 24 Aug 07 04:58:57 PM PDT 24 80837056 ps
T255 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3161836288 Aug 07 04:59:17 PM PDT 24 Aug 07 04:59:19 PM PDT 24 76091359 ps
T246 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1499701298 Aug 07 04:59:06 PM PDT 24 Aug 07 04:59:10 PM PDT 24 570817928 ps
T301 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3970085089 Aug 07 04:58:45 PM PDT 24 Aug 07 04:58:47 PM PDT 24 312031268 ps
T247 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3660972404 Aug 07 04:58:48 PM PDT 24 Aug 07 04:58:51 PM PDT 24 858407508 ps
T271 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3215212860 Aug 07 04:59:14 PM PDT 24 Aug 07 04:59:15 PM PDT 24 78945511 ps
T256 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3279090726 Aug 07 04:59:19 PM PDT 24 Aug 07 04:59:21 PM PDT 24 146915018 ps
T3133 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1491962661 Aug 07 04:59:34 PM PDT 24 Aug 07 04:59:35 PM PDT 24 48646467 ps
T272 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2487321305 Aug 07 04:59:24 PM PDT 24 Aug 07 04:59:25 PM PDT 24 56310264 ps
T273 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1589581498 Aug 07 04:59:08 PM PDT 24 Aug 07 04:59:09 PM PDT 24 51208923 ps
T337 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.207164926 Aug 07 04:58:45 PM PDT 24 Aug 07 04:58:49 PM PDT 24 760820683 ps
T291 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4233366245 Aug 07 04:58:47 PM PDT 24 Aug 07 04:58:49 PM PDT 24 96716001 ps
T3134 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3038915080 Aug 07 04:58:48 PM PDT 24 Aug 07 04:58:51 PM PDT 24 109052562 ps
T252 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1677447004 Aug 07 04:58:53 PM PDT 24 Aug 07 04:58:55 PM PDT 24 94231633 ps
T3135 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3791316573 Aug 07 04:59:20 PM PDT 24 Aug 07 04:59:22 PM PDT 24 154946010 ps
T302 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.864617469 Aug 07 04:58:56 PM PDT 24 Aug 07 04:58:58 PM PDT 24 165570904 ps
T274 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3480392895 Aug 07 04:59:17 PM PDT 24 Aug 07 04:59:18 PM PDT 24 65901364 ps
T3136 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.859659458 Aug 07 04:59:15 PM PDT 24 Aug 07 04:59:16 PM PDT 24 80793997 ps
T3137 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3956878997 Aug 07 04:59:19 PM PDT 24 Aug 07 04:59:20 PM PDT 24 47873379 ps
T3138 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1511831003 Aug 07 04:59:24 PM PDT 24 Aug 07 04:59:25 PM PDT 24 41026061 ps
T275 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2609577999 Aug 07 04:59:09 PM PDT 24 Aug 07 04:59:10 PM PDT 24 52924193 ps
T303 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.250457005 Aug 07 04:59:00 PM PDT 24 Aug 07 04:59:02 PM PDT 24 170996643 ps
T3139 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2088704245 Aug 07 04:59:18 PM PDT 24 Aug 07 04:59:19 PM PDT 24 46926218 ps
T3140 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2360962381 Aug 07 04:58:57 PM PDT 24 Aug 07 04:59:06 PM PDT 24 901447767 ps
T339 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1667148909 Aug 07 04:59:13 PM PDT 24 Aug 07 04:59:18 PM PDT 24 1933654741 ps
T334 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1568960082 Aug 07 04:59:14 PM PDT 24 Aug 07 04:59:15 PM PDT 24 40450587 ps
T3141 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1507567526 Aug 07 04:58:56 PM PDT 24 Aug 07 04:58:57 PM PDT 24 174444191 ps
T3142 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4082684434 Aug 07 04:59:24 PM PDT 24 Aug 07 04:59:25 PM PDT 24 51001724 ps
T3143 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.598968763 Aug 07 04:59:23 PM PDT 24 Aug 07 04:59:24 PM PDT 24 64188146 ps
T3144 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.638992536 Aug 07 04:58:46 PM PDT 24 Aug 07 04:58:47 PM PDT 24 368842040 ps
T3145 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2676831846 Aug 07 04:59:16 PM PDT 24 Aug 07 04:59:17 PM PDT 24 75612872 ps
T3146 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3689618415 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:42 PM PDT 24 45661756 ps
T253 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2676983769 Aug 07 04:59:08 PM PDT 24 Aug 07 04:59:12 PM PDT 24 119289640 ps
T276 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2403661157 Aug 07 04:58:48 PM PDT 24 Aug 07 04:58:49 PM PDT 24 108430407 ps
T3147 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4138662699 Aug 07 04:58:52 PM PDT 24 Aug 07 04:58:53 PM PDT 24 60827705 ps
T277 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1722263345 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:52 PM PDT 24 148429439 ps
T3148 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2981636279 Aug 07 04:59:33 PM PDT 24 Aug 07 04:59:34 PM PDT 24 41069452 ps
T3149 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.4226428259 Aug 07 04:59:23 PM PDT 24 Aug 07 04:59:25 PM PDT 24 209115084 ps
T3150 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2137545373 Aug 07 04:59:21 PM PDT 24 Aug 07 04:59:22 PM PDT 24 49902552 ps
T3151 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2282604535 Aug 07 04:59:34 PM PDT 24 Aug 07 04:59:35 PM PDT 24 46883976 ps
T254 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.65653545 Aug 07 04:59:03 PM PDT 24 Aug 07 04:59:06 PM PDT 24 165067711 ps
T3152 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.122200060 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:52 PM PDT 24 95045288 ps
T3153 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3383419571 Aug 07 04:59:10 PM PDT 24 Aug 07 04:59:11 PM PDT 24 62891203 ps
T3154 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.751963065 Aug 07 04:58:56 PM PDT 24 Aug 07 04:58:58 PM PDT 24 104855892 ps
T3155 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2950260581 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:52 PM PDT 24 110469159 ps
T3156 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.930170503 Aug 07 04:58:53 PM PDT 24 Aug 07 04:58:54 PM PDT 24 80641961 ps
T259 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2950951819 Aug 07 04:59:04 PM PDT 24 Aug 07 04:59:06 PM PDT 24 230894231 ps
T304 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1455274917 Aug 07 04:59:07 PM PDT 24 Aug 07 04:59:10 PM PDT 24 402674623 ps
T278 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2610796215 Aug 07 04:58:54 PM PDT 24 Aug 07 04:59:02 PM PDT 24 1638780205 ps
T3157 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1503834984 Aug 07 04:58:52 PM PDT 24 Aug 07 04:58:54 PM PDT 24 255061966 ps
T305 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1364873348 Aug 07 04:59:10 PM PDT 24 Aug 07 04:59:12 PM PDT 24 181120228 ps
T260 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.448980899 Aug 07 04:58:56 PM PDT 24 Aug 07 04:58:59 PM PDT 24 253948846 ps
T279 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2848452679 Aug 07 04:59:20 PM PDT 24 Aug 07 04:59:21 PM PDT 24 130146958 ps
T3158 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2616597880 Aug 07 04:58:44 PM PDT 24 Aug 07 04:58:46 PM PDT 24 163656020 ps
T3159 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2725886746 Aug 07 04:58:55 PM PDT 24 Aug 07 04:58:58 PM PDT 24 295555646 ps
T3160 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3725821085 Aug 07 04:59:14 PM PDT 24 Aug 07 04:59:15 PM PDT 24 112315023 ps
T280 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1367203908 Aug 07 04:58:47 PM PDT 24 Aug 07 04:58:49 PM PDT 24 100006533 ps
T3161 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3122422846 Aug 07 04:59:15 PM PDT 24 Aug 07 04:59:16 PM PDT 24 42433145 ps
T3162 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.571461385 Aug 07 04:59:28 PM PDT 24 Aug 07 04:59:32 PM PDT 24 299768910 ps
T480 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4234410528 Aug 07 04:59:03 PM PDT 24 Aug 07 04:59:06 PM PDT 24 418857228 ps
T338 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.129493837 Aug 07 04:58:57 PM PDT 24 Aug 07 04:59:02 PM PDT 24 2183979040 ps
T3163 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3364784407 Aug 07 04:58:50 PM PDT 24 Aug 07 04:58:53 PM PDT 24 110040602 ps
T3164 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2085522993 Aug 07 04:58:45 PM PDT 24 Aug 07 04:58:46 PM PDT 24 101952256 ps
T3165 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3228268370 Aug 07 04:58:50 PM PDT 24 Aug 07 04:58:51 PM PDT 24 73147750 ps
T3166 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1641034610 Aug 07 04:59:13 PM PDT 24 Aug 07 04:59:16 PM PDT 24 227230833 ps
T281 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3967368224 Aug 07 04:58:57 PM PDT 24 Aug 07 04:59:06 PM PDT 24 1553362841 ps
T282 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.825555038 Aug 07 04:58:47 PM PDT 24 Aug 07 04:58:49 PM PDT 24 153117911 ps
T285 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1323345924 Aug 07 04:59:13 PM PDT 24 Aug 07 04:59:14 PM PDT 24 117262480 ps
T3167 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3027361962 Aug 07 04:59:28 PM PDT 24 Aug 07 04:59:29 PM PDT 24 64781038 ps
T3168 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.566533151 Aug 07 04:58:54 PM PDT 24 Aug 07 04:58:55 PM PDT 24 98292446 ps
T340 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3474899294 Aug 07 04:59:07 PM PDT 24 Aug 07 04:59:11 PM PDT 24 755258118 ps
T3169 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.802816330 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:52 PM PDT 24 65186341 ps
T3170 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2842280262 Aug 07 04:58:55 PM PDT 24 Aug 07 04:58:57 PM PDT 24 103860548 ps
T3171 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3374405350 Aug 07 04:59:23 PM PDT 24 Aug 07 04:59:26 PM PDT 24 241857755 ps
T3172 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.154807238 Aug 07 04:59:22 PM PDT 24 Aug 07 04:59:23 PM PDT 24 104270833 ps
T3173 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1667150327 Aug 07 04:59:15 PM PDT 24 Aug 07 04:59:18 PM PDT 24 453628578 ps
T3174 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.552929513 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:53 PM PDT 24 87717667 ps
T258 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2507721271 Aug 07 04:59:23 PM PDT 24 Aug 07 04:59:28 PM PDT 24 605376013 ps
T3175 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1768841482 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:53 PM PDT 24 118001162 ps
T3176 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1140579322 Aug 07 04:59:12 PM PDT 24 Aug 07 04:59:14 PM PDT 24 153310197 ps
T3177 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3046167402 Aug 07 04:59:05 PM PDT 24 Aug 07 04:59:07 PM PDT 24 171443361 ps
T3178 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1620694240 Aug 07 04:58:48 PM PDT 24 Aug 07 04:58:49 PM PDT 24 90845250 ps
T3179 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2280769631 Aug 07 04:58:57 PM PDT 24 Aug 07 04:59:01 PM PDT 24 488170868 ps
T3180 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1992897078 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:53 PM PDT 24 87991613 ps
T3181 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.674517068 Aug 07 04:58:57 PM PDT 24 Aug 07 04:58:58 PM PDT 24 103087195 ps
T3182 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1731818961 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:53 PM PDT 24 232474023 ps
T3183 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.256984840 Aug 07 04:59:23 PM PDT 24 Aug 07 04:59:26 PM PDT 24 505509144 ps
T3184 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2499455929 Aug 07 04:59:20 PM PDT 24 Aug 07 04:59:21 PM PDT 24 166959588 ps
T3185 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.960775264 Aug 07 04:59:31 PM PDT 24 Aug 07 04:59:31 PM PDT 24 49213425 ps
T3186 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2961392789 Aug 07 04:58:45 PM PDT 24 Aug 07 04:58:51 PM PDT 24 73647538 ps
T3187 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1628937970 Aug 07 04:59:32 PM PDT 24 Aug 07 04:59:33 PM PDT 24 37175191 ps
T3188 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4153414145 Aug 07 04:58:53 PM PDT 24 Aug 07 04:58:54 PM PDT 24 97423829 ps
T3189 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.310138811 Aug 07 04:59:04 PM PDT 24 Aug 07 04:59:06 PM PDT 24 190988193 ps
T3190 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.4031525348 Aug 07 04:59:19 PM PDT 24 Aug 07 04:59:20 PM PDT 24 38802030 ps
T3191 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.372084690 Aug 07 04:59:14 PM PDT 24 Aug 07 04:59:16 PM PDT 24 605208343 ps
T3192 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3974750931 Aug 07 04:59:12 PM PDT 24 Aug 07 04:59:13 PM PDT 24 85003550 ps
T3193 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.698186374 Aug 07 04:59:00 PM PDT 24 Aug 07 04:59:04 PM PDT 24 309515883 ps
T3194 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3205629462 Aug 07 04:59:07 PM PDT 24 Aug 07 04:59:08 PM PDT 24 122712238 ps
T3195 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1331807533 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:58 PM PDT 24 202581844 ps
T335 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.4035995778 Aug 07 04:59:15 PM PDT 24 Aug 07 04:59:18 PM PDT 24 472787277 ps
T3196 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1498222477 Aug 07 04:58:57 PM PDT 24 Aug 07 04:58:58 PM PDT 24 48397860 ps
T283 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2866738277 Aug 07 04:58:44 PM PDT 24 Aug 07 04:58:47 PM PDT 24 179231093 ps
T3197 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3942492702 Aug 07 04:59:10 PM PDT 24 Aug 07 04:59:11 PM PDT 24 356143491 ps
T3198 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3107277559 Aug 07 04:58:50 PM PDT 24 Aug 07 04:58:54 PM PDT 24 933802834 ps
T3199 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2161512865 Aug 07 04:59:21 PM PDT 24 Aug 07 04:59:23 PM PDT 24 71202844 ps
T3200 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3889281258 Aug 07 04:59:09 PM PDT 24 Aug 07 04:59:10 PM PDT 24 69043379 ps
T3201 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.634636612 Aug 07 04:58:48 PM PDT 24 Aug 07 04:58:49 PM PDT 24 101198588 ps
T3202 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1152663849 Aug 07 04:59:05 PM PDT 24 Aug 07 04:59:06 PM PDT 24 101280091 ps
T3203 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3484402544 Aug 07 04:58:59 PM PDT 24 Aug 07 04:59:00 PM PDT 24 51917483 ps
T3204 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2334587002 Aug 07 04:59:12 PM PDT 24 Aug 07 04:59:15 PM PDT 24 681114734 ps
T284 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2444440659 Aug 07 04:59:00 PM PDT 24 Aug 07 04:59:01 PM PDT 24 107196830 ps
T3205 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4160978814 Aug 07 04:59:07 PM PDT 24 Aug 07 04:59:08 PM PDT 24 58597299 ps
T3206 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4175201109 Aug 07 04:59:08 PM PDT 24 Aug 07 04:59:10 PM PDT 24 173785822 ps
T3207 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1552654767 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:54 PM PDT 24 93441510 ps
T3208 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2108154730 Aug 07 04:58:52 PM PDT 24 Aug 07 04:58:56 PM PDT 24 476699953 ps
T3209 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1392576260 Aug 07 04:59:10 PM PDT 24 Aug 07 04:59:11 PM PDT 24 52113924 ps
T3210 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.659453701 Aug 07 04:58:54 PM PDT 24 Aug 07 04:58:56 PM PDT 24 171914203 ps
T3211 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.416124807 Aug 07 04:59:09 PM PDT 24 Aug 07 04:59:12 PM PDT 24 524128359 ps
T3212 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4187239753 Aug 07 04:59:24 PM PDT 24 Aug 07 04:59:25 PM PDT 24 45922809 ps
T3213 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3015635791 Aug 07 04:59:07 PM PDT 24 Aug 07 04:59:11 PM PDT 24 705474292 ps
T3214 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1501616364 Aug 07 04:59:20 PM PDT 24 Aug 07 04:59:21 PM PDT 24 39319194 ps
T3215 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1719947289 Aug 07 04:59:20 PM PDT 24 Aug 07 04:59:21 PM PDT 24 129713590 ps
T3216 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3185190340 Aug 07 04:58:52 PM PDT 24 Aug 07 04:58:53 PM PDT 24 99472022 ps
T3217 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1911537093 Aug 07 04:59:21 PM PDT 24 Aug 07 04:59:22 PM PDT 24 53535142 ps
T286 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3587989845 Aug 07 04:58:58 PM PDT 24 Aug 07 04:58:58 PM PDT 24 46014988 ps
T3218 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4160033709 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:52 PM PDT 24 72152265 ps
T3219 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.4028652799 Aug 07 04:59:20 PM PDT 24 Aug 07 04:59:21 PM PDT 24 55690457 ps
T3220 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3400241060 Aug 07 04:59:19 PM PDT 24 Aug 07 04:59:19 PM PDT 24 37305141 ps
T287 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1019271003 Aug 07 04:58:50 PM PDT 24 Aug 07 04:58:52 PM PDT 24 88616354 ps
T3221 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2075449801 Aug 07 04:59:12 PM PDT 24 Aug 07 04:59:13 PM PDT 24 127138301 ps
T3222 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3410144794 Aug 07 04:59:02 PM PDT 24 Aug 07 04:59:08 PM PDT 24 1723323068 ps
T336 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.743331240 Aug 07 04:58:52 PM PDT 24 Aug 07 04:58:55 PM PDT 24 520588828 ps
T3223 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3999082836 Aug 07 04:58:55 PM PDT 24 Aug 07 04:58:57 PM PDT 24 140307792 ps
T3224 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1692220679 Aug 07 04:59:08 PM PDT 24 Aug 07 04:59:09 PM PDT 24 97051928 ps
T3225 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3088368358 Aug 07 04:58:55 PM PDT 24 Aug 07 04:58:57 PM PDT 24 233212083 ps
T3226 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2786348049 Aug 07 04:59:31 PM PDT 24 Aug 07 04:59:33 PM PDT 24 136584659 ps
T3227 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1685503227 Aug 07 04:58:50 PM PDT 24 Aug 07 04:58:51 PM PDT 24 33814802 ps
T3228 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2597132792 Aug 07 04:59:15 PM PDT 24 Aug 07 04:59:18 PM PDT 24 100012296 ps
T3229 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3377100768 Aug 07 04:58:48 PM PDT 24 Aug 07 04:58:49 PM PDT 24 115065410 ps
T3230 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.667151871 Aug 07 04:59:14 PM PDT 24 Aug 07 04:59:15 PM PDT 24 70161056 ps
T3231 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1696326496 Aug 07 04:59:16 PM PDT 24 Aug 07 04:59:21 PM PDT 24 41148646 ps
T3232 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1002591593 Aug 07 04:59:04 PM PDT 24 Aug 07 04:59:06 PM PDT 24 264189269 ps

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.1538642781
Short name T4
Test name
Test status
Simulation time 1849468173 ps
CPU time 52.99 seconds
Started Aug 07 06:00:49 PM PDT 24
Finished Aug 07 06:01:42 PM PDT 24
Peak memory 216904 kb
Host smart-71eafe37-c3db-4088-bdad-8a0600f4cc7b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1538642781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.1538642781
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3141745143
Short name T7
Test name
Test status
Simulation time 14503784087 ps
CPU time 15.68 seconds
Started Aug 07 06:01:14 PM PDT 24
Finished Aug 07 06:01:30 PM PDT 24
Peak memory 215480 kb
Host smart-a846b2fc-ae62-4cbf-9eea-a2215277fefb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141745143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3141745143
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_device_address.950124214
Short name T86
Test name
Test status
Simulation time 26379368084 ps
CPU time 45.79 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 207344 kb
Host smart-fbddb3a7-9ef8-458f-83c7-e70b7656ca61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95012
4214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.950124214
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3979269717
Short name T331
Test name
Test status
Simulation time 49482704 ps
CPU time 0.69 seconds
Started Aug 07 04:58:49 PM PDT 24
Finished Aug 07 04:58:50 PM PDT 24
Peak memory 206416 kb
Host smart-090ae010-2c45-4f0d-b2df-f12940d1a6bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3979269717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3979269717
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2165926624
Short name T6
Test name
Test status
Simulation time 3027561127 ps
CPU time 90.5 seconds
Started Aug 07 06:00:04 PM PDT 24
Finished Aug 07 06:01:37 PM PDT 24
Peak memory 217540 kb
Host smart-7608945a-2059-4507-a2fc-0e10ab72e278
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2165926624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2165926624
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.351727125
Short name T216
Test name
Test status
Simulation time 100141858 ps
CPU time 1.46 seconds
Started Aug 07 04:58:57 PM PDT 24
Finished Aug 07 04:58:59 PM PDT 24
Peak memory 214976 kb
Host smart-b7c063ec-3259-43c9-b862-d6142a4c8804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351727125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.351727125
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.982467161
Short name T9
Test name
Test status
Simulation time 11366945113 ps
CPU time 14.11 seconds
Started Aug 07 06:03:52 PM PDT 24
Finished Aug 07 06:04:06 PM PDT 24
Peak memory 207164 kb
Host smart-b8553f5e-85c6-4653-8c7c-ef165323d7d4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982467161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_ao
n_wake_disconnect.982467161
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.4121422785
Short name T108
Test name
Test status
Simulation time 6575454558 ps
CPU time 8.4 seconds
Started Aug 07 06:12:27 PM PDT 24
Finished Aug 07 06:12:36 PM PDT 24
Peak memory 207308 kb
Host smart-e8391f0c-135b-4e05-acb6-f91bd0d36560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41214
22785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.4121422785
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1365218115
Short name T84
Test name
Test status
Simulation time 524410928 ps
CPU time 1.63 seconds
Started Aug 07 06:01:41 PM PDT 24
Finished Aug 07 06:01:43 PM PDT 24
Peak memory 206992 kb
Host smart-43e9e79f-f527-4384-a032-80337e71dbb9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1365218115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1365218115
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.274002703
Short name T212
Test name
Test status
Simulation time 441739796 ps
CPU time 1.33 seconds
Started Aug 07 05:58:41 PM PDT 24
Finished Aug 07 05:58:42 PM PDT 24
Peak memory 223056 kb
Host smart-72ff2c67-45c6-4aa3-9070-36bc723f7b78
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=274002703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.274002703
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1487244508
Short name T106
Test name
Test status
Simulation time 297270840 ps
CPU time 1.09 seconds
Started Aug 07 05:58:07 PM PDT 24
Finished Aug 07 05:58:09 PM PDT 24
Peak memory 206948 kb
Host smart-8b5e84ed-8abc-435b-b7ca-67152401f407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14872
44508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.1487244508
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3027204767
Short name T225
Test name
Test status
Simulation time 42665429 ps
CPU time 0.78 seconds
Started Aug 07 04:59:15 PM PDT 24
Finished Aug 07 04:59:16 PM PDT 24
Peak memory 206384 kb
Host smart-c6c865d2-6b8f-4c5e-ac18-b1a726e0195c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3027204767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3027204767
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2166391197
Short name T25
Test name
Test status
Simulation time 72409358 ps
CPU time 0.7 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:00:58 PM PDT 24
Peak memory 206828 kb
Host smart-666bbdf4-b47b-4ce7-a04f-1aa01106cb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21663
91197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2166391197
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1139694550
Short name T30
Test name
Test status
Simulation time 8979123178 ps
CPU time 20.61 seconds
Started Aug 07 06:01:05 PM PDT 24
Finished Aug 07 06:01:25 PM PDT 24
Peak memory 215564 kb
Host smart-26b6ec04-7474-4a1a-8ece-3c1bc2bbd54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11396
94550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1139694550
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1319863551
Short name T12
Test name
Test status
Simulation time 19134038389 ps
CPU time 24.98 seconds
Started Aug 07 06:04:57 PM PDT 24
Finished Aug 07 06:05:22 PM PDT 24
Peak memory 207468 kb
Host smart-2ef26d30-e5ea-416a-809a-77f039cbef75
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319863551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1319863551
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1499701298
Short name T246
Test name
Test status
Simulation time 570817928 ps
CPU time 3.94 seconds
Started Aug 07 04:59:06 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 206824 kb
Host smart-080dfb96-3ca9-4d76-adda-aa2451fc05da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1499701298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1499701298
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2487321305
Short name T272
Test name
Test status
Simulation time 56310264 ps
CPU time 0.82 seconds
Started Aug 07 04:59:24 PM PDT 24
Finished Aug 07 04:59:25 PM PDT 24
Peak memory 206464 kb
Host smart-a321f046-2133-4419-ad49-c93bbb7b9e7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2487321305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2487321305
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1328537172
Short name T70
Test name
Test status
Simulation time 11096148083 ps
CPU time 225.61 seconds
Started Aug 07 05:59:41 PM PDT 24
Finished Aug 07 06:03:26 PM PDT 24
Peak memory 223680 kb
Host smart-5f55de72-aa11-4eb9-9e9f-dc9252a11509
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328537172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1328537172
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.885609426
Short name T756
Test name
Test status
Simulation time 28489412990 ps
CPU time 33.58 seconds
Started Aug 07 06:08:04 PM PDT 24
Finished Aug 07 06:08:38 PM PDT 24
Peak memory 207280 kb
Host smart-56d996f1-9534-4970-8216-9d06c0fc2492
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885609426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ao
n_wake_resume.885609426
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.3154052664
Short name T779
Test name
Test status
Simulation time 5238065236 ps
CPU time 8.61 seconds
Started Aug 07 06:01:17 PM PDT 24
Finished Aug 07 06:01:26 PM PDT 24
Peak memory 215664 kb
Host smart-c29a3c6c-8632-4af3-802d-47be746db173
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154052664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.3154052664
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_device_address.547427641
Short name T198
Test name
Test status
Simulation time 53125907426 ps
CPU time 76.55 seconds
Started Aug 07 06:02:08 PM PDT 24
Finished Aug 07 06:03:25 PM PDT 24
Peak memory 207316 kb
Host smart-a53132f9-77ce-45fd-8052-ed7fb23879a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54742
7641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.547427641
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_rx_full.1663157731
Short name T49
Test name
Test status
Simulation time 291227932 ps
CPU time 1.16 seconds
Started Aug 07 06:09:21 PM PDT 24
Finished Aug 07 06:09:22 PM PDT 24
Peak memory 207008 kb
Host smart-a92f579a-3a30-4667-9368-a861ef985a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16631
57731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.1663157731
Directory /workspace/38.usbdev_rx_full/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1677447004
Short name T252
Test name
Test status
Simulation time 94231633 ps
CPU time 2.44 seconds
Started Aug 07 04:58:53 PM PDT 24
Finished Aug 07 04:58:55 PM PDT 24
Peak memory 206712 kb
Host smart-18b3951f-040c-4c76-945d-340c784b317e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1677447004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1677447004
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/82.usbdev_endpoint_types.1282612622
Short name T81
Test name
Test status
Simulation time 726812755 ps
CPU time 1.73 seconds
Started Aug 07 06:12:53 PM PDT 24
Finished Aug 07 06:12:55 PM PDT 24
Peak memory 206992 kb
Host smart-af163651-aa50-499d-95c2-8af01a1bc969
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1282612622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.1282612622
Directory /workspace/82.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/93.usbdev_endpoint_types.1931663210
Short name T325
Test name
Test status
Simulation time 890008053 ps
CPU time 2.01 seconds
Started Aug 07 06:12:50 PM PDT 24
Finished Aug 07 06:12:53 PM PDT 24
Peak memory 206976 kb
Host smart-eb39b782-1144-4ffa-bd12-626bbd4a9df2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1931663210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.1931663210
Directory /workspace/93.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/168.usbdev_endpoint_types.339259306
Short name T384
Test name
Test status
Simulation time 631870556 ps
CPU time 1.49 seconds
Started Aug 07 06:13:13 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206976 kb
Host smart-e84173d7-8cb2-4bf3-80c4-01b927f3465d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=339259306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.339259306
Directory /workspace/168.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.937432881
Short name T489
Test name
Test status
Simulation time 145964016 ps
CPU time 0.81 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:00:10 PM PDT 24
Peak memory 206888 kb
Host smart-de510dad-ffd5-43b0-bf96-63cdd6233e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93743
2881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.937432881
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/58.usbdev_endpoint_types.884646654
Short name T411
Test name
Test status
Simulation time 749898067 ps
CPU time 1.75 seconds
Started Aug 07 06:12:42 PM PDT 24
Finished Aug 07 06:12:44 PM PDT 24
Peak memory 206948 kb
Host smart-e52f3689-82c3-400b-988a-8413117e2f85
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=884646654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.884646654
Directory /workspace/58.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3073462115
Short name T333
Test name
Test status
Simulation time 94855656 ps
CPU time 0.82 seconds
Started Aug 07 04:59:10 PM PDT 24
Finished Aug 07 04:59:11 PM PDT 24
Peak memory 206416 kb
Host smart-cf5fe793-a5da-492a-b691-83fd993a0fe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3073462115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3073462115
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/default/133.usbdev_endpoint_types.572478140
Short name T358
Test name
Test status
Simulation time 928053768 ps
CPU time 1.87 seconds
Started Aug 07 06:13:08 PM PDT 24
Finished Aug 07 06:13:10 PM PDT 24
Peak memory 206960 kb
Host smart-849c420c-6409-4dbe-931f-87952dc1881a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=572478140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.572478140
Directory /workspace/133.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/164.usbdev_endpoint_types.1688472583
Short name T370
Test name
Test status
Simulation time 807581137 ps
CPU time 1.83 seconds
Started Aug 07 06:13:10 PM PDT 24
Finished Aug 07 06:13:12 PM PDT 24
Peak memory 206972 kb
Host smart-aa11426d-f7c8-4139-bc0e-b1937ee5b64a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1688472583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.1688472583
Directory /workspace/164.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.331242159
Short name T932
Test name
Test status
Simulation time 164916349 ps
CPU time 0.87 seconds
Started Aug 07 06:01:37 PM PDT 24
Finished Aug 07 06:01:38 PM PDT 24
Peak memory 206900 kb
Host smart-8d152652-b645-488b-a0d0-41de54308456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33124
2159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.331242159
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.265801885
Short name T37
Test name
Test status
Simulation time 141590105 ps
CPU time 0.82 seconds
Started Aug 07 06:01:50 PM PDT 24
Finished Aug 07 06:01:51 PM PDT 24
Peak memory 206960 kb
Host smart-49ed3dd9-5096-4ada-ae78-71b502b9d3a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26580
1885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.265801885
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1053727591
Short name T29
Test name
Test status
Simulation time 455249750 ps
CPU time 1.54 seconds
Started Aug 07 05:59:20 PM PDT 24
Finished Aug 07 05:59:22 PM PDT 24
Peak memory 206960 kb
Host smart-b40e3ee9-ad45-40cb-82d6-8f97b5e04a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10537
27591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1053727591
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_types.772229717
Short name T401
Test name
Test status
Simulation time 563111391 ps
CPU time 1.48 seconds
Started Aug 07 06:01:52 PM PDT 24
Finished Aug 07 06:01:54 PM PDT 24
Peak memory 206968 kb
Host smart-1f5c468f-46e2-4d61-b5e6-44ac86ffd673
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=772229717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.772229717
Directory /workspace/15.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.406464899
Short name T341
Test name
Test status
Simulation time 187430842 ps
CPU time 0.94 seconds
Started Aug 07 06:02:34 PM PDT 24
Finished Aug 07 06:02:35 PM PDT 24
Peak memory 206896 kb
Host smart-9034291d-5a5c-4e4e-becc-513a1658e676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40646
4899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.406464899
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.3200923784
Short name T166
Test name
Test status
Simulation time 3877719126 ps
CPU time 110.46 seconds
Started Aug 07 06:09:37 PM PDT 24
Finished Aug 07 06:11:28 PM PDT 24
Peak memory 218104 kb
Host smart-32dac96d-2ca7-4a9f-9970-b006abb78bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32009
23784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.3200923784
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/154.usbdev_endpoint_types.1979198907
Short name T448
Test name
Test status
Simulation time 475291440 ps
CPU time 1.46 seconds
Started Aug 07 06:13:10 PM PDT 24
Finished Aug 07 06:13:12 PM PDT 24
Peak memory 206876 kb
Host smart-f5f0e568-865d-4e34-a8ba-5b5097485d98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1979198907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.1979198907
Directory /workspace/154.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_types.1279475880
Short name T390
Test name
Test status
Simulation time 567859460 ps
CPU time 1.52 seconds
Started Aug 07 06:06:12 PM PDT 24
Finished Aug 07 06:06:14 PM PDT 24
Peak memory 206948 kb
Host smart-fb160a28-4b74-4e2c-bc1c-2bcd56e66d1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1279475880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.1279475880
Directory /workspace/33.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/67.usbdev_endpoint_types.1281997464
Short name T320
Test name
Test status
Simulation time 395580962 ps
CPU time 1.32 seconds
Started Aug 07 06:12:51 PM PDT 24
Finished Aug 07 06:12:53 PM PDT 24
Peak memory 206976 kb
Host smart-66eb9133-2ada-4227-8527-f7ae4c4a62f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1281997464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.1281997464
Directory /workspace/67.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/150.usbdev_endpoint_types.1853409398
Short name T374
Test name
Test status
Simulation time 621237416 ps
CPU time 1.51 seconds
Started Aug 07 06:13:09 PM PDT 24
Finished Aug 07 06:13:11 PM PDT 24
Peak memory 206988 kb
Host smart-4a33b57e-0093-483f-96a0-8644776bbda7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1853409398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.1853409398
Directory /workspace/150.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_types.4198665890
Short name T348
Test name
Test status
Simulation time 720101829 ps
CPU time 1.93 seconds
Started Aug 07 06:12:03 PM PDT 24
Finished Aug 07 06:12:05 PM PDT 24
Peak memory 206864 kb
Host smart-b25b4f3d-147a-429e-8da4-7a566e8622d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4198665890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.4198665890
Directory /workspace/47.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/117.usbdev_endpoint_types.800506906
Short name T344
Test name
Test status
Simulation time 901872018 ps
CPU time 1.79 seconds
Started Aug 07 06:13:01 PM PDT 24
Finished Aug 07 06:13:03 PM PDT 24
Peak memory 206976 kb
Host smart-07829eef-b0c5-41c3-8b4d-7b3d2a972ab0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=800506906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.800506906
Directory /workspace/117.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/149.usbdev_endpoint_types.2166370597
Short name T351
Test name
Test status
Simulation time 651274115 ps
CPU time 1.5 seconds
Started Aug 07 06:13:10 PM PDT 24
Finished Aug 07 06:13:11 PM PDT 24
Peak memory 206980 kb
Host smart-aa967c48-2a18-414a-9573-b59d2fde30c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2166370597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.2166370597
Directory /workspace/149.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/157.usbdev_endpoint_types.1787832408
Short name T2341
Test name
Test status
Simulation time 581303058 ps
CPU time 1.46 seconds
Started Aug 07 06:13:17 PM PDT 24
Finished Aug 07 06:13:19 PM PDT 24
Peak memory 206960 kb
Host smart-841198e3-f4fb-4252-b3e1-7499a1c1a4aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1787832408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.1787832408
Directory /workspace/157.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/167.usbdev_endpoint_types.2341010389
Short name T3019
Test name
Test status
Simulation time 557609033 ps
CPU time 1.43 seconds
Started Aug 07 06:13:11 PM PDT 24
Finished Aug 07 06:13:13 PM PDT 24
Peak memory 206928 kb
Host smart-7447d111-d68b-4f69-80b9-99dadbedaf8f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2341010389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.2341010389
Directory /workspace/167.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/87.usbdev_endpoint_types.726918672
Short name T324
Test name
Test status
Simulation time 357855826 ps
CPU time 1.19 seconds
Started Aug 07 06:12:50 PM PDT 24
Finished Aug 07 06:12:52 PM PDT 24
Peak memory 206880 kb
Host smart-b6351fff-feaa-4144-b5c0-7444c2c8eceb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=726918672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.726918672
Directory /workspace/87.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.82011278
Short name T551
Test name
Test status
Simulation time 113108043 ps
CPU time 0.75 seconds
Started Aug 07 06:01:15 PM PDT 24
Finished Aug 07 06:01:16 PM PDT 24
Peak memory 207048 kb
Host smart-6995f600-3774-4bc4-b4b6-74b466c63591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=82011278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.82011278
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_device_address.567211032
Short name T484
Test name
Test status
Simulation time 47161316804 ps
CPU time 72.97 seconds
Started Aug 07 06:12:29 PM PDT 24
Finished Aug 07 06:13:42 PM PDT 24
Peak memory 207264 kb
Host smart-12981e10-e72b-4d15-89a5-6546be00ac84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56721
1032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.567211032
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3367382291
Short name T241
Test name
Test status
Simulation time 303510005 ps
CPU time 2.49 seconds
Started Aug 07 04:59:04 PM PDT 24
Finished Aug 07 04:59:06 PM PDT 24
Peak memory 206808 kb
Host smart-88745126-e968-40b0-bbee-3633f08e0fdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3367382291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3367382291
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_types.786535974
Short name T450
Test name
Test status
Simulation time 740220998 ps
CPU time 1.82 seconds
Started Aug 07 06:01:04 PM PDT 24
Finished Aug 07 06:01:06 PM PDT 24
Peak memory 206932 kb
Host smart-e9caf4ee-5aa6-4999-9f78-32977e9afefb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=786535974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.786535974
Directory /workspace/11.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/120.usbdev_endpoint_types.1247638900
Short name T3075
Test name
Test status
Simulation time 569285659 ps
CPU time 1.44 seconds
Started Aug 07 06:13:03 PM PDT 24
Finished Aug 07 06:13:05 PM PDT 24
Peak memory 206996 kb
Host smart-d8feb24b-ccc8-4a59-86ee-8bc86cddf479
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1247638900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.1247638900
Directory /workspace/120.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_types.854708420
Short name T452
Test name
Test status
Simulation time 562509692 ps
CPU time 1.47 seconds
Started Aug 07 06:02:49 PM PDT 24
Finished Aug 07 06:02:51 PM PDT 24
Peak memory 206948 kb
Host smart-1dc9652a-74bd-47b9-91af-7b5e948f19fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=854708420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.854708420
Directory /workspace/21.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_types.1838095605
Short name T468
Test name
Test status
Simulation time 560339488 ps
CPU time 1.55 seconds
Started Aug 07 05:59:51 PM PDT 24
Finished Aug 07 05:59:53 PM PDT 24
Peak memory 206928 kb
Host smart-0d4d8e84-54a8-4125-a399-73a6ec7e0548
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1838095605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.1838095605
Directory /workspace/5.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3364784407
Short name T3163
Test name
Test status
Simulation time 110040602 ps
CPU time 2.73 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 206720 kb
Host smart-a56a27fd-b067-4576-b23c-149871107e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3364784407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3364784407
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2181840193
Short name T184
Test name
Test status
Simulation time 2924889634 ps
CPU time 69.79 seconds
Started Aug 07 05:58:16 PM PDT 24
Finished Aug 07 05:59:26 PM PDT 24
Peak memory 223680 kb
Host smart-67c27dda-15d9-4fe4-bf72-ad4fbc58a78e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181840193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2181840193
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.3607878977
Short name T68
Test name
Test status
Simulation time 545322974 ps
CPU time 1.6 seconds
Started Aug 07 05:57:51 PM PDT 24
Finished Aug 07 05:57:53 PM PDT 24
Peak memory 206960 kb
Host smart-287509d7-4c8e-4c3f-804d-42eff827f04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36078
78977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.3607878977
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1991027840
Short name T230
Test name
Test status
Simulation time 637213149 ps
CPU time 1.46 seconds
Started Aug 07 05:58:21 PM PDT 24
Finished Aug 07 05:58:22 PM PDT 24
Peak memory 224016 kb
Host smart-1f80c993-2263-4590-8d01-af6185397545
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1991027840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1991027840
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3259222094
Short name T103
Test name
Test status
Simulation time 162593076 ps
CPU time 0.89 seconds
Started Aug 07 05:57:46 PM PDT 24
Finished Aug 07 05:57:47 PM PDT 24
Peak memory 206980 kb
Host smart-85f5d8ee-f86d-4f9c-a569-f4e1f2160d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32592
22094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3259222094
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.207164926
Short name T337
Test name
Test status
Simulation time 760820683 ps
CPU time 4.34 seconds
Started Aug 07 04:58:45 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 206712 kb
Host smart-cbdca029-7564-4b71-8f48-589836c0cd11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=207164926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.207164926
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.497626947
Short name T308
Test name
Test status
Simulation time 63677404 ps
CPU time 0.72 seconds
Started Aug 07 04:59:21 PM PDT 24
Finished Aug 07 04:59:22 PM PDT 24
Peak memory 206396 kb
Host smart-835159c5-7663-439c-a1c1-3fd79b68a517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=497626947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.497626947
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.3041380195
Short name T329
Test name
Test status
Simulation time 119398066993 ps
CPU time 205.96 seconds
Started Aug 07 05:58:25 PM PDT 24
Finished Aug 07 06:01:51 PM PDT 24
Peak memory 207332 kb
Host smart-0de9c2f8-20e0-4fac-89d4-24f0f3773f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041380195 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.3041380195
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/111.usbdev_endpoint_types.1096496593
Short name T406
Test name
Test status
Simulation time 298758974 ps
CPU time 1.13 seconds
Started Aug 07 06:13:03 PM PDT 24
Finished Aug 07 06:13:04 PM PDT 24
Peak memory 206928 kb
Host smart-bf334fab-615b-403c-a8de-09fe54b9bdfb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1096496593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.1096496593
Directory /workspace/111.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/119.usbdev_endpoint_types.3669450071
Short name T2140
Test name
Test status
Simulation time 401294331 ps
CPU time 1.37 seconds
Started Aug 07 06:13:03 PM PDT 24
Finished Aug 07 06:13:04 PM PDT 24
Peak memory 207012 kb
Host smart-56ca1c47-0fe4-4215-81b8-6ccc051caa93
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3669450071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.3669450071
Directory /workspace/119.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/143.usbdev_endpoint_types.3250436386
Short name T413
Test name
Test status
Simulation time 547266033 ps
CPU time 1.62 seconds
Started Aug 07 06:13:14 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206984 kb
Host smart-63e3df8e-9ec0-4238-b112-cf09f89102f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3250436386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.3250436386
Directory /workspace/143.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_types.2510263409
Short name T425
Test name
Test status
Simulation time 600745712 ps
CPU time 1.62 seconds
Started Aug 07 06:02:05 PM PDT 24
Finished Aug 07 06:02:07 PM PDT 24
Peak memory 206928 kb
Host smart-90e6cef3-f967-4962-9e5a-1e3a4767703d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2510263409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.2510263409
Directory /workspace/16.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_types.2600068574
Short name T355
Test name
Test status
Simulation time 702436399 ps
CPU time 1.64 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:02:21 PM PDT 24
Peak memory 207004 kb
Host smart-448f6138-12fe-48a2-b683-0c1022cc3871
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2600068574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.2600068574
Directory /workspace/18.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/187.usbdev_endpoint_types.13580604
Short name T435
Test name
Test status
Simulation time 890269678 ps
CPU time 1.88 seconds
Started Aug 07 06:13:19 PM PDT 24
Finished Aug 07 06:13:21 PM PDT 24
Peak memory 206952 kb
Host smart-24c4802d-29fb-4a33-8b89-bfc49d4180c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=13580604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.13580604
Directory /workspace/187.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_types.3588731705
Short name T343
Test name
Test status
Simulation time 595423566 ps
CPU time 1.62 seconds
Started Aug 07 06:08:55 PM PDT 24
Finished Aug 07 06:08:57 PM PDT 24
Peak memory 206880 kb
Host smart-eb6d60c5-5092-4c82-be07-e4c9d965216a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3588731705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.3588731705
Directory /workspace/38.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/85.usbdev_endpoint_types.3490289541
Short name T470
Test name
Test status
Simulation time 741423985 ps
CPU time 2.02 seconds
Started Aug 07 06:12:55 PM PDT 24
Finished Aug 07 06:12:57 PM PDT 24
Peak memory 206952 kb
Host smart-7e0f83eb-09f6-4947-8510-3241b25f55b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3490289541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.3490289541
Directory /workspace/85.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2429835507
Short name T82
Test name
Test status
Simulation time 12397982857 ps
CPU time 66.1 seconds
Started Aug 07 05:59:18 PM PDT 24
Finished Aug 07 06:00:24 PM PDT 24
Peak memory 223676 kb
Host smart-c4931db2-1c9d-4a2a-8369-80b422c8a426
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429835507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2429835507
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_device_address.1959558343
Short name T90
Test name
Test status
Simulation time 43093805839 ps
CPU time 62.49 seconds
Started Aug 07 06:06:13 PM PDT 24
Finished Aug 07 06:07:15 PM PDT 24
Peak memory 207376 kb
Host smart-ae971c6b-b780-4ff7-83b1-14e4235fc203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19595
58343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1959558343
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2507721271
Short name T258
Test name
Test status
Simulation time 605376013 ps
CPU time 4.35 seconds
Started Aug 07 04:59:23 PM PDT 24
Finished Aug 07 04:59:28 PM PDT 24
Peak memory 206576 kb
Host smart-b98d9343-96fa-4a15-80ad-65eb5be7b184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2507721271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2507721271
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1032079580
Short name T200
Test name
Test status
Simulation time 47673332887 ps
CPU time 69.64 seconds
Started Aug 07 06:04:41 PM PDT 24
Finished Aug 07 06:05:51 PM PDT 24
Peak memory 207324 kb
Host smart-3d249c1c-6bb1-40cf-987b-6da0c6621ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10320
79580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1032079580
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2143453349
Short name T217
Test name
Test status
Simulation time 97585561 ps
CPU time 2.41 seconds
Started Aug 07 04:59:14 PM PDT 24
Finished Aug 07 04:59:17 PM PDT 24
Peak memory 215032 kb
Host smart-3d96afa6-6d7e-4890-ba44-80fb9bb5be78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143453349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2143453349
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2414976391
Short name T23
Test name
Test status
Simulation time 46930904 ps
CPU time 0.71 seconds
Started Aug 07 06:01:55 PM PDT 24
Finished Aug 07 06:01:56 PM PDT 24
Peak memory 206984 kb
Host smart-167ee3a4-365c-4a49-a937-d05b28b0c32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24149
76391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2414976391
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.2419433686
Short name T122
Test name
Test status
Simulation time 3220007488 ps
CPU time 89.35 seconds
Started Aug 07 06:00:13 PM PDT 24
Finished Aug 07 06:01:42 PM PDT 24
Peak memory 215480 kb
Host smart-80969493-df09-4f80-80a1-686dd9359668
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2419433686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.2419433686
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.743331240
Short name T336
Test name
Test status
Simulation time 520588828 ps
CPU time 3.08 seconds
Started Aug 07 04:58:52 PM PDT 24
Finished Aug 07 04:58:55 PM PDT 24
Peak memory 206740 kb
Host smart-c3b42426-6d3b-4a8a-8aa7-ff0dd67ac235
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=743331240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.743331240
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4138662699
Short name T3147
Test name
Test status
Simulation time 60827705 ps
CPU time 0.72 seconds
Started Aug 07 04:58:52 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 206368 kb
Host smart-fb3e68a8-b7f5-4524-add1-0977168e3330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4138662699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.4138662699
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_types.3320637313
Short name T418
Test name
Test status
Simulation time 484886750 ps
CPU time 1.36 seconds
Started Aug 07 05:57:51 PM PDT 24
Finished Aug 07 05:57:52 PM PDT 24
Peak memory 206932 kb
Host smart-f7e3fe9a-35df-497d-8b3c-68cfef1a99b4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3320637313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.3320637313
Directory /workspace/0.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.4060702684
Short name T315
Test name
Test status
Simulation time 160232845 ps
CPU time 0.83 seconds
Started Aug 07 05:58:17 PM PDT 24
Finished Aug 07 05:58:17 PM PDT 24
Peak memory 206988 kb
Host smart-08131c4e-d04d-4835-beda-d102ab897436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40607
02684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.4060702684
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.4124857273
Short name T716
Test name
Test status
Simulation time 199564054 ps
CPU time 0.97 seconds
Started Aug 07 05:58:41 PM PDT 24
Finished Aug 07 05:58:42 PM PDT 24
Peak memory 206980 kb
Host smart-22e38044-5021-403d-aded-fdb1c401504f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41248
57273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.4124857273
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1900495278
Short name T491
Test name
Test status
Simulation time 3861611887 ps
CPU time 28.42 seconds
Started Aug 07 06:00:54 PM PDT 24
Finished Aug 07 06:01:22 PM PDT 24
Peak memory 207248 kb
Host smart-30845a27-08d8-4f24-8b99-1a777d194d75
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1900495278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1900495278
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/124.usbdev_endpoint_types.4213496369
Short name T2673
Test name
Test status
Simulation time 256052232 ps
CPU time 1.04 seconds
Started Aug 07 06:13:01 PM PDT 24
Finished Aug 07 06:13:02 PM PDT 24
Peak memory 206884 kb
Host smart-bff88fd8-8381-4b91-90b5-b147bc7094eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4213496369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.4213496369
Directory /workspace/124.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/128.usbdev_endpoint_types.794050085
Short name T424
Test name
Test status
Simulation time 382031488 ps
CPU time 1.21 seconds
Started Aug 07 06:13:07 PM PDT 24
Finished Aug 07 06:13:08 PM PDT 24
Peak memory 206960 kb
Host smart-022c9eab-3aab-47d2-8fe6-5d3b68649df8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=794050085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.794050085
Directory /workspace/128.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/137.usbdev_endpoint_types.984310941
Short name T394
Test name
Test status
Simulation time 478289736 ps
CPU time 1.28 seconds
Started Aug 07 06:13:09 PM PDT 24
Finished Aug 07 06:13:10 PM PDT 24
Peak memory 206976 kb
Host smart-72f9cecb-2306-42ee-b65d-fe1bc7e03823
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=984310941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.984310941
Directory /workspace/137.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/142.usbdev_endpoint_types.738663427
Short name T403
Test name
Test status
Simulation time 761226905 ps
CPU time 1.84 seconds
Started Aug 07 06:13:16 PM PDT 24
Finished Aug 07 06:13:18 PM PDT 24
Peak memory 207008 kb
Host smart-76e311b1-650a-44c0-ac15-71676144a4c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=738663427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.738663427
Directory /workspace/142.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/173.usbdev_endpoint_types.3653552178
Short name T1921
Test name
Test status
Simulation time 539164441 ps
CPU time 1.61 seconds
Started Aug 07 06:13:16 PM PDT 24
Finished Aug 07 06:13:18 PM PDT 24
Peak memory 207000 kb
Host smart-eb1c6943-5416-4471-9dfc-efe8746c09f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3653552178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.3653552178
Directory /workspace/173.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.3263790255
Short name T326
Test name
Test status
Simulation time 93154237439 ps
CPU time 147.98 seconds
Started Aug 07 05:58:48 PM PDT 24
Finished Aug 07 06:01:16 PM PDT 24
Peak memory 207312 kb
Host smart-09c64cd7-e527-4fdf-a363-f5797ba8f3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263790255 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.3263790255
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1489862975
Short name T28
Test name
Test status
Simulation time 90245996278 ps
CPU time 144.66 seconds
Started Aug 07 05:58:45 PM PDT 24
Finished Aug 07 06:01:10 PM PDT 24
Peak memory 207264 kb
Host smart-ee186867-3710-481d-aff1-77e964edaf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489862975 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1489862975
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/21.usbdev_rx_full.807629180
Short name T312
Test name
Test status
Simulation time 246809129 ps
CPU time 1.05 seconds
Started Aug 07 06:02:57 PM PDT 24
Finished Aug 07 06:02:58 PM PDT 24
Peak memory 206968 kb
Host smart-d6bd6b77-4548-476a-8c87-184b6c06e423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80762
9180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.807629180
Directory /workspace/21.usbdev_rx_full/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.994706314
Short name T493
Test name
Test status
Simulation time 3721888631 ps
CPU time 28.13 seconds
Started Aug 07 06:11:43 PM PDT 24
Finished Aug 07 06:12:11 PM PDT 24
Peak memory 215544 kb
Host smart-5c681a61-5c84-4806-aaf8-951e3e1492d6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=994706314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.994706314
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_rx_full.2967496170
Short name T314
Test name
Test status
Simulation time 402662676 ps
CPU time 1.49 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:12:27 PM PDT 24
Peak memory 207012 kb
Host smart-7995b32e-fed4-4351-a975-00989c8bfcc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29674
96170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.2967496170
Directory /workspace/48.usbdev_rx_full/latest

Test location /workspace/coverage/default/81.usbdev_endpoint_types.3843071804
Short name T446
Test name
Test status
Simulation time 450665617 ps
CPU time 1.4 seconds
Started Aug 07 06:12:57 PM PDT 24
Finished Aug 07 06:12:58 PM PDT 24
Peak memory 206956 kb
Host smart-adc37ef8-aac5-475e-a366-5b7dfec4f1f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3843071804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.3843071804
Directory /workspace/81.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1646110968
Short name T661
Test name
Test status
Simulation time 143673793 ps
CPU time 0.84 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:00:58 PM PDT 24
Peak memory 206672 kb
Host smart-99a4d883-17ed-4465-9485-23a18e0112c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16461
10968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1646110968
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.86657530
Short name T1590
Test name
Test status
Simulation time 28600154642 ps
CPU time 45.05 seconds
Started Aug 07 05:58:25 PM PDT 24
Finished Aug 07 05:59:11 PM PDT 24
Peak memory 207488 kb
Host smart-75c1aa82-04bc-4ec9-a0b9-1df958ffb93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86657
530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.86657530
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.468225947
Short name T133
Test name
Test status
Simulation time 166284423 ps
CPU time 0.87 seconds
Started Aug 07 06:01:09 PM PDT 24
Finished Aug 07 06:01:10 PM PDT 24
Peak memory 207016 kb
Host smart-e5d8c5c7-55f0-4d60-b931-0e736d907d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46822
5947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.468225947
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.3586412109
Short name T58
Test name
Test status
Simulation time 154287923 ps
CPU time 0.93 seconds
Started Aug 07 05:59:38 PM PDT 24
Finished Aug 07 05:59:39 PM PDT 24
Peak memory 206980 kb
Host smart-085b3b01-0ab3-49ed-b619-74d15967da7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35864
12109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.3586412109
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3292945238
Short name T54
Test name
Test status
Simulation time 150701438 ps
CPU time 0.82 seconds
Started Aug 07 05:57:45 PM PDT 24
Finished Aug 07 05:57:46 PM PDT 24
Peak memory 207016 kb
Host smart-4caf4c76-0ecc-4237-b923-fd32ec3abef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32929
45238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3292945238
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.481183451
Short name T62
Test name
Test status
Simulation time 4175149380 ps
CPU time 10.16 seconds
Started Aug 07 05:57:52 PM PDT 24
Finished Aug 07 05:58:03 PM PDT 24
Peak memory 207272 kb
Host smart-924a0ccb-8165-4cc9-9d7a-7f95c1118d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48118
3451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.481183451
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.105075364
Short name T63
Test name
Test status
Simulation time 202686120 ps
CPU time 0.92 seconds
Started Aug 07 05:57:56 PM PDT 24
Finished Aug 07 05:57:57 PM PDT 24
Peak memory 206892 kb
Host smart-27d69699-0e3a-44da-a179-9465c1273abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10507
5364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.105075364
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1110065696
Short name T78
Test name
Test status
Simulation time 195787731 ps
CPU time 0.88 seconds
Started Aug 07 05:58:14 PM PDT 24
Finished Aug 07 05:58:15 PM PDT 24
Peak memory 206956 kb
Host smart-06020b95-8a22-45fc-b6c0-2ea8d2e18c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11100
65696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1110065696
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.2132183601
Short name T42
Test name
Test status
Simulation time 173677697 ps
CPU time 0.94 seconds
Started Aug 07 05:58:23 PM PDT 24
Finished Aug 07 05:58:24 PM PDT 24
Peak memory 207196 kb
Host smart-1ecd2311-2418-4485-855c-8aaf086cf3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21321
83601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2132183601
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.4213007177
Short name T1108
Test name
Test status
Simulation time 13269842133 ps
CPU time 94.63 seconds
Started Aug 07 05:57:55 PM PDT 24
Finished Aug 07 05:59:30 PM PDT 24
Peak memory 207172 kb
Host smart-8179540a-1f2b-485b-958a-3bad07b92032
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4213007177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.4213007177
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.4039271685
Short name T156
Test name
Test status
Simulation time 231016370 ps
CPU time 1.03 seconds
Started Aug 07 05:58:09 PM PDT 24
Finished Aug 07 05:58:10 PM PDT 24
Peak memory 206964 kb
Host smart-ccb959fb-e74d-462f-83a3-2f30f343f93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40392
71685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.4039271685
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.517896880
Short name T2848
Test name
Test status
Simulation time 202062501 ps
CPU time 0.92 seconds
Started Aug 07 05:58:28 PM PDT 24
Finished Aug 07 05:58:29 PM PDT 24
Peak memory 207016 kb
Host smart-70e570a9-ace9-4915-87c4-65b8fc17d87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51789
6880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.517896880
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2058389021
Short name T791
Test name
Test status
Simulation time 283162520 ps
CPU time 1.98 seconds
Started Aug 07 06:00:55 PM PDT 24
Finished Aug 07 06:00:57 PM PDT 24
Peak memory 207204 kb
Host smart-fc76bd82-52e9-441f-b772-9b653c294d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20583
89021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2058389021
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.39717860
Short name T141
Test name
Test status
Simulation time 187913683 ps
CPU time 0.96 seconds
Started Aug 07 06:00:59 PM PDT 24
Finished Aug 07 06:01:00 PM PDT 24
Peak memory 206984 kb
Host smart-2104dd91-cc17-45da-b473-8cb667de5ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39717
860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.39717860
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.572265912
Short name T162
Test name
Test status
Simulation time 229291616 ps
CPU time 1.06 seconds
Started Aug 07 06:01:39 PM PDT 24
Finished Aug 07 06:01:40 PM PDT 24
Peak memory 207196 kb
Host smart-0a0cb43b-1a37-413a-bd3c-d2154906eca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57226
5912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.572265912
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2058827305
Short name T2950
Test name
Test status
Simulation time 198279559 ps
CPU time 0.98 seconds
Started Aug 07 06:01:42 PM PDT 24
Finished Aug 07 06:01:43 PM PDT 24
Peak memory 206948 kb
Host smart-e3128d8a-a1eb-4ddb-8034-bafe5154e3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20588
27305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2058827305
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3849847976
Short name T157
Test name
Test status
Simulation time 174589499 ps
CPU time 0.88 seconds
Started Aug 07 06:02:03 PM PDT 24
Finished Aug 07 06:02:04 PM PDT 24
Peak memory 207000 kb
Host smart-2c36c78a-08a2-4640-9ab9-6029c07aabeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38498
47976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3849847976
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2144659064
Short name T135
Test name
Test status
Simulation time 182376176 ps
CPU time 0.86 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:02:20 PM PDT 24
Peak memory 206984 kb
Host smart-df5c1c00-eb18-4b14-b8ec-f52b9e210a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21446
59064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2144659064
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2467230169
Short name T2145
Test name
Test status
Simulation time 203390552 ps
CPU time 1.02 seconds
Started Aug 07 06:02:58 PM PDT 24
Finished Aug 07 06:03:00 PM PDT 24
Peak memory 207012 kb
Host smart-a928ed0d-39d2-4751-b448-0e74911cc965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24672
30169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2467230169
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1453748923
Short name T138
Test name
Test status
Simulation time 220847191 ps
CPU time 0.91 seconds
Started Aug 07 06:04:04 PM PDT 24
Finished Aug 07 06:04:05 PM PDT 24
Peak memory 206980 kb
Host smart-3c990d13-116a-4fa2-92b2-02871a881ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14537
48923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1453748923
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3316441090
Short name T150
Test name
Test status
Simulation time 203942561 ps
CPU time 0.94 seconds
Started Aug 07 06:09:07 PM PDT 24
Finished Aug 07 06:09:08 PM PDT 24
Peak memory 206864 kb
Host smart-1bbca86f-1a42-4ef1-8c7c-6a3e2849d39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33164
41090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3316441090
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.325626019
Short name T175
Test name
Test status
Simulation time 7127226598 ps
CPU time 39.47 seconds
Started Aug 07 05:59:34 PM PDT 24
Finished Aug 07 06:00:13 PM PDT 24
Peak memory 223696 kb
Host smart-d7a734e6-2f0e-47d3-92d0-a9ca8bf4ae99
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=325626019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.325626019
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.562014452
Short name T160
Test name
Test status
Simulation time 188041927 ps
CPU time 0.99 seconds
Started Aug 07 05:59:51 PM PDT 24
Finished Aug 07 05:59:52 PM PDT 24
Peak memory 206964 kb
Host smart-1c46a837-5325-4577-b8e8-d119a0be7b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56201
4452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.562014452
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3970085089
Short name T301
Test name
Test status
Simulation time 312031268 ps
CPU time 2.31 seconds
Started Aug 07 04:58:45 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 206796 kb
Host smart-0e1a5512-2c60-4ba8-855e-07ff390b22f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3970085089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3970085089
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2360962381
Short name T3140
Test name
Test status
Simulation time 901447767 ps
CPU time 8.89 seconds
Started Aug 07 04:58:57 PM PDT 24
Finished Aug 07 04:59:06 PM PDT 24
Peak memory 206596 kb
Host smart-8091b0b4-f4e0-4c04-88ba-692a65556a99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2360962381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2360962381
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1722263345
Short name T277
Test name
Test status
Simulation time 148429439 ps
CPU time 0.94 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 206380 kb
Host smart-52f25931-551b-4998-b587-be62a4519a42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1722263345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1722263345
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3999082836
Short name T3223
Test name
Test status
Simulation time 140307792 ps
CPU time 1.84 seconds
Started Aug 07 04:58:55 PM PDT 24
Finished Aug 07 04:58:57 PM PDT 24
Peak memory 218272 kb
Host smart-70539549-5161-4b70-a23c-82566fc1cf41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999082836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3999082836
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.674517068
Short name T3181
Test name
Test status
Simulation time 103087195 ps
CPU time 0.96 seconds
Started Aug 07 04:58:57 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 206572 kb
Host smart-1927fd0c-0464-4a40-a231-cfb21b169d7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=674517068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.674517068
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.634636612
Short name T3201
Test name
Test status
Simulation time 101198588 ps
CPU time 0.75 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 206284 kb
Host smart-81540ed2-8321-4431-aea8-0820e684f31c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=634636612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.634636612
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2403661157
Short name T276
Test name
Test status
Simulation time 108430407 ps
CPU time 1.48 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 206696 kb
Host smart-9d151138-398e-4926-99b1-dccc12f8ac6a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2403661157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2403661157
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2842280262
Short name T3170
Test name
Test status
Simulation time 103860548 ps
CPU time 2.36 seconds
Started Aug 07 04:58:55 PM PDT 24
Finished Aug 07 04:58:57 PM PDT 24
Peak memory 206540 kb
Host smart-fb707ae3-f6a3-4a38-ac25-e9b2112b897a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2842280262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2842280262
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1507567526
Short name T3141
Test name
Test status
Simulation time 174444191 ps
CPU time 1.13 seconds
Started Aug 07 04:58:56 PM PDT 24
Finished Aug 07 04:58:57 PM PDT 24
Peak memory 206800 kb
Host smart-061895aa-182f-4942-9f29-68e189d8a7bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1507567526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1507567526
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1692220679
Short name T3224
Test name
Test status
Simulation time 97051928 ps
CPU time 1.48 seconds
Started Aug 07 04:59:08 PM PDT 24
Finished Aug 07 04:59:09 PM PDT 24
Peak memory 206784 kb
Host smart-7aba532c-e8c8-4fb9-a10e-8c428c334c98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1692220679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1692220679
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.310138811
Short name T3189
Test name
Test status
Simulation time 190988193 ps
CPU time 2.19 seconds
Started Aug 07 04:59:04 PM PDT 24
Finished Aug 07 04:59:06 PM PDT 24
Peak memory 206720 kb
Host smart-b2a30a24-0349-4482-ae79-0aa48daa02e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=310138811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.310138811
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3967368224
Short name T281
Test name
Test status
Simulation time 1553362841 ps
CPU time 8.94 seconds
Started Aug 07 04:58:57 PM PDT 24
Finished Aug 07 04:59:06 PM PDT 24
Peak memory 206788 kb
Host smart-79221e82-8fbf-41c7-8fc3-ae1ef54b9f93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3967368224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3967368224
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2961392789
Short name T3186
Test name
Test status
Simulation time 73647538 ps
CPU time 0.88 seconds
Started Aug 07 04:58:45 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 206452 kb
Host smart-22317dc4-24b5-4fc0-8001-0d9d85038ae9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2961392789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2961392789
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2616597880
Short name T3158
Test name
Test status
Simulation time 163656020 ps
CPU time 1.87 seconds
Started Aug 07 04:58:44 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 214976 kb
Host smart-b47539d2-a833-4ba4-965b-fbfc6e13697e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616597880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2616597880
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1589581498
Short name T273
Test name
Test status
Simulation time 51208923 ps
CPU time 0.99 seconds
Started Aug 07 04:59:08 PM PDT 24
Finished Aug 07 04:59:09 PM PDT 24
Peak memory 206364 kb
Host smart-bf421c70-9f79-4747-8dd2-288c091c4d03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1589581498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1589581498
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3689618415
Short name T3146
Test name
Test status
Simulation time 45661756 ps
CPU time 0.7 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:42 PM PDT 24
Peak memory 206416 kb
Host smart-6c706253-f106-45d5-b5ad-169492af30ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3689618415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3689618415
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2866738277
Short name T283
Test name
Test status
Simulation time 179231093 ps
CPU time 2.32 seconds
Started Aug 07 04:58:44 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 206668 kb
Host smart-f7cef1ea-cf9a-4bf9-808d-e932b8e8b9a7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2866738277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2866738277
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4197178698
Short name T3128
Test name
Test status
Simulation time 275489262 ps
CPU time 2.52 seconds
Started Aug 07 04:59:05 PM PDT 24
Finished Aug 07 04:59:08 PM PDT 24
Peak memory 206672 kb
Host smart-7340e40a-5482-4507-a2cf-afa1a6a2d165
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4197178698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.4197178698
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.638992536
Short name T3144
Test name
Test status
Simulation time 368842040 ps
CPU time 1.62 seconds
Started Aug 07 04:58:46 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 206748 kb
Host smart-d6c7a0c1-fb1a-4812-b9a4-f3d345de83df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=638992536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.638992536
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.659453701
Short name T3210
Test name
Test status
Simulation time 171914203 ps
CPU time 1.69 seconds
Started Aug 07 04:58:54 PM PDT 24
Finished Aug 07 04:58:56 PM PDT 24
Peak memory 214888 kb
Host smart-def60561-05f5-4676-a752-aab01478a745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659453701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.659453701
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.552929513
Short name T3174
Test name
Test status
Simulation time 87717667 ps
CPU time 1.03 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 206540 kb
Host smart-77f788b1-24c9-4406-94e4-0f425730ed59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=552929513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.552929513
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3185190340
Short name T3216
Test name
Test status
Simulation time 99472022 ps
CPU time 0.73 seconds
Started Aug 07 04:58:52 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 206356 kb
Host smart-c7af7943-230b-428e-80bb-e81d5570daec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3185190340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3185190340
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1503834984
Short name T3157
Test name
Test status
Simulation time 255061966 ps
CPU time 1.28 seconds
Started Aug 07 04:58:52 PM PDT 24
Finished Aug 07 04:58:54 PM PDT 24
Peak memory 206728 kb
Host smart-847e8a92-d616-41b8-b8f2-a2ab75ae0b94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1503834984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1503834984
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.698186374
Short name T3193
Test name
Test status
Simulation time 309515883 ps
CPU time 3.19 seconds
Started Aug 07 04:59:00 PM PDT 24
Finished Aug 07 04:59:04 PM PDT 24
Peak memory 206652 kb
Host smart-3e56807e-6784-4ae3-8c01-3c3d6e7db67e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=698186374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.698186374
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4234410528
Short name T480
Test name
Test status
Simulation time 418857228 ps
CPU time 3.03 seconds
Started Aug 07 04:59:03 PM PDT 24
Finished Aug 07 04:59:06 PM PDT 24
Peak memory 206768 kb
Host smart-83913f28-ca43-49b1-8262-7fccafeed3cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4234410528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.4234410528
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2672035353
Short name T257
Test name
Test status
Simulation time 139656794 ps
CPU time 1.71 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 04:58:57 PM PDT 24
Peak memory 223136 kb
Host smart-3a4d69c0-2e22-4fa8-b1da-f2b20c0d75e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672035353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2672035353
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1498222477
Short name T3196
Test name
Test status
Simulation time 48397860 ps
CPU time 0.79 seconds
Started Aug 07 04:58:57 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 206440 kb
Host smart-d8400e2f-d710-45fb-932c-eaf3d0876e95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1498222477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1498222477
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.566533151
Short name T3168
Test name
Test status
Simulation time 98292446 ps
CPU time 1.09 seconds
Started Aug 07 04:58:54 PM PDT 24
Finished Aug 07 04:58:55 PM PDT 24
Peak memory 206716 kb
Host smart-602461f5-a371-480c-8a10-e3a068ccb6c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=566533151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.566533151
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1641034610
Short name T3166
Test name
Test status
Simulation time 227230833 ps
CPU time 2.25 seconds
Started Aug 07 04:59:13 PM PDT 24
Finished Aug 07 04:59:16 PM PDT 24
Peak memory 206732 kb
Host smart-8b7a0c84-da73-4826-a210-d464c5fff823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1641034610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1641034610
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3279090726
Short name T256
Test name
Test status
Simulation time 146915018 ps
CPU time 1.82 seconds
Started Aug 07 04:59:19 PM PDT 24
Finished Aug 07 04:59:21 PM PDT 24
Peak memory 218420 kb
Host smart-ec24116d-74c1-48cc-af65-ae68b9ea4722
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279090726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.3279090726
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3215212860
Short name T271
Test name
Test status
Simulation time 78945511 ps
CPU time 1.08 seconds
Started Aug 07 04:59:14 PM PDT 24
Finished Aug 07 04:59:15 PM PDT 24
Peak memory 206468 kb
Host smart-e57da9de-876a-4807-9337-70af3cbe4cd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3215212860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3215212860
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.4031525348
Short name T3190
Test name
Test status
Simulation time 38802030 ps
CPU time 0.7 seconds
Started Aug 07 04:59:19 PM PDT 24
Finished Aug 07 04:59:20 PM PDT 24
Peak memory 206296 kb
Host smart-6f6df968-dee2-46fc-a7fa-8bd362bb2ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4031525348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.4031525348
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3725821085
Short name T3160
Test name
Test status
Simulation time 112315023 ps
CPU time 1.18 seconds
Started Aug 07 04:59:14 PM PDT 24
Finished Aug 07 04:59:15 PM PDT 24
Peak memory 206680 kb
Host smart-b8e25283-e616-4f58-81fc-fa644a40b94b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3725821085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3725821085
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1992897078
Short name T3180
Test name
Test status
Simulation time 87991613 ps
CPU time 2.14 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 222480 kb
Host smart-d8c017ba-243c-4bf3-b785-65e83627f5c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1992897078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1992897078
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2108154730
Short name T3208
Test name
Test status
Simulation time 476699953 ps
CPU time 4.15 seconds
Started Aug 07 04:58:52 PM PDT 24
Finished Aug 07 04:58:56 PM PDT 24
Peak memory 206764 kb
Host smart-2d380c24-de14-49d3-adb1-af2487977aff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2108154730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2108154730
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.892433483
Short name T261
Test name
Test status
Simulation time 80374678 ps
CPU time 1.86 seconds
Started Aug 07 04:59:19 PM PDT 24
Finished Aug 07 04:59:21 PM PDT 24
Peak memory 214940 kb
Host smart-ad0a6416-818d-40f2-b8a3-b36f88e29272
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892433483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.892433483
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1323345924
Short name T285
Test name
Test status
Simulation time 117262480 ps
CPU time 0.84 seconds
Started Aug 07 04:59:13 PM PDT 24
Finished Aug 07 04:59:14 PM PDT 24
Peak memory 206504 kb
Host smart-f73f5b66-499f-4393-9622-ca87a81873d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1323345924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1323345924
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1696326496
Short name T3231
Test name
Test status
Simulation time 41148646 ps
CPU time 0.7 seconds
Started Aug 07 04:59:16 PM PDT 24
Finished Aug 07 04:59:21 PM PDT 24
Peak memory 206404 kb
Host smart-e56c4dee-703f-486e-b27e-7d792613eb69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1696326496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1696326496
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.154807238
Short name T3172
Test name
Test status
Simulation time 104270833 ps
CPU time 1.56 seconds
Started Aug 07 04:59:22 PM PDT 24
Finished Aug 07 04:59:23 PM PDT 24
Peak memory 206616 kb
Host smart-3a2395b3-867b-4019-8dbc-5a6e6b41cf35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=154807238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.154807238
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2597132792
Short name T3228
Test name
Test status
Simulation time 100012296 ps
CPU time 2.44 seconds
Started Aug 07 04:59:15 PM PDT 24
Finished Aug 07 04:59:18 PM PDT 24
Peak memory 215200 kb
Host smart-31f861f2-4b0a-4533-9498-19b1b9bf8c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2597132792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2597132792
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.256984840
Short name T3183
Test name
Test status
Simulation time 505509144 ps
CPU time 2.87 seconds
Started Aug 07 04:59:23 PM PDT 24
Finished Aug 07 04:59:26 PM PDT 24
Peak memory 206744 kb
Host smart-988952e7-6c9e-4f02-bf11-7a69ad69eccb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=256984840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.256984840
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1364873348
Short name T305
Test name
Test status
Simulation time 181120228 ps
CPU time 1.85 seconds
Started Aug 07 04:59:10 PM PDT 24
Finished Aug 07 04:59:12 PM PDT 24
Peak memory 215112 kb
Host smart-680c4513-ebea-40d0-9f84-7a3e850f594e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364873348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1364873348
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3480392895
Short name T274
Test name
Test status
Simulation time 65901364 ps
CPU time 0.82 seconds
Started Aug 07 04:59:17 PM PDT 24
Finished Aug 07 04:59:18 PM PDT 24
Peak memory 206364 kb
Host smart-a58d707a-0505-4aeb-88b7-c4485478968b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3480392895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3480392895
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.667151871
Short name T3230
Test name
Test status
Simulation time 70161056 ps
CPU time 0.78 seconds
Started Aug 07 04:59:14 PM PDT 24
Finished Aug 07 04:59:15 PM PDT 24
Peak memory 206456 kb
Host smart-dcf3d2f5-954f-479c-abd0-77f5ba18f348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=667151871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.667151871
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2499455929
Short name T3184
Test name
Test status
Simulation time 166959588 ps
CPU time 1.2 seconds
Started Aug 07 04:59:20 PM PDT 24
Finished Aug 07 04:59:21 PM PDT 24
Peak memory 206516 kb
Host smart-84031800-89a0-4cf4-af79-b43b824ebb7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2499455929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2499455929
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.571461385
Short name T3162
Test name
Test status
Simulation time 299768910 ps
CPU time 3.89 seconds
Started Aug 07 04:59:28 PM PDT 24
Finished Aug 07 04:59:32 PM PDT 24
Peak memory 223036 kb
Host smart-04fe2b74-cfa0-4d10-9e1f-7b36583e4a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=571461385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.571461385
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1667150327
Short name T3173
Test name
Test status
Simulation time 453628578 ps
CPU time 2.53 seconds
Started Aug 07 04:59:15 PM PDT 24
Finished Aug 07 04:59:18 PM PDT 24
Peak memory 206816 kb
Host smart-a81037f7-64e3-4b84-899a-28b8c88eddf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1667150327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1667150327
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1392576260
Short name T3209
Test name
Test status
Simulation time 52113924 ps
CPU time 0.97 seconds
Started Aug 07 04:59:10 PM PDT 24
Finished Aug 07 04:59:11 PM PDT 24
Peak memory 206356 kb
Host smart-96558cbc-6e65-4084-a921-7f2a907a6164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1392576260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1392576260
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.41894268
Short name T224
Test name
Test status
Simulation time 105069951 ps
CPU time 0.78 seconds
Started Aug 07 04:59:12 PM PDT 24
Finished Aug 07 04:59:13 PM PDT 24
Peak memory 206416 kb
Host smart-642fac8a-8a32-425d-b3be-2e53633e5180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=41894268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.41894268
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3490273273
Short name T290
Test name
Test status
Simulation time 143569760 ps
CPU time 1.2 seconds
Started Aug 07 04:59:18 PM PDT 24
Finished Aug 07 04:59:20 PM PDT 24
Peak memory 206616 kb
Host smart-f3f4a435-4130-4352-9739-61de34d6a3d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3490273273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3490273273
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4175201109
Short name T3206
Test name
Test status
Simulation time 173785822 ps
CPU time 1.79 seconds
Started Aug 07 04:59:08 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 206716 kb
Host smart-317122e1-388c-4994-870a-43b29e24cad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4175201109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.4175201109
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.4035995778
Short name T335
Test name
Test status
Simulation time 472787277 ps
CPU time 2.73 seconds
Started Aug 07 04:59:15 PM PDT 24
Finished Aug 07 04:59:18 PM PDT 24
Peak memory 206640 kb
Host smart-1c73bbc7-0e76-4c7f-a262-b1d0a774f7cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4035995778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.4035995778
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.433733163
Short name T245
Test name
Test status
Simulation time 90308337 ps
CPU time 2.27 seconds
Started Aug 07 04:59:23 PM PDT 24
Finished Aug 07 04:59:26 PM PDT 24
Peak memory 215052 kb
Host smart-6a5b1744-9b90-439e-9480-664d0cefcc4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433733163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.433733163
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2848452679
Short name T279
Test name
Test status
Simulation time 130146958 ps
CPU time 1.04 seconds
Started Aug 07 04:59:20 PM PDT 24
Finished Aug 07 04:59:21 PM PDT 24
Peak memory 206496 kb
Host smart-491ccdb2-e3fb-4d1d-9063-18e4ca0d938b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2848452679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2848452679
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3383419571
Short name T3153
Test name
Test status
Simulation time 62891203 ps
CPU time 0.99 seconds
Started Aug 07 04:59:10 PM PDT 24
Finished Aug 07 04:59:11 PM PDT 24
Peak memory 206572 kb
Host smart-9f951bbd-7120-449a-a5a1-cb0457b57286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3383419571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3383419571
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3374405350
Short name T3171
Test name
Test status
Simulation time 241857755 ps
CPU time 2.84 seconds
Started Aug 07 04:59:23 PM PDT 24
Finished Aug 07 04:59:26 PM PDT 24
Peak memory 206792 kb
Host smart-23c382ed-5d19-43eb-8aaa-dab1fdb75c87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3374405350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3374405350
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.416124807
Short name T3211
Test name
Test status
Simulation time 524128359 ps
CPU time 3.11 seconds
Started Aug 07 04:59:09 PM PDT 24
Finished Aug 07 04:59:12 PM PDT 24
Peak memory 206760 kb
Host smart-1f8c36c0-4222-47ea-ac4e-a5614c0b6a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=416124807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.416124807
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1719947289
Short name T3215
Test name
Test status
Simulation time 129713590 ps
CPU time 1.6 seconds
Started Aug 07 04:59:20 PM PDT 24
Finished Aug 07 04:59:21 PM PDT 24
Peak memory 214948 kb
Host smart-56075abc-510c-4a51-8b4d-52337e0cef3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719947289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1719947289
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4160978814
Short name T3205
Test name
Test status
Simulation time 58597299 ps
CPU time 0.84 seconds
Started Aug 07 04:59:07 PM PDT 24
Finished Aug 07 04:59:08 PM PDT 24
Peak memory 206556 kb
Host smart-83241233-18fe-458b-aca0-7576615ae469
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4160978814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.4160978814
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3939845811
Short name T309
Test name
Test status
Simulation time 45178330 ps
CPU time 0.77 seconds
Started Aug 07 04:59:28 PM PDT 24
Finished Aug 07 04:59:29 PM PDT 24
Peak memory 206416 kb
Host smart-2e545c8a-546c-4d7d-aa06-175ca2f2c6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3939845811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3939845811
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.418965233
Short name T218
Test name
Test status
Simulation time 449791346 ps
CPU time 2.02 seconds
Started Aug 07 04:59:16 PM PDT 24
Finished Aug 07 04:59:18 PM PDT 24
Peak memory 206724 kb
Host smart-c4e37aca-e5ba-43e4-96d4-1913f645f5f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=418965233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.418965233
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1948000273
Short name T244
Test name
Test status
Simulation time 206143560 ps
CPU time 2.24 seconds
Started Aug 07 04:59:20 PM PDT 24
Finished Aug 07 04:59:23 PM PDT 24
Peak memory 206756 kb
Host smart-81d7145c-f0c2-428b-8c0e-642bc0f7a4dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1948000273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1948000273
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2334587002
Short name T3204
Test name
Test status
Simulation time 681114734 ps
CPU time 3.05 seconds
Started Aug 07 04:59:12 PM PDT 24
Finished Aug 07 04:59:15 PM PDT 24
Peak memory 206796 kb
Host smart-7a638f58-6b94-48b9-9a05-041d45c53b06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2334587002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2334587002
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2786348049
Short name T3226
Test name
Test status
Simulation time 136584659 ps
CPU time 1.61 seconds
Started Aug 07 04:59:31 PM PDT 24
Finished Aug 07 04:59:33 PM PDT 24
Peak memory 214984 kb
Host smart-0de80830-ceec-4f48-ac73-0640c5fd0081
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786348049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2786348049
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3956878997
Short name T3137
Test name
Test status
Simulation time 47873379 ps
CPU time 0.73 seconds
Started Aug 07 04:59:19 PM PDT 24
Finished Aug 07 04:59:20 PM PDT 24
Peak memory 206412 kb
Host smart-8dc35db3-a798-404c-932f-45db5b6be8ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3956878997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3956878997
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.4226428259
Short name T3149
Test name
Test status
Simulation time 209115084 ps
CPU time 1.65 seconds
Started Aug 07 04:59:23 PM PDT 24
Finished Aug 07 04:59:25 PM PDT 24
Peak memory 206552 kb
Host smart-9b09305c-ec38-47d5-b603-9a31c1bf1804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4226428259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.4226428259
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3161836288
Short name T255
Test name
Test status
Simulation time 76091359 ps
CPU time 1.96 seconds
Started Aug 07 04:59:17 PM PDT 24
Finished Aug 07 04:59:19 PM PDT 24
Peak memory 206700 kb
Host smart-2260ead6-7d9c-49b0-b756-c9bd92e8cf0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3161836288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3161836288
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.372084690
Short name T3191
Test name
Test status
Simulation time 605208343 ps
CPU time 2.78 seconds
Started Aug 07 04:59:14 PM PDT 24
Finished Aug 07 04:59:16 PM PDT 24
Peak memory 206756 kb
Host smart-1480c1d3-e3f2-4e04-b382-49cc0495df8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=372084690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.372084690
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3791316573
Short name T3135
Test name
Test status
Simulation time 154946010 ps
CPU time 1.73 seconds
Started Aug 07 04:59:20 PM PDT 24
Finished Aug 07 04:59:22 PM PDT 24
Peak memory 215012 kb
Host smart-abfc83de-07b8-4f66-bb43-7d9c0b71ad4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791316573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3791316573
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2075449801
Short name T3221
Test name
Test status
Simulation time 127138301 ps
CPU time 1.13 seconds
Started Aug 07 04:59:12 PM PDT 24
Finished Aug 07 04:59:13 PM PDT 24
Peak memory 206552 kb
Host smart-7ae41e15-0d52-46de-888d-d2f7211bad85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2075449801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2075449801
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4187239753
Short name T3212
Test name
Test status
Simulation time 45922809 ps
CPU time 0.71 seconds
Started Aug 07 04:59:24 PM PDT 24
Finished Aug 07 04:59:25 PM PDT 24
Peak memory 206368 kb
Host smart-066ab318-e089-4945-947f-f00440c8729f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4187239753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.4187239753
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1140579322
Short name T3176
Test name
Test status
Simulation time 153310197 ps
CPU time 1.6 seconds
Started Aug 07 04:59:12 PM PDT 24
Finished Aug 07 04:59:14 PM PDT 24
Peak memory 206704 kb
Host smart-18eef256-ece3-419f-b8d6-281106aeb068
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1140579322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1140579322
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2161512865
Short name T3199
Test name
Test status
Simulation time 71202844 ps
CPU time 1.76 seconds
Started Aug 07 04:59:21 PM PDT 24
Finished Aug 07 04:59:23 PM PDT 24
Peak memory 214872 kb
Host smart-02b6c128-495d-4bdb-b703-a0515c9ca1c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2161512865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2161512865
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3046167402
Short name T3177
Test name
Test status
Simulation time 171443361 ps
CPU time 2.02 seconds
Started Aug 07 04:59:05 PM PDT 24
Finished Aug 07 04:59:07 PM PDT 24
Peak memory 206644 kb
Host smart-90107010-ec6b-4d0a-b924-46d7587f70d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3046167402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3046167402
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1823549847
Short name T219
Test name
Test status
Simulation time 1113190225 ps
CPU time 4.4 seconds
Started Aug 07 04:58:52 PM PDT 24
Finished Aug 07 04:58:57 PM PDT 24
Peak memory 206692 kb
Host smart-6d54765b-f530-44b6-920a-d93c0544550b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1823549847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1823549847
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4160033709
Short name T3218
Test name
Test status
Simulation time 72152265 ps
CPU time 0.76 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 206412 kb
Host smart-7cb8d391-ed3d-4257-84d2-2a5c01e5775e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4160033709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.4160033709
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2609577999
Short name T275
Test name
Test status
Simulation time 52924193 ps
CPU time 0.9 seconds
Started Aug 07 04:59:09 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 206532 kb
Host smart-ee5b5c75-0c59-464d-b639-f0d8aa7e4a43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2609577999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2609577999
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1620694240
Short name T3178
Test name
Test status
Simulation time 90845250 ps
CPU time 0.72 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 206416 kb
Host smart-b48b2770-1247-42b7-8720-80c4eb54138a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1620694240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1620694240
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1367203908
Short name T280
Test name
Test status
Simulation time 100006533 ps
CPU time 1.44 seconds
Started Aug 07 04:58:47 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 206700 kb
Host smart-7d335d64-0a2d-414b-af0b-55a471156ba1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1367203908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1367203908
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2280769631
Short name T3179
Test name
Test status
Simulation time 488170868 ps
CPU time 4.16 seconds
Started Aug 07 04:58:57 PM PDT 24
Finished Aug 07 04:59:01 PM PDT 24
Peak memory 206648 kb
Host smart-cf5a3c94-453f-41ba-a98f-b7fbe09e978b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2280769631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2280769631
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.751963065
Short name T3154
Test name
Test status
Simulation time 104855892 ps
CPU time 1.53 seconds
Started Aug 07 04:58:56 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 206716 kb
Host smart-0ee8975e-d350-4a6a-a2cb-4a363983ebb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=751963065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.751963065
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2725886746
Short name T3159
Test name
Test status
Simulation time 295555646 ps
CPU time 2.92 seconds
Started Aug 07 04:58:55 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 215004 kb
Host smart-e7b56537-e107-447a-89c1-f65771fd1167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2725886746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2725886746
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1455274917
Short name T304
Test name
Test status
Simulation time 402674623 ps
CPU time 2.72 seconds
Started Aug 07 04:59:07 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 206736 kb
Host smart-7856372c-43f8-4910-b186-713797d724f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1455274917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1455274917
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3197194535
Short name T307
Test name
Test status
Simulation time 63532857 ps
CPU time 0.73 seconds
Started Aug 07 04:59:21 PM PDT 24
Finished Aug 07 04:59:22 PM PDT 24
Peak memory 206396 kb
Host smart-2b562391-0c28-4a65-b0fd-12b5449f3e34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3197194535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3197194535
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3400241060
Short name T3220
Test name
Test status
Simulation time 37305141 ps
CPU time 0.7 seconds
Started Aug 07 04:59:19 PM PDT 24
Finished Aug 07 04:59:19 PM PDT 24
Peak memory 206396 kb
Host smart-2e90c27a-9541-4680-9a76-0da85814d15a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3400241060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3400241060
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4093894117
Short name T227
Test name
Test status
Simulation time 77463404 ps
CPU time 0.77 seconds
Started Aug 07 04:59:26 PM PDT 24
Finished Aug 07 04:59:27 PM PDT 24
Peak memory 206400 kb
Host smart-7ab80a1a-b626-4d29-b448-5b23609e6e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4093894117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.4093894117
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2088704245
Short name T3139
Test name
Test status
Simulation time 46926218 ps
CPU time 0.68 seconds
Started Aug 07 04:59:18 PM PDT 24
Finished Aug 07 04:59:19 PM PDT 24
Peak memory 206296 kb
Host smart-d8721140-20ff-4bf5-a9f1-67658206681e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2088704245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2088704245
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1091718795
Short name T228
Test name
Test status
Simulation time 83392297 ps
CPU time 0.73 seconds
Started Aug 07 04:59:11 PM PDT 24
Finished Aug 07 04:59:12 PM PDT 24
Peak memory 206440 kb
Host smart-2a7357cb-3b69-4856-a98f-81fbfb8c3011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1091718795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1091718795
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1628937970
Short name T3187
Test name
Test status
Simulation time 37175191 ps
CPU time 0.68 seconds
Started Aug 07 04:59:32 PM PDT 24
Finished Aug 07 04:59:33 PM PDT 24
Peak memory 206352 kb
Host smart-5e91b3d9-6fd8-4e97-ae17-8d6ecea06765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1628937970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1628937970
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.859659458
Short name T3136
Test name
Test status
Simulation time 80793997 ps
CPU time 0.75 seconds
Started Aug 07 04:59:15 PM PDT 24
Finished Aug 07 04:59:16 PM PDT 24
Peak memory 206392 kb
Host smart-4b15ee61-cabb-47e1-9ef5-209e6ccc9b0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=859659458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.859659458
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2836103271
Short name T226
Test name
Test status
Simulation time 62690603 ps
CPU time 0.75 seconds
Started Aug 07 04:59:35 PM PDT 24
Finished Aug 07 04:59:36 PM PDT 24
Peak memory 206312 kb
Host smart-b5712079-6893-44f1-aba1-22cf76d4098f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2836103271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2836103271
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1019271003
Short name T287
Test name
Test status
Simulation time 88616354 ps
CPU time 1.89 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 206756 kb
Host smart-ee273bdf-02e2-4a3f-97a5-deec5d6c8056
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1019271003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1019271003
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3015635791
Short name T3213
Test name
Test status
Simulation time 705474292 ps
CPU time 4.36 seconds
Started Aug 07 04:59:07 PM PDT 24
Finished Aug 07 04:59:11 PM PDT 24
Peak memory 206716 kb
Host smart-d8259f75-eeb7-47b5-8c77-289938ee38fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3015635791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3015635791
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3377100768
Short name T3229
Test name
Test status
Simulation time 115065410 ps
CPU time 0.91 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 206520 kb
Host smart-d3b2a2e1-c60c-451f-a7ed-353363e27f62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3377100768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3377100768
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1331807533
Short name T3195
Test name
Test status
Simulation time 202581844 ps
CPU time 1.76 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 217684 kb
Host smart-6b6739f6-f6f3-406c-9d04-436086fb75fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331807533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.1331807533
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2085522993
Short name T3164
Test name
Test status
Simulation time 101952256 ps
CPU time 0.97 seconds
Started Aug 07 04:58:45 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 206752 kb
Host smart-964b4ecb-34fb-4a83-b86a-21d0ed5df3b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2085522993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2085522993
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1964248304
Short name T270
Test name
Test status
Simulation time 104816723 ps
CPU time 1.4 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 206752 kb
Host smart-1d95fb90-3708-4a6c-81a3-e52a58c505cb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1964248304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1964248304
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3038915080
Short name T3134
Test name
Test status
Simulation time 109052562 ps
CPU time 2.36 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 206644 kb
Host smart-0357fe8b-5046-47f4-9a10-dc5b8680a0f2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3038915080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3038915080
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4233366245
Short name T291
Test name
Test status
Simulation time 96716001 ps
CPU time 1.05 seconds
Started Aug 07 04:58:47 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 206624 kb
Host smart-6a4acd34-5740-40ef-b96e-52b79d5d0a24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4233366245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.4233366245
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2950951819
Short name T259
Test name
Test status
Simulation time 230894231 ps
CPU time 2.43 seconds
Started Aug 07 04:59:04 PM PDT 24
Finished Aug 07 04:59:06 PM PDT 24
Peak memory 222296 kb
Host smart-2b18240b-7411-4e7f-aacc-92ca85e87472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2950951819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2950951819
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3474899294
Short name T340
Test name
Test status
Simulation time 755258118 ps
CPU time 3.54 seconds
Started Aug 07 04:59:07 PM PDT 24
Finished Aug 07 04:59:11 PM PDT 24
Peak memory 206776 kb
Host smart-28dc4de0-fb8d-4501-a0ab-8412d101ede1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3474899294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3474899294
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2137545373
Short name T3150
Test name
Test status
Simulation time 49902552 ps
CPU time 0.73 seconds
Started Aug 07 04:59:21 PM PDT 24
Finished Aug 07 04:59:22 PM PDT 24
Peak memory 206296 kb
Host smart-14ffc220-0f07-45f9-91ea-c83a5f173757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2137545373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2137545373
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3027361962
Short name T3167
Test name
Test status
Simulation time 64781038 ps
CPU time 0.8 seconds
Started Aug 07 04:59:28 PM PDT 24
Finished Aug 07 04:59:29 PM PDT 24
Peak memory 206416 kb
Host smart-acd1187d-eca3-4f8b-a1ed-b7019172b932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3027361962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3027361962
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.4028652799
Short name T3219
Test name
Test status
Simulation time 55690457 ps
CPU time 0.76 seconds
Started Aug 07 04:59:20 PM PDT 24
Finished Aug 07 04:59:21 PM PDT 24
Peak memory 206296 kb
Host smart-8586be7c-975a-4535-9844-5754b68ee33b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4028652799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.4028652799
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1491962661
Short name T3133
Test name
Test status
Simulation time 48646467 ps
CPU time 0.67 seconds
Started Aug 07 04:59:34 PM PDT 24
Finished Aug 07 04:59:35 PM PDT 24
Peak memory 206440 kb
Host smart-96de174e-7b41-4b95-b43d-a5da31ec6bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1491962661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1491962661
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1511831003
Short name T3138
Test name
Test status
Simulation time 41026061 ps
CPU time 0.79 seconds
Started Aug 07 04:59:24 PM PDT 24
Finished Aug 07 04:59:25 PM PDT 24
Peak memory 206380 kb
Host smart-46eacdae-2770-4d52-9bb6-a5fa588ea7f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1511831003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1511831003
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1501616364
Short name T3214
Test name
Test status
Simulation time 39319194 ps
CPU time 0.72 seconds
Started Aug 07 04:59:20 PM PDT 24
Finished Aug 07 04:59:21 PM PDT 24
Peak memory 206400 kb
Host smart-a96ae46b-b96c-481f-bc14-36333ca710e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1501616364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1501616364
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1911537093
Short name T3217
Test name
Test status
Simulation time 53535142 ps
CPU time 0.71 seconds
Started Aug 07 04:59:21 PM PDT 24
Finished Aug 07 04:59:22 PM PDT 24
Peak memory 206404 kb
Host smart-8f618115-cf72-4f1e-b74b-1531a7c4b303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1911537093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1911537093
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4082684434
Short name T3142
Test name
Test status
Simulation time 51001724 ps
CPU time 0.68 seconds
Started Aug 07 04:59:24 PM PDT 24
Finished Aug 07 04:59:25 PM PDT 24
Peak memory 206356 kb
Host smart-5e958c33-e5e7-4233-b5d4-f50fe3684d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4082684434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.4082684434
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3541787683
Short name T3129
Test name
Test status
Simulation time 51052134 ps
CPU time 0.71 seconds
Started Aug 07 04:59:46 PM PDT 24
Finished Aug 07 04:59:47 PM PDT 24
Peak memory 206420 kb
Host smart-7aabfbb7-d647-4b3c-8d83-7cdf62e9156a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3541787683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3541787683
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.954807150
Short name T223
Test name
Test status
Simulation time 43298825 ps
CPU time 0.67 seconds
Started Aug 07 04:59:24 PM PDT 24
Finished Aug 07 04:59:24 PM PDT 24
Peak memory 206396 kb
Host smart-b8d4c542-54c6-40f5-a336-392e48b3da75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=954807150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.954807150
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3088368358
Short name T3225
Test name
Test status
Simulation time 233212083 ps
CPU time 2.13 seconds
Started Aug 07 04:58:55 PM PDT 24
Finished Aug 07 04:58:57 PM PDT 24
Peak memory 206648 kb
Host smart-40cbfcbc-68d5-4dea-8505-f2b9c1e071f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3088368358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3088368358
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2610796215
Short name T278
Test name
Test status
Simulation time 1638780205 ps
CPU time 8.13 seconds
Started Aug 07 04:58:54 PM PDT 24
Finished Aug 07 04:59:02 PM PDT 24
Peak memory 206748 kb
Host smart-ff5c8652-8fea-4617-9890-97d9c01fa351
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2610796215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2610796215
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3205629462
Short name T3194
Test name
Test status
Simulation time 122712238 ps
CPU time 0.84 seconds
Started Aug 07 04:59:07 PM PDT 24
Finished Aug 07 04:59:08 PM PDT 24
Peak memory 206472 kb
Host smart-6d1da840-4893-48d4-86c7-a262405a6b98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3205629462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3205629462
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1768841482
Short name T3175
Test name
Test status
Simulation time 118001162 ps
CPU time 1.68 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 214904 kb
Host smart-9fe756b6-50f6-4c9a-aa9d-e2307c05e0fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768841482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1768841482
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3587989845
Short name T286
Test name
Test status
Simulation time 46014988 ps
CPU time 0.8 seconds
Started Aug 07 04:58:58 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 206476 kb
Host smart-3cc05c5a-9e1e-480c-ad45-a5ebbb669732
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3587989845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3587989845
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3122422846
Short name T3161
Test name
Test status
Simulation time 42433145 ps
CPU time 0.73 seconds
Started Aug 07 04:59:15 PM PDT 24
Finished Aug 07 04:59:16 PM PDT 24
Peak memory 206420 kb
Host smart-d641bdba-973f-42b9-a94c-5c1a477e3c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3122422846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3122422846
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.825555038
Short name T282
Test name
Test status
Simulation time 153117911 ps
CPU time 1.43 seconds
Started Aug 07 04:58:47 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 206748 kb
Host smart-1088f053-da78-4b6f-bac0-13d5219f6daf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=825555038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.825555038
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.428347711
Short name T3131
Test name
Test status
Simulation time 380696292 ps
CPU time 2.65 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:54 PM PDT 24
Peak memory 206652 kb
Host smart-b2240648-fea9-4a5e-b617-cd51b9cfd119
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=428347711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.428347711
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3942492702
Short name T3197
Test name
Test status
Simulation time 356143491 ps
CPU time 1.71 seconds
Started Aug 07 04:59:10 PM PDT 24
Finished Aug 07 04:59:11 PM PDT 24
Peak memory 206672 kb
Host smart-e271de7f-ac72-4e1f-a64d-f8d1a00789fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3942492702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3942492702
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3107277559
Short name T3198
Test name
Test status
Simulation time 933802834 ps
CPU time 3.59 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 04:58:54 PM PDT 24
Peak memory 206804 kb
Host smart-443f7613-f367-48ac-aa7d-76b2d391180f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3107277559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3107277559
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3974750931
Short name T3192
Test name
Test status
Simulation time 85003550 ps
CPU time 0.79 seconds
Started Aug 07 04:59:12 PM PDT 24
Finished Aug 07 04:59:13 PM PDT 24
Peak memory 206412 kb
Host smart-859bbf18-9e9f-42a0-8ae1-045272bbbb56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3974750931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3974750931
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2282604535
Short name T3151
Test name
Test status
Simulation time 46883976 ps
CPU time 0.75 seconds
Started Aug 07 04:59:34 PM PDT 24
Finished Aug 07 04:59:35 PM PDT 24
Peak memory 206428 kb
Host smart-0a9ed21e-e296-424e-951b-ed868a2cba08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2282604535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2282604535
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1568960082
Short name T334
Test name
Test status
Simulation time 40450587 ps
CPU time 0.7 seconds
Started Aug 07 04:59:14 PM PDT 24
Finished Aug 07 04:59:15 PM PDT 24
Peak memory 206416 kb
Host smart-dcd59c0b-cfe6-404a-866d-2e72b28f9ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1568960082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1568960082
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3348664863
Short name T306
Test name
Test status
Simulation time 44578363 ps
CPU time 0.78 seconds
Started Aug 07 04:59:20 PM PDT 24
Finished Aug 07 04:59:21 PM PDT 24
Peak memory 206416 kb
Host smart-26fb57f8-e3a2-4e8b-bf21-db016c001e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3348664863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3348664863
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.960775264
Short name T3185
Test name
Test status
Simulation time 49213425 ps
CPU time 0.72 seconds
Started Aug 07 04:59:31 PM PDT 24
Finished Aug 07 04:59:31 PM PDT 24
Peak memory 206432 kb
Host smart-7261a81e-97fd-40cc-bd4c-b07d55615c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=960775264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.960775264
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.598968763
Short name T3143
Test name
Test status
Simulation time 64188146 ps
CPU time 0.72 seconds
Started Aug 07 04:59:23 PM PDT 24
Finished Aug 07 04:59:24 PM PDT 24
Peak memory 206332 kb
Host smart-b37213c1-d0d1-4e1e-910a-46588f78d7a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=598968763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.598968763
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1978992839
Short name T3132
Test name
Test status
Simulation time 67202907 ps
CPU time 0.72 seconds
Started Aug 07 04:59:20 PM PDT 24
Finished Aug 07 04:59:21 PM PDT 24
Peak memory 206312 kb
Host smart-cb162341-dcef-478e-9662-58486f6be556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1978992839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1978992839
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2676831846
Short name T3145
Test name
Test status
Simulation time 75612872 ps
CPU time 0.71 seconds
Started Aug 07 04:59:16 PM PDT 24
Finished Aug 07 04:59:17 PM PDT 24
Peak memory 206396 kb
Host smart-2f33eb58-9e22-485d-ac99-ab0ef1848069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2676831846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2676831846
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2981636279
Short name T3148
Test name
Test status
Simulation time 41069452 ps
CPU time 0.69 seconds
Started Aug 07 04:59:33 PM PDT 24
Finished Aug 07 04:59:34 PM PDT 24
Peak memory 206412 kb
Host smart-055a58ba-ee2c-427f-8d40-65ffb7235f8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2981636279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2981636279
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2537605479
Short name T3130
Test name
Test status
Simulation time 34351941 ps
CPU time 0.69 seconds
Started Aug 07 04:59:37 PM PDT 24
Finished Aug 07 04:59:38 PM PDT 24
Peak memory 206312 kb
Host smart-53caab6b-dbdd-4812-a20b-67099ea15b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2537605479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2537605479
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2903496224
Short name T215
Test name
Test status
Simulation time 77321935 ps
CPU time 1.1 seconds
Started Aug 07 04:59:01 PM PDT 24
Finished Aug 07 04:59:02 PM PDT 24
Peak memory 222704 kb
Host smart-ec66755c-f845-46ce-b056-e13be0756e86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903496224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2903496224
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3228268370
Short name T3165
Test name
Test status
Simulation time 73147750 ps
CPU time 0.97 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 206560 kb
Host smart-52abedcc-4a1d-4374-8215-30633b870e1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3228268370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3228268370
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1685503227
Short name T3227
Test name
Test status
Simulation time 33814802 ps
CPU time 0.67 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 206384 kb
Host smart-487c3cc2-cc95-4606-abe1-b4efec63c8d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1685503227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1685503227
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.176189876
Short name T288
Test name
Test status
Simulation time 103813983 ps
CPU time 1.14 seconds
Started Aug 07 04:58:46 PM PDT 24
Finished Aug 07 04:58:57 PM PDT 24
Peak memory 206740 kb
Host smart-aa241e95-50f0-4a63-bdf7-86c11bc32d7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=176189876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.176189876
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3377700764
Short name T242
Test name
Test status
Simulation time 161762099 ps
CPU time 2.06 seconds
Started Aug 07 04:58:52 PM PDT 24
Finished Aug 07 04:58:55 PM PDT 24
Peak memory 214928 kb
Host smart-45207439-80f2-4b39-8e07-d92311767e09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3377700764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3377700764
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3410144794
Short name T3222
Test name
Test status
Simulation time 1723323068 ps
CPU time 5.87 seconds
Started Aug 07 04:59:02 PM PDT 24
Finished Aug 07 04:59:08 PM PDT 24
Peak memory 206784 kb
Host smart-6714e60a-bf1b-438a-83b9-5c32e58ecaf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3410144794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3410144794
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.250457005
Short name T303
Test name
Test status
Simulation time 170996643 ps
CPU time 1.62 seconds
Started Aug 07 04:59:00 PM PDT 24
Finished Aug 07 04:59:02 PM PDT 24
Peak memory 215036 kb
Host smart-c4ab2ff6-0c45-432e-ad6b-201d1e9fbc05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250457005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.250457005
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.122200060
Short name T3152
Test name
Test status
Simulation time 95045288 ps
CPU time 0.91 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 206400 kb
Host smart-3147564b-326e-48c1-85fa-75b234289c75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=122200060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.122200060
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3484402544
Short name T3203
Test name
Test status
Simulation time 51917483 ps
CPU time 0.75 seconds
Started Aug 07 04:58:59 PM PDT 24
Finished Aug 07 04:59:00 PM PDT 24
Peak memory 206420 kb
Host smart-a782469f-c22a-49d6-94c5-f2d990ec8ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3484402544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3484402544
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.802816330
Short name T3169
Test name
Test status
Simulation time 65186341 ps
CPU time 1.1 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 206724 kb
Host smart-1898fb6e-74fd-477f-8da9-0ff4d552f6f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=802816330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.802816330
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.448980899
Short name T260
Test name
Test status
Simulation time 253948846 ps
CPU time 2.72 seconds
Started Aug 07 04:58:56 PM PDT 24
Finished Aug 07 04:58:59 PM PDT 24
Peak memory 215052 kb
Host smart-ff1fd70e-b02a-47e7-af36-49c33023fd48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=448980899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.448980899
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.129493837
Short name T338
Test name
Test status
Simulation time 2183979040 ps
CPU time 5.2 seconds
Started Aug 07 04:58:57 PM PDT 24
Finished Aug 07 04:59:02 PM PDT 24
Peak memory 206872 kb
Host smart-0aabdf61-7002-401a-9648-ac192d749af1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=129493837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.129493837
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.864617469
Short name T302
Test name
Test status
Simulation time 165570904 ps
CPU time 1.75 seconds
Started Aug 07 04:58:56 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 214976 kb
Host smart-c1d30794-deca-4db4-9737-28fbc9633d89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864617469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.864617469
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2444440659
Short name T284
Test name
Test status
Simulation time 107196830 ps
CPU time 0.87 seconds
Started Aug 07 04:59:00 PM PDT 24
Finished Aug 07 04:59:01 PM PDT 24
Peak memory 206408 kb
Host smart-63fdeda2-1b3d-4af5-a596-6177f9ae67a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2444440659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2444440659
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1611741005
Short name T332
Test name
Test status
Simulation time 40953563 ps
CPU time 0.72 seconds
Started Aug 07 04:59:09 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 206372 kb
Host smart-635d9de9-3293-48dd-917c-90710bce1fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1611741005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1611741005
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1731818961
Short name T3182
Test name
Test status
Simulation time 232474023 ps
CPU time 1.7 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 206624 kb
Host smart-2229a79d-3f36-4a7f-9739-28254371333e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1731818961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1731818961
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.65653545
Short name T254
Test name
Test status
Simulation time 165067711 ps
CPU time 2.38 seconds
Started Aug 07 04:59:03 PM PDT 24
Finished Aug 07 04:59:06 PM PDT 24
Peak memory 222840 kb
Host smart-7fa263d2-87a2-4815-852a-310360eda05c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=65653545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.65653545
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1667148909
Short name T339
Test name
Test status
Simulation time 1933654741 ps
CPU time 5.34 seconds
Started Aug 07 04:59:13 PM PDT 24
Finished Aug 07 04:59:18 PM PDT 24
Peak memory 206688 kb
Host smart-8e637b28-da3e-4bbf-b042-a97c0aecf935
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1667148909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1667148909
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1231313395
Short name T262
Test name
Test status
Simulation time 80837056 ps
CPU time 1.62 seconds
Started Aug 07 04:58:55 PM PDT 24
Finished Aug 07 04:58:57 PM PDT 24
Peak memory 215056 kb
Host smart-404fec7b-e867-4544-a644-2c3885870d36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231313395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1231313395
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2950260581
Short name T3155
Test name
Test status
Simulation time 110469159 ps
CPU time 0.87 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 206460 kb
Host smart-4acf3cdd-1ce2-4be0-b75e-f0d8f0ec7306
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2950260581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2950260581
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3889281258
Short name T3200
Test name
Test status
Simulation time 69043379 ps
CPU time 0.8 seconds
Started Aug 07 04:59:09 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 206396 kb
Host smart-82f12646-d38b-427e-8808-3c23da5c7503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3889281258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3889281258
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2792514367
Short name T289
Test name
Test status
Simulation time 100043630 ps
CPU time 1.03 seconds
Started Aug 07 04:58:55 PM PDT 24
Finished Aug 07 04:58:56 PM PDT 24
Peak memory 206376 kb
Host smart-eb758a99-5bd8-4578-a819-3d7b85511818
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2792514367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2792514367
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2676983769
Short name T253
Test name
Test status
Simulation time 119289640 ps
CPU time 3.24 seconds
Started Aug 07 04:59:08 PM PDT 24
Finished Aug 07 04:59:12 PM PDT 24
Peak memory 222980 kb
Host smart-cb242c92-f995-424a-88db-02e076c5a53f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2676983769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2676983769
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3660972404
Short name T247
Test name
Test status
Simulation time 858407508 ps
CPU time 3.2 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 206784 kb
Host smart-baae116e-2193-4979-920f-92351a01c61b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3660972404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3660972404
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.930170503
Short name T3156
Test name
Test status
Simulation time 80641961 ps
CPU time 1.34 seconds
Started Aug 07 04:58:53 PM PDT 24
Finished Aug 07 04:58:54 PM PDT 24
Peak memory 215008 kb
Host smart-b69e0767-7bab-4708-a67d-db204e491cdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930170503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.930170503
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4153414145
Short name T3188
Test name
Test status
Simulation time 97423829 ps
CPU time 0.99 seconds
Started Aug 07 04:58:53 PM PDT 24
Finished Aug 07 04:58:54 PM PDT 24
Peak memory 206428 kb
Host smart-91bed38d-8910-40a8-b04f-197853593750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4153414145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4153414145
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1152663849
Short name T3202
Test name
Test status
Simulation time 101280091 ps
CPU time 0.76 seconds
Started Aug 07 04:59:05 PM PDT 24
Finished Aug 07 04:59:06 PM PDT 24
Peak memory 206440 kb
Host smart-925b1fe0-6eb8-40ba-95f9-c91476d9ca80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1152663849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1152663849
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1002591593
Short name T3232
Test name
Test status
Simulation time 264189269 ps
CPU time 2.02 seconds
Started Aug 07 04:59:04 PM PDT 24
Finished Aug 07 04:59:06 PM PDT 24
Peak memory 206820 kb
Host smart-ee0c3303-f7f1-442d-b9ce-f83d00aa9a10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1002591593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1002591593
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1552654767
Short name T3207
Test name
Test status
Simulation time 93441510 ps
CPU time 2.75 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:54 PM PDT 24
Peak memory 219816 kb
Host smart-cc7cdb14-5e02-41cd-88ae-38012739638d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1552654767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1552654767
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1112455679
Short name T1131
Test name
Test status
Simulation time 63398958 ps
CPU time 0.72 seconds
Started Aug 07 05:58:25 PM PDT 24
Finished Aug 07 05:58:26 PM PDT 24
Peak memory 206972 kb
Host smart-33032ae6-7865-4854-90fb-eb69e542b177
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1112455679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1112455679
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3293811955
Short name T2054
Test name
Test status
Simulation time 11100196268 ps
CPU time 15.87 seconds
Started Aug 07 05:57:44 PM PDT 24
Finished Aug 07 05:58:00 PM PDT 24
Peak memory 207240 kb
Host smart-440190ee-bb9a-4b03-a3f5-b7ee51b66174
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293811955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.3293811955
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3099980779
Short name T1201
Test name
Test status
Simulation time 13523569368 ps
CPU time 15.57 seconds
Started Aug 07 05:57:49 PM PDT 24
Finished Aug 07 05:58:05 PM PDT 24
Peak memory 215456 kb
Host smart-7c339cbb-2f87-4a6e-9941-32b3bc4122ec
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099980779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3099980779
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3123400869
Short name T2099
Test name
Test status
Simulation time 25242457297 ps
CPU time 30.98 seconds
Started Aug 07 05:57:52 PM PDT 24
Finished Aug 07 05:58:23 PM PDT 24
Peak memory 215436 kb
Host smart-402b19f5-7743-490e-956e-40fdaae980cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123400869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.3123400869
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4161685485
Short name T1035
Test name
Test status
Simulation time 152005350 ps
CPU time 0.87 seconds
Started Aug 07 05:57:46 PM PDT 24
Finished Aug 07 05:57:47 PM PDT 24
Peak memory 207004 kb
Host smart-e06ffd82-f3ed-48aa-98c3-2538b01ea461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41616
85485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4161685485
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1238480058
Short name T2200
Test name
Test status
Simulation time 162388347 ps
CPU time 0.85 seconds
Started Aug 07 05:57:45 PM PDT 24
Finished Aug 07 05:57:46 PM PDT 24
Peak memory 206960 kb
Host smart-3cdbb6d7-5ddd-451e-a61d-5e50d4b2635e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12384
80058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1238480058
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.4106391642
Short name T576
Test name
Test status
Simulation time 436274103 ps
CPU time 1.56 seconds
Started Aug 07 05:57:46 PM PDT 24
Finished Aug 07 05:57:48 PM PDT 24
Peak memory 206972 kb
Host smart-51ce2bc5-92ba-4040-a531-19abd01b1b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41063
91642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.4106391642
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3230654543
Short name T2079
Test name
Test status
Simulation time 1145306467 ps
CPU time 3.19 seconds
Started Aug 07 05:57:47 PM PDT 24
Finished Aug 07 05:57:50 PM PDT 24
Peak memory 207440 kb
Host smart-a9fddf28-5998-4240-abd5-fa8287afc547
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3230654543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3230654543
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2730469248
Short name T485
Test name
Test status
Simulation time 37249865743 ps
CPU time 61.17 seconds
Started Aug 07 05:57:48 PM PDT 24
Finished Aug 07 05:58:49 PM PDT 24
Peak memory 207344 kb
Host smart-bb5ec4d6-e5d5-421b-b1fe-07317a5b4975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27304
69248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2730469248
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.975420792
Short name T2660
Test name
Test status
Simulation time 3908074027 ps
CPU time 34.23 seconds
Started Aug 07 05:57:53 PM PDT 24
Finished Aug 07 05:58:28 PM PDT 24
Peak memory 207336 kb
Host smart-279f9dbe-bfea-4f42-ab4d-49de8b96a380
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975420792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.975420792
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3928487315
Short name T1672
Test name
Test status
Simulation time 571120634 ps
CPU time 1.68 seconds
Started Aug 07 05:57:49 PM PDT 24
Finished Aug 07 05:57:51 PM PDT 24
Peak memory 206956 kb
Host smart-feb9fefe-e289-4c12-8e96-7bd7ea09beb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39284
87315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3928487315
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2977718559
Short name T2618
Test name
Test status
Simulation time 152954603 ps
CPU time 0.78 seconds
Started Aug 07 05:57:52 PM PDT 24
Finished Aug 07 05:57:53 PM PDT 24
Peak memory 206952 kb
Host smart-ab623531-59fe-4cd3-90b7-0b4cb81571da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29777
18559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2977718559
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3482483781
Short name T2026
Test name
Test status
Simulation time 5107645116 ps
CPU time 138.75 seconds
Started Aug 07 05:57:49 PM PDT 24
Finished Aug 07 06:00:08 PM PDT 24
Peak memory 215564 kb
Host smart-82ad4cf1-96eb-4b21-ba6a-a8326264bc0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34824
83781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3482483781
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.1650638016
Short name T2463
Test name
Test status
Simulation time 37617131 ps
CPU time 0.7 seconds
Started Aug 07 05:58:43 PM PDT 24
Finished Aug 07 05:58:44 PM PDT 24
Peak memory 206980 kb
Host smart-9d567dba-2395-4015-9bda-7d445f72267f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16506
38016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1650638016
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3987346872
Short name T739
Test name
Test status
Simulation time 890561495 ps
CPU time 2.43 seconds
Started Aug 07 05:57:51 PM PDT 24
Finished Aug 07 05:57:53 PM PDT 24
Peak memory 207256 kb
Host smart-7e2c26c5-c601-441d-aa26-9efc028f9155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39873
46872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3987346872
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2025811552
Short name T1439
Test name
Test status
Simulation time 237581731 ps
CPU time 1.6 seconds
Started Aug 07 05:57:49 PM PDT 24
Finished Aug 07 05:57:51 PM PDT 24
Peak memory 207152 kb
Host smart-4e24be9a-e520-4e3d-b8fa-38f55434f65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20258
11552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2025811552
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2965284573
Short name T1674
Test name
Test status
Simulation time 107187899137 ps
CPU time 174.34 seconds
Started Aug 07 05:57:50 PM PDT 24
Finished Aug 07 06:00:45 PM PDT 24
Peak memory 207224 kb
Host smart-ad184f27-2b1b-45a7-bed9-095bf66d6e51
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2965284573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2965284573
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.3996524290
Short name T2654
Test name
Test status
Simulation time 114161854757 ps
CPU time 183.04 seconds
Started Aug 07 05:57:48 PM PDT 24
Finished Aug 07 06:00:52 PM PDT 24
Peak memory 207268 kb
Host smart-b1321d84-6adc-40cd-88d0-2b5888a73440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996524290 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.3996524290
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.748667823
Short name T251
Test name
Test status
Simulation time 90102532557 ps
CPU time 139.37 seconds
Started Aug 07 05:57:51 PM PDT 24
Finished Aug 07 06:00:11 PM PDT 24
Peak memory 207236 kb
Host smart-9e89f605-dce8-4110-9f90-6f4a3f6ff937
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=748667823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.748667823
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.930676200
Short name T1644
Test name
Test status
Simulation time 111057632568 ps
CPU time 189.66 seconds
Started Aug 07 05:57:51 PM PDT 24
Finished Aug 07 06:01:01 PM PDT 24
Peak memory 207316 kb
Host smart-2070e96c-bd97-4845-83a3-016e42568ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930676200 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.930676200
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.1653260142
Short name T2756
Test name
Test status
Simulation time 119166176050 ps
CPU time 187.97 seconds
Started Aug 07 05:57:51 PM PDT 24
Finished Aug 07 06:00:59 PM PDT 24
Peak memory 207292 kb
Host smart-f7e3c231-e014-4ebd-85b6-0ec0f93621fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16532
60142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.1653260142
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.3398511368
Short name T1090
Test name
Test status
Simulation time 263012125 ps
CPU time 1.16 seconds
Started Aug 07 05:57:52 PM PDT 24
Finished Aug 07 05:57:53 PM PDT 24
Peak memory 207124 kb
Host smart-bb3ce3b5-2a97-4d8b-b9f1-e2bbd39789b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3398511368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.3398511368
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2682448677
Short name T1852
Test name
Test status
Simulation time 156070490 ps
CPU time 0.82 seconds
Started Aug 07 05:57:52 PM PDT 24
Finished Aug 07 05:57:53 PM PDT 24
Peak memory 206984 kb
Host smart-f2aca456-bb7c-4dc8-b579-b7d87b32691a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26824
48677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2682448677
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3429624377
Short name T549
Test name
Test status
Simulation time 163564162 ps
CPU time 0.93 seconds
Started Aug 07 05:57:57 PM PDT 24
Finished Aug 07 05:57:58 PM PDT 24
Peak memory 207004 kb
Host smart-2b2a4a9e-bebe-489a-aa5e-2f96eff5d8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34296
24377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3429624377
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.2610123575
Short name T2739
Test name
Test status
Simulation time 3440949877 ps
CPU time 95.3 seconds
Started Aug 07 05:57:50 PM PDT 24
Finished Aug 07 05:59:26 PM PDT 24
Peak memory 223664 kb
Host smart-43cc6cd1-d51c-4f79-9dba-fae81e39c4a7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2610123575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.2610123575
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3974249599
Short name T770
Test name
Test status
Simulation time 200076726 ps
CPU time 0.99 seconds
Started Aug 07 05:57:54 PM PDT 24
Finished Aug 07 05:57:55 PM PDT 24
Peak memory 207000 kb
Host smart-2065b347-1e84-46c0-b6c8-86191d81fbca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39742
49599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3974249599
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.902679129
Short name T67
Test name
Test status
Simulation time 441752945 ps
CPU time 1.36 seconds
Started Aug 07 05:57:56 PM PDT 24
Finished Aug 07 05:57:57 PM PDT 24
Peak memory 206980 kb
Host smart-6779ee98-4a49-45f9-a37c-a086b5ca1878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90267
9129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.902679129
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2024939222
Short name T3053
Test name
Test status
Simulation time 30180394660 ps
CPU time 59 seconds
Started Aug 07 05:57:56 PM PDT 24
Finished Aug 07 05:58:55 PM PDT 24
Peak memory 207272 kb
Host smart-fdd8099c-90d0-497f-82d0-6094b6f5590e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20249
39222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2024939222
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.731707773
Short name T927
Test name
Test status
Simulation time 8649231195 ps
CPU time 11.18 seconds
Started Aug 07 05:57:55 PM PDT 24
Finished Aug 07 05:58:06 PM PDT 24
Peak memory 207264 kb
Host smart-477cc2b5-0cab-4099-88c6-c165f08de9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73170
7773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.731707773
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.688896819
Short name T1913
Test name
Test status
Simulation time 2589629249 ps
CPU time 22.96 seconds
Started Aug 07 05:57:57 PM PDT 24
Finished Aug 07 05:58:20 PM PDT 24
Peak memory 217600 kb
Host smart-79ea9f72-161f-48ae-87c8-dc70d5d67ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68889
6819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.688896819
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2809368367
Short name T2014
Test name
Test status
Simulation time 2411024046 ps
CPU time 19.06 seconds
Started Aug 07 05:57:56 PM PDT 24
Finished Aug 07 05:58:15 PM PDT 24
Peak memory 223660 kb
Host smart-7dfb64cc-1860-4529-8129-13af124c715a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2809368367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2809368367
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.618716820
Short name T2961
Test name
Test status
Simulation time 251449636 ps
CPU time 1.03 seconds
Started Aug 07 05:57:56 PM PDT 24
Finished Aug 07 05:57:57 PM PDT 24
Peak memory 206968 kb
Host smart-80d3b4b4-fcc7-47b2-8a9c-a0ce107f4dc4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=618716820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.618716820
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3470510008
Short name T2940
Test name
Test status
Simulation time 230143117 ps
CPU time 1.04 seconds
Started Aug 07 05:58:01 PM PDT 24
Finished Aug 07 05:58:02 PM PDT 24
Peak memory 206988 kb
Host smart-32856b3b-bf53-4259-aacb-cef9e053c50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34705
10008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3470510008
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.2286187336
Short name T164
Test name
Test status
Simulation time 1669340662 ps
CPU time 47.16 seconds
Started Aug 07 05:58:02 PM PDT 24
Finished Aug 07 05:58:50 PM PDT 24
Peak memory 216852 kb
Host smart-cd9418f0-a756-4d0c-9e84-86e1ff14a442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22861
87336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.2286187336
Directory /workspace/0.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.1432112193
Short name T1601
Test name
Test status
Simulation time 2810472984 ps
CPU time 22.81 seconds
Started Aug 07 05:58:03 PM PDT 24
Finished Aug 07 05:58:26 PM PDT 24
Peak memory 223716 kb
Host smart-233cd96a-cd02-4904-9098-b706bb9fca86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1432112193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.1432112193
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.1293477606
Short name T667
Test name
Test status
Simulation time 2448830749 ps
CPU time 24.61 seconds
Started Aug 07 05:58:01 PM PDT 24
Finished Aug 07 05:58:26 PM PDT 24
Peak memory 217044 kb
Host smart-cc2adca8-a534-43fc-b813-3f0319e3bede
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1293477606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1293477606
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.2526018922
Short name T908
Test name
Test status
Simulation time 158358188 ps
CPU time 0.88 seconds
Started Aug 07 05:57:59 PM PDT 24
Finished Aug 07 05:58:00 PM PDT 24
Peak memory 207020 kb
Host smart-483f05af-413f-440f-bc60-cf97121a246f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2526018922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.2526018922
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.4278925260
Short name T1714
Test name
Test status
Simulation time 150245963 ps
CPU time 0.85 seconds
Started Aug 07 05:58:01 PM PDT 24
Finished Aug 07 05:58:02 PM PDT 24
Peak memory 207004 kb
Host smart-784c3dd5-a5ab-408f-9570-64ab2e3be701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42789
25260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.4278925260
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3641785367
Short name T66
Test name
Test status
Simulation time 485750930 ps
CPU time 1.46 seconds
Started Aug 07 05:58:00 PM PDT 24
Finished Aug 07 05:58:02 PM PDT 24
Peak memory 206952 kb
Host smart-0f59f4a0-ca63-4926-a17f-72a773f3e72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36417
85367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3641785367
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2828501644
Short name T505
Test name
Test status
Simulation time 189254709 ps
CPU time 0.92 seconds
Started Aug 07 05:58:05 PM PDT 24
Finished Aug 07 05:58:06 PM PDT 24
Peak memory 207004 kb
Host smart-961a7956-c7ee-4f34-bdfa-3df99cf1171d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285
01644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2828501644
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2975323276
Short name T2575
Test name
Test status
Simulation time 195094048 ps
CPU time 0.86 seconds
Started Aug 07 05:58:01 PM PDT 24
Finished Aug 07 05:58:02 PM PDT 24
Peak memory 206988 kb
Host smart-ccb5a86d-7e6c-4224-a306-0f06dc837e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29753
23276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2975323276
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3069690401
Short name T1728
Test name
Test status
Simulation time 155105888 ps
CPU time 0.83 seconds
Started Aug 07 05:57:59 PM PDT 24
Finished Aug 07 05:58:00 PM PDT 24
Peak memory 206904 kb
Host smart-a1a25970-48a6-4326-8002-7b5661058b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30696
90401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3069690401
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3260654153
Short name T2578
Test name
Test status
Simulation time 161995682 ps
CPU time 0.85 seconds
Started Aug 07 05:58:01 PM PDT 24
Finished Aug 07 05:58:02 PM PDT 24
Peak memory 207012 kb
Host smart-8cd73512-925f-470e-8c79-8013d3c65cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32606
54153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3260654153
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1530760394
Short name T2033
Test name
Test status
Simulation time 190326144 ps
CPU time 0.92 seconds
Started Aug 07 05:58:05 PM PDT 24
Finished Aug 07 05:58:06 PM PDT 24
Peak memory 206964 kb
Host smart-b3045d9a-2bec-46d1-82ab-ab49d03c5655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15307
60394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1530760394
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.2150507324
Short name T1566
Test name
Test status
Simulation time 224056128 ps
CPU time 1.04 seconds
Started Aug 07 05:58:08 PM PDT 24
Finished Aug 07 05:58:09 PM PDT 24
Peak memory 207016 kb
Host smart-fdf03622-e2ba-4f05-b60e-f1fdfbacc2f9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2150507324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.2150507324
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1831705356
Short name T2605
Test name
Test status
Simulation time 241472916 ps
CPU time 1.1 seconds
Started Aug 07 05:58:04 PM PDT 24
Finished Aug 07 05:58:05 PM PDT 24
Peak memory 206964 kb
Host smart-9e79f9ce-70a8-41b5-872a-6366bb2bfeb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18317
05356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1831705356
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.503713495
Short name T1972
Test name
Test status
Simulation time 245797830 ps
CPU time 1.03 seconds
Started Aug 07 05:58:04 PM PDT 24
Finished Aug 07 05:58:05 PM PDT 24
Peak memory 206992 kb
Host smart-816b8cde-692a-4aa3-85fc-76bbc91ace89
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=503713495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.503713495
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2407874667
Short name T220
Test name
Test status
Simulation time 255833113 ps
CPU time 1.04 seconds
Started Aug 07 05:58:05 PM PDT 24
Finished Aug 07 05:58:06 PM PDT 24
Peak memory 206964 kb
Host smart-ac77023f-8f4e-4d1b-85ba-facd30773ef2
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2407874667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.2407874667
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2711716366
Short name T3090
Test name
Test status
Simulation time 161260605 ps
CPU time 0.83 seconds
Started Aug 07 05:58:07 PM PDT 24
Finished Aug 07 05:58:08 PM PDT 24
Peak memory 206956 kb
Host smart-bb0736bd-7227-4a3d-ab5d-ed079ee68f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27117
16366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2711716366
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3169354419
Short name T2159
Test name
Test status
Simulation time 63016601 ps
CPU time 0.72 seconds
Started Aug 07 05:58:05 PM PDT 24
Finished Aug 07 05:58:06 PM PDT 24
Peak memory 206984 kb
Host smart-38322e9d-d2d6-43ca-a7e9-ee9b5c537fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31693
54419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3169354419
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.4115875871
Short name T1964
Test name
Test status
Simulation time 17016135212 ps
CPU time 44.51 seconds
Started Aug 07 05:58:08 PM PDT 24
Finished Aug 07 05:58:52 PM PDT 24
Peak memory 215508 kb
Host smart-89dc7ae9-33b5-4af5-bb7a-bdd6a5dcb095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41158
75871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.4115875871
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1663491699
Short name T1781
Test name
Test status
Simulation time 158188546 ps
CPU time 0.83 seconds
Started Aug 07 05:58:07 PM PDT 24
Finished Aug 07 05:58:08 PM PDT 24
Peak memory 206980 kb
Host smart-545d9a09-b19c-4bf7-b1c3-e57bf463e944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16634
91699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1663491699
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1106828903
Short name T1809
Test name
Test status
Simulation time 221875902 ps
CPU time 0.94 seconds
Started Aug 07 05:58:04 PM PDT 24
Finished Aug 07 05:58:05 PM PDT 24
Peak memory 206888 kb
Host smart-7bae6bf4-2dad-4a99-8b87-baf845eac013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11068
28903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1106828903
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.4076682097
Short name T2313
Test name
Test status
Simulation time 6222111319 ps
CPU time 21.05 seconds
Started Aug 07 05:58:12 PM PDT 24
Finished Aug 07 05:58:33 PM PDT 24
Peak memory 217688 kb
Host smart-11344db2-45de-46a5-b545-f1f0af38860e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4076682097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.4076682097
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.3867587049
Short name T2620
Test name
Test status
Simulation time 5316607509 ps
CPU time 17.68 seconds
Started Aug 07 05:58:15 PM PDT 24
Finished Aug 07 05:58:32 PM PDT 24
Peak memory 215452 kb
Host smart-710e138d-4dfb-4b20-968e-6ddb6fc9270a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867587049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3867587049
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3012561612
Short name T2101
Test name
Test status
Simulation time 212658183 ps
CPU time 0.93 seconds
Started Aug 07 05:58:13 PM PDT 24
Finished Aug 07 05:58:14 PM PDT 24
Peak memory 206992 kb
Host smart-b543977e-78fb-483b-a8d6-8bcc0c6503ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30125
61612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3012561612
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.2573598575
Short name T2865
Test name
Test status
Simulation time 163888717 ps
CPU time 0.88 seconds
Started Aug 07 05:58:15 PM PDT 24
Finished Aug 07 05:58:16 PM PDT 24
Peak memory 206980 kb
Host smart-0684f974-1f6e-4b59-82ac-8969fd41aef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25735
98575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.2573598575
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.3511259242
Short name T2242
Test name
Test status
Simulation time 20161030732 ps
CPU time 25.54 seconds
Started Aug 07 05:58:14 PM PDT 24
Finished Aug 07 05:58:39 PM PDT 24
Peak memory 207052 kb
Host smart-c49fad4e-f377-4e12-818c-0e1f2bcb1250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35112
59242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.3511259242
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1726439468
Short name T773
Test name
Test status
Simulation time 147995678 ps
CPU time 0.84 seconds
Started Aug 07 05:58:09 PM PDT 24
Finished Aug 07 05:58:10 PM PDT 24
Peak memory 206920 kb
Host smart-1d56499e-f929-4421-84ee-36d7e6f539a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17264
39468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1726439468
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.1824276863
Short name T1760
Test name
Test status
Simulation time 262927818 ps
CPU time 1.1 seconds
Started Aug 07 05:58:13 PM PDT 24
Finished Aug 07 05:58:14 PM PDT 24
Peak memory 206984 kb
Host smart-8b3f5d20-cb04-4dbc-ad49-4d3fb425ab88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18242
76863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.1824276863
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.17086075
Short name T3050
Test name
Test status
Simulation time 421000217 ps
CPU time 1.46 seconds
Started Aug 07 05:58:17 PM PDT 24
Finished Aug 07 05:58:18 PM PDT 24
Peak memory 206972 kb
Host smart-8ed6ec9b-8ef1-4513-bbcb-7121fbbd6f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17086
075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.17086075
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.273922863
Short name T2931
Test name
Test status
Simulation time 241645008 ps
CPU time 1 seconds
Started Aug 07 05:58:17 PM PDT 24
Finished Aug 07 05:58:18 PM PDT 24
Peak memory 206980 kb
Host smart-66b8af41-b85d-4e20-be44-a9218046209e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27392
2863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.273922863
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2335270210
Short name T1141
Test name
Test status
Simulation time 211315316 ps
CPU time 0.94 seconds
Started Aug 07 05:58:15 PM PDT 24
Finished Aug 07 05:58:16 PM PDT 24
Peak memory 206968 kb
Host smart-96ef5dfe-08d5-4722-839a-b2308d22e47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23352
70210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2335270210
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2705966864
Short name T2853
Test name
Test status
Simulation time 203054815 ps
CPU time 1.01 seconds
Started Aug 07 05:58:16 PM PDT 24
Finished Aug 07 05:58:17 PM PDT 24
Peak memory 206900 kb
Host smart-7a3a9c8f-c282-47e4-8c9e-aa477b85f909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27059
66864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2705966864
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.2635725085
Short name T1808
Test name
Test status
Simulation time 2565007512 ps
CPU time 72.42 seconds
Started Aug 07 05:58:12 PM PDT 24
Finished Aug 07 05:59:25 PM PDT 24
Peak memory 217060 kb
Host smart-39d34f66-1cf1-424d-a67d-2197a83ccad0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2635725085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2635725085
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3307393718
Short name T863
Test name
Test status
Simulation time 177649316 ps
CPU time 0.85 seconds
Started Aug 07 05:58:16 PM PDT 24
Finished Aug 07 05:58:17 PM PDT 24
Peak memory 206980 kb
Host smart-2ecdbd14-59ba-42e2-990a-aa23392d20db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33073
93718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3307393718
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3314609832
Short name T1941
Test name
Test status
Simulation time 173397688 ps
CPU time 0.86 seconds
Started Aug 07 05:58:14 PM PDT 24
Finished Aug 07 05:58:15 PM PDT 24
Peak memory 207008 kb
Host smart-23a0dfe7-bea2-4eba-b94c-c9af1282f5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33146
09832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3314609832
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1079069305
Short name T508
Test name
Test status
Simulation time 1208861630 ps
CPU time 2.8 seconds
Started Aug 07 05:58:14 PM PDT 24
Finished Aug 07 05:58:17 PM PDT 24
Peak memory 207044 kb
Host smart-486376c2-59f4-4687-b2ae-65db9c4dbf20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10790
69305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1079069305
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.3127570890
Short name T2648
Test name
Test status
Simulation time 3886730968 ps
CPU time 113.61 seconds
Started Aug 07 05:58:15 PM PDT 24
Finished Aug 07 06:00:09 PM PDT 24
Peak memory 216748 kb
Host smart-7b35d161-dd48-42e2-9a85-98f809030191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31275
70890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3127570890
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2071138685
Short name T76
Test name
Test status
Simulation time 7570696009 ps
CPU time 54.45 seconds
Started Aug 07 05:58:19 PM PDT 24
Finished Aug 07 05:59:13 PM PDT 24
Peak memory 223680 kb
Host smart-8c107854-47bb-4e6a-adf6-574b524c6be7
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071138685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2071138685
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.1456234835
Short name T653
Test name
Test status
Simulation time 1611707644 ps
CPU time 36.42 seconds
Started Aug 07 05:57:53 PM PDT 24
Finished Aug 07 05:58:30 PM PDT 24
Peak memory 207156 kb
Host smart-c37cb7ae-9bdb-403a-9a92-771b61a2b7c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456234835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.1456234835
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.1012472461
Short name T1371
Test name
Test status
Simulation time 93856671 ps
CPU time 0.73 seconds
Started Aug 07 05:58:40 PM PDT 24
Finished Aug 07 05:58:41 PM PDT 24
Peak memory 207080 kb
Host smart-f95953e1-a2a8-4d93-b6ce-f2531de0a33b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1012472461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1012472461
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1419642030
Short name T1576
Test name
Test status
Simulation time 9260411216 ps
CPU time 11.23 seconds
Started Aug 07 05:58:20 PM PDT 24
Finished Aug 07 05:58:32 PM PDT 24
Peak memory 207288 kb
Host smart-4fe6d98e-7bb0-47af-82ff-3e4d8a56e228
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419642030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.1419642030
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.74616279
Short name T1377
Test name
Test status
Simulation time 19970128171 ps
CPU time 24.27 seconds
Started Aug 07 05:58:23 PM PDT 24
Finished Aug 07 05:58:48 PM PDT 24
Peak memory 207292 kb
Host smart-5658724b-528e-40ae-b773-4f3f2a89de6f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=74616279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.74616279
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.991349232
Short name T1487
Test name
Test status
Simulation time 29669206694 ps
CPU time 36.26 seconds
Started Aug 07 05:58:20 PM PDT 24
Finished Aug 07 05:58:56 PM PDT 24
Peak memory 207220 kb
Host smart-ec59b80b-5e09-4ef4-b0e2-5fa626853046
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991349232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon
_wake_resume.991349232
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3000696478
Short name T2863
Test name
Test status
Simulation time 158931014 ps
CPU time 0.83 seconds
Started Aug 07 05:58:20 PM PDT 24
Finished Aug 07 05:58:21 PM PDT 24
Peak memory 207008 kb
Host smart-862d4e8e-b144-49bd-a264-4c6db61d5a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30006
96478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3000696478
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.968048993
Short name T104
Test name
Test status
Simulation time 134202785 ps
CPU time 0.88 seconds
Started Aug 07 05:58:20 PM PDT 24
Finished Aug 07 05:58:21 PM PDT 24
Peak memory 206924 kb
Host smart-3ad829c1-d364-4d60-a253-8eb954a66bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96804
8993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.968048993
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2823811533
Short name T1530
Test name
Test status
Simulation time 151169572 ps
CPU time 0.89 seconds
Started Aug 07 05:58:20 PM PDT 24
Finished Aug 07 05:58:21 PM PDT 24
Peak memory 206964 kb
Host smart-bcf08ebe-dcaf-4c29-bbf2-91c00d5469d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28238
11533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2823811533
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.281353968
Short name T2117
Test name
Test status
Simulation time 473499198 ps
CPU time 1.55 seconds
Started Aug 07 05:58:19 PM PDT 24
Finished Aug 07 05:58:21 PM PDT 24
Peak memory 206904 kb
Host smart-f576f4fe-e1a4-4886-9b10-6eaff0c7699f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28135
3968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.281353968
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.3178150909
Short name T3035
Test name
Test status
Simulation time 344978667 ps
CPU time 1.25 seconds
Started Aug 07 05:59:05 PM PDT 24
Finished Aug 07 05:59:07 PM PDT 24
Peak memory 207012 kb
Host smart-d1acc91d-2944-44fe-9b88-321bef887703
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3178150909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3178150909
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.716394168
Short name T414
Test name
Test status
Simulation time 42220003208 ps
CPU time 66.7 seconds
Started Aug 07 05:58:20 PM PDT 24
Finished Aug 07 05:59:26 PM PDT 24
Peak memory 207352 kb
Host smart-b8653525-f61d-47a5-bd85-89fba86b99b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71639
4168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.716394168
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.416998319
Short name T858
Test name
Test status
Simulation time 5258919822 ps
CPU time 48.37 seconds
Started Aug 07 05:58:23 PM PDT 24
Finished Aug 07 05:59:11 PM PDT 24
Peak memory 207268 kb
Host smart-b0decffe-5b84-4e75-a5ff-c31406fe08ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416998319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.416998319
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2833199373
Short name T2414
Test name
Test status
Simulation time 1404700156 ps
CPU time 2.68 seconds
Started Aug 07 05:58:21 PM PDT 24
Finished Aug 07 05:58:24 PM PDT 24
Peak memory 206948 kb
Host smart-96864a93-ab0f-4fc7-afff-2faba0771a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28331
99373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2833199373
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1788297601
Short name T1552
Test name
Test status
Simulation time 151294583 ps
CPU time 0.87 seconds
Started Aug 07 05:58:19 PM PDT 24
Finished Aug 07 05:58:20 PM PDT 24
Peak memory 206956 kb
Host smart-bc39fa4a-0f05-4d7a-88cd-51b19c9d801c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17882
97601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1788297601
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.2540806563
Short name T833
Test name
Test status
Simulation time 60575274 ps
CPU time 0.71 seconds
Started Aug 07 05:58:20 PM PDT 24
Finished Aug 07 05:58:21 PM PDT 24
Peak memory 206932 kb
Host smart-7ac3221a-4fc9-4d7f-80a4-7a4b238e0044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25408
06563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2540806563
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.483736798
Short name T1937
Test name
Test status
Simulation time 919965625 ps
CPU time 2.2 seconds
Started Aug 07 05:58:25 PM PDT 24
Finished Aug 07 05:58:27 PM PDT 24
Peak memory 207128 kb
Host smart-6baad78f-3474-415c-937f-27886c7052df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48373
6798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.483736798
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_types.2862507326
Short name T2734
Test name
Test status
Simulation time 353939646 ps
CPU time 1.15 seconds
Started Aug 07 05:58:25 PM PDT 24
Finished Aug 07 05:58:26 PM PDT 24
Peak memory 206936 kb
Host smart-db83fd71-da60-44f8-b58c-a51f1bccd2be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2862507326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.2862507326
Directory /workspace/1.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2279036034
Short name T2433
Test name
Test status
Simulation time 192844330 ps
CPU time 2.32 seconds
Started Aug 07 05:58:26 PM PDT 24
Finished Aug 07 05:58:28 PM PDT 24
Peak memory 207172 kb
Host smart-eaa83d13-c1c8-41a9-bff9-3191c5d64a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22790
36034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2279036034
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.282355027
Short name T2103
Test name
Test status
Simulation time 102199498579 ps
CPU time 150.15 seconds
Started Aug 07 05:58:43 PM PDT 24
Finished Aug 07 06:01:13 PM PDT 24
Peak memory 207328 kb
Host smart-f7310398-6577-4928-be29-701922b8b67a
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=282355027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.282355027
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.3105687528
Short name T1770
Test name
Test status
Simulation time 106144977476 ps
CPU time 174.46 seconds
Started Aug 07 05:58:23 PM PDT 24
Finished Aug 07 06:01:17 PM PDT 24
Peak memory 207316 kb
Host smart-8f81c854-388e-4425-892d-fd0dfdac80e4
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3105687528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.3105687528
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.4236382875
Short name T2708
Test name
Test status
Simulation time 120998621743 ps
CPU time 196.45 seconds
Started Aug 07 05:58:27 PM PDT 24
Finished Aug 07 06:01:43 PM PDT 24
Peak memory 207316 kb
Host smart-9c6c6f0f-9ade-425e-b7da-d7c5b25ade65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236382875 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.4236382875
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.576897023
Short name T1272
Test name
Test status
Simulation time 114149323125 ps
CPU time 216.81 seconds
Started Aug 07 05:58:23 PM PDT 24
Finished Aug 07 06:02:00 PM PDT 24
Peak memory 207288 kb
Host smart-f4a74d6b-d1a4-473a-806b-63432e44d077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57689
7023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.576897023
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2890147748
Short name T2541
Test name
Test status
Simulation time 176878435 ps
CPU time 0.93 seconds
Started Aug 07 05:58:26 PM PDT 24
Finished Aug 07 05:58:27 PM PDT 24
Peak memory 206968 kb
Host smart-2fe902ca-16f1-4ffb-b248-98097c1e5250
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2890147748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2890147748
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3522616952
Short name T1822
Test name
Test status
Simulation time 173148991 ps
CPU time 0.87 seconds
Started Aug 07 05:58:25 PM PDT 24
Finished Aug 07 05:58:26 PM PDT 24
Peak memory 206944 kb
Host smart-c88399d6-66c9-4690-8338-cba51274cd4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35226
16952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3522616952
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2956556564
Short name T1432
Test name
Test status
Simulation time 173842460 ps
CPU time 0.9 seconds
Started Aug 07 05:58:42 PM PDT 24
Finished Aug 07 05:58:43 PM PDT 24
Peak memory 206992 kb
Host smart-86ff112d-48f0-45f8-8517-aab90c7867ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29565
56564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2956556564
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2634665894
Short name T2561
Test name
Test status
Simulation time 3066274743 ps
CPU time 24.72 seconds
Started Aug 07 05:58:22 PM PDT 24
Finished Aug 07 05:58:47 PM PDT 24
Peak memory 223624 kb
Host smart-3f14f140-8c60-4600-84c8-18269aef76f8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2634665894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2634665894
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.461443566
Short name T545
Test name
Test status
Simulation time 3816605593 ps
CPU time 48.16 seconds
Started Aug 07 05:58:26 PM PDT 24
Finished Aug 07 05:59:14 PM PDT 24
Peak memory 207236 kb
Host smart-c97873b6-9523-4661-b1f5-de16543c8e77
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=461443566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.461443566
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.2043423144
Short name T1630
Test name
Test status
Simulation time 256000734 ps
CPU time 1.06 seconds
Started Aug 07 05:58:25 PM PDT 24
Finished Aug 07 05:58:26 PM PDT 24
Peak memory 206884 kb
Host smart-648c63d3-bef0-4834-ac7c-e27b32403489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20434
23144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2043423144
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1930583803
Short name T575
Test name
Test status
Simulation time 4463477867 ps
CPU time 6.84 seconds
Started Aug 07 05:58:25 PM PDT 24
Finished Aug 07 05:58:32 PM PDT 24
Peak memory 207284 kb
Host smart-fc15ce81-e42b-4612-8125-64268f6134c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19305
83803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1930583803
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.1059730476
Short name T1066
Test name
Test status
Simulation time 2750234208 ps
CPU time 76.44 seconds
Started Aug 07 05:58:31 PM PDT 24
Finished Aug 07 05:59:48 PM PDT 24
Peak memory 215436 kb
Host smart-9405ef6b-cc27-41e3-8e95-4165994b4989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10597
30476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.1059730476
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1307863979
Short name T3101
Test name
Test status
Simulation time 3175714135 ps
CPU time 32.79 seconds
Started Aug 07 05:58:29 PM PDT 24
Finished Aug 07 05:59:02 PM PDT 24
Peak memory 217092 kb
Host smart-5395ada9-f5c2-4182-94ac-5b5b641a65d0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1307863979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1307863979
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3492056426
Short name T707
Test name
Test status
Simulation time 235550083 ps
CPU time 1.03 seconds
Started Aug 07 05:58:29 PM PDT 24
Finished Aug 07 05:58:31 PM PDT 24
Peak memory 206952 kb
Host smart-cdb8f2d8-8034-4396-9159-99807dccf03e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3492056426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3492056426
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1433189083
Short name T744
Test name
Test status
Simulation time 191312045 ps
CPU time 0.98 seconds
Started Aug 07 05:58:30 PM PDT 24
Finished Aug 07 05:58:31 PM PDT 24
Peak memory 206960 kb
Host smart-a5e04a07-4412-44de-852a-539b8d8bccf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14331
89083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1433189083
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.4030998949
Short name T1406
Test name
Test status
Simulation time 1563928475 ps
CPU time 14.41 seconds
Started Aug 07 05:58:29 PM PDT 24
Finished Aug 07 05:58:44 PM PDT 24
Peak memory 223592 kb
Host smart-ded7876d-7e33-4b07-94e0-947663cd502c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40309
98949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.4030998949
Directory /workspace/1.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.798262740
Short name T124
Test name
Test status
Simulation time 1955170738 ps
CPU time 21.61 seconds
Started Aug 07 05:58:42 PM PDT 24
Finished Aug 07 05:59:04 PM PDT 24
Peak memory 223560 kb
Host smart-371fc4fc-8871-4f7e-b66e-f2e77ac1cf74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=798262740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.798262740
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.120160888
Short name T1979
Test name
Test status
Simulation time 3491565840 ps
CPU time 34.19 seconds
Started Aug 07 05:58:31 PM PDT 24
Finished Aug 07 05:59:05 PM PDT 24
Peak memory 215480 kb
Host smart-57e6b7e2-b40f-4260-91d2-ece6eb313577
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=120160888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.120160888
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1055265141
Short name T602
Test name
Test status
Simulation time 162580983 ps
CPU time 0.86 seconds
Started Aug 07 05:58:33 PM PDT 24
Finished Aug 07 05:58:34 PM PDT 24
Peak memory 206988 kb
Host smart-bfb41c9e-da8a-44cc-8a79-74e228c22adc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1055265141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1055265141
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.4183207263
Short name T2582
Test name
Test status
Simulation time 177313795 ps
CPU time 0.83 seconds
Started Aug 07 05:58:31 PM PDT 24
Finished Aug 07 05:58:32 PM PDT 24
Peak memory 207020 kb
Host smart-91193d38-b5f0-415b-9da7-127ca871c869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41832
07263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.4183207263
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3926208781
Short name T749
Test name
Test status
Simulation time 176710414 ps
CPU time 0.91 seconds
Started Aug 07 05:58:32 PM PDT 24
Finished Aug 07 05:58:33 PM PDT 24
Peak memory 206984 kb
Host smart-532482b3-ec35-4335-a328-c0df72cf4afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39262
08781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3926208781
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2843891137
Short name T2966
Test name
Test status
Simulation time 178068433 ps
CPU time 0.9 seconds
Started Aug 07 05:58:31 PM PDT 24
Finished Aug 07 05:58:32 PM PDT 24
Peak memory 207016 kb
Host smart-e59c0323-5da8-429a-bfef-1247b14ff7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28438
91137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2843891137
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2998122007
Short name T2957
Test name
Test status
Simulation time 218101203 ps
CPU time 0.9 seconds
Started Aug 07 05:58:28 PM PDT 24
Finished Aug 07 05:58:29 PM PDT 24
Peak memory 206976 kb
Host smart-533059cc-091d-4b32-bd35-38643c472067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29981
22007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2998122007
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2435194340
Short name T1723
Test name
Test status
Simulation time 154971669 ps
CPU time 0.85 seconds
Started Aug 07 05:58:30 PM PDT 24
Finished Aug 07 05:58:31 PM PDT 24
Peak memory 206992 kb
Host smart-2ac1d861-a11a-4d1b-9c9e-dcfeee9b2f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24351
94340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2435194340
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.2611668774
Short name T2152
Test name
Test status
Simulation time 237971396 ps
CPU time 1.02 seconds
Started Aug 07 05:58:27 PM PDT 24
Finished Aug 07 05:58:29 PM PDT 24
Peak memory 207028 kb
Host smart-b7516afe-b28d-4096-bae7-fd32e8603427
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2611668774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.2611668774
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3235685995
Short name T221
Test name
Test status
Simulation time 208194116 ps
CPU time 0.9 seconds
Started Aug 07 05:58:31 PM PDT 24
Finished Aug 07 05:58:32 PM PDT 24
Peak memory 206912 kb
Host smart-b340ab9c-4048-496a-a928-ba25475cade3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32356
85995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3235685995
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.763536805
Short name T1687
Test name
Test status
Simulation time 153391399 ps
CPU time 0.82 seconds
Started Aug 07 05:58:31 PM PDT 24
Finished Aug 07 05:58:32 PM PDT 24
Peak memory 206988 kb
Host smart-56c1e4c2-576e-4c4a-aec3-21e6eaff4955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76353
6805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.763536805
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3892317265
Short name T2334
Test name
Test status
Simulation time 46760774 ps
CPU time 0.73 seconds
Started Aug 07 05:58:28 PM PDT 24
Finished Aug 07 05:58:29 PM PDT 24
Peak memory 206952 kb
Host smart-7aedaf85-c74a-4098-b375-edd1c943df69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38923
17265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3892317265
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.4027554350
Short name T2857
Test name
Test status
Simulation time 17218832328 ps
CPU time 47.29 seconds
Started Aug 07 05:58:30 PM PDT 24
Finished Aug 07 05:59:17 PM PDT 24
Peak memory 223752 kb
Host smart-626b9aa0-c051-4646-a07f-fccbe499dfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40275
54350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.4027554350
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.4263941789
Short name T2527
Test name
Test status
Simulation time 222821406 ps
CPU time 0.93 seconds
Started Aug 07 05:58:36 PM PDT 24
Finished Aug 07 05:58:38 PM PDT 24
Peak memory 206996 kb
Host smart-8afacd64-0be4-4d95-a2c8-2700a403a2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42639
41789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.4263941789
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2102338767
Short name T1814
Test name
Test status
Simulation time 244594304 ps
CPU time 1 seconds
Started Aug 07 05:58:36 PM PDT 24
Finished Aug 07 05:58:37 PM PDT 24
Peak memory 206976 kb
Host smart-a2e07c84-c188-4f56-a3a9-9acbf1b19c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21023
38767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2102338767
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2986785427
Short name T940
Test name
Test status
Simulation time 5834730560 ps
CPU time 22.32 seconds
Started Aug 07 05:58:33 PM PDT 24
Finished Aug 07 05:58:56 PM PDT 24
Peak memory 223688 kb
Host smart-4c874dc1-c65d-4d6d-ab9f-baf305da7a38
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986785427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2986785427
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.1487188512
Short name T1318
Test name
Test status
Simulation time 3026119672 ps
CPU time 17.77 seconds
Started Aug 07 05:58:35 PM PDT 24
Finished Aug 07 05:58:53 PM PDT 24
Peak memory 218136 kb
Host smart-8b75e099-3257-43a3-b2d8-77f0712536d5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1487188512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.1487188512
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.2668637786
Short name T2699
Test name
Test status
Simulation time 13167481199 ps
CPU time 91.15 seconds
Started Aug 07 05:58:36 PM PDT 24
Finished Aug 07 06:00:07 PM PDT 24
Peak memory 217736 kb
Host smart-b890fc6c-cd5e-408c-8b45-dac38a2903f3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668637786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.2668637786
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.1717149416
Short name T1889
Test name
Test status
Simulation time 165605545 ps
CPU time 0.85 seconds
Started Aug 07 05:58:34 PM PDT 24
Finished Aug 07 05:58:35 PM PDT 24
Peak memory 206964 kb
Host smart-f394f1e1-eb99-4581-a407-0469ee951060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17171
49416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.1717149416
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.1723496850
Short name T3087
Test name
Test status
Simulation time 169813449 ps
CPU time 0.91 seconds
Started Aug 07 05:58:40 PM PDT 24
Finished Aug 07 05:58:41 PM PDT 24
Peak memory 206980 kb
Host smart-af859d0e-f46a-465f-9a8c-fd7bce1e8ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17234
96850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.1723496850
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_resume_link_active.2845796480
Short name T113
Test name
Test status
Simulation time 20164170689 ps
CPU time 25.33 seconds
Started Aug 07 05:58:35 PM PDT 24
Finished Aug 07 05:59:01 PM PDT 24
Peak memory 207056 kb
Host smart-1f3d18ae-bdb9-4e9c-892e-54700ca0f81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28457
96480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.2845796480
Directory /workspace/1.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3030227843
Short name T1956
Test name
Test status
Simulation time 160571473 ps
CPU time 0.85 seconds
Started Aug 07 05:58:37 PM PDT 24
Finished Aug 07 05:58:38 PM PDT 24
Peak memory 206984 kb
Host smart-6853e5b4-d875-4524-b981-92fe67715776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30302
27843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3030227843
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_full.2352302166
Short name T933
Test name
Test status
Simulation time 370065666 ps
CPU time 1.21 seconds
Started Aug 07 05:58:37 PM PDT 24
Finished Aug 07 05:58:39 PM PDT 24
Peak memory 207188 kb
Host smart-a3375d1f-8a85-4ad5-8f45-7bbcd7be6666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23523
02166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.2352302166
Directory /workspace/1.usbdev_rx_full/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2822269502
Short name T2304
Test name
Test status
Simulation time 187380979 ps
CPU time 0.91 seconds
Started Aug 07 05:58:40 PM PDT 24
Finished Aug 07 05:58:41 PM PDT 24
Peak memory 206980 kb
Host smart-2dc084d6-d767-48ed-b513-78d5c6b47bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28222
69502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2822269502
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.4041689558
Short name T574
Test name
Test status
Simulation time 439692406 ps
CPU time 1.56 seconds
Started Aug 07 05:58:36 PM PDT 24
Finished Aug 07 05:58:37 PM PDT 24
Peak memory 206912 kb
Host smart-24f23589-5bc1-4cde-bffc-6ee03b7c2871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40416
89558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.4041689558
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.1252744842
Short name T196
Test name
Test status
Simulation time 207209661 ps
CPU time 0.9 seconds
Started Aug 07 05:58:34 PM PDT 24
Finished Aug 07 05:58:35 PM PDT 24
Peak memory 207016 kb
Host smart-407eb3b7-bfb7-4333-b95a-b775f0c79a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12527
44842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.1252744842
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3946022923
Short name T1228
Test name
Test status
Simulation time 158033891 ps
CPU time 0.86 seconds
Started Aug 07 05:58:37 PM PDT 24
Finished Aug 07 05:58:38 PM PDT 24
Peak memory 206976 kb
Host smart-15b97dd5-01fa-4035-8636-7f837c9434e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39460
22923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3946022923
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2601472563
Short name T2187
Test name
Test status
Simulation time 169967828 ps
CPU time 0.89 seconds
Started Aug 07 05:58:34 PM PDT 24
Finished Aug 07 05:58:35 PM PDT 24
Peak memory 206960 kb
Host smart-cc42b24b-b704-417b-97ad-9584a6175502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26014
72563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2601472563
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3837687150
Short name T1990
Test name
Test status
Simulation time 232736867 ps
CPU time 0.97 seconds
Started Aug 07 05:58:35 PM PDT 24
Finished Aug 07 05:58:36 PM PDT 24
Peak memory 207008 kb
Host smart-0706d8eb-91ff-460c-9b67-e36fca77a770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38376
87150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3837687150
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2144863905
Short name T820
Test name
Test status
Simulation time 1988060463 ps
CPU time 15.02 seconds
Started Aug 07 05:58:40 PM PDT 24
Finished Aug 07 05:58:55 PM PDT 24
Peak memory 217084 kb
Host smart-f6fde8f8-b971-4bf5-968a-efd9b42b6b9b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2144863905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2144863905
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3674039248
Short name T937
Test name
Test status
Simulation time 241429425 ps
CPU time 0.92 seconds
Started Aug 07 05:58:35 PM PDT 24
Finished Aug 07 05:58:36 PM PDT 24
Peak memory 206984 kb
Host smart-3c29e520-3acb-4359-8ed7-933653321d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36740
39248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3674039248
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.588309775
Short name T2698
Test name
Test status
Simulation time 1329436444 ps
CPU time 3.18 seconds
Started Aug 07 05:58:40 PM PDT 24
Finished Aug 07 05:58:44 PM PDT 24
Peak memory 207120 kb
Host smart-e188bbfd-54de-4ea0-88ce-311c254c07c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58830
9775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.588309775
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.493186012
Short name T1678
Test name
Test status
Simulation time 2480190028 ps
CPU time 69.68 seconds
Started Aug 07 05:58:40 PM PDT 24
Finished Aug 07 05:59:50 PM PDT 24
Peak memory 217104 kb
Host smart-9e0ec269-032b-4df0-83df-2a337bc059cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49318
6012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.493186012
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2595218729
Short name T126
Test name
Test status
Simulation time 11315713558 ps
CPU time 89.55 seconds
Started Aug 07 05:58:41 PM PDT 24
Finished Aug 07 06:00:10 PM PDT 24
Peak memory 223656 kb
Host smart-8c4da41d-ee84-43e1-9947-66277db454ac
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595218729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.2595218729
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.3745723540
Short name T762
Test name
Test status
Simulation time 695452082 ps
CPU time 14.65 seconds
Started Aug 07 05:58:20 PM PDT 24
Finished Aug 07 05:58:35 PM PDT 24
Peak memory 207036 kb
Host smart-df5f54ec-5329-4e2e-8df9-3eec096454e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745723540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.3745723540
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.1351244064
Short name T3127
Test name
Test status
Simulation time 34892735 ps
CPU time 0.66 seconds
Started Aug 07 06:01:03 PM PDT 24
Finished Aug 07 06:01:04 PM PDT 24
Peak memory 206952 kb
Host smart-3844a442-2750-42f3-8baf-708e18af9e57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1351244064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.1351244064
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.132661196
Short name T965
Test name
Test status
Simulation time 10565857692 ps
CPU time 16.66 seconds
Started Aug 07 06:00:50 PM PDT 24
Finished Aug 07 06:01:07 PM PDT 24
Peak memory 207168 kb
Host smart-4310a30e-af37-4960-b785-bb6fa919c93d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132661196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_ao
n_wake_disconnect.132661196
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1134958985
Short name T2270
Test name
Test status
Simulation time 19296817797 ps
CPU time 25.42 seconds
Started Aug 07 06:00:48 PM PDT 24
Finished Aug 07 06:01:14 PM PDT 24
Peak memory 207304 kb
Host smart-26aa16c1-7721-4128-b544-0f9ba7951078
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134958985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1134958985
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.2163509103
Short name T850
Test name
Test status
Simulation time 29619636559 ps
CPU time 43.61 seconds
Started Aug 07 06:00:48 PM PDT 24
Finished Aug 07 06:01:31 PM PDT 24
Peak memory 207256 kb
Host smart-9045e269-71f4-4280-a5d5-0884604c1a5a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163509103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.2163509103
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2940480051
Short name T2087
Test name
Test status
Simulation time 158709865 ps
CPU time 0.88 seconds
Started Aug 07 06:00:50 PM PDT 24
Finished Aug 07 06:00:52 PM PDT 24
Peak memory 206984 kb
Host smart-fdc01a0b-66b4-4d03-a42b-2cd7f50c15c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29404
80051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2940480051
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.2066335576
Short name T1583
Test name
Test status
Simulation time 169202127 ps
CPU time 0.88 seconds
Started Aug 07 06:00:52 PM PDT 24
Finished Aug 07 06:00:53 PM PDT 24
Peak memory 206956 kb
Host smart-f0ffd3db-1f3d-4d53-b8d7-0d13f43cbfcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20663
35576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2066335576
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3413911878
Short name T2750
Test name
Test status
Simulation time 220400502 ps
CPU time 1.06 seconds
Started Aug 07 06:00:50 PM PDT 24
Finished Aug 07 06:00:51 PM PDT 24
Peak memory 206980 kb
Host smart-1e62bf89-6fa8-4eec-aad0-026987799bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34139
11878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3413911878
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.621688652
Short name T2141
Test name
Test status
Simulation time 1101959201 ps
CPU time 2.65 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:01:00 PM PDT 24
Peak memory 207144 kb
Host smart-d9b34d47-9b1e-4cbf-bd73-bdefa6887816
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=621688652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.621688652
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3827563704
Short name T2952
Test name
Test status
Simulation time 30179256189 ps
CPU time 51.61 seconds
Started Aug 07 06:00:58 PM PDT 24
Finished Aug 07 06:01:49 PM PDT 24
Peak memory 207288 kb
Host smart-a6b906f2-c440-4d13-8610-4cf4b651392e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38275
63704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3827563704
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.381169115
Short name T2267
Test name
Test status
Simulation time 498688040 ps
CPU time 8.62 seconds
Started Aug 07 06:00:56 PM PDT 24
Finished Aug 07 06:01:04 PM PDT 24
Peak memory 207200 kb
Host smart-7873cb6b-ba4f-4adc-b979-c40b35b9c746
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381169115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.381169115
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.1778478253
Short name T3084
Test name
Test status
Simulation time 581674568 ps
CPU time 1.51 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:00:59 PM PDT 24
Peak memory 206984 kb
Host smart-8041a1fb-54a7-4708-8038-af0c442054ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17784
78253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.1778478253
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3645256112
Short name T2793
Test name
Test status
Simulation time 210166097 ps
CPU time 0.91 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:00:58 PM PDT 24
Peak memory 206868 kb
Host smart-c86d9398-06f1-4835-b4e5-5715c9cdfdcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36452
56112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3645256112
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.969924284
Short name T2285
Test name
Test status
Simulation time 44253300 ps
CPU time 0.71 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:00:58 PM PDT 24
Peak memory 206684 kb
Host smart-4fc09879-1099-4fc3-bf9a-b963c9225479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96992
4284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.969924284
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.357356797
Short name T1235
Test name
Test status
Simulation time 950155366 ps
CPU time 2.52 seconds
Started Aug 07 06:00:58 PM PDT 24
Finished Aug 07 06:01:01 PM PDT 24
Peak memory 207124 kb
Host smart-a446f70a-f001-44eb-8444-532700023ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35735
6797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.357356797
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_types.877829673
Short name T3123
Test name
Test status
Simulation time 603998565 ps
CPU time 1.49 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:01:51 PM PDT 24
Peak memory 207188 kb
Host smart-c381595d-1d61-41f1-9255-e134c37fa8b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=877829673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.877829673
Directory /workspace/10.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3036262903
Short name T2312
Test name
Test status
Simulation time 164571727 ps
CPU time 0.88 seconds
Started Aug 07 06:00:56 PM PDT 24
Finished Aug 07 06:00:57 PM PDT 24
Peak memory 206992 kb
Host smart-9b27b93a-fcb6-42a2-aaa5-6aea1d4fad70
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3036262903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3036262903
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2702367858
Short name T2266
Test name
Test status
Simulation time 140115680 ps
CPU time 0.79 seconds
Started Aug 07 06:00:56 PM PDT 24
Finished Aug 07 06:00:57 PM PDT 24
Peak memory 206936 kb
Host smart-3fac0e69-cf2f-4392-9e5b-afb6ae8b4257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27023
67858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2702367858
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2444446588
Short name T495
Test name
Test status
Simulation time 258622593 ps
CPU time 1.08 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:00:59 PM PDT 24
Peak memory 207196 kb
Host smart-7ba8ae6e-81b5-4cab-98b6-f0d47dcd769e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24444
46588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2444446588
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.1430651991
Short name T2379
Test name
Test status
Simulation time 4667229046 ps
CPU time 133.71 seconds
Started Aug 07 06:00:54 PM PDT 24
Finished Aug 07 06:03:08 PM PDT 24
Peak memory 217996 kb
Host smart-be7c4070-dcf6-49fc-88ba-17d7de625113
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1430651991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.1430651991
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.1725438396
Short name T88
Test name
Test status
Simulation time 3885572523 ps
CPU time 47.06 seconds
Started Aug 07 06:00:56 PM PDT 24
Finished Aug 07 06:01:43 PM PDT 24
Peak memory 207248 kb
Host smart-bf921eb8-9bf1-4cb0-a7f5-f40f986e9fb5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1725438396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.1725438396
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.4240944632
Short name T2022
Test name
Test status
Simulation time 231977017 ps
CPU time 0.96 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:00:58 PM PDT 24
Peak memory 207040 kb
Host smart-43a45f43-f706-4aba-aae1-ffc855003824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42409
44632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.4240944632
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.1257171969
Short name T2001
Test name
Test status
Simulation time 12591981350 ps
CPU time 17.11 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:01:14 PM PDT 24
Peak memory 207332 kb
Host smart-56599371-b3af-428b-aedf-e2c4bc02f70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12571
71969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1257171969
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.834854330
Short name T2386
Test name
Test status
Simulation time 6302457603 ps
CPU time 8.34 seconds
Started Aug 07 06:01:00 PM PDT 24
Finished Aug 07 06:01:08 PM PDT 24
Peak memory 215492 kb
Host smart-cd89ccc9-a5c7-4e75-8596-87f5cc44aa71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83485
4330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.834854330
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2185574489
Short name T1249
Test name
Test status
Simulation time 3985314294 ps
CPU time 29.73 seconds
Started Aug 07 06:00:56 PM PDT 24
Finished Aug 07 06:01:26 PM PDT 24
Peak memory 215388 kb
Host smart-7822176a-72e5-461c-8d4a-004222a858a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21855
74489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2185574489
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.3467986687
Short name T2736
Test name
Test status
Simulation time 2381779316 ps
CPU time 68.08 seconds
Started Aug 07 06:00:58 PM PDT 24
Finished Aug 07 06:02:07 PM PDT 24
Peak memory 216952 kb
Host smart-19d906a7-11c8-4996-b80e-b4fc6111401d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3467986687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3467986687
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.128538680
Short name T1876
Test name
Test status
Simulation time 250684750 ps
CPU time 0.98 seconds
Started Aug 07 06:00:55 PM PDT 24
Finished Aug 07 06:00:56 PM PDT 24
Peak memory 206896 kb
Host smart-62c3fa87-2094-4b09-9be9-a64c4679af7f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=128538680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.128538680
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.457979927
Short name T2066
Test name
Test status
Simulation time 192323295 ps
CPU time 0.95 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:00:58 PM PDT 24
Peak memory 207000 kb
Host smart-e260e9b5-c68e-48fa-baa7-790ce9a89750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45797
9927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.457979927
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.403710386
Short name T873
Test name
Test status
Simulation time 3102816275 ps
CPU time 30.46 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:01:28 PM PDT 24
Peak memory 223540 kb
Host smart-d13ec37b-6f3d-48c2-be5b-cebc01fd86f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40371
0386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.403710386
Directory /workspace/10.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1177103859
Short name T2112
Test name
Test status
Simulation time 2971639356 ps
CPU time 32.77 seconds
Started Aug 07 06:00:55 PM PDT 24
Finished Aug 07 06:01:28 PM PDT 24
Peak memory 217832 kb
Host smart-78a1d0dc-56f7-4614-b25e-35d065249a23
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1177103859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1177103859
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.3837192109
Short name T1087
Test name
Test status
Simulation time 147703895 ps
CPU time 0.88 seconds
Started Aug 07 06:00:54 PM PDT 24
Finished Aug 07 06:00:55 PM PDT 24
Peak memory 206988 kb
Host smart-bd991f81-3a18-4afb-8287-1b6158ece6df
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3837192109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.3837192109
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2025697909
Short name T1265
Test name
Test status
Simulation time 160621599 ps
CPU time 0.83 seconds
Started Aug 07 06:00:56 PM PDT 24
Finished Aug 07 06:00:57 PM PDT 24
Peak memory 206960 kb
Host smart-0a25997f-eb43-473c-8ae0-599f44aa0df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20256
97909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2025697909
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.778507592
Short name T1965
Test name
Test status
Simulation time 196551179 ps
CPU time 0.89 seconds
Started Aug 07 06:00:58 PM PDT 24
Finished Aug 07 06:00:59 PM PDT 24
Peak memory 207016 kb
Host smart-8de8064f-28e2-4aae-9e1b-755193b14503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77850
7592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.778507592
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.320498969
Short name T769
Test name
Test status
Simulation time 172982385 ps
CPU time 0.9 seconds
Started Aug 07 06:00:58 PM PDT 24
Finished Aug 07 06:00:59 PM PDT 24
Peak memory 206984 kb
Host smart-bd0386dd-5e2d-49a7-9255-9364f7ab4011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32049
8969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.320498969
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1999384723
Short name T65
Test name
Test status
Simulation time 191141952 ps
CPU time 0.94 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:00:58 PM PDT 24
Peak memory 206900 kb
Host smart-86648fd1-9a2c-462d-9d2d-005d2c91cc45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19993
84723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1999384723
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.4162393848
Short name T1421
Test name
Test status
Simulation time 236778906 ps
CPU time 0.92 seconds
Started Aug 07 06:00:58 PM PDT 24
Finished Aug 07 06:00:59 PM PDT 24
Peak memory 207016 kb
Host smart-6f37e45f-8bc6-46f0-9031-da5f9832e3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41623
93848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.4162393848
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.3482720706
Short name T2844
Test name
Test status
Simulation time 254850843 ps
CPU time 1.02 seconds
Started Aug 07 06:00:54 PM PDT 24
Finished Aug 07 06:00:55 PM PDT 24
Peak memory 206896 kb
Host smart-af46738c-89c0-40ef-85c1-3b37a9c190c6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3482720706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.3482720706
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3237473590
Short name T2760
Test name
Test status
Simulation time 201105698 ps
CPU time 0.92 seconds
Started Aug 07 06:01:04 PM PDT 24
Finished Aug 07 06:01:05 PM PDT 24
Peak memory 206896 kb
Host smart-2cf1f24d-dcea-4159-87a4-a3b74b073c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32374
73590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3237473590
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3742724850
Short name T700
Test name
Test status
Simulation time 159912518 ps
CPU time 0.92 seconds
Started Aug 07 06:01:03 PM PDT 24
Finished Aug 07 06:01:04 PM PDT 24
Peak memory 206988 kb
Host smart-8ada8f8e-40d0-46ec-8c88-871bbe923477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37427
24850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3742724850
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3093494519
Short name T1124
Test name
Test status
Simulation time 204028013 ps
CPU time 0.98 seconds
Started Aug 07 06:01:02 PM PDT 24
Finished Aug 07 06:01:03 PM PDT 24
Peak memory 206948 kb
Host smart-16a9a033-e124-499e-94d7-d18046eae109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30934
94519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3093494519
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2821555152
Short name T520
Test name
Test status
Simulation time 208808612 ps
CPU time 0.93 seconds
Started Aug 07 06:01:04 PM PDT 24
Finished Aug 07 06:01:05 PM PDT 24
Peak memory 207012 kb
Host smart-daeacdd5-34f2-4617-a799-6eb5b65f0475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28215
55152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2821555152
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_resume_link_active.2556215588
Short name T660
Test name
Test status
Simulation time 20218195358 ps
CPU time 23.99 seconds
Started Aug 07 06:01:02 PM PDT 24
Finished Aug 07 06:01:26 PM PDT 24
Peak memory 207036 kb
Host smart-29bf12e6-83a3-4ada-84da-a5f2131585d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25562
15588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.2556215588
Directory /workspace/10.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2612844965
Short name T1720
Test name
Test status
Simulation time 174359451 ps
CPU time 0.83 seconds
Started Aug 07 06:01:07 PM PDT 24
Finished Aug 07 06:01:08 PM PDT 24
Peak memory 206952 kb
Host smart-a9a98304-a505-408b-a990-4f789626f82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26128
44965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2612844965
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_rx_full.703767203
Short name T3120
Test name
Test status
Simulation time 364692348 ps
CPU time 1.38 seconds
Started Aug 07 06:01:02 PM PDT 24
Finished Aug 07 06:01:03 PM PDT 24
Peak memory 206992 kb
Host smart-da573f61-a984-4e9b-b0dd-93e8958ff39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70376
7203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.703767203
Directory /workspace/10.usbdev_rx_full/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2688754970
Short name T2822
Test name
Test status
Simulation time 162424635 ps
CPU time 0.82 seconds
Started Aug 07 06:01:03 PM PDT 24
Finished Aug 07 06:01:04 PM PDT 24
Peak memory 206960 kb
Host smart-ca521415-e131-4b4d-9ec0-c46b784bc520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26887
54970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2688754970
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3129840586
Short name T316
Test name
Test status
Simulation time 161071266 ps
CPU time 0.84 seconds
Started Aug 07 06:01:04 PM PDT 24
Finished Aug 07 06:01:05 PM PDT 24
Peak memory 206948 kb
Host smart-74ec9eaf-4563-40b6-995c-c1fe01d85f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31298
40586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3129840586
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3765807214
Short name T999
Test name
Test status
Simulation time 248107723 ps
CPU time 1.12 seconds
Started Aug 07 06:01:05 PM PDT 24
Finished Aug 07 06:01:06 PM PDT 24
Peak memory 207016 kb
Host smart-bcc8a7f1-ff5b-4fb6-9e33-fcecf63ab2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37658
07214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3765807214
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.28530961
Short name T1007
Test name
Test status
Simulation time 2942651981 ps
CPU time 22.8 seconds
Started Aug 07 06:01:04 PM PDT 24
Finished Aug 07 06:01:27 PM PDT 24
Peak memory 223508 kb
Host smart-1e716c40-81bf-43e3-846f-1a296b97ad67
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=28530961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.28530961
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.4293486843
Short name T2105
Test name
Test status
Simulation time 168953936 ps
CPU time 0.87 seconds
Started Aug 07 06:01:12 PM PDT 24
Finished Aug 07 06:01:13 PM PDT 24
Peak memory 207012 kb
Host smart-48d0377b-ee48-48ae-a3e1-73a8366005ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42934
86843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.4293486843
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.515173211
Short name T2593
Test name
Test status
Simulation time 166343643 ps
CPU time 0.92 seconds
Started Aug 07 06:01:04 PM PDT 24
Finished Aug 07 06:01:05 PM PDT 24
Peak memory 206972 kb
Host smart-0992403d-fece-4b6c-aad0-499a112a138f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51517
3211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.515173211
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.2344633603
Short name T731
Test name
Test status
Simulation time 900893916 ps
CPU time 2.28 seconds
Started Aug 07 06:01:04 PM PDT 24
Finished Aug 07 06:01:06 PM PDT 24
Peak memory 207156 kb
Host smart-72863b80-0e9f-472b-a664-23a42ad3e071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23446
33603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.2344633603
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3488184745
Short name T2047
Test name
Test status
Simulation time 2074587619 ps
CPU time 61.28 seconds
Started Aug 07 06:01:05 PM PDT 24
Finished Aug 07 06:02:06 PM PDT 24
Peak memory 215328 kb
Host smart-2b0e2c46-c9fa-419d-b781-9fa3a373b61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34881
84745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3488184745
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.1355512466
Short name T672
Test name
Test status
Simulation time 4340314022 ps
CPU time 28.84 seconds
Started Aug 07 06:00:57 PM PDT 24
Finished Aug 07 06:01:26 PM PDT 24
Peak memory 207260 kb
Host smart-9b739789-1788-45a4-a0a5-7118750437ca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355512466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.1355512466
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/100.usbdev_endpoint_types.1501681841
Short name T642
Test name
Test status
Simulation time 326029289 ps
CPU time 1.12 seconds
Started Aug 07 06:12:55 PM PDT 24
Finished Aug 07 06:12:56 PM PDT 24
Peak memory 206964 kb
Host smart-e276d5bf-ddd0-414f-83c5-2b3b147c68f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1501681841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.1501681841
Directory /workspace/100.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/101.usbdev_endpoint_types.2256946461
Short name T354
Test name
Test status
Simulation time 875372409 ps
CPU time 1.78 seconds
Started Aug 07 06:12:50 PM PDT 24
Finished Aug 07 06:12:52 PM PDT 24
Peak memory 206976 kb
Host smart-861766c0-2aee-4560-b490-262928861a12
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2256946461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.2256946461
Directory /workspace/101.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/102.usbdev_endpoint_types.1189456852
Short name T673
Test name
Test status
Simulation time 261603990 ps
CPU time 1.09 seconds
Started Aug 07 06:12:53 PM PDT 24
Finished Aug 07 06:12:54 PM PDT 24
Peak memory 206876 kb
Host smart-dd760f0e-a92b-401b-9bcd-5d6ead47bc30
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1189456852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.1189456852
Directory /workspace/102.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/103.usbdev_endpoint_types.3127299416
Short name T369
Test name
Test status
Simulation time 584553099 ps
CPU time 1.63 seconds
Started Aug 07 06:13:02 PM PDT 24
Finished Aug 07 06:13:04 PM PDT 24
Peak memory 206964 kb
Host smart-b189e259-e4dd-49d3-a05a-2a5cefce9215
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3127299416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.3127299416
Directory /workspace/103.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/104.usbdev_endpoint_types.3339311803
Short name T417
Test name
Test status
Simulation time 287683256 ps
CPU time 1.09 seconds
Started Aug 07 06:13:04 PM PDT 24
Finished Aug 07 06:13:05 PM PDT 24
Peak memory 206908 kb
Host smart-3dc5fe66-053a-4a40-8bc6-0e57f8d88384
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3339311803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.3339311803
Directory /workspace/104.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/105.usbdev_endpoint_types.3863257491
Short name T373
Test name
Test status
Simulation time 768116164 ps
CPU time 1.71 seconds
Started Aug 07 06:13:08 PM PDT 24
Finished Aug 07 06:13:10 PM PDT 24
Peak memory 206972 kb
Host smart-b79ba14a-8a8f-4f86-a524-c8392ecdfacc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3863257491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.3863257491
Directory /workspace/105.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/106.usbdev_endpoint_types.4178427135
Short name T2964
Test name
Test status
Simulation time 914939714 ps
CPU time 2.31 seconds
Started Aug 07 06:13:04 PM PDT 24
Finished Aug 07 06:13:06 PM PDT 24
Peak memory 206964 kb
Host smart-d6a6d088-53d2-4364-b428-979bd9e3d4d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4178427135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.4178427135
Directory /workspace/106.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/107.usbdev_endpoint_types.1539197543
Short name T382
Test name
Test status
Simulation time 408042519 ps
CPU time 1.33 seconds
Started Aug 07 06:13:03 PM PDT 24
Finished Aug 07 06:13:04 PM PDT 24
Peak memory 206988 kb
Host smart-dfd88cc2-47b0-4d6c-94a9-52f459777597
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1539197543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.1539197543
Directory /workspace/107.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/108.usbdev_endpoint_types.3912939405
Short name T396
Test name
Test status
Simulation time 422716255 ps
CPU time 1.32 seconds
Started Aug 07 06:13:02 PM PDT 24
Finished Aug 07 06:13:03 PM PDT 24
Peak memory 206964 kb
Host smart-7b4f713c-7436-401c-86dd-35c2cfeabb17
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3912939405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.3912939405
Directory /workspace/108.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/109.usbdev_endpoint_types.3262744778
Short name T383
Test name
Test status
Simulation time 441123000 ps
CPU time 1.32 seconds
Started Aug 07 06:13:04 PM PDT 24
Finished Aug 07 06:13:05 PM PDT 24
Peak memory 206976 kb
Host smart-3a1b6df0-a490-40fc-9c71-b34d7cc157b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3262744778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.3262744778
Directory /workspace/109.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1165250446
Short name T2574
Test name
Test status
Simulation time 6162669710 ps
CPU time 8.09 seconds
Started Aug 07 06:01:05 PM PDT 24
Finished Aug 07 06:01:13 PM PDT 24
Peak memory 215436 kb
Host smart-871607cd-4b51-466c-90a8-1fafeb9b5d98
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165250446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.1165250446
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.263410229
Short name T1679
Test name
Test status
Simulation time 15623950097 ps
CPU time 18.05 seconds
Started Aug 07 06:01:06 PM PDT 24
Finished Aug 07 06:01:24 PM PDT 24
Peak memory 215412 kb
Host smart-9b7d3e34-b17d-4dc6-aca9-5072ff544cc2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=263410229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.263410229
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1729369359
Short name T1585
Test name
Test status
Simulation time 25894289496 ps
CPU time 31.29 seconds
Started Aug 07 06:01:02 PM PDT 24
Finished Aug 07 06:01:34 PM PDT 24
Peak memory 215484 kb
Host smart-6481664a-a2a3-4867-8351-e1bc58e1ae91
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729369359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.1729369359
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1106197653
Short name T537
Test name
Test status
Simulation time 174740717 ps
CPU time 1 seconds
Started Aug 07 06:01:03 PM PDT 24
Finished Aug 07 06:01:04 PM PDT 24
Peak memory 206988 kb
Host smart-e3c2791a-beb1-4770-a16c-54d67d65f016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11061
97653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1106197653
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1989496513
Short name T1520
Test name
Test status
Simulation time 154982495 ps
CPU time 0.85 seconds
Started Aug 07 06:01:07 PM PDT 24
Finished Aug 07 06:01:08 PM PDT 24
Peak memory 206952 kb
Host smart-a4664fab-8d75-433b-a6d8-a0fb66b7fa58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19894
96513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1989496513
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.1285279849
Short name T809
Test name
Test status
Simulation time 500927643 ps
CPU time 1.67 seconds
Started Aug 07 06:01:04 PM PDT 24
Finished Aug 07 06:01:06 PM PDT 24
Peak memory 206972 kb
Host smart-58f9da59-bb61-40b6-b797-417c52c42edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12852
79849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.1285279849
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.4231685583
Short name T2596
Test name
Test status
Simulation time 502632952 ps
CPU time 1.59 seconds
Started Aug 07 06:01:02 PM PDT 24
Finished Aug 07 06:01:04 PM PDT 24
Peak memory 207040 kb
Host smart-e7b42cf8-bf22-40c7-baa8-73099277ed95
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4231685583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.4231685583
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.764971363
Short name T1892
Test name
Test status
Simulation time 56449416679 ps
CPU time 78.72 seconds
Started Aug 07 06:01:04 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 207276 kb
Host smart-f05571a5-6ae0-4fae-a085-bd360a3bdec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76497
1363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.764971363
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.2525099420
Short name T1098
Test name
Test status
Simulation time 1141509424 ps
CPU time 8.91 seconds
Started Aug 07 06:01:07 PM PDT 24
Finished Aug 07 06:01:16 PM PDT 24
Peak memory 207164 kb
Host smart-eac564d1-4f5d-4758-99f1-4b89a13d2551
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525099420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.2525099420
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.3330573542
Short name T1875
Test name
Test status
Simulation time 731670280 ps
CPU time 1.85 seconds
Started Aug 07 06:01:01 PM PDT 24
Finished Aug 07 06:01:03 PM PDT 24
Peak memory 206948 kb
Host smart-ee5d7f78-8fd6-4f29-85ec-90c3fb645616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33305
73542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.3330573542
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1271618157
Short name T1611
Test name
Test status
Simulation time 152592541 ps
CPU time 0.83 seconds
Started Aug 07 06:01:04 PM PDT 24
Finished Aug 07 06:01:05 PM PDT 24
Peak memory 206920 kb
Host smart-ae278d9f-6785-4f45-bc5a-770dd32f3dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12716
18157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1271618157
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3644354517
Short name T1208
Test name
Test status
Simulation time 85510653 ps
CPU time 0.78 seconds
Started Aug 07 06:01:02 PM PDT 24
Finished Aug 07 06:01:03 PM PDT 24
Peak memory 206864 kb
Host smart-92657173-9025-4027-8598-d6e676d38756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36443
54517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3644354517
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2974946165
Short name T533
Test name
Test status
Simulation time 814547562 ps
CPU time 2.17 seconds
Started Aug 07 06:01:04 PM PDT 24
Finished Aug 07 06:01:06 PM PDT 24
Peak memory 207248 kb
Host smart-efa82b4b-5d80-4897-9e4b-1bd52dd01d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29749
46165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2974946165
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3831060496
Short name T1146
Test name
Test status
Simulation time 318455371 ps
CPU time 2.77 seconds
Started Aug 07 06:01:03 PM PDT 24
Finished Aug 07 06:01:06 PM PDT 24
Peak memory 207188 kb
Host smart-c188c826-7ca5-48d0-8c02-5775553c8d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38310
60496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3831060496
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1837824164
Short name T510
Test name
Test status
Simulation time 235336054 ps
CPU time 1.23 seconds
Started Aug 07 06:01:00 PM PDT 24
Finished Aug 07 06:01:01 PM PDT 24
Peak memory 223524 kb
Host smart-bef3806f-e9d4-4853-81c1-68dcac4c4071
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1837824164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1837824164
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.439038943
Short name T94
Test name
Test status
Simulation time 150853606 ps
CPU time 0.86 seconds
Started Aug 07 06:01:02 PM PDT 24
Finished Aug 07 06:01:02 PM PDT 24
Peak memory 206972 kb
Host smart-d57b29f0-ab0d-4334-b692-fa3617f5b2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43903
8943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.439038943
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1820855406
Short name T2235
Test name
Test status
Simulation time 247199874 ps
CPU time 1.14 seconds
Started Aug 07 06:01:02 PM PDT 24
Finished Aug 07 06:01:03 PM PDT 24
Peak memory 206984 kb
Host smart-895594cb-8111-4382-b0e6-402868af438f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18208
55406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1820855406
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.3963773884
Short name T1977
Test name
Test status
Simulation time 4465823243 ps
CPU time 131.52 seconds
Started Aug 07 06:01:05 PM PDT 24
Finished Aug 07 06:03:16 PM PDT 24
Peak memory 217780 kb
Host smart-0afd9450-65b8-401c-9b0e-08ec4e78f10f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3963773884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.3963773884
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.3281625764
Short name T1908
Test name
Test status
Simulation time 7443768856 ps
CPU time 45.3 seconds
Started Aug 07 06:01:09 PM PDT 24
Finished Aug 07 06:01:54 PM PDT 24
Peak memory 207260 kb
Host smart-8848102b-b165-408e-af6f-de695c158209
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3281625764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.3281625764
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.312208446
Short name T2617
Test name
Test status
Simulation time 230203094 ps
CPU time 0.96 seconds
Started Aug 07 06:01:09 PM PDT 24
Finished Aug 07 06:01:10 PM PDT 24
Peak memory 207016 kb
Host smart-a87b1e58-b133-4feb-bb66-dee04055804c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31220
8446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.312208446
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.4293895973
Short name T2224
Test name
Test status
Simulation time 11225595659 ps
CPU time 18.27 seconds
Started Aug 07 06:01:07 PM PDT 24
Finished Aug 07 06:01:26 PM PDT 24
Peak memory 207296 kb
Host smart-943883d7-7f58-40ce-b3d1-d71af4b98ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42938
95973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.4293895973
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.3022257234
Short name T2674
Test name
Test status
Simulation time 3652323494 ps
CPU time 5.46 seconds
Started Aug 07 06:01:10 PM PDT 24
Finished Aug 07 06:01:16 PM PDT 24
Peak memory 216268 kb
Host smart-e5197ae5-2dc0-4d26-8059-a60698fca5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30222
57234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3022257234
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2262385175
Short name T2150
Test name
Test status
Simulation time 4067855520 ps
CPU time 117.1 seconds
Started Aug 07 06:01:07 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 217912 kb
Host smart-92c0c86f-ac39-4aa1-8967-4a3c240ee355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22623
85175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2262385175
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.859227034
Short name T1883
Test name
Test status
Simulation time 2201906351 ps
CPU time 59.55 seconds
Started Aug 07 06:01:09 PM PDT 24
Finished Aug 07 06:02:09 PM PDT 24
Peak memory 215480 kb
Host smart-a2e38eb7-b94e-4894-9559-728c70edeaee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=859227034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.859227034
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1957608791
Short name T2342
Test name
Test status
Simulation time 234464729 ps
CPU time 1.02 seconds
Started Aug 07 06:01:09 PM PDT 24
Finished Aug 07 06:01:11 PM PDT 24
Peak memory 206992 kb
Host smart-bccb6f55-d359-4d57-b47a-245de07eca33
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1957608791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1957608791
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3441860526
Short name T1677
Test name
Test status
Simulation time 201609160 ps
CPU time 0.95 seconds
Started Aug 07 06:01:10 PM PDT 24
Finished Aug 07 06:01:11 PM PDT 24
Peak memory 206956 kb
Host smart-0f03014f-04cb-44b3-809f-c62d5bdca4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34418
60526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3441860526
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.3315871839
Short name T811
Test name
Test status
Simulation time 2240095540 ps
CPU time 16.91 seconds
Started Aug 07 06:01:08 PM PDT 24
Finished Aug 07 06:01:25 PM PDT 24
Peak memory 217148 kb
Host smart-a462cbb0-bd98-40eb-863c-14d22496e10b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33158
71839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.3315871839
Directory /workspace/11.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.90549495
Short name T1424
Test name
Test status
Simulation time 1810930875 ps
CPU time 19.59 seconds
Started Aug 07 06:01:08 PM PDT 24
Finished Aug 07 06:01:28 PM PDT 24
Peak memory 223456 kb
Host smart-fe6162fc-aac6-4db7-b226-d71478cf6601
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=90549495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.90549495
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.1071822760
Short name T3038
Test name
Test status
Simulation time 3764505384 ps
CPU time 109.64 seconds
Started Aug 07 06:01:09 PM PDT 24
Finished Aug 07 06:02:59 PM PDT 24
Peak memory 215516 kb
Host smart-e9da71e3-cbbf-40de-9820-f0a8acc5878e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1071822760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.1071822760
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.7886503
Short name T2766
Test name
Test status
Simulation time 160460595 ps
CPU time 0.87 seconds
Started Aug 07 06:01:08 PM PDT 24
Finished Aug 07 06:01:09 PM PDT 24
Peak memory 206968 kb
Host smart-4494db6a-8665-46e9-82f3-2cde5a998830
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=7886503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.7886503
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1837243823
Short name T1589
Test name
Test status
Simulation time 181492582 ps
CPU time 0.94 seconds
Started Aug 07 06:01:09 PM PDT 24
Finished Aug 07 06:01:10 PM PDT 24
Peak memory 206980 kb
Host smart-72852a19-a225-4e9a-85c0-5ede43dc4c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18372
43823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1837243823
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.4131892727
Short name T795
Test name
Test status
Simulation time 183935392 ps
CPU time 0.93 seconds
Started Aug 07 06:01:11 PM PDT 24
Finished Aug 07 06:01:12 PM PDT 24
Peak memory 207024 kb
Host smart-a7d890a8-b28f-4efe-a289-5d94fa014539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41318
92727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.4131892727
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.656531646
Short name T1942
Test name
Test status
Simulation time 163443685 ps
CPU time 0.89 seconds
Started Aug 07 06:01:06 PM PDT 24
Finished Aug 07 06:01:07 PM PDT 24
Peak memory 206960 kb
Host smart-180b0f6e-b544-4645-a3df-c80514dfadf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65653
1646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.656531646
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.487026823
Short name T613
Test name
Test status
Simulation time 215135743 ps
CPU time 0.92 seconds
Started Aug 07 06:01:11 PM PDT 24
Finished Aug 07 06:01:12 PM PDT 24
Peak memory 206904 kb
Host smart-95eb7d30-2e16-4192-9eb3-5b7e3c94dc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48702
6823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.487026823
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3082819443
Short name T177
Test name
Test status
Simulation time 187551516 ps
CPU time 0.91 seconds
Started Aug 07 06:01:10 PM PDT 24
Finished Aug 07 06:01:11 PM PDT 24
Peak memory 207040 kb
Host smart-6b672ca8-347e-429e-9877-238f3f84fdd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30828
19443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3082819443
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.2167906623
Short name T543
Test name
Test status
Simulation time 275883706 ps
CPU time 1.13 seconds
Started Aug 07 06:01:10 PM PDT 24
Finished Aug 07 06:01:11 PM PDT 24
Peak memory 207048 kb
Host smart-9311e34d-8798-454f-81c2-4425ab59d59d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2167906623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2167906623
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1676851134
Short name T636
Test name
Test status
Simulation time 145999474 ps
CPU time 0.85 seconds
Started Aug 07 06:01:10 PM PDT 24
Finished Aug 07 06:01:11 PM PDT 24
Peak memory 206956 kb
Host smart-c716e607-5ac8-42a8-a8ab-f8966ea2a8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16768
51134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1676851134
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3897180166
Short name T1329
Test name
Test status
Simulation time 42774081 ps
CPU time 0.71 seconds
Started Aug 07 06:01:10 PM PDT 24
Finished Aug 07 06:01:11 PM PDT 24
Peak memory 206980 kb
Host smart-b7a6c668-ba66-4912-821e-e1b618d07140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38971
80166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3897180166
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2786768898
Short name T3117
Test name
Test status
Simulation time 15776533285 ps
CPU time 37.52 seconds
Started Aug 07 06:01:11 PM PDT 24
Finished Aug 07 06:01:49 PM PDT 24
Peak memory 215504 kb
Host smart-e862a9f2-8d5b-4ad6-a5e3-70d4995ef37d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
68898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2786768898
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3807563877
Short name T2651
Test name
Test status
Simulation time 158238978 ps
CPU time 0.87 seconds
Started Aug 07 06:01:11 PM PDT 24
Finished Aug 07 06:01:12 PM PDT 24
Peak memory 206936 kb
Host smart-0070070b-f14e-48e8-8b7d-39c976d08e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38075
63877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3807563877
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3167833757
Short name T705
Test name
Test status
Simulation time 225486534 ps
CPU time 1.01 seconds
Started Aug 07 06:01:08 PM PDT 24
Finished Aug 07 06:01:09 PM PDT 24
Peak memory 206980 kb
Host smart-ac6b0575-da4a-478a-9bb5-787b0c172300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31678
33757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3167833757
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.2389211318
Short name T2288
Test name
Test status
Simulation time 176124314 ps
CPU time 0.89 seconds
Started Aug 07 06:01:11 PM PDT 24
Finished Aug 07 06:01:12 PM PDT 24
Peak memory 206984 kb
Host smart-1f5e264b-af9f-4cf2-ad32-6036e4c1caf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23892
11318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.2389211318
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.2468039079
Short name T518
Test name
Test status
Simulation time 223567311 ps
CPU time 0.94 seconds
Started Aug 07 06:01:06 PM PDT 24
Finished Aug 07 06:01:07 PM PDT 24
Peak memory 206960 kb
Host smart-3b95ed51-ac0b-40bd-8c4c-989bfd930eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24680
39079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2468039079
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_resume_link_active.417537629
Short name T2763
Test name
Test status
Simulation time 20197582212 ps
CPU time 25.55 seconds
Started Aug 07 06:01:12 PM PDT 24
Finished Aug 07 06:01:37 PM PDT 24
Peak memory 207100 kb
Host smart-ab47911c-6ef0-4698-b023-2d79a89683b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41753
7629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.417537629
Directory /workspace/11.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.3238664935
Short name T1600
Test name
Test status
Simulation time 182402019 ps
CPU time 0.91 seconds
Started Aug 07 06:01:11 PM PDT 24
Finished Aug 07 06:01:12 PM PDT 24
Peak memory 207012 kb
Host smart-ca6ac27a-ba18-4229-9e37-c2cae58ad532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32386
64935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.3238664935
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_rx_full.418066489
Short name T2320
Test name
Test status
Simulation time 252833659 ps
CPU time 1.12 seconds
Started Aug 07 06:01:10 PM PDT 24
Finished Aug 07 06:01:11 PM PDT 24
Peak memory 206904 kb
Host smart-733c2eb7-ebd3-489e-ba0f-1c0549389ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41806
6489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.418066489
Directory /workspace/11.usbdev_rx_full/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1235088256
Short name T623
Test name
Test status
Simulation time 167522168 ps
CPU time 0.86 seconds
Started Aug 07 06:01:09 PM PDT 24
Finished Aug 07 06:01:10 PM PDT 24
Peak memory 206948 kb
Host smart-9e6729d5-87fb-44d2-8eaf-3625022ed6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12350
88256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1235088256
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.4211973388
Short name T2616
Test name
Test status
Simulation time 165935875 ps
CPU time 0.89 seconds
Started Aug 07 06:01:13 PM PDT 24
Finished Aug 07 06:01:14 PM PDT 24
Peak memory 207012 kb
Host smart-a21425ed-ef5f-48a7-b45d-2ff668ba8c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42119
73388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.4211973388
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2884808606
Short name T1427
Test name
Test status
Simulation time 210186887 ps
CPU time 0.98 seconds
Started Aug 07 06:01:11 PM PDT 24
Finished Aug 07 06:01:12 PM PDT 24
Peak memory 206960 kb
Host smart-bc49226f-6cba-47eb-acfa-2094250b9edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28848
08606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2884808606
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.2116532441
Short name T171
Test name
Test status
Simulation time 2357223281 ps
CPU time 23.9 seconds
Started Aug 07 06:01:10 PM PDT 24
Finished Aug 07 06:01:34 PM PDT 24
Peak memory 215412 kb
Host smart-aecd8ae6-a84e-4455-84da-dfa7b5cb11df
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2116532441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.2116532441
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2502968139
Short name T721
Test name
Test status
Simulation time 150995635 ps
CPU time 0.85 seconds
Started Aug 07 06:01:34 PM PDT 24
Finished Aug 07 06:01:35 PM PDT 24
Peak memory 206964 kb
Host smart-256fa5c0-fa79-4c9f-848f-11dad074f870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25029
68139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2502968139
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3228498386
Short name T2481
Test name
Test status
Simulation time 185065622 ps
CPU time 0.9 seconds
Started Aug 07 06:01:10 PM PDT 24
Finished Aug 07 06:01:11 PM PDT 24
Peak memory 206984 kb
Host smart-e1d20b27-fbb7-471c-9944-3e69ff462baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32284
98386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3228498386
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.299159333
Short name T1455
Test name
Test status
Simulation time 462749576 ps
CPU time 1.44 seconds
Started Aug 07 06:01:15 PM PDT 24
Finished Aug 07 06:01:16 PM PDT 24
Peak memory 206932 kb
Host smart-e8a24600-3766-4c76-8cd8-f3580938622e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29915
9333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.299159333
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.900190951
Short name T690
Test name
Test status
Simulation time 3533287735 ps
CPU time 35.64 seconds
Started Aug 07 06:01:13 PM PDT 24
Finished Aug 07 06:01:49 PM PDT 24
Peak memory 217056 kb
Host smart-2c7fec31-7f68-47b7-a1be-092db0db0274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90019
0951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.900190951
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.1705960507
Short name T1664
Test name
Test status
Simulation time 2199462188 ps
CPU time 14.79 seconds
Started Aug 07 06:01:03 PM PDT 24
Finished Aug 07 06:01:18 PM PDT 24
Peak memory 207300 kb
Host smart-b083b838-e007-485e-9e32-c7825f4ddddd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705960507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.1705960507
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/110.usbdev_endpoint_types.3134311197
Short name T2526
Test name
Test status
Simulation time 167505213 ps
CPU time 0.89 seconds
Started Aug 07 06:13:04 PM PDT 24
Finished Aug 07 06:13:05 PM PDT 24
Peak memory 206876 kb
Host smart-8505141d-9678-4dd8-aaad-f60eab6de558
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3134311197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.3134311197
Directory /workspace/110.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/112.usbdev_endpoint_types.1493758803
Short name T430
Test name
Test status
Simulation time 393565193 ps
CPU time 1.24 seconds
Started Aug 07 06:12:59 PM PDT 24
Finished Aug 07 06:13:00 PM PDT 24
Peak memory 206888 kb
Host smart-99fc19a5-e339-42b4-a41e-f293a3698e8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1493758803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.1493758803
Directory /workspace/112.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/113.usbdev_endpoint_types.3943483502
Short name T2083
Test name
Test status
Simulation time 438689941 ps
CPU time 1.25 seconds
Started Aug 07 06:13:00 PM PDT 24
Finished Aug 07 06:13:01 PM PDT 24
Peak memory 206964 kb
Host smart-e5af4167-379f-49a9-9376-c3b0d969f3b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3943483502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.3943483502
Directory /workspace/113.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/114.usbdev_endpoint_types.1258973835
Short name T2835
Test name
Test status
Simulation time 228863081 ps
CPU time 1.07 seconds
Started Aug 07 06:13:04 PM PDT 24
Finished Aug 07 06:13:05 PM PDT 24
Peak memory 206984 kb
Host smart-4a304dba-1880-43c1-a672-8d9a25640a1e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1258973835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.1258973835
Directory /workspace/114.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/115.usbdev_endpoint_types.2596028962
Short name T466
Test name
Test status
Simulation time 180056536 ps
CPU time 1.03 seconds
Started Aug 07 06:13:04 PM PDT 24
Finished Aug 07 06:13:05 PM PDT 24
Peak memory 206984 kb
Host smart-77143f58-fcd5-4e85-9ca4-5748c0472a22
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2596028962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.2596028962
Directory /workspace/115.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/116.usbdev_endpoint_types.3807039808
Short name T472
Test name
Test status
Simulation time 637790886 ps
CPU time 1.52 seconds
Started Aug 07 06:13:01 PM PDT 24
Finished Aug 07 06:13:03 PM PDT 24
Peak memory 206984 kb
Host smart-8f454cf3-56c3-4b69-942c-626af35a756f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3807039808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.3807039808
Directory /workspace/116.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/118.usbdev_endpoint_types.3077100295
Short name T451
Test name
Test status
Simulation time 668736735 ps
CPU time 1.74 seconds
Started Aug 07 06:13:04 PM PDT 24
Finished Aug 07 06:13:06 PM PDT 24
Peak memory 206940 kb
Host smart-d51bd9ad-330b-4181-8637-c79065602d55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3077100295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.3077100295
Directory /workspace/118.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.785775321
Short name T205
Test name
Test status
Simulation time 34775119 ps
CPU time 0.66 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:01:31 PM PDT 24
Peak memory 207048 kb
Host smart-ab8015dd-bac6-4a97-b48e-fce22e5df5cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=785775321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.785775321
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2946030137
Short name T2803
Test name
Test status
Simulation time 24281611038 ps
CPU time 28.7 seconds
Started Aug 07 06:01:16 PM PDT 24
Finished Aug 07 06:01:45 PM PDT 24
Peak memory 215376 kb
Host smart-2996f3d9-4c04-4bd4-bf5d-2d790ba49dc2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946030137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.2946030137
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3921889396
Short name T1240
Test name
Test status
Simulation time 145665989 ps
CPU time 0.82 seconds
Started Aug 07 06:01:19 PM PDT 24
Finished Aug 07 06:01:20 PM PDT 24
Peak memory 207016 kb
Host smart-f5aac40d-641e-41d3-8754-369e62d69f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39218
89396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3921889396
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.2863840206
Short name T2065
Test name
Test status
Simulation time 186915260 ps
CPU time 0.89 seconds
Started Aug 07 06:01:16 PM PDT 24
Finished Aug 07 06:01:18 PM PDT 24
Peak memory 206984 kb
Host smart-dcf56f38-93f5-42dc-b472-96ebb914fd48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28638
40206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.2863840206
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2840492720
Short name T2914
Test name
Test status
Simulation time 268383221 ps
CPU time 1.13 seconds
Started Aug 07 06:01:16 PM PDT 24
Finished Aug 07 06:01:18 PM PDT 24
Peak memory 207008 kb
Host smart-24ddcc95-d7c5-4f0b-8041-7e3fc7e5d7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28404
92720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2840492720
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1183931146
Short name T2098
Test name
Test status
Simulation time 629715047 ps
CPU time 1.72 seconds
Started Aug 07 06:01:14 PM PDT 24
Finished Aug 07 06:01:16 PM PDT 24
Peak memory 206960 kb
Host smart-4f92419a-6a97-4867-a695-fc529a01ca0d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1183931146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1183931146
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1420902274
Short name T188
Test name
Test status
Simulation time 25968595413 ps
CPU time 44.68 seconds
Started Aug 07 06:01:20 PM PDT 24
Finished Aug 07 06:02:04 PM PDT 24
Peak memory 207328 kb
Host smart-0ef806e4-9708-4635-bab7-98ee48f927b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14209
02274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1420902274
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.252973493
Short name T2805
Test name
Test status
Simulation time 278168864 ps
CPU time 4.39 seconds
Started Aug 07 06:01:12 PM PDT 24
Finished Aug 07 06:01:17 PM PDT 24
Peak memory 207184 kb
Host smart-46326305-32aa-40d3-a69a-6a9e0eb5d0b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252973493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.252973493
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.1824752603
Short name T1565
Test name
Test status
Simulation time 1071626572 ps
CPU time 2.22 seconds
Started Aug 07 06:01:15 PM PDT 24
Finished Aug 07 06:01:17 PM PDT 24
Peak memory 206944 kb
Host smart-48a32dbd-c093-478c-941b-d76da796e938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18247
52603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.1824752603
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.185350500
Short name T1366
Test name
Test status
Simulation time 135439255 ps
CPU time 0.82 seconds
Started Aug 07 06:01:48 PM PDT 24
Finished Aug 07 06:01:49 PM PDT 24
Peak memory 206948 kb
Host smart-d7425f60-6c91-451f-b103-49e2ee72083e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18535
0500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.185350500
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1516402986
Short name T2302
Test name
Test status
Simulation time 42588020 ps
CPU time 0.72 seconds
Started Aug 07 06:01:16 PM PDT 24
Finished Aug 07 06:01:17 PM PDT 24
Peak memory 206968 kb
Host smart-8792194d-8a3d-44ee-9328-d19915360c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15164
02986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1516402986
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.3317820049
Short name T3041
Test name
Test status
Simulation time 972638052 ps
CPU time 2.43 seconds
Started Aug 07 06:01:14 PM PDT 24
Finished Aug 07 06:01:17 PM PDT 24
Peak memory 207200 kb
Host smart-9e5bfe46-aeb0-402f-b5fd-6d5811a3ffc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33178
20049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3317820049
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_types.3970853722
Short name T477
Test name
Test status
Simulation time 989979510 ps
CPU time 2 seconds
Started Aug 07 06:01:16 PM PDT 24
Finished Aug 07 06:01:18 PM PDT 24
Peak memory 206976 kb
Host smart-e69c04d5-edb3-4997-80b7-4e25edd55f68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3970853722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.3970853722
Directory /workspace/12.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3118795749
Short name T2495
Test name
Test status
Simulation time 293050570 ps
CPU time 2.56 seconds
Started Aug 07 06:01:15 PM PDT 24
Finished Aug 07 06:01:18 PM PDT 24
Peak memory 207212 kb
Host smart-d75851ad-9b27-494a-93db-3c350915820b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31187
95749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3118795749
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1955484816
Short name T2729
Test name
Test status
Simulation time 234053053 ps
CPU time 1.21 seconds
Started Aug 07 06:01:18 PM PDT 24
Finished Aug 07 06:01:19 PM PDT 24
Peak memory 215380 kb
Host smart-9342a88e-058d-4078-b0a7-109ac8342bf8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1955484816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1955484816
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.506397259
Short name T511
Test name
Test status
Simulation time 190145319 ps
CPU time 0.87 seconds
Started Aug 07 06:01:17 PM PDT 24
Finished Aug 07 06:01:18 PM PDT 24
Peak memory 206956 kb
Host smart-34d7db6b-9f86-444f-8eed-32428c34de03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50639
7259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.506397259
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1156580432
Short name T1457
Test name
Test status
Simulation time 176349012 ps
CPU time 0.9 seconds
Started Aug 07 06:01:19 PM PDT 24
Finished Aug 07 06:01:20 PM PDT 24
Peak memory 206904 kb
Host smart-0efce7d8-d151-4543-943a-76624b0d0458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11565
80432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1156580432
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.3725477255
Short name T1570
Test name
Test status
Simulation time 3633086048 ps
CPU time 28.62 seconds
Started Aug 07 06:01:19 PM PDT 24
Finished Aug 07 06:01:48 PM PDT 24
Peak memory 223624 kb
Host smart-ce18d114-b369-4ac7-8a7f-3155f5fec793
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3725477255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.3725477255
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.1427726702
Short name T546
Test name
Test status
Simulation time 4299305928 ps
CPU time 27.86 seconds
Started Aug 07 06:01:16 PM PDT 24
Finished Aug 07 06:01:44 PM PDT 24
Peak memory 207184 kb
Host smart-30e9ae31-b7fa-4756-a7f8-22f501018ec2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1427726702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.1427726702
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2838568046
Short name T1402
Test name
Test status
Simulation time 211210307 ps
CPU time 0.96 seconds
Started Aug 07 06:01:17 PM PDT 24
Finished Aug 07 06:01:18 PM PDT 24
Peak memory 207028 kb
Host smart-430e1348-d43d-402f-a28e-d67ba13550ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28385
68046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2838568046
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.1191875895
Short name T2930
Test name
Test status
Simulation time 7364356743 ps
CPU time 10.96 seconds
Started Aug 07 06:01:23 PM PDT 24
Finished Aug 07 06:01:34 PM PDT 24
Peak memory 215600 kb
Host smart-3123a183-825f-4a57-9594-004738673da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11918
75895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1191875895
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2054010456
Short name T2436
Test name
Test status
Simulation time 4407454670 ps
CPU time 5.72 seconds
Started Aug 07 06:01:24 PM PDT 24
Finished Aug 07 06:01:30 PM PDT 24
Peak memory 207272 kb
Host smart-d30c875b-2c8d-4e14-a13d-c6775af925d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20540
10456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2054010456
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.89456836
Short name T2327
Test name
Test status
Simulation time 4253670889 ps
CPU time 123.18 seconds
Started Aug 07 06:01:20 PM PDT 24
Finished Aug 07 06:03:23 PM PDT 24
Peak memory 217800 kb
Host smart-89a9d278-4bf1-4257-8f00-8abac73ae6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89456
836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.89456836
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.1377028280
Short name T1622
Test name
Test status
Simulation time 2879209781 ps
CPU time 81.24 seconds
Started Aug 07 06:01:21 PM PDT 24
Finished Aug 07 06:02:43 PM PDT 24
Peak memory 216984 kb
Host smart-a2cd5966-aa31-4481-870e-f0f2b2a9e722
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1377028280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.1377028280
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.1774597714
Short name T1067
Test name
Test status
Simulation time 255122958 ps
CPU time 0.95 seconds
Started Aug 07 06:01:23 PM PDT 24
Finished Aug 07 06:01:24 PM PDT 24
Peak memory 206964 kb
Host smart-d7dc4c9d-428d-4303-93a0-d72ee4932aef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1774597714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.1774597714
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2195186665
Short name T1745
Test name
Test status
Simulation time 253760960 ps
CPU time 1.04 seconds
Started Aug 07 06:01:24 PM PDT 24
Finished Aug 07 06:01:25 PM PDT 24
Peak memory 207012 kb
Host smart-0216d252-7149-44f2-9d83-04904a027399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21951
86665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2195186665
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.616709399
Short name T1746
Test name
Test status
Simulation time 2154470740 ps
CPU time 15.82 seconds
Started Aug 07 06:01:25 PM PDT 24
Finished Aug 07 06:01:40 PM PDT 24
Peak memory 207164 kb
Host smart-8616d718-0a63-44b9-aa53-7ae892f5eb47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61670
9399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.616709399
Directory /workspace/12.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.417261936
Short name T2488
Test name
Test status
Simulation time 2628019950 ps
CPU time 77.54 seconds
Started Aug 07 06:01:23 PM PDT 24
Finished Aug 07 06:02:40 PM PDT 24
Peak memory 215480 kb
Host smart-98c5d266-e8e7-4e49-9215-f33d5a0538cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=417261936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.417261936
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.3061627558
Short name T2753
Test name
Test status
Simulation time 3005453864 ps
CPU time 86.41 seconds
Started Aug 07 06:01:23 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 215448 kb
Host smart-29f20797-b1a6-4ccf-adb8-bbc9725426bf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3061627558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.3061627558
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.1360355268
Short name T2509
Test name
Test status
Simulation time 156018920 ps
CPU time 0.88 seconds
Started Aug 07 06:01:23 PM PDT 24
Finished Aug 07 06:01:24 PM PDT 24
Peak memory 207004 kb
Host smart-acd73e48-026d-40d6-983b-8793a296df6b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1360355268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.1360355268
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2654639091
Short name T3039
Test name
Test status
Simulation time 148238916 ps
CPU time 0.78 seconds
Started Aug 07 06:01:23 PM PDT 24
Finished Aug 07 06:01:24 PM PDT 24
Peak memory 206980 kb
Host smart-a7175305-b969-454c-b85e-bb479f348dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26546
39091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2654639091
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1255354254
Short name T131
Test name
Test status
Simulation time 294083564 ps
CPU time 1.05 seconds
Started Aug 07 06:01:24 PM PDT 24
Finished Aug 07 06:01:25 PM PDT 24
Peak memory 207024 kb
Host smart-52ac2568-48ee-4ff5-a31c-4f43923654e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12553
54254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1255354254
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3117037846
Short name T830
Test name
Test status
Simulation time 176737493 ps
CPU time 0.92 seconds
Started Aug 07 06:01:21 PM PDT 24
Finished Aug 07 06:01:22 PM PDT 24
Peak memory 206972 kb
Host smart-2ac282e0-b3bc-4aca-bebc-1ad23a756bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31170
37846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3117037846
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2120656923
Short name T1215
Test name
Test status
Simulation time 179253694 ps
CPU time 0.91 seconds
Started Aug 07 06:01:23 PM PDT 24
Finished Aug 07 06:01:24 PM PDT 24
Peak memory 206992 kb
Host smart-029c1653-c8cd-4c6a-b333-07d3b48e4962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21206
56923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2120656923
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1900786699
Short name T928
Test name
Test status
Simulation time 169766289 ps
CPU time 0.91 seconds
Started Aug 07 06:01:24 PM PDT 24
Finished Aug 07 06:01:25 PM PDT 24
Peak memory 207000 kb
Host smart-90344502-ef91-40bf-9cb2-1645bc70181c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19007
86699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1900786699
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1426729239
Short name T192
Test name
Test status
Simulation time 174493079 ps
CPU time 0.89 seconds
Started Aug 07 06:01:24 PM PDT 24
Finished Aug 07 06:01:25 PM PDT 24
Peak memory 206880 kb
Host smart-86759800-d97a-4f3e-a957-8b37c9bc608a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14267
29239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1426729239
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.27803992
Short name T1634
Test name
Test status
Simulation time 219453889 ps
CPU time 1 seconds
Started Aug 07 06:01:21 PM PDT 24
Finished Aug 07 06:01:22 PM PDT 24
Peak memory 206948 kb
Host smart-7535c491-d8d3-4738-987e-4c977c488fac
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=27803992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.27803992
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3399148297
Short name T565
Test name
Test status
Simulation time 162686528 ps
CPU time 0.82 seconds
Started Aug 07 06:01:23 PM PDT 24
Finished Aug 07 06:01:24 PM PDT 24
Peak memory 206948 kb
Host smart-c2212add-8792-4fd5-93f8-0df6963513ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33991
48297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3399148297
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3858594233
Short name T1511
Test name
Test status
Simulation time 77501490 ps
CPU time 0.76 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:01:50 PM PDT 24
Peak memory 206924 kb
Host smart-8de70c4e-7112-4f26-9d2f-b7290c7a71cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38585
94233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3858594233
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2530604260
Short name T2808
Test name
Test status
Simulation time 7029903488 ps
CPU time 17.89 seconds
Started Aug 07 06:01:22 PM PDT 24
Finished Aug 07 06:01:40 PM PDT 24
Peak memory 219288 kb
Host smart-33b95eaf-ed53-4355-b0c7-0fffac516075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25306
04260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2530604260
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.481002298
Short name T924
Test name
Test status
Simulation time 177587036 ps
CPU time 0.93 seconds
Started Aug 07 06:01:20 PM PDT 24
Finished Aug 07 06:01:21 PM PDT 24
Peak memory 207040 kb
Host smart-10148a86-1d42-481c-b413-6974d526063c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48100
2298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.481002298
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1360501509
Short name T1517
Test name
Test status
Simulation time 225905598 ps
CPU time 1 seconds
Started Aug 07 06:01:24 PM PDT 24
Finished Aug 07 06:01:25 PM PDT 24
Peak memory 207004 kb
Host smart-c9237785-2725-4555-989c-0cb4997c458d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13605
01509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1360501509
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1583991136
Short name T736
Test name
Test status
Simulation time 157148477 ps
CPU time 0.89 seconds
Started Aug 07 06:01:26 PM PDT 24
Finished Aug 07 06:01:27 PM PDT 24
Peak memory 207020 kb
Host smart-caae4063-5e5a-440c-a804-9aa7cee598d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15839
91136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1583991136
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.1140686476
Short name T3080
Test name
Test status
Simulation time 175138342 ps
CPU time 0.9 seconds
Started Aug 07 06:01:23 PM PDT 24
Finished Aug 07 06:01:24 PM PDT 24
Peak memory 206964 kb
Host smart-ae70c427-2288-439e-87a0-1ba3e90d3258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11406
86476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.1140686476
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_resume_link_active.2746591349
Short name T2507
Test name
Test status
Simulation time 20149905560 ps
CPU time 24.8 seconds
Started Aug 07 06:01:22 PM PDT 24
Finished Aug 07 06:01:47 PM PDT 24
Peak memory 207084 kb
Host smart-3614b483-f96b-4f2d-8cf8-ca830b89c670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27465
91349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.2746591349
Directory /workspace/12.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2151799326
Short name T1815
Test name
Test status
Simulation time 151573120 ps
CPU time 0.84 seconds
Started Aug 07 06:01:22 PM PDT 24
Finished Aug 07 06:01:23 PM PDT 24
Peak memory 206968 kb
Host smart-f71bd710-2291-491b-a21e-14703c1efab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21517
99326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2151799326
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_rx_full.1285327347
Short name T3086
Test name
Test status
Simulation time 302398356 ps
CPU time 1.17 seconds
Started Aug 07 06:01:23 PM PDT 24
Finished Aug 07 06:01:24 PM PDT 24
Peak memory 206904 kb
Host smart-2a3bc9a3-433c-4d2f-9917-c116e7bf8684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12853
27347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.1285327347
Directory /workspace/12.usbdev_rx_full/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.4165800691
Short name T948
Test name
Test status
Simulation time 160786588 ps
CPU time 0.85 seconds
Started Aug 07 06:01:31 PM PDT 24
Finished Aug 07 06:01:32 PM PDT 24
Peak memory 206984 kb
Host smart-ce8e60c4-6309-4aa6-b1e2-7a8f70afe978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41658
00691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.4165800691
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3390749366
Short name T3006
Test name
Test status
Simulation time 153015298 ps
CPU time 0.86 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:01:31 PM PDT 24
Peak memory 206964 kb
Host smart-8c7a70d4-fe56-4b23-a176-cd11a74461cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33907
49366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3390749366
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.4260332276
Short name T2707
Test name
Test status
Simulation time 256536842 ps
CPU time 1.03 seconds
Started Aug 07 06:01:32 PM PDT 24
Finished Aug 07 06:01:34 PM PDT 24
Peak memory 206980 kb
Host smart-4503786e-ce7e-42e6-9d28-e89ef9f8db05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42603
32276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.4260332276
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.669946609
Short name T2873
Test name
Test status
Simulation time 2796881374 ps
CPU time 28.48 seconds
Started Aug 07 06:01:29 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 223568 kb
Host smart-d10496b9-2f99-4c65-bcdf-c33cd0f140d5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=669946609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.669946609
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3566580355
Short name T947
Test name
Test status
Simulation time 188492873 ps
CPU time 0.9 seconds
Started Aug 07 06:01:29 PM PDT 24
Finished Aug 07 06:01:30 PM PDT 24
Peak memory 206960 kb
Host smart-207a2b94-ce04-41ff-9905-0b7e7b00f564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35665
80355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3566580355
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2290695320
Short name T1787
Test name
Test status
Simulation time 176605597 ps
CPU time 0.88 seconds
Started Aug 07 06:01:31 PM PDT 24
Finished Aug 07 06:01:32 PM PDT 24
Peak memory 206968 kb
Host smart-c15fc508-84cb-4869-9508-16d394aa0d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22906
95320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2290695320
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.4080504151
Short name T499
Test name
Test status
Simulation time 957781681 ps
CPU time 2.51 seconds
Started Aug 07 06:01:48 PM PDT 24
Finished Aug 07 06:01:50 PM PDT 24
Peak memory 207160 kb
Host smart-8b226848-7357-443c-9379-975999662179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40805
04151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.4080504151
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1358577186
Short name T2614
Test name
Test status
Simulation time 2858165739 ps
CPU time 24.01 seconds
Started Aug 07 06:01:32 PM PDT 24
Finished Aug 07 06:01:56 PM PDT 24
Peak memory 215484 kb
Host smart-4ad9ae39-92d5-41ed-8621-bf8ccfdeb4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13585
77186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1358577186
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.2563480372
Short name T2443
Test name
Test status
Simulation time 3744202522 ps
CPU time 25.53 seconds
Started Aug 07 06:01:15 PM PDT 24
Finished Aug 07 06:01:41 PM PDT 24
Peak memory 207260 kb
Host smart-5a59229b-7e75-4b71-b91e-c8fb6b300130
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563480372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.2563480372
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/121.usbdev_endpoint_types.2934302763
Short name T2232
Test name
Test status
Simulation time 386438459 ps
CPU time 1.28 seconds
Started Aug 07 06:13:04 PM PDT 24
Finished Aug 07 06:13:05 PM PDT 24
Peak memory 206944 kb
Host smart-fbbf965d-bd6c-431a-949e-fe447cf22bde
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2934302763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.2934302763
Directory /workspace/121.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/122.usbdev_endpoint_types.3355859392
Short name T387
Test name
Test status
Simulation time 511814721 ps
CPU time 1.41 seconds
Started Aug 07 06:13:00 PM PDT 24
Finished Aug 07 06:13:02 PM PDT 24
Peak memory 206988 kb
Host smart-cd0b730d-07ac-4805-9345-14e1dca68649
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3355859392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.3355859392
Directory /workspace/122.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/123.usbdev_endpoint_types.361321234
Short name T1840
Test name
Test status
Simulation time 185244593 ps
CPU time 0.87 seconds
Started Aug 07 06:13:05 PM PDT 24
Finished Aug 07 06:13:06 PM PDT 24
Peak memory 206960 kb
Host smart-02cfa881-ae7a-49ca-a4fb-e9963ee6b3b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=361321234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.361321234
Directory /workspace/123.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/125.usbdev_endpoint_types.2873373772
Short name T2919
Test name
Test status
Simulation time 156636933 ps
CPU time 0.87 seconds
Started Aug 07 06:13:04 PM PDT 24
Finished Aug 07 06:13:05 PM PDT 24
Peak memory 206944 kb
Host smart-a1b88802-944e-49b7-bd6c-be9f9bc72e82
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2873373772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.2873373772
Directory /workspace/125.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/126.usbdev_endpoint_types.4176010830
Short name T442
Test name
Test status
Simulation time 552328321 ps
CPU time 1.44 seconds
Started Aug 07 06:13:01 PM PDT 24
Finished Aug 07 06:13:02 PM PDT 24
Peak memory 206896 kb
Host smart-fdd25e77-b6fb-4a7d-9dc6-458149ca5f9c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4176010830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.4176010830
Directory /workspace/126.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/127.usbdev_endpoint_types.1655967554
Short name T102
Test name
Test status
Simulation time 349129256 ps
CPU time 1.09 seconds
Started Aug 07 06:13:05 PM PDT 24
Finished Aug 07 06:13:06 PM PDT 24
Peak memory 206972 kb
Host smart-a3400bf4-9aac-45eb-ae88-9f1d1e2d6ee2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1655967554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.1655967554
Directory /workspace/127.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/129.usbdev_endpoint_types.1909592012
Short name T449
Test name
Test status
Simulation time 426876238 ps
CPU time 1.27 seconds
Started Aug 07 06:13:03 PM PDT 24
Finished Aug 07 06:13:04 PM PDT 24
Peak memory 206948 kb
Host smart-8fd7713f-280c-406a-9074-349dac16428c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1909592012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.1909592012
Directory /workspace/129.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.1749183806
Short name T1079
Test name
Test status
Simulation time 60454356 ps
CPU time 0.69 seconds
Started Aug 07 06:01:38 PM PDT 24
Finished Aug 07 06:01:39 PM PDT 24
Peak memory 206952 kb
Host smart-70552be0-dd8e-4657-ad9a-4262598d5cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1749183806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.1749183806
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3052774367
Short name T1901
Test name
Test status
Simulation time 9231770720 ps
CPU time 12.27 seconds
Started Aug 07 06:01:29 PM PDT 24
Finished Aug 07 06:01:41 PM PDT 24
Peak memory 207308 kb
Host smart-f700c052-d79b-41a5-9c32-6a7b74667f12
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052774367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.3052774367
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1282297947
Short name T2151
Test name
Test status
Simulation time 19742495563 ps
CPU time 20.81 seconds
Started Aug 07 06:01:29 PM PDT 24
Finished Aug 07 06:01:50 PM PDT 24
Peak memory 207260 kb
Host smart-d2de5e3b-e591-4130-9235-031102953045
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282297947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1282297947
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.2270347182
Short name T1762
Test name
Test status
Simulation time 25386928148 ps
CPU time 30.96 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:02:01 PM PDT 24
Peak memory 215372 kb
Host smart-79ff1869-a553-4650-acac-778272c9a0b8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270347182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.2270347182
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3521187531
Short name T2830
Test name
Test status
Simulation time 151208585 ps
CPU time 0.88 seconds
Started Aug 07 06:01:28 PM PDT 24
Finished Aug 07 06:01:29 PM PDT 24
Peak memory 206980 kb
Host smart-f9f41b7f-3a42-4eaa-85a8-eb8321d32b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35211
87531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3521187531
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2020835001
Short name T1614
Test name
Test status
Simulation time 170175761 ps
CPU time 0.89 seconds
Started Aug 07 06:01:31 PM PDT 24
Finished Aug 07 06:01:32 PM PDT 24
Peak memory 206972 kb
Host smart-4b17a31e-7dd0-4c91-9713-9189e1e31889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20208
35001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2020835001
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3144845976
Short name T2953
Test name
Test status
Simulation time 298077781 ps
CPU time 1.13 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:01:31 PM PDT 24
Peak memory 206992 kb
Host smart-883ef49a-0e58-483d-8ad6-b8a51704a6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31448
45976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3144845976
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2493704479
Short name T644
Test name
Test status
Simulation time 347691129 ps
CPU time 1.26 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:01:31 PM PDT 24
Peak memory 206992 kb
Host smart-057f50f1-08de-4c80-8e93-1f8fa4bf1c21
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2493704479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2493704479
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.1359820592
Short name T1800
Test name
Test status
Simulation time 1079929113 ps
CPU time 24.32 seconds
Started Aug 07 06:01:32 PM PDT 24
Finished Aug 07 06:01:56 PM PDT 24
Peak memory 207136 kb
Host smart-64ba2dbc-0979-4d3f-898d-9c3db9009af2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359820592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.1359820592
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.3188833114
Short name T2116
Test name
Test status
Simulation time 1092284174 ps
CPU time 2.11 seconds
Started Aug 07 06:01:29 PM PDT 24
Finished Aug 07 06:01:31 PM PDT 24
Peak memory 206952 kb
Host smart-06d3d818-57b8-4bc6-b6a4-a233f1b8be3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31888
33114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.3188833114
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2355213708
Short name T2676
Test name
Test status
Simulation time 217629217 ps
CPU time 0.98 seconds
Started Aug 07 06:01:28 PM PDT 24
Finished Aug 07 06:01:30 PM PDT 24
Peak memory 206868 kb
Host smart-e6cbd0d5-45bc-49d3-bd29-4fd2c039cacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23552
13708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2355213708
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2854699665
Short name T2903
Test name
Test status
Simulation time 45828499 ps
CPU time 0.72 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:01:31 PM PDT 24
Peak memory 206960 kb
Host smart-17756a90-23d8-47cd-abfb-ef04dee11c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28546
99665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2854699665
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.344197656
Short name T2356
Test name
Test status
Simulation time 930966280 ps
CPU time 2.77 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:01:33 PM PDT 24
Peak memory 207156 kb
Host smart-441027a6-efa3-4fc4-bbe9-8974a2f37c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34419
7656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.344197656
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_types.299151041
Short name T381
Test name
Test status
Simulation time 834956383 ps
CPU time 1.82 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:01:32 PM PDT 24
Peak memory 206964 kb
Host smart-f8200173-efb5-4812-ac4d-5336bec97388
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=299151041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.299151041
Directory /workspace/13.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3973895743
Short name T815
Test name
Test status
Simulation time 205446996 ps
CPU time 1.42 seconds
Started Aug 07 06:01:29 PM PDT 24
Finished Aug 07 06:01:31 PM PDT 24
Peak memory 207212 kb
Host smart-b03d756c-3114-44d4-80b2-ca810929deeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39738
95743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3973895743
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.4210048532
Short name T1469
Test name
Test status
Simulation time 250440435 ps
CPU time 1.36 seconds
Started Aug 07 06:01:31 PM PDT 24
Finished Aug 07 06:01:33 PM PDT 24
Peak memory 215352 kb
Host smart-d44896b9-5740-4527-a07c-791cc11fd05b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4210048532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.4210048532
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3008455342
Short name T570
Test name
Test status
Simulation time 143487164 ps
CPU time 0.84 seconds
Started Aug 07 06:01:32 PM PDT 24
Finished Aug 07 06:01:33 PM PDT 24
Peak memory 206948 kb
Host smart-6f1ff8b8-8a12-4e3f-a32e-c88db10445ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30084
55342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3008455342
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.4115024699
Short name T2298
Test name
Test status
Simulation time 185679004 ps
CPU time 0.95 seconds
Started Aug 07 06:01:32 PM PDT 24
Finished Aug 07 06:01:33 PM PDT 24
Peak memory 206992 kb
Host smart-e775b5d0-2009-491f-adca-b5a69ef4d782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41150
24699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.4115024699
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.1862125553
Short name T1904
Test name
Test status
Simulation time 2842256557 ps
CPU time 27.63 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:01:58 PM PDT 24
Peak memory 223580 kb
Host smart-125b87d4-3782-44d5-a142-c6aa062b50be
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1862125553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.1862125553
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.1833194491
Short name T2391
Test name
Test status
Simulation time 5645473703 ps
CPU time 37.41 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:02:07 PM PDT 24
Peak memory 207260 kb
Host smart-5d9fe2ad-4358-44c2-b94d-bddd977aef4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1833194491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.1833194491
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1554290859
Short name T1281
Test name
Test status
Simulation time 237225899 ps
CPU time 0.96 seconds
Started Aug 07 06:01:31 PM PDT 24
Finished Aug 07 06:01:32 PM PDT 24
Peak memory 206980 kb
Host smart-50197ce8-d276-4137-8532-ee6ac7137d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15542
90859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1554290859
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.2310189639
Short name T960
Test name
Test status
Simulation time 27716843407 ps
CPU time 41.69 seconds
Started Aug 07 06:01:29 PM PDT 24
Finished Aug 07 06:02:11 PM PDT 24
Peak memory 207328 kb
Host smart-c3b367cf-fa2e-45ba-83ae-72c62ef83c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23101
89639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.2310189639
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.1169241547
Short name T1866
Test name
Test status
Simulation time 8424006585 ps
CPU time 10.61 seconds
Started Aug 07 06:01:28 PM PDT 24
Finished Aug 07 06:01:39 PM PDT 24
Peak memory 207256 kb
Host smart-aae31ac8-4148-4b35-85bf-70e4d2432dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11692
41547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.1169241547
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.267698150
Short name T492
Test name
Test status
Simulation time 4438562169 ps
CPU time 125.57 seconds
Started Aug 07 06:01:31 PM PDT 24
Finished Aug 07 06:03:37 PM PDT 24
Peak memory 215500 kb
Host smart-aa32462a-560c-4e1a-a0f6-0af07c835bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26769
8150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.267698150
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1992971593
Short name T2332
Test name
Test status
Simulation time 2550559624 ps
CPU time 19.5 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:01:50 PM PDT 24
Peak memory 217024 kb
Host smart-304dc335-4487-4df7-87f0-dc40ae5dd8ae
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1992971593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1992971593
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1490493146
Short name T2958
Test name
Test status
Simulation time 239598777 ps
CPU time 0.96 seconds
Started Aug 07 06:01:35 PM PDT 24
Finished Aug 07 06:01:36 PM PDT 24
Peak memory 207024 kb
Host smart-be68c324-0f45-438e-b11c-0f890d282ce6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1490493146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1490493146
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.646269876
Short name T2679
Test name
Test status
Simulation time 187793482 ps
CPU time 0.99 seconds
Started Aug 07 06:01:36 PM PDT 24
Finished Aug 07 06:01:37 PM PDT 24
Peak memory 206908 kb
Host smart-ac6d9f19-04f1-4508-89b4-afaff170615f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64626
9876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.646269876
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.3095772685
Short name T173
Test name
Test status
Simulation time 1951137142 ps
CPU time 18.95 seconds
Started Aug 07 06:01:37 PM PDT 24
Finished Aug 07 06:01:56 PM PDT 24
Peak memory 216992 kb
Host smart-b8bcc8f8-d8d4-4ef9-8325-20d160262390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30957
72685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.3095772685
Directory /workspace/13.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2676255452
Short name T1912
Test name
Test status
Simulation time 2766877903 ps
CPU time 32.33 seconds
Started Aug 07 06:01:36 PM PDT 24
Finished Aug 07 06:02:08 PM PDT 24
Peak memory 223472 kb
Host smart-7b631c2d-2b0b-4094-882b-e9fc30949080
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2676255452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2676255452
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.771401758
Short name T2328
Test name
Test status
Simulation time 3157650457 ps
CPU time 92.97 seconds
Started Aug 07 06:01:36 PM PDT 24
Finished Aug 07 06:03:09 PM PDT 24
Peak memory 216904 kb
Host smart-ebfd656b-1752-4c2f-bda6-6871bc6da5f4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=771401758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.771401758
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.3807969522
Short name T2223
Test name
Test status
Simulation time 151656544 ps
CPU time 0.84 seconds
Started Aug 07 06:01:35 PM PDT 24
Finished Aug 07 06:01:36 PM PDT 24
Peak memory 207004 kb
Host smart-4864d7e8-bfaf-42cb-bba2-fcc9b0d94428
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3807969522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3807969522
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1207368388
Short name T2289
Test name
Test status
Simulation time 143451967 ps
CPU time 0.85 seconds
Started Aug 07 06:01:36 PM PDT 24
Finished Aug 07 06:01:37 PM PDT 24
Peak memory 207028 kb
Host smart-a3d219f3-139c-46eb-8340-23dd0c66f95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12073
68388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1207368388
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1674720969
Short name T98
Test name
Test status
Simulation time 211823818 ps
CPU time 1.1 seconds
Started Aug 07 06:01:38 PM PDT 24
Finished Aug 07 06:01:40 PM PDT 24
Peak memory 206904 kb
Host smart-102881f9-18bc-4383-be21-39611d7f6cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16747
20969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1674720969
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2117531662
Short name T1357
Test name
Test status
Simulation time 222464302 ps
CPU time 1 seconds
Started Aug 07 06:01:38 PM PDT 24
Finished Aug 07 06:01:39 PM PDT 24
Peak memory 206964 kb
Host smart-c7aaf261-980f-4710-9b59-d38289acfbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21175
31662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2117531662
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2396137360
Short name T1667
Test name
Test status
Simulation time 174863343 ps
CPU time 0.9 seconds
Started Aug 07 06:01:37 PM PDT 24
Finished Aug 07 06:01:38 PM PDT 24
Peak memory 206912 kb
Host smart-65bc7d8d-8245-4c20-8a37-080f829298ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23961
37360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2396137360
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3156365886
Short name T1727
Test name
Test status
Simulation time 156246053 ps
CPU time 0.87 seconds
Started Aug 07 06:01:35 PM PDT 24
Finished Aug 07 06:01:36 PM PDT 24
Peak memory 207000 kb
Host smart-ca06a3ec-7361-40ef-8e5f-59cfd7c1f9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31563
65886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3156365886
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.2306165709
Short name T2148
Test name
Test status
Simulation time 255721886 ps
CPU time 1.01 seconds
Started Aug 07 06:01:37 PM PDT 24
Finished Aug 07 06:01:38 PM PDT 24
Peak memory 206928 kb
Host smart-751153d2-3fba-470a-9b01-e32bb2c83691
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2306165709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.2306165709
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.996248246
Short name T1290
Test name
Test status
Simulation time 144594073 ps
CPU time 0.88 seconds
Started Aug 07 06:01:34 PM PDT 24
Finished Aug 07 06:01:35 PM PDT 24
Peak memory 206988 kb
Host smart-9547ba95-72b5-4dea-aff4-983d8ae4d29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99624
8246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.996248246
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.862809203
Short name T2827
Test name
Test status
Simulation time 53966782 ps
CPU time 0.72 seconds
Started Aug 07 06:01:38 PM PDT 24
Finished Aug 07 06:01:39 PM PDT 24
Peak memory 206908 kb
Host smart-7b50a917-fa68-4d33-b8a0-c23750eecd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86280
9203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.862809203
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.287170738
Short name T1349
Test name
Test status
Simulation time 15333252720 ps
CPU time 38.01 seconds
Started Aug 07 06:01:37 PM PDT 24
Finished Aug 07 06:02:15 PM PDT 24
Peak memory 215500 kb
Host smart-0049f4a1-791f-4bbf-87a4-c9d3e929ce64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28717
0738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.287170738
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1009509225
Short name T2867
Test name
Test status
Simulation time 182812291 ps
CPU time 0.99 seconds
Started Aug 07 06:01:35 PM PDT 24
Finished Aug 07 06:01:36 PM PDT 24
Peak memory 206916 kb
Host smart-b39345d4-a7d1-4ac3-8983-3a63c7a18d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10095
09225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1009509225
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.642185753
Short name T1125
Test name
Test status
Simulation time 179056896 ps
CPU time 0.89 seconds
Started Aug 07 06:01:39 PM PDT 24
Finished Aug 07 06:01:40 PM PDT 24
Peak memory 206964 kb
Host smart-c6db8a90-7eb6-431b-92b1-10d70af13cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64218
5753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.642185753
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.230127829
Short name T1708
Test name
Test status
Simulation time 190300791 ps
CPU time 0.88 seconds
Started Aug 07 06:01:36 PM PDT 24
Finished Aug 07 06:01:37 PM PDT 24
Peak memory 207012 kb
Host smart-dd23fae7-a8ba-4e5b-a5c1-9108dd51a1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23012
7829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.230127829
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.443701830
Short name T2984
Test name
Test status
Simulation time 175851970 ps
CPU time 0.87 seconds
Started Aug 07 06:01:35 PM PDT 24
Finished Aug 07 06:01:36 PM PDT 24
Peak memory 206900 kb
Host smart-bacf0fe3-ba63-4167-a6c2-83b96d8e8be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44370
1830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.443701830
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_resume_link_active.1266046017
Short name T888
Test name
Test status
Simulation time 20166560583 ps
CPU time 29.55 seconds
Started Aug 07 06:01:35 PM PDT 24
Finished Aug 07 06:02:05 PM PDT 24
Peak memory 206992 kb
Host smart-b110da81-5009-4f51-9912-a3148b775060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12660
46017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.1266046017
Directory /workspace/13.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.1542891504
Short name T2096
Test name
Test status
Simulation time 143547127 ps
CPU time 0.84 seconds
Started Aug 07 06:01:36 PM PDT 24
Finished Aug 07 06:01:37 PM PDT 24
Peak memory 206940 kb
Host smart-7a8a889e-bb21-48ce-804e-2e28deaaa261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15428
91504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1542891504
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_rx_full.2909628321
Short name T2915
Test name
Test status
Simulation time 262745537 ps
CPU time 1.06 seconds
Started Aug 07 06:01:36 PM PDT 24
Finished Aug 07 06:01:38 PM PDT 24
Peak memory 206880 kb
Host smart-86892b3e-862a-4c97-a09a-fabc5f2b81b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29096
28321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.2909628321
Directory /workspace/13.usbdev_rx_full/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.648590277
Short name T2092
Test name
Test status
Simulation time 193414780 ps
CPU time 0.92 seconds
Started Aug 07 06:01:37 PM PDT 24
Finished Aug 07 06:01:38 PM PDT 24
Peak memory 206960 kb
Host smart-5a90856f-8435-43d8-bfac-433fe2b9d0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64859
0277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.648590277
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2156404770
Short name T1572
Test name
Test status
Simulation time 164307050 ps
CPU time 0.88 seconds
Started Aug 07 06:01:37 PM PDT 24
Finished Aug 07 06:01:38 PM PDT 24
Peak memory 206968 kb
Host smart-2dad3ad0-afa8-4df9-a735-f82e1f0be966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21564
04770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2156404770
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.4232750465
Short name T2741
Test name
Test status
Simulation time 207403329 ps
CPU time 0.96 seconds
Started Aug 07 06:01:36 PM PDT 24
Finished Aug 07 06:01:37 PM PDT 24
Peak memory 206996 kb
Host smart-77708459-2386-4316-9475-c9d0a0716bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42327
50465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.4232750465
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2948940072
Short name T3049
Test name
Test status
Simulation time 3004648138 ps
CPU time 32.57 seconds
Started Aug 07 06:01:34 PM PDT 24
Finished Aug 07 06:02:07 PM PDT 24
Peak memory 215528 kb
Host smart-a52b7093-c62c-405e-ba55-36aa7ab23d65
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2948940072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2948940072
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2916075920
Short name T1165
Test name
Test status
Simulation time 199641779 ps
CPU time 0.92 seconds
Started Aug 07 06:01:38 PM PDT 24
Finished Aug 07 06:01:39 PM PDT 24
Peak memory 207216 kb
Host smart-c1b4531e-a249-44df-ba3e-540f497f55d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29160
75920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2916075920
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.621280835
Short name T1920
Test name
Test status
Simulation time 200644402 ps
CPU time 0.89 seconds
Started Aug 07 06:01:36 PM PDT 24
Finished Aug 07 06:01:37 PM PDT 24
Peak memory 206968 kb
Host smart-9c5263bf-452c-42e9-b4db-cd7e992b34b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62128
0835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.621280835
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.2201661526
Short name T2048
Test name
Test status
Simulation time 1236806776 ps
CPU time 2.9 seconds
Started Aug 07 06:01:39 PM PDT 24
Finished Aug 07 06:01:42 PM PDT 24
Peak memory 207092 kb
Host smart-c5bfd41e-a1d2-4238-a02c-b34abd1d656d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22016
61526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.2201661526
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2194832447
Short name T1563
Test name
Test status
Simulation time 1934106305 ps
CPU time 14.93 seconds
Started Aug 07 06:01:36 PM PDT 24
Finished Aug 07 06:01:51 PM PDT 24
Peak memory 216548 kb
Host smart-7d0adf7f-c27f-452b-a850-9659c1336309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21948
32447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2194832447
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.502680604
Short name T2268
Test name
Test status
Simulation time 160541118 ps
CPU time 0.87 seconds
Started Aug 07 06:01:30 PM PDT 24
Finished Aug 07 06:01:31 PM PDT 24
Peak memory 206952 kb
Host smart-0e75bb99-6373-448b-a714-fc55df1fe975
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502680604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_host
_handshake.502680604
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/130.usbdev_endpoint_types.2090474824
Short name T434
Test name
Test status
Simulation time 185615836 ps
CPU time 0.9 seconds
Started Aug 07 06:13:03 PM PDT 24
Finished Aug 07 06:13:04 PM PDT 24
Peak memory 206876 kb
Host smart-4c16681c-032a-49e7-898c-04a9aeabe611
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2090474824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.2090474824
Directory /workspace/130.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/131.usbdev_endpoint_types.2105375644
Short name T376
Test name
Test status
Simulation time 946258337 ps
CPU time 1.89 seconds
Started Aug 07 06:13:04 PM PDT 24
Finished Aug 07 06:13:06 PM PDT 24
Peak memory 206940 kb
Host smart-06b9a974-7910-43f9-bbad-4c9b5513377a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2105375644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.2105375644
Directory /workspace/131.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/132.usbdev_endpoint_types.3145176805
Short name T321
Test name
Test status
Simulation time 350064911 ps
CPU time 1.12 seconds
Started Aug 07 06:13:03 PM PDT 24
Finished Aug 07 06:13:04 PM PDT 24
Peak memory 206980 kb
Host smart-a91baa70-bda2-4b69-8c03-af28e6010131
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3145176805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.3145176805
Directory /workspace/132.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/134.usbdev_endpoint_types.256826527
Short name T465
Test name
Test status
Simulation time 217364235 ps
CPU time 1.01 seconds
Started Aug 07 06:13:00 PM PDT 24
Finished Aug 07 06:13:01 PM PDT 24
Peak memory 206952 kb
Host smart-f1227dae-b174-498d-98ed-9dd0acf150d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=256826527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.256826527
Directory /workspace/134.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/135.usbdev_endpoint_types.1267661468
Short name T445
Test name
Test status
Simulation time 148479745 ps
CPU time 0.85 seconds
Started Aug 07 06:13:12 PM PDT 24
Finished Aug 07 06:13:13 PM PDT 24
Peak memory 206972 kb
Host smart-95906233-0aa3-4c6a-baf3-4c6d0a3c1881
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1267661468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.1267661468
Directory /workspace/135.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/136.usbdev_endpoint_types.685858027
Short name T2147
Test name
Test status
Simulation time 442029490 ps
CPU time 1.31 seconds
Started Aug 07 06:13:14 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206876 kb
Host smart-dca8861d-dd16-4420-b04f-816c2db20859
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=685858027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.685858027
Directory /workspace/136.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/138.usbdev_endpoint_types.1659252569
Short name T350
Test name
Test status
Simulation time 391774520 ps
CPU time 1.24 seconds
Started Aug 07 06:13:13 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206976 kb
Host smart-c9a8f57a-1c1a-4271-8d44-44d8ced757f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1659252569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.1659252569
Directory /workspace/138.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/139.usbdev_endpoint_types.3537095900
Short name T1109
Test name
Test status
Simulation time 238771690 ps
CPU time 1.01 seconds
Started Aug 07 06:13:18 PM PDT 24
Finished Aug 07 06:13:19 PM PDT 24
Peak memory 206960 kb
Host smart-58e9ed74-79e6-4c13-85e2-b3f2a06b360d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3537095900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.3537095900
Directory /workspace/139.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.596085404
Short name T204
Test name
Test status
Simulation time 97495877 ps
CPU time 0.71 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:01:50 PM PDT 24
Peak memory 207000 kb
Host smart-438e9078-9c42-4a48-ae13-6c6042c1a583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=596085404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.596085404
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1052844126
Short name T2329
Test name
Test status
Simulation time 4801368065 ps
CPU time 7.32 seconds
Started Aug 07 06:01:37 PM PDT 24
Finished Aug 07 06:01:44 PM PDT 24
Peak memory 215484 kb
Host smart-a897797d-62f6-4efd-adb6-9996f262f17c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052844126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.1052844126
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2456860191
Short name T2196
Test name
Test status
Simulation time 18705372909 ps
CPU time 21.53 seconds
Started Aug 07 06:01:39 PM PDT 24
Finished Aug 07 06:02:00 PM PDT 24
Peak memory 207276 kb
Host smart-8cf6d758-40ee-48fe-a3ac-a0ada67637e0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456860191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2456860191
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2352503867
Short name T8
Test name
Test status
Simulation time 23582180812 ps
CPU time 30.06 seconds
Started Aug 07 06:01:36 PM PDT 24
Finished Aug 07 06:02:07 PM PDT 24
Peak memory 215432 kb
Host smart-b63e99d4-0f90-426e-a3ec-047f602cad94
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352503867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.2352503867
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2084360016
Short name T1580
Test name
Test status
Simulation time 159071326 ps
CPU time 0.84 seconds
Started Aug 07 06:01:38 PM PDT 24
Finished Aug 07 06:01:39 PM PDT 24
Peak memory 207016 kb
Host smart-fa0ef08a-0090-4e8e-b42f-a38148b1a22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20843
60016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2084360016
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.2968780654
Short name T647
Test name
Test status
Simulation time 252227057 ps
CPU time 1.07 seconds
Started Aug 07 06:01:38 PM PDT 24
Finished Aug 07 06:01:39 PM PDT 24
Peak memory 206868 kb
Host smart-6b42576d-4c83-4169-bb13-c70421e4e669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29687
80654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2968780654
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_device_address.3569906471
Short name T2929
Test name
Test status
Simulation time 19214968202 ps
CPU time 29.14 seconds
Started Aug 07 06:01:48 PM PDT 24
Finished Aug 07 06:02:17 PM PDT 24
Peak memory 207276 kb
Host smart-33ad700c-8487-4523-98dd-fa0ed3d56e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35699
06471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.3569906471
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.3587113269
Short name T2046
Test name
Test status
Simulation time 2008732086 ps
CPU time 46.6 seconds
Started Aug 07 06:01:43 PM PDT 24
Finished Aug 07 06:02:29 PM PDT 24
Peak memory 207192 kb
Host smart-9d78f36b-3ae0-455f-9a8a-d0b5802a9e99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587113269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.3587113269
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.2394794330
Short name T1376
Test name
Test status
Simulation time 915375840 ps
CPU time 2.28 seconds
Started Aug 07 06:01:46 PM PDT 24
Finished Aug 07 06:01:48 PM PDT 24
Peak memory 206976 kb
Host smart-82f15f5d-ca23-4ffb-8b4e-9b039d7646f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23947
94330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.2394794330
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.579934345
Short name T2776
Test name
Test status
Simulation time 149490821 ps
CPU time 0.82 seconds
Started Aug 07 06:01:44 PM PDT 24
Finished Aug 07 06:01:45 PM PDT 24
Peak memory 206984 kb
Host smart-7916a363-a71a-4ea4-aa4a-c384ead12e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57993
4345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.579934345
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2612939715
Short name T248
Test name
Test status
Simulation time 33141188 ps
CPU time 0.72 seconds
Started Aug 07 06:01:41 PM PDT 24
Finished Aug 07 06:01:42 PM PDT 24
Peak memory 206864 kb
Host smart-83acfabb-f313-4a19-b86d-5ffb191cc613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26129
39715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2612939715
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.543043984
Short name T487
Test name
Test status
Simulation time 838873693 ps
CPU time 2.2 seconds
Started Aug 07 06:01:41 PM PDT 24
Finished Aug 07 06:01:43 PM PDT 24
Peak memory 207212 kb
Host smart-8858436d-ec29-4fa6-b7e0-8983ad67ce1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54304
3984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.543043984
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_types.2832310036
Short name T367
Test name
Test status
Simulation time 433743556 ps
CPU time 1.44 seconds
Started Aug 07 06:01:42 PM PDT 24
Finished Aug 07 06:01:44 PM PDT 24
Peak memory 206996 kb
Host smart-4b475b2a-a72d-4a84-83db-713b95c41184
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2832310036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.2832310036
Directory /workspace/14.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3047363326
Short name T1754
Test name
Test status
Simulation time 286582689 ps
CPU time 2.06 seconds
Started Aug 07 06:01:43 PM PDT 24
Finished Aug 07 06:01:45 PM PDT 24
Peak memory 207064 kb
Host smart-78154af6-2de5-4fbc-83f8-64ecd9d7f8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30473
63326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3047363326
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.4171232653
Short name T3126
Test name
Test status
Simulation time 160574683 ps
CPU time 0.99 seconds
Started Aug 07 06:01:45 PM PDT 24
Finished Aug 07 06:01:47 PM PDT 24
Peak memory 207000 kb
Host smart-1123399b-3d7c-431b-adec-a8828e5f0d3e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4171232653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.4171232653
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1305238698
Short name T812
Test name
Test status
Simulation time 165397801 ps
CPU time 0.84 seconds
Started Aug 07 06:01:42 PM PDT 24
Finished Aug 07 06:01:44 PM PDT 24
Peak memory 206928 kb
Host smart-3b168677-3c0e-4550-a452-2c7bf73898df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13052
38698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1305238698
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2543093676
Short name T906
Test name
Test status
Simulation time 229700533 ps
CPU time 0.99 seconds
Started Aug 07 06:01:42 PM PDT 24
Finished Aug 07 06:01:43 PM PDT 24
Peak memory 206992 kb
Host smart-bfecb4fd-d9a9-4dae-a845-0300a682f9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25430
93676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2543093676
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.3930594924
Short name T594
Test name
Test status
Simulation time 4386268740 ps
CPU time 125.49 seconds
Started Aug 07 06:01:44 PM PDT 24
Finished Aug 07 06:03:50 PM PDT 24
Peak memory 223616 kb
Host smart-f95014b1-707c-40d5-818c-1b0c3f91db48
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3930594924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.3930594924
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.2951196899
Short name T2474
Test name
Test status
Simulation time 217134680 ps
CPU time 0.98 seconds
Started Aug 07 06:01:42 PM PDT 24
Finished Aug 07 06:01:43 PM PDT 24
Peak memory 206892 kb
Host smart-f1ed4f9d-d7e8-4632-be90-4b8698d5a024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29511
96899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.2951196899
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3591266866
Short name T2963
Test name
Test status
Simulation time 11153763357 ps
CPU time 16.87 seconds
Started Aug 07 06:01:45 PM PDT 24
Finished Aug 07 06:02:02 PM PDT 24
Peak memory 207244 kb
Host smart-ed02d243-a6bf-4cc5-b9e6-167f64b44302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35912
66866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3591266866
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.2287817292
Short name T2280
Test name
Test status
Simulation time 10504210450 ps
CPU time 14.02 seconds
Started Aug 07 06:01:45 PM PDT 24
Finished Aug 07 06:01:59 PM PDT 24
Peak memory 207264 kb
Host smart-334895e3-9bff-498e-946b-4e50845571ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22878
17292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2287817292
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.2219587172
Short name T2340
Test name
Test status
Simulation time 3758864221 ps
CPU time 27.19 seconds
Started Aug 07 06:01:41 PM PDT 24
Finished Aug 07 06:02:08 PM PDT 24
Peak memory 217592 kb
Host smart-b63a859e-9ff5-40e7-a59e-32f7716862c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22195
87172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.2219587172
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3247266159
Short name T2378
Test name
Test status
Simulation time 1465115928 ps
CPU time 11.63 seconds
Started Aug 07 06:01:45 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 223452 kb
Host smart-aa3020ce-190c-4ce3-815c-19354a53bcfb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3247266159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3247266159
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1355355118
Short name T1257
Test name
Test status
Simulation time 259047009 ps
CPU time 1.05 seconds
Started Aug 07 06:01:44 PM PDT 24
Finished Aug 07 06:01:45 PM PDT 24
Peak memory 206960 kb
Host smart-2f1e8548-276c-4cae-bb53-fd6a28c84999
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1355355118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1355355118
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2656858696
Short name T2954
Test name
Test status
Simulation time 194635627 ps
CPU time 0.95 seconds
Started Aug 07 06:01:46 PM PDT 24
Finished Aug 07 06:01:47 PM PDT 24
Peak memory 206992 kb
Host smart-2b2238c0-2bd1-42f3-977b-705bc16972ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26568
58696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2656858696
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.4173553737
Short name T866
Test name
Test status
Simulation time 2363881984 ps
CPU time 69.27 seconds
Started Aug 07 06:01:42 PM PDT 24
Finished Aug 07 06:02:51 PM PDT 24
Peak memory 215508 kb
Host smart-20207eb4-ee36-427f-aee1-f0c55e9b9ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41735
53737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.4173553737
Directory /workspace/14.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3810998322
Short name T128
Test name
Test status
Simulation time 3095531836 ps
CPU time 88.4 seconds
Started Aug 07 06:01:42 PM PDT 24
Finished Aug 07 06:03:11 PM PDT 24
Peak memory 217748 kb
Host smart-7b7b4882-5a97-42a6-bd13-5fb866e07e87
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3810998322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3810998322
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3169262108
Short name T734
Test name
Test status
Simulation time 3972187104 ps
CPU time 114.06 seconds
Started Aug 07 06:01:42 PM PDT 24
Finished Aug 07 06:03:37 PM PDT 24
Peak memory 216904 kb
Host smart-98a177d5-4a60-4222-862a-cc27e49c9634
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3169262108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3169262108
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3912984987
Short name T1230
Test name
Test status
Simulation time 156701262 ps
CPU time 0.88 seconds
Started Aug 07 06:01:43 PM PDT 24
Finished Aug 07 06:01:44 PM PDT 24
Peak memory 207020 kb
Host smart-c6987e9d-45ae-4462-a81e-481aa99851f7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3912984987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3912984987
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.64857821
Short name T2120
Test name
Test status
Simulation time 171446859 ps
CPU time 0.86 seconds
Started Aug 07 06:01:44 PM PDT 24
Finished Aug 07 06:01:45 PM PDT 24
Peak memory 207016 kb
Host smart-c3683501-5f0c-4842-a3b8-de35e2172afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64857
821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.64857821
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.693972774
Short name T524
Test name
Test status
Simulation time 184969589 ps
CPU time 0.96 seconds
Started Aug 07 06:01:44 PM PDT 24
Finished Aug 07 06:01:46 PM PDT 24
Peak memory 207000 kb
Host smart-c3508db3-5c25-4036-85e3-e0d00a3befcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69397
2774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.693972774
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1494259102
Short name T1818
Test name
Test status
Simulation time 157841653 ps
CPU time 0.85 seconds
Started Aug 07 06:01:43 PM PDT 24
Finished Aug 07 06:01:44 PM PDT 24
Peak memory 206944 kb
Host smart-56e6bbdf-5d78-4f28-81f8-958240bb2057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14942
59102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1494259102
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.826099198
Short name T1138
Test name
Test status
Simulation time 161253645 ps
CPU time 0.86 seconds
Started Aug 07 06:01:42 PM PDT 24
Finished Aug 07 06:01:43 PM PDT 24
Peak memory 207020 kb
Host smart-16f1b677-ca33-47a0-97d0-8fab0b799279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82609
9198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.826099198
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3514355863
Short name T986
Test name
Test status
Simulation time 171927244 ps
CPU time 0.87 seconds
Started Aug 07 06:01:45 PM PDT 24
Finished Aug 07 06:01:46 PM PDT 24
Peak memory 206980 kb
Host smart-07d8b148-1365-4ca1-863f-2dbfd9763566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35143
55863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3514355863
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3215955370
Short name T1801
Test name
Test status
Simulation time 217046487 ps
CPU time 1.04 seconds
Started Aug 07 06:01:45 PM PDT 24
Finished Aug 07 06:01:46 PM PDT 24
Peak memory 207000 kb
Host smart-12682715-0e49-4a20-8d7c-afef449cf843
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3215955370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3215955370
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1629203175
Short name T2657
Test name
Test status
Simulation time 151420135 ps
CPU time 0.91 seconds
Started Aug 07 06:01:41 PM PDT 24
Finished Aug 07 06:01:42 PM PDT 24
Peak memory 206944 kb
Host smart-f7d1d66b-2f62-4758-ab27-22290c447591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16292
03175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1629203175
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2693919292
Short name T32
Test name
Test status
Simulation time 61167537 ps
CPU time 0.7 seconds
Started Aug 07 06:01:43 PM PDT 24
Finished Aug 07 06:01:44 PM PDT 24
Peak memory 206972 kb
Host smart-885ee5de-3897-4649-8629-df91f6f182f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26939
19292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2693919292
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2610256773
Short name T1980
Test name
Test status
Simulation time 23053672460 ps
CPU time 58.93 seconds
Started Aug 07 06:01:43 PM PDT 24
Finished Aug 07 06:02:42 PM PDT 24
Peak memory 215584 kb
Host smart-97b2201e-41ec-45c9-800a-5ec822e61d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
56773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2610256773
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1556251478
Short name T2143
Test name
Test status
Simulation time 164118335 ps
CPU time 0.91 seconds
Started Aug 07 06:01:46 PM PDT 24
Finished Aug 07 06:01:47 PM PDT 24
Peak memory 206996 kb
Host smart-d8a70db9-a561-4677-95c9-d1d5264602e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15562
51478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1556251478
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1131388581
Short name T1737
Test name
Test status
Simulation time 309456843 ps
CPU time 1.07 seconds
Started Aug 07 06:01:45 PM PDT 24
Finished Aug 07 06:01:47 PM PDT 24
Peak memory 206956 kb
Host smart-9ffa9edc-9cfc-465e-a87e-4d1179473ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11313
88581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1131388581
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.1733308453
Short name T618
Test name
Test status
Simulation time 157004828 ps
CPU time 0.9 seconds
Started Aug 07 06:01:44 PM PDT 24
Finished Aug 07 06:01:45 PM PDT 24
Peak memory 207004 kb
Host smart-127d2bfa-36bc-4000-8023-fb53119dae77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17333
08453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.1733308453
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1466771202
Short name T513
Test name
Test status
Simulation time 186827617 ps
CPU time 0.96 seconds
Started Aug 07 06:01:44 PM PDT 24
Finished Aug 07 06:01:45 PM PDT 24
Peak memory 207024 kb
Host smart-d61929a9-35c5-4282-9461-b303b1a786ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14667
71202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1466771202
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_resume_link_active.3250156664
Short name T935
Test name
Test status
Simulation time 20149358519 ps
CPU time 23.39 seconds
Started Aug 07 06:01:45 PM PDT 24
Finished Aug 07 06:02:09 PM PDT 24
Peak memory 207104 kb
Host smart-d04efb69-421e-4c57-b994-977479d7b190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32501
56664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.3250156664
Directory /workspace/14.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2642361107
Short name T2365
Test name
Test status
Simulation time 200070272 ps
CPU time 0.99 seconds
Started Aug 07 06:01:46 PM PDT 24
Finished Aug 07 06:01:47 PM PDT 24
Peak memory 206992 kb
Host smart-d1ede485-7ccc-4690-a27c-6c95ef71d058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26423
61107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2642361107
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_rx_full.2072775760
Short name T2779
Test name
Test status
Simulation time 332191708 ps
CPU time 1.16 seconds
Started Aug 07 06:01:42 PM PDT 24
Finished Aug 07 06:01:43 PM PDT 24
Peak memory 207036 kb
Host smart-f65f5523-7373-4ce1-ab19-67452577a624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20727
75760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.2072775760
Directory /workspace/14.usbdev_rx_full/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1193806880
Short name T859
Test name
Test status
Simulation time 147085862 ps
CPU time 0.9 seconds
Started Aug 07 06:01:44 PM PDT 24
Finished Aug 07 06:01:45 PM PDT 24
Peak memory 206940 kb
Host smart-3a262bde-2d24-489d-9b1f-2522d85db0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11938
06880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1193806880
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2923030585
Short name T2897
Test name
Test status
Simulation time 168651041 ps
CPU time 0.91 seconds
Started Aug 07 06:01:50 PM PDT 24
Finished Aug 07 06:01:51 PM PDT 24
Peak memory 206968 kb
Host smart-39c32caf-03ef-46c6-9b59-b29b31b309c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29230
30585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2923030585
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2641116035
Short name T172
Test name
Test status
Simulation time 242192419 ps
CPU time 1.09 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:01:50 PM PDT 24
Peak memory 206964 kb
Host smart-6d90d419-7473-490d-9200-2780f9576b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26411
16035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2641116035
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.570402135
Short name T189
Test name
Test status
Simulation time 2582265378 ps
CPU time 75.09 seconds
Started Aug 07 06:01:51 PM PDT 24
Finished Aug 07 06:03:06 PM PDT 24
Peak memory 223624 kb
Host smart-892ac6d4-c7c1-41f5-b577-2d58714c0dad
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=570402135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.570402135
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.769838548
Short name T2165
Test name
Test status
Simulation time 250822769 ps
CPU time 0.98 seconds
Started Aug 07 06:01:47 PM PDT 24
Finished Aug 07 06:01:48 PM PDT 24
Peak memory 206992 kb
Host smart-c6a0c19f-1ace-4290-883e-fe85484374fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76983
8548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.769838548
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1474124727
Short name T588
Test name
Test status
Simulation time 161186143 ps
CPU time 0.82 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:01:50 PM PDT 24
Peak memory 207000 kb
Host smart-9b4b932f-8cf4-44d4-a7cf-b707c0589bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14741
24727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1474124727
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.1884253979
Short name T892
Test name
Test status
Simulation time 339638170 ps
CPU time 1.19 seconds
Started Aug 07 06:01:52 PM PDT 24
Finished Aug 07 06:01:53 PM PDT 24
Peak memory 207012 kb
Host smart-ddd83c6b-fb39-407d-9948-cc7d8b400d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18842
53979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.1884253979
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2900621890
Short name T1451
Test name
Test status
Simulation time 2926687309 ps
CPU time 23.24 seconds
Started Aug 07 06:01:48 PM PDT 24
Finished Aug 07 06:02:12 PM PDT 24
Peak memory 215536 kb
Host smart-5d2f1510-02c5-4462-9e22-f8ca2a9cd961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29006
21890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2900621890
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.2079481196
Short name T1447
Test name
Test status
Simulation time 1000216907 ps
CPU time 22.93 seconds
Started Aug 07 06:01:44 PM PDT 24
Finished Aug 07 06:02:08 PM PDT 24
Peak memory 207172 kb
Host smart-e1eb6347-7fa6-4b93-939f-e732c043a7d8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079481196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.2079481196
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/140.usbdev_endpoint_types.3725854404
Short name T464
Test name
Test status
Simulation time 424303435 ps
CPU time 1.46 seconds
Started Aug 07 06:13:10 PM PDT 24
Finished Aug 07 06:13:11 PM PDT 24
Peak memory 206876 kb
Host smart-da3c4341-f224-436f-8cef-24258359b6f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3725854404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.3725854404
Directory /workspace/140.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/141.usbdev_endpoint_types.855380343
Short name T3094
Test name
Test status
Simulation time 255375348 ps
CPU time 0.99 seconds
Started Aug 07 06:13:18 PM PDT 24
Finished Aug 07 06:13:19 PM PDT 24
Peak memory 206948 kb
Host smart-52dc0f05-11a2-41dd-bd2d-2063ae8f91b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=855380343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.855380343
Directory /workspace/141.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/144.usbdev_endpoint_types.3955111998
Short name T440
Test name
Test status
Simulation time 189419032 ps
CPU time 0.95 seconds
Started Aug 07 06:13:12 PM PDT 24
Finished Aug 07 06:13:13 PM PDT 24
Peak memory 206948 kb
Host smart-d00fdd8f-5ece-436b-b73f-0ce118b71638
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3955111998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.3955111998
Directory /workspace/144.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/145.usbdev_endpoint_types.540985805
Short name T432
Test name
Test status
Simulation time 635245688 ps
CPU time 1.47 seconds
Started Aug 07 06:13:11 PM PDT 24
Finished Aug 07 06:13:13 PM PDT 24
Peak memory 206948 kb
Host smart-82b09de4-2421-4c6d-8b03-c499ff7a2de8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=540985805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.540985805
Directory /workspace/145.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/146.usbdev_endpoint_types.2113153610
Short name T453
Test name
Test status
Simulation time 395126964 ps
CPU time 1.16 seconds
Started Aug 07 06:13:14 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206876 kb
Host smart-d2d1dbb0-d13f-4725-9907-e60e2b74d387
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2113153610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.2113153610
Directory /workspace/146.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/147.usbdev_endpoint_types.3964650209
Short name T456
Test name
Test status
Simulation time 393381691 ps
CPU time 1.27 seconds
Started Aug 07 06:13:13 PM PDT 24
Finished Aug 07 06:13:14 PM PDT 24
Peak memory 206944 kb
Host smart-272b213c-f9a7-4f18-b365-88d6b18cce67
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3964650209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.3964650209
Directory /workspace/147.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/148.usbdev_endpoint_types.3454997308
Short name T936
Test name
Test status
Simulation time 273604776 ps
CPU time 0.97 seconds
Started Aug 07 06:13:09 PM PDT 24
Finished Aug 07 06:13:10 PM PDT 24
Peak memory 206972 kb
Host smart-b6dba025-3b60-492c-9c4f-bfcb2107f9f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3454997308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.3454997308
Directory /workspace/148.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.3496528210
Short name T1360
Test name
Test status
Simulation time 111538222 ps
CPU time 0.78 seconds
Started Aug 07 06:02:01 PM PDT 24
Finished Aug 07 06:02:02 PM PDT 24
Peak memory 207064 kb
Host smart-da87b1e6-fe64-4560-8498-ca20b103cd05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3496528210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3496528210
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2578714730
Short name T1700
Test name
Test status
Simulation time 10754302103 ps
CPU time 14.05 seconds
Started Aug 07 06:02:00 PM PDT 24
Finished Aug 07 06:02:14 PM PDT 24
Peak memory 207336 kb
Host smart-2121a46c-90ae-4c46-99e5-126975a605a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578714730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.2578714730
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.1707864924
Short name T1311
Test name
Test status
Simulation time 13352428200 ps
CPU time 17.37 seconds
Started Aug 07 06:01:48 PM PDT 24
Finished Aug 07 06:02:06 PM PDT 24
Peak memory 215436 kb
Host smart-f7860fb4-5b83-40e6-9b3d-faa4eebefe26
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707864924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.1707864924
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.4137550214
Short name T3081
Test name
Test status
Simulation time 25247741277 ps
CPU time 30.86 seconds
Started Aug 07 06:01:51 PM PDT 24
Finished Aug 07 06:02:22 PM PDT 24
Peak memory 215500 kb
Host smart-2057aa6b-e76c-48ba-a43e-7b1e2dd7f3af
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137550214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.4137550214
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2502694749
Short name T2081
Test name
Test status
Simulation time 146023158 ps
CPU time 0.88 seconds
Started Aug 07 06:01:47 PM PDT 24
Finished Aug 07 06:01:48 PM PDT 24
Peak memory 207036 kb
Host smart-33f4d166-0dfd-4f97-8a6f-8917337d7b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25026
94749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2502694749
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2338968858
Short name T1532
Test name
Test status
Simulation time 158053955 ps
CPU time 0.86 seconds
Started Aug 07 06:01:51 PM PDT 24
Finished Aug 07 06:01:52 PM PDT 24
Peak memory 206956 kb
Host smart-61fa869a-d874-4fff-8cfe-f9e9f004a10b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23389
68858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2338968858
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1017626754
Short name T578
Test name
Test status
Simulation time 440971580 ps
CPU time 1.5 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:01:51 PM PDT 24
Peak memory 206996 kb
Host smart-6603bf15-e6e1-4370-909e-d929f51bdb0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10176
26754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1017626754
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3039550203
Short name T2100
Test name
Test status
Simulation time 671873483 ps
CPU time 1.88 seconds
Started Aug 07 06:01:51 PM PDT 24
Finished Aug 07 06:01:53 PM PDT 24
Peak memory 207008 kb
Host smart-e6c33683-5c08-4b06-894f-7053caa7c99b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3039550203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3039550203
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.667814922
Short name T399
Test name
Test status
Simulation time 15350000546 ps
CPU time 30.05 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:02:20 PM PDT 24
Peak memory 207320 kb
Host smart-2db97185-c1bf-45f2-8e3d-90a751a07be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66781
4922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.667814922
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.3649096174
Short name T2969
Test name
Test status
Simulation time 876951118 ps
CPU time 18.93 seconds
Started Aug 07 06:01:48 PM PDT 24
Finished Aug 07 06:02:07 PM PDT 24
Peak memory 207112 kb
Host smart-542c96ec-451c-4c16-bba4-dec0995025cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649096174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.3649096174
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.1021592810
Short name T2832
Test name
Test status
Simulation time 1121449283 ps
CPU time 2.38 seconds
Started Aug 07 06:01:48 PM PDT 24
Finished Aug 07 06:01:51 PM PDT 24
Peak memory 206944 kb
Host smart-037bf73f-f60d-4cd9-9b8d-e08d766ef58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10215
92810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.1021592810
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_enable.688069773
Short name T1797
Test name
Test status
Simulation time 30779778 ps
CPU time 0.68 seconds
Started Aug 07 06:01:51 PM PDT 24
Finished Aug 07 06:01:52 PM PDT 24
Peak memory 206980 kb
Host smart-c4629e0d-581e-4d0c-ad4e-fd1313369035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68806
9773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.688069773
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3354507741
Short name T1971
Test name
Test status
Simulation time 795541157 ps
CPU time 2.26 seconds
Started Aug 07 06:01:50 PM PDT 24
Finished Aug 07 06:01:52 PM PDT 24
Peak memory 207172 kb
Host smart-0196a8f0-ead3-4289-a462-aba9dc7b5028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33545
07741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3354507741
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.4277666155
Short name T2913
Test name
Test status
Simulation time 239411930 ps
CPU time 1.51 seconds
Started Aug 07 06:01:48 PM PDT 24
Finished Aug 07 06:01:49 PM PDT 24
Peak memory 207124 kb
Host smart-b9e30f58-2856-43bf-8519-9cb1169e7717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42776
66155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.4277666155
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.333923122
Short name T2135
Test name
Test status
Simulation time 183004127 ps
CPU time 0.94 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:01:51 PM PDT 24
Peak memory 206908 kb
Host smart-8e2c645b-a55d-4210-9545-d2c085777560
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=333923122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.333923122
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1222129232
Short name T1096
Test name
Test status
Simulation time 146467554 ps
CPU time 0.81 seconds
Started Aug 07 06:01:52 PM PDT 24
Finished Aug 07 06:01:53 PM PDT 24
Peak memory 207012 kb
Host smart-7ce7e5a9-3a92-445a-9bdf-9e5d7c0789e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12221
29232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1222129232
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.4122417427
Short name T1021
Test name
Test status
Simulation time 207828795 ps
CPU time 0.9 seconds
Started Aug 07 06:01:50 PM PDT 24
Finished Aug 07 06:01:52 PM PDT 24
Peak memory 206976 kb
Host smart-cd8af110-c7ec-4ea0-adc8-5f9d3e700288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41224
17427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.4122417427
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.615542195
Short name T2279
Test name
Test status
Simulation time 2780979187 ps
CPU time 19.95 seconds
Started Aug 07 06:01:50 PM PDT 24
Finished Aug 07 06:02:11 PM PDT 24
Peak memory 223724 kb
Host smart-27827a8e-ebda-487b-979d-234a3209dff2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=615542195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.615542195
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.4159557629
Short name T985
Test name
Test status
Simulation time 5049313916 ps
CPU time 34.21 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 207288 kb
Host smart-957060b8-ebda-47af-854d-31e74963a2d8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4159557629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.4159557629
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.991734672
Short name T1782
Test name
Test status
Simulation time 185478507 ps
CPU time 0.96 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:01:50 PM PDT 24
Peak memory 206924 kb
Host smart-8f0a0f5e-b857-4aa8-adf2-9a460433dcb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99173
4672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.991734672
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.1634389019
Short name T556
Test name
Test status
Simulation time 22752628625 ps
CPU time 39.13 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:02:28 PM PDT 24
Peak memory 215472 kb
Host smart-ac096b09-430e-466c-8d3d-28ec1bd8b38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16343
89019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.1634389019
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.732274929
Short name T1304
Test name
Test status
Simulation time 4133434879 ps
CPU time 5.79 seconds
Started Aug 07 06:01:48 PM PDT 24
Finished Aug 07 06:01:54 PM PDT 24
Peak memory 207288 kb
Host smart-3750b4dd-df83-4bff-9cf4-7e5c3fc94092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73227
4929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.732274929
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2010053552
Short name T1806
Test name
Test status
Simulation time 4869411703 ps
CPU time 142.95 seconds
Started Aug 07 06:01:50 PM PDT 24
Finished Aug 07 06:04:13 PM PDT 24
Peak memory 218124 kb
Host smart-e47af748-87f6-4165-af5f-3900a7c5893a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20100
53552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2010053552
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.4181274367
Short name T1405
Test name
Test status
Simulation time 2595984758 ps
CPU time 73.24 seconds
Started Aug 07 06:01:49 PM PDT 24
Finished Aug 07 06:03:03 PM PDT 24
Peak memory 223436 kb
Host smart-b0e9bd62-0095-427b-b803-36a2541a081d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4181274367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.4181274367
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3316373981
Short name T580
Test name
Test status
Simulation time 294692183 ps
CPU time 1.1 seconds
Started Aug 07 06:01:50 PM PDT 24
Finished Aug 07 06:01:52 PM PDT 24
Peak memory 206904 kb
Host smart-ad317dbb-372f-4973-a49d-028c613c3639
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3316373981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3316373981
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.4147828657
Short name T1958
Test name
Test status
Simulation time 191083782 ps
CPU time 0.94 seconds
Started Aug 07 06:01:48 PM PDT 24
Finished Aug 07 06:01:49 PM PDT 24
Peak memory 207000 kb
Host smart-107a37dd-aca2-461e-8092-e01f22057e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41478
28657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.4147828657
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.2630913983
Short name T2871
Test name
Test status
Simulation time 2086858686 ps
CPU time 15.73 seconds
Started Aug 07 06:01:56 PM PDT 24
Finished Aug 07 06:02:12 PM PDT 24
Peak memory 223556 kb
Host smart-4e4f6f3a-dd3a-4c83-8777-4cf073564ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26309
13983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.2630913983
Directory /workspace/15.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2866090036
Short name T1480
Test name
Test status
Simulation time 3362599102 ps
CPU time 28.82 seconds
Started Aug 07 06:01:56 PM PDT 24
Finished Aug 07 06:02:25 PM PDT 24
Peak memory 215564 kb
Host smart-8788f020-2071-4778-9b5b-09019f1b93bd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2866090036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2866090036
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1750923135
Short name T1129
Test name
Test status
Simulation time 166307131 ps
CPU time 0.88 seconds
Started Aug 07 06:01:55 PM PDT 24
Finished Aug 07 06:01:56 PM PDT 24
Peak memory 206988 kb
Host smart-3ba8361b-25f4-4fe6-b1a5-702f21b8640e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1750923135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1750923135
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.396983244
Short name T2272
Test name
Test status
Simulation time 147398144 ps
CPU time 0.84 seconds
Started Aug 07 06:01:58 PM PDT 24
Finished Aug 07 06:01:59 PM PDT 24
Peak memory 207004 kb
Host smart-2874a271-8713-4684-9fce-8fadd31939ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39698
3244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.396983244
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3089514794
Short name T2166
Test name
Test status
Simulation time 178831256 ps
CPU time 0.89 seconds
Started Aug 07 06:01:56 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 206948 kb
Host smart-3cba4628-38bd-41ed-8669-98c3ae22b17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30895
14794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3089514794
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.517962854
Short name T2182
Test name
Test status
Simulation time 228367833 ps
CPU time 1.05 seconds
Started Aug 07 06:01:56 PM PDT 24
Finished Aug 07 06:01:58 PM PDT 24
Peak memory 206960 kb
Host smart-d10fbfc6-c7d1-46ae-8d0b-82a67168b236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51796
2854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.517962854
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3831486832
Short name T2639
Test name
Test status
Simulation time 192672471 ps
CPU time 0.99 seconds
Started Aug 07 06:01:55 PM PDT 24
Finished Aug 07 06:01:56 PM PDT 24
Peak memory 206992 kb
Host smart-fa038389-11df-46ac-8589-22cc8b4dff54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38314
86832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3831486832
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.9442627
Short name T1649
Test name
Test status
Simulation time 205973099 ps
CPU time 1.01 seconds
Started Aug 07 06:01:56 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 207020 kb
Host smart-4b7d4492-f444-4fc2-b085-3714a3c67c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94426
27 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.9442627
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.960792889
Short name T2473
Test name
Test status
Simulation time 151675527 ps
CPU time 0.87 seconds
Started Aug 07 06:01:57 PM PDT 24
Finished Aug 07 06:01:58 PM PDT 24
Peak memory 206992 kb
Host smart-322440b6-c6d5-44ae-a72e-b969a0cbe696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96079
2889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.960792889
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.1502146159
Short name T1119
Test name
Test status
Simulation time 234053065 ps
CPU time 1.09 seconds
Started Aug 07 06:01:57 PM PDT 24
Finished Aug 07 06:01:58 PM PDT 24
Peak memory 206928 kb
Host smart-0f3499f1-dc12-4da1-a7f1-86bc0e747178
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1502146159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.1502146159
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2749191473
Short name T2437
Test name
Test status
Simulation time 145640268 ps
CPU time 0.81 seconds
Started Aug 07 06:01:55 PM PDT 24
Finished Aug 07 06:01:56 PM PDT 24
Peak memory 207004 kb
Host smart-cf493c0a-2f0c-4a0b-b5a4-aaa8ee3c9c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27491
91473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2749191473
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.4282569316
Short name T2093
Test name
Test status
Simulation time 18968820963 ps
CPU time 48.52 seconds
Started Aug 07 06:01:56 PM PDT 24
Finished Aug 07 06:02:45 PM PDT 24
Peak memory 219328 kb
Host smart-09e2418a-df8a-4fe9-85fd-d7c0eddeeea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42825
69316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.4282569316
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1035139597
Short name T662
Test name
Test status
Simulation time 153669999 ps
CPU time 0.85 seconds
Started Aug 07 06:01:57 PM PDT 24
Finished Aug 07 06:01:58 PM PDT 24
Peak memory 206972 kb
Host smart-b0e30034-6d9b-47de-b90a-d1ba902e4f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10351
39597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1035139597
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2579507920
Short name T1564
Test name
Test status
Simulation time 179920702 ps
CPU time 0.91 seconds
Started Aug 07 06:01:55 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 207008 kb
Host smart-07d48b26-c0ba-4d14-8249-2f7fd8d67c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25795
07920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2579507920
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.4017195760
Short name T971
Test name
Test status
Simulation time 261581974 ps
CPU time 1.01 seconds
Started Aug 07 06:01:58 PM PDT 24
Finished Aug 07 06:01:59 PM PDT 24
Peak memory 206984 kb
Host smart-d6d49325-4a29-4309-99cd-bf89e7b95e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40171
95760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.4017195760
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1971805585
Short name T2215
Test name
Test status
Simulation time 188483511 ps
CPU time 0.9 seconds
Started Aug 07 06:01:56 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 206984 kb
Host smart-74f46453-21b4-4c78-8305-44831436ac93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19718
05585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1971805585
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_resume_link_active.4197857501
Short name T115
Test name
Test status
Simulation time 20185812350 ps
CPU time 23.73 seconds
Started Aug 07 06:01:57 PM PDT 24
Finished Aug 07 06:02:21 PM PDT 24
Peak memory 207056 kb
Host smart-8a8709c0-713a-42a0-ae13-26d3f3cad46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41978
57501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.4197857501
Directory /workspace/15.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.250918697
Short name T2015
Test name
Test status
Simulation time 143382204 ps
CPU time 0.82 seconds
Started Aug 07 06:01:54 PM PDT 24
Finished Aug 07 06:01:55 PM PDT 24
Peak memory 206960 kb
Host smart-8124621e-33a7-48cd-966b-3c9d343cb2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25091
8697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.250918697
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_rx_full.654761127
Short name T1045
Test name
Test status
Simulation time 259176064 ps
CPU time 1.15 seconds
Started Aug 07 06:01:55 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 206956 kb
Host smart-6cadec52-5213-4d5d-b8d0-20a63084cead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65476
1127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.654761127
Directory /workspace/15.usbdev_rx_full/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.1372393225
Short name T1430
Test name
Test status
Simulation time 160120669 ps
CPU time 0.86 seconds
Started Aug 07 06:01:55 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 206972 kb
Host smart-7902e29d-5a24-45cd-81a1-c81bfd8eb446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13723
93225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.1372393225
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2109479205
Short name T593
Test name
Test status
Simulation time 146830257 ps
CPU time 0.86 seconds
Started Aug 07 06:01:58 PM PDT 24
Finished Aug 07 06:01:59 PM PDT 24
Peak memory 206984 kb
Host smart-b797d12c-d41e-4e34-a688-eb6be17d5294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21094
79205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2109479205
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3311939774
Short name T1332
Test name
Test status
Simulation time 215059332 ps
CPU time 1.05 seconds
Started Aug 07 06:01:56 PM PDT 24
Finished Aug 07 06:01:58 PM PDT 24
Peak memory 206964 kb
Host smart-3dd53f21-7969-401f-9625-3110b8ca8b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33119
39774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3311939774
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.4119824374
Short name T2450
Test name
Test status
Simulation time 3376281200 ps
CPU time 95.11 seconds
Started Aug 07 06:01:57 PM PDT 24
Finished Aug 07 06:03:32 PM PDT 24
Peak memory 223668 kb
Host smart-72e554fd-c71b-4ad1-a7dd-736e6554d79e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4119824374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.4119824374
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1274406991
Short name T2733
Test name
Test status
Simulation time 186736154 ps
CPU time 0.93 seconds
Started Aug 07 06:01:56 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 206904 kb
Host smart-38f4731e-90c1-4337-bbbd-ae0a408ab08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12744
06991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1274406991
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.61899402
Short name T1388
Test name
Test status
Simulation time 188993264 ps
CPU time 0.87 seconds
Started Aug 07 06:01:54 PM PDT 24
Finished Aug 07 06:01:55 PM PDT 24
Peak memory 206972 kb
Host smart-e8f5dc27-a6c5-4398-b022-62d82e809c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61899
402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.61899402
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.3918290835
Short name T2390
Test name
Test status
Simulation time 1240243297 ps
CPU time 2.88 seconds
Started Aug 07 06:01:57 PM PDT 24
Finished Aug 07 06:02:00 PM PDT 24
Peak memory 207208 kb
Host smart-86544c88-2c3b-4967-be67-c4f258a11714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39182
90835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.3918290835
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.858822075
Short name T183
Test name
Test status
Simulation time 4093551570 ps
CPU time 32.54 seconds
Started Aug 07 06:01:58 PM PDT 24
Finished Aug 07 06:02:30 PM PDT 24
Peak memory 215540 kb
Host smart-1b616573-9f1c-47a3-b314-343c6621dcae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85882
2075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.858822075
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.1152174607
Short name T766
Test name
Test status
Simulation time 5240524986 ps
CPU time 44.86 seconds
Started Aug 07 06:01:50 PM PDT 24
Finished Aug 07 06:02:36 PM PDT 24
Peak memory 207300 kb
Host smart-0decb108-1d22-4f8a-9be5-6c6c6b4fc41a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152174607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.1152174607
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/151.usbdev_endpoint_types.1636532942
Short name T349
Test name
Test status
Simulation time 491891618 ps
CPU time 1.41 seconds
Started Aug 07 06:13:11 PM PDT 24
Finished Aug 07 06:13:13 PM PDT 24
Peak memory 206956 kb
Host smart-f06f5d0c-2042-4dfd-b507-7fe8eb2e7738
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1636532942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.1636532942
Directory /workspace/151.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/152.usbdev_endpoint_types.2807377090
Short name T426
Test name
Test status
Simulation time 327261348 ps
CPU time 1.1 seconds
Started Aug 07 06:13:13 PM PDT 24
Finished Aug 07 06:13:14 PM PDT 24
Peak memory 206944 kb
Host smart-39b7f91e-b2d8-4ce0-8c79-4a9cac0edc79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2807377090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.2807377090
Directory /workspace/152.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/153.usbdev_endpoint_types.1005209986
Short name T412
Test name
Test status
Simulation time 369771562 ps
CPU time 1.1 seconds
Started Aug 07 06:13:23 PM PDT 24
Finished Aug 07 06:13:24 PM PDT 24
Peak memory 206960 kb
Host smart-892599a3-867a-4566-9805-202be91991a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1005209986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.1005209986
Directory /workspace/153.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/155.usbdev_endpoint_types.2498956067
Short name T2444
Test name
Test status
Simulation time 299713468 ps
CPU time 1.11 seconds
Started Aug 07 06:13:10 PM PDT 24
Finished Aug 07 06:13:11 PM PDT 24
Peak memory 206944 kb
Host smart-679e6a61-c655-4e87-b130-89111ee9d4cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2498956067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.2498956067
Directory /workspace/155.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/156.usbdev_endpoint_types.604776820
Short name T366
Test name
Test status
Simulation time 565812478 ps
CPU time 1.51 seconds
Started Aug 07 06:13:10 PM PDT 24
Finished Aug 07 06:13:11 PM PDT 24
Peak memory 206972 kb
Host smart-4479b4ed-51b5-494e-a418-a7ded4eba012
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=604776820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.604776820
Directory /workspace/156.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/158.usbdev_endpoint_types.4144826302
Short name T408
Test name
Test status
Simulation time 519094106 ps
CPU time 1.51 seconds
Started Aug 07 06:13:13 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206972 kb
Host smart-e36a68b4-45ac-4b75-9405-4f4b409133c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4144826302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.4144826302
Directory /workspace/158.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/159.usbdev_endpoint_types.3544338430
Short name T1957
Test name
Test status
Simulation time 495470171 ps
CPU time 1.41 seconds
Started Aug 07 06:13:16 PM PDT 24
Finished Aug 07 06:13:17 PM PDT 24
Peak memory 207000 kb
Host smart-d268b05f-95fe-4159-a8b0-256a58f518e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3544338430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.3544338430
Directory /workspace/159.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.1680761358
Short name T1729
Test name
Test status
Simulation time 37796577 ps
CPU time 0.64 seconds
Started Aug 07 06:02:05 PM PDT 24
Finished Aug 07 06:02:06 PM PDT 24
Peak memory 207032 kb
Host smart-90a954cd-7110-4536-86df-88d9d85c4bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1680761358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.1680761358
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3988146637
Short name T10
Test name
Test status
Simulation time 6321301241 ps
CPU time 9.31 seconds
Started Aug 07 06:01:56 PM PDT 24
Finished Aug 07 06:02:06 PM PDT 24
Peak memory 215460 kb
Host smart-f9e20198-7f54-48d1-91fa-e845116f0acd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988146637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.3988146637
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3871503295
Short name T819
Test name
Test status
Simulation time 21065089732 ps
CPU time 24.85 seconds
Started Aug 07 06:02:00 PM PDT 24
Finished Aug 07 06:02:25 PM PDT 24
Peak memory 207252 kb
Host smart-31df514c-fe44-4424-84f4-436f561cb986
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871503295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3871503295
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.533033850
Short name T13
Test name
Test status
Simulation time 24435161173 ps
CPU time 28.42 seconds
Started Aug 07 06:02:03 PM PDT 24
Finished Aug 07 06:02:31 PM PDT 24
Peak memory 215516 kb
Host smart-8285db97-a2ba-44a0-91d8-f58334ceed26
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533033850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ao
n_wake_resume.533033850
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2008496936
Short name T2408
Test name
Test status
Simulation time 235882775 ps
CPU time 1.03 seconds
Started Aug 07 06:02:00 PM PDT 24
Finished Aug 07 06:02:02 PM PDT 24
Peak memory 207016 kb
Host smart-c5facf62-cff5-4e25-b4dd-5fb193878a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20084
96936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2008496936
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3282485179
Short name T488
Test name
Test status
Simulation time 165106493 ps
CPU time 0.9 seconds
Started Aug 07 06:02:01 PM PDT 24
Finished Aug 07 06:02:02 PM PDT 24
Peak memory 206972 kb
Host smart-7476ca8f-0c33-478d-af80-e67911a35545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32824
85179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3282485179
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.4033345485
Short name T2405
Test name
Test status
Simulation time 652687006 ps
CPU time 2.08 seconds
Started Aug 07 06:02:04 PM PDT 24
Finished Aug 07 06:02:06 PM PDT 24
Peak memory 207140 kb
Host smart-c3ec1f3b-f783-4bbf-b41d-86b1d3395ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40333
45485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.4033345485
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3864225825
Short name T3028
Test name
Test status
Simulation time 1085853637 ps
CPU time 2.81 seconds
Started Aug 07 06:02:01 PM PDT 24
Finished Aug 07 06:02:04 PM PDT 24
Peak memory 207112 kb
Host smart-dcd9a26f-fba7-439f-95ce-e7ad3960c848
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3864225825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3864225825
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3843840610
Short name T1166
Test name
Test status
Simulation time 38415089578 ps
CPU time 59.05 seconds
Started Aug 07 06:02:02 PM PDT 24
Finished Aug 07 06:03:01 PM PDT 24
Peak memory 207332 kb
Host smart-c3a6553a-5cd0-47b8-8a5e-99a3965590f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38438
40610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3843840610
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.1909386024
Short name T1666
Test name
Test status
Simulation time 1506066249 ps
CPU time 9.81 seconds
Started Aug 07 06:02:06 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 207096 kb
Host smart-d4af12d5-0b13-4f84-96be-00973aefb2ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909386024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.1909386024
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.661446979
Short name T1162
Test name
Test status
Simulation time 872456773 ps
CPU time 1.9 seconds
Started Aug 07 06:02:02 PM PDT 24
Finished Aug 07 06:02:04 PM PDT 24
Peak memory 206968 kb
Host smart-ffc054f8-baa8-45f9-924c-b7a5240d293e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66144
6979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.661446979
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.1635512211
Short name T1026
Test name
Test status
Simulation time 195999460 ps
CPU time 0.9 seconds
Started Aug 07 06:02:05 PM PDT 24
Finished Aug 07 06:02:06 PM PDT 24
Peak memory 206988 kb
Host smart-22678bd6-4ca2-4d57-b799-1b94e9ff2d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16355
12211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1635512211
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.2230383513
Short name T557
Test name
Test status
Simulation time 44046543 ps
CPU time 0.78 seconds
Started Aug 07 06:02:02 PM PDT 24
Finished Aug 07 06:02:03 PM PDT 24
Peak memory 206956 kb
Host smart-840b8f41-def8-4072-bc5a-bf16e4b1b6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22303
83513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2230383513
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2077968851
Short name T1263
Test name
Test status
Simulation time 1063555039 ps
CPU time 2.56 seconds
Started Aug 07 06:02:03 PM PDT 24
Finished Aug 07 06:02:06 PM PDT 24
Peak memory 207268 kb
Host smart-fdd4b491-79d4-4f44-a0d9-df3cdad8cae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20779
68851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2077968851
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.193738069
Short name T649
Test name
Test status
Simulation time 306842296 ps
CPU time 2.04 seconds
Started Aug 07 06:02:00 PM PDT 24
Finished Aug 07 06:02:03 PM PDT 24
Peak memory 207076 kb
Host smart-a22a568c-e6e0-4df5-bf1e-e8a5d3f38117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19373
8069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.193738069
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.194398378
Short name T2301
Test name
Test status
Simulation time 176599640 ps
CPU time 0.96 seconds
Started Aug 07 06:02:06 PM PDT 24
Finished Aug 07 06:02:07 PM PDT 24
Peak memory 206912 kb
Host smart-33d9516f-6fd0-4ff7-b926-b23bed584278
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=194398378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.194398378
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2266029205
Short name T483
Test name
Test status
Simulation time 147405115 ps
CPU time 0.78 seconds
Started Aug 07 06:02:04 PM PDT 24
Finished Aug 07 06:02:05 PM PDT 24
Peak memory 206952 kb
Host smart-380811b4-10c7-4433-823b-091b594f994b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22660
29205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2266029205
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3796348635
Short name T3013
Test name
Test status
Simulation time 182419269 ps
CPU time 0.93 seconds
Started Aug 07 06:02:03 PM PDT 24
Finished Aug 07 06:02:04 PM PDT 24
Peak memory 206908 kb
Host smart-8afa5f8e-c9f5-459b-962b-56a9b768e11b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37963
48635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3796348635
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.796303312
Short name T1864
Test name
Test status
Simulation time 3996827528 ps
CPU time 30.12 seconds
Started Aug 07 06:01:59 PM PDT 24
Finished Aug 07 06:02:29 PM PDT 24
Peak memory 215560 kb
Host smart-3b088d12-2c07-4599-93bd-d832fb4fe71a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=796303312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.796303312
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.2627083615
Short name T761
Test name
Test status
Simulation time 8166281735 ps
CPU time 54.26 seconds
Started Aug 07 06:02:01 PM PDT 24
Finished Aug 07 06:02:56 PM PDT 24
Peak memory 207244 kb
Host smart-63cd95f0-8c31-443e-ac0b-8c1331c71ebf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2627083615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.2627083615
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.386349290
Short name T1763
Test name
Test status
Simulation time 169786724 ps
CPU time 0.92 seconds
Started Aug 07 06:02:07 PM PDT 24
Finished Aug 07 06:02:08 PM PDT 24
Peak memory 206980 kb
Host smart-bd018b35-9468-40cf-bb16-e4d0b32c7804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38634
9290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.386349290
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1091830912
Short name T2989
Test name
Test status
Simulation time 13310698559 ps
CPU time 16.71 seconds
Started Aug 07 06:01:59 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 207244 kb
Host smart-2b74cee0-407b-4c33-b63a-a0f007844889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10918
30912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1091830912
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.612286947
Short name T2037
Test name
Test status
Simulation time 4324914422 ps
CPU time 5.89 seconds
Started Aug 07 06:02:03 PM PDT 24
Finished Aug 07 06:02:09 PM PDT 24
Peak memory 207156 kb
Host smart-181c5b4c-6463-4b8e-b921-55c5ad7cd63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61228
6947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.612286947
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.2388910588
Short name T2358
Test name
Test status
Simulation time 2921502641 ps
CPU time 20.04 seconds
Started Aug 07 06:02:03 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 223740 kb
Host smart-6d3545e2-81c0-48ce-aebe-647cab48c40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23889
10588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2388910588
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.3025481122
Short name T1544
Test name
Test status
Simulation time 2063495279 ps
CPU time 21.26 seconds
Started Aug 07 06:02:01 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 215404 kb
Host smart-60070c1a-716c-4e96-a02d-a7068d4bad7e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3025481122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.3025481122
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.2196239524
Short name T2993
Test name
Test status
Simulation time 294751232 ps
CPU time 1.04 seconds
Started Aug 07 06:02:01 PM PDT 24
Finished Aug 07 06:02:02 PM PDT 24
Peak memory 206972 kb
Host smart-d7e7145f-6bdc-4c6d-ae7a-fbdff230c74b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2196239524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.2196239524
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1231934518
Short name T1954
Test name
Test status
Simulation time 187553044 ps
CPU time 1.01 seconds
Started Aug 07 06:02:02 PM PDT 24
Finished Aug 07 06:02:03 PM PDT 24
Peak memory 206980 kb
Host smart-b012143d-2c90-4a6e-8369-dac34c6a6586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12319
34518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1231934518
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.819362058
Short name T1591
Test name
Test status
Simulation time 1914326681 ps
CPU time 13.89 seconds
Started Aug 07 06:02:03 PM PDT 24
Finished Aug 07 06:02:17 PM PDT 24
Peak memory 223504 kb
Host smart-7fa48fb5-9fb6-43ce-a583-a8af501215a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81936
2058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.819362058
Directory /workspace/16.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3768468010
Short name T1175
Test name
Test status
Simulation time 3699981377 ps
CPU time 109.99 seconds
Started Aug 07 06:02:03 PM PDT 24
Finished Aug 07 06:03:53 PM PDT 24
Peak memory 215428 kb
Host smart-fa48503b-c655-4f90-a5f8-a7d76627add8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3768468010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3768468010
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3344858225
Short name T2700
Test name
Test status
Simulation time 168355294 ps
CPU time 0.9 seconds
Started Aug 07 06:02:02 PM PDT 24
Finished Aug 07 06:02:03 PM PDT 24
Peak memory 206896 kb
Host smart-a4b23502-c7e8-4233-a11c-7ab53d349d72
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3344858225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3344858225
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.4275639036
Short name T2483
Test name
Test status
Simulation time 200638384 ps
CPU time 0.94 seconds
Started Aug 07 06:02:04 PM PDT 24
Finished Aug 07 06:02:05 PM PDT 24
Peak memory 206988 kb
Host smart-3278f690-050f-44eb-8485-2af2145266ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42756
39036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.4275639036
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1990549233
Short name T1825
Test name
Test status
Simulation time 159486307 ps
CPU time 0.89 seconds
Started Aug 07 06:02:02 PM PDT 24
Finished Aug 07 06:02:03 PM PDT 24
Peak memory 207004 kb
Host smart-c7666f07-f049-43e2-82ec-5ec359959632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19905
49233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1990549233
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3953824515
Short name T1665
Test name
Test status
Simulation time 194429342 ps
CPU time 0.89 seconds
Started Aug 07 06:02:05 PM PDT 24
Finished Aug 07 06:02:06 PM PDT 24
Peak memory 207016 kb
Host smart-dad5e422-2f5f-4da9-bfd5-a820fc08dddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39538
24515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3953824515
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3737526316
Short name T2941
Test name
Test status
Simulation time 150432167 ps
CPU time 0.83 seconds
Started Aug 07 06:02:05 PM PDT 24
Finished Aug 07 06:02:06 PM PDT 24
Peak memory 207024 kb
Host smart-c5ec66f9-ad23-4a00-b5f2-c5aa6affeea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37375
26316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3737526316
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.306860256
Short name T2566
Test name
Test status
Simulation time 159060342 ps
CPU time 0.84 seconds
Started Aug 07 06:02:02 PM PDT 24
Finished Aug 07 06:02:03 PM PDT 24
Peak memory 207192 kb
Host smart-00a7494e-e09f-45a6-bc69-ac9e84b030ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30686
0256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.306860256
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.2255780513
Short name T2719
Test name
Test status
Simulation time 197016987 ps
CPU time 1.01 seconds
Started Aug 07 06:02:03 PM PDT 24
Finished Aug 07 06:02:05 PM PDT 24
Peak memory 207004 kb
Host smart-ccbbc469-f0fa-43e4-bef2-66778bf2b1e6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2255780513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.2255780513
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3124146399
Short name T2894
Test name
Test status
Simulation time 145900052 ps
CPU time 0.81 seconds
Started Aug 07 06:02:07 PM PDT 24
Finished Aug 07 06:02:08 PM PDT 24
Peak memory 206908 kb
Host smart-a1add552-9e7a-47ae-affb-d3d85605e45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31241
46399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3124146399
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1390613589
Short name T1961
Test name
Test status
Simulation time 63785742 ps
CPU time 0.72 seconds
Started Aug 07 06:02:07 PM PDT 24
Finished Aug 07 06:02:08 PM PDT 24
Peak memory 206912 kb
Host smart-6a678445-e8cd-474a-acca-e04c6ab7fab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13906
13589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1390613589
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3914077678
Short name T267
Test name
Test status
Simulation time 17424340055 ps
CPU time 44.26 seconds
Started Aug 07 06:02:09 PM PDT 24
Finished Aug 07 06:02:54 PM PDT 24
Peak memory 215520 kb
Host smart-3521b869-b825-4be3-9c43-fdb59f7be84e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39140
77678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3914077678
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2383899502
Short name T1142
Test name
Test status
Simulation time 180175513 ps
CPU time 0.88 seconds
Started Aug 07 06:02:07 PM PDT 24
Finished Aug 07 06:02:08 PM PDT 24
Peak memory 207004 kb
Host smart-ea495737-21ca-4aee-88fc-665aee0fa8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23838
99502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2383899502
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3428089399
Short name T1868
Test name
Test status
Simulation time 163227859 ps
CPU time 0.9 seconds
Started Aug 07 06:02:06 PM PDT 24
Finished Aug 07 06:02:07 PM PDT 24
Peak memory 206964 kb
Host smart-9b20dd67-e969-4822-bbb3-0bc422cc75be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34280
89399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3428089399
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1264454420
Short name T2214
Test name
Test status
Simulation time 296937063 ps
CPU time 1.11 seconds
Started Aug 07 06:02:09 PM PDT 24
Finished Aug 07 06:02:10 PM PDT 24
Peak memory 206992 kb
Host smart-d62b51d6-55ab-4809-b2b5-244542c35adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12644
54420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1264454420
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1993900006
Short name T2237
Test name
Test status
Simulation time 225725726 ps
CPU time 0.94 seconds
Started Aug 07 06:02:06 PM PDT 24
Finished Aug 07 06:02:07 PM PDT 24
Peak memory 206976 kb
Host smart-b08d72a5-65dd-4559-8566-c5ca6d637d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19939
00006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1993900006
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_resume_link_active.719859497
Short name T1022
Test name
Test status
Simulation time 20249328591 ps
CPU time 22.75 seconds
Started Aug 07 06:02:08 PM PDT 24
Finished Aug 07 06:02:31 PM PDT 24
Peak memory 207080 kb
Host smart-60a48f55-62c0-426b-b4f9-f200fb57e52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71985
9497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.719859497
Directory /workspace/16.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1450597845
Short name T2158
Test name
Test status
Simulation time 196750304 ps
CPU time 0.86 seconds
Started Aug 07 06:02:05 PM PDT 24
Finished Aug 07 06:02:06 PM PDT 24
Peak memory 206972 kb
Host smart-270f301c-a039-4cda-bf5b-0833710cb583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14505
97845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1450597845
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_rx_full.948280401
Short name T2901
Test name
Test status
Simulation time 265203804 ps
CPU time 1.11 seconds
Started Aug 07 06:02:09 PM PDT 24
Finished Aug 07 06:02:10 PM PDT 24
Peak memory 206980 kb
Host smart-4174a053-5628-4b07-9ae3-8552abcfe5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94828
0401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.948280401
Directory /workspace/16.usbdev_rx_full/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1367081591
Short name T1025
Test name
Test status
Simulation time 157389116 ps
CPU time 0.84 seconds
Started Aug 07 06:02:08 PM PDT 24
Finished Aug 07 06:02:09 PM PDT 24
Peak memory 206984 kb
Host smart-bc7c7017-3238-4753-9f5b-68cd6a795838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13670
81591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1367081591
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.159928849
Short name T539
Test name
Test status
Simulation time 170193318 ps
CPU time 0.89 seconds
Started Aug 07 06:02:07 PM PDT 24
Finished Aug 07 06:02:08 PM PDT 24
Peak memory 206948 kb
Host smart-a6fb0e10-7d8f-4ab7-a401-747759c0b2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15992
8849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.159928849
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1343220728
Short name T1509
Test name
Test status
Simulation time 208423023 ps
CPU time 0.98 seconds
Started Aug 07 06:02:05 PM PDT 24
Finished Aug 07 06:02:06 PM PDT 24
Peak memory 206960 kb
Host smart-b1e4c73e-f723-42a4-97d6-d678b962adc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13432
20728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1343220728
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.3343765385
Short name T2511
Test name
Test status
Simulation time 2832997636 ps
CPU time 80.89 seconds
Started Aug 07 06:02:07 PM PDT 24
Finished Aug 07 06:03:28 PM PDT 24
Peak memory 223716 kb
Host smart-544b36a0-b1b6-43e6-ae89-803771939cf7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3343765385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.3343765385
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.3212964525
Short name T752
Test name
Test status
Simulation time 177415732 ps
CPU time 0.94 seconds
Started Aug 07 06:02:08 PM PDT 24
Finished Aug 07 06:02:09 PM PDT 24
Peak memory 206996 kb
Host smart-0b1acf0e-43c4-4385-a027-1f809b27dd86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32129
64525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.3212964525
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.328240156
Short name T1662
Test name
Test status
Simulation time 238885160 ps
CPU time 1.03 seconds
Started Aug 07 06:02:07 PM PDT 24
Finished Aug 07 06:02:08 PM PDT 24
Peak memory 206984 kb
Host smart-7258a3a2-bb9c-4e1a-b931-9d67cfb5ef61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32824
0156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.328240156
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.162520662
Short name T2398
Test name
Test status
Simulation time 277406017 ps
CPU time 1.18 seconds
Started Aug 07 06:02:06 PM PDT 24
Finished Aug 07 06:02:08 PM PDT 24
Peak memory 206872 kb
Host smart-d19b6402-88a4-4bb9-b412-ab8376c40b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252
0662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.162520662
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.4264601251
Short name T2840
Test name
Test status
Simulation time 1948188208 ps
CPU time 15.24 seconds
Started Aug 07 06:02:07 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 207200 kb
Host smart-52627793-5183-44a3-b8e2-838173c3cae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42646
01251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.4264601251
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.946821417
Short name T1618
Test name
Test status
Simulation time 170165847 ps
CPU time 0.94 seconds
Started Aug 07 06:02:02 PM PDT 24
Finished Aug 07 06:02:03 PM PDT 24
Peak memory 206944 kb
Host smart-2d2f982e-3647-4104-b78d-42640b0e5223
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946821417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_host
_handshake.946821417
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/160.usbdev_endpoint_types.2225126404
Short name T454
Test name
Test status
Simulation time 213311870 ps
CPU time 1.03 seconds
Started Aug 07 06:13:17 PM PDT 24
Finished Aug 07 06:13:18 PM PDT 24
Peak memory 206960 kb
Host smart-3fada9f9-0585-4d27-b27c-528d8bc027f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2225126404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.2225126404
Directory /workspace/160.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/161.usbdev_endpoint_types.2473896070
Short name T1375
Test name
Test status
Simulation time 165292194 ps
CPU time 0.98 seconds
Started Aug 07 06:13:14 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206980 kb
Host smart-a2864e56-fe66-458e-a538-b08b3a6f12de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2473896070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.2473896070
Directory /workspace/161.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/162.usbdev_endpoint_types.3408345651
Short name T3034
Test name
Test status
Simulation time 474779583 ps
CPU time 1.26 seconds
Started Aug 07 06:13:17 PM PDT 24
Finished Aug 07 06:13:18 PM PDT 24
Peak memory 206960 kb
Host smart-97a431e9-acc6-47f0-9f88-7b5909df4636
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3408345651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.3408345651
Directory /workspace/162.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/163.usbdev_endpoint_types.475075500
Short name T393
Test name
Test status
Simulation time 409457540 ps
CPU time 1.28 seconds
Started Aug 07 06:13:13 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206976 kb
Host smart-4f5baeb7-a540-4fef-8621-b96ab1d9b8eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=475075500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.475075500
Directory /workspace/163.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/165.usbdev_endpoint_types.745704048
Short name T2572
Test name
Test status
Simulation time 380787873 ps
CPU time 1.23 seconds
Started Aug 07 06:13:10 PM PDT 24
Finished Aug 07 06:13:11 PM PDT 24
Peak memory 206964 kb
Host smart-acd3a548-afad-4c51-b9cc-8cff4ceda6ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=745704048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.745704048
Directory /workspace/165.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/166.usbdev_endpoint_types.4077730823
Short name T1953
Test name
Test status
Simulation time 410949630 ps
CPU time 1.19 seconds
Started Aug 07 06:13:09 PM PDT 24
Finished Aug 07 06:13:11 PM PDT 24
Peak memory 206968 kb
Host smart-8d554269-c4d8-4293-af9f-5a22e300fdba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4077730823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.4077730823
Directory /workspace/166.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/169.usbdev_endpoint_types.983327637
Short name T1724
Test name
Test status
Simulation time 182547095 ps
CPU time 0.92 seconds
Started Aug 07 06:13:14 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206968 kb
Host smart-c18cd243-c2e4-416f-9663-3fc19b8e86c6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=983327637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.983327637
Directory /workspace/169.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.1921005420
Short name T1898
Test name
Test status
Simulation time 50893503 ps
CPU time 0.65 seconds
Started Aug 07 06:02:22 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 207072 kb
Host smart-de86604b-d4c7-4b12-83f7-0977c6c3013a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1921005420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.1921005420
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2595277580
Short name T1101
Test name
Test status
Simulation time 3925243138 ps
CPU time 6.67 seconds
Started Aug 07 06:02:08 PM PDT 24
Finished Aug 07 06:02:15 PM PDT 24
Peak memory 215480 kb
Host smart-174498e6-b80c-44d0-82fa-8fc50d050571
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595277580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.2595277580
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3696038231
Short name T2640
Test name
Test status
Simulation time 14837602585 ps
CPU time 18.09 seconds
Started Aug 07 06:02:10 PM PDT 24
Finished Aug 07 06:02:28 PM PDT 24
Peak memory 215332 kb
Host smart-7a25720c-1777-49d9-86f5-4bf977f93f21
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696038231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3696038231
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.526381282
Short name T2382
Test name
Test status
Simulation time 30831667740 ps
CPU time 33.27 seconds
Started Aug 07 06:02:08 PM PDT 24
Finished Aug 07 06:02:42 PM PDT 24
Peak memory 207256 kb
Host smart-c984c99f-430d-45ad-8814-fae504431ae9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526381282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_ao
n_wake_resume.526381282
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3795302703
Short name T1865
Test name
Test status
Simulation time 223987330 ps
CPU time 0.91 seconds
Started Aug 07 06:02:09 PM PDT 24
Finished Aug 07 06:02:10 PM PDT 24
Peak memory 207016 kb
Host smart-cbc6df05-b6bc-4085-8ea0-58c9e1a4e507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37953
02703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3795302703
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.958731794
Short name T1531
Test name
Test status
Simulation time 168079003 ps
CPU time 0.85 seconds
Started Aug 07 06:02:07 PM PDT 24
Finished Aug 07 06:02:07 PM PDT 24
Peak memory 206948 kb
Host smart-adc7ffad-d5e2-4271-b0d9-70def21b5b90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95873
1794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.958731794
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1390441528
Short name T584
Test name
Test status
Simulation time 235992557 ps
CPU time 1.06 seconds
Started Aug 07 06:02:11 PM PDT 24
Finished Aug 07 06:02:12 PM PDT 24
Peak memory 206444 kb
Host smart-dae5de48-a408-4da2-b069-c44cfa0d770e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13904
41528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1390441528
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1542071223
Short name T3125
Test name
Test status
Simulation time 816310005 ps
CPU time 2.29 seconds
Started Aug 07 06:02:08 PM PDT 24
Finished Aug 07 06:02:10 PM PDT 24
Peak memory 207172 kb
Host smart-e2ad5f59-dc62-4358-85d5-811ad4b48732
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1542071223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1542071223
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.3434376126
Short name T1475
Test name
Test status
Simulation time 1109561454 ps
CPU time 9.3 seconds
Started Aug 07 06:02:09 PM PDT 24
Finished Aug 07 06:02:19 PM PDT 24
Peak memory 207168 kb
Host smart-91fb96d8-f0ee-4f8b-9e13-eeaaea00c253
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434376126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.3434376126
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.3223478212
Short name T2815
Test name
Test status
Simulation time 938613163 ps
CPU time 2.12 seconds
Started Aug 07 06:02:11 PM PDT 24
Finished Aug 07 06:02:13 PM PDT 24
Peak memory 206368 kb
Host smart-04d99826-5241-4f04-880a-6f85397f7f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32234
78212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.3223478212
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2931175622
Short name T2560
Test name
Test status
Simulation time 178798288 ps
CPU time 0.84 seconds
Started Aug 07 06:02:08 PM PDT 24
Finished Aug 07 06:02:09 PM PDT 24
Peak memory 206948 kb
Host smart-1be066e4-cfab-48c8-ac62-2926e2d4071f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29311
75622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2931175622
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2537851699
Short name T1017
Test name
Test status
Simulation time 68454463 ps
CPU time 0.72 seconds
Started Aug 07 06:02:08 PM PDT 24
Finished Aug 07 06:02:09 PM PDT 24
Peak memory 206948 kb
Host smart-e6d5beca-615e-4fc1-a96e-1df2ac8503bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25378
51699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2537851699
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1614137752
Short name T2204
Test name
Test status
Simulation time 903700193 ps
CPU time 2.61 seconds
Started Aug 07 06:02:08 PM PDT 24
Finished Aug 07 06:02:11 PM PDT 24
Peak memory 207152 kb
Host smart-92f0471e-67b3-4956-ab4b-92fa55a3e93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16141
37752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1614137752
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_types.4249737285
Short name T2701
Test name
Test status
Simulation time 760267164 ps
CPU time 1.75 seconds
Started Aug 07 06:02:11 PM PDT 24
Finished Aug 07 06:02:13 PM PDT 24
Peak memory 206332 kb
Host smart-68f8dae6-a4b9-49bb-8531-825946e478c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4249737285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.4249737285
Directory /workspace/17.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.675287151
Short name T2229
Test name
Test status
Simulation time 178887753 ps
CPU time 1.72 seconds
Started Aug 07 06:02:09 PM PDT 24
Finished Aug 07 06:02:11 PM PDT 24
Peak memory 207160 kb
Host smart-43df5391-81a9-4567-a896-27e09493d24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67528
7151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.675287151
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.230540191
Short name T2208
Test name
Test status
Simulation time 181070356 ps
CPU time 1.03 seconds
Started Aug 07 06:02:12 PM PDT 24
Finished Aug 07 06:02:13 PM PDT 24
Peak memory 207144 kb
Host smart-e2d1444c-0916-45ea-a118-589cdf320a31
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=230540191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.230540191
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.908409441
Short name T2482
Test name
Test status
Simulation time 135867812 ps
CPU time 0.83 seconds
Started Aug 07 06:02:12 PM PDT 24
Finished Aug 07 06:02:13 PM PDT 24
Peak memory 206868 kb
Host smart-9adf22ae-fb10-4d19-97ee-04116c692e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90840
9441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.908409441
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.685892981
Short name T2249
Test name
Test status
Simulation time 279622608 ps
CPU time 1.14 seconds
Started Aug 07 06:02:17 PM PDT 24
Finished Aug 07 06:02:19 PM PDT 24
Peak memory 206980 kb
Host smart-5928c57a-a2fb-408d-9e1e-ca6a00540edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68589
2981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.685892981
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.3014815101
Short name T2790
Test name
Test status
Simulation time 3658583895 ps
CPU time 106.41 seconds
Started Aug 07 06:02:12 PM PDT 24
Finished Aug 07 06:03:59 PM PDT 24
Peak memory 217148 kb
Host smart-0fd47732-a12a-4f07-bfba-f4ab66f1516d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3014815101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.3014815101
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.1725537870
Short name T2558
Test name
Test status
Simulation time 10852386761 ps
CPU time 133.56 seconds
Started Aug 07 06:02:13 PM PDT 24
Finished Aug 07 06:04:27 PM PDT 24
Peak memory 207208 kb
Host smart-a60b03b8-d1c0-4a80-a324-ef042ff963e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1725537870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.1725537870
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2930248366
Short name T698
Test name
Test status
Simulation time 157482027 ps
CPU time 0.88 seconds
Started Aug 07 06:02:11 PM PDT 24
Finished Aug 07 06:02:12 PM PDT 24
Peak memory 206988 kb
Host smart-6d0b7442-a79f-414e-96e4-29c545a8ad62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29302
48366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2930248366
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.731595878
Short name T1001
Test name
Test status
Simulation time 30692191895 ps
CPU time 46.36 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 207268 kb
Host smart-268d78e1-e8eb-481a-9856-d109001a15bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73159
5878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.731595878
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2686305057
Short name T1626
Test name
Test status
Simulation time 11250390317 ps
CPU time 15.07 seconds
Started Aug 07 06:02:15 PM PDT 24
Finished Aug 07 06:02:30 PM PDT 24
Peak memory 207276 kb
Host smart-f0fdc9c8-4318-4df2-b9dd-66cb68efba00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26863
05057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2686305057
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.229257972
Short name T585
Test name
Test status
Simulation time 3713706430 ps
CPU time 34.33 seconds
Started Aug 07 06:02:15 PM PDT 24
Finished Aug 07 06:02:49 PM PDT 24
Peak memory 217948 kb
Host smart-bd2bb415-b6a9-4fa1-8b9c-9193011a9684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22925
7972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.229257972
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1792869005
Short name T1939
Test name
Test status
Simulation time 2127270259 ps
CPU time 59.69 seconds
Started Aug 07 06:02:16 PM PDT 24
Finished Aug 07 06:03:16 PM PDT 24
Peak memory 215372 kb
Host smart-771ba046-1924-4295-a9cf-df02d3564de7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1792869005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1792869005
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.1666613949
Short name T1280
Test name
Test status
Simulation time 247060470 ps
CPU time 0.98 seconds
Started Aug 07 06:02:15 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 207000 kb
Host smart-6292979d-e42d-48e2-b854-01ed66d951c1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1666613949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1666613949
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2027667657
Short name T1442
Test name
Test status
Simulation time 182245074 ps
CPU time 0.91 seconds
Started Aug 07 06:02:11 PM PDT 24
Finished Aug 07 06:02:12 PM PDT 24
Peak memory 206948 kb
Host smart-980288a8-8787-498e-9a33-3c080d233cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20276
67657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2027667657
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.275142213
Short name T1878
Test name
Test status
Simulation time 2690766113 ps
CPU time 76.65 seconds
Started Aug 07 06:02:14 PM PDT 24
Finished Aug 07 06:03:31 PM PDT 24
Peak memory 217044 kb
Host smart-459085b8-04b1-427d-ba60-2f1691526984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27514
2213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.275142213
Directory /workspace/17.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3324080024
Short name T886
Test name
Test status
Simulation time 2883903138 ps
CPU time 20.7 seconds
Started Aug 07 06:02:14 PM PDT 24
Finished Aug 07 06:02:35 PM PDT 24
Peak memory 217212 kb
Host smart-bc60df07-e4b6-47ab-bbce-d94fad49b422
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3324080024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3324080024
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.785924429
Short name T2563
Test name
Test status
Simulation time 188419574 ps
CPU time 0.89 seconds
Started Aug 07 06:02:15 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 206956 kb
Host smart-9d6f2cf3-05c2-4db3-ba12-22102855ec65
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=785924429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.785924429
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.670738983
Short name T1037
Test name
Test status
Simulation time 150245265 ps
CPU time 0.85 seconds
Started Aug 07 06:02:15 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 207004 kb
Host smart-75bf3410-3cdc-4053-85c8-a72fc247738f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67073
8983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.670738983
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.686856710
Short name T140
Test name
Test status
Simulation time 265369841 ps
CPU time 1.04 seconds
Started Aug 07 06:02:15 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 207000 kb
Host smart-4e3c9d74-c334-4dd8-ab1d-0ab6bfa508d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68685
6710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.686856710
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1370795686
Short name T1080
Test name
Test status
Simulation time 179055278 ps
CPU time 0.9 seconds
Started Aug 07 06:02:13 PM PDT 24
Finished Aug 07 06:02:14 PM PDT 24
Peak memory 206856 kb
Host smart-a7aa2b30-5b7c-4fb5-a120-4c0fffe0092d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13707
95686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1370795686
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.671151203
Short name T638
Test name
Test status
Simulation time 181248072 ps
CPU time 0.93 seconds
Started Aug 07 06:02:13 PM PDT 24
Finished Aug 07 06:02:15 PM PDT 24
Peak memory 207016 kb
Host smart-30a0b75b-807e-4efa-817a-a4584073548c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67115
1203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.671151203
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1487992506
Short name T2044
Test name
Test status
Simulation time 210101236 ps
CPU time 1.01 seconds
Started Aug 07 06:02:14 PM PDT 24
Finished Aug 07 06:02:15 PM PDT 24
Peak memory 206900 kb
Host smart-2877c1af-771a-4f18-9992-1ce0874238de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14879
92506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1487992506
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2469881236
Short name T191
Test name
Test status
Simulation time 157181834 ps
CPU time 0.84 seconds
Started Aug 07 06:02:16 PM PDT 24
Finished Aug 07 06:02:17 PM PDT 24
Peak memory 206976 kb
Host smart-5c144406-c3af-4542-9c09-b6407bfc6719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24698
81236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2469881236
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.892670884
Short name T107
Test name
Test status
Simulation time 264055422 ps
CPU time 1.07 seconds
Started Aug 07 06:02:15 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 206964 kb
Host smart-2e457380-1614-42ae-b1bb-710f65fcb22c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=892670884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.892670884
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.4167092976
Short name T1691
Test name
Test status
Simulation time 154924883 ps
CPU time 0.83 seconds
Started Aug 07 06:02:13 PM PDT 24
Finished Aug 07 06:02:14 PM PDT 24
Peak memory 206928 kb
Host smart-dd0f7553-df95-4f2b-b0e2-1f0f0a3c3d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41670
92976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.4167092976
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2335757085
Short name T2606
Test name
Test status
Simulation time 64784350 ps
CPU time 0.72 seconds
Started Aug 07 06:02:15 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 206988 kb
Host smart-187d3e29-1ffc-4176-b880-8e2e7e80d7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23357
57085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2335757085
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1140768095
Short name T264
Test name
Test status
Simulation time 14730849129 ps
CPU time 35.83 seconds
Started Aug 07 06:02:14 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 215360 kb
Host smart-922512b9-0041-4ec1-ae0a-b1071b8b2bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11407
68095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1140768095
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.449883339
Short name T1846
Test name
Test status
Simulation time 224591313 ps
CPU time 0.95 seconds
Started Aug 07 06:02:15 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 206908 kb
Host smart-b00d4acd-3fb0-4102-9854-35a2036209ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44988
3339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.449883339
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2027592729
Short name T970
Test name
Test status
Simulation time 195086715 ps
CPU time 1.01 seconds
Started Aug 07 06:02:15 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 206956 kb
Host smart-4083bdd4-be9d-4686-a226-2da8fb5ded9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20275
92729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2027592729
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.3428114547
Short name T2108
Test name
Test status
Simulation time 200374386 ps
CPU time 0.96 seconds
Started Aug 07 06:02:13 PM PDT 24
Finished Aug 07 06:02:14 PM PDT 24
Peak memory 206964 kb
Host smart-3de51d9a-0a39-416a-bc11-fa8fb7023a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34281
14547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.3428114547
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1054988999
Short name T568
Test name
Test status
Simulation time 204870564 ps
CPU time 0.96 seconds
Started Aug 07 06:02:13 PM PDT 24
Finished Aug 07 06:02:14 PM PDT 24
Peak memory 207016 kb
Host smart-f844d140-964d-47cb-b0d7-19e34ec79e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10549
88999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1054988999
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_resume_link_active.624445968
Short name T1062
Test name
Test status
Simulation time 20158217224 ps
CPU time 28.42 seconds
Started Aug 07 06:02:13 PM PDT 24
Finished Aug 07 06:02:42 PM PDT 24
Peak memory 206992 kb
Host smart-2c744c01-08ce-4f0e-91ae-f8441ba7295f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62444
5968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.624445968
Directory /workspace/17.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.4008013981
Short name T1707
Test name
Test status
Simulation time 163628411 ps
CPU time 0.86 seconds
Started Aug 07 06:02:14 PM PDT 24
Finished Aug 07 06:02:15 PM PDT 24
Peak memory 206940 kb
Host smart-f5cbd89c-fa8e-4cb8-8cdd-f8489e9ade55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40080
13981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.4008013981
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_rx_full.1314659300
Short name T842
Test name
Test status
Simulation time 384249719 ps
CPU time 1.27 seconds
Started Aug 07 06:02:12 PM PDT 24
Finished Aug 07 06:02:13 PM PDT 24
Peak memory 206916 kb
Host smart-7715b461-202d-43e2-895b-ff64e445188a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13146
59300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.1314659300
Directory /workspace/17.usbdev_rx_full/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.65569554
Short name T1642
Test name
Test status
Simulation time 154934900 ps
CPU time 0.85 seconds
Started Aug 07 06:02:12 PM PDT 24
Finished Aug 07 06:02:13 PM PDT 24
Peak memory 206984 kb
Host smart-29086b83-6338-4bf4-8a97-57d917881a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65569
554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.65569554
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3844190951
Short name T1654
Test name
Test status
Simulation time 197233323 ps
CPU time 1 seconds
Started Aug 07 06:02:14 PM PDT 24
Finished Aug 07 06:02:15 PM PDT 24
Peak memory 206992 kb
Host smart-8bff70cf-b6ce-4128-959d-38f9385e670c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38441
90951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3844190951
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3623653450
Short name T1891
Test name
Test status
Simulation time 222622370 ps
CPU time 1.02 seconds
Started Aug 07 06:02:12 PM PDT 24
Finished Aug 07 06:02:13 PM PDT 24
Peak memory 206968 kb
Host smart-4b9d18f3-5d56-485b-a65d-4700ce30008f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36236
53450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3623653450
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.4105168221
Short name T2518
Test name
Test status
Simulation time 2652238425 ps
CPU time 29.08 seconds
Started Aug 07 06:02:13 PM PDT 24
Finished Aug 07 06:02:42 PM PDT 24
Peak memory 217532 kb
Host smart-9ce1c1c6-4f69-4bbc-9be6-6c22ecaa6f0d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4105168221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.4105168221
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3636872603
Short name T666
Test name
Test status
Simulation time 171743156 ps
CPU time 0.88 seconds
Started Aug 07 06:02:13 PM PDT 24
Finished Aug 07 06:02:14 PM PDT 24
Peak memory 207016 kb
Host smart-01a621eb-38d7-48c4-8a3f-347e410d8e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36368
72603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3636872603
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3412036917
Short name T1060
Test name
Test status
Simulation time 156447462 ps
CPU time 0.82 seconds
Started Aug 07 06:02:15 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 207044 kb
Host smart-f2e944ae-3911-4628-b350-a1ce470b93ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34120
36917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3412036917
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.2514920187
Short name T2928
Test name
Test status
Simulation time 375542750 ps
CPU time 1.26 seconds
Started Aug 07 06:02:17 PM PDT 24
Finished Aug 07 06:02:19 PM PDT 24
Peak memory 207004 kb
Host smart-c44839d8-aff5-46c4-a66a-4b14aaa1d51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25149
20187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.2514920187
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.1029632234
Short name T2991
Test name
Test status
Simulation time 2146383290 ps
CPU time 17.07 seconds
Started Aug 07 06:02:14 PM PDT 24
Finished Aug 07 06:02:32 PM PDT 24
Peak memory 215808 kb
Host smart-b2c26d40-3c2b-47f8-b3e3-68134d030508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10296
32234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.1029632234
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.333919933
Short name T621
Test name
Test status
Simulation time 732397298 ps
CPU time 15.08 seconds
Started Aug 07 06:02:07 PM PDT 24
Finished Aug 07 06:02:22 PM PDT 24
Peak memory 207156 kb
Host smart-3d35b296-6f1a-42fc-a4d8-b096a8477476
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333919933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_host
_handshake.333919933
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/170.usbdev_endpoint_types.2243333445
Short name T380
Test name
Test status
Simulation time 550551452 ps
CPU time 1.39 seconds
Started Aug 07 06:13:09 PM PDT 24
Finished Aug 07 06:13:10 PM PDT 24
Peak memory 206964 kb
Host smart-fc7c41f5-dad3-47a9-8f4d-48224d232a02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2243333445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.2243333445
Directory /workspace/170.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/171.usbdev_endpoint_types.3139123126
Short name T423
Test name
Test status
Simulation time 255062982 ps
CPU time 1.02 seconds
Started Aug 07 06:13:11 PM PDT 24
Finished Aug 07 06:13:13 PM PDT 24
Peak memory 207012 kb
Host smart-dd4a468f-b0ce-40d4-8200-ba438e2692df
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3139123126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.3139123126
Directory /workspace/171.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/172.usbdev_endpoint_types.3690613873
Short name T428
Test name
Test status
Simulation time 512612018 ps
CPU time 1.4 seconds
Started Aug 07 06:13:11 PM PDT 24
Finished Aug 07 06:13:12 PM PDT 24
Peak memory 206940 kb
Host smart-f75fd5c7-4f29-470f-b29c-1aff4af529cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3690613873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.3690613873
Directory /workspace/172.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/174.usbdev_endpoint_types.3066767451
Short name T436
Test name
Test status
Simulation time 368918418 ps
CPU time 1.24 seconds
Started Aug 07 06:13:11 PM PDT 24
Finished Aug 07 06:13:12 PM PDT 24
Peak memory 206940 kb
Host smart-00da4967-f8e1-447e-b409-30246dcab04d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3066767451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.3066767451
Directory /workspace/174.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/175.usbdev_endpoint_types.3485605845
Short name T402
Test name
Test status
Simulation time 469084062 ps
CPU time 1.41 seconds
Started Aug 07 06:13:08 PM PDT 24
Finished Aug 07 06:13:10 PM PDT 24
Peak memory 206888 kb
Host smart-97e4bfc8-e0eb-4c9a-82de-2e370fe6cb55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3485605845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.3485605845
Directory /workspace/175.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/176.usbdev_endpoint_types.3316993543
Short name T356
Test name
Test status
Simulation time 278553091 ps
CPU time 1.09 seconds
Started Aug 07 06:13:13 PM PDT 24
Finished Aug 07 06:13:14 PM PDT 24
Peak memory 206932 kb
Host smart-01998ffb-f61b-4abc-ae03-6e3a69673112
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3316993543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.3316993543
Directory /workspace/176.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/177.usbdev_endpoint_types.185073661
Short name T2090
Test name
Test status
Simulation time 732563793 ps
CPU time 1.79 seconds
Started Aug 07 06:13:11 PM PDT 24
Finished Aug 07 06:13:13 PM PDT 24
Peak memory 206884 kb
Host smart-03ee416e-8ad6-4e11-b2e2-796092610f2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=185073661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.185073661
Directory /workspace/177.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/178.usbdev_endpoint_types.1566502695
Short name T420
Test name
Test status
Simulation time 783469554 ps
CPU time 1.85 seconds
Started Aug 07 06:13:13 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206976 kb
Host smart-1b20982f-13f9-4b83-98ec-770575d2db01
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1566502695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.1566502695
Directory /workspace/178.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/179.usbdev_endpoint_types.3755958193
Short name T1944
Test name
Test status
Simulation time 217988109 ps
CPU time 0.92 seconds
Started Aug 07 06:13:10 PM PDT 24
Finished Aug 07 06:13:11 PM PDT 24
Peak memory 207000 kb
Host smart-63c8763e-d1a1-405f-b051-0e00f2fb09cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3755958193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.3755958193
Directory /workspace/179.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.1135756917
Short name T1189
Test name
Test status
Simulation time 40124937 ps
CPU time 0.66 seconds
Started Aug 07 06:02:25 PM PDT 24
Finished Aug 07 06:02:26 PM PDT 24
Peak memory 207068 kb
Host smart-a3a20a16-9b8b-4ebb-baaa-dde3678d312f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1135756917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.1135756917
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.9001192
Short name T2665
Test name
Test status
Simulation time 10468728713 ps
CPU time 12.72 seconds
Started Aug 07 06:02:20 PM PDT 24
Finished Aug 07 06:02:33 PM PDT 24
Peak memory 207352 kb
Host smart-12ffb2c0-55c9-475a-ae4f-3768fdaf6377
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9001192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us
bdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_
wake_disconnect.9001192
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2180047292
Short name T1506
Test name
Test status
Simulation time 20767987361 ps
CPU time 23.32 seconds
Started Aug 07 06:02:18 PM PDT 24
Finished Aug 07 06:02:42 PM PDT 24
Peak memory 207244 kb
Host smart-e2c0a7cb-044c-4e6a-bf23-e9b586da076b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180047292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2180047292
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.2152811446
Short name T2533
Test name
Test status
Simulation time 29799626746 ps
CPU time 32.94 seconds
Started Aug 07 06:02:23 PM PDT 24
Finished Aug 07 06:02:56 PM PDT 24
Peak memory 207284 kb
Host smart-9322be2a-d5b7-4bae-9f37-7a80e880328b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152811446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.2152811446
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2087476022
Short name T1924
Test name
Test status
Simulation time 153098083 ps
CPU time 0.85 seconds
Started Aug 07 06:02:23 PM PDT 24
Finished Aug 07 06:02:24 PM PDT 24
Peak memory 206444 kb
Host smart-738eb9cb-dbef-4bae-9e5d-3478f838fa94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20874
76022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2087476022
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.481859898
Short name T1170
Test name
Test status
Simulation time 140839815 ps
CPU time 0.81 seconds
Started Aug 07 06:02:20 PM PDT 24
Finished Aug 07 06:02:21 PM PDT 24
Peak memory 207028 kb
Host smart-92f150a6-455e-48a2-a3b9-c0718716f4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48185
9898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.481859898
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.120205440
Short name T1916
Test name
Test status
Simulation time 505240207 ps
CPU time 1.57 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:02:21 PM PDT 24
Peak memory 207016 kb
Host smart-faa648de-38f6-4b8e-8c95-bdcaaccb0fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12020
5440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.120205440
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3592814920
Short name T1900
Test name
Test status
Simulation time 1086075655 ps
CPU time 2.79 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:02:22 PM PDT 24
Peak memory 207244 kb
Host smart-37e76515-db55-4504-9631-0d1305cf24a0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3592814920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3592814920
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.1052158910
Short name T182
Test name
Test status
Simulation time 54479058061 ps
CPU time 79.23 seconds
Started Aug 07 06:02:18 PM PDT 24
Finished Aug 07 06:03:38 PM PDT 24
Peak memory 207272 kb
Host smart-e8739f4c-c526-4da4-b661-e00294685949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10521
58910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.1052158910
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.2925529963
Short name T91
Test name
Test status
Simulation time 4980430820 ps
CPU time 33.35 seconds
Started Aug 07 06:02:21 PM PDT 24
Finished Aug 07 06:02:54 PM PDT 24
Peak memory 207332 kb
Host smart-f34a0953-f3ab-41af-8df4-92c713e54399
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925529963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.2925529963
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.703776751
Short name T357
Test name
Test status
Simulation time 935428172 ps
CPU time 2.08 seconds
Started Aug 07 06:02:28 PM PDT 24
Finished Aug 07 06:02:30 PM PDT 24
Peak memory 206980 kb
Host smart-a07e8101-b2f2-4145-a5ec-5ae2f83947e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70377
6751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.703776751
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2311854386
Short name T657
Test name
Test status
Simulation time 156367093 ps
CPU time 0.83 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:02:20 PM PDT 24
Peak memory 206968 kb
Host smart-31212473-4aaf-4491-b911-b0068d2f3d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23118
54386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2311854386
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2564446514
Short name T1140
Test name
Test status
Simulation time 115695943 ps
CPU time 0.9 seconds
Started Aug 07 06:02:24 PM PDT 24
Finished Aug 07 06:02:25 PM PDT 24
Peak memory 206900 kb
Host smart-027aa43e-85ff-492a-8c67-23f1d5dfbd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25644
46514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2564446514
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2383890317
Short name T2902
Test name
Test status
Simulation time 802332495 ps
CPU time 2.18 seconds
Started Aug 07 06:02:20 PM PDT 24
Finished Aug 07 06:02:22 PM PDT 24
Peak memory 207152 kb
Host smart-42c236a2-1268-4e6e-abd2-8c445436eb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23838
90317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2383890317
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1131316907
Short name T1182
Test name
Test status
Simulation time 168674992 ps
CPU time 1.95 seconds
Started Aug 07 06:02:20 PM PDT 24
Finished Aug 07 06:02:22 PM PDT 24
Peak memory 207236 kb
Host smart-4d920dcc-7cbb-4444-b117-246170d3eb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11313
16907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1131316907
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.1220042673
Short name T628
Test name
Test status
Simulation time 220567133 ps
CPU time 1.18 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:02:20 PM PDT 24
Peak memory 215292 kb
Host smart-36fcc3d4-2b8b-4f0c-a4f2-3aa79421b9e1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1220042673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1220042673
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3398262678
Short name T2588
Test name
Test status
Simulation time 145627223 ps
CPU time 0.87 seconds
Started Aug 07 06:02:20 PM PDT 24
Finished Aug 07 06:02:21 PM PDT 24
Peak memory 206956 kb
Host smart-4b7f78ff-4f3f-4a9c-af0b-c698e04cfb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33982
62678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3398262678
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.74245569
Short name T2075
Test name
Test status
Simulation time 188522361 ps
CPU time 0.94 seconds
Started Aug 07 06:02:18 PM PDT 24
Finished Aug 07 06:02:19 PM PDT 24
Peak memory 206904 kb
Host smart-5dbd3556-b74a-4316-af83-09114371d3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74245
569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.74245569
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.1263007750
Short name T1149
Test name
Test status
Simulation time 5283292346 ps
CPU time 52.62 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:03:11 PM PDT 24
Peak memory 217808 kb
Host smart-46cf4c52-1051-4397-8533-ea8f020928a5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1263007750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.1263007750
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.858636758
Short name T1960
Test name
Test status
Simulation time 12350448456 ps
CPU time 85.79 seconds
Started Aug 07 06:02:20 PM PDT 24
Finished Aug 07 06:03:46 PM PDT 24
Peak memory 207164 kb
Host smart-b27c0b95-d46a-4b04-b462-a10201ff6578
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=858636758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.858636758
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2669808019
Short name T95
Test name
Test status
Simulation time 189622907 ps
CPU time 0.94 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:02:20 PM PDT 24
Peak memory 207012 kb
Host smart-499da07f-c091-44da-b50f-d1b2272d4505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26698
08019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2669808019
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.2484157088
Short name T2512
Test name
Test status
Simulation time 14391652317 ps
CPU time 18.95 seconds
Started Aug 07 06:02:28 PM PDT 24
Finished Aug 07 06:02:47 PM PDT 24
Peak memory 207296 kb
Host smart-ed20bc41-6f30-42cc-8882-a1558b719c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24841
57088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.2484157088
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.798373637
Short name T1289
Test name
Test status
Simulation time 10035163992 ps
CPU time 13.7 seconds
Started Aug 07 06:02:22 PM PDT 24
Finished Aug 07 06:02:35 PM PDT 24
Peak memory 207328 kb
Host smart-448491c1-8d60-473b-ad99-a17464880c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79837
3637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.798373637
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.29539309
Short name T1217
Test name
Test status
Simulation time 3324213490 ps
CPU time 91.99 seconds
Started Aug 07 06:02:28 PM PDT 24
Finished Aug 07 06:04:00 PM PDT 24
Peak memory 215480 kb
Host smart-b0aaf2fc-e0c4-42b4-aa4c-69184b272b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29539
309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.29539309
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.346764372
Short name T1345
Test name
Test status
Simulation time 2545412515 ps
CPU time 18.78 seconds
Started Aug 07 06:02:26 PM PDT 24
Finished Aug 07 06:02:45 PM PDT 24
Peak memory 215416 kb
Host smart-a695c63d-9fa4-4cc7-bd5f-68fefbc7fd36
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=346764372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.346764372
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.615641277
Short name T1214
Test name
Test status
Simulation time 275690808 ps
CPU time 1 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:02:20 PM PDT 24
Peak memory 206992 kb
Host smart-7005229d-40f2-4d41-8a19-3a1f4e991784
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=615641277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.615641277
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3317101166
Short name T2002
Test name
Test status
Simulation time 187699842 ps
CPU time 0.91 seconds
Started Aug 07 06:02:23 PM PDT 24
Finished Aug 07 06:02:24 PM PDT 24
Peak memory 207008 kb
Host smart-92cffda9-10d6-4fdd-97a5-b7cfc9f3fbbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33171
01166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3317101166
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.1938014072
Short name T2836
Test name
Test status
Simulation time 1783627746 ps
CPU time 13.1 seconds
Started Aug 07 06:02:25 PM PDT 24
Finished Aug 07 06:02:38 PM PDT 24
Peak memory 223528 kb
Host smart-5bd7f17e-6003-4378-9676-db924424fe5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19380
14072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.1938014072
Directory /workspace/18.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1005592126
Short name T1254
Test name
Test status
Simulation time 2768406390 ps
CPU time 82.52 seconds
Started Aug 07 06:02:20 PM PDT 24
Finished Aug 07 06:03:43 PM PDT 24
Peak memory 216820 kb
Host smart-7e2ad727-d8c1-47c8-9b2f-e9a406cfc7cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1005592126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1005592126
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.187468449
Short name T2905
Test name
Test status
Simulation time 154376803 ps
CPU time 0.88 seconds
Started Aug 07 06:02:20 PM PDT 24
Finished Aug 07 06:02:21 PM PDT 24
Peak memory 207020 kb
Host smart-c3852f14-5a85-45f1-a60f-4e3e55164c38
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=187468449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.187468449
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.877563879
Short name T2088
Test name
Test status
Simulation time 157395870 ps
CPU time 0.89 seconds
Started Aug 07 06:02:20 PM PDT 24
Finished Aug 07 06:02:21 PM PDT 24
Peak memory 206988 kb
Host smart-e2767cfc-c2ea-4d31-ab70-b7dce5da3a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87756
3879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.877563879
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.999273725
Short name T2345
Test name
Test status
Simulation time 154950979 ps
CPU time 0.8 seconds
Started Aug 07 06:02:28 PM PDT 24
Finished Aug 07 06:02:29 PM PDT 24
Peak memory 207012 kb
Host smart-463037e0-a2a6-4b04-b0b0-f5c936637151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99927
3725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.999273725
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3583793694
Short name T567
Test name
Test status
Simulation time 194258622 ps
CPU time 0.92 seconds
Started Aug 07 06:02:25 PM PDT 24
Finished Aug 07 06:02:26 PM PDT 24
Peak memory 206944 kb
Host smart-4dcf6c2f-6ac0-4b4d-8cce-2934a61efe39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35837
93694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3583793694
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2813347694
Short name T2125
Test name
Test status
Simulation time 159143831 ps
CPU time 0.83 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:02:20 PM PDT 24
Peak memory 206992 kb
Host smart-2c3462d9-8b58-4468-94c0-23a0b7615584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28133
47694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2813347694
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2470038449
Short name T1460
Test name
Test status
Simulation time 148318426 ps
CPU time 0.82 seconds
Started Aug 07 06:02:22 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 206980 kb
Host smart-58aea561-d2e4-4b78-9600-6bf2abf1ec09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24700
38449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2470038449
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.3895424400
Short name T2430
Test name
Test status
Simulation time 218303986 ps
CPU time 1 seconds
Started Aug 07 06:02:19 PM PDT 24
Finished Aug 07 06:02:20 PM PDT 24
Peak memory 206964 kb
Host smart-c7b41a64-7431-488a-a1af-fcaf8fe0d083
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3895424400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.3895424400
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1012940469
Short name T2987
Test name
Test status
Simulation time 148704281 ps
CPU time 0.8 seconds
Started Aug 07 06:02:23 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 206948 kb
Host smart-c8dec953-8b10-4c54-ae2f-227bd35245fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10129
40469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1012940469
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1805555339
Short name T2737
Test name
Test status
Simulation time 33888326 ps
CPU time 0.74 seconds
Started Aug 07 06:02:22 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 206960 kb
Host smart-cd429eba-baf0-4575-8940-b1ffcc692b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18055
55339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1805555339
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3143956248
Short name T263
Test name
Test status
Simulation time 11443970548 ps
CPU time 28.61 seconds
Started Aug 07 06:02:21 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 215544 kb
Host smart-539a0438-d196-4cd8-95b2-9bf31c21e2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31439
56248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3143956248
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.3251277731
Short name T1974
Test name
Test status
Simulation time 168666696 ps
CPU time 0.86 seconds
Started Aug 07 06:02:27 PM PDT 24
Finished Aug 07 06:02:33 PM PDT 24
Peak memory 206988 kb
Host smart-111f703e-af13-4872-8a76-cdde66613277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32512
77731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.3251277731
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3261562610
Short name T582
Test name
Test status
Simulation time 157312862 ps
CPU time 0.85 seconds
Started Aug 07 06:02:30 PM PDT 24
Finished Aug 07 06:02:36 PM PDT 24
Peak memory 206992 kb
Host smart-a074c916-8484-452e-bd4f-a994d926149e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32615
62610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3261562610
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.1347229557
Short name T2170
Test name
Test status
Simulation time 238330108 ps
CPU time 1 seconds
Started Aug 07 06:02:25 PM PDT 24
Finished Aug 07 06:02:27 PM PDT 24
Peak memory 207008 kb
Host smart-cebcacb0-cdbc-494d-bffd-078d37df9a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13472
29557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.1347229557
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.4135509805
Short name T1075
Test name
Test status
Simulation time 179642492 ps
CPU time 0.94 seconds
Started Aug 07 06:02:27 PM PDT 24
Finished Aug 07 06:02:28 PM PDT 24
Peak memory 207016 kb
Host smart-4e53a418-985b-4bc1-be2c-0092501f6efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41355
09805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.4135509805
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_resume_link_active.1510968376
Short name T767
Test name
Test status
Simulation time 20155342462 ps
CPU time 24.39 seconds
Started Aug 07 06:02:24 PM PDT 24
Finished Aug 07 06:02:49 PM PDT 24
Peak memory 207080 kb
Host smart-b532adcc-8789-452a-8fc5-cccb932e8db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15109
68376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_resume_link_active.1510968376
Directory /workspace/18.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1386882331
Short name T2508
Test name
Test status
Simulation time 239295236 ps
CPU time 0.93 seconds
Started Aug 07 06:02:26 PM PDT 24
Finished Aug 07 06:02:27 PM PDT 24
Peak memory 207016 kb
Host smart-819e0462-8f74-4d6e-b08b-35e5f44888ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13868
82331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1386882331
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_rx_full.2691644563
Short name T1384
Test name
Test status
Simulation time 358665679 ps
CPU time 1.31 seconds
Started Aug 07 06:02:24 PM PDT 24
Finished Aug 07 06:02:26 PM PDT 24
Peak memory 207000 kb
Host smart-4381123a-298e-4c74-b7a6-c0d5adcedb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26916
44563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.2691644563
Directory /workspace/18.usbdev_rx_full/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1614520308
Short name T3025
Test name
Test status
Simulation time 147850221 ps
CPU time 0.83 seconds
Started Aug 07 06:02:29 PM PDT 24
Finished Aug 07 06:02:30 PM PDT 24
Peak memory 206960 kb
Host smart-02e5f50c-4034-4cc0-8491-0c740fa96841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16145
20308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1614520308
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1432236232
Short name T2271
Test name
Test status
Simulation time 202616393 ps
CPU time 0.9 seconds
Started Aug 07 06:02:25 PM PDT 24
Finished Aug 07 06:02:26 PM PDT 24
Peak memory 206916 kb
Host smart-cb77ec1f-d8e5-420c-b11c-e8403e6b5f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14322
36232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1432236232
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2133643061
Short name T2409
Test name
Test status
Simulation time 259616134 ps
CPU time 1.13 seconds
Started Aug 07 06:02:26 PM PDT 24
Finished Aug 07 06:02:27 PM PDT 24
Peak memory 207000 kb
Host smart-d0fc3959-9ba9-4d51-89f3-8e653685cce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21336
43061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2133643061
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.1973999485
Short name T2281
Test name
Test status
Simulation time 2378158339 ps
CPU time 64.59 seconds
Started Aug 07 06:02:27 PM PDT 24
Finished Aug 07 06:03:31 PM PDT 24
Peak memory 223656 kb
Host smart-8abda510-c63e-4d6e-ae57-916da2b68557
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1973999485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.1973999485
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2208601648
Short name T3119
Test name
Test status
Simulation time 170450606 ps
CPU time 0.85 seconds
Started Aug 07 06:02:24 PM PDT 24
Finished Aug 07 06:02:25 PM PDT 24
Peak memory 207008 kb
Host smart-144cd2f8-c5ab-438c-997a-ce03bf9efa06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22086
01648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2208601648
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2948143757
Short name T912
Test name
Test status
Simulation time 180305973 ps
CPU time 0.85 seconds
Started Aug 07 06:02:27 PM PDT 24
Finished Aug 07 06:02:28 PM PDT 24
Peak memory 206984 kb
Host smart-98ffede2-9863-4073-ac7f-1efc2415b345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29481
43757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2948143757
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.668905654
Short name T542
Test name
Test status
Simulation time 1343358651 ps
CPU time 2.98 seconds
Started Aug 07 06:02:28 PM PDT 24
Finished Aug 07 06:02:31 PM PDT 24
Peak memory 207092 kb
Host smart-2c0f4087-8e11-4293-a0c5-a9732fc0f938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66890
5654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.668905654
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2797469944
Short name T2636
Test name
Test status
Simulation time 2526426384 ps
CPU time 70.25 seconds
Started Aug 07 06:02:23 PM PDT 24
Finished Aug 07 06:03:33 PM PDT 24
Peak memory 217212 kb
Host smart-8098031c-da81-4e1b-8701-38ed757b7df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27974
69944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2797469944
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.331759584
Short name T1123
Test name
Test status
Simulation time 7719420564 ps
CPU time 50.32 seconds
Started Aug 07 06:02:20 PM PDT 24
Finished Aug 07 06:03:10 PM PDT 24
Peak memory 207296 kb
Host smart-5ee86705-e545-4613-9fa1-5037c8c320f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331759584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_host
_handshake.331759584
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/180.usbdev_endpoint_types.4200062170
Short name T461
Test name
Test status
Simulation time 284994956 ps
CPU time 1.16 seconds
Started Aug 07 06:13:09 PM PDT 24
Finished Aug 07 06:13:11 PM PDT 24
Peak memory 206952 kb
Host smart-e9213de9-c7b4-4744-9ace-be008ae13f9f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4200062170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.4200062170
Directory /workspace/180.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/181.usbdev_endpoint_types.2620436614
Short name T1807
Test name
Test status
Simulation time 180141068 ps
CPU time 0.9 seconds
Started Aug 07 06:13:09 PM PDT 24
Finished Aug 07 06:13:11 PM PDT 24
Peak memory 206948 kb
Host smart-9250dfe2-4eeb-4b4f-8f26-21d8e473ed68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2620436614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.2620436614
Directory /workspace/181.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/182.usbdev_endpoint_types.4165068948
Short name T441
Test name
Test status
Simulation time 292318634 ps
CPU time 1.16 seconds
Started Aug 07 06:13:13 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206980 kb
Host smart-f6b148b6-884f-454e-8e55-c604b583c1cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4165068948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.4165068948
Directory /workspace/182.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/183.usbdev_endpoint_types.1334626243
Short name T2273
Test name
Test status
Simulation time 632881311 ps
CPU time 1.55 seconds
Started Aug 07 06:13:13 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 206940 kb
Host smart-b3228c49-3673-42eb-8aea-49f291e39499
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1334626243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.1334626243
Directory /workspace/183.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/184.usbdev_endpoint_types.3494993043
Short name T404
Test name
Test status
Simulation time 437329226 ps
CPU time 1.33 seconds
Started Aug 07 06:13:13 PM PDT 24
Finished Aug 07 06:13:14 PM PDT 24
Peak memory 206976 kb
Host smart-b9155b72-85c1-42ba-ab72-814aa5980c06
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3494993043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.3494993043
Directory /workspace/184.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/185.usbdev_endpoint_types.3451091621
Short name T2406
Test name
Test status
Simulation time 402445500 ps
CPU time 1.21 seconds
Started Aug 07 06:13:10 PM PDT 24
Finished Aug 07 06:13:11 PM PDT 24
Peak memory 206944 kb
Host smart-dab68338-6c4b-46dc-999e-72f34eba701d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3451091621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.3451091621
Directory /workspace/185.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/186.usbdev_endpoint_types.2755637335
Short name T362
Test name
Test status
Simulation time 637219531 ps
CPU time 1.44 seconds
Started Aug 07 06:13:10 PM PDT 24
Finished Aug 07 06:13:12 PM PDT 24
Peak memory 206884 kb
Host smart-1f8a9c10-6980-4b88-b877-4e8be21deee5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2755637335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.2755637335
Directory /workspace/186.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/188.usbdev_endpoint_types.1740564478
Short name T443
Test name
Test status
Simulation time 290564374 ps
CPU time 1.06 seconds
Started Aug 07 06:13:23 PM PDT 24
Finished Aug 07 06:13:24 PM PDT 24
Peak memory 206956 kb
Host smart-5a3130cf-a1fa-4af4-a889-c715c31dbb95
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1740564478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.1740564478
Directory /workspace/188.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/189.usbdev_endpoint_types.3136367178
Short name T409
Test name
Test status
Simulation time 419162692 ps
CPU time 1.26 seconds
Started Aug 07 06:13:20 PM PDT 24
Finished Aug 07 06:13:22 PM PDT 24
Peak memory 206928 kb
Host smart-95c96f23-32a8-450e-ac03-34c61421d79a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3136367178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.3136367178
Directory /workspace/189.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.1285663296
Short name T1422
Test name
Test status
Simulation time 40178363 ps
CPU time 0.69 seconds
Started Aug 07 06:02:38 PM PDT 24
Finished Aug 07 06:02:39 PM PDT 24
Peak memory 207072 kb
Host smart-906e15ce-098b-4c4d-8b83-dfa8e7487e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1285663296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.1285663296
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1079715196
Short name T738
Test name
Test status
Simulation time 4816333943 ps
CPU time 6.26 seconds
Started Aug 07 06:02:24 PM PDT 24
Finished Aug 07 06:02:30 PM PDT 24
Peak memory 215396 kb
Host smart-598b032f-9d3a-4ec8-b9ec-95a7bc49ee55
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079715196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.1079715196
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.18086198
Short name T1398
Test name
Test status
Simulation time 18922819706 ps
CPU time 22.06 seconds
Started Aug 07 06:02:25 PM PDT 24
Finished Aug 07 06:02:47 PM PDT 24
Peak memory 207192 kb
Host smart-860eaa0c-41ff-401b-a740-b836eb359e2e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=18086198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.18086198
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2638267725
Short name T1821
Test name
Test status
Simulation time 29047837963 ps
CPU time 33.23 seconds
Started Aug 07 06:02:28 PM PDT 24
Finished Aug 07 06:03:01 PM PDT 24
Peak memory 207264 kb
Host smart-945eed04-3734-477e-8914-18a2be9ea3b0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638267725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_resume.2638267725
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3228142654
Short name T2888
Test name
Test status
Simulation time 166833308 ps
CPU time 0.87 seconds
Started Aug 07 06:02:25 PM PDT 24
Finished Aug 07 06:02:26 PM PDT 24
Peak memory 207036 kb
Host smart-ed34b714-af55-4a69-8037-6423ba3df4f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32281
42654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3228142654
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.940026629
Short name T2634
Test name
Test status
Simulation time 139836120 ps
CPU time 0.86 seconds
Started Aug 07 06:02:31 PM PDT 24
Finished Aug 07 06:02:32 PM PDT 24
Peak memory 207000 kb
Host smart-f664d3c4-aaca-48a3-8dea-4d15f01c5d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94002
6629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.940026629
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.2218948153
Short name T2907
Test name
Test status
Simulation time 356554790 ps
CPU time 1.33 seconds
Started Aug 07 06:02:28 PM PDT 24
Finished Aug 07 06:02:29 PM PDT 24
Peak memory 206992 kb
Host smart-39e1ac33-3dcb-4efd-99eb-bb867a013fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22189
48153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.2218948153
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2161439083
Short name T624
Test name
Test status
Simulation time 1281594794 ps
CPU time 3.49 seconds
Started Aug 07 06:02:24 PM PDT 24
Finished Aug 07 06:02:28 PM PDT 24
Peak memory 207080 kb
Host smart-3e143052-1a32-4004-87c4-6342494c432b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2161439083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2161439083
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.3244748711
Short name T181
Test name
Test status
Simulation time 46934087322 ps
CPU time 70.6 seconds
Started Aug 07 06:02:31 PM PDT 24
Finished Aug 07 06:03:42 PM PDT 24
Peak memory 207300 kb
Host smart-0dda3ef8-d9a4-4f35-9a58-f582380a8bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32447
48711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.3244748711
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.1908342987
Short name T825
Test name
Test status
Simulation time 278310334 ps
CPU time 4.29 seconds
Started Aug 07 06:02:25 PM PDT 24
Finished Aug 07 06:02:29 PM PDT 24
Peak memory 207124 kb
Host smart-5bd112c6-a42e-487d-b23e-37f0cac55891
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908342987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.1908342987
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.1754351607
Short name T2602
Test name
Test status
Simulation time 700992663 ps
CPU time 1.77 seconds
Started Aug 07 06:02:32 PM PDT 24
Finished Aug 07 06:02:34 PM PDT 24
Peak memory 206976 kb
Host smart-fff8e6ce-b15d-4d2b-8acf-20141938f5fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17543
51607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.1754351607
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.984241808
Short name T954
Test name
Test status
Simulation time 139135220 ps
CPU time 0.82 seconds
Started Aug 07 06:02:32 PM PDT 24
Finished Aug 07 06:02:33 PM PDT 24
Peak memory 206980 kb
Host smart-2d6641c8-75fa-4c63-b9a4-49f86c47b7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98424
1808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.984241808
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2344759375
Short name T976
Test name
Test status
Simulation time 25329991 ps
CPU time 0.65 seconds
Started Aug 07 06:02:24 PM PDT 24
Finished Aug 07 06:02:25 PM PDT 24
Peak memory 206952 kb
Host smart-86a4ca64-b591-4675-a6da-55aa6b494f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23447
59375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2344759375
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3457506699
Short name T1
Test name
Test status
Simulation time 934871025 ps
CPU time 2.44 seconds
Started Aug 07 06:02:28 PM PDT 24
Finished Aug 07 06:02:31 PM PDT 24
Peak memory 207236 kb
Host smart-02dd6bf5-9c63-43f5-8bf7-2ff1ccaa385d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34575
06699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3457506699
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_types.2787470926
Short name T1541
Test name
Test status
Simulation time 272987393 ps
CPU time 1.11 seconds
Started Aug 07 06:02:26 PM PDT 24
Finished Aug 07 06:02:27 PM PDT 24
Peak memory 206956 kb
Host smart-3bf7a4f6-4a24-4b44-a763-cdb99bb95e03
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2787470926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.2787470926
Directory /workspace/19.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2175803821
Short name T2045
Test name
Test status
Simulation time 193526263 ps
CPU time 1.48 seconds
Started Aug 07 06:02:26 PM PDT 24
Finished Aug 07 06:02:27 PM PDT 24
Peak memory 207004 kb
Host smart-4b4ced96-4726-41b4-84c8-122178c71727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21758
03821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2175803821
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3830718626
Short name T2936
Test name
Test status
Simulation time 234752131 ps
CPU time 1.21 seconds
Started Aug 07 06:02:27 PM PDT 24
Finished Aug 07 06:02:28 PM PDT 24
Peak memory 215340 kb
Host smart-60464931-5ab9-4c43-a6a1-36194ff41adf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3830718626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3830718626
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.4266663360
Short name T2622
Test name
Test status
Simulation time 142935145 ps
CPU time 0.84 seconds
Started Aug 07 06:02:26 PM PDT 24
Finished Aug 07 06:02:27 PM PDT 24
Peak memory 206924 kb
Host smart-93858150-9ea3-4a0c-a393-4611f6e8ba00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42666
63360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.4266663360
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2135035040
Short name T1000
Test name
Test status
Simulation time 170716823 ps
CPU time 0.86 seconds
Started Aug 07 06:02:25 PM PDT 24
Finished Aug 07 06:02:26 PM PDT 24
Peak memory 207012 kb
Host smart-4b7186f3-52c1-4064-a4b1-7e1630c19d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21350
35040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2135035040
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.167041600
Short name T1039
Test name
Test status
Simulation time 4280748314 ps
CPU time 125 seconds
Started Aug 07 06:02:27 PM PDT 24
Finished Aug 07 06:04:32 PM PDT 24
Peak memory 223532 kb
Host smart-be53e9f4-3008-4ed3-9ebd-6eb455e16603
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=167041600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.167041600
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.2589975946
Short name T5
Test name
Test status
Simulation time 10718813432 ps
CPU time 79.41 seconds
Started Aug 07 06:02:28 PM PDT 24
Finished Aug 07 06:03:47 PM PDT 24
Peak memory 207260 kb
Host smart-5267bb1b-35ce-4983-8b4c-2ba327de7f59
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2589975946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.2589975946
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.822504084
Short name T1143
Test name
Test status
Simulation time 211855160 ps
CPU time 0.9 seconds
Started Aug 07 06:02:30 PM PDT 24
Finished Aug 07 06:02:31 PM PDT 24
Peak memory 206992 kb
Host smart-88a1f1a8-bfa4-4373-9e59-516f6a4a3bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82250
4084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.822504084
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.738549462
Short name T2988
Test name
Test status
Simulation time 29382343094 ps
CPU time 34.58 seconds
Started Aug 07 06:02:28 PM PDT 24
Finished Aug 07 06:03:03 PM PDT 24
Peak memory 207280 kb
Host smart-b10960ab-63fa-469b-872c-3ff5e6d57000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73854
9462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.738549462
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.1370943896
Short name T1339
Test name
Test status
Simulation time 4183580285 ps
CPU time 5.81 seconds
Started Aug 07 06:02:27 PM PDT 24
Finished Aug 07 06:02:33 PM PDT 24
Peak memory 215460 kb
Host smart-823053fe-150a-427a-9269-f2d092192ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13709
43896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1370943896
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.2272600900
Short name T2565
Test name
Test status
Simulation time 4742256400 ps
CPU time 140.18 seconds
Started Aug 07 06:02:29 PM PDT 24
Finished Aug 07 06:04:49 PM PDT 24
Peak memory 218168 kb
Host smart-5dcf84a6-aa68-4cd6-9a8e-20c1b3b42f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22726
00900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.2272600900
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.689628479
Short name T2825
Test name
Test status
Simulation time 2106170047 ps
CPU time 57.58 seconds
Started Aug 07 06:02:26 PM PDT 24
Finished Aug 07 06:03:23 PM PDT 24
Peak memory 215260 kb
Host smart-125dfb37-d241-472b-b453-ec1057d4c32e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=689628479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.689628479
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.1028105866
Short name T232
Test name
Test status
Simulation time 314082580 ps
CPU time 1.08 seconds
Started Aug 07 06:02:27 PM PDT 24
Finished Aug 07 06:02:29 PM PDT 24
Peak memory 207020 kb
Host smart-3c276e64-165d-499c-b3d1-0b1fa4a939f3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1028105866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.1028105866
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.699910254
Short name T2502
Test name
Test status
Simulation time 198613430 ps
CPU time 1.01 seconds
Started Aug 07 06:02:35 PM PDT 24
Finished Aug 07 06:02:36 PM PDT 24
Peak memory 206956 kb
Host smart-ef286f14-f097-4695-82ce-0f6fff62ec5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69991
0254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.699910254
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.1530273813
Short name T1266
Test name
Test status
Simulation time 2697314981 ps
CPU time 79.09 seconds
Started Aug 07 06:02:35 PM PDT 24
Finished Aug 07 06:03:54 PM PDT 24
Peak memory 215436 kb
Host smart-9fe57292-9fbe-46c1-8a09-264d5a78749f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15302
73813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.1530273813
Directory /workspace/19.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.711182949
Short name T1481
Test name
Test status
Simulation time 2320937543 ps
CPU time 18.22 seconds
Started Aug 07 06:02:34 PM PDT 24
Finished Aug 07 06:02:52 PM PDT 24
Peak memory 207332 kb
Host smart-8b910be4-941b-4109-aa4d-933afac37286
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=711182949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.711182949
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.42246040
Short name T535
Test name
Test status
Simulation time 209869034 ps
CPU time 0.92 seconds
Started Aug 07 06:02:54 PM PDT 24
Finished Aug 07 06:02:55 PM PDT 24
Peak memory 206964 kb
Host smart-30b253f6-f173-4acf-953d-2cf2a310d411
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=42246040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.42246040
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3687499174
Short name T923
Test name
Test status
Simulation time 154005107 ps
CPU time 0.88 seconds
Started Aug 07 06:02:33 PM PDT 24
Finished Aug 07 06:02:34 PM PDT 24
Peak memory 206964 kb
Host smart-bd8d0413-8654-407d-951d-0f7c3e3175c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36874
99174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3687499174
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2466992324
Short name T2501
Test name
Test status
Simulation time 199673989 ps
CPU time 0.92 seconds
Started Aug 07 06:02:35 PM PDT 24
Finished Aug 07 06:02:36 PM PDT 24
Peak memory 206888 kb
Host smart-9cda9e75-966c-4762-bb61-09709caf8db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24669
92324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2466992324
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2935582051
Short name T1849
Test name
Test status
Simulation time 167539991 ps
CPU time 0.86 seconds
Started Aug 07 06:02:32 PM PDT 24
Finished Aug 07 06:02:33 PM PDT 24
Peak memory 206960 kb
Host smart-8489cefb-381d-4a67-a6ff-c616ff62762a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29355
82051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2935582051
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3360840698
Short name T1693
Test name
Test status
Simulation time 187846179 ps
CPU time 0.93 seconds
Started Aug 07 06:02:35 PM PDT 24
Finished Aug 07 06:02:36 PM PDT 24
Peak memory 206960 kb
Host smart-4a8edf26-f83b-4439-9509-7a668758c902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33608
40698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3360840698
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2455738102
Short name T1510
Test name
Test status
Simulation time 165077443 ps
CPU time 0.83 seconds
Started Aug 07 06:02:31 PM PDT 24
Finished Aug 07 06:02:32 PM PDT 24
Peak memory 207000 kb
Host smart-f08d5cf6-6221-4790-91ae-2a0935390f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24557
38102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2455738102
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3494096167
Short name T1873
Test name
Test status
Simulation time 181197624 ps
CPU time 0.89 seconds
Started Aug 07 06:02:37 PM PDT 24
Finished Aug 07 06:02:38 PM PDT 24
Peak memory 207192 kb
Host smart-f99ba2f3-5b03-4370-b446-96dbf3d9c011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34940
96167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3494096167
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3705667118
Short name T1599
Test name
Test status
Simulation time 303349705 ps
CPU time 1.06 seconds
Started Aug 07 06:02:33 PM PDT 24
Finished Aug 07 06:02:34 PM PDT 24
Peak memory 206996 kb
Host smart-871dacb6-23ca-40eb-ba81-58a33474935d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3705667118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3705667118
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.384791077
Short name T2043
Test name
Test status
Simulation time 137572785 ps
CPU time 0.77 seconds
Started Aug 07 06:02:31 PM PDT 24
Finished Aug 07 06:02:32 PM PDT 24
Peak memory 206876 kb
Host smart-90d4e3e4-cc8c-4d0d-ac00-c258d6d4a0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38479
1077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.384791077
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3505482906
Short name T3060
Test name
Test status
Simulation time 35841179 ps
CPU time 0.68 seconds
Started Aug 07 06:02:32 PM PDT 24
Finished Aug 07 06:02:33 PM PDT 24
Peak memory 206952 kb
Host smart-06e9c78b-b541-456f-a15a-7063226a0941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35054
82906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3505482906
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3856810819
Short name T2667
Test name
Test status
Simulation time 23181804943 ps
CPU time 66.9 seconds
Started Aug 07 06:02:36 PM PDT 24
Finished Aug 07 06:03:43 PM PDT 24
Peak memory 215524 kb
Host smart-4e36d33c-479d-4162-81ad-c629c531d4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38568
10819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3856810819
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.56126375
Short name T679
Test name
Test status
Simulation time 194293572 ps
CPU time 0.95 seconds
Started Aug 07 06:02:42 PM PDT 24
Finished Aug 07 06:02:43 PM PDT 24
Peak memory 207016 kb
Host smart-87b6513f-f680-47d3-9e32-48ea1cd29ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56126
375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.56126375
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3508908060
Short name T531
Test name
Test status
Simulation time 237064370 ps
CPU time 1.05 seconds
Started Aug 07 06:02:33 PM PDT 24
Finished Aug 07 06:02:34 PM PDT 24
Peak memory 206964 kb
Host smart-77126397-3aeb-4084-8f6c-33a8a346b5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35089
08060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3508908060
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1533199772
Short name T829
Test name
Test status
Simulation time 240329255 ps
CPU time 0.96 seconds
Started Aug 07 06:02:33 PM PDT 24
Finished Aug 07 06:02:34 PM PDT 24
Peak memory 206908 kb
Host smart-394d5d8b-aa0a-49be-bef2-9bd6ab229743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15331
99772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1533199772
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_resume_link_active.4217706580
Short name T2259
Test name
Test status
Simulation time 20172850516 ps
CPU time 21.84 seconds
Started Aug 07 06:02:35 PM PDT 24
Finished Aug 07 06:02:57 PM PDT 24
Peak memory 207036 kb
Host smart-185e3e1c-c15a-4d1e-ba17-5fbc472e7846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42177
06580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.4217706580
Directory /workspace/19.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1484982088
Short name T2261
Test name
Test status
Simulation time 163506395 ps
CPU time 0.91 seconds
Started Aug 07 06:02:48 PM PDT 24
Finished Aug 07 06:02:49 PM PDT 24
Peak memory 206992 kb
Host smart-c0751375-69b0-4dbc-964e-02b824245aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14849
82088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1484982088
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_rx_full.114349838
Short name T2265
Test name
Test status
Simulation time 249896973 ps
CPU time 1.15 seconds
Started Aug 07 06:02:48 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 207008 kb
Host smart-b427ae02-66bc-45b0-a86e-7b5ea48e9243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11434
9838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.114349838
Directory /workspace/19.usbdev_rx_full/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2787313663
Short name T2239
Test name
Test status
Simulation time 155115360 ps
CPU time 0.84 seconds
Started Aug 07 06:02:35 PM PDT 24
Finished Aug 07 06:02:36 PM PDT 24
Peak memory 207004 kb
Host smart-31359ab6-c2fb-4986-bdcb-88e2142ad811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27873
13663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2787313663
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3676350866
Short name T2269
Test name
Test status
Simulation time 150183030 ps
CPU time 0.91 seconds
Started Aug 07 06:02:36 PM PDT 24
Finished Aug 07 06:02:37 PM PDT 24
Peak memory 206916 kb
Host smart-561e95a3-241b-47a8-8828-fbe2982c6371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36763
50866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3676350866
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2192464145
Short name T1341
Test name
Test status
Simulation time 210540950 ps
CPU time 1 seconds
Started Aug 07 06:02:33 PM PDT 24
Finished Aug 07 06:02:34 PM PDT 24
Peak memory 207000 kb
Host smart-ead5d38d-3251-4751-9ecd-1e4bedf2a00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21924
64145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2192464145
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3077009822
Short name T817
Test name
Test status
Simulation time 2679696163 ps
CPU time 27.09 seconds
Started Aug 07 06:02:34 PM PDT 24
Finished Aug 07 06:03:02 PM PDT 24
Peak memory 223568 kb
Host smart-e3b21bfb-de53-447a-b055-0e39a1e422b7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3077009822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3077009822
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2818168100
Short name T3063
Test name
Test status
Simulation time 152924159 ps
CPU time 0.87 seconds
Started Aug 07 06:02:35 PM PDT 24
Finished Aug 07 06:02:36 PM PDT 24
Peak memory 206980 kb
Host smart-b91cb463-af36-4770-b722-f9ebed7b4909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28181
68100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2818168100
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3784280626
Short name T2434
Test name
Test status
Simulation time 150700675 ps
CPU time 0.85 seconds
Started Aug 07 06:02:34 PM PDT 24
Finished Aug 07 06:02:35 PM PDT 24
Peak memory 206984 kb
Host smart-b7538feb-4525-48ce-9023-c46f74371a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37842
80626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3784280626
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.2368689147
Short name T2791
Test name
Test status
Simulation time 1197350811 ps
CPU time 2.8 seconds
Started Aug 07 06:02:32 PM PDT 24
Finished Aug 07 06:02:35 PM PDT 24
Peak memory 207168 kb
Host smart-89b7aad7-786a-49d8-a422-138a3802bdd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23686
89147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.2368689147
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.2660849757
Short name T1914
Test name
Test status
Simulation time 1838396479 ps
CPU time 52.21 seconds
Started Aug 07 06:02:35 PM PDT 24
Finished Aug 07 06:03:28 PM PDT 24
Peak memory 215360 kb
Host smart-cd74d8ea-cb30-48c6-ab64-d829647db15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26608
49757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.2660849757
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.3519675239
Short name T1008
Test name
Test status
Simulation time 926592842 ps
CPU time 18.68 seconds
Started Aug 07 06:02:26 PM PDT 24
Finished Aug 07 06:02:45 PM PDT 24
Peak memory 207128 kb
Host smart-96a776bb-27f8-43a8-a470-5c0aa33bfb0d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519675239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.3519675239
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/190.usbdev_endpoint_types.4270978051
Short name T439
Test name
Test status
Simulation time 159144762 ps
CPU time 0.92 seconds
Started Aug 07 06:13:18 PM PDT 24
Finished Aug 07 06:13:19 PM PDT 24
Peak memory 206944 kb
Host smart-ae48dea5-b615-4c39-b28c-30efa43a0e39
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4270978051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.4270978051
Directory /workspace/190.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/191.usbdev_endpoint_types.3705729811
Short name T447
Test name
Test status
Simulation time 343388170 ps
CPU time 1.17 seconds
Started Aug 07 06:13:21 PM PDT 24
Finished Aug 07 06:13:22 PM PDT 24
Peak memory 206964 kb
Host smart-01351ae4-70f0-4ced-b800-39eb956667b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3705729811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.3705729811
Directory /workspace/191.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/192.usbdev_endpoint_types.3710769035
Short name T392
Test name
Test status
Simulation time 426572801 ps
CPU time 1.22 seconds
Started Aug 07 06:13:22 PM PDT 24
Finished Aug 07 06:13:23 PM PDT 24
Peak memory 206408 kb
Host smart-1109e0d9-f19e-4426-91b6-85e90d7881fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3710769035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.3710769035
Directory /workspace/192.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/193.usbdev_endpoint_types.3426934976
Short name T431
Test name
Test status
Simulation time 462298844 ps
CPU time 1.27 seconds
Started Aug 07 06:13:22 PM PDT 24
Finished Aug 07 06:13:23 PM PDT 24
Peak memory 206876 kb
Host smart-7e93cf65-38f5-4c20-89e7-1556e349dd93
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3426934976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.3426934976
Directory /workspace/193.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/194.usbdev_endpoint_types.3532652347
Short name T372
Test name
Test status
Simulation time 724361685 ps
CPU time 1.64 seconds
Started Aug 07 06:13:22 PM PDT 24
Finished Aug 07 06:13:23 PM PDT 24
Peak memory 206408 kb
Host smart-84255ca6-0980-415e-a0eb-4beb5d57fc46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3532652347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.3532652347
Directory /workspace/194.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/195.usbdev_endpoint_types.2137771288
Short name T2389
Test name
Test status
Simulation time 436945466 ps
CPU time 1.3 seconds
Started Aug 07 06:13:20 PM PDT 24
Finished Aug 07 06:13:22 PM PDT 24
Peak memory 207012 kb
Host smart-a202e2cc-77a2-42f8-96c2-2e4d86bbb702
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2137771288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.2137771288
Directory /workspace/195.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/196.usbdev_endpoint_types.3565502862
Short name T479
Test name
Test status
Simulation time 716215933 ps
CPU time 1.7 seconds
Started Aug 07 06:13:20 PM PDT 24
Finished Aug 07 06:13:21 PM PDT 24
Peak memory 206964 kb
Host smart-5d87d049-d9aa-4cb1-9c63-1dc2072a57a9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3565502862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.3565502862
Directory /workspace/196.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/197.usbdev_endpoint_types.309237121
Short name T3045
Test name
Test status
Simulation time 486950393 ps
CPU time 1.3 seconds
Started Aug 07 06:13:20 PM PDT 24
Finished Aug 07 06:13:21 PM PDT 24
Peak memory 206956 kb
Host smart-27f4d9bc-b1c2-4627-9390-21761fcd3774
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=309237121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.309237121
Directory /workspace/197.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/198.usbdev_endpoint_types.1004397462
Short name T2469
Test name
Test status
Simulation time 214227383 ps
CPU time 0.88 seconds
Started Aug 07 06:13:17 PM PDT 24
Finished Aug 07 06:13:18 PM PDT 24
Peak memory 206952 kb
Host smart-486b5d3f-d18c-48a4-9f28-bfbead58f032
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1004397462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.1004397462
Directory /workspace/198.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/199.usbdev_endpoint_types.3423106970
Short name T455
Test name
Test status
Simulation time 523846022 ps
CPU time 1.32 seconds
Started Aug 07 06:13:19 PM PDT 24
Finished Aug 07 06:13:20 PM PDT 24
Peak memory 206892 kb
Host smart-94beea7c-1056-4fcf-b320-217f4fa84e60
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3423106970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.3423106970
Directory /workspace/199.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.2211728849
Short name T2190
Test name
Test status
Simulation time 60227381 ps
CPU time 0.69 seconds
Started Aug 07 05:59:02 PM PDT 24
Finished Aug 07 05:59:03 PM PDT 24
Peak memory 207096 kb
Host smart-f8077ba1-dfe5-4ccd-8184-a54db19fb509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2211728849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.2211728849
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.2726702329
Short name T1092
Test name
Test status
Simulation time 11635074155 ps
CPU time 14.5 seconds
Started Aug 07 05:58:40 PM PDT 24
Finished Aug 07 05:58:54 PM PDT 24
Peak memory 207308 kb
Host smart-7b3ac90a-ef72-48a5-b799-7027c57767fc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726702329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.2726702329
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.2254114227
Short name T1444
Test name
Test status
Simulation time 14490082890 ps
CPU time 16.73 seconds
Started Aug 07 05:58:40 PM PDT 24
Finished Aug 07 05:58:57 PM PDT 24
Peak memory 215380 kb
Host smart-c99b75e3-c2f0-4c9f-8c64-0a3ce785afa3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254114227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2254114227
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.188865141
Short name T2013
Test name
Test status
Simulation time 24521606695 ps
CPU time 34.5 seconds
Started Aug 07 05:58:40 PM PDT 24
Finished Aug 07 05:59:15 PM PDT 24
Peak memory 215420 kb
Host smart-dc3e5679-cfff-4821-8e72-7f4207fdffc6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188865141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon
_wake_resume.188865141
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.142782934
Short name T504
Test name
Test status
Simulation time 210565267 ps
CPU time 0.93 seconds
Started Aug 07 05:58:40 PM PDT 24
Finished Aug 07 05:58:41 PM PDT 24
Peak memory 206972 kb
Host smart-3fbd7608-7c9c-42aa-a5a9-fcd12ea54346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14278
2934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.142782934
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.1021356518
Short name T43
Test name
Test status
Simulation time 155787032 ps
CPU time 0.85 seconds
Started Aug 07 05:58:41 PM PDT 24
Finished Aug 07 05:58:42 PM PDT 24
Peak memory 206856 kb
Host smart-da7104c2-3a5f-4fea-b9cc-16bdd2e7d1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10213
56518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.1021356518
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.3473893882
Short name T59
Test name
Test status
Simulation time 153755740 ps
CPU time 0.87 seconds
Started Aug 07 05:58:41 PM PDT 24
Finished Aug 07 05:58:42 PM PDT 24
Peak memory 206944 kb
Host smart-972c7dc7-fccf-4f34-a595-05079c95ac95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34738
93882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.3473893882
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2146437758
Short name T1643
Test name
Test status
Simulation time 195550395 ps
CPU time 0.94 seconds
Started Aug 07 05:58:42 PM PDT 24
Finished Aug 07 05:58:43 PM PDT 24
Peak memory 206936 kb
Host smart-8f76cef4-99dc-4a38-82a4-45880d4c441a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21464
37758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2146437758
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.1958714729
Short name T753
Test name
Test status
Simulation time 202374459 ps
CPU time 0.99 seconds
Started Aug 07 05:58:39 PM PDT 24
Finished Aug 07 05:58:40 PM PDT 24
Peak memory 207008 kb
Host smart-84640ce2-240f-4617-b588-5e8f90c7964c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19587
14729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.1958714729
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.698637391
Short name T2900
Test name
Test status
Simulation time 859857226 ps
CPU time 2.49 seconds
Started Aug 07 05:58:41 PM PDT 24
Finished Aug 07 05:58:43 PM PDT 24
Peak memory 207184 kb
Host smart-508288dd-2fb7-4d5c-9592-384f22e0be39
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=698637391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.698637391
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.301024369
Short name T482
Test name
Test status
Simulation time 40807793254 ps
CPU time 64.23 seconds
Started Aug 07 05:58:42 PM PDT 24
Finished Aug 07 05:59:46 PM PDT 24
Peak memory 207316 kb
Host smart-d79162eb-d209-465f-8c85-1da2570bc0be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30102
4369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.301024369
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.4112676640
Short name T2932
Test name
Test status
Simulation time 717376044 ps
CPU time 15.63 seconds
Started Aug 07 05:58:41 PM PDT 24
Finished Aug 07 05:58:57 PM PDT 24
Peak memory 207160 kb
Host smart-7a85438e-96e7-4916-811b-c8cb7c3f83d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112676640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.4112676640
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1417510522
Short name T3003
Test name
Test status
Simulation time 690334970 ps
CPU time 1.8 seconds
Started Aug 07 05:59:25 PM PDT 24
Finished Aug 07 05:59:27 PM PDT 24
Peak memory 206932 kb
Host smart-1e190535-aa31-426a-a28e-5a6f2a7a87c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14175
10522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1417510522
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2606503186
Short name T1550
Test name
Test status
Simulation time 141457113 ps
CPU time 0.8 seconds
Started Aug 07 05:58:41 PM PDT 24
Finished Aug 07 05:58:42 PM PDT 24
Peak memory 206972 kb
Host smart-d54d6b96-23f5-4ce9-ad4a-bf511d84423b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26065
03186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2606503186
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.4074054377
Short name T1041
Test name
Test status
Simulation time 56538085 ps
CPU time 0.71 seconds
Started Aug 07 05:58:42 PM PDT 24
Finished Aug 07 05:58:43 PM PDT 24
Peak memory 207008 kb
Host smart-c1d01ebf-f149-4f8b-abf8-cbed566bb943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40740
54377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.4074054377
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2399621846
Short name T2933
Test name
Test status
Simulation time 1002879788 ps
CPU time 2.67 seconds
Started Aug 07 05:58:40 PM PDT 24
Finished Aug 07 05:58:43 PM PDT 24
Peak memory 207272 kb
Host smart-328cb1fe-ee2b-4a2c-9731-17a91d8860b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23996
21846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2399621846
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_types.3794282971
Short name T444
Test name
Test status
Simulation time 557201073 ps
CPU time 1.39 seconds
Started Aug 07 05:58:38 PM PDT 24
Finished Aug 07 05:58:39 PM PDT 24
Peak memory 206912 kb
Host smart-aff007bf-82dd-417e-b915-46cc1c22bbf6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3794282971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.3794282971
Directory /workspace/2.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1858233424
Short name T799
Test name
Test status
Simulation time 300628683 ps
CPU time 2.18 seconds
Started Aug 07 05:58:44 PM PDT 24
Finished Aug 07 05:58:47 PM PDT 24
Peak memory 207148 kb
Host smart-9141fc30-b63d-4192-83f0-a5ae8cdc29f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18582
33424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1858233424
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.767124450
Short name T2396
Test name
Test status
Simulation time 101177626808 ps
CPU time 178.02 seconds
Started Aug 07 05:58:46 PM PDT 24
Finished Aug 07 06:01:44 PM PDT 24
Peak memory 207276 kb
Host smart-23c0fdd0-2e96-412c-9654-2b84dfb94a62
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=767124450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.767124450
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.1325652171
Short name T1499
Test name
Test status
Simulation time 108100593885 ps
CPU time 177.73 seconds
Started Aug 07 05:58:46 PM PDT 24
Finished Aug 07 06:01:44 PM PDT 24
Peak memory 207284 kb
Host smart-6fdbe4dd-2ec3-4d45-ba5f-7837c4438b80
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1325652171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.1325652171
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.776565894
Short name T1193
Test name
Test status
Simulation time 96164428931 ps
CPU time 159.01 seconds
Started Aug 07 05:58:47 PM PDT 24
Finished Aug 07 06:01:26 PM PDT 24
Peak memory 207392 kb
Host smart-255d6fd0-3016-4eec-930a-6b19a6fce030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77656
5894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.776565894
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1763582841
Short name T1099
Test name
Test status
Simulation time 213053987 ps
CPU time 1.12 seconds
Started Aug 07 05:58:46 PM PDT 24
Finished Aug 07 05:58:47 PM PDT 24
Peak memory 207168 kb
Host smart-a0afa6cc-f36a-4a6b-a409-c41fb5c3e573
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1763582841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1763582841
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3510859954
Short name T2884
Test name
Test status
Simulation time 143514963 ps
CPU time 0.8 seconds
Started Aug 07 05:58:43 PM PDT 24
Finished Aug 07 05:58:44 PM PDT 24
Peak memory 206944 kb
Host smart-c9ab6e52-69a4-43a3-b11c-51ecb0d2ab6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35108
59954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3510859954
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.678177855
Short name T2796
Test name
Test status
Simulation time 194284695 ps
CPU time 0.93 seconds
Started Aug 07 05:58:47 PM PDT 24
Finished Aug 07 05:58:48 PM PDT 24
Peak memory 206956 kb
Host smart-c403783a-d64a-4bd2-bef3-a645ce8b94e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67817
7855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.678177855
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.1733869570
Short name T2896
Test name
Test status
Simulation time 3664722187 ps
CPU time 34.85 seconds
Started Aug 07 05:58:47 PM PDT 24
Finished Aug 07 05:59:21 PM PDT 24
Peak memory 223632 kb
Host smart-835d9ca9-504a-4a67-b765-62fe7613deca
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1733869570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.1733869570
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1015137053
Short name T2889
Test name
Test status
Simulation time 158580756 ps
CPU time 0.85 seconds
Started Aug 07 05:58:50 PM PDT 24
Finished Aug 07 05:58:52 PM PDT 24
Peak memory 207028 kb
Host smart-cbae6140-dd81-41fc-ba63-50bb3bdeeed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10151
37053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1015137053
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.913049811
Short name T1135
Test name
Test status
Simulation time 5546538894 ps
CPU time 9.92 seconds
Started Aug 07 05:58:50 PM PDT 24
Finished Aug 07 05:59:01 PM PDT 24
Peak memory 215700 kb
Host smart-a156d6d9-c034-407b-b1c9-9f22b64c32d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91304
9811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.913049811
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.1923378496
Short name T1052
Test name
Test status
Simulation time 3988356331 ps
CPU time 5.68 seconds
Started Aug 07 05:58:51 PM PDT 24
Finished Aug 07 05:58:57 PM PDT 24
Peak memory 215600 kb
Host smart-d23175a5-b3cc-480b-bb65-cc69a271e572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19233
78496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1923378496
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.3675261969
Short name T2751
Test name
Test status
Simulation time 5031434653 ps
CPU time 139.08 seconds
Started Aug 07 05:58:51 PM PDT 24
Finished Aug 07 06:01:11 PM PDT 24
Peak memory 218068 kb
Host smart-9b83d689-bd7f-4fe5-93b6-d1f7febed939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36752
61969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.3675261969
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.1535175733
Short name T2748
Test name
Test status
Simulation time 2586251547 ps
CPU time 75.41 seconds
Started Aug 07 05:58:52 PM PDT 24
Finished Aug 07 06:00:07 PM PDT 24
Peak memory 216820 kb
Host smart-1e26f615-1834-40e8-8562-074c6a4f6d5d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1535175733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.1535175733
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.2421812810
Short name T1695
Test name
Test status
Simulation time 257263353 ps
CPU time 1.1 seconds
Started Aug 07 05:58:52 PM PDT 24
Finished Aug 07 05:58:53 PM PDT 24
Peak memory 206992 kb
Host smart-d0282b8d-f253-4d65-a8eb-2aa904fac682
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2421812810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.2421812810
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3922216388
Short name T509
Test name
Test status
Simulation time 235470786 ps
CPU time 0.95 seconds
Started Aug 07 05:58:52 PM PDT 24
Finished Aug 07 05:58:53 PM PDT 24
Peak memory 206988 kb
Host smart-3229e188-8435-438a-b932-986511fe99f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39222
16388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3922216388
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.865223607
Short name T1287
Test name
Test status
Simulation time 1480530986 ps
CPU time 41.81 seconds
Started Aug 07 05:58:51 PM PDT 24
Finished Aug 07 05:59:33 PM PDT 24
Peak memory 215240 kb
Host smart-e1e3de1e-5ff0-4c9f-8654-b5d552480210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86522
3607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.865223607
Directory /workspace/2.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1853097791
Short name T2724
Test name
Test status
Simulation time 3282269091 ps
CPU time 33.53 seconds
Started Aug 07 05:58:50 PM PDT 24
Finished Aug 07 05:59:23 PM PDT 24
Peak memory 223652 kb
Host smart-bd6c217c-778b-48da-b100-555041af700d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1853097791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1853097791
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.655886114
Short name T92
Test name
Test status
Simulation time 2957338213 ps
CPU time 87.35 seconds
Started Aug 07 05:58:52 PM PDT 24
Finished Aug 07 06:00:19 PM PDT 24
Peak memory 216856 kb
Host smart-7c213a9c-486c-4f2a-87f9-20665495f183
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=655886114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.655886114
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.4159668115
Short name T1793
Test name
Test status
Simulation time 153194973 ps
CPU time 0.89 seconds
Started Aug 07 05:58:52 PM PDT 24
Finished Aug 07 05:58:53 PM PDT 24
Peak memory 206900 kb
Host smart-1bfe895a-19a6-46b9-a478-73950dbc8554
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4159668115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.4159668115
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.543235320
Short name T2424
Test name
Test status
Simulation time 137718656 ps
CPU time 0.84 seconds
Started Aug 07 05:58:50 PM PDT 24
Finished Aug 07 05:58:52 PM PDT 24
Peak memory 206988 kb
Host smart-3f0b1ab9-0497-486c-b231-9254f5a9cc7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54323
5320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.543235320
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.998021233
Short name T2212
Test name
Test status
Simulation time 193527261 ps
CPU time 0.95 seconds
Started Aug 07 05:58:51 PM PDT 24
Finished Aug 07 05:58:53 PM PDT 24
Peak memory 207004 kb
Host smart-afb5672f-2313-4239-ad42-8e70f20bcf3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99802
1233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.998021233
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.360989507
Short name T2918
Test name
Test status
Simulation time 193338156 ps
CPU time 0.99 seconds
Started Aug 07 05:58:53 PM PDT 24
Finished Aug 07 05:58:54 PM PDT 24
Peak memory 206980 kb
Host smart-24204c06-fa92-4742-9c4d-e96d38cf5eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36098
9507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.360989507
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1710578136
Short name T630
Test name
Test status
Simulation time 179137799 ps
CPU time 0.93 seconds
Started Aug 07 05:58:53 PM PDT 24
Finished Aug 07 05:58:54 PM PDT 24
Peak memory 206980 kb
Host smart-bb5b8839-7752-4e53-967f-0e431f88e32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17105
78136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1710578136
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2420363968
Short name T2806
Test name
Test status
Simulation time 176906132 ps
CPU time 0.87 seconds
Started Aug 07 05:58:54 PM PDT 24
Finished Aug 07 05:58:55 PM PDT 24
Peak memory 206956 kb
Host smart-70a1ccbc-8395-43d7-99c8-72f6fb86f099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24203
63968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2420363968
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3943092208
Short name T2717
Test name
Test status
Simulation time 213554297 ps
CPU time 0.88 seconds
Started Aug 07 05:58:50 PM PDT 24
Finished Aug 07 05:58:52 PM PDT 24
Peak memory 206944 kb
Host smart-c44e867f-adf3-407c-8a34-5e8fc8711dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39430
92208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3943092208
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.113852269
Short name T2552
Test name
Test status
Simulation time 227626598 ps
CPU time 1.02 seconds
Started Aug 07 05:58:53 PM PDT 24
Finished Aug 07 05:58:54 PM PDT 24
Peak memory 206996 kb
Host smart-f53fff4e-d09a-46f3-9326-4f2aef1f1a2d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=113852269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.113852269
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.3009297078
Short name T2817
Test name
Test status
Simulation time 243915337 ps
CPU time 1.11 seconds
Started Aug 07 05:58:53 PM PDT 24
Finished Aug 07 05:58:54 PM PDT 24
Peak memory 206980 kb
Host smart-bfc1db1c-fe3f-41b8-b9f0-b0b20f922222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30092
97078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.3009297078
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1201783043
Short name T978
Test name
Test status
Simulation time 149240214 ps
CPU time 0.86 seconds
Started Aug 07 05:58:51 PM PDT 24
Finished Aug 07 05:58:52 PM PDT 24
Peak memory 206960 kb
Host smart-9318ea52-81e5-4366-9c51-a45c3211bdf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12017
83043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1201783043
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3268083514
Short name T2609
Test name
Test status
Simulation time 61815099 ps
CPU time 0.76 seconds
Started Aug 07 05:58:55 PM PDT 24
Finished Aug 07 05:58:56 PM PDT 24
Peak memory 206972 kb
Host smart-7c554b89-c4f5-419f-b095-14ecf5393f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32680
83514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3268083514
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1595432509
Short name T2646
Test name
Test status
Simulation time 21743410577 ps
CPU time 59.18 seconds
Started Aug 07 05:58:56 PM PDT 24
Finished Aug 07 05:59:55 PM PDT 24
Peak memory 220140 kb
Host smart-ac10acc8-7d7f-480f-824e-50c6e0c063c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15954
32509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1595432509
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3655511398
Short name T2663
Test name
Test status
Simulation time 155886819 ps
CPU time 0.84 seconds
Started Aug 07 05:58:58 PM PDT 24
Finished Aug 07 05:58:59 PM PDT 24
Peak memory 207016 kb
Host smart-e84bde6e-9e67-4865-acd5-5b03d0bec585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36555
11398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3655511398
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1237885456
Short name T2095
Test name
Test status
Simulation time 176787042 ps
CPU time 0.89 seconds
Started Aug 07 05:58:59 PM PDT 24
Finished Aug 07 05:59:00 PM PDT 24
Peak memory 206904 kb
Host smart-0b3faaf7-02fe-4b39-a9fa-e3caa314b425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
85456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1237885456
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3858685634
Short name T1929
Test name
Test status
Simulation time 7278082263 ps
CPU time 211.76 seconds
Started Aug 07 05:58:57 PM PDT 24
Finished Aug 07 06:02:29 PM PDT 24
Peak memory 223824 kb
Host smart-82f9da0e-f2d1-4ed6-9b04-6a956670a8ac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858685634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3858685634
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2598346633
Short name T1943
Test name
Test status
Simulation time 4327661696 ps
CPU time 31.82 seconds
Started Aug 07 05:58:56 PM PDT 24
Finished Aug 07 05:59:28 PM PDT 24
Peak memory 216300 kb
Host smart-d9e6a248-72e8-4e88-87c3-f05229d50a3b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2598346633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2598346633
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2874863829
Short name T2275
Test name
Test status
Simulation time 9164426413 ps
CPU time 157.36 seconds
Started Aug 07 05:58:57 PM PDT 24
Finished Aug 07 06:01:34 PM PDT 24
Peak memory 217980 kb
Host smart-384e7c5c-5252-4dc7-af09-45201d823ba0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874863829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2874863829
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.293051206
Short name T787
Test name
Test status
Simulation time 174805895 ps
CPU time 0.89 seconds
Started Aug 07 05:58:55 PM PDT 24
Finished Aug 07 05:58:56 PM PDT 24
Peak memory 206924 kb
Host smart-71b75658-efd8-4719-bd61-ac100a510ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29305
1206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.293051206
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.3914816357
Short name T2331
Test name
Test status
Simulation time 191161428 ps
CPU time 0.95 seconds
Started Aug 07 05:58:56 PM PDT 24
Finished Aug 07 05:58:57 PM PDT 24
Peak memory 206996 kb
Host smart-b071007a-3139-4536-9625-417ae0802186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39148
16357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.3914816357
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_resume_link_active.680279028
Short name T625
Test name
Test status
Simulation time 20151839554 ps
CPU time 23.49 seconds
Started Aug 07 05:59:10 PM PDT 24
Finished Aug 07 05:59:33 PM PDT 24
Peak memory 207080 kb
Host smart-12419f5e-d1fe-42e1-8e2c-fede8d93b7d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68027
9028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.680279028
Directory /workspace/2.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3077673690
Short name T1969
Test name
Test status
Simulation time 165398711 ps
CPU time 0.89 seconds
Started Aug 07 05:59:00 PM PDT 24
Finished Aug 07 05:59:01 PM PDT 24
Peak memory 206904 kb
Host smart-ba7cbc90-59e3-4bcf-b5a8-9ecbe706ef10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30776
73690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3077673690
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_full.3365127449
Short name T1710
Test name
Test status
Simulation time 262900037 ps
CPU time 1.1 seconds
Started Aug 07 05:59:00 PM PDT 24
Finished Aug 07 05:59:02 PM PDT 24
Peak memory 206904 kb
Host smart-1ac874f7-3baa-49bf-a2cb-a4db3970f3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33651
27449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.3365127449
Directory /workspace/2.usbdev_rx_full/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.3981573150
Short name T77
Test name
Test status
Simulation time 196298018 ps
CPU time 0.92 seconds
Started Aug 07 05:58:55 PM PDT 24
Finished Aug 07 05:58:57 PM PDT 24
Peak memory 206984 kb
Host smart-26d137ff-beb4-4a51-ad80-853581d12c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39815
73150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.3981573150
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3252558138
Short name T229
Test name
Test status
Simulation time 490131568 ps
CPU time 1.33 seconds
Started Aug 07 05:59:04 PM PDT 24
Finished Aug 07 05:59:05 PM PDT 24
Peak memory 224112 kb
Host smart-aa55b519-eba5-4143-9881-66cbc9ae1e6e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3252558138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3252558138
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.1761144072
Short name T45
Test name
Test status
Simulation time 449012951 ps
CPU time 1.42 seconds
Started Aug 07 05:58:55 PM PDT 24
Finished Aug 07 05:58:57 PM PDT 24
Peak memory 206976 kb
Host smart-aea8aaf6-f022-4f00-b1ab-613ed25bed4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17611
44072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1761144072
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.912614407
Short name T199
Test name
Test status
Simulation time 176973386 ps
CPU time 0.92 seconds
Started Aug 07 05:58:58 PM PDT 24
Finished Aug 07 05:58:59 PM PDT 24
Peak memory 207012 kb
Host smart-53504cb9-9f61-4cfa-b8b2-7efc047e99c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91261
4407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.912614407
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1213655345
Short name T1308
Test name
Test status
Simulation time 243936777 ps
CPU time 0.88 seconds
Started Aug 07 05:58:54 PM PDT 24
Finished Aug 07 05:58:55 PM PDT 24
Peak memory 206956 kb
Host smart-0423edec-686e-4802-8799-eb5c93e65da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12136
55345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1213655345
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.422744299
Short name T733
Test name
Test status
Simulation time 150881708 ps
CPU time 0.89 seconds
Started Aug 07 05:58:57 PM PDT 24
Finished Aug 07 05:58:59 PM PDT 24
Peak memory 207012 kb
Host smart-aad625f6-361f-40a5-ae30-2c09444e9933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42274
4299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.422744299
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.285243926
Short name T680
Test name
Test status
Simulation time 214081158 ps
CPU time 1.11 seconds
Started Aug 07 05:59:01 PM PDT 24
Finished Aug 07 05:59:02 PM PDT 24
Peak memory 206904 kb
Host smart-61871848-6810-4be5-9d99-efaed70d3eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28524
3926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.285243926
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1966101520
Short name T2713
Test name
Test status
Simulation time 2055065524 ps
CPU time 20.46 seconds
Started Aug 07 05:59:03 PM PDT 24
Finished Aug 07 05:59:23 PM PDT 24
Peak memory 216868 kb
Host smart-5de5a8ab-64df-487d-bf36-4a71eca1902d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1966101520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1966101520
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2631205208
Short name T2030
Test name
Test status
Simulation time 163992523 ps
CPU time 0.87 seconds
Started Aug 07 05:59:02 PM PDT 24
Finished Aug 07 05:59:03 PM PDT 24
Peak memory 206888 kb
Host smart-dafe679a-0dca-45f1-a4ca-d39db4fb81fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26312
05208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2631205208
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2194122475
Short name T1491
Test name
Test status
Simulation time 226873253 ps
CPU time 1 seconds
Started Aug 07 05:59:01 PM PDT 24
Finished Aug 07 05:59:03 PM PDT 24
Peak memory 206984 kb
Host smart-0d0172fd-c8eb-4590-b18c-b0b544142cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21941
22475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2194122475
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.946314689
Short name T2530
Test name
Test status
Simulation time 730655336 ps
CPU time 1.85 seconds
Started Aug 07 05:59:02 PM PDT 24
Finished Aug 07 05:59:04 PM PDT 24
Peak memory 206956 kb
Host smart-478212d4-fe48-4171-adfe-0f2378973489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94631
4689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.946314689
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.841289513
Short name T1216
Test name
Test status
Simulation time 2798424642 ps
CPU time 81.44 seconds
Started Aug 07 05:59:03 PM PDT 24
Finished Aug 07 06:00:25 PM PDT 24
Peak memory 215376 kb
Host smart-8d66a94f-c1fb-4a10-8780-6c7167e7e12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84128
9513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.841289513
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2316206143
Short name T79
Test name
Test status
Simulation time 8543989164 ps
CPU time 43.58 seconds
Started Aug 07 05:59:02 PM PDT 24
Finished Aug 07 05:59:46 PM PDT 24
Peak memory 223140 kb
Host smart-4f8330c4-5050-4687-a047-548fb08af438
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316206143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2316206143
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.3838066726
Short name T1036
Test name
Test status
Simulation time 4315328725 ps
CPU time 29.04 seconds
Started Aug 07 05:58:41 PM PDT 24
Finished Aug 07 05:59:10 PM PDT 24
Peak memory 207268 kb
Host smart-65ca0f83-5144-4c75-9da5-07536ef5ab81
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838066726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.3838066726
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.1600448728
Short name T3121
Test name
Test status
Simulation time 43024118 ps
CPU time 0.65 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:02:52 PM PDT 24
Peak memory 207064 kb
Host smart-0b720fad-0174-4b87-ae54-0f3472ac2289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1600448728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.1600448728
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2258335536
Short name T1753
Test name
Test status
Simulation time 11641899555 ps
CPU time 14.21 seconds
Started Aug 07 06:02:44 PM PDT 24
Finished Aug 07 06:02:58 PM PDT 24
Peak memory 207312 kb
Host smart-f55feb77-3804-425a-a80f-5c547230ad83
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258335536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_disconnect.2258335536
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.344515337
Short name T2669
Test name
Test status
Simulation time 16280408253 ps
CPU time 17.58 seconds
Started Aug 07 06:02:31 PM PDT 24
Finished Aug 07 06:02:49 PM PDT 24
Peak memory 215488 kb
Host smart-712ef447-3032-4116-92ce-766c30b7dc9b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=344515337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.344515337
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.989510703
Short name T2837
Test name
Test status
Simulation time 24203292587 ps
CPU time 31.42 seconds
Started Aug 07 06:02:32 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 215456 kb
Host smart-2c376ef3-04cc-49a6-aab1-0790c024a31f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989510703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_ao
n_wake_resume.989510703
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2869730607
Short name T2687
Test name
Test status
Simulation time 225949334 ps
CPU time 0.91 seconds
Started Aug 07 06:02:33 PM PDT 24
Finished Aug 07 06:02:34 PM PDT 24
Peak memory 207016 kb
Host smart-712de9a8-3a4d-4a47-88eb-aeb72786d80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28697
30607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2869730607
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.285395140
Short name T1516
Test name
Test status
Simulation time 151566994 ps
CPU time 0.84 seconds
Started Aug 07 06:02:35 PM PDT 24
Finished Aug 07 06:02:35 PM PDT 24
Peak memory 206976 kb
Host smart-3df1fe1e-37e2-4e57-affc-1b1e73a1ddb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28539
5140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.285395140
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2918419043
Short name T96
Test name
Test status
Simulation time 446264153 ps
CPU time 1.56 seconds
Started Aug 07 06:02:34 PM PDT 24
Finished Aug 07 06:02:36 PM PDT 24
Peak memory 206968 kb
Host smart-139316ea-3df2-42c8-90fb-6386ab8f6f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29184
19043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2918419043
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1969421213
Short name T3027
Test name
Test status
Simulation time 938835075 ps
CPU time 2.69 seconds
Started Aug 07 06:02:33 PM PDT 24
Finished Aug 07 06:02:36 PM PDT 24
Peak memory 207172 kb
Host smart-00ff323f-f6f7-459c-a9e5-00c32d78575b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1969421213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1969421213
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.2448670121
Short name T2516
Test name
Test status
Simulation time 32845774525 ps
CPU time 55.51 seconds
Started Aug 07 06:02:33 PM PDT 24
Finished Aug 07 06:03:29 PM PDT 24
Peak memory 207268 kb
Host smart-3d77eee7-fcb1-4f7f-a5b6-9aca4bc81503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24486
70121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.2448670121
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.1409587689
Short name T1323
Test name
Test status
Simulation time 1681525148 ps
CPU time 39.25 seconds
Started Aug 07 06:02:32 PM PDT 24
Finished Aug 07 06:03:12 PM PDT 24
Peak memory 207136 kb
Host smart-68efea50-c193-4982-869e-9da8529b0ecf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409587689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.1409587689
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.991164413
Short name T1501
Test name
Test status
Simulation time 595196554 ps
CPU time 1.7 seconds
Started Aug 07 06:02:44 PM PDT 24
Finished Aug 07 06:02:46 PM PDT 24
Peak memory 207160 kb
Host smart-8ee842dd-41a1-4ca0-a1a6-bf2b943e1716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99116
4413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.991164413
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1960896727
Short name T2311
Test name
Test status
Simulation time 160040402 ps
CPU time 0.91 seconds
Started Aug 07 06:02:39 PM PDT 24
Finished Aug 07 06:02:40 PM PDT 24
Peak memory 206924 kb
Host smart-3a73b3f0-2951-432c-9535-110039adf1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19608
96727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1960896727
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1549481029
Short name T887
Test name
Test status
Simulation time 58295917 ps
CPU time 0.71 seconds
Started Aug 07 06:02:48 PM PDT 24
Finished Aug 07 06:02:49 PM PDT 24
Peak memory 206972 kb
Host smart-b55db852-9d9d-4e42-9253-806369d70b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15494
81029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1549481029
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2788244569
Short name T741
Test name
Test status
Simulation time 853241696 ps
CPU time 2.34 seconds
Started Aug 07 06:02:40 PM PDT 24
Finished Aug 07 06:02:42 PM PDT 24
Peak memory 207096 kb
Host smart-453d1414-99e9-45bf-b3fc-50a7b73c7970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27882
44569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2788244569
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_types.171092716
Short name T467
Test name
Test status
Simulation time 570770747 ps
CPU time 1.55 seconds
Started Aug 07 06:02:39 PM PDT 24
Finished Aug 07 06:02:41 PM PDT 24
Peak memory 206964 kb
Host smart-6c064510-ab28-41ef-adc0-60551ca07a49
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=171092716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.171092716
Directory /workspace/20.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1374220141
Short name T202
Test name
Test status
Simulation time 263721101 ps
CPU time 1.88 seconds
Started Aug 07 06:02:39 PM PDT 24
Finished Aug 07 06:02:41 PM PDT 24
Peak memory 207072 kb
Host smart-50a727fe-e66a-464f-a22a-06390293fee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13742
20141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1374220141
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3438395976
Short name T2171
Test name
Test status
Simulation time 189215545 ps
CPU time 1.01 seconds
Started Aug 07 06:02:50 PM PDT 24
Finished Aug 07 06:02:51 PM PDT 24
Peak memory 207152 kb
Host smart-b895b570-6545-4814-b350-8e24ceaa06ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3438395976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3438395976
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1018837015
Short name T975
Test name
Test status
Simulation time 186573636 ps
CPU time 0.98 seconds
Started Aug 07 06:02:49 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 206968 kb
Host smart-c9ac0e1a-f0e6-4ef6-86c2-26d58e10ce0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10188
37015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1018837015
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3449370497
Short name T816
Test name
Test status
Simulation time 189315603 ps
CPU time 0.95 seconds
Started Aug 07 06:02:48 PM PDT 24
Finished Aug 07 06:02:49 PM PDT 24
Peak memory 207016 kb
Host smart-05c30fb1-4b4f-4299-957c-2f461c68d41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34493
70497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3449370497
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.1102836668
Short name T1557
Test name
Test status
Simulation time 4182060136 ps
CPU time 30.5 seconds
Started Aug 07 06:02:41 PM PDT 24
Finished Aug 07 06:03:11 PM PDT 24
Peak memory 215484 kb
Host smart-ea79dbd8-1262-478e-b6bb-b426e09abbf3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1102836668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.1102836668
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.3925331334
Short name T2060
Test name
Test status
Simulation time 5019890643 ps
CPU time 57.32 seconds
Started Aug 07 06:02:47 PM PDT 24
Finished Aug 07 06:03:44 PM PDT 24
Peak memory 207240 kb
Host smart-87731655-d2c3-4a70-bf6e-8e519ff2df36
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3925331334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.3925331334
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3482596447
Short name T1033
Test name
Test status
Simulation time 192391935 ps
CPU time 0.96 seconds
Started Aug 07 06:02:40 PM PDT 24
Finished Aug 07 06:02:41 PM PDT 24
Peak memory 206988 kb
Host smart-edd6f11e-1aa4-4e2e-ad57-343941c13b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34825
96447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3482596447
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.1993364261
Short name T2849
Test name
Test status
Simulation time 30301197066 ps
CPU time 46.04 seconds
Started Aug 07 06:02:44 PM PDT 24
Finished Aug 07 06:03:30 PM PDT 24
Peak memory 207528 kb
Host smart-885826bf-d60d-4753-a79b-ec371f3e2f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19933
64261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.1993364261
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.1741580012
Short name T2168
Test name
Test status
Simulation time 10257303244 ps
CPU time 12.55 seconds
Started Aug 07 06:02:42 PM PDT 24
Finished Aug 07 06:02:55 PM PDT 24
Peak memory 207224 kb
Host smart-6ff86901-c384-4a22-84ec-29e08deb89d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17415
80012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1741580012
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.2654356108
Short name T317
Test name
Test status
Simulation time 5471633871 ps
CPU time 54.89 seconds
Started Aug 07 06:02:41 PM PDT 24
Finished Aug 07 06:03:36 PM PDT 24
Peak memory 218264 kb
Host smart-83d99221-b703-4caf-9ff9-cd541c0a9a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26543
56108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.2654356108
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2252546458
Short name T2188
Test name
Test status
Simulation time 1844737485 ps
CPU time 14.59 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:03:06 PM PDT 24
Peak memory 223532 kb
Host smart-b9f9edaa-b2f7-4bea-b129-4605d270d5ee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2252546458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2252546458
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1184385227
Short name T1187
Test name
Test status
Simulation time 263505092 ps
CPU time 1.06 seconds
Started Aug 07 06:02:41 PM PDT 24
Finished Aug 07 06:02:42 PM PDT 24
Peak memory 206936 kb
Host smart-b926aaf4-6c21-4c6b-a835-5cad9b40c4d6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1184385227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1184385227
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.922636989
Short name T2548
Test name
Test status
Simulation time 183170978 ps
CPU time 0.91 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:02:52 PM PDT 24
Peak memory 206988 kb
Host smart-f95c6f84-dd30-4f2e-94e4-b6a6d74ad5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92263
6989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.922636989
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.423906214
Short name T2980
Test name
Test status
Simulation time 2981536147 ps
CPU time 88.65 seconds
Started Aug 07 06:02:47 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 217144 kb
Host smart-182fc6c3-f8b0-4b65-8bbc-6415a74ab405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42390
6214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.423906214
Directory /workspace/20.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1888782813
Short name T1751
Test name
Test status
Simulation time 2411373293 ps
CPU time 68.86 seconds
Started Aug 07 06:02:47 PM PDT 24
Finished Aug 07 06:03:56 PM PDT 24
Peak memory 216984 kb
Host smart-99c8fd85-ecaf-48f0-923d-fc5fd7ad30af
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1888782813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1888782813
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.775390029
Short name T1117
Test name
Test status
Simulation time 206755834 ps
CPU time 0.96 seconds
Started Aug 07 06:02:41 PM PDT 24
Finished Aug 07 06:02:42 PM PDT 24
Peak memory 206904 kb
Host smart-c3f4ae41-1216-45db-87cf-73cf1bcdb619
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=775390029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.775390029
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3958768497
Short name T503
Test name
Test status
Simulation time 144945684 ps
CPU time 0.82 seconds
Started Aug 07 06:02:48 PM PDT 24
Finished Aug 07 06:02:49 PM PDT 24
Peak memory 206992 kb
Host smart-75e9f4a8-846b-4ae7-b33b-140c7e363b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39587
68497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3958768497
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3381241566
Short name T163
Test name
Test status
Simulation time 180395207 ps
CPU time 0.9 seconds
Started Aug 07 06:02:38 PM PDT 24
Finished Aug 07 06:02:39 PM PDT 24
Peak memory 206980 kb
Host smart-285f7bf7-35a2-4c53-b9f4-ba9378d5fc6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33812
41566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3381241566
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.91286326
Short name T566
Test name
Test status
Simulation time 166744743 ps
CPU time 0.91 seconds
Started Aug 07 06:02:44 PM PDT 24
Finished Aug 07 06:02:45 PM PDT 24
Peak memory 207216 kb
Host smart-91cbd139-b44c-46cc-83d3-b72a848aabd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91286
326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.91286326
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2920245149
Short name T2019
Test name
Test status
Simulation time 162640393 ps
CPU time 0.92 seconds
Started Aug 07 06:02:47 PM PDT 24
Finished Aug 07 06:02:48 PM PDT 24
Peak memory 206904 kb
Host smart-f6f2b09e-1894-40e2-82a4-9d020e98b109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29202
45149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2920245149
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1091738344
Short name T1983
Test name
Test status
Simulation time 230427483 ps
CPU time 0.9 seconds
Started Aug 07 06:02:40 PM PDT 24
Finished Aug 07 06:02:41 PM PDT 24
Peak memory 206972 kb
Host smart-c35679b2-5202-4507-a221-0ba4f14af95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10917
38344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1091738344
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2189702050
Short name T1392
Test name
Test status
Simulation time 164587298 ps
CPU time 0.9 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:02:52 PM PDT 24
Peak memory 206980 kb
Host smart-7d92b116-4cb9-4fae-b521-ee2ea8c7665d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21897
02050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2189702050
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2281891408
Short name T2049
Test name
Test status
Simulation time 240204526 ps
CPU time 1.11 seconds
Started Aug 07 06:02:45 PM PDT 24
Finished Aug 07 06:02:47 PM PDT 24
Peak memory 206884 kb
Host smart-6788f7f2-6cb1-4371-996f-a3121b261a9e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2281891408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2281891408
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.4051024182
Short name T2762
Test name
Test status
Simulation time 158290056 ps
CPU time 0.86 seconds
Started Aug 07 06:02:47 PM PDT 24
Finished Aug 07 06:02:48 PM PDT 24
Peak memory 206984 kb
Host smart-a016b463-4178-4d7e-b68a-69956c0f9da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40510
24182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.4051024182
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2053893780
Short name T24
Test name
Test status
Simulation time 43556623 ps
CPU time 0.69 seconds
Started Aug 07 06:02:47 PM PDT 24
Finished Aug 07 06:02:48 PM PDT 24
Peak memory 206952 kb
Host smart-eb151239-f889-45cc-8aa1-0ebce0653f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20538
93780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2053893780
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.2353180544
Short name T2703
Test name
Test status
Simulation time 11127008468 ps
CPU time 30.35 seconds
Started Aug 07 06:02:46 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 215464 kb
Host smart-2687123d-13f7-4751-be0b-3d6df0a28b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23531
80544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.2353180544
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2508469938
Short name T571
Test name
Test status
Simulation time 159546640 ps
CPU time 0.86 seconds
Started Aug 07 06:02:52 PM PDT 24
Finished Aug 07 06:02:53 PM PDT 24
Peak memory 206988 kb
Host smart-d1bf8399-dbc0-4721-886c-0e1f21d700d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
69938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2508469938
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3163768697
Short name T1766
Test name
Test status
Simulation time 282050283 ps
CPU time 1.06 seconds
Started Aug 07 06:02:48 PM PDT 24
Finished Aug 07 06:02:49 PM PDT 24
Peak memory 207016 kb
Host smart-cd4d5517-28c2-4f9d-8352-a8037180490f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31637
68697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3163768697
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3258914568
Short name T2136
Test name
Test status
Simulation time 236713807 ps
CPU time 0.97 seconds
Started Aug 07 06:02:45 PM PDT 24
Finished Aug 07 06:02:46 PM PDT 24
Peak memory 206988 kb
Host smart-e43f0ea0-f282-4cc5-960a-2f3a0bbb27e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32589
14568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3258914568
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.2874210649
Short name T249
Test name
Test status
Simulation time 183203544 ps
CPU time 0.95 seconds
Started Aug 07 06:02:50 PM PDT 24
Finished Aug 07 06:02:52 PM PDT 24
Peak memory 207016 kb
Host smart-1b2be6df-ca3b-49bd-8785-1b6cc1b94baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28742
10649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.2874210649
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3552149813
Short name T2058
Test name
Test status
Simulation time 169881549 ps
CPU time 0.91 seconds
Started Aug 07 06:02:56 PM PDT 24
Finished Aug 07 06:02:57 PM PDT 24
Peak memory 207008 kb
Host smart-89c18db3-9f19-4d14-9d07-8f42386fb060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35521
49813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3552149813
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_rx_full.3479128375
Short name T1863
Test name
Test status
Simulation time 328081132 ps
CPU time 1.1 seconds
Started Aug 07 06:02:46 PM PDT 24
Finished Aug 07 06:02:47 PM PDT 24
Peak memory 206940 kb
Host smart-2d874539-0622-4e45-a07e-e014bdf2b766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34791
28375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.3479128375
Directory /workspace/20.usbdev_rx_full/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3285386455
Short name T1093
Test name
Test status
Simulation time 149901493 ps
CPU time 0.82 seconds
Started Aug 07 06:02:47 PM PDT 24
Finished Aug 07 06:02:48 PM PDT 24
Peak memory 206968 kb
Host smart-fb35c41c-8d18-45dc-9a6c-7953129f0764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32853
86455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3285386455
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.314032962
Short name T2826
Test name
Test status
Simulation time 149430432 ps
CPU time 0.85 seconds
Started Aug 07 06:02:50 PM PDT 24
Finished Aug 07 06:02:51 PM PDT 24
Peak memory 206912 kb
Host smart-8b45cd83-a9ea-4b6a-af18-dbc7beb0053f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31403
2962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.314032962
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1204974245
Short name T742
Test name
Test status
Simulation time 204322385 ps
CPU time 1.04 seconds
Started Aug 07 06:02:49 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 206912 kb
Host smart-26e1c510-ebf3-4d9a-960f-cbbaf767632a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12049
74245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1204974245
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1680055431
Short name T2831
Test name
Test status
Simulation time 3040254676 ps
CPU time 86.87 seconds
Started Aug 07 06:02:46 PM PDT 24
Finished Aug 07 06:04:13 PM PDT 24
Peak memory 223704 kb
Host smart-c689341d-4170-4b24-bae5-88128c0f1e7e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1680055431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1680055431
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2714669260
Short name T2478
Test name
Test status
Simulation time 161504408 ps
CPU time 0.85 seconds
Started Aug 07 06:02:52 PM PDT 24
Finished Aug 07 06:02:53 PM PDT 24
Peak memory 206980 kb
Host smart-2b030f4b-2311-4167-bb65-5b2126f9d0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27146
69260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2714669260
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1172911994
Short name T2787
Test name
Test status
Simulation time 187916666 ps
CPU time 0.99 seconds
Started Aug 07 06:02:49 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 207012 kb
Host smart-96ce1076-db26-4c63-bf57-0b4e1455417c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11729
11994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1172911994
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.1282584262
Short name T2589
Test name
Test status
Simulation time 1190381442 ps
CPU time 2.59 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:02:54 PM PDT 24
Peak memory 207176 kb
Host smart-17d1e6e5-5447-407d-97f3-7a8455fe3099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12825
84262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.1282584262
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.305882164
Short name T2343
Test name
Test status
Simulation time 4214719667 ps
CPU time 32.12 seconds
Started Aug 07 06:02:50 PM PDT 24
Finished Aug 07 06:03:22 PM PDT 24
Peak memory 215548 kb
Host smart-2bfc2d53-5c66-4d66-a564-90a753519d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30588
2164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.305882164
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.3880441784
Short name T2369
Test name
Test status
Simulation time 5533647817 ps
CPU time 37.14 seconds
Started Aug 07 06:02:49 PM PDT 24
Finished Aug 07 06:03:26 PM PDT 24
Peak memory 207244 kb
Host smart-6e11d092-efdb-4752-81ca-999647f93d92
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880441784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.3880441784
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.3440390585
Short name T1302
Test name
Test status
Simulation time 77703130 ps
CPU time 0.71 seconds
Started Aug 07 06:02:59 PM PDT 24
Finished Aug 07 06:03:00 PM PDT 24
Peak memory 207100 kb
Host smart-4de5eafa-c968-4cbf-a060-ab342aba0274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3440390585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.3440390585
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.1959406840
Short name T1598
Test name
Test status
Simulation time 9865971019 ps
CPU time 12.18 seconds
Started Aug 07 06:02:50 PM PDT 24
Finished Aug 07 06:03:02 PM PDT 24
Peak memory 207184 kb
Host smart-5cc2f7e6-76a2-4f37-9a9b-d2eb300f3416
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959406840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.1959406840
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2105841799
Short name T2435
Test name
Test status
Simulation time 19627659063 ps
CPU time 20.78 seconds
Started Aug 07 06:02:46 PM PDT 24
Finished Aug 07 06:03:07 PM PDT 24
Peak memory 207196 kb
Host smart-9ed4d458-c9b7-4678-bb6a-b3da030be2a6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105841799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2105841799
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.3533138365
Short name T1115
Test name
Test status
Simulation time 23660279962 ps
CPU time 29.8 seconds
Started Aug 07 06:02:53 PM PDT 24
Finished Aug 07 06:03:23 PM PDT 24
Peak memory 215452 kb
Host smart-6c427581-3920-4f69-8fee-fc7ec50dc909
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533138365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.3533138365
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2600409659
Short name T2035
Test name
Test status
Simulation time 161106273 ps
CPU time 0.88 seconds
Started Aug 07 06:02:46 PM PDT 24
Finished Aug 07 06:02:47 PM PDT 24
Peak memory 206968 kb
Host smart-e61e131e-0ddd-42a5-b14d-bed658ce0061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26004
09659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2600409659
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3407981868
Short name T2211
Test name
Test status
Simulation time 162106734 ps
CPU time 0.84 seconds
Started Aug 07 06:02:48 PM PDT 24
Finished Aug 07 06:02:49 PM PDT 24
Peak memory 206952 kb
Host smart-a0318436-b02c-4cb9-b611-f31ee10a0348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34079
81868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3407981868
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2123076462
Short name T719
Test name
Test status
Simulation time 303899689 ps
CPU time 1.14 seconds
Started Aug 07 06:02:56 PM PDT 24
Finished Aug 07 06:02:57 PM PDT 24
Peak memory 206984 kb
Host smart-0fb783bf-f864-492f-824b-cb0c1cddb399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21230
76462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2123076462
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2131623954
Short name T1844
Test name
Test status
Simulation time 999911032 ps
CPU time 2.64 seconds
Started Aug 07 06:02:46 PM PDT 24
Finished Aug 07 06:02:49 PM PDT 24
Peak memory 207176 kb
Host smart-1ea40df6-a8bf-4963-8a66-292083f4ec67
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2131623954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2131623954
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3098595450
Short name T2813
Test name
Test status
Simulation time 32232642458 ps
CPU time 45.02 seconds
Started Aug 07 06:02:47 PM PDT 24
Finished Aug 07 06:03:33 PM PDT 24
Peak memory 207172 kb
Host smart-53f7d1f6-527c-42c8-b0f2-f88cbadc21b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30985
95450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3098595450
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.1794772802
Short name T945
Test name
Test status
Simulation time 507969195 ps
CPU time 8.4 seconds
Started Aug 07 06:02:47 PM PDT 24
Finished Aug 07 06:02:56 PM PDT 24
Peak memory 207160 kb
Host smart-6365bb27-cf63-42a0-8a3b-67c3e32fc5c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794772802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.1794772802
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3755575102
Short name T1361
Test name
Test status
Simulation time 635648705 ps
CPU time 1.83 seconds
Started Aug 07 06:02:52 PM PDT 24
Finished Aug 07 06:02:54 PM PDT 24
Peak memory 206948 kb
Host smart-543955d9-03bb-4ed5-967b-790f2b002d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555
75102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3755575102
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1481130417
Short name T1521
Test name
Test status
Simulation time 206773363 ps
CPU time 0.87 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:02:52 PM PDT 24
Peak memory 206988 kb
Host smart-afd208be-5d37-4269-9946-5eaac6563951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14811
30417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1481130417
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2081546840
Short name T2123
Test name
Test status
Simulation time 50925531 ps
CPU time 0.69 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:02:51 PM PDT 24
Peak memory 206936 kb
Host smart-6e54127f-a642-4beb-96f9-ff13b0b118f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20815
46840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2081546840
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1899112424
Short name T1675
Test name
Test status
Simulation time 887722711 ps
CPU time 2.31 seconds
Started Aug 07 06:02:46 PM PDT 24
Finished Aug 07 06:02:48 PM PDT 24
Peak memory 207096 kb
Host smart-53ea06f2-d2ec-4400-ac82-62417984f22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18991
12424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1899112424
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3323528188
Short name T1721
Test name
Test status
Simulation time 326234749 ps
CPU time 2.68 seconds
Started Aug 07 06:02:50 PM PDT 24
Finished Aug 07 06:02:52 PM PDT 24
Peak memory 207164 kb
Host smart-055c2a38-5c9f-498f-a683-e816972f3299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33235
28188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3323528188
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1779674991
Short name T239
Test name
Test status
Simulation time 221498627 ps
CPU time 1.07 seconds
Started Aug 07 06:02:50 PM PDT 24
Finished Aug 07 06:02:51 PM PDT 24
Peak memory 207164 kb
Host smart-966ba1a8-5735-43a5-a24f-341e80642103
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1779674991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1779674991
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1957101243
Short name T2898
Test name
Test status
Simulation time 144442877 ps
CPU time 0.83 seconds
Started Aug 07 06:02:49 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 206944 kb
Host smart-188483cf-5db9-458c-9a9a-66081519cb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19571
01243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1957101243
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1432900757
Short name T668
Test name
Test status
Simulation time 254650813 ps
CPU time 1.04 seconds
Started Aug 07 06:02:49 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 206960 kb
Host smart-9e291704-5912-4cee-9ab7-30947ea7985e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14329
00757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1432900757
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.3178076804
Short name T920
Test name
Test status
Simulation time 5020221971 ps
CPU time 46.68 seconds
Started Aug 07 06:02:52 PM PDT 24
Finished Aug 07 06:03:39 PM PDT 24
Peak memory 223660 kb
Host smart-68626c88-8e14-480c-9e5a-9de197f724fd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3178076804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.3178076804
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.1877114449
Short name T1394
Test name
Test status
Simulation time 9848766235 ps
CPU time 74.07 seconds
Started Aug 07 06:02:47 PM PDT 24
Finished Aug 07 06:04:01 PM PDT 24
Peak memory 207240 kb
Host smart-1320ff4b-6b04-4811-9d4f-ffa2d5baa237
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1877114449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.1877114449
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1717973681
Short name T1331
Test name
Test status
Simulation time 204038902 ps
CPU time 0.94 seconds
Started Aug 07 06:02:50 PM PDT 24
Finished Aug 07 06:02:52 PM PDT 24
Peak memory 206984 kb
Host smart-24cdb9f4-a654-4b63-915a-8e502adc114a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17179
73681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1717973681
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.3928886977
Short name T2725
Test name
Test status
Simulation time 31507276716 ps
CPU time 48.88 seconds
Started Aug 07 06:02:49 PM PDT 24
Finished Aug 07 06:03:38 PM PDT 24
Peak memory 207292 kb
Host smart-24907b86-f310-43e1-89b0-8f1e3460c462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39288
86977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.3928886977
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.2516407059
Short name T725
Test name
Test status
Simulation time 10593830942 ps
CPU time 12.92 seconds
Started Aug 07 06:02:46 PM PDT 24
Finished Aug 07 06:02:59 PM PDT 24
Peak memory 207292 kb
Host smart-8210ae1a-8977-4002-aba7-a76b355f74a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25164
07059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.2516407059
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.223257676
Short name T1872
Test name
Test status
Simulation time 2756476294 ps
CPU time 20.68 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:03:12 PM PDT 24
Peak memory 215512 kb
Host smart-b7ddd397-b0b9-414b-85d4-1825b086c937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22325
7676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.223257676
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2576553653
Short name T774
Test name
Test status
Simulation time 1648816672 ps
CPU time 12.49 seconds
Started Aug 07 06:02:52 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 207132 kb
Host smart-9cc6d31e-1630-43b8-a9c5-1f5a317d28b5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2576553653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2576553653
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3918973820
Short name T1317
Test name
Test status
Simulation time 234069526 ps
CPU time 1 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:02:52 PM PDT 24
Peak memory 206952 kb
Host smart-373db29b-5ab1-4135-98e0-fb5ee6155828
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3918973820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3918973820
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.771122945
Short name T2503
Test name
Test status
Simulation time 199180340 ps
CPU time 0.95 seconds
Started Aug 07 06:02:49 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 206920 kb
Host smart-311155a9-c8f4-4f69-bd6a-141f26471c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77112
2945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.771122945
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.3480487062
Short name T3007
Test name
Test status
Simulation time 2842706868 ps
CPU time 29.01 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:03:20 PM PDT 24
Peak memory 217312 kb
Host smart-78fcb0c9-24c9-4621-8307-9d4175543698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34804
87062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.3480487062
Directory /workspace/21.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.2589803113
Short name T2645
Test name
Test status
Simulation time 2139615174 ps
CPU time 16.2 seconds
Started Aug 07 06:02:45 PM PDT 24
Finished Aug 07 06:03:01 PM PDT 24
Peak memory 207060 kb
Host smart-27a98c3d-60c9-4ce7-8d3c-d38c95a7f582
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2589803113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2589803113
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1460891800
Short name T2649
Test name
Test status
Simulation time 185220314 ps
CPU time 0.87 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:02:52 PM PDT 24
Peak memory 206952 kb
Host smart-c661ff6c-1dfb-42ec-b885-94d219a394fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1460891800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1460891800
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2759233755
Short name T1704
Test name
Test status
Simulation time 148470921 ps
CPU time 0.83 seconds
Started Aug 07 06:02:49 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 207012 kb
Host smart-a3b341e4-fd9d-480a-b5ed-01ceb12c3835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27592
33755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2759233755
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1241237050
Short name T139
Test name
Test status
Simulation time 187409065 ps
CPU time 0.95 seconds
Started Aug 07 06:02:52 PM PDT 24
Finished Aug 07 06:02:53 PM PDT 24
Peak memory 207036 kb
Host smart-e7dd8e5d-03d2-4598-9ac1-e331819f8468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12412
37050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1241237050
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2869911261
Short name T1845
Test name
Test status
Simulation time 157410907 ps
CPU time 0.86 seconds
Started Aug 07 06:02:49 PM PDT 24
Finished Aug 07 06:02:50 PM PDT 24
Peak memory 206972 kb
Host smart-02de04fd-09a3-43e6-b08d-0249aa98d79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28699
11261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2869911261
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.4006184779
Short name T474
Test name
Test status
Simulation time 156329245 ps
CPU time 0.89 seconds
Started Aug 07 06:02:48 PM PDT 24
Finished Aug 07 06:02:49 PM PDT 24
Peak memory 207016 kb
Host smart-0182e637-7e39-4ea3-bd21-4b1153bc55dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40061
84779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.4006184779
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3790577803
Short name T2428
Test name
Test status
Simulation time 170296704 ps
CPU time 0.88 seconds
Started Aug 07 06:02:46 PM PDT 24
Finished Aug 07 06:02:47 PM PDT 24
Peak memory 206972 kb
Host smart-1f71bf44-b05b-4c2a-a254-edefd3c1bf95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37905
77803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3790577803
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.997893268
Short name T1747
Test name
Test status
Simulation time 158803250 ps
CPU time 0.87 seconds
Started Aug 07 06:02:54 PM PDT 24
Finished Aug 07 06:02:55 PM PDT 24
Peak memory 206964 kb
Host smart-8e1c4322-68ac-4eb3-b522-927de9b0f75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99789
3268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.997893268
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.12907716
Short name T852
Test name
Test status
Simulation time 221776711 ps
CPU time 0.99 seconds
Started Aug 07 06:02:56 PM PDT 24
Finished Aug 07 06:02:57 PM PDT 24
Peak memory 206940 kb
Host smart-99a66a77-7db1-4c31-961c-66d74b8508c2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=12907716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.12907716
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2552028724
Short name T2531
Test name
Test status
Simulation time 161088496 ps
CPU time 0.9 seconds
Started Aug 07 06:03:01 PM PDT 24
Finished Aug 07 06:03:02 PM PDT 24
Peak memory 206984 kb
Host smart-a5e66a90-55e5-4d9b-8a87-55671138b954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520
28724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2552028724
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3290853463
Short name T3072
Test name
Test status
Simulation time 46014045 ps
CPU time 0.72 seconds
Started Aug 07 06:03:03 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 206972 kb
Host smart-99d9e15d-36c0-47fb-9d65-aefa9941ee70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32908
53463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3290853463
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.4041751340
Short name T1484
Test name
Test status
Simulation time 6781467590 ps
CPU time 18.98 seconds
Started Aug 07 06:02:56 PM PDT 24
Finished Aug 07 06:03:15 PM PDT 24
Peak memory 220004 kb
Host smart-88acdbf1-9896-41cd-a3ee-5ead0ee491c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40417
51340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.4041751340
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1190074021
Short name T2656
Test name
Test status
Simulation time 157648907 ps
CPU time 0.89 seconds
Started Aug 07 06:02:58 PM PDT 24
Finished Aug 07 06:02:59 PM PDT 24
Peak memory 206996 kb
Host smart-d1f8919b-46b1-4fbe-811b-5dc1796c8c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11900
74021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1190074021
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.252198266
Short name T2891
Test name
Test status
Simulation time 276018189 ps
CPU time 1.14 seconds
Started Aug 07 06:03:01 PM PDT 24
Finished Aug 07 06:03:02 PM PDT 24
Peak memory 207016 kb
Host smart-d99c4d78-04e6-4997-9af2-e767c9902a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25219
8266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.252198266
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.400347509
Short name T2349
Test name
Test status
Simulation time 183154151 ps
CPU time 0.93 seconds
Started Aug 07 06:03:03 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 207008 kb
Host smart-bd336c91-6da6-4f0f-921d-fd60a456d263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40034
7509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.400347509
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.4093834721
Short name T780
Test name
Test status
Simulation time 163652372 ps
CPU time 0.88 seconds
Started Aug 07 06:02:58 PM PDT 24
Finished Aug 07 06:02:59 PM PDT 24
Peak memory 206948 kb
Host smart-9eb0cccd-8767-4b12-aaa7-3d65dcb94ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40938
34721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.4093834721
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.1531660244
Short name T2355
Test name
Test status
Simulation time 195798495 ps
CPU time 0.96 seconds
Started Aug 07 06:02:54 PM PDT 24
Finished Aug 07 06:02:55 PM PDT 24
Peak memory 206956 kb
Host smart-ae1b0199-3eb7-415d-baab-9e1ab642743f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15316
60244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.1531660244
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.704515219
Short name T2383
Test name
Test status
Simulation time 167074396 ps
CPU time 0.82 seconds
Started Aug 07 06:03:03 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 206976 kb
Host smart-8976a82e-c1a5-473d-8328-182fe8a76d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70451
5219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.704515219
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1983897355
Short name T2306
Test name
Test status
Simulation time 229992479 ps
CPU time 0.89 seconds
Started Aug 07 06:02:59 PM PDT 24
Finished Aug 07 06:03:00 PM PDT 24
Peak memory 207000 kb
Host smart-63d236cb-88e2-43da-8f81-1a81f48b2914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19838
97355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1983897355
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3858263117
Short name T2202
Test name
Test status
Simulation time 202674149 ps
CPU time 0.93 seconds
Started Aug 07 06:02:55 PM PDT 24
Finished Aug 07 06:02:56 PM PDT 24
Peak memory 207008 kb
Host smart-a705dbe9-2df3-4328-9123-05f860ba953a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38582
63117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3858263117
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.2831171379
Short name T2696
Test name
Test status
Simulation time 2281471547 ps
CPU time 65.64 seconds
Started Aug 07 06:02:57 PM PDT 24
Finished Aug 07 06:04:03 PM PDT 24
Peak memory 223612 kb
Host smart-f93109ad-fe1a-49bb-b745-0e6af180d937
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2831171379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.2831171379
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3064251467
Short name T1500
Test name
Test status
Simulation time 186058744 ps
CPU time 0.96 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:02 PM PDT 24
Peak memory 206972 kb
Host smart-abd35837-6d76-4c8f-a6ef-8f69ee6773fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30642
51467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3064251467
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.390650571
Short name T235
Test name
Test status
Simulation time 174924983 ps
CPU time 0.87 seconds
Started Aug 07 06:02:53 PM PDT 24
Finished Aug 07 06:02:53 PM PDT 24
Peak memory 207016 kb
Host smart-74819c03-6a3a-451c-9181-d8b81543e97e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39065
0571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.390650571
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.139621903
Short name T586
Test name
Test status
Simulation time 368450245 ps
CPU time 1.25 seconds
Started Aug 07 06:03:03 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 206984 kb
Host smart-09e77531-f4ab-4419-8e4e-b66de5abda33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13962
1903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.139621903
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.2583125836
Short name T2846
Test name
Test status
Simulation time 2357494802 ps
CPU time 23.37 seconds
Started Aug 07 06:03:01 PM PDT 24
Finished Aug 07 06:03:25 PM PDT 24
Peak memory 217180 kb
Host smart-b5d8b93f-6cff-4482-821a-939d4e3f6692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25831
25836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2583125836
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.2766728008
Short name T1836
Test name
Test status
Simulation time 2916386939 ps
CPU time 25.94 seconds
Started Aug 07 06:02:52 PM PDT 24
Finished Aug 07 06:03:18 PM PDT 24
Peak memory 207248 kb
Host smart-10c428db-2fd3-4b30-8324-6efb9f5eec8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766728008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.2766728008
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.1146794622
Short name T2570
Test name
Test status
Simulation time 35020457 ps
CPU time 0.64 seconds
Started Aug 07 06:02:58 PM PDT 24
Finished Aug 07 06:02:59 PM PDT 24
Peak memory 207012 kb
Host smart-747d014b-d959-4516-bb07-cdcdf180d3ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1146794622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1146794622
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3458706766
Short name T974
Test name
Test status
Simulation time 4395101286 ps
CPU time 6 seconds
Started Aug 07 06:02:59 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 215480 kb
Host smart-4832cda4-0e2b-44db-a71f-ee47dcd27a28
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458706766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.3458706766
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3566731835
Short name T1226
Test name
Test status
Simulation time 19624815084 ps
CPU time 26.66 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:27 PM PDT 24
Peak memory 207272 kb
Host smart-5c37a89d-7a30-47c5-8b1c-ee001d434cd7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566731835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3566731835
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.3136554450
Short name T1414
Test name
Test status
Simulation time 24799016198 ps
CPU time 28.24 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:03:19 PM PDT 24
Peak memory 215380 kb
Host smart-fb8e531e-fca6-4fac-bc20-66519c5a181b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136554450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_resume.3136554450
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2395004507
Short name T1765
Test name
Test status
Simulation time 153466582 ps
CPU time 0.85 seconds
Started Aug 07 06:02:55 PM PDT 24
Finished Aug 07 06:02:56 PM PDT 24
Peak memory 206912 kb
Host smart-f77d893e-0b0b-4ef1-adac-b23672dc5fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23950
04507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2395004507
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.87956833
Short name T1637
Test name
Test status
Simulation time 146791792 ps
CPU time 0.88 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:02:52 PM PDT 24
Peak memory 207004 kb
Host smart-5aeb735e-86c1-45e8-9302-6cb18bfef434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87956
833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.87956833
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.341260352
Short name T3098
Test name
Test status
Simulation time 686324800 ps
CPU time 1.92 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:06 PM PDT 24
Peak memory 207188 kb
Host smart-deb561c9-daca-49f8-8505-42b57c64a867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34126
0352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.341260352
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.85113166
Short name T885
Test name
Test status
Simulation time 657897346 ps
CPU time 1.85 seconds
Started Aug 07 06:02:58 PM PDT 24
Finished Aug 07 06:03:00 PM PDT 24
Peak memory 206976 kb
Host smart-b9c73b2d-73a5-4ae8-93bb-315aba0fd4c6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=85113166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.85113166
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.3462502131
Short name T2613
Test name
Test status
Simulation time 33304645053 ps
CPU time 50.23 seconds
Started Aug 07 06:03:01 PM PDT 24
Finished Aug 07 06:03:51 PM PDT 24
Peak memory 207356 kb
Host smart-f54395a6-6d1e-49a9-981f-c0b1e968138c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34625
02131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.3462502131
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.3872211215
Short name T1925
Test name
Test status
Simulation time 4813638233 ps
CPU time 44.01 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:44 PM PDT 24
Peak memory 207328 kb
Host smart-2393f79b-c2b1-4d98-8197-3a22d1bc3cd4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872211215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.3872211215
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2674216412
Short name T2041
Test name
Test status
Simulation time 1055899647 ps
CPU time 2.46 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:03 PM PDT 24
Peak memory 206988 kb
Host smart-59756a2a-8342-4fc0-a27f-a67a972d5106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26742
16412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2674216412
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1581244965
Short name T609
Test name
Test status
Simulation time 190184203 ps
CPU time 0.9 seconds
Started Aug 07 06:02:55 PM PDT 24
Finished Aug 07 06:02:56 PM PDT 24
Peak memory 206884 kb
Host smart-ac0de043-9399-46fb-b239-a8905c51bbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15812
44965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1581244965
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1172155700
Short name T2162
Test name
Test status
Simulation time 38934288 ps
CPU time 0.79 seconds
Started Aug 07 06:03:03 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 206944 kb
Host smart-7f6f3a3f-a85c-4c19-ad97-4a3e48f05418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11721
55700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1172155700
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3824708038
Short name T1173
Test name
Test status
Simulation time 981877506 ps
CPU time 2.37 seconds
Started Aug 07 06:02:54 PM PDT 24
Finished Aug 07 06:02:57 PM PDT 24
Peak memory 207184 kb
Host smart-31651bd1-f8ea-4081-9efc-0d2d4e9f6c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38247
08038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3824708038
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_types.2515518964
Short name T2939
Test name
Test status
Simulation time 314457448 ps
CPU time 1.15 seconds
Started Aug 07 06:02:53 PM PDT 24
Finished Aug 07 06:02:54 PM PDT 24
Peak memory 206968 kb
Host smart-39d1b2be-4cea-49a3-a782-4bdfb20994d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2515518964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.2515518964
Directory /workspace/22.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2557065560
Short name T1136
Test name
Test status
Simulation time 292855803 ps
CPU time 1.56 seconds
Started Aug 07 06:02:52 PM PDT 24
Finished Aug 07 06:02:53 PM PDT 24
Peak memory 207112 kb
Host smart-917df00d-8ab8-4511-89d9-682a9f6636e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25570
65560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2557065560
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1493826502
Short name T1006
Test name
Test status
Simulation time 226370099 ps
CPU time 1.23 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:01 PM PDT 24
Peak memory 207184 kb
Host smart-03bf3e27-45b0-4ad8-8512-13c810ccc026
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1493826502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1493826502
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.506991342
Short name T2205
Test name
Test status
Simulation time 143696761 ps
CPU time 0.88 seconds
Started Aug 07 06:02:52 PM PDT 24
Finished Aug 07 06:02:53 PM PDT 24
Peak memory 206828 kb
Host smart-2753270e-3520-4c28-a6f6-0203fa5ddf26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50699
1342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.506991342
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1531124721
Short name T2800
Test name
Test status
Simulation time 166723915 ps
CPU time 0.99 seconds
Started Aug 07 06:02:58 PM PDT 24
Finished Aug 07 06:02:59 PM PDT 24
Peak memory 207000 kb
Host smart-27e1b8da-42fc-4a0d-a553-fce7080b7872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15311
24721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1531124721
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1445049247
Short name T860
Test name
Test status
Simulation time 3541956628 ps
CPU time 107.03 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:04:48 PM PDT 24
Peak memory 215512 kb
Host smart-9c70ca33-2aa6-436d-85c9-2b10a6a5e4f0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1445049247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1445049247
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.3106326771
Short name T2213
Test name
Test status
Simulation time 4407718976 ps
CPU time 30.65 seconds
Started Aug 07 06:02:53 PM PDT 24
Finished Aug 07 06:03:24 PM PDT 24
Peak memory 207304 kb
Host smart-24489507-2aa3-4d4f-90ed-9e631ce070aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3106326771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.3106326771
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3218040617
Short name T1479
Test name
Test status
Simulation time 225380568 ps
CPU time 0.96 seconds
Started Aug 07 06:02:53 PM PDT 24
Finished Aug 07 06:02:54 PM PDT 24
Peak memory 206984 kb
Host smart-07330b1a-fe0f-48c1-8e4c-d2808321d9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32180
40617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3218040617
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1831156914
Short name T614
Test name
Test status
Simulation time 13674897715 ps
CPU time 19.48 seconds
Started Aug 07 06:02:51 PM PDT 24
Finished Aug 07 06:03:11 PM PDT 24
Peak memory 207288 kb
Host smart-ce62c1cb-a2da-404f-86d0-c88e88ab1706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18311
56914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1831156914
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1961568806
Short name T2004
Test name
Test status
Simulation time 4303582041 ps
CPU time 6.31 seconds
Started Aug 07 06:02:59 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 216296 kb
Host smart-e1ea826a-2b60-4e30-918b-c0f73d0e8ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19615
68806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1961568806
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1936354565
Short name T2528
Test name
Test status
Simulation time 3347066091 ps
CPU time 23.72 seconds
Started Aug 07 06:02:54 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 223716 kb
Host smart-d4a8257c-eadf-4357-8dcf-c97d140ed780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19363
54565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1936354565
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.986042129
Short name T1462
Test name
Test status
Simulation time 4056728696 ps
CPU time 40.98 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:41 PM PDT 24
Peak memory 215564 kb
Host smart-f09cdbc2-6eb4-4780-b0c9-5d803bf74d32
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=986042129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.986042129
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1271833615
Short name T2623
Test name
Test status
Simulation time 249566245 ps
CPU time 0.99 seconds
Started Aug 07 06:02:56 PM PDT 24
Finished Aug 07 06:02:57 PM PDT 24
Peak memory 206980 kb
Host smart-36e9cd07-c7ed-4a6d-aa52-695d394929aa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1271833615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1271833615
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1249480833
Short name T1624
Test name
Test status
Simulation time 215174559 ps
CPU time 0.98 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:02 PM PDT 24
Peak memory 207028 kb
Host smart-78b35e4f-cb79-4563-9c1a-998cf1ceae98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12494
80833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1249480833
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.44435376
Short name T2995
Test name
Test status
Simulation time 2007918368 ps
CPU time 59.33 seconds
Started Aug 07 06:02:57 PM PDT 24
Finished Aug 07 06:03:56 PM PDT 24
Peak memory 216964 kb
Host smart-636a7378-581c-4ca4-a657-7d0404806fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44435
376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.44435376
Directory /workspace/22.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.4166394282
Short name T1195
Test name
Test status
Simulation time 2813297043 ps
CPU time 85.8 seconds
Started Aug 07 06:02:59 PM PDT 24
Finished Aug 07 06:04:25 PM PDT 24
Peak memory 216816 kb
Host smart-29485fe8-45ef-47b4-b61e-63bdceaf05ba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4166394282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.4166394282
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1869749334
Short name T2085
Test name
Test status
Simulation time 155778903 ps
CPU time 0.83 seconds
Started Aug 07 06:03:01 PM PDT 24
Finished Aug 07 06:03:02 PM PDT 24
Peak memory 207032 kb
Host smart-bd88ea6f-3de8-4057-a0bc-6f2e5900da6b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1869749334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1869749334
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.686442010
Short name T2361
Test name
Test status
Simulation time 146879991 ps
CPU time 0.83 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:01 PM PDT 24
Peak memory 206964 kb
Host smart-37ab5b20-048b-4065-8be5-2c6351efeb1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68644
2010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.686442010
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1182290715
Short name T640
Test name
Test status
Simulation time 173446100 ps
CPU time 0.9 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:01 PM PDT 24
Peak memory 207024 kb
Host smart-3d96999f-35d9-4af4-bce7-c1ae45192ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11822
90715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1182290715
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3955029149
Short name T1443
Test name
Test status
Simulation time 169526842 ps
CPU time 0.87 seconds
Started Aug 07 06:03:02 PM PDT 24
Finished Aug 07 06:03:03 PM PDT 24
Peak memory 206972 kb
Host smart-69c99cac-d725-4870-bddc-92a59f6cea63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550
29149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3955029149
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1950831329
Short name T648
Test name
Test status
Simulation time 158042408 ps
CPU time 0.94 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 206912 kb
Host smart-fbaebd1a-5afa-4a6d-8add-512df3f9c2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19508
31329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1950831329
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.2160372553
Short name T1471
Test name
Test status
Simulation time 156292208 ps
CPU time 0.85 seconds
Started Aug 07 06:02:59 PM PDT 24
Finished Aug 07 06:03:00 PM PDT 24
Peak memory 207000 kb
Host smart-34f072d0-ebcf-4368-82b2-c8615b5a4eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21603
72553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2160372553
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1033606114
Short name T2410
Test name
Test status
Simulation time 256147994 ps
CPU time 1.11 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 206896 kb
Host smart-65ff1607-6c84-4c5c-b3fd-dad15a53df92
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1033606114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1033606114
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1574881267
Short name T1641
Test name
Test status
Simulation time 140971283 ps
CPU time 0.85 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:01 PM PDT 24
Peak memory 207004 kb
Host smart-c6bc1f96-72bb-4ec8-9d2e-b5cedb8cee85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15748
81267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1574881267
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1112337186
Short name T2263
Test name
Test status
Simulation time 35508323 ps
CPU time 0.72 seconds
Started Aug 07 06:02:59 PM PDT 24
Finished Aug 07 06:03:00 PM PDT 24
Peak memory 206952 kb
Host smart-745f8bd5-f859-4b46-bde0-57bbb9847cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11123
37186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1112337186
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2032030513
Short name T2821
Test name
Test status
Simulation time 15687196679 ps
CPU time 38.84 seconds
Started Aug 07 06:03:01 PM PDT 24
Finished Aug 07 06:03:40 PM PDT 24
Peak memory 223676 kb
Host smart-bedeb522-aec3-47f0-a95b-fa12309e333e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20320
30513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2032030513
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1892821085
Short name T697
Test name
Test status
Simulation time 188682170 ps
CPU time 0.91 seconds
Started Aug 07 06:03:01 PM PDT 24
Finished Aug 07 06:03:02 PM PDT 24
Peak memory 207196 kb
Host smart-c67ffc05-c6e5-4d64-a5ac-2f1f6fc20f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18928
21085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1892821085
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2532877510
Short name T498
Test name
Test status
Simulation time 229013391 ps
CPU time 1.05 seconds
Started Aug 07 06:03:05 PM PDT 24
Finished Aug 07 06:03:06 PM PDT 24
Peak memory 206884 kb
Host smart-3253c698-6e9f-431d-9ee8-bce1e4d0205a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25328
77510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2532877510
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.4073041440
Short name T2234
Test name
Test status
Simulation time 215397094 ps
CPU time 0.94 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 206996 kb
Host smart-43cb0acd-cbca-4867-bdd7-2da3df2427d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40730
41440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.4073041440
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3588432033
Short name T2233
Test name
Test status
Simulation time 205987535 ps
CPU time 0.95 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 206996 kb
Host smart-3b8e2bb9-c20e-4a14-b27c-75f4b7a6686b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35884
32033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3588432033
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.839969276
Short name T2197
Test name
Test status
Simulation time 183325086 ps
CPU time 0.92 seconds
Started Aug 07 06:02:59 PM PDT 24
Finished Aug 07 06:03:00 PM PDT 24
Peak memory 207016 kb
Host smart-e67c1d08-14c1-47ba-a2f5-fd6867b8cab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83996
9276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.839969276
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_rx_full.3053674398
Short name T2706
Test name
Test status
Simulation time 401820570 ps
CPU time 1.29 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 206996 kb
Host smart-b0976c31-139b-4a09-b6ab-2bd101ff030f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30536
74398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.3053674398
Directory /workspace/22.usbdev_rx_full/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3406729919
Short name T934
Test name
Test status
Simulation time 198580977 ps
CPU time 0.93 seconds
Started Aug 07 06:03:02 PM PDT 24
Finished Aug 07 06:03:03 PM PDT 24
Peak memory 207008 kb
Host smart-63a6656d-dbc5-40eb-84c9-a6e009b52d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34067
29919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3406729919
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1505904098
Short name T1832
Test name
Test status
Simulation time 149794030 ps
CPU time 0.86 seconds
Started Aug 07 06:02:59 PM PDT 24
Finished Aug 07 06:03:00 PM PDT 24
Peak memory 206904 kb
Host smart-02590311-2503-4371-9cc7-e286e548a53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15059
04098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1505904098
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2602432715
Short name T1592
Test name
Test status
Simulation time 219249586 ps
CPU time 1.04 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 206904 kb
Host smart-7a2b91a6-d2b5-432b-8c30-e70b11b043ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26024
32715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2602432715
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.1144070948
Short name T2876
Test name
Test status
Simulation time 2490836838 ps
CPU time 68.68 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:04:13 PM PDT 24
Peak memory 215472 kb
Host smart-5588e238-5dcc-4e67-b111-f276917259a9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1144070948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1144070948
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2232948492
Short name T701
Test name
Test status
Simulation time 222598252 ps
CPU time 1 seconds
Started Aug 07 06:03:03 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 206980 kb
Host smart-72028c5e-40b3-44aa-adfa-d699292f6ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22329
48492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2232948492
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.252983449
Short name T3099
Test name
Test status
Simulation time 193012009 ps
CPU time 0.94 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 207024 kb
Host smart-eb320366-8ff5-422f-985f-69417e770bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25298
3449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.252983449
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.1924227703
Short name T1185
Test name
Test status
Simulation time 931053816 ps
CPU time 2.25 seconds
Started Aug 07 06:02:58 PM PDT 24
Finished Aug 07 06:03:01 PM PDT 24
Peak memory 207120 kb
Host smart-c87c7c8d-e2da-422d-a93d-25452506a8c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19242
27703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.1924227703
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2549371827
Short name T2872
Test name
Test status
Simulation time 3870132262 ps
CPU time 31.35 seconds
Started Aug 07 06:03:01 PM PDT 24
Finished Aug 07 06:03:32 PM PDT 24
Peak memory 215548 kb
Host smart-38afae3b-0920-4bfe-98e1-697e6041d9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25493
71827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2549371827
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.3213202623
Short name T250
Test name
Test status
Simulation time 4321366169 ps
CPU time 37.89 seconds
Started Aug 07 06:02:52 PM PDT 24
Finished Aug 07 06:03:30 PM PDT 24
Peak memory 207172 kb
Host smart-ebcb72d7-67ac-423f-8563-1ce423482260
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213202623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.3213202623
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.3545380212
Short name T2743
Test name
Test status
Simulation time 42005727 ps
CPU time 0.68 seconds
Started Aug 07 06:03:11 PM PDT 24
Finished Aug 07 06:03:11 PM PDT 24
Peak memory 206908 kb
Host smart-9ec6d166-e7f9-47e1-8887-d42d8ef97b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3545380212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.3545380212
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.1954742412
Short name T794
Test name
Test status
Simulation time 9255725951 ps
CPU time 11.57 seconds
Started Aug 07 06:03:01 PM PDT 24
Finished Aug 07 06:03:12 PM PDT 24
Peak memory 207296 kb
Host smart-f7a5d321-6929-4bba-b5c4-35b832d05b1d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954742412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.1954742412
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3605673424
Short name T1619
Test name
Test status
Simulation time 13632593735 ps
CPU time 15.69 seconds
Started Aug 07 06:03:02 PM PDT 24
Finished Aug 07 06:03:18 PM PDT 24
Peak memory 215508 kb
Host smart-d4bed9df-b16f-4fb8-be8f-758775b9d494
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605673424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3605673424
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.2092637514
Short name T2292
Test name
Test status
Simulation time 23644601396 ps
CPU time 31 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:35 PM PDT 24
Peak memory 215484 kb
Host smart-d63c5e6c-47ed-42bd-8106-2d6281a749e6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092637514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.2092637514
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3385002490
Short name T1871
Test name
Test status
Simulation time 171009301 ps
CPU time 0.9 seconds
Started Aug 07 06:02:58 PM PDT 24
Finished Aug 07 06:02:59 PM PDT 24
Peak memory 206892 kb
Host smart-3effc1c3-e301-4748-ab57-0df1566a8f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33850
02490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3385002490
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3350524200
Short name T1415
Test name
Test status
Simulation time 143028081 ps
CPU time 0.9 seconds
Started Aug 07 06:03:02 PM PDT 24
Finished Aug 07 06:03:03 PM PDT 24
Peak memory 206988 kb
Host smart-34cb2d4c-9fbb-46d2-bb40-1d933b0f38cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33505
24200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3350524200
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1620079930
Short name T1940
Test name
Test status
Simulation time 386366140 ps
CPU time 1.4 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 206996 kb
Host smart-2fc0f1e3-0b4d-4fc4-b33c-ab6d87d9463f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16200
79930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1620079930
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2196152852
Short name T2922
Test name
Test status
Simulation time 1140653289 ps
CPU time 2.81 seconds
Started Aug 07 06:02:58 PM PDT 24
Finished Aug 07 06:03:01 PM PDT 24
Peak memory 207176 kb
Host smart-1292e225-4eda-4d90-b263-6abd3cf1b1b4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2196152852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2196152852
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.4100460298
Short name T2348
Test name
Test status
Simulation time 54323020471 ps
CPU time 75.42 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 207292 kb
Host smart-fc7f070e-2915-4246-a7cd-8617c3737fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41004
60298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.4100460298
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.486737450
Short name T2994
Test name
Test status
Simulation time 739120557 ps
CPU time 5.39 seconds
Started Aug 07 06:02:59 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 207196 kb
Host smart-74e3aba1-2dec-4079-a7e4-82c0596edf14
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486737450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.486737450
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.483723265
Short name T2465
Test name
Test status
Simulation time 1053814215 ps
CPU time 2.37 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:07 PM PDT 24
Peak memory 206984 kb
Host smart-c5d2670a-e4ca-46a0-b1ac-c5eab1f47e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48372
3265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.483723265
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.145128878
Short name T3114
Test name
Test status
Simulation time 138098051 ps
CPU time 0.84 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:01 PM PDT 24
Peak memory 206960 kb
Host smart-03c4fe05-1ef2-4eaf-b918-ebb5bfce87ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14512
8878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.145128878
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.417778
Short name T2052
Test name
Test status
Simulation time 40143751 ps
CPU time 0.75 seconds
Started Aug 07 06:03:03 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 206944 kb
Host smart-345d6959-e807-4a74-9acb-1fcb72a71a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41777
8 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.417778
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.52419634
Short name T1632
Test name
Test status
Simulation time 921210288 ps
CPU time 2.82 seconds
Started Aug 07 06:03:08 PM PDT 24
Finished Aug 07 06:03:11 PM PDT 24
Peak memory 207200 kb
Host smart-390f636d-cdba-4eb5-ba4c-56fd1abd442a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52419
634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.52419634
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_types.1766298292
Short name T429
Test name
Test status
Simulation time 330178391 ps
CPU time 1.18 seconds
Started Aug 07 06:03:06 PM PDT 24
Finished Aug 07 06:03:07 PM PDT 24
Peak memory 206976 kb
Host smart-7317566e-f73d-4ad6-a85e-89fd942e92f9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1766298292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.1766298292
Directory /workspace/23.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3700698026
Short name T2163
Test name
Test status
Simulation time 317110948 ps
CPU time 2.89 seconds
Started Aug 07 06:03:06 PM PDT 24
Finished Aug 07 06:03:09 PM PDT 24
Peak memory 207148 kb
Host smart-b7054747-bd3a-4c80-88e6-a32320c8023c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37006
98026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3700698026
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2108508031
Short name T1380
Test name
Test status
Simulation time 215438563 ps
CPU time 1.1 seconds
Started Aug 07 06:03:02 PM PDT 24
Finished Aug 07 06:03:03 PM PDT 24
Peak memory 207168 kb
Host smart-49c3b68b-42f9-4968-99c5-a71afab72fad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2108508031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2108508031
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.603857797
Short name T517
Test name
Test status
Simulation time 149189084 ps
CPU time 0.79 seconds
Started Aug 07 06:03:06 PM PDT 24
Finished Aug 07 06:03:07 PM PDT 24
Peak memory 206952 kb
Host smart-c40ff62a-9937-451e-aada-cd492c3cca01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60385
7797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.603857797
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3166859870
Short name T1197
Test name
Test status
Simulation time 166222738 ps
CPU time 0.87 seconds
Started Aug 07 06:03:10 PM PDT 24
Finished Aug 07 06:03:11 PM PDT 24
Peak memory 207004 kb
Host smart-b250b75d-3c0b-4196-bd86-bf4f0916b132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31668
59870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3166859870
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3291078657
Short name T2543
Test name
Test status
Simulation time 4691557913 ps
CPU time 44.1 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:48 PM PDT 24
Peak memory 217796 kb
Host smart-138b0243-df56-4cfe-b27f-d7c7c13cf434
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3291078657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3291078657
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.368479516
Short name T2847
Test name
Test status
Simulation time 4021604567 ps
CPU time 28.3 seconds
Started Aug 07 06:03:05 PM PDT 24
Finished Aug 07 06:03:34 PM PDT 24
Peak memory 207220 kb
Host smart-16754eaf-3489-4e24-a395-30ae579a8615
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=368479516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.368479516
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.3225708003
Short name T637
Test name
Test status
Simulation time 240557376 ps
CPU time 0.95 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 207008 kb
Host smart-37c3701e-15b9-417a-8618-8bbd45f34a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32257
08003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3225708003
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.1354879088
Short name T737
Test name
Test status
Simulation time 25715781862 ps
CPU time 45.09 seconds
Started Aug 07 06:03:05 PM PDT 24
Finished Aug 07 06:03:50 PM PDT 24
Peak memory 216260 kb
Host smart-25ae9ef9-ad1e-4b78-b005-be79db48de1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13548
79088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.1354879088
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1556188496
Short name T1159
Test name
Test status
Simulation time 10376048071 ps
CPU time 14.09 seconds
Started Aug 07 06:03:06 PM PDT 24
Finished Aug 07 06:03:20 PM PDT 24
Peak memory 207308 kb
Host smart-ab79b876-fddd-4010-90dd-a4341309eb40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15561
88496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1556188496
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.124916720
Short name T980
Test name
Test status
Simulation time 5041954108 ps
CPU time 48.34 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:53 PM PDT 24
Peak memory 217200 kb
Host smart-12148d9b-3314-4920-9286-57663830334f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12491
6720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.124916720
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.2539045689
Short name T1040
Test name
Test status
Simulation time 2165612039 ps
CPU time 16.68 seconds
Started Aug 07 06:03:11 PM PDT 24
Finished Aug 07 06:03:28 PM PDT 24
Peak memory 214936 kb
Host smart-42639961-f4ef-41b2-b4af-2fb9de130ebd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2539045689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.2539045689
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.792005239
Short name T2384
Test name
Test status
Simulation time 244494379 ps
CPU time 1 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 206992 kb
Host smart-27e12d98-f4ba-4e4c-bb19-5908394a58f0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=792005239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.792005239
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2491890143
Short name T1307
Test name
Test status
Simulation time 245567853 ps
CPU time 1.02 seconds
Started Aug 07 06:03:11 PM PDT 24
Finished Aug 07 06:03:12 PM PDT 24
Peak memory 206544 kb
Host smart-226aecfa-16ca-461c-983b-cdabe3de870c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24918
90143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2491890143
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.696300703
Short name T1186
Test name
Test status
Simulation time 2776936417 ps
CPU time 21.51 seconds
Started Aug 07 06:03:09 PM PDT 24
Finished Aug 07 06:03:31 PM PDT 24
Peak memory 223664 kb
Host smart-a6caa663-7442-4171-9956-05e067c9f904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69630
0703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.696300703
Directory /workspace/23.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.1813157571
Short name T2489
Test name
Test status
Simulation time 2053892056 ps
CPU time 15.71 seconds
Started Aug 07 06:03:09 PM PDT 24
Finished Aug 07 06:03:25 PM PDT 24
Peak memory 207164 kb
Host smart-dad033d1-bcb9-4119-8736-ed7e8bf04fb3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1813157571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.1813157571
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.4294878827
Short name T1542
Test name
Test status
Simulation time 227413947 ps
CPU time 0.95 seconds
Started Aug 07 06:03:13 PM PDT 24
Finished Aug 07 06:03:15 PM PDT 24
Peak memory 206996 kb
Host smart-7be4b5be-8315-42ab-997c-cdaa0d64af34
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4294878827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.4294878827
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.4144359186
Short name T2154
Test name
Test status
Simulation time 149396692 ps
CPU time 0.92 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 206964 kb
Host smart-42397763-6039-4934-a304-2973e0c503b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41443
59186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.4144359186
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1790585509
Short name T2330
Test name
Test status
Simulation time 220950556 ps
CPU time 0.98 seconds
Started Aug 07 06:03:05 PM PDT 24
Finished Aug 07 06:03:06 PM PDT 24
Peak memory 207008 kb
Host smart-420006e8-a5a2-4fe9-b322-097557d1b7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17905
85509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1790585509
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.1425993616
Short name T1856
Test name
Test status
Simulation time 172414002 ps
CPU time 0.9 seconds
Started Aug 07 06:03:03 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 206972 kb
Host smart-64c28895-5b53-4f0d-81c4-4e78d32513e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14259
93616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.1425993616
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3257611431
Short name T2359
Test name
Test status
Simulation time 212293086 ps
CPU time 0.9 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 207036 kb
Host smart-e2977b70-3e5b-4218-8bb1-d8967c8522d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32576
11431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3257611431
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3576759448
Short name T3105
Test name
Test status
Simulation time 245051164 ps
CPU time 1.09 seconds
Started Aug 07 06:03:05 PM PDT 24
Finished Aug 07 06:03:06 PM PDT 24
Peak memory 206972 kb
Host smart-df8b52a3-f4de-4987-b3f2-3b7ad62c7aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767
59448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3576759448
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.645207256
Short name T1638
Test name
Test status
Simulation time 170759688 ps
CPU time 0.88 seconds
Started Aug 07 06:03:11 PM PDT 24
Finished Aug 07 06:03:12 PM PDT 24
Peak memory 207004 kb
Host smart-befee0b9-5b07-4618-add3-cacd65ad7cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64520
7256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.645207256
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1701784413
Short name T1841
Test name
Test status
Simulation time 234383062 ps
CPU time 1.01 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 207000 kb
Host smart-2153d367-6ba2-4953-bd93-9d10f6e0f303
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1701784413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1701784413
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2885310873
Short name T2055
Test name
Test status
Simulation time 144450132 ps
CPU time 0.84 seconds
Started Aug 07 06:03:03 PM PDT 24
Finished Aug 07 06:03:04 PM PDT 24
Peak memory 206980 kb
Host smart-dd102789-a428-4b60-9bd6-2165d2c1bce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28853
10873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2885310873
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3718538785
Short name T2935
Test name
Test status
Simulation time 60189743 ps
CPU time 0.75 seconds
Started Aug 07 06:03:08 PM PDT 24
Finished Aug 07 06:03:08 PM PDT 24
Peak memory 206828 kb
Host smart-8ab76d52-a590-49fe-920a-66733c4ec3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37185
38785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3718538785
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1749696678
Short name T294
Test name
Test status
Simulation time 13535511305 ps
CPU time 33.99 seconds
Started Aug 07 06:03:07 PM PDT 24
Finished Aug 07 06:03:41 PM PDT 24
Peak memory 215360 kb
Host smart-38c40401-876d-477a-acd5-4ccd4a289799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17496
96678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1749696678
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.512168765
Short name T2494
Test name
Test status
Simulation time 175609440 ps
CPU time 0.86 seconds
Started Aug 07 06:03:06 PM PDT 24
Finished Aug 07 06:03:07 PM PDT 24
Peak memory 206984 kb
Host smart-49e22ea2-d31f-429e-afb8-66bb91445c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51216
8765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.512168765
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.4189400531
Short name T1663
Test name
Test status
Simulation time 192571097 ps
CPU time 0.92 seconds
Started Aug 07 06:03:05 PM PDT 24
Finished Aug 07 06:03:06 PM PDT 24
Peak memory 206964 kb
Host smart-ff012117-8179-48b3-aa85-b069402afba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41894
00531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.4189400531
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.1726893806
Short name T2139
Test name
Test status
Simulation time 215019768 ps
CPU time 1.06 seconds
Started Aug 07 06:03:04 PM PDT 24
Finished Aug 07 06:03:06 PM PDT 24
Peak memory 206964 kb
Host smart-79b3bf3b-d354-4220-9465-1ccbb9cdcfb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17268
93806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.1726893806
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2697077989
Short name T1981
Test name
Test status
Simulation time 202506373 ps
CPU time 0.93 seconds
Started Aug 07 06:03:09 PM PDT 24
Finished Aug 07 06:03:10 PM PDT 24
Peak memory 207016 kb
Host smart-228bd4a7-362e-47c8-8e9b-49f3e67cbabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26970
77989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2697077989
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.1488071126
Short name T1493
Test name
Test status
Simulation time 150949823 ps
CPU time 0.85 seconds
Started Aug 07 06:03:09 PM PDT 24
Finished Aug 07 06:03:09 PM PDT 24
Peak memory 207020 kb
Host smart-40421462-d829-461f-80da-ea92810f034d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14880
71126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1488071126
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_rx_full.2559818209
Short name T1655
Test name
Test status
Simulation time 384661596 ps
CPU time 1.3 seconds
Started Aug 07 06:03:08 PM PDT 24
Finished Aug 07 06:03:10 PM PDT 24
Peak memory 207016 kb
Host smart-24ad292c-e37e-4523-917f-7170a1e476f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25598
18209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.2559818209
Directory /workspace/23.usbdev_rx_full/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3504252648
Short name T891
Test name
Test status
Simulation time 185443996 ps
CPU time 0.9 seconds
Started Aug 07 06:03:06 PM PDT 24
Finished Aug 07 06:03:07 PM PDT 24
Peak memory 206996 kb
Host smart-42e97fbc-22af-4265-991d-a85cc7398318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35042
52648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3504252648
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1941618993
Short name T696
Test name
Test status
Simulation time 184646544 ps
CPU time 0.87 seconds
Started Aug 07 06:03:08 PM PDT 24
Finished Aug 07 06:03:09 PM PDT 24
Peak memory 207016 kb
Host smart-082e698d-8248-4784-9869-8b1cbf414911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19416
18993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1941618993
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1583673367
Short name T1804
Test name
Test status
Simulation time 246904155 ps
CPU time 1.05 seconds
Started Aug 07 06:03:08 PM PDT 24
Finished Aug 07 06:03:09 PM PDT 24
Peak memory 206944 kb
Host smart-ee8e8d21-09e9-4e9b-b4fd-973e5eaa8481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15836
73367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1583673367
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.2718542603
Short name T902
Test name
Test status
Simulation time 2235163423 ps
CPU time 21.88 seconds
Started Aug 07 06:03:06 PM PDT 24
Finished Aug 07 06:03:28 PM PDT 24
Peak memory 223676 kb
Host smart-4a49ac97-192f-462a-b5df-924a97c2c0e3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2718542603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.2718542603
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2531715794
Short name T2245
Test name
Test status
Simulation time 191261570 ps
CPU time 0.89 seconds
Started Aug 07 06:03:18 PM PDT 24
Finished Aug 07 06:03:19 PM PDT 24
Peak memory 206904 kb
Host smart-99d5797e-c000-4683-be15-dcbe809713d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25317
15794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2531715794
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3935175400
Short name T2523
Test name
Test status
Simulation time 168749298 ps
CPU time 0.9 seconds
Started Aug 07 06:03:15 PM PDT 24
Finished Aug 07 06:03:16 PM PDT 24
Peak memory 206992 kb
Host smart-a89de3cf-37f5-4150-a39c-6795c0c086bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39351
75400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3935175400
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.3519735474
Short name T2890
Test name
Test status
Simulation time 838761590 ps
CPU time 2.15 seconds
Started Aug 07 06:03:14 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 207152 kb
Host smart-a1ab52fe-4fc9-4175-abea-a4b87e63e2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35197
35474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.3519735474
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.157635788
Short name T995
Test name
Test status
Simulation time 3818382055 ps
CPU time 33.12 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:50 PM PDT 24
Peak memory 215692 kb
Host smart-78662b5c-539c-4d75-a7c0-df196c6136bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15763
5788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.157635788
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.1443308961
Short name T1239
Test name
Test status
Simulation time 831820553 ps
CPU time 5.66 seconds
Started Aug 07 06:03:00 PM PDT 24
Finished Aug 07 06:03:06 PM PDT 24
Peak memory 207192 kb
Host smart-9fc06e9f-61b2-4840-9b9a-2e48f15428f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443308961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.1443308961
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.2418507429
Short name T1786
Test name
Test status
Simulation time 31550038 ps
CPU time 0.67 seconds
Started Aug 07 06:03:24 PM PDT 24
Finished Aug 07 06:03:25 PM PDT 24
Peak memory 207080 kb
Host smart-7250bf82-f820-426a-9910-baabe62687cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2418507429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2418507429
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3716233778
Short name T1245
Test name
Test status
Simulation time 4131187064 ps
CPU time 5.62 seconds
Started Aug 07 06:03:15 PM PDT 24
Finished Aug 07 06:03:20 PM PDT 24
Peak memory 215484 kb
Host smart-20bb80cf-5f06-4e3c-91ac-caf8864f40ca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716233778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_disconnect.3716233778
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1001836454
Short name T836
Test name
Test status
Simulation time 14702484793 ps
CPU time 20.15 seconds
Started Aug 07 06:03:13 PM PDT 24
Finished Aug 07 06:03:34 PM PDT 24
Peak memory 215456 kb
Host smart-838b0b25-3ee4-4c4a-8b67-89889f4c1c6d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001836454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1001836454
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.3523219794
Short name T1998
Test name
Test status
Simulation time 30541871070 ps
CPU time 36.2 seconds
Started Aug 07 06:03:11 PM PDT 24
Finished Aug 07 06:03:47 PM PDT 24
Peak memory 207260 kb
Host smart-4b02fe8d-106a-48db-91e6-8a3c94516b4b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523219794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.3523219794
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2562245693
Short name T1429
Test name
Test status
Simulation time 177086902 ps
CPU time 0.89 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 207000 kb
Host smart-5ac0823c-3bc4-43d9-829d-f4f12358e5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25622
45693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2562245693
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.657687976
Short name T2653
Test name
Test status
Simulation time 188351448 ps
CPU time 0.89 seconds
Started Aug 07 06:03:13 PM PDT 24
Finished Aug 07 06:03:14 PM PDT 24
Peak memory 206996 kb
Host smart-5e5612bd-99f5-4cc0-bd6a-b984f04351b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65768
7976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.657687976
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.3438160840
Short name T1399
Test name
Test status
Simulation time 374397920 ps
CPU time 1.28 seconds
Started Aug 07 06:03:15 PM PDT 24
Finished Aug 07 06:03:16 PM PDT 24
Peak memory 206504 kb
Host smart-4ed9b9f0-0c5b-4ace-8e73-0d40875f6546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34381
60840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.3438160840
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1437557974
Short name T2462
Test name
Test status
Simulation time 466264183 ps
CPU time 1.65 seconds
Started Aug 07 06:03:12 PM PDT 24
Finished Aug 07 06:03:14 PM PDT 24
Peak memory 206972 kb
Host smart-1a784b08-fc8c-4af5-9d61-e82f1c67f318
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1437557974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1437557974
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.3931637070
Short name T3046
Test name
Test status
Simulation time 40548998666 ps
CPU time 61.26 seconds
Started Aug 07 06:03:15 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 206684 kb
Host smart-aa4a4feb-49f0-40f6-97e3-c8c11a94ca5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39316
37070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3931637070
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.436480710
Short name T1834
Test name
Test status
Simulation time 788683009 ps
CPU time 15.39 seconds
Started Aug 07 06:03:31 PM PDT 24
Finished Aug 07 06:03:46 PM PDT 24
Peak memory 207216 kb
Host smart-edfb1548-2cfc-452c-9273-3328780d50d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436480710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.436480710
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2796728101
Short name T1043
Test name
Test status
Simulation time 685400116 ps
CPU time 1.8 seconds
Started Aug 07 06:03:15 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 206888 kb
Host smart-7acfb566-ac60-42f0-9c9f-c60aef879cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27967
28101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2796728101
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3924433057
Short name T2076
Test name
Test status
Simulation time 159133308 ps
CPU time 0.86 seconds
Started Aug 07 06:03:14 PM PDT 24
Finished Aug 07 06:03:15 PM PDT 24
Peak memory 206940 kb
Host smart-269d4033-a1d4-4605-9108-a6c8ef0d067d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39244
33057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3924433057
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2974725463
Short name T2385
Test name
Test status
Simulation time 73799404 ps
CPU time 0.81 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 207156 kb
Host smart-c3c52a43-54a9-4e47-95d7-3f16da8670cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29747
25463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2974725463
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.2722294914
Short name T1005
Test name
Test status
Simulation time 1072763754 ps
CPU time 2.7 seconds
Started Aug 07 06:03:14 PM PDT 24
Finished Aug 07 06:03:16 PM PDT 24
Peak memory 207164 kb
Host smart-c263f7a8-f867-4c74-8361-39c1738fff87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27222
94914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2722294914
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_types.720465484
Short name T2241
Test name
Test status
Simulation time 595219785 ps
CPU time 1.52 seconds
Started Aug 07 06:03:14 PM PDT 24
Finished Aug 07 06:03:15 PM PDT 24
Peak memory 206960 kb
Host smart-a5a0d866-3415-4aec-9b3d-bd14eb273ba0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=720465484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.720465484
Directory /workspace/24.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1512821312
Short name T2999
Test name
Test status
Simulation time 313684796 ps
CPU time 2.21 seconds
Started Aug 07 06:03:12 PM PDT 24
Finished Aug 07 06:03:15 PM PDT 24
Peak memory 207104 kb
Host smart-d81fb765-fd2d-4ff7-8d43-a5e74a5ac542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15128
21312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1512821312
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.851404361
Short name T740
Test name
Test status
Simulation time 208714582 ps
CPU time 1.1 seconds
Started Aug 07 06:03:12 PM PDT 24
Finished Aug 07 06:03:13 PM PDT 24
Peak memory 207140 kb
Host smart-c7cfb4fb-9729-445c-8bf7-eabf8faba46e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=851404361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.851404361
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.465660719
Short name T2998
Test name
Test status
Simulation time 152086197 ps
CPU time 0.83 seconds
Started Aug 07 06:03:12 PM PDT 24
Finished Aug 07 06:03:13 PM PDT 24
Peak memory 206928 kb
Host smart-43f29662-b39c-4c6d-a6eb-b77bc1cb21cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46566
0719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.465660719
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3555708982
Short name T1218
Test name
Test status
Simulation time 171866135 ps
CPU time 0.91 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 206992 kb
Host smart-9ea5a00b-0ed6-4e83-999f-2470f35ed9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35557
08982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3555708982
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.1955305068
Short name T2352
Test name
Test status
Simulation time 4392088074 ps
CPU time 44.9 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:04:01 PM PDT 24
Peak memory 217424 kb
Host smart-1efc5883-a9af-4698-a5df-4cd3aada7b85
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1955305068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.1955305068
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.1901475577
Short name T1902
Test name
Test status
Simulation time 5684243744 ps
CPU time 42.23 seconds
Started Aug 07 06:03:15 PM PDT 24
Finished Aug 07 06:03:58 PM PDT 24
Peak memory 207240 kb
Host smart-a26c94af-d50f-43d2-b0a6-69505ded680b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1901475577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.1901475577
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3578192735
Short name T1436
Test name
Test status
Simulation time 239906158 ps
CPU time 1 seconds
Started Aug 07 06:03:13 PM PDT 24
Finished Aug 07 06:03:14 PM PDT 24
Peak memory 207036 kb
Host smart-82437748-0a3b-4b9e-9fab-10c0aba07e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35781
92735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3578192735
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1092100967
Short name T1161
Test name
Test status
Simulation time 8925161944 ps
CPU time 14.29 seconds
Started Aug 07 06:03:19 PM PDT 24
Finished Aug 07 06:03:33 PM PDT 24
Peak memory 215380 kb
Host smart-1c3ac3b8-42f2-43b6-b963-2f15cad310a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10921
00967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1092100967
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.675085103
Short name T2243
Test name
Test status
Simulation time 9568665410 ps
CPU time 14.55 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:31 PM PDT 24
Peak memory 207316 kb
Host smart-59c2285c-bb8e-4277-94ff-7b954d2985c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67508
5103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.675085103
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.2786892040
Short name T1537
Test name
Test status
Simulation time 4007044018 ps
CPU time 31.25 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:48 PM PDT 24
Peak memory 223676 kb
Host smart-180286b6-29d7-4e0e-9517-2a14dabcb549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27868
92040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.2786892040
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.55387968
Short name T1496
Test name
Test status
Simulation time 2520386101 ps
CPU time 20.43 seconds
Started Aug 07 06:03:13 PM PDT 24
Finished Aug 07 06:03:34 PM PDT 24
Peak memory 217220 kb
Host smart-c67a1043-27a9-439e-9684-7d69f4f68ecb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=55387968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.55387968
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.3476522443
Short name T1681
Test name
Test status
Simulation time 259456476 ps
CPU time 1 seconds
Started Aug 07 06:03:15 PM PDT 24
Finished Aug 07 06:03:16 PM PDT 24
Peak memory 206904 kb
Host smart-428f0793-a8d5-4f0b-96c6-4f6e7ac2eae2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3476522443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3476522443
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.102777483
Short name T2070
Test name
Test status
Simulation time 195369715 ps
CPU time 0.97 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 207020 kb
Host smart-50a4aab6-27d6-4a5d-b3f9-e6c1691390c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10277
7483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.102777483
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.1954746468
Short name T1069
Test name
Test status
Simulation time 2678985799 ps
CPU time 21.12 seconds
Started Aug 07 06:03:13 PM PDT 24
Finished Aug 07 06:03:34 PM PDT 24
Peak memory 223612 kb
Host smart-53c0125f-0f93-4c89-bd9c-9e8e5010a9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19547
46468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.1954746468
Directory /workspace/24.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.1253410206
Short name T587
Test name
Test status
Simulation time 3107531308 ps
CPU time 31.64 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:48 PM PDT 24
Peak memory 217048 kb
Host smart-0a9bb6de-5086-4f16-8891-bee7bf215e4b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1253410206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.1253410206
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.2556903799
Short name T1984
Test name
Test status
Simulation time 156864896 ps
CPU time 0.85 seconds
Started Aug 07 06:03:11 PM PDT 24
Finished Aug 07 06:03:12 PM PDT 24
Peak memory 206960 kb
Host smart-abbf8618-bc0c-47c0-ab5e-05ce59198a19
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2556903799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.2556903799
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1137186523
Short name T1009
Test name
Test status
Simulation time 144050954 ps
CPU time 0.85 seconds
Started Aug 07 06:03:13 PM PDT 24
Finished Aug 07 06:03:14 PM PDT 24
Peak memory 206908 kb
Host smart-19a9cdb6-9af4-459d-a0c4-0175699a571d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11371
86523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1137186523
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.433891435
Short name T2926
Test name
Test status
Simulation time 207862401 ps
CPU time 0.98 seconds
Started Aug 07 06:03:15 PM PDT 24
Finished Aug 07 06:03:16 PM PDT 24
Peak memory 207012 kb
Host smart-d5ec8447-3945-4afd-885a-4ccb56e03168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43389
1435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.433891435
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.3749251254
Short name T822
Test name
Test status
Simulation time 176715958 ps
CPU time 0.94 seconds
Started Aug 07 06:03:12 PM PDT 24
Finished Aug 07 06:03:13 PM PDT 24
Peak memory 206960 kb
Host smart-69609f5e-acce-4ce7-9307-38dd69e7b670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37492
51254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3749251254
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2070809712
Short name T2992
Test name
Test status
Simulation time 162282784 ps
CPU time 0.94 seconds
Started Aug 07 06:03:17 PM PDT 24
Finished Aug 07 06:03:18 PM PDT 24
Peak memory 206972 kb
Host smart-f92f26ce-bfe2-4e9f-be0e-08423b28c00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20708
09712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2070809712
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.604291231
Short name T2363
Test name
Test status
Simulation time 201511854 ps
CPU time 0.92 seconds
Started Aug 07 06:03:17 PM PDT 24
Finished Aug 07 06:03:18 PM PDT 24
Peak memory 206988 kb
Host smart-349e3604-b6e5-42c6-9c3a-641d6d5c575d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60429
1231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.604291231
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3729942221
Short name T190
Test name
Test status
Simulation time 152856545 ps
CPU time 0.85 seconds
Started Aug 07 06:03:20 PM PDT 24
Finished Aug 07 06:03:21 PM PDT 24
Peak memory 206968 kb
Host smart-c73f0a46-0bc5-477e-a8f5-a1e374165113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37299
42221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3729942221
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.588734975
Short name T1719
Test name
Test status
Simulation time 219171370 ps
CPU time 0.99 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 206996 kb
Host smart-9890e3a2-ac2f-42e0-8e5d-5f7416137833
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=588734975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.588734975
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.552133196
Short name T2730
Test name
Test status
Simulation time 151646968 ps
CPU time 0.85 seconds
Started Aug 07 06:03:18 PM PDT 24
Finished Aug 07 06:03:19 PM PDT 24
Peak memory 206852 kb
Host smart-059c6407-8385-49f3-bd15-b4ac3bc43f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55213
3196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.552133196
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2278665032
Short name T26
Test name
Test status
Simulation time 38919000 ps
CPU time 0.66 seconds
Started Aug 07 06:03:17 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 206984 kb
Host smart-ac5d1814-d7d1-4f29-ae12-ac5408bf5f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22786
65032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2278665032
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1475487113
Short name T298
Test name
Test status
Simulation time 8069938003 ps
CPU time 20.9 seconds
Started Aug 07 06:03:17 PM PDT 24
Finished Aug 07 06:03:38 PM PDT 24
Peak memory 215488 kb
Host smart-088785b4-b7f2-410d-a727-8de71a15c9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14754
87113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1475487113
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3288550097
Short name T2529
Test name
Test status
Simulation time 181097486 ps
CPU time 0.89 seconds
Started Aug 07 06:03:15 PM PDT 24
Finished Aug 07 06:03:16 PM PDT 24
Peak memory 206972 kb
Host smart-b8bae92f-28ef-469f-a100-01b50f3d7cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32885
50097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3288550097
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3036494602
Short name T2264
Test name
Test status
Simulation time 236663000 ps
CPU time 0.96 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 206904 kb
Host smart-2eea64af-5aad-4fd4-ba6a-bb654a06c517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30364
94602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3036494602
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3847964837
Short name T997
Test name
Test status
Simulation time 243210554 ps
CPU time 0.99 seconds
Started Aug 07 06:03:18 PM PDT 24
Finished Aug 07 06:03:19 PM PDT 24
Peak memory 206944 kb
Host smart-e9d8186d-fb76-4a1c-bd87-0e7d95322fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38479
64837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3847964837
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2036257524
Short name T3104
Test name
Test status
Simulation time 171302623 ps
CPU time 0.9 seconds
Started Aug 07 06:03:18 PM PDT 24
Finished Aug 07 06:03:19 PM PDT 24
Peak memory 206884 kb
Host smart-469feffb-6b59-4f9e-bbd7-fd86ebbedad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20362
57524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2036257524
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3351236105
Short name T1829
Test name
Test status
Simulation time 142147622 ps
CPU time 0.83 seconds
Started Aug 07 06:03:17 PM PDT 24
Finished Aug 07 06:03:18 PM PDT 24
Peak memory 206924 kb
Host smart-2acff6c2-5d91-4717-8748-184a6204cade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33512
36105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3351236105
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_rx_full.3994497026
Short name T1413
Test name
Test status
Simulation time 350051202 ps
CPU time 1.35 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 206988 kb
Host smart-c60e9ced-65bc-46a4-9336-e0b6b6067066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39944
97026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.3994497026
Directory /workspace/24.usbdev_rx_full/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.282456525
Short name T3066
Test name
Test status
Simulation time 177428338 ps
CPU time 0.89 seconds
Started Aug 07 06:03:18 PM PDT 24
Finished Aug 07 06:03:20 PM PDT 24
Peak memory 206872 kb
Host smart-eaaedd28-9baa-429f-8799-b2c469428905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28245
6525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.282456525
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.911661813
Short name T1089
Test name
Test status
Simulation time 148278237 ps
CPU time 0.82 seconds
Started Aug 07 06:03:17 PM PDT 24
Finished Aug 07 06:03:18 PM PDT 24
Peak memory 206968 kb
Host smart-67d2bd41-0f5e-44da-9fe8-27cb1b9a70e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91166
1813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.911661813
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3202442103
Short name T2885
Test name
Test status
Simulation time 245520520 ps
CPU time 1.06 seconds
Started Aug 07 06:03:17 PM PDT 24
Finished Aug 07 06:03:18 PM PDT 24
Peak memory 206964 kb
Host smart-4722eadf-c80e-45df-830f-aa28dbff58a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32024
42103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3202442103
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1906251160
Short name T1334
Test name
Test status
Simulation time 2599108837 ps
CPU time 73.21 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:04:29 PM PDT 24
Peak memory 217064 kb
Host smart-18c0913e-0f0d-47ae-937b-68d6861ddd06
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1906251160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1906251160
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3607794906
Short name T1828
Test name
Test status
Simulation time 178427101 ps
CPU time 0.98 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 206968 kb
Host smart-0c218c4b-ed67-499f-8cce-306b62caea86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36077
94906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3607794906
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3965408633
Short name T1391
Test name
Test status
Simulation time 242911671 ps
CPU time 0.95 seconds
Started Aug 07 06:03:18 PM PDT 24
Finished Aug 07 06:03:19 PM PDT 24
Peak memory 206984 kb
Host smart-eb18c288-6200-4956-b2e9-fe5cc9fc791a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39654
08633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3965408633
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.4224707084
Short name T993
Test name
Test status
Simulation time 1015291792 ps
CPU time 2.64 seconds
Started Aug 07 06:03:23 PM PDT 24
Finished Aug 07 06:03:26 PM PDT 24
Peak memory 207184 kb
Host smart-19f20039-2eaf-4ee9-86c1-3dbad40ede82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42247
07084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.4224707084
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.718329407
Short name T2710
Test name
Test status
Simulation time 2156961944 ps
CPU time 22.87 seconds
Started Aug 07 06:03:18 PM PDT 24
Finished Aug 07 06:03:41 PM PDT 24
Peak memory 216872 kb
Host smart-682ef9b7-bef3-48f4-ad69-706b43c66088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71832
9407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.718329407
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.434214111
Short name T1680
Test name
Test status
Simulation time 614261503 ps
CPU time 4.74 seconds
Started Aug 07 06:03:16 PM PDT 24
Finished Aug 07 06:03:21 PM PDT 24
Peak memory 207176 kb
Host smart-36b88b55-e958-44e8-a3b3-df958c31ffa6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434214111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_host
_handshake.434214111
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.3700588593
Short name T3112
Test name
Test status
Simulation time 33920651 ps
CPU time 0.67 seconds
Started Aug 07 06:03:41 PM PDT 24
Finished Aug 07 06:03:42 PM PDT 24
Peak memory 207052 kb
Host smart-6adc8f8c-e740-4ecd-a5b6-c02396d20249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3700588593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.3700588593
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1958092639
Short name T604
Test name
Test status
Simulation time 4155324255 ps
CPU time 5.44 seconds
Started Aug 07 06:03:31 PM PDT 24
Finished Aug 07 06:03:37 PM PDT 24
Peak memory 215488 kb
Host smart-d595074b-51c3-4c40-a21a-83e98a645989
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958092639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.1958092639
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.387316771
Short name T1978
Test name
Test status
Simulation time 20965910836 ps
CPU time 24.79 seconds
Started Aug 07 06:03:38 PM PDT 24
Finished Aug 07 06:04:03 PM PDT 24
Peak memory 207296 kb
Host smart-7efa5057-bc00-4639-bc41-a0551348a603
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=387316771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.387316771
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1409825991
Short name T1676
Test name
Test status
Simulation time 24588209394 ps
CPU time 31.33 seconds
Started Aug 07 06:03:32 PM PDT 24
Finished Aug 07 06:04:03 PM PDT 24
Peak memory 215468 kb
Host smart-ec0481ba-dd71-44c7-b1ff-85a49fde9663
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409825991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.1409825991
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2995022341
Short name T1474
Test name
Test status
Simulation time 172320684 ps
CPU time 0.85 seconds
Started Aug 07 06:03:26 PM PDT 24
Finished Aug 07 06:03:27 PM PDT 24
Peak memory 206996 kb
Host smart-6f1e98c0-7166-4b91-bf97-83eddb76c4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29950
22341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2995022341
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.4003194865
Short name T1325
Test name
Test status
Simulation time 154077117 ps
CPU time 0.84 seconds
Started Aug 07 06:03:25 PM PDT 24
Finished Aug 07 06:03:26 PM PDT 24
Peak memory 206908 kb
Host smart-0e84e068-34fd-46b8-89e0-e21b8ae294cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40031
94865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.4003194865
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.524054308
Short name T1993
Test name
Test status
Simulation time 441674269 ps
CPU time 1.58 seconds
Started Aug 07 06:03:34 PM PDT 24
Finished Aug 07 06:03:36 PM PDT 24
Peak memory 207012 kb
Host smart-1ec576c6-abcf-47b7-afa5-b4d337587df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52405
4308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.524054308
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2984786800
Short name T1661
Test name
Test status
Simulation time 870715589 ps
CPU time 2.35 seconds
Started Aug 07 06:03:24 PM PDT 24
Finished Aug 07 06:03:27 PM PDT 24
Peak memory 207200 kb
Host smart-013ae721-a9fd-4aee-b081-cff43595deb4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2984786800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2984786800
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.786445258
Short name T1918
Test name
Test status
Simulation time 46181581335 ps
CPU time 73.9 seconds
Started Aug 07 06:03:25 PM PDT 24
Finished Aug 07 06:04:39 PM PDT 24
Peak memory 207288 kb
Host smart-c1614f19-fc26-44a4-ba32-c86a2557b465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78644
5258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.786445258
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.3192182812
Short name T1703
Test name
Test status
Simulation time 2994846346 ps
CPU time 24.55 seconds
Started Aug 07 06:03:37 PM PDT 24
Finished Aug 07 06:04:01 PM PDT 24
Peak memory 207344 kb
Host smart-ddc018d8-0dae-4688-9296-17f20d5148d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192182812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.3192182812
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1876492433
Short name T1410
Test name
Test status
Simulation time 904696913 ps
CPU time 1.99 seconds
Started Aug 07 06:03:40 PM PDT 24
Finished Aug 07 06:03:42 PM PDT 24
Peak memory 206984 kb
Host smart-8c034e8c-5720-4fda-8175-7f9dabfbe888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18764
92433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1876492433
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1764952935
Short name T1259
Test name
Test status
Simulation time 185951023 ps
CPU time 0.92 seconds
Started Aug 07 06:03:43 PM PDT 24
Finished Aug 07 06:03:44 PM PDT 24
Peak memory 206988 kb
Host smart-93e67ccf-3532-479b-995b-3b6631b97b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17649
52935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1764952935
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.802541989
Short name T1237
Test name
Test status
Simulation time 75386740 ps
CPU time 0.73 seconds
Started Aug 07 06:03:31 PM PDT 24
Finished Aug 07 06:03:32 PM PDT 24
Peak memory 206876 kb
Host smart-08e74ee2-4a66-47fd-a7c8-c09ac20db9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80254
1989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.802541989
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.4007425442
Short name T2228
Test name
Test status
Simulation time 948769669 ps
CPU time 2.65 seconds
Started Aug 07 06:03:29 PM PDT 24
Finished Aug 07 06:03:31 PM PDT 24
Peak memory 207196 kb
Host smart-6307ba30-cf2a-41d9-aedb-8ae8bb279b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40074
25442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.4007425442
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_types.3803460111
Short name T437
Test name
Test status
Simulation time 403383262 ps
CPU time 1.41 seconds
Started Aug 07 06:03:29 PM PDT 24
Finished Aug 07 06:03:30 PM PDT 24
Peak memory 206932 kb
Host smart-dd1c92be-610d-403e-abe6-8bebc7103852
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3803460111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.3803460111
Directory /workspace/25.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2962742328
Short name T2820
Test name
Test status
Simulation time 321016176 ps
CPU time 2.23 seconds
Started Aug 07 06:03:40 PM PDT 24
Finished Aug 07 06:03:43 PM PDT 24
Peak memory 207140 kb
Host smart-fd86655d-9a58-4e80-978a-ec1e7ec8d921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29627
42328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2962742328
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.953058866
Short name T1396
Test name
Test status
Simulation time 161631409 ps
CPU time 0.88 seconds
Started Aug 07 06:03:30 PM PDT 24
Finished Aug 07 06:03:31 PM PDT 24
Peak memory 206912 kb
Host smart-c4eb1f6f-3f3e-4639-bd53-25c47b710412
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=953058866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.953058866
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2748184678
Short name T2637
Test name
Test status
Simulation time 139778479 ps
CPU time 0.86 seconds
Started Aug 07 06:03:31 PM PDT 24
Finished Aug 07 06:03:32 PM PDT 24
Peak memory 206828 kb
Host smart-da9ef3bf-1a2b-448b-9285-3f9b7f970064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27481
84678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2748184678
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3494099248
Short name T629
Test name
Test status
Simulation time 226939790 ps
CPU time 0.95 seconds
Started Aug 07 06:03:27 PM PDT 24
Finished Aug 07 06:03:28 PM PDT 24
Peak memory 206976 kb
Host smart-31df4577-eef2-45b1-b346-df1ed03d55cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34940
99248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3494099248
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.2661993476
Short name T123
Test name
Test status
Simulation time 4588315795 ps
CPU time 33.53 seconds
Started Aug 07 06:03:44 PM PDT 24
Finished Aug 07 06:04:18 PM PDT 24
Peak memory 215484 kb
Host smart-c7426834-94df-443d-90be-9a09d10ecfd9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2661993476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2661993476
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.1657318446
Short name T2156
Test name
Test status
Simulation time 4287458125 ps
CPU time 26.8 seconds
Started Aug 07 06:03:42 PM PDT 24
Finished Aug 07 06:04:09 PM PDT 24
Peak memory 207260 kb
Host smart-205a39ae-d09c-483e-b9eb-d694bc3db5a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1657318446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.1657318446
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3385002603
Short name T977
Test name
Test status
Simulation time 257542817 ps
CPU time 0.98 seconds
Started Aug 07 06:03:37 PM PDT 24
Finished Aug 07 06:03:38 PM PDT 24
Peak memory 207016 kb
Host smart-0ad0dc8e-4743-4c51-862a-aa937b8d770b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33850
02603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3385002603
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.3275652756
Short name T2968
Test name
Test status
Simulation time 14323333995 ps
CPU time 23.31 seconds
Started Aug 07 06:03:28 PM PDT 24
Finished Aug 07 06:03:52 PM PDT 24
Peak memory 207260 kb
Host smart-6f4cc307-7248-402f-8423-a5a1ba2c0ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32756
52756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.3275652756
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.3995684878
Short name T2314
Test name
Test status
Simulation time 3479672953 ps
CPU time 5.02 seconds
Started Aug 07 06:03:41 PM PDT 24
Finished Aug 07 06:03:46 PM PDT 24
Peak memory 215552 kb
Host smart-4d2be1c0-9529-4795-b4e5-37f1f40c3cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39956
84878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.3995684878
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.3047990632
Short name T1514
Test name
Test status
Simulation time 4501586576 ps
CPU time 42.34 seconds
Started Aug 07 06:03:31 PM PDT 24
Finished Aug 07 06:04:13 PM PDT 24
Peak memory 217904 kb
Host smart-90b49439-545a-47ea-8a2e-0e8303ae48ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30479
90632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3047990632
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.2508551197
Short name T607
Test name
Test status
Simulation time 3488966653 ps
CPU time 104.64 seconds
Started Aug 07 06:03:41 PM PDT 24
Finished Aug 07 06:05:27 PM PDT 24
Peak memory 217048 kb
Host smart-f6d16915-0bd1-4bf7-b796-9c6ae9f8d8e1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2508551197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.2508551197
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1495588983
Short name T2388
Test name
Test status
Simulation time 241553049 ps
CPU time 0.99 seconds
Started Aug 07 06:03:31 PM PDT 24
Finished Aug 07 06:03:32 PM PDT 24
Peak memory 206904 kb
Host smart-b3b959b4-a328-40e4-afe1-de85b03ab32a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1495588983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1495588983
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2839094274
Short name T677
Test name
Test status
Simulation time 237229709 ps
CPU time 0.99 seconds
Started Aug 07 06:03:46 PM PDT 24
Finished Aug 07 06:03:47 PM PDT 24
Peak memory 207004 kb
Host smart-fd628481-62dd-49fa-bcf9-717c4f71b4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28390
94274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2839094274
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.212442619
Short name T845
Test name
Test status
Simulation time 3245531267 ps
CPU time 33.23 seconds
Started Aug 07 06:03:39 PM PDT 24
Finished Aug 07 06:04:13 PM PDT 24
Peak memory 215540 kb
Host smart-1ecf6376-c122-420e-9a06-d73808a3889a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=212442619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.212442619
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2232775568
Short name T2833
Test name
Test status
Simulation time 157695877 ps
CPU time 0.88 seconds
Started Aug 07 06:03:43 PM PDT 24
Finished Aug 07 06:03:44 PM PDT 24
Peak memory 207020 kb
Host smart-b836ce22-eefa-4e7b-8d54-53e556708b88
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2232775568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2232775568
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2048113927
Short name T2097
Test name
Test status
Simulation time 157462941 ps
CPU time 0.84 seconds
Started Aug 07 06:03:31 PM PDT 24
Finished Aug 07 06:03:32 PM PDT 24
Peak memory 206920 kb
Host smart-ba4587fd-7491-4351-80b0-acd37bc28a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20481
13927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2048113927
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3642821006
Short name T159
Test name
Test status
Simulation time 203065153 ps
CPU time 1 seconds
Started Aug 07 06:03:43 PM PDT 24
Finished Aug 07 06:03:44 PM PDT 24
Peak memory 207008 kb
Host smart-729912d3-6e0a-4fbd-a2e9-7bee5c2adcc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36428
21006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3642821006
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.287598266
Short name T2305
Test name
Test status
Simulation time 180235648 ps
CPU time 0.9 seconds
Started Aug 07 06:03:33 PM PDT 24
Finished Aug 07 06:03:34 PM PDT 24
Peak memory 207192 kb
Host smart-6d16abda-6a9e-4cb1-bd2b-7b1f77eed85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28759
8266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.287598266
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3263651368
Short name T129
Test name
Test status
Simulation time 249091962 ps
CPU time 0.97 seconds
Started Aug 07 06:03:44 PM PDT 24
Finished Aug 07 06:03:46 PM PDT 24
Peak memory 206992 kb
Host smart-3f2ea6ab-3aef-4e6c-8344-ec7fb10f8247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32636
51368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3263651368
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.4018370787
Short name T3095
Test name
Test status
Simulation time 193970923 ps
CPU time 0.91 seconds
Started Aug 07 06:03:35 PM PDT 24
Finished Aug 07 06:03:36 PM PDT 24
Peak memory 206956 kb
Host smart-6ac92fd4-e875-438a-8c95-5fde69ecbc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40183
70787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.4018370787
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3289842130
Short name T185
Test name
Test status
Simulation time 190747480 ps
CPU time 0.94 seconds
Started Aug 07 06:03:35 PM PDT 24
Finished Aug 07 06:03:36 PM PDT 24
Peak memory 207040 kb
Host smart-afd32c37-ccf2-4c93-9d1c-cb06e310eda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32898
42130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3289842130
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.1538515618
Short name T2978
Test name
Test status
Simulation time 197691651 ps
CPU time 0.95 seconds
Started Aug 07 06:03:44 PM PDT 24
Finished Aug 07 06:03:45 PM PDT 24
Peak memory 206984 kb
Host smart-f5418843-3bce-4a00-982c-33a7932ace70
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1538515618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.1538515618
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.675374581
Short name T2686
Test name
Test status
Simulation time 207075084 ps
CPU time 0.88 seconds
Started Aug 07 06:03:35 PM PDT 24
Finished Aug 07 06:03:36 PM PDT 24
Peak memory 206956 kb
Host smart-5fce172a-c2fc-47b8-81d3-99ac45a83f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67537
4581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.675374581
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.4031797988
Short name T1433
Test name
Test status
Simulation time 35627079 ps
CPU time 0.7 seconds
Started Aug 07 06:03:36 PM PDT 24
Finished Aug 07 06:03:37 PM PDT 24
Peak memory 206912 kb
Host smart-4bd1999e-fe73-435e-a148-87b543b201a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40317
97988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.4031797988
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.4002724193
Short name T2682
Test name
Test status
Simulation time 11363178925 ps
CPU time 29.6 seconds
Started Aug 07 06:03:34 PM PDT 24
Finished Aug 07 06:04:04 PM PDT 24
Peak memory 215488 kb
Host smart-b3401727-43ac-4bad-94da-f59c8e2714fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40027
24193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.4002724193
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2624652284
Short name T527
Test name
Test status
Simulation time 203805895 ps
CPU time 0.98 seconds
Started Aug 07 06:03:38 PM PDT 24
Finished Aug 07 06:03:39 PM PDT 24
Peak memory 206952 kb
Host smart-468836dc-9ce9-4eb4-bd6c-036d693f97c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26246
52284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2624652284
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.870989667
Short name T1028
Test name
Test status
Simulation time 238639351 ps
CPU time 1 seconds
Started Aug 07 06:03:39 PM PDT 24
Finished Aug 07 06:03:40 PM PDT 24
Peak memory 206948 kb
Host smart-8e3a739e-705c-4d2d-a2ff-9e26d21c46b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87098
9667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.870989667
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3418574438
Short name T1020
Test name
Test status
Simulation time 216293490 ps
CPU time 1.02 seconds
Started Aug 07 06:03:33 PM PDT 24
Finished Aug 07 06:03:34 PM PDT 24
Peak memory 206964 kb
Host smart-d661c11c-b002-4bc1-b039-d01070f36d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34185
74438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3418574438
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.4084147442
Short name T99
Test name
Test status
Simulation time 186616051 ps
CPU time 0.92 seconds
Started Aug 07 06:03:34 PM PDT 24
Finished Aug 07 06:03:35 PM PDT 24
Peak memory 207004 kb
Host smart-701c6b73-28ea-4d86-875b-190d20c9c78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40841
47442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.4084147442
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1969704200
Short name T1573
Test name
Test status
Simulation time 171546698 ps
CPU time 0.88 seconds
Started Aug 07 06:03:41 PM PDT 24
Finished Aug 07 06:03:43 PM PDT 24
Peak memory 207016 kb
Host smart-b1cb4cdb-d281-43ad-a9aa-ddaaa365542c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19697
04200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1969704200
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_rx_full.536002643
Short name T2635
Test name
Test status
Simulation time 348519986 ps
CPU time 1.2 seconds
Started Aug 07 06:03:39 PM PDT 24
Finished Aug 07 06:03:40 PM PDT 24
Peak memory 206980 kb
Host smart-a776db25-9463-4a74-b89c-8e362bb89d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53600
2643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.536002643
Directory /workspace/25.usbdev_rx_full/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.212388350
Short name T1967
Test name
Test status
Simulation time 144925695 ps
CPU time 0.87 seconds
Started Aug 07 06:03:36 PM PDT 24
Finished Aug 07 06:03:37 PM PDT 24
Peak memory 206948 kb
Host smart-db91749f-ae4f-4ccc-b44d-6a40d008ed93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21238
8350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.212388350
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2589962967
Short name T1988
Test name
Test status
Simulation time 155009044 ps
CPU time 0.85 seconds
Started Aug 07 06:03:43 PM PDT 24
Finished Aug 07 06:03:44 PM PDT 24
Peak memory 206980 kb
Host smart-b2a5c474-cef8-4de0-8a7f-c42b96096d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25899
62967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2589962967
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.349923065
Short name T3068
Test name
Test status
Simulation time 226187846 ps
CPU time 0.95 seconds
Started Aug 07 06:03:34 PM PDT 24
Finished Aug 07 06:03:35 PM PDT 24
Peak memory 207000 kb
Host smart-045b0ed6-b331-4a44-bf4d-312b544ea592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34992
3065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.349923065
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.444210535
Short name T1790
Test name
Test status
Simulation time 2907967690 ps
CPU time 78.37 seconds
Started Aug 07 06:03:39 PM PDT 24
Finished Aug 07 06:04:58 PM PDT 24
Peak memory 223688 kb
Host smart-25476382-85de-4bdd-aa0c-d3a6240bb41f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=444210535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.444210535
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2657723818
Short name T1907
Test name
Test status
Simulation time 173273635 ps
CPU time 0.87 seconds
Started Aug 07 06:03:35 PM PDT 24
Finished Aug 07 06:03:36 PM PDT 24
Peak memory 207008 kb
Host smart-9b0dc37b-c2ba-4c77-af66-52aa7e38efc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26577
23818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2657723818
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1840361823
Short name T788
Test name
Test status
Simulation time 161119558 ps
CPU time 0.85 seconds
Started Aug 07 06:03:48 PM PDT 24
Finished Aug 07 06:03:49 PM PDT 24
Peak memory 206944 kb
Host smart-2f53112a-2094-48d0-b160-dbf2fe33f41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18403
61823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1840361823
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.3000712889
Short name T650
Test name
Test status
Simulation time 450582015 ps
CPU time 1.5 seconds
Started Aug 07 06:03:40 PM PDT 24
Finished Aug 07 06:03:42 PM PDT 24
Peak memory 206916 kb
Host smart-f9d801d4-f69a-4bff-98d0-84567f485c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30007
12889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.3000712889
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.4240758885
Short name T2132
Test name
Test status
Simulation time 2374327507 ps
CPU time 18.48 seconds
Started Aug 07 06:03:44 PM PDT 24
Finished Aug 07 06:04:03 PM PDT 24
Peak memory 217116 kb
Host smart-dd698858-ffdd-4a3b-adbd-4fd0adbd7232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42407
58885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.4240758885
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.726857523
Short name T3051
Test name
Test status
Simulation time 1194311489 ps
CPU time 25.83 seconds
Started Aug 07 06:03:28 PM PDT 24
Finished Aug 07 06:03:54 PM PDT 24
Peak memory 207216 kb
Host smart-4e525096-863e-457a-b645-5aff337823da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726857523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_host
_handshake.726857523
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2591572932
Short name T2608
Test name
Test status
Simulation time 46526102 ps
CPU time 0.65 seconds
Started Aug 07 06:03:56 PM PDT 24
Finished Aug 07 06:03:57 PM PDT 24
Peak memory 207088 kb
Host smart-a6218527-8b6d-472c-8356-654907c7d733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2591572932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2591572932
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1003702377
Short name T1579
Test name
Test status
Simulation time 10372407628 ps
CPU time 12.75 seconds
Started Aug 07 06:03:41 PM PDT 24
Finished Aug 07 06:03:54 PM PDT 24
Peak memory 207328 kb
Host smart-82bac5ad-7820-4f0c-9245-ea5ec7814628
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003702377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.1003702377
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2184543126
Short name T1058
Test name
Test status
Simulation time 15541894090 ps
CPU time 22.28 seconds
Started Aug 07 06:03:41 PM PDT 24
Finished Aug 07 06:04:04 PM PDT 24
Peak memory 215448 kb
Host smart-22713f3b-4286-4a83-91ff-406fb6c00340
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184543126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2184543126
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2320620282
Short name T112
Test name
Test status
Simulation time 30672073127 ps
CPU time 38.82 seconds
Started Aug 07 06:03:51 PM PDT 24
Finished Aug 07 06:04:30 PM PDT 24
Peak memory 207276 kb
Host smart-5cea61bd-9240-4f7d-8295-1aa1e7da8372
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320620282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.2320620282
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.656919925
Short name T2071
Test name
Test status
Simulation time 199485970 ps
CPU time 0.95 seconds
Started Aug 07 06:03:53 PM PDT 24
Finished Aug 07 06:03:54 PM PDT 24
Peak memory 206896 kb
Host smart-08e36d6d-c692-452d-98c1-62eb53d94c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65691
9925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.656919925
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3735678384
Short name T2545
Test name
Test status
Simulation time 152581534 ps
CPU time 0.86 seconds
Started Aug 07 06:03:41 PM PDT 24
Finished Aug 07 06:03:42 PM PDT 24
Peak memory 206948 kb
Host smart-7c3b4827-c50d-4da8-bfc1-4c31e74bf0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37356
78384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3735678384
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.1364795756
Short name T529
Test name
Test status
Simulation time 160665653 ps
CPU time 0.88 seconds
Started Aug 07 06:03:51 PM PDT 24
Finished Aug 07 06:03:52 PM PDT 24
Peak memory 207004 kb
Host smart-1b185314-d70e-4cf9-bac0-87c4585557b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13647
95756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.1364795756
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.987464243
Short name T1326
Test name
Test status
Simulation time 1037227953 ps
CPU time 2.76 seconds
Started Aug 07 06:03:43 PM PDT 24
Finished Aug 07 06:03:46 PM PDT 24
Peak memory 207224 kb
Host smart-a490ac35-5122-44f3-b590-0875421e06f9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=987464243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.987464243
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.182031339
Short name T89
Test name
Test status
Simulation time 33054283782 ps
CPU time 55.64 seconds
Started Aug 07 06:03:45 PM PDT 24
Finished Aug 07 06:04:41 PM PDT 24
Peak memory 207396 kb
Host smart-b99a6c2a-dbb9-4000-8735-32859d4d7f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18203
1339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.182031339
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.498620289
Short name T2709
Test name
Test status
Simulation time 1556967258 ps
CPU time 13.35 seconds
Started Aug 07 06:03:47 PM PDT 24
Finished Aug 07 06:04:00 PM PDT 24
Peak memory 207132 kb
Host smart-45079ffd-6342-420f-b3c3-d1e7cad1bdba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498620289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.498620289
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.174156783
Short name T2325
Test name
Test status
Simulation time 745410078 ps
CPU time 1.78 seconds
Started Aug 07 06:03:42 PM PDT 24
Finished Aug 07 06:03:44 PM PDT 24
Peak memory 206948 kb
Host smart-0cadcfb6-c457-4df0-9147-283c9f9981bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17415
6783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.174156783
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1037045200
Short name T1508
Test name
Test status
Simulation time 164099158 ps
CPU time 0.93 seconds
Started Aug 07 06:03:46 PM PDT 24
Finished Aug 07 06:03:47 PM PDT 24
Peak memory 206872 kb
Host smart-b492037c-8a3a-4c87-a7bb-8263c72c8fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
45200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1037045200
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.4210204520
Short name T2180
Test name
Test status
Simulation time 38187144 ps
CPU time 0.71 seconds
Started Aug 07 06:03:54 PM PDT 24
Finished Aug 07 06:03:55 PM PDT 24
Peak memory 206856 kb
Host smart-369a3d1b-7dda-42ca-a53c-1c93435567dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42102
04520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.4210204520
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.1536223009
Short name T1445
Test name
Test status
Simulation time 973667701 ps
CPU time 2.53 seconds
Started Aug 07 06:03:42 PM PDT 24
Finished Aug 07 06:03:45 PM PDT 24
Peak memory 207188 kb
Host smart-ed943472-8c38-407d-85e4-a0495106b4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15362
23009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.1536223009
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_types.4211611289
Short name T120
Test name
Test status
Simulation time 528630894 ps
CPU time 1.33 seconds
Started Aug 07 06:03:52 PM PDT 24
Finished Aug 07 06:03:54 PM PDT 24
Peak memory 206888 kb
Host smart-ec1e0ab7-f76a-471e-bfc6-80fc5a7026a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4211611289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.4211611289
Directory /workspace/26.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3702944983
Short name T20
Test name
Test status
Simulation time 178706832 ps
CPU time 1.86 seconds
Started Aug 07 06:03:39 PM PDT 24
Finished Aug 07 06:03:41 PM PDT 24
Peak memory 207132 kb
Host smart-ded62c7c-8304-47e1-addf-12028de27170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37029
44983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3702944983
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3434313607
Short name T2685
Test name
Test status
Simulation time 217384493 ps
CPU time 1.12 seconds
Started Aug 07 06:03:46 PM PDT 24
Finished Aug 07 06:03:48 PM PDT 24
Peak memory 215388 kb
Host smart-4f2a5026-48bb-49f8-aad0-bced7ee0e91d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3434313607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3434313607
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3163451946
Short name T2056
Test name
Test status
Simulation time 154907580 ps
CPU time 0.82 seconds
Started Aug 07 06:03:50 PM PDT 24
Finished Aug 07 06:03:51 PM PDT 24
Peak memory 206940 kb
Host smart-834b4863-ef3c-4563-bd0c-78febaf7a20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31634
51946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3163451946
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3368143989
Short name T1963
Test name
Test status
Simulation time 255186924 ps
CPU time 1.11 seconds
Started Aug 07 06:03:50 PM PDT 24
Finished Aug 07 06:03:51 PM PDT 24
Peak memory 207000 kb
Host smart-1110068a-bbe0-490c-a0da-4d0b89dcfd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33681
43989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3368143989
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.4131000264
Short name T635
Test name
Test status
Simulation time 4792203359 ps
CPU time 47.43 seconds
Started Aug 07 06:03:46 PM PDT 24
Finished Aug 07 06:04:34 PM PDT 24
Peak memory 217868 kb
Host smart-0fbf8502-a8e9-4f27-8b84-fc45cc4d6177
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4131000264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.4131000264
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.3313812659
Short name T834
Test name
Test status
Simulation time 4185147428 ps
CPU time 51.66 seconds
Started Aug 07 06:03:45 PM PDT 24
Finished Aug 07 06:04:37 PM PDT 24
Peak memory 207304 kb
Host smart-617f4e95-540d-4318-b0bc-5cd63f3eb7df
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3313812659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.3313812659
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1071985140
Short name T572
Test name
Test status
Simulation time 174316102 ps
CPU time 0.96 seconds
Started Aug 07 06:03:45 PM PDT 24
Finished Aug 07 06:03:46 PM PDT 24
Peak memory 207040 kb
Host smart-0ffccb0d-d37b-457e-8b7c-e8c04ef5ee93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10719
85140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1071985140
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.1866395895
Short name T939
Test name
Test status
Simulation time 11712407960 ps
CPU time 15.96 seconds
Started Aug 07 06:03:42 PM PDT 24
Finished Aug 07 06:03:58 PM PDT 24
Peak memory 207308 kb
Host smart-b4b9b271-a669-4fcb-9add-25a124898e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18663
95895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.1866395895
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2793664359
Short name T917
Test name
Test status
Simulation time 6234658506 ps
CPU time 10.05 seconds
Started Aug 07 06:03:46 PM PDT 24
Finished Aug 07 06:03:56 PM PDT 24
Peak memory 215624 kb
Host smart-6701fd95-8bfa-455c-ac5b-0089066237bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27936
64359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2793664359
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.892586620
Short name T3118
Test name
Test status
Simulation time 3829779469 ps
CPU time 28.98 seconds
Started Aug 07 06:03:43 PM PDT 24
Finished Aug 07 06:04:12 PM PDT 24
Peak memory 216988 kb
Host smart-6710d47d-74c8-4a88-bb52-7e2c1917889c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89258
6620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.892586620
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1823451966
Short name T1571
Test name
Test status
Simulation time 2486925671 ps
CPU time 24.38 seconds
Started Aug 07 06:03:48 PM PDT 24
Finished Aug 07 06:04:13 PM PDT 24
Peak memory 223604 kb
Host smart-d31da955-9383-400e-9ce0-617572f29bf1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1823451966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1823451966
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.2826220629
Short name T1659
Test name
Test status
Simulation time 252294767 ps
CPU time 1.02 seconds
Started Aug 07 06:03:43 PM PDT 24
Finished Aug 07 06:03:44 PM PDT 24
Peak memory 206936 kb
Host smart-0dff4d20-5106-4d01-aba2-2c8110af9363
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2826220629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.2826220629
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.653811222
Short name T2774
Test name
Test status
Simulation time 198241382 ps
CPU time 0.96 seconds
Started Aug 07 06:03:47 PM PDT 24
Finished Aug 07 06:03:48 PM PDT 24
Peak memory 206976 kb
Host smart-3d97fb13-ad4c-429d-9da0-689ee188e576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65381
1222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.653811222
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.1275085956
Short name T2460
Test name
Test status
Simulation time 4207742296 ps
CPU time 31.9 seconds
Started Aug 07 06:03:53 PM PDT 24
Finished Aug 07 06:04:25 PM PDT 24
Peak memory 215436 kb
Host smart-b77dc6d5-5f92-48ec-af9d-70d14441355f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1275085956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.1275085956
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.1741249359
Short name T958
Test name
Test status
Simulation time 215915899 ps
CPU time 1 seconds
Started Aug 07 06:05:20 PM PDT 24
Finished Aug 07 06:05:21 PM PDT 24
Peak memory 206988 kb
Host smart-55e872cc-c4b0-45b7-aa73-af400107e5ec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1741249359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.1741249359
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1531434785
Short name T2416
Test name
Test status
Simulation time 157135830 ps
CPU time 0.89 seconds
Started Aug 07 06:03:50 PM PDT 24
Finished Aug 07 06:03:51 PM PDT 24
Peak memory 207012 kb
Host smart-23832383-f38f-4256-8cad-2aec7007b1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15314
34785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1531434785
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.142608713
Short name T146
Test name
Test status
Simulation time 227396235 ps
CPU time 0.93 seconds
Started Aug 07 06:03:44 PM PDT 24
Finished Aug 07 06:03:45 PM PDT 24
Peak memory 207004 kb
Host smart-25771ff0-c41d-4a2c-b724-6a2e7edaf3bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14260
8713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.142608713
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3968293967
Short name T1692
Test name
Test status
Simulation time 168906765 ps
CPU time 0.88 seconds
Started Aug 07 06:04:00 PM PDT 24
Finished Aug 07 06:04:01 PM PDT 24
Peak memory 206904 kb
Host smart-9b05f5ec-e900-4bc7-97eb-2952ace9e4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39682
93967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3968293967
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2600876754
Short name T2421
Test name
Test status
Simulation time 194628965 ps
CPU time 0.93 seconds
Started Aug 07 06:03:53 PM PDT 24
Finished Aug 07 06:03:54 PM PDT 24
Peak memory 206976 kb
Host smart-6d9f1eb0-618c-4949-ac4b-2e177ace2ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26008
76754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2600876754
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1862006244
Short name T1018
Test name
Test status
Simulation time 176976739 ps
CPU time 0.9 seconds
Started Aug 07 06:03:49 PM PDT 24
Finished Aug 07 06:03:50 PM PDT 24
Peak memory 206916 kb
Host smart-ef47ebbc-c6b9-4882-ae50-4396b29a6e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18620
06244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1862006244
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3994629475
Short name T2638
Test name
Test status
Simulation time 163282074 ps
CPU time 0.86 seconds
Started Aug 07 06:03:45 PM PDT 24
Finished Aug 07 06:03:46 PM PDT 24
Peak memory 206980 kb
Host smart-8bdbaa3d-248f-4e22-b920-c3b07186731a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39946
29475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3994629475
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1660775413
Short name T605
Test name
Test status
Simulation time 210326272 ps
CPU time 0.99 seconds
Started Aug 07 06:03:52 PM PDT 24
Finished Aug 07 06:03:53 PM PDT 24
Peak memory 207040 kb
Host smart-e0076dbd-7610-4ca3-83cc-d39d1d2e2d99
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1660775413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1660775413
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.4178191108
Short name T745
Test name
Test status
Simulation time 160945900 ps
CPU time 0.91 seconds
Started Aug 07 06:04:01 PM PDT 24
Finished Aug 07 06:04:02 PM PDT 24
Peak memory 206872 kb
Host smart-2280fcdd-ebd9-4815-8d64-74b76ff8c0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41781
91108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.4178191108
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.837477364
Short name T2458
Test name
Test status
Simulation time 47159951 ps
CPU time 0.71 seconds
Started Aug 07 06:04:01 PM PDT 24
Finished Aug 07 06:04:02 PM PDT 24
Peak memory 206872 kb
Host smart-72b32d6d-9690-4ae8-abf3-b5566ab46356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83747
7364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.837477364
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2278916625
Short name T1903
Test name
Test status
Simulation time 11010499375 ps
CPU time 29.56 seconds
Started Aug 07 06:03:48 PM PDT 24
Finished Aug 07 06:04:18 PM PDT 24
Peak memory 215696 kb
Host smart-0bd379ad-9a86-4c9d-bc5a-3012616842ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22789
16625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2278916625
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2126875500
Short name T1867
Test name
Test status
Simulation time 180967638 ps
CPU time 1.01 seconds
Started Aug 07 06:04:00 PM PDT 24
Finished Aug 07 06:04:02 PM PDT 24
Peak memory 206904 kb
Host smart-43daafc9-4c66-423c-9c7d-f0213973ba51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21268
75500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2126875500
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2183677205
Short name T2297
Test name
Test status
Simulation time 248208457 ps
CPU time 1.05 seconds
Started Aug 07 06:03:53 PM PDT 24
Finished Aug 07 06:03:54 PM PDT 24
Peak memory 207016 kb
Host smart-f9fc4876-2ac1-4c7d-98c3-e707d8b5fa3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21836
77205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2183677205
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1462911071
Short name T1553
Test name
Test status
Simulation time 229161714 ps
CPU time 0.92 seconds
Started Aug 07 06:03:56 PM PDT 24
Finished Aug 07 06:03:57 PM PDT 24
Peak memory 207016 kb
Host smart-4ffa9756-e459-484a-92d0-9c6fd470d2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14629
11071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1462911071
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.205692045
Short name T2662
Test name
Test status
Simulation time 162790682 ps
CPU time 0.9 seconds
Started Aug 07 06:03:48 PM PDT 24
Finished Aug 07 06:03:49 PM PDT 24
Peak memory 207036 kb
Host smart-f39e2bfc-5885-4e37-af1f-5bba2727aaf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20569
2045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.205692045
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1260540353
Short name T2198
Test name
Test status
Simulation time 149651964 ps
CPU time 0.87 seconds
Started Aug 07 06:03:52 PM PDT 24
Finished Aug 07 06:03:53 PM PDT 24
Peak memory 206920 kb
Host smart-c93e4639-a0e6-437e-af9e-50b39838d390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12605
40353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1260540353
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_rx_full.1853160067
Short name T2955
Test name
Test status
Simulation time 325311984 ps
CPU time 1.15 seconds
Started Aug 07 06:03:56 PM PDT 24
Finished Aug 07 06:03:57 PM PDT 24
Peak memory 206984 kb
Host smart-3032826b-1c31-493f-8348-f4461aac6740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18531
60067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.1853160067
Directory /workspace/26.usbdev_rx_full/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1987565767
Short name T1370
Test name
Test status
Simulation time 188051645 ps
CPU time 0.86 seconds
Started Aug 07 06:03:55 PM PDT 24
Finished Aug 07 06:03:56 PM PDT 24
Peak memory 206952 kb
Host smart-7ef0ef70-4173-4a72-a66a-fbb4db4b97fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19875
65767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1987565767
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1257800433
Short name T1851
Test name
Test status
Simulation time 221822654 ps
CPU time 1 seconds
Started Aug 07 06:04:05 PM PDT 24
Finished Aug 07 06:04:06 PM PDT 24
Peak memory 207008 kb
Host smart-10f8c450-81e9-4f29-987e-38de2379e2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12578
00433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1257800433
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.4027423151
Short name T639
Test name
Test status
Simulation time 330157178 ps
CPU time 1.14 seconds
Started Aug 07 06:03:52 PM PDT 24
Finished Aug 07 06:03:53 PM PDT 24
Peak memory 206960 kb
Host smart-ddab5518-1dfe-44bb-bec4-6e35e506e7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40274
23151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4027423151
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1601383659
Short name T1529
Test name
Test status
Simulation time 2138126808 ps
CPU time 60.82 seconds
Started Aug 07 06:04:05 PM PDT 24
Finished Aug 07 06:05:06 PM PDT 24
Peak memory 217220 kb
Host smart-be984266-9af7-4263-810f-20fe576da1a0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1601383659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1601383659
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1462882345
Short name T1390
Test name
Test status
Simulation time 234207340 ps
CPU time 0.97 seconds
Started Aug 07 06:03:50 PM PDT 24
Finished Aug 07 06:03:51 PM PDT 24
Peak memory 206968 kb
Host smart-ffc7e8b2-a910-4bfe-bb67-943b59d6c919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14628
82345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1462882345
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1503556726
Short name T3037
Test name
Test status
Simulation time 167646072 ps
CPU time 0.86 seconds
Started Aug 07 06:03:51 PM PDT 24
Finished Aug 07 06:03:52 PM PDT 24
Peak memory 206932 kb
Host smart-0e95b43f-c19b-40a6-800c-877b8472bf28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15035
56726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1503556726
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.3900565534
Short name T2086
Test name
Test status
Simulation time 1210981338 ps
CPU time 2.76 seconds
Started Aug 07 06:03:55 PM PDT 24
Finished Aug 07 06:03:58 PM PDT 24
Peak memory 207220 kb
Host smart-7d06d279-b173-483e-96e7-52fa13da0d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39005
65534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.3900565534
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2916018962
Short name T706
Test name
Test status
Simulation time 2339992138 ps
CPU time 64.05 seconds
Started Aug 07 06:03:53 PM PDT 24
Finished Aug 07 06:04:57 PM PDT 24
Peak memory 217248 kb
Host smart-250a5909-d134-422b-ba28-1ad033f36c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29160
18962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2916018962
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.3472361573
Short name T2067
Test name
Test status
Simulation time 1962808275 ps
CPU time 18.24 seconds
Started Aug 07 06:03:53 PM PDT 24
Finished Aug 07 06:04:11 PM PDT 24
Peak memory 207092 kb
Host smart-cd44e4e9-0e0b-4a31-ac10-d8d034bb29b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472361573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.3472361573
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3432725558
Short name T595
Test name
Test status
Simulation time 41696996 ps
CPU time 0.68 seconds
Started Aug 07 06:04:15 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 207080 kb
Host smart-55d30ff1-ff6d-4ad3-a77f-508e12fe98da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3432725558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3432725558
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2521739687
Short name T1180
Test name
Test status
Simulation time 13999927256 ps
CPU time 15.66 seconds
Started Aug 07 06:04:03 PM PDT 24
Finished Aug 07 06:04:19 PM PDT 24
Peak memory 215384 kb
Host smart-2d77a96e-1a3b-44f6-8a90-afe5edf0b210
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521739687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2521739687
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.2002989064
Short name T328
Test name
Test status
Simulation time 30291911919 ps
CPU time 42.96 seconds
Started Aug 07 06:03:55 PM PDT 24
Finished Aug 07 06:04:38 PM PDT 24
Peak memory 207316 kb
Host smart-55f09fc0-d274-42f8-9c7c-8e9404c57d3a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002989064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.2002989064
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.354156610
Short name T2227
Test name
Test status
Simulation time 209360784 ps
CPU time 0.96 seconds
Started Aug 07 06:03:56 PM PDT 24
Finished Aug 07 06:03:58 PM PDT 24
Peak memory 207012 kb
Host smart-245b4650-e164-41c3-939a-60b77c64c124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35415
6610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.354156610
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3395165712
Short name T959
Test name
Test status
Simulation time 158555395 ps
CPU time 0.89 seconds
Started Aug 07 06:03:55 PM PDT 24
Finished Aug 07 06:03:56 PM PDT 24
Peak memory 206928 kb
Host smart-1a02b903-354e-47c5-9b08-2b08b291e91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33951
65712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3395165712
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2884917189
Short name T919
Test name
Test status
Simulation time 192159341 ps
CPU time 0.95 seconds
Started Aug 07 06:03:59 PM PDT 24
Finished Aug 07 06:04:00 PM PDT 24
Peak memory 206984 kb
Host smart-14936914-ee52-4ae3-8ff7-e9a6efd8c25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28849
17189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2884917189
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2967353295
Short name T1934
Test name
Test status
Simulation time 871595956 ps
CPU time 2.54 seconds
Started Aug 07 06:04:05 PM PDT 24
Finished Aug 07 06:04:08 PM PDT 24
Peak memory 207184 kb
Host smart-6782c257-8db0-4b41-9325-31819b117e21
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2967353295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2967353295
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.3660695951
Short name T2094
Test name
Test status
Simulation time 27309244259 ps
CPU time 44.31 seconds
Started Aug 07 06:03:59 PM PDT 24
Finished Aug 07 06:04:43 PM PDT 24
Peak memory 207220 kb
Host smart-c7debdb5-4058-4d55-9a08-2016546e0f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36606
95951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3660695951
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.2960432590
Short name T2029
Test name
Test status
Simulation time 1162441480 ps
CPU time 25.89 seconds
Started Aug 07 06:03:57 PM PDT 24
Finished Aug 07 06:04:23 PM PDT 24
Peak memory 207200 kb
Host smart-17a604af-8be3-4183-96b6-408852efe257
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960432590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.2960432590
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3371303783
Short name T694
Test name
Test status
Simulation time 608186060 ps
CPU time 1.72 seconds
Started Aug 07 06:03:57 PM PDT 24
Finished Aug 07 06:03:59 PM PDT 24
Peak memory 207160 kb
Host smart-1d84b02d-cec6-4359-8801-f33b48f9df1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
03783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3371303783
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1176539239
Short name T2286
Test name
Test status
Simulation time 158909960 ps
CPU time 0.87 seconds
Started Aug 07 06:04:01 PM PDT 24
Finished Aug 07 06:04:02 PM PDT 24
Peak memory 206876 kb
Host smart-02814839-0392-4364-ad8f-897917741265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11765
39239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1176539239
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.3162496445
Short name T1671
Test name
Test status
Simulation time 48402788 ps
CPU time 0.73 seconds
Started Aug 07 06:03:54 PM PDT 24
Finished Aug 07 06:03:55 PM PDT 24
Peak memory 206868 kb
Host smart-a18e6df0-6eeb-4af6-a7bc-c412d913047f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31624
96445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3162496445
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.366829481
Short name T1183
Test name
Test status
Simulation time 792153967 ps
CPU time 2.14 seconds
Started Aug 07 06:04:01 PM PDT 24
Finished Aug 07 06:04:04 PM PDT 24
Peak memory 207232 kb
Host smart-bf1e0528-cf71-4c80-9736-c341fcb177e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36682
9481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.366829481
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_types.2544741352
Short name T2882
Test name
Test status
Simulation time 187225848 ps
CPU time 0.93 seconds
Started Aug 07 06:04:00 PM PDT 24
Finished Aug 07 06:04:01 PM PDT 24
Peak memory 206960 kb
Host smart-05808dc2-4671-49ca-8064-e470857a6ce4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2544741352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.2544741352
Directory /workspace/27.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1450275600
Short name T2407
Test name
Test status
Simulation time 283785510 ps
CPU time 2.61 seconds
Started Aug 07 06:04:02 PM PDT 24
Finished Aug 07 06:04:05 PM PDT 24
Peak memory 207120 kb
Host smart-20fd56e6-731a-4077-8ee0-d45bd94857a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14502
75600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1450275600
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.4163613684
Short name T1449
Test name
Test status
Simulation time 248523576 ps
CPU time 1.25 seconds
Started Aug 07 06:04:01 PM PDT 24
Finished Aug 07 06:04:02 PM PDT 24
Peak memory 215388 kb
Host smart-5491d8f4-6f0f-4eb4-9d67-a0a818b5cc4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4163613684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.4163613684
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2963046192
Short name T746
Test name
Test status
Simulation time 156554535 ps
CPU time 0.85 seconds
Started Aug 07 06:04:03 PM PDT 24
Finished Aug 07 06:04:04 PM PDT 24
Peak memory 206852 kb
Host smart-866b3b9f-5df8-4ff4-9d25-f72dc93d847b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29630
46192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2963046192
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2889534111
Short name T2404
Test name
Test status
Simulation time 243679049 ps
CPU time 1.09 seconds
Started Aug 07 06:04:05 PM PDT 24
Finished Aug 07 06:04:06 PM PDT 24
Peak memory 207004 kb
Host smart-996d3495-c76c-4dac-af8d-9161a591e10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28895
34111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2889534111
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.4010044985
Short name T867
Test name
Test status
Simulation time 3644855018 ps
CPU time 28.98 seconds
Started Aug 07 06:04:01 PM PDT 24
Finished Aug 07 06:04:30 PM PDT 24
Peak memory 223680 kb
Host smart-f58d60e8-0f8c-4daa-a91e-486bd9d3e9d7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4010044985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.4010044985
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.3484251248
Short name T105
Test name
Test status
Simulation time 6641093714 ps
CPU time 77.32 seconds
Started Aug 07 06:03:59 PM PDT 24
Finished Aug 07 06:05:17 PM PDT 24
Peak memory 207280 kb
Host smart-1d2aaf4a-569c-4f6e-9a9c-2a92ac744715
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3484251248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.3484251248
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.1531687434
Short name T83
Test name
Test status
Simulation time 200734602 ps
CPU time 0.93 seconds
Started Aug 07 06:04:15 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 207016 kb
Host smart-823eb49e-4d46-4f4e-96e6-4adcdc6f302f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15316
87434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.1531687434
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.4262715648
Short name T2869
Test name
Test status
Simulation time 23372962641 ps
CPU time 43.81 seconds
Started Aug 07 06:04:05 PM PDT 24
Finished Aug 07 06:04:49 PM PDT 24
Peak memory 215596 kb
Host smart-e1eab6b4-1739-44bb-8759-a408a464e969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42627
15648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.4262715648
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1021553882
Short name T2244
Test name
Test status
Simulation time 8334724281 ps
CPU time 9.96 seconds
Started Aug 07 06:04:10 PM PDT 24
Finished Aug 07 06:04:20 PM PDT 24
Peak memory 207288 kb
Host smart-47646abf-747b-469f-ab91-1c8c25e1b41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10215
53882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1021553882
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.765328908
Short name T3070
Test name
Test status
Simulation time 4369971080 ps
CPU time 44.02 seconds
Started Aug 07 06:04:06 PM PDT 24
Finished Aug 07 06:04:50 PM PDT 24
Peak memory 223604 kb
Host smart-6f8ee4c8-043d-476c-bcec-616f4f5bd87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76532
8908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.765328908
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.1187207909
Short name T1935
Test name
Test status
Simulation time 3183087154 ps
CPU time 31.47 seconds
Started Aug 07 06:04:05 PM PDT 24
Finished Aug 07 06:04:36 PM PDT 24
Peak memory 217224 kb
Host smart-5b8adcd5-1ca4-4a76-a088-8c130629746a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1187207909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.1187207909
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.275736290
Short name T611
Test name
Test status
Simulation time 292268711 ps
CPU time 1.11 seconds
Started Aug 07 06:04:15 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 206936 kb
Host smart-e0077f6e-eaa7-4f35-958f-843c8d1ef34e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=275736290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.275736290
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2645580374
Short name T1465
Test name
Test status
Simulation time 213939459 ps
CPU time 0.98 seconds
Started Aug 07 06:04:08 PM PDT 24
Finished Aug 07 06:04:09 PM PDT 24
Peak memory 207016 kb
Host smart-1c55979b-d020-4b0a-951b-11a263f45814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26455
80374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2645580374
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1000803161
Short name T2778
Test name
Test status
Simulation time 1390954103 ps
CPU time 11.34 seconds
Started Aug 07 06:04:12 PM PDT 24
Finished Aug 07 06:04:24 PM PDT 24
Peak memory 216916 kb
Host smart-21456c50-ba4d-4147-8478-d9ddba9fe3c7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1000803161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1000803161
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.2680053769
Short name T2374
Test name
Test status
Simulation time 168644255 ps
CPU time 0.87 seconds
Started Aug 07 06:04:09 PM PDT 24
Finished Aug 07 06:04:10 PM PDT 24
Peak memory 207216 kb
Host smart-a4302039-f4a8-433e-a1b3-64f5b6e708e4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2680053769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2680053769
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3330340197
Short name T2291
Test name
Test status
Simulation time 173570602 ps
CPU time 0.84 seconds
Started Aug 07 06:04:09 PM PDT 24
Finished Aug 07 06:04:10 PM PDT 24
Peak memory 206988 kb
Host smart-2360c3d0-a7fb-44aa-bc3e-a6518f43c977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33303
40197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3330340197
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.1588633893
Short name T1726
Test name
Test status
Simulation time 152335934 ps
CPU time 0.85 seconds
Started Aug 07 06:04:09 PM PDT 24
Finished Aug 07 06:04:10 PM PDT 24
Peak memory 206940 kb
Host smart-a6a8c27e-6785-4363-a97f-f9ca03d454c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15886
33893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1588633893
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2700648144
Short name T1999
Test name
Test status
Simulation time 177450659 ps
CPU time 0.87 seconds
Started Aug 07 06:04:16 PM PDT 24
Finished Aug 07 06:04:17 PM PDT 24
Peak memory 207024 kb
Host smart-80919a7d-8857-445c-838c-d9df39073389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27006
48144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2700648144
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.4041860187
Short name T2782
Test name
Test status
Simulation time 147699774 ps
CPU time 0.82 seconds
Started Aug 07 06:04:05 PM PDT 24
Finished Aug 07 06:04:06 PM PDT 24
Peak memory 206976 kb
Host smart-c3fd31bd-c917-4c2a-92e8-95dac2500175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40418
60187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.4041860187
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.858720793
Short name T179
Test name
Test status
Simulation time 167006721 ps
CPU time 0.84 seconds
Started Aug 07 06:04:15 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 206980 kb
Host smart-897cb3bc-387f-444c-832f-3dc2f6d043e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85872
0793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.858720793
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2516409081
Short name T1299
Test name
Test status
Simulation time 236623269 ps
CPU time 1.08 seconds
Started Aug 07 06:04:05 PM PDT 24
Finished Aug 07 06:04:06 PM PDT 24
Peak memory 207008 kb
Host smart-0b2af555-94f6-43dc-b52d-71bc002fc3c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2516409081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2516409081
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1572153633
Short name T1870
Test name
Test status
Simulation time 172507759 ps
CPU time 0.85 seconds
Started Aug 07 06:04:04 PM PDT 24
Finished Aug 07 06:04:05 PM PDT 24
Peak memory 206940 kb
Host smart-5c86f99b-8181-429b-a51e-6ca0c402ac8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15721
53633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1572153633
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3320898163
Short name T33
Test name
Test status
Simulation time 52029617 ps
CPU time 0.72 seconds
Started Aug 07 06:04:15 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 206888 kb
Host smart-fbd523af-ac7a-448e-9323-b15a5c121dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33208
98163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3320898163
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2103671480
Short name T296
Test name
Test status
Simulation time 14916433969 ps
CPU time 35.46 seconds
Started Aug 07 06:04:14 PM PDT 24
Finished Aug 07 06:04:49 PM PDT 24
Peak memory 215476 kb
Host smart-598931d1-21d7-4786-a5a4-ca326579f118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21036
71480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2103671480
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1752010725
Short name T1164
Test name
Test status
Simulation time 213720030 ps
CPU time 0.95 seconds
Started Aug 07 06:04:21 PM PDT 24
Finished Aug 07 06:04:22 PM PDT 24
Peak memory 206960 kb
Host smart-8cee416c-1137-4250-8ab6-162c5ae1a7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17520
10725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1752010725
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.524152105
Short name T2586
Test name
Test status
Simulation time 160607561 ps
CPU time 0.9 seconds
Started Aug 07 06:04:10 PM PDT 24
Finished Aug 07 06:04:11 PM PDT 24
Peak memory 206964 kb
Host smart-c3a499da-f494-43d5-87b2-df5b6b962c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52415
2105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.524152105
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.2810615600
Short name T871
Test name
Test status
Simulation time 185214137 ps
CPU time 0.87 seconds
Started Aug 07 06:04:12 PM PDT 24
Finished Aug 07 06:04:13 PM PDT 24
Peak memory 207012 kb
Host smart-8b71cd1e-5396-4d8c-aba2-dcf4a77c1d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28106
15600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2810615600
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.4189960443
Short name T2859
Test name
Test status
Simulation time 172123406 ps
CPU time 0.92 seconds
Started Aug 07 06:04:09 PM PDT 24
Finished Aug 07 06:04:10 PM PDT 24
Peak memory 207000 kb
Host smart-f781c9e7-39c9-4833-81e8-98bc0700d2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41899
60443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.4189960443
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2182779782
Short name T1986
Test name
Test status
Simulation time 191207578 ps
CPU time 0.87 seconds
Started Aug 07 06:04:14 PM PDT 24
Finished Aug 07 06:04:15 PM PDT 24
Peak memory 206904 kb
Host smart-4aa04125-8fb2-473a-8831-108ca78feaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21827
79782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2182779782
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_rx_full.1050204444
Short name T1387
Test name
Test status
Simulation time 335902238 ps
CPU time 1.17 seconds
Started Aug 07 06:04:16 PM PDT 24
Finished Aug 07 06:04:18 PM PDT 24
Peak memory 207040 kb
Host smart-209fb60a-cea2-4a00-a811-87a2bdfaea89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10502
04444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.1050204444
Directory /workspace/27.usbdev_rx_full/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1940624820
Short name T720
Test name
Test status
Simulation time 153708568 ps
CPU time 0.87 seconds
Started Aug 07 06:04:14 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 206872 kb
Host smart-5ee5288a-573e-4eee-b9f8-c85b4044f0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19406
24820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1940624820
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1041853233
Short name T1291
Test name
Test status
Simulation time 189163641 ps
CPU time 0.94 seconds
Started Aug 07 06:04:14 PM PDT 24
Finished Aug 07 06:04:15 PM PDT 24
Peak memory 206912 kb
Host smart-db27b890-0e41-417a-ba25-afbbedccfea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10418
53233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1041853233
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2287971077
Short name T2109
Test name
Test status
Simulation time 251720025 ps
CPU time 1.09 seconds
Started Aug 07 06:04:11 PM PDT 24
Finished Aug 07 06:04:12 PM PDT 24
Peak memory 207016 kb
Host smart-b7a653cc-ee65-43b0-90e4-116329295304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22879
71077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2287971077
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.3359219149
Short name T3057
Test name
Test status
Simulation time 1389133257 ps
CPU time 10.95 seconds
Started Aug 07 06:04:14 PM PDT 24
Finished Aug 07 06:04:25 PM PDT 24
Peak memory 217008 kb
Host smart-ce4033b5-f8eb-4c2b-b624-63456c2bd024
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3359219149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.3359219149
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1544993538
Short name T1551
Test name
Test status
Simulation time 219389091 ps
CPU time 0.93 seconds
Started Aug 07 06:04:14 PM PDT 24
Finished Aug 07 06:04:15 PM PDT 24
Peak memory 207004 kb
Host smart-355d12ae-03ec-4403-a2cf-f21b3fd7fc59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15449
93538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1544993538
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2824407795
Short name T1055
Test name
Test status
Simulation time 181146065 ps
CPU time 0.87 seconds
Started Aug 07 06:04:15 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 206904 kb
Host smart-18632182-d424-4e24-b405-d3b10bc0b95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28244
07795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2824407795
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.1007808944
Short name T813
Test name
Test status
Simulation time 1303535044 ps
CPU time 3.38 seconds
Started Aug 07 06:04:19 PM PDT 24
Finished Aug 07 06:04:22 PM PDT 24
Peak memory 207228 kb
Host smart-c3bc75b3-6d3b-4141-adbf-e420295bf536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10078
08944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.1007808944
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1066567502
Short name T2003
Test name
Test status
Simulation time 4285232490 ps
CPU time 44.7 seconds
Started Aug 07 06:04:10 PM PDT 24
Finished Aug 07 06:04:55 PM PDT 24
Peak memory 217152 kb
Host smart-4dca6553-57c7-4033-8725-262d4f916697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10665
67502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1066567502
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.2943467547
Short name T1776
Test name
Test status
Simulation time 1293759680 ps
CPU time 28.2 seconds
Started Aug 07 06:04:01 PM PDT 24
Finished Aug 07 06:04:29 PM PDT 24
Peak memory 207040 kb
Host smart-403e17cf-3396-4b24-8885-1b57b66359e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943467547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.2943467547
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.2921282517
Short name T793
Test name
Test status
Simulation time 40741561 ps
CPU time 0.67 seconds
Started Aug 07 06:04:36 PM PDT 24
Finished Aug 07 06:04:37 PM PDT 24
Peak memory 207060 kb
Host smart-695713ff-af0a-4e67-8f05-83da3f8a22cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2921282517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.2921282517
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1291657658
Short name T678
Test name
Test status
Simulation time 4586601949 ps
CPU time 5.94 seconds
Started Aug 07 06:04:15 PM PDT 24
Finished Aug 07 06:04:21 PM PDT 24
Peak memory 215452 kb
Host smart-edd5aa72-7b7a-4ad9-9104-c915c1836263
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291657658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.1291657658
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1097225869
Short name T686
Test name
Test status
Simulation time 16396090791 ps
CPU time 20.42 seconds
Started Aug 07 06:04:18 PM PDT 24
Finished Aug 07 06:04:38 PM PDT 24
Peak memory 215448 kb
Host smart-cfc4648e-b36f-4105-ac7d-f0c419ebc513
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097225869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1097225869
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3896604546
Short name T2506
Test name
Test status
Simulation time 24687544037 ps
CPU time 28.37 seconds
Started Aug 07 06:04:16 PM PDT 24
Finished Aug 07 06:04:44 PM PDT 24
Peak memory 215480 kb
Host smart-ac01e848-148a-4bec-9532-6479248c5303
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896604546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.3896604546
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.79295420
Short name T1567
Test name
Test status
Simulation time 179328957 ps
CPU time 0.87 seconds
Started Aug 07 06:04:14 PM PDT 24
Finished Aug 07 06:04:15 PM PDT 24
Peak memory 206980 kb
Host smart-ed85d198-382e-4af4-b803-1a30dcfdca1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79295
420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.79295420
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1034020195
Short name T2451
Test name
Test status
Simulation time 153704524 ps
CPU time 0.85 seconds
Started Aug 07 06:04:31 PM PDT 24
Finished Aug 07 06:04:32 PM PDT 24
Peak memory 206956 kb
Host smart-3a8180de-c74b-4b14-9bab-d08fbeaa12d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10340
20195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1034020195
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.4285123643
Short name T1948
Test name
Test status
Simulation time 442134664 ps
CPU time 1.6 seconds
Started Aug 07 06:04:15 PM PDT 24
Finished Aug 07 06:04:17 PM PDT 24
Peak memory 206948 kb
Host smart-ea8de21f-10d2-4218-838a-63d25cbd2c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42851
23643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.4285123643
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2507009781
Short name T627
Test name
Test status
Simulation time 587197172 ps
CPU time 1.66 seconds
Started Aug 07 06:04:17 PM PDT 24
Finished Aug 07 06:04:18 PM PDT 24
Peak memory 206972 kb
Host smart-6aa6d30e-ff6c-4898-85fd-28a8642d83fc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2507009781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2507009781
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2955605118
Short name T2895
Test name
Test status
Simulation time 61708064511 ps
CPU time 86.98 seconds
Started Aug 07 06:04:21 PM PDT 24
Finished Aug 07 06:05:48 PM PDT 24
Peak memory 207316 kb
Host smart-6d7697e6-3c06-486d-b79c-9a36db800a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29556
05118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2955605118
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.1210270884
Short name T1116
Test name
Test status
Simulation time 741305665 ps
CPU time 15.36 seconds
Started Aug 07 06:04:25 PM PDT 24
Finished Aug 07 06:04:40 PM PDT 24
Peak memory 207228 kb
Host smart-9a9f8e44-0c87-42b0-842f-41c4dfaa864c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210270884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.1210270884
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.4142558722
Short name T377
Test name
Test status
Simulation time 1081137568 ps
CPU time 2.16 seconds
Started Aug 07 06:04:24 PM PDT 24
Finished Aug 07 06:04:26 PM PDT 24
Peak memory 206964 kb
Host smart-f7eea82b-b22e-47a4-a80a-2e2f9b57ec64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41425
58722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.4142558722
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.856807765
Short name T61
Test name
Test status
Simulation time 139749139 ps
CPU time 0.84 seconds
Started Aug 07 06:04:34 PM PDT 24
Finished Aug 07 06:04:35 PM PDT 24
Peak memory 206980 kb
Host smart-738b987e-ca72-4341-9ef4-705d80d68b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85680
7765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.856807765
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1649759380
Short name T1732
Test name
Test status
Simulation time 47519287 ps
CPU time 0.72 seconds
Started Aug 07 06:04:32 PM PDT 24
Finished Aug 07 06:04:33 PM PDT 24
Peak memory 206980 kb
Host smart-309b0294-d53f-4b7a-8fd1-d3e3a084add1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16497
59380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1649759380
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.3893256657
Short name T2318
Test name
Test status
Simulation time 877760528 ps
CPU time 2.26 seconds
Started Aug 07 06:04:33 PM PDT 24
Finished Aug 07 06:04:36 PM PDT 24
Peak memory 207244 kb
Host smart-8f2bc67d-7196-4aba-9173-78d51a0b199b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38932
56657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.3893256657
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_types.3479476371
Short name T395
Test name
Test status
Simulation time 474670308 ps
CPU time 1.33 seconds
Started Aug 07 06:04:21 PM PDT 24
Finished Aug 07 06:04:23 PM PDT 24
Peak memory 206952 kb
Host smart-92e1b327-a135-411b-b9ec-8443557d3255
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3479476371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.3479476371
Directory /workspace/28.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2912735181
Short name T1403
Test name
Test status
Simulation time 169416655 ps
CPU time 1.74 seconds
Started Aug 07 06:04:34 PM PDT 24
Finished Aug 07 06:04:36 PM PDT 24
Peak memory 207140 kb
Host smart-befdd527-7771-47dc-8e87-75e9a5b2ec8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29127
35181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2912735181
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2249153203
Short name T2643
Test name
Test status
Simulation time 209529131 ps
CPU time 1.12 seconds
Started Aug 07 06:04:27 PM PDT 24
Finished Aug 07 06:04:29 PM PDT 24
Peak memory 207188 kb
Host smart-2ff47de6-7e15-4b7b-8008-9af73e67a1e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2249153203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2249153203
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.122200717
Short name T2128
Test name
Test status
Simulation time 144858577 ps
CPU time 0.85 seconds
Started Aug 07 06:04:34 PM PDT 24
Finished Aug 07 06:04:35 PM PDT 24
Peak memory 206960 kb
Host smart-31f64f83-f842-428f-ad1c-0d125bbc233f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12220
0717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.122200717
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1952625829
Short name T1416
Test name
Test status
Simulation time 222412656 ps
CPU time 0.97 seconds
Started Aug 07 06:04:28 PM PDT 24
Finished Aug 07 06:04:29 PM PDT 24
Peak memory 206992 kb
Host smart-9b195246-fb0f-420d-b72a-139f2cb53dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19526
25829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1952625829
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.800256113
Short name T3030
Test name
Test status
Simulation time 3292590746 ps
CPU time 33.89 seconds
Started Aug 07 06:04:26 PM PDT 24
Finished Aug 07 06:05:00 PM PDT 24
Peak memory 223600 kb
Host smart-73e48d71-5ade-4236-9938-09de59076676
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=800256113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.800256113
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.509116971
Short name T1082
Test name
Test status
Simulation time 7276075374 ps
CPU time 55.2 seconds
Started Aug 07 06:04:27 PM PDT 24
Finished Aug 07 06:05:22 PM PDT 24
Peak memory 207248 kb
Host smart-87b17b2c-7bc7-43bc-97ce-77aa312aa8a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=509116971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.509116971
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1124943983
Short name T876
Test name
Test status
Simulation time 184256662 ps
CPU time 0.9 seconds
Started Aug 07 06:04:34 PM PDT 24
Finished Aug 07 06:04:35 PM PDT 24
Peak memory 206976 kb
Host smart-916e7c4e-f3e8-4083-851d-e214d35ea286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11249
43983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1124943983
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.2827552291
Short name T2920
Test name
Test status
Simulation time 29169142272 ps
CPU time 38.98 seconds
Started Aug 07 06:04:25 PM PDT 24
Finished Aug 07 06:05:04 PM PDT 24
Peak memory 207280 kb
Host smart-e3610024-bd18-4414-b78a-6e915fea59f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28275
52291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.2827552291
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1830580748
Short name T109
Test name
Test status
Simulation time 9922989866 ps
CPU time 12.9 seconds
Started Aug 07 06:04:23 PM PDT 24
Finished Aug 07 06:04:36 PM PDT 24
Peak memory 207260 kb
Host smart-80d71e24-ca1f-4e4e-9221-2c17be382eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18305
80748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1830580748
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.4286991187
Short name T2612
Test name
Test status
Simulation time 3017491518 ps
CPU time 22.57 seconds
Started Aug 07 06:04:24 PM PDT 24
Finished Aug 07 06:04:47 PM PDT 24
Peak memory 215484 kb
Host smart-fe9c1de3-30ff-4cba-9ff0-bf074175efe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42869
91187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.4286991187
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.211383406
Short name T612
Test name
Test status
Simulation time 2084895337 ps
CPU time 61.36 seconds
Started Aug 07 06:04:22 PM PDT 24
Finished Aug 07 06:05:24 PM PDT 24
Peak memory 215356 kb
Host smart-abfd9fd7-db77-4310-aa90-5bc602c20ac1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=211383406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.211383406
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.2823672728
Short name T3082
Test name
Test status
Simulation time 250450006 ps
CPU time 1.03 seconds
Started Aug 07 06:04:38 PM PDT 24
Finished Aug 07 06:04:39 PM PDT 24
Peak memory 206976 kb
Host smart-19710109-9d17-4a1d-92bf-a89e03bb13e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2823672728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.2823672728
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1943703418
Short name T1894
Test name
Test status
Simulation time 224932011 ps
CPU time 0.94 seconds
Started Aug 07 06:04:22 PM PDT 24
Finished Aug 07 06:04:23 PM PDT 24
Peak memory 206908 kb
Host smart-8396e4bc-1a66-48c6-bfee-c4cd6cd38caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19437
03418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1943703418
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.524640693
Short name T2764
Test name
Test status
Simulation time 3724351806 ps
CPU time 30.73 seconds
Started Aug 07 06:04:30 PM PDT 24
Finished Aug 07 06:05:01 PM PDT 24
Peak memory 217084 kb
Host smart-fb5796bc-da62-4d28-84ca-e79999465975
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=524640693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.524640693
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.634861142
Short name T2770
Test name
Test status
Simulation time 166308746 ps
CPU time 0.88 seconds
Started Aug 07 06:04:27 PM PDT 24
Finished Aug 07 06:04:28 PM PDT 24
Peak memory 206956 kb
Host smart-7b5f4ec2-64af-4c28-87a9-785e075e3a8c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=634861142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.634861142
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3576776247
Short name T2619
Test name
Test status
Simulation time 151466989 ps
CPU time 0.91 seconds
Started Aug 07 06:04:23 PM PDT 24
Finished Aug 07 06:04:24 PM PDT 24
Peak memory 207028 kb
Host smart-d3db2200-b279-4fd0-a62d-f2dbda1686b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767
76247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3576776247
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.4218114805
Short name T2946
Test name
Test status
Simulation time 213322130 ps
CPU time 0.93 seconds
Started Aug 07 06:04:22 PM PDT 24
Finished Aug 07 06:04:23 PM PDT 24
Peak memory 206980 kb
Host smart-1f3d00cc-559b-4946-a139-3196d0311fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42181
14805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.4218114805
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2188813199
Short name T709
Test name
Test status
Simulation time 206226003 ps
CPU time 0.99 seconds
Started Aug 07 06:04:35 PM PDT 24
Finished Aug 07 06:04:36 PM PDT 24
Peak memory 207016 kb
Host smart-8a834bc7-9dea-464d-849f-8d8a8a86a104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21888
13199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2188813199
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1014444896
Short name T1344
Test name
Test status
Simulation time 168256100 ps
CPU time 0.9 seconds
Started Aug 07 06:04:24 PM PDT 24
Finished Aug 07 06:04:25 PM PDT 24
Peak memory 206968 kb
Host smart-cb941121-0574-488f-84f7-d7d7a5253030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10144
44896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1014444896
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2045179737
Short name T2316
Test name
Test status
Simulation time 165921728 ps
CPU time 0.82 seconds
Started Aug 07 06:04:24 PM PDT 24
Finished Aug 07 06:04:25 PM PDT 24
Peak memory 206904 kb
Host smart-76711ef2-c0fc-4dc5-b1e4-2a13f0c08cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20451
79737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2045179737
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1986802396
Short name T1184
Test name
Test status
Simulation time 178754729 ps
CPU time 0.88 seconds
Started Aug 07 06:04:28 PM PDT 24
Finished Aug 07 06:04:29 PM PDT 24
Peak memory 206972 kb
Host smart-a5054cfb-e4c3-454e-b2e3-dbc064082c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19868
02396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1986802396
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3180944360
Short name T1842
Test name
Test status
Simulation time 239294491 ps
CPU time 1.07 seconds
Started Aug 07 06:04:26 PM PDT 24
Finished Aug 07 06:04:28 PM PDT 24
Peak memory 206964 kb
Host smart-25c5b41a-f594-4e33-a66b-c45a8ec3658c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3180944360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3180944360
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.4075561413
Short name T1660
Test name
Test status
Simulation time 149941068 ps
CPU time 0.79 seconds
Started Aug 07 06:04:25 PM PDT 24
Finished Aug 07 06:04:26 PM PDT 24
Peak memory 206928 kb
Host smart-9387a532-fa44-40a9-9109-18b9966e4899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40755
61413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.4075561413
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1974690077
Short name T2597
Test name
Test status
Simulation time 31767243 ps
CPU time 0.69 seconds
Started Aug 07 06:04:25 PM PDT 24
Finished Aug 07 06:04:26 PM PDT 24
Peak memory 206924 kb
Host smart-04121979-351c-4482-a823-613ebd19352b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19746
90077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1974690077
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3058252219
Short name T2293
Test name
Test status
Simulation time 21763035862 ps
CPU time 47.59 seconds
Started Aug 07 06:04:29 PM PDT 24
Finished Aug 07 06:05:16 PM PDT 24
Peak memory 215484 kb
Host smart-e0bcd262-cb51-4299-866f-10c1c4f233f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30582
52219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3058252219
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1833927715
Short name T1985
Test name
Test status
Simulation time 184811513 ps
CPU time 0.94 seconds
Started Aug 07 06:04:32 PM PDT 24
Finished Aug 07 06:04:33 PM PDT 24
Peak memory 206996 kb
Host smart-35ca7486-59a4-43f4-b60a-315b4e41f188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18339
27715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1833927715
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3956040615
Short name T726
Test name
Test status
Simulation time 170962036 ps
CPU time 0.87 seconds
Started Aug 07 06:04:28 PM PDT 24
Finished Aug 07 06:04:29 PM PDT 24
Peak memory 207044 kb
Host smart-8666077a-cfec-4019-bbcd-983b6dce3b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39560
40615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3956040615
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3084972847
Short name T2064
Test name
Test status
Simulation time 176069434 ps
CPU time 0.88 seconds
Started Aug 07 06:04:37 PM PDT 24
Finished Aug 07 06:04:38 PM PDT 24
Peak memory 206988 kb
Host smart-cef3682e-1b2c-4618-af63-5b03b65b699a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30849
72847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3084972847
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.389244539
Short name T2333
Test name
Test status
Simulation time 153186347 ps
CPU time 0.88 seconds
Started Aug 07 06:04:33 PM PDT 24
Finished Aug 07 06:04:34 PM PDT 24
Peak memory 207016 kb
Host smart-a8b55343-9fa9-4761-a59b-618653ff6a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38924
4539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.389244539
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.295823262
Short name T2546
Test name
Test status
Simulation time 181561817 ps
CPU time 0.92 seconds
Started Aug 07 06:04:31 PM PDT 24
Finished Aug 07 06:04:32 PM PDT 24
Peak memory 207036 kb
Host smart-1659c0c1-a8d0-44bd-83ef-041c0bd68aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29582
3262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.295823262
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_rx_full.2687297056
Short name T2986
Test name
Test status
Simulation time 342659860 ps
CPU time 1.21 seconds
Started Aug 07 06:04:28 PM PDT 24
Finished Aug 07 06:04:29 PM PDT 24
Peak memory 206880 kb
Host smart-5e14a7ec-c84b-461d-a0dd-5b5570c3e0ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26872
97056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.2687297056
Directory /workspace/28.usbdev_rx_full/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1238229588
Short name T899
Test name
Test status
Simulation time 164303662 ps
CPU time 0.85 seconds
Started Aug 07 06:04:33 PM PDT 24
Finished Aug 07 06:04:34 PM PDT 24
Peak memory 206964 kb
Host smart-f9ed4994-69bd-4c52-99c2-064e70073a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12382
29588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1238229588
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2346547486
Short name T931
Test name
Test status
Simulation time 152629650 ps
CPU time 0.79 seconds
Started Aug 07 06:04:29 PM PDT 24
Finished Aug 07 06:04:30 PM PDT 24
Peak memory 206992 kb
Host smart-dfb658cc-17e3-4d9b-9bd1-e21f0597f571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
47486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2346547486
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2360791957
Short name T1167
Test name
Test status
Simulation time 243169351 ps
CPU time 1.02 seconds
Started Aug 07 06:04:36 PM PDT 24
Finished Aug 07 06:04:37 PM PDT 24
Peak memory 206980 kb
Host smart-a6e5027a-5331-4d80-a59c-4fa1ca5e9c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23607
91957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2360791957
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.2152938254
Short name T1799
Test name
Test status
Simulation time 2039710207 ps
CPU time 16.4 seconds
Started Aug 07 06:04:35 PM PDT 24
Finished Aug 07 06:04:51 PM PDT 24
Peak memory 223572 kb
Host smart-9a5f8b6a-e229-4f4a-b520-51ed58c3c4a7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2152938254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2152938254
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3165632420
Short name T987
Test name
Test status
Simulation time 170714162 ps
CPU time 0.91 seconds
Started Aug 07 06:04:37 PM PDT 24
Finished Aug 07 06:04:38 PM PDT 24
Peak memory 206904 kb
Host smart-85417819-647e-4350-b17f-b2dea76b9426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31656
32420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3165632420
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1934245285
Short name T1975
Test name
Test status
Simulation time 179367554 ps
CPU time 0.92 seconds
Started Aug 07 06:04:29 PM PDT 24
Finished Aug 07 06:04:30 PM PDT 24
Peak memory 206988 kb
Host smart-e11ab856-d046-4f06-9aee-81501023ef4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19342
45285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1934245285
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.3443243009
Short name T525
Test name
Test status
Simulation time 1087405096 ps
CPU time 2.54 seconds
Started Aug 07 06:04:38 PM PDT 24
Finished Aug 07 06:04:40 PM PDT 24
Peak memory 207192 kb
Host smart-713b008c-8304-4183-a359-151f8be04ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34432
43009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.3443243009
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.343522752
Short name T1617
Test name
Test status
Simulation time 1798501428 ps
CPU time 14.31 seconds
Started Aug 07 06:04:36 PM PDT 24
Finished Aug 07 06:04:50 PM PDT 24
Peak memory 216728 kb
Host smart-f5ca0900-2c40-4b83-8f0a-82b7842ebe00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34352
2752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.343522752
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.2201413113
Short name T1853
Test name
Test status
Simulation time 355435622 ps
CPU time 4.55 seconds
Started Aug 07 06:04:14 PM PDT 24
Finished Aug 07 06:04:19 PM PDT 24
Peak memory 207176 kb
Host smart-bada3311-8d22-4410-983a-e35f7f7f1c80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201413113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.2201413113
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.1527957063
Short name T831
Test name
Test status
Simulation time 43415597 ps
CPU time 0.71 seconds
Started Aug 07 06:04:56 PM PDT 24
Finished Aug 07 06:04:57 PM PDT 24
Peak memory 207108 kb
Host smart-a584cfcf-ad08-41da-bac7-0742d405f240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1527957063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.1527957063
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1156537653
Short name T1393
Test name
Test status
Simulation time 4745157530 ps
CPU time 7.13 seconds
Started Aug 07 06:04:45 PM PDT 24
Finished Aug 07 06:04:52 PM PDT 24
Peak memory 215392 kb
Host smart-53d84b17-16c8-4bc4-8d0b-e0ddee192960
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156537653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.1156537653
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.991259027
Short name T2338
Test name
Test status
Simulation time 19689400596 ps
CPU time 22.28 seconds
Started Aug 07 06:04:37 PM PDT 24
Finished Aug 07 06:04:59 PM PDT 24
Peak memory 207328 kb
Host smart-fa8b641a-0f04-42b6-a8a4-b752b79e5cf5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=991259027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.991259027
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.936566394
Short name T1400
Test name
Test status
Simulation time 25446325262 ps
CPU time 33.03 seconds
Started Aug 07 06:04:38 PM PDT 24
Finished Aug 07 06:05:11 PM PDT 24
Peak memory 215484 kb
Host smart-fde8ea0f-7887-4d63-b180-9e09dd9abac3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936566394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_resume.936566394
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.853977241
Short name T1987
Test name
Test status
Simulation time 150713553 ps
CPU time 0.95 seconds
Started Aug 07 06:04:51 PM PDT 24
Finished Aug 07 06:04:52 PM PDT 24
Peak memory 206960 kb
Host smart-4d8cd568-b832-448f-a6d3-abec6ed76165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85397
7241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.853977241
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1065695759
Short name T1139
Test name
Test status
Simulation time 171052384 ps
CPU time 0.93 seconds
Started Aug 07 06:04:43 PM PDT 24
Finished Aug 07 06:04:44 PM PDT 24
Peak memory 206860 kb
Host smart-6c89bfc8-5922-44b9-819d-607e513803ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10656
95759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1065695759
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3109287354
Short name T2689
Test name
Test status
Simulation time 629267004 ps
CPU time 1.94 seconds
Started Aug 07 06:04:38 PM PDT 24
Finished Aug 07 06:04:40 PM PDT 24
Peak memory 207260 kb
Host smart-c3a3d9fc-8909-46f2-9ffb-d70d6796128b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31092
87354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3109287354
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3507972977
Short name T2807
Test name
Test status
Simulation time 568942748 ps
CPU time 1.75 seconds
Started Aug 07 06:04:40 PM PDT 24
Finished Aug 07 06:04:42 PM PDT 24
Peak memory 206992 kb
Host smart-687ad788-c529-4b5c-abf4-4e4ea7a8b80a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3507972977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3507972977
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.969947418
Short name T1486
Test name
Test status
Simulation time 3403264254 ps
CPU time 28.84 seconds
Started Aug 07 06:04:42 PM PDT 24
Finished Aug 07 06:05:11 PM PDT 24
Peak memory 207264 kb
Host smart-f0f286b6-889a-49fa-8f4c-a7ee2238e67c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969947418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.969947418
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.186881980
Short name T988
Test name
Test status
Simulation time 927395950 ps
CPU time 2.02 seconds
Started Aug 07 06:04:30 PM PDT 24
Finished Aug 07 06:04:32 PM PDT 24
Peak memory 206872 kb
Host smart-cc0643a8-6983-4b56-9fe2-94cb1fa708de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18688
1980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.186881980
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3810077661
Short name T1176
Test name
Test status
Simulation time 149218967 ps
CPU time 0.84 seconds
Started Aug 07 06:04:38 PM PDT 24
Finished Aug 07 06:04:39 PM PDT 24
Peak memory 206972 kb
Host smart-0aec6912-dbf5-4618-b6cd-2f17e1d4a446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38100
77661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3810077661
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2582995958
Short name T1434
Test name
Test status
Simulation time 36475829 ps
CPU time 0.73 seconds
Started Aug 07 06:04:36 PM PDT 24
Finished Aug 07 06:04:37 PM PDT 24
Peak memory 206964 kb
Host smart-f142efb4-a228-42c7-807f-d5efd3e7f62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25829
95958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2582995958
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.301718027
Short name T1298
Test name
Test status
Simulation time 718706759 ps
CPU time 2.12 seconds
Started Aug 07 06:04:48 PM PDT 24
Finished Aug 07 06:04:50 PM PDT 24
Peak memory 207044 kb
Host smart-4dea0365-babe-42f2-a1cd-7dce37f0f09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30171
8027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.301718027
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_types.263517436
Short name T385
Test name
Test status
Simulation time 430982891 ps
CPU time 1.19 seconds
Started Aug 07 06:04:46 PM PDT 24
Finished Aug 07 06:04:47 PM PDT 24
Peak memory 206948 kb
Host smart-1dd94e81-1973-46d3-92f2-25ea13408a63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=263517436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.263517436
Directory /workspace/29.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1287390011
Short name T1706
Test name
Test status
Simulation time 255388727 ps
CPU time 1.73 seconds
Started Aug 07 06:04:46 PM PDT 24
Finished Aug 07 06:04:48 PM PDT 24
Peak memory 207252 kb
Host smart-d153e2be-1408-44f8-8c40-bfedfe905e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12873
90011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1287390011
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1943981872
Short name T2422
Test name
Test status
Simulation time 254534291 ps
CPU time 1.07 seconds
Started Aug 07 06:04:42 PM PDT 24
Finished Aug 07 06:04:44 PM PDT 24
Peak memory 207188 kb
Host smart-ce96bb16-cd90-49d2-9673-0baccf825c01
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1943981872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1943981872
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2971839791
Short name T2553
Test name
Test status
Simulation time 198868991 ps
CPU time 0.89 seconds
Started Aug 07 06:04:47 PM PDT 24
Finished Aug 07 06:04:48 PM PDT 24
Peak memory 206828 kb
Host smart-31865e46-9399-48cb-b5d1-b1f8fead6ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29718
39791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2971839791
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.667758631
Short name T1373
Test name
Test status
Simulation time 206084937 ps
CPU time 1 seconds
Started Aug 07 06:04:40 PM PDT 24
Finished Aug 07 06:04:41 PM PDT 24
Peak memory 206940 kb
Host smart-f8f5db03-72d6-47a0-8b60-5df6ca18dfd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66775
8631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.667758631
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.1325145224
Short name T2942
Test name
Test status
Simulation time 4033878217 ps
CPU time 107.19 seconds
Started Aug 07 06:04:45 PM PDT 24
Finished Aug 07 06:06:32 PM PDT 24
Peak memory 215452 kb
Host smart-571da0e3-2901-4203-8ae2-7f2cbc90c1a3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1325145224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.1325145224
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.3201902478
Short name T2977
Test name
Test status
Simulation time 10210901796 ps
CPU time 79.55 seconds
Started Aug 07 06:04:40 PM PDT 24
Finished Aug 07 06:06:00 PM PDT 24
Peak memory 207296 kb
Host smart-44da265c-94d8-423d-8c4d-84aa34850f16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3201902478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.3201902478
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.816231676
Short name T1533
Test name
Test status
Simulation time 211060240 ps
CPU time 0.91 seconds
Started Aug 07 06:04:47 PM PDT 24
Finished Aug 07 06:04:48 PM PDT 24
Peak memory 207016 kb
Host smart-1d1d6119-de7b-4a32-921f-a146cb693477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81623
1676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.816231676
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3051498018
Short name T2948
Test name
Test status
Simulation time 24264286168 ps
CPU time 39.21 seconds
Started Aug 07 06:04:47 PM PDT 24
Finished Aug 07 06:05:26 PM PDT 24
Peak memory 215516 kb
Host smart-fbd367a2-a7ce-4875-926d-900e22d2acb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30514
98018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3051498018
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3035019197
Short name T2976
Test name
Test status
Simulation time 8939869117 ps
CPU time 13.15 seconds
Started Aug 07 06:04:45 PM PDT 24
Finished Aug 07 06:04:59 PM PDT 24
Peak memory 207300 kb
Host smart-23a5e5a5-6678-40d3-aa0d-ccd4745637b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30350
19197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3035019197
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.335107794
Short name T1095
Test name
Test status
Simulation time 4044425580 ps
CPU time 120.31 seconds
Started Aug 07 06:04:47 PM PDT 24
Finished Aug 07 06:06:47 PM PDT 24
Peak memory 217936 kb
Host smart-da06c517-8a29-485e-a1a4-f1fc159b46a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33510
7794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.335107794
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.3408322575
Short name T674
Test name
Test status
Simulation time 2657840784 ps
CPU time 77.51 seconds
Started Aug 07 06:04:46 PM PDT 24
Finished Aug 07 06:06:03 PM PDT 24
Peak memory 223468 kb
Host smart-1bae0463-3c13-49e3-b659-046c719d0af8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3408322575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.3408322575
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.2447621794
Short name T846
Test name
Test status
Simulation time 241077239 ps
CPU time 0.96 seconds
Started Aug 07 06:04:44 PM PDT 24
Finished Aug 07 06:04:45 PM PDT 24
Peak memory 206988 kb
Host smart-619dd283-bbc0-4f4f-878a-0f10ce4e3a36
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2447621794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.2447621794
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2198021581
Short name T3008
Test name
Test status
Simulation time 237569723 ps
CPU time 1.08 seconds
Started Aug 07 06:04:42 PM PDT 24
Finished Aug 07 06:04:43 PM PDT 24
Peak memory 207004 kb
Host smart-713e01ae-93bc-4193-a6c5-c99cc5ee2b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21980
21581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2198021581
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3041214175
Short name T1495
Test name
Test status
Simulation time 2475838279 ps
CPU time 69.78 seconds
Started Aug 07 06:04:44 PM PDT 24
Finished Aug 07 06:05:54 PM PDT 24
Peak memory 215452 kb
Host smart-437babfe-5d64-43ac-8e8e-48da75a033fc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3041214175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3041214175
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1560398122
Short name T2051
Test name
Test status
Simulation time 163708129 ps
CPU time 0.89 seconds
Started Aug 07 06:04:44 PM PDT 24
Finished Aug 07 06:04:45 PM PDT 24
Peak memory 206988 kb
Host smart-d36cd729-8b88-46b0-9ff9-07936f2046d5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1560398122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1560398122
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3471828232
Short name T2226
Test name
Test status
Simulation time 160801273 ps
CPU time 0.87 seconds
Started Aug 07 06:04:47 PM PDT 24
Finished Aug 07 06:04:49 PM PDT 24
Peak memory 207016 kb
Host smart-fba228fd-711a-466b-a539-bf2622477fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34718
28232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3471828232
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.102113744
Short name T136
Test name
Test status
Simulation time 215900461 ps
CPU time 0.93 seconds
Started Aug 07 06:04:46 PM PDT 24
Finished Aug 07 06:04:47 PM PDT 24
Peak memory 206988 kb
Host smart-a650295b-ec03-4ddb-a3f9-5667449ab839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10211
3744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.102113744
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2205469153
Short name T2466
Test name
Test status
Simulation time 227514953 ps
CPU time 0.97 seconds
Started Aug 07 06:04:46 PM PDT 24
Finished Aug 07 06:04:47 PM PDT 24
Peak memory 206972 kb
Host smart-7012b49a-9f23-4708-a10d-ae49d0944320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22054
69153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2205469153
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2045201011
Short name T879
Test name
Test status
Simulation time 181425011 ps
CPU time 0.88 seconds
Started Aug 07 06:04:47 PM PDT 24
Finished Aug 07 06:04:48 PM PDT 24
Peak memory 206908 kb
Host smart-27076185-fb9f-48fe-ab19-4d8e450eff55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20452
01011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2045201011
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2359124329
Short name T2222
Test name
Test status
Simulation time 180366765 ps
CPU time 0.86 seconds
Started Aug 07 06:04:48 PM PDT 24
Finished Aug 07 06:04:49 PM PDT 24
Peak memory 207024 kb
Host smart-cd310f51-f40c-4e9c-9030-405b5b4972b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23591
24329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2359124329
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3685372215
Short name T176
Test name
Test status
Simulation time 144888946 ps
CPU time 0.85 seconds
Started Aug 07 06:04:48 PM PDT 24
Finished Aug 07 06:04:49 PM PDT 24
Peak memory 206980 kb
Host smart-200de763-f63f-4443-9755-f6f6463b9e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36853
72215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3685372215
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1817320840
Short name T1034
Test name
Test status
Simulation time 242392528 ps
CPU time 1.1 seconds
Started Aug 07 06:04:42 PM PDT 24
Finished Aug 07 06:04:43 PM PDT 24
Peak memory 207000 kb
Host smart-8f620fb9-f3e0-464c-88e1-8aa02786d6fb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1817320840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1817320840
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3862907074
Short name T2718
Test name
Test status
Simulation time 186617490 ps
CPU time 0.91 seconds
Started Aug 07 06:04:41 PM PDT 24
Finished Aug 07 06:04:42 PM PDT 24
Peak memory 206872 kb
Host smart-66dfa862-0f4f-450c-a5c1-0876f20f7e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38629
07074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3862907074
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1164409262
Short name T2735
Test name
Test status
Simulation time 40150567 ps
CPU time 0.69 seconds
Started Aug 07 06:04:45 PM PDT 24
Finished Aug 07 06:04:46 PM PDT 24
Peak memory 206968 kb
Host smart-7f2ad9e7-86ab-4284-a0a3-527ea55b4612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11644
09262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1164409262
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1961163810
Short name T2063
Test name
Test status
Simulation time 22238252820 ps
CPU time 65.2 seconds
Started Aug 07 06:04:50 PM PDT 24
Finished Aug 07 06:05:56 PM PDT 24
Peak memory 215548 kb
Host smart-0ab5d734-9591-4e7f-bc63-8e718892c6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19611
63810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1961163810
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3787034249
Short name T1696
Test name
Test status
Simulation time 178497154 ps
CPU time 0.92 seconds
Started Aug 07 06:04:43 PM PDT 24
Finished Aug 07 06:04:44 PM PDT 24
Peak memory 206984 kb
Host smart-1e9cf210-8f6b-4d87-b1da-6882a17ffc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37870
34249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3787034249
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2064054837
Short name T1813
Test name
Test status
Simulation time 221181007 ps
CPU time 0.98 seconds
Started Aug 07 06:04:53 PM PDT 24
Finished Aug 07 06:04:54 PM PDT 24
Peak memory 206944 kb
Host smart-910e89a2-2286-4ac9-92af-538f7d76269f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20640
54837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2064054837
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2182325382
Short name T1468
Test name
Test status
Simulation time 210495275 ps
CPU time 0.99 seconds
Started Aug 07 06:04:52 PM PDT 24
Finished Aug 07 06:04:53 PM PDT 24
Peak memory 206972 kb
Host smart-7be5b2cb-a186-4b2b-b4c6-233b0c531a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21823
25382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2182325382
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3538682924
Short name T1286
Test name
Test status
Simulation time 187617750 ps
CPU time 0.94 seconds
Started Aug 07 06:04:50 PM PDT 24
Finished Aug 07 06:04:52 PM PDT 24
Peak memory 207016 kb
Host smart-c3e9932d-7070-4beb-a485-dd375ff93976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35386
82924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3538682924
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.4286077749
Short name T1221
Test name
Test status
Simulation time 169695508 ps
CPU time 0.91 seconds
Started Aug 07 06:04:52 PM PDT 24
Finished Aug 07 06:04:53 PM PDT 24
Peak memory 206904 kb
Host smart-b905ae7d-5d40-43cb-95c7-79892a67c619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42860
77749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.4286077749
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_rx_full.3057734846
Short name T3108
Test name
Test status
Simulation time 267982997 ps
CPU time 1.14 seconds
Started Aug 07 06:04:55 PM PDT 24
Finished Aug 07 06:04:56 PM PDT 24
Peak memory 207024 kb
Host smart-3b9ea33c-dc41-474d-a4e5-0c86f48eb5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30577
34846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.3057734846
Directory /workspace/29.usbdev_rx_full/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3328337100
Short name T3116
Test name
Test status
Simulation time 175635185 ps
CPU time 0.87 seconds
Started Aug 07 06:04:55 PM PDT 24
Finished Aug 07 06:04:56 PM PDT 24
Peak memory 206968 kb
Host smart-19e1c538-e3a0-4cf2-bc4f-d10230ebdf52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33283
37100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3328337100
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.467614317
Short name T1796
Test name
Test status
Simulation time 143746035 ps
CPU time 0.84 seconds
Started Aug 07 06:04:51 PM PDT 24
Finished Aug 07 06:04:52 PM PDT 24
Peak memory 207016 kb
Host smart-e50005ff-9277-40da-b726-32c7c2ed61cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46761
4317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.467614317
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3850549203
Short name T2519
Test name
Test status
Simulation time 215089314 ps
CPU time 0.94 seconds
Started Aug 07 06:04:50 PM PDT 24
Finished Aug 07 06:04:51 PM PDT 24
Peak memory 207012 kb
Host smart-b31e0c9a-93c8-4c0c-84c4-d94222385644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38505
49203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3850549203
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3322827841
Short name T946
Test name
Test status
Simulation time 3136247514 ps
CPU time 30.72 seconds
Started Aug 07 06:04:53 PM PDT 24
Finished Aug 07 06:05:24 PM PDT 24
Peak memory 223568 kb
Host smart-e8cad0b8-2969-42f8-a104-06e27e597a21
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3322827841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3322827841
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.4283525158
Short name T1682
Test name
Test status
Simulation time 185071659 ps
CPU time 0.86 seconds
Started Aug 07 06:04:52 PM PDT 24
Finished Aug 07 06:04:53 PM PDT 24
Peak memory 207008 kb
Host smart-a86902b9-d6bb-4c03-a98f-887ed41b110c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42835
25158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.4283525158
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.855681843
Short name T801
Test name
Test status
Simulation time 210141615 ps
CPU time 0.98 seconds
Started Aug 07 06:04:53 PM PDT 24
Finished Aug 07 06:04:54 PM PDT 24
Peak memory 207012 kb
Host smart-d51f5e68-1168-4c55-9f47-bc759d3e63bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85568
1843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.855681843
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.2034298350
Short name T1609
Test name
Test status
Simulation time 1365539866 ps
CPU time 3.2 seconds
Started Aug 07 06:04:53 PM PDT 24
Finished Aug 07 06:04:56 PM PDT 24
Peak memory 207192 kb
Host smart-19cc0419-78fe-4fa7-97d5-cccfe5671a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20342
98350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.2034298350
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.642058829
Short name T2346
Test name
Test status
Simulation time 3379548758 ps
CPU time 27.76 seconds
Started Aug 07 06:04:55 PM PDT 24
Finished Aug 07 06:05:23 PM PDT 24
Peak memory 215528 kb
Host smart-59f8ba16-cb00-4874-b7ae-2cde0293994c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64205
8829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.642058829
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.916142871
Short name T1646
Test name
Test status
Simulation time 537930546 ps
CPU time 11.83 seconds
Started Aug 07 06:04:47 PM PDT 24
Finished Aug 07 06:04:59 PM PDT 24
Peak memory 207176 kb
Host smart-55726e41-fa03-4b0b-a9d6-272ea3446777
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916142871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_host
_handshake.916142871
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.3651762403
Short name T2704
Test name
Test status
Simulation time 48570925 ps
CPU time 0.7 seconds
Started Aug 07 05:59:19 PM PDT 24
Finished Aug 07 05:59:20 PM PDT 24
Peak memory 207088 kb
Host smart-3271f61a-3136-45d9-b132-ae710267dd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3651762403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3651762403
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1985426389
Short name T669
Test name
Test status
Simulation time 4101663100 ps
CPU time 5.86 seconds
Started Aug 07 05:59:03 PM PDT 24
Finished Aug 07 05:59:09 PM PDT 24
Peak memory 215360 kb
Host smart-7244ac7e-3202-4f28-9ce2-4cf546a53465
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985426389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.1985426389
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2911215326
Short name T620
Test name
Test status
Simulation time 19431387948 ps
CPU time 20.36 seconds
Started Aug 07 05:59:04 PM PDT 24
Finished Aug 07 05:59:24 PM PDT 24
Peak memory 207468 kb
Host smart-33c11323-8a16-456a-8d57-ff8df46e7346
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911215326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2911215326
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.1456517871
Short name T2573
Test name
Test status
Simulation time 28784136875 ps
CPU time 35.56 seconds
Started Aug 07 05:59:01 PM PDT 24
Finished Aug 07 05:59:37 PM PDT 24
Peak memory 207208 kb
Host smart-2834001a-3b58-46c1-9894-bc681a8e7a22
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456517871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.1456517871
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3059485676
Short name T1086
Test name
Test status
Simulation time 200446446 ps
CPU time 0.91 seconds
Started Aug 07 05:59:02 PM PDT 24
Finished Aug 07 05:59:03 PM PDT 24
Peak memory 206932 kb
Host smart-a9353c41-cc60-4b0b-882e-3ba73175db7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30594
85676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3059485676
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2185024609
Short name T53
Test name
Test status
Simulation time 171240139 ps
CPU time 0.85 seconds
Started Aug 07 05:59:03 PM PDT 24
Finished Aug 07 05:59:04 PM PDT 24
Peak memory 207016 kb
Host smart-999d6b93-6feb-4fb5-bc79-d14d52701775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21850
24609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2185024609
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.1085803465
Short name T80
Test name
Test status
Simulation time 171259361 ps
CPU time 0.95 seconds
Started Aug 07 05:59:02 PM PDT 24
Finished Aug 07 05:59:03 PM PDT 24
Peak memory 206956 kb
Host smart-014cf700-de44-4acd-93d0-94b86b1ae6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10858
03465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.1085803465
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.4207394273
Short name T1014
Test name
Test status
Simulation time 366656218 ps
CPU time 1.38 seconds
Started Aug 07 05:59:01 PM PDT 24
Finished Aug 07 05:59:03 PM PDT 24
Peak memory 206992 kb
Host smart-cc8dc431-fca8-4b4c-9a0e-419493ef05da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42073
94273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.4207394273
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3941012435
Short name T2395
Test name
Test status
Simulation time 291211097 ps
CPU time 1.07 seconds
Started Aug 07 05:59:02 PM PDT 24
Finished Aug 07 05:59:03 PM PDT 24
Peak memory 206996 kb
Host smart-58eddd41-25cb-4bfe-896b-c8f4f7ed3c95
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3941012435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3941012435
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.3991391043
Short name T2522
Test name
Test status
Simulation time 54713140834 ps
CPU time 84.8 seconds
Started Aug 07 05:59:01 PM PDT 24
Finished Aug 07 06:00:26 PM PDT 24
Peak memory 207348 kb
Host smart-2706a5bf-3ec1-4f19-b961-249ae53400aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39913
91043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.3991391043
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.3919657560
Short name T2881
Test name
Test status
Simulation time 626195743 ps
CPU time 5.15 seconds
Started Aug 07 05:59:10 PM PDT 24
Finished Aug 07 05:59:15 PM PDT 24
Peak memory 207192 kb
Host smart-326e11d2-b7eb-47fa-aae8-139f545c5507
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919657560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.3919657560
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3021165122
Short name T2225
Test name
Test status
Simulation time 1202746674 ps
CPU time 2.43 seconds
Started Aug 07 05:59:12 PM PDT 24
Finished Aug 07 05:59:15 PM PDT 24
Peak memory 206932 kb
Host smart-e91e1aa2-c451-490c-b8f2-eef755f49c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30211
65122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3021165122
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2683064265
Short name T1126
Test name
Test status
Simulation time 145995283 ps
CPU time 0.83 seconds
Started Aug 07 05:59:08 PM PDT 24
Finished Aug 07 05:59:09 PM PDT 24
Peak memory 206964 kb
Host smart-c95ff933-19c7-4f4d-a548-ae7617a1f588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26830
64265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2683064265
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2208555624
Short name T1091
Test name
Test status
Simulation time 37674375 ps
CPU time 0.69 seconds
Started Aug 07 05:59:09 PM PDT 24
Finished Aug 07 05:59:10 PM PDT 24
Peak memory 206944 kb
Host smart-627d8190-a2e6-4ac4-a963-9ba7663784d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22085
55624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2208555624
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.2145090465
Short name T3069
Test name
Test status
Simulation time 921916571 ps
CPU time 2.43 seconds
Started Aug 07 05:59:09 PM PDT 24
Finished Aug 07 05:59:12 PM PDT 24
Peak memory 207200 kb
Host smart-2f7d3fc8-a890-4920-af19-052f3269aa4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21450
90465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2145090465
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_types.1268316041
Short name T389
Test name
Test status
Simulation time 340952730 ps
CPU time 1.17 seconds
Started Aug 07 05:59:09 PM PDT 24
Finished Aug 07 05:59:10 PM PDT 24
Peak memory 206972 kb
Host smart-de7b6862-feec-484a-87c4-dda43366242b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1268316041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.1268316041
Directory /workspace/3.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3338700465
Short name T1010
Test name
Test status
Simulation time 147480205 ps
CPU time 1.35 seconds
Started Aug 07 05:59:07 PM PDT 24
Finished Aug 07 05:59:09 PM PDT 24
Peak memory 207144 kb
Host smart-4a41968e-e3c8-48da-84a4-311fdde1f25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33387
00465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3338700465
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3782471127
Short name T929
Test name
Test status
Simulation time 84176877038 ps
CPU time 159.73 seconds
Started Aug 07 05:59:09 PM PDT 24
Finished Aug 07 06:01:49 PM PDT 24
Peak memory 207316 kb
Host smart-b60133da-d69e-439f-aa52-8755d4faea3b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3782471127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3782471127
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.3536182935
Short name T1401
Test name
Test status
Simulation time 82162128540 ps
CPU time 131.47 seconds
Started Aug 07 05:59:07 PM PDT 24
Finished Aug 07 06:01:18 PM PDT 24
Peak memory 207296 kb
Host smart-fc0493b4-600b-4ff7-9fb6-dedc41ad621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536182935 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3536182935
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.266679965
Short name T1777
Test name
Test status
Simulation time 81170423953 ps
CPU time 127.22 seconds
Started Aug 07 05:59:06 PM PDT 24
Finished Aug 07 06:01:13 PM PDT 24
Peak memory 207208 kb
Host smart-0532d1da-f243-4f41-9d3a-3cb3a907ed4f
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=266679965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.266679965
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.2069666924
Short name T1778
Test name
Test status
Simulation time 83968094637 ps
CPU time 140.57 seconds
Started Aug 07 05:59:07 PM PDT 24
Finished Aug 07 06:01:28 PM PDT 24
Peak memory 207248 kb
Host smart-7f835aba-92c3-4c64-9d8d-7a5819d67e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069666924 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.2069666924
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.2690300744
Short name T327
Test name
Test status
Simulation time 101120858377 ps
CPU time 185 seconds
Started Aug 07 05:59:09 PM PDT 24
Finished Aug 07 06:02:15 PM PDT 24
Peak memory 207300 kb
Host smart-64a56cc5-09e6-4ef6-ba60-8bf8fb26711d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26903
00744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.2690300744
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3340001417
Short name T894
Test name
Test status
Simulation time 223546138 ps
CPU time 1.1 seconds
Started Aug 07 05:59:08 PM PDT 24
Finished Aug 07 05:59:09 PM PDT 24
Peak memory 207196 kb
Host smart-7eafb280-db95-4b8f-81d3-264fa986f373
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3340001417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3340001417
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3817774366
Short name T1049
Test name
Test status
Simulation time 149261591 ps
CPU time 0.9 seconds
Started Aug 07 05:59:08 PM PDT 24
Finished Aug 07 05:59:09 PM PDT 24
Peak memory 206872 kb
Host smart-11e4e094-01ca-448d-adf5-2bd981f73c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38177
74366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3817774366
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1820284128
Short name T930
Test name
Test status
Simulation time 262438994 ps
CPU time 1.08 seconds
Started Aug 07 05:59:11 PM PDT 24
Finished Aug 07 05:59:12 PM PDT 24
Peak memory 206984 kb
Host smart-ae74185b-afc1-43dc-9dc7-973331b42fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18202
84128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1820284128
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.347293511
Short name T2477
Test name
Test status
Simulation time 4063979130 ps
CPU time 43.37 seconds
Started Aug 07 05:59:10 PM PDT 24
Finished Aug 07 05:59:54 PM PDT 24
Peak memory 217356 kb
Host smart-daaaf0a1-46a4-4ea5-908a-e469364fc71d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=347293511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.347293511
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.1663848832
Short name T1488
Test name
Test status
Simulation time 10249827800 ps
CPU time 76.17 seconds
Started Aug 07 05:59:08 PM PDT 24
Finished Aug 07 06:00:24 PM PDT 24
Peak memory 207280 kb
Host smart-5307af93-21a0-4752-b077-c6a0c2fbc3f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1663848832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.1663848832
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1283437399
Short name T2257
Test name
Test status
Simulation time 240864275 ps
CPU time 0.98 seconds
Started Aug 07 05:59:08 PM PDT 24
Finished Aug 07 05:59:09 PM PDT 24
Peak memory 207016 kb
Host smart-fb8c9d8f-26a8-4d46-a407-0328c81feb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12834
37399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1283437399
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.2512245635
Short name T64
Test name
Test status
Simulation time 29505357544 ps
CPU time 45.75 seconds
Started Aug 07 05:59:09 PM PDT 24
Finished Aug 07 05:59:55 PM PDT 24
Peak memory 207288 kb
Host smart-c7b9fac7-664f-437f-b935-7a54be9c530a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25122
45635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.2512245635
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.3966063803
Short name T748
Test name
Test status
Simulation time 3792729783 ps
CPU time 5.51 seconds
Started Aug 07 05:59:08 PM PDT 24
Finished Aug 07 05:59:14 PM PDT 24
Peak memory 216300 kb
Host smart-974e8196-aec3-4b5a-acc1-6d97879c94f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39660
63803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.3966063803
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2538853003
Short name T727
Test name
Test status
Simulation time 3032796089 ps
CPU time 21.23 seconds
Started Aug 07 05:59:08 PM PDT 24
Finished Aug 07 05:59:29 PM PDT 24
Peak memory 218132 kb
Host smart-6d86167b-ef65-419c-b538-4b60ea3e2945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25388
53003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2538853003
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.580253484
Short name T1670
Test name
Test status
Simulation time 3419627491 ps
CPU time 26.27 seconds
Started Aug 07 05:59:08 PM PDT 24
Finished Aug 07 05:59:35 PM PDT 24
Peak memory 215432 kb
Host smart-9115d0fe-549a-4582-a78c-a32247060e79
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=580253484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.580253484
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.264487830
Short name T1899
Test name
Test status
Simulation time 234807572 ps
CPU time 0.98 seconds
Started Aug 07 05:59:07 PM PDT 24
Finished Aug 07 05:59:08 PM PDT 24
Peak memory 207012 kb
Host smart-99aa4b4b-a5f1-44d4-ae3a-13aaacbebfcb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=264487830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.264487830
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.724589781
Short name T600
Test name
Test status
Simulation time 199441117 ps
CPU time 0.94 seconds
Started Aug 07 05:59:09 PM PDT 24
Finished Aug 07 05:59:11 PM PDT 24
Peak memory 207020 kb
Host smart-a72e0c18-ad52-47fe-8e94-d690c812c4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72458
9781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.724589781
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.2708901195
Short name T1397
Test name
Test status
Simulation time 2088931909 ps
CPU time 16.57 seconds
Started Aug 07 05:59:07 PM PDT 24
Finished Aug 07 05:59:24 PM PDT 24
Peak memory 223596 kb
Host smart-5162010f-a735-46f0-a4d9-e63c355dce50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27089
01195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.2708901195
Directory /workspace/3.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3983158673
Short name T125
Test name
Test status
Simulation time 2594618762 ps
CPU time 27.51 seconds
Started Aug 07 05:59:07 PM PDT 24
Finished Aug 07 05:59:35 PM PDT 24
Peak memory 223684 kb
Host smart-e6171418-1ec5-49fd-9e82-0b86e43bf7d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3983158673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3983158673
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.1669106030
Short name T1454
Test name
Test status
Simulation time 2738974333 ps
CPU time 23.49 seconds
Started Aug 07 05:59:07 PM PDT 24
Finished Aug 07 05:59:30 PM PDT 24
Peak memory 223648 kb
Host smart-360bf8e9-7c6c-44ad-a3c7-a707042761ec
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1669106030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.1669106030
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.87971312
Short name T3109
Test name
Test status
Simulation time 153838444 ps
CPU time 0.85 seconds
Started Aug 07 05:59:08 PM PDT 24
Finished Aug 07 05:59:09 PM PDT 24
Peak memory 206988 kb
Host smart-d2f41201-d012-49e5-af42-c6e0f7aae338
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=87971312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.87971312
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.4225973453
Short name T874
Test name
Test status
Simulation time 135716654 ps
CPU time 0.83 seconds
Started Aug 07 05:59:12 PM PDT 24
Finished Aug 07 05:59:13 PM PDT 24
Peak memory 206956 kb
Host smart-1c90e7d3-5987-4646-b19e-0623997658c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42259
73453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.4225973453
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.4231379765
Short name T154
Test name
Test status
Simulation time 231177764 ps
CPU time 1.01 seconds
Started Aug 07 05:59:13 PM PDT 24
Finished Aug 07 05:59:14 PM PDT 24
Peak memory 207020 kb
Host smart-0c263ddd-71b3-4bb4-85ef-877318472a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42313
79765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.4231379765
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3019043513
Short name T2415
Test name
Test status
Simulation time 214455432 ps
CPU time 1.01 seconds
Started Aug 07 05:59:14 PM PDT 24
Finished Aug 07 05:59:15 PM PDT 24
Peak memory 207024 kb
Host smart-ec04f43b-1744-4d3c-aa15-e4ce087de16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30190
43513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3019043513
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.1639221970
Short name T2624
Test name
Test status
Simulation time 170528465 ps
CPU time 0.89 seconds
Started Aug 07 05:59:14 PM PDT 24
Finished Aug 07 05:59:15 PM PDT 24
Peak memory 206984 kb
Host smart-140b95aa-93c1-474d-9d6c-0587e0f71fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16392
21970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1639221970
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3573003178
Short name T3089
Test name
Test status
Simulation time 172180999 ps
CPU time 0.87 seconds
Started Aug 07 05:59:18 PM PDT 24
Finished Aug 07 05:59:19 PM PDT 24
Peak memory 206956 kb
Host smart-0bf64d77-f7a6-4bd4-931c-17a3c201fb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35730
03178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3573003178
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2008851993
Short name T2247
Test name
Test status
Simulation time 150311354 ps
CPU time 0.86 seconds
Started Aug 07 05:59:14 PM PDT 24
Finished Aug 07 05:59:15 PM PDT 24
Peak memory 207016 kb
Host smart-962f3490-6872-4049-aca7-2602ac56bf18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20088
51993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2008851993
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2328712437
Short name T1740
Test name
Test status
Simulation time 257606556 ps
CPU time 1.14 seconds
Started Aug 07 05:59:12 PM PDT 24
Finished Aug 07 05:59:14 PM PDT 24
Peak memory 206932 kb
Host smart-ad62bd83-0835-4ab2-a577-40592fc84ff5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2328712437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2328712437
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.1624565811
Short name T222
Test name
Test status
Simulation time 264860770 ps
CPU time 1 seconds
Started Aug 07 05:59:18 PM PDT 24
Finished Aug 07 05:59:20 PM PDT 24
Peak memory 206964 kb
Host smart-a20b9685-c5f0-4380-acca-60e487c7fe1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16245
65811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.1624565811
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2403294124
Short name T210
Test name
Test status
Simulation time 140571448 ps
CPU time 0.82 seconds
Started Aug 07 05:59:13 PM PDT 24
Finished Aug 07 05:59:14 PM PDT 24
Peak memory 206872 kb
Host smart-df58bd6a-4d10-4d06-a4a4-cedf37958f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24032
94124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2403294124
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2703305992
Short name T1152
Test name
Test status
Simulation time 41854745 ps
CPU time 0.7 seconds
Started Aug 07 05:59:14 PM PDT 24
Finished Aug 07 05:59:15 PM PDT 24
Peak memory 206932 kb
Host smart-f278d388-6ecc-40eb-8f82-03eec01fa08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27033
05992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2703305992
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3784277245
Short name T268
Test name
Test status
Simulation time 16330169479 ps
CPU time 42.4 seconds
Started Aug 07 05:59:13 PM PDT 24
Finished Aug 07 05:59:56 PM PDT 24
Peak memory 215568 kb
Host smart-314867a3-59cb-4ef9-839d-aa53882346b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37842
77245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3784277245
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.588434842
Short name T1004
Test name
Test status
Simulation time 158933511 ps
CPU time 0.89 seconds
Started Aug 07 05:59:13 PM PDT 24
Finished Aug 07 05:59:15 PM PDT 24
Peak memory 206996 kb
Host smart-00bb62fe-026d-40c1-8eb0-646268d4be12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58843
4842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.588434842
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1827875399
Short name T2973
Test name
Test status
Simulation time 169789493 ps
CPU time 0.9 seconds
Started Aug 07 05:59:15 PM PDT 24
Finished Aug 07 05:59:16 PM PDT 24
Peak memory 206956 kb
Host smart-1f21dc9f-f3c5-4f92-b729-c9621751ac20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18278
75399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1827875399
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.1060918430
Short name T2367
Test name
Test status
Simulation time 2697938509 ps
CPU time 17.96 seconds
Started Aug 07 05:59:14 PM PDT 24
Finished Aug 07 05:59:32 PM PDT 24
Peak memory 217652 kb
Host smart-28cda47b-0080-4b00-9519-c879e543f389
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060918430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.1060918430
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.3465034882
Short name T1688
Test name
Test status
Simulation time 3188217564 ps
CPU time 17.79 seconds
Started Aug 07 05:59:18 PM PDT 24
Finished Aug 07 05:59:36 PM PDT 24
Peak memory 223636 kb
Host smart-a32c27f8-7be0-4b3c-aa25-ffa304295a28
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3465034882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.3465034882
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2402399654
Short name T1105
Test name
Test status
Simulation time 5925042173 ps
CPU time 20.71 seconds
Started Aug 07 05:59:15 PM PDT 24
Finished Aug 07 05:59:36 PM PDT 24
Peak memory 215492 kb
Host smart-11761828-8590-4916-91f9-45b88b3a1090
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402399654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2402399654
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.3759717864
Short name T2177
Test name
Test status
Simulation time 202736261 ps
CPU time 0.91 seconds
Started Aug 07 05:59:12 PM PDT 24
Finished Aug 07 05:59:13 PM PDT 24
Peak memory 206996 kb
Host smart-3eb127f2-c29a-4594-95cb-fe67d4ed5058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37597
17864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.3759717864
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.674415308
Short name T1420
Test name
Test status
Simulation time 144008737 ps
CPU time 0.79 seconds
Started Aug 07 05:59:14 PM PDT 24
Finished Aug 07 05:59:15 PM PDT 24
Peak memory 207000 kb
Host smart-38240607-9e35-43ad-abc3-460375bdefc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67441
5308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.674415308
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_resume_link_active.3912627412
Short name T2997
Test name
Test status
Simulation time 20227573795 ps
CPU time 29.38 seconds
Started Aug 07 05:59:14 PM PDT 24
Finished Aug 07 05:59:44 PM PDT 24
Peak memory 207092 kb
Host smart-26b4c6c6-8bb5-40f5-adca-3b9996b32593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39126
27412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.3912627412
Directory /workspace/3.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3203677766
Short name T2934
Test name
Test status
Simulation time 171174521 ps
CPU time 0.87 seconds
Started Aug 07 05:59:13 PM PDT 24
Finished Aug 07 05:59:14 PM PDT 24
Peak memory 206972 kb
Host smart-11fe2370-d815-4ad9-9999-73e0d7d92a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32036
77766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3203677766
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_full.196075468
Short name T310
Test name
Test status
Simulation time 264302071 ps
CPU time 1.1 seconds
Started Aug 07 05:59:19 PM PDT 24
Finished Aug 07 05:59:20 PM PDT 24
Peak memory 206864 kb
Host smart-f4fef2bb-a7a8-4582-98c0-a345297da066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19607
5468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.196075468
Directory /workspace/3.usbdev_rx_full/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.1445001945
Short name T75
Test name
Test status
Simulation time 157500372 ps
CPU time 0.84 seconds
Started Aug 07 05:59:17 PM PDT 24
Finished Aug 07 05:59:18 PM PDT 24
Peak memory 207004 kb
Host smart-66fca93e-2ede-4031-a339-e2626cf689d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14450
01945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.1445001945
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3702775428
Short name T213
Test name
Test status
Simulation time 567611559 ps
CPU time 1.48 seconds
Started Aug 07 05:59:19 PM PDT 24
Finished Aug 07 05:59:21 PM PDT 24
Peak memory 223908 kb
Host smart-d32e59f7-b7d9-479d-98a5-0f82e89035c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3702775428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3702775428
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.1315152262
Short name T2307
Test name
Test status
Simulation time 259709703 ps
CPU time 0.98 seconds
Started Aug 07 05:59:16 PM PDT 24
Finished Aug 07 05:59:17 PM PDT 24
Peak memory 207032 kb
Host smart-dae30d57-c1d0-4960-8bd2-b1f8d3bbe252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13151
52262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.1315152262
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.136918992
Short name T2031
Test name
Test status
Simulation time 173364940 ps
CPU time 0.85 seconds
Started Aug 07 05:59:17 PM PDT 24
Finished Aug 07 05:59:18 PM PDT 24
Peak memory 206984 kb
Host smart-24f900d5-6c32-4538-bc9d-820945540239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13691
8992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.136918992
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.373853256
Short name T1546
Test name
Test status
Simulation time 153184345 ps
CPU time 0.83 seconds
Started Aug 07 05:59:17 PM PDT 24
Finished Aug 07 05:59:18 PM PDT 24
Peak memory 207012 kb
Host smart-24c0b1c6-97fc-41ad-babf-d8bfc61287cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37385
3256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.373853256
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1793664979
Short name T1930
Test name
Test status
Simulation time 247275459 ps
CPU time 1.07 seconds
Started Aug 07 05:59:19 PM PDT 24
Finished Aug 07 05:59:20 PM PDT 24
Peak memory 206992 kb
Host smart-bf35c81a-d764-4764-81ab-29e68ff54d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17936
64979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1793664979
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3232996957
Short name T786
Test name
Test status
Simulation time 2330991500 ps
CPU time 17.16 seconds
Started Aug 07 05:59:19 PM PDT 24
Finished Aug 07 05:59:37 PM PDT 24
Peak memory 207244 kb
Host smart-bba6c867-7e8e-4a56-8509-f59be87ccc8c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3232996957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3232996957
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.834971186
Short name T2819
Test name
Test status
Simulation time 214739465 ps
CPU time 0.93 seconds
Started Aug 07 05:59:18 PM PDT 24
Finished Aug 07 05:59:19 PM PDT 24
Peak memory 206960 kb
Host smart-9dff115d-c4c4-4342-9f3e-420e2158dd2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83497
1186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.834971186
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2042417304
Short name T3115
Test name
Test status
Simulation time 151122305 ps
CPU time 0.83 seconds
Started Aug 07 05:59:18 PM PDT 24
Finished Aug 07 05:59:19 PM PDT 24
Peak memory 207016 kb
Host smart-84335c25-b280-44eb-9102-cb8a1922c4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20424
17304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2042417304
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.3306916486
Short name T2161
Test name
Test status
Simulation time 314791933 ps
CPU time 1.28 seconds
Started Aug 07 05:59:17 PM PDT 24
Finished Aug 07 05:59:19 PM PDT 24
Peak memory 206936 kb
Host smart-1790dd5d-ccc0-46d9-882e-5a4739bdda2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33069
16486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3306916486
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.782865637
Short name T2975
Test name
Test status
Simulation time 3611111602 ps
CPU time 28.41 seconds
Started Aug 07 05:59:17 PM PDT 24
Finished Aug 07 05:59:45 PM PDT 24
Peak memory 215448 kb
Host smart-65645d03-d8c0-4ff8-bc9a-8047262b059e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78286
5637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.782865637
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.1880022419
Short name T641
Test name
Test status
Simulation time 5666488203 ps
CPU time 39.21 seconds
Started Aug 07 05:59:06 PM PDT 24
Finished Aug 07 05:59:46 PM PDT 24
Peak memory 207300 kb
Host smart-3bd7c970-417f-4f97-83a5-a9c90812ce9e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880022419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.1880022419
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2608650062
Short name T1097
Test name
Test status
Simulation time 57861028 ps
CPU time 0.73 seconds
Started Aug 07 06:05:16 PM PDT 24
Finished Aug 07 06:05:17 PM PDT 24
Peak memory 207096 kb
Host smart-40bfad44-e384-4338-9e1b-2d2f646adb09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2608650062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2608650062
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1217445502
Short name T243
Test name
Test status
Simulation time 6199919640 ps
CPU time 9.64 seconds
Started Aug 07 06:04:53 PM PDT 24
Finished Aug 07 06:05:03 PM PDT 24
Peak memory 215484 kb
Host smart-ace9e045-b339-4733-b0d3-fe28e8004e73
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217445502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.1217445502
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.468281538
Short name T2576
Test name
Test status
Simulation time 25131223433 ps
CPU time 31.94 seconds
Started Aug 07 06:04:52 PM PDT 24
Finished Aug 07 06:05:24 PM PDT 24
Peak memory 215476 kb
Host smart-849e189d-2d80-4742-8371-66d6264c70ed
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468281538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ao
n_wake_resume.468281538
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1945547615
Short name T1011
Test name
Test status
Simulation time 183894881 ps
CPU time 0.96 seconds
Started Aug 07 06:04:52 PM PDT 24
Finished Aug 07 06:04:53 PM PDT 24
Peak memory 206992 kb
Host smart-ae38a446-28b1-4615-a2d2-824b86321ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19455
47615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1945547615
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.804040812
Short name T2007
Test name
Test status
Simulation time 154153359 ps
CPU time 0.82 seconds
Started Aug 07 06:04:56 PM PDT 24
Finished Aug 07 06:04:57 PM PDT 24
Peak memory 206912 kb
Host smart-5eaf7e12-4c21-4745-9d3d-fc4889a427f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80404
0812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.804040812
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.862587836
Short name T1587
Test name
Test status
Simulation time 264385133 ps
CPU time 1.08 seconds
Started Aug 07 06:04:56 PM PDT 24
Finished Aug 07 06:04:57 PM PDT 24
Peak memory 207012 kb
Host smart-e444dbfa-ba94-4692-ab99-87fde8da4155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86258
7836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.862587836
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.133538074
Short name T1064
Test name
Test status
Simulation time 803943113 ps
CPU time 2.29 seconds
Started Aug 07 06:05:00 PM PDT 24
Finished Aug 07 06:05:02 PM PDT 24
Peak memory 207096 kb
Host smart-acfdad48-4cc1-4603-855d-9a898f80b427
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=133538074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.133538074
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.4033121685
Short name T1452
Test name
Test status
Simulation time 39197330901 ps
CPU time 62.39 seconds
Started Aug 07 06:04:56 PM PDT 24
Finished Aug 07 06:05:59 PM PDT 24
Peak memory 207260 kb
Host smart-325a74c6-dcf9-42c5-98cd-cf99d41f53d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40331
21685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.4033121685
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.2030866714
Short name T1294
Test name
Test status
Simulation time 1127500290 ps
CPU time 25.59 seconds
Started Aug 07 06:05:00 PM PDT 24
Finished Aug 07 06:05:26 PM PDT 24
Peak memory 207360 kb
Host smart-294a1c16-66f8-486a-ab0a-6f3a324c227d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030866714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.2030866714
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.2574268938
Short name T827
Test name
Test status
Simulation time 898805412 ps
CPU time 1.83 seconds
Started Aug 07 06:05:01 PM PDT 24
Finished Aug 07 06:05:03 PM PDT 24
Peak memory 206888 kb
Host smart-7ed8ceb0-b557-41a8-b14d-ec4506b6a3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25742
68938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.2574268938
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2706348516
Short name T579
Test name
Test status
Simulation time 146486508 ps
CPU time 0.81 seconds
Started Aug 07 06:04:56 PM PDT 24
Finished Aug 07 06:04:57 PM PDT 24
Peak memory 206884 kb
Host smart-782bd5a3-32dc-4c9e-977f-50bc7da3c73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27063
48516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2706348516
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2966334358
Short name T1238
Test name
Test status
Simulation time 55058411 ps
CPU time 0.79 seconds
Started Aug 07 06:04:56 PM PDT 24
Finished Aug 07 06:04:57 PM PDT 24
Peak memory 206948 kb
Host smart-002fc98c-be32-4a8d-924e-4d5aabb8096d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29663
34358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2966334358
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.4292301483
Short name T2784
Test name
Test status
Simulation time 784202516 ps
CPU time 2.24 seconds
Started Aug 07 06:04:55 PM PDT 24
Finished Aug 07 06:04:58 PM PDT 24
Peak memory 207176 kb
Host smart-207de4d7-ff6a-4fb3-a26a-1045f64b7774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42923
01483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.4292301483
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_types.659775998
Short name T353
Test name
Test status
Simulation time 417622611 ps
CPU time 1.19 seconds
Started Aug 07 06:04:58 PM PDT 24
Finished Aug 07 06:04:59 PM PDT 24
Peak memory 206944 kb
Host smart-656c0e9a-9b00-41ce-910b-e18e6f5111f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=659775998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.659775998
Directory /workspace/30.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2676734826
Short name T201
Test name
Test status
Simulation time 239046250 ps
CPU time 1.77 seconds
Started Aug 07 06:04:57 PM PDT 24
Finished Aug 07 06:04:59 PM PDT 24
Peak memory 207180 kb
Host smart-075fc0fd-af72-486a-92f3-123768a63ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26767
34826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2676734826
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1446373960
Short name T2475
Test name
Test status
Simulation time 225859591 ps
CPU time 1.15 seconds
Started Aug 07 06:04:57 PM PDT 24
Finished Aug 07 06:04:58 PM PDT 24
Peak memory 207160 kb
Host smart-372c8570-16bd-4eb9-a896-0aa734534519
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1446373960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1446373960
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3708355574
Short name T691
Test name
Test status
Simulation time 145476562 ps
CPU time 0.79 seconds
Started Aug 07 06:05:01 PM PDT 24
Finished Aug 07 06:05:02 PM PDT 24
Peak memory 206936 kb
Host smart-982927d8-4b20-4b29-877b-abc55eba8d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37083
55574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3708355574
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2932559932
Short name T1192
Test name
Test status
Simulation time 198401164 ps
CPU time 0.91 seconds
Started Aug 07 06:05:03 PM PDT 24
Finished Aug 07 06:05:04 PM PDT 24
Peak memory 206908 kb
Host smart-5a18879b-0708-46c6-b2fa-f08decdef02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29325
59932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2932559932
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.4274525295
Short name T1973
Test name
Test status
Simulation time 3817093781 ps
CPU time 109.65 seconds
Started Aug 07 06:05:00 PM PDT 24
Finished Aug 07 06:06:49 PM PDT 24
Peak memory 223548 kb
Host smart-7954fbf9-3332-4375-bd22-275e780141ad
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4274525295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.4274525295
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.3474508934
Short name T713
Test name
Test status
Simulation time 4561621670 ps
CPU time 55.02 seconds
Started Aug 07 06:05:06 PM PDT 24
Finished Aug 07 06:06:01 PM PDT 24
Peak memory 207212 kb
Host smart-bb5444d4-37a3-4630-9c51-7eb933686400
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3474508934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.3474508934
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.4167979491
Short name T2517
Test name
Test status
Simulation time 223422098 ps
CPU time 1.03 seconds
Started Aug 07 06:05:01 PM PDT 24
Finished Aug 07 06:05:02 PM PDT 24
Peak memory 207016 kb
Host smart-2a3adf9c-1b07-4991-b8bd-5d14724d9dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41679
79491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.4167979491
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.1231520536
Short name T2082
Test name
Test status
Simulation time 24460033936 ps
CPU time 38.5 seconds
Started Aug 07 06:05:05 PM PDT 24
Finished Aug 07 06:05:44 PM PDT 24
Peak memory 215480 kb
Host smart-5ba5158f-f050-4431-9d5b-4b5cb3f7838c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12315
20536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.1231520536
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1678216175
Short name T708
Test name
Test status
Simulation time 8731876560 ps
CPU time 12.15 seconds
Started Aug 07 06:05:02 PM PDT 24
Finished Aug 07 06:05:14 PM PDT 24
Peak memory 207236 kb
Host smart-9bc52d97-7e2d-4d8f-b3fb-44d38c87246a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16782
16175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1678216175
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.2836545503
Short name T1767
Test name
Test status
Simulation time 3154147246 ps
CPU time 30.69 seconds
Started Aug 07 06:05:03 PM PDT 24
Finished Aug 07 06:05:34 PM PDT 24
Peak memory 218048 kb
Host smart-246c0996-6291-46c8-be7f-6062e96e2cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28365
45503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2836545503
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.2574918910
Short name T2036
Test name
Test status
Simulation time 3796903079 ps
CPU time 30.37 seconds
Started Aug 07 06:05:06 PM PDT 24
Finished Aug 07 06:05:36 PM PDT 24
Peak memory 215524 kb
Host smart-138a6c01-fa07-439c-be87-d9967e81f0fd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2574918910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.2574918910
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.3328854759
Short name T2585
Test name
Test status
Simulation time 250953981 ps
CPU time 1.05 seconds
Started Aug 07 06:05:01 PM PDT 24
Finished Aug 07 06:05:02 PM PDT 24
Peak memory 207016 kb
Host smart-6a218df5-442e-4b4c-ad79-bddf439cbb09
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3328854759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.3328854759
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2409361115
Short name T1029
Test name
Test status
Simulation time 184341795 ps
CPU time 0.99 seconds
Started Aug 07 06:05:02 PM PDT 24
Finished Aug 07 06:05:03 PM PDT 24
Peak memory 207036 kb
Host smart-14bb6849-2aca-404e-8165-4b27a1065faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24093
61115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2409361115
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.4038032692
Short name T1556
Test name
Test status
Simulation time 2143450523 ps
CPU time 61.43 seconds
Started Aug 07 06:05:02 PM PDT 24
Finished Aug 07 06:06:04 PM PDT 24
Peak memory 215320 kb
Host smart-2fb31489-14a2-4d62-b257-681bbfcdbcab
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4038032692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.4038032692
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2441489833
Short name T1212
Test name
Test status
Simulation time 183995874 ps
CPU time 0.87 seconds
Started Aug 07 06:05:01 PM PDT 24
Finished Aug 07 06:05:02 PM PDT 24
Peak memory 207020 kb
Host smart-6e05f814-408c-4dc5-91c0-4ffc06b7323b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2441489833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2441489833
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.4278912576
Short name T1273
Test name
Test status
Simulation time 146499361 ps
CPU time 0.9 seconds
Started Aug 07 06:05:02 PM PDT 24
Finished Aug 07 06:05:03 PM PDT 24
Peak memory 206964 kb
Host smart-8657f7ff-bde1-4aea-9d48-8b01270cb98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42789
12576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.4278912576
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2255779269
Short name T144
Test name
Test status
Simulation time 210251216 ps
CPU time 1.01 seconds
Started Aug 07 06:05:03 PM PDT 24
Finished Aug 07 06:05:04 PM PDT 24
Peak memory 207008 kb
Host smart-64fd5503-97d0-4e4a-94cf-f612cd684626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22557
79269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2255779269
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3177781797
Short name T1419
Test name
Test status
Simulation time 195226523 ps
CPU time 1 seconds
Started Aug 07 06:05:02 PM PDT 24
Finished Aug 07 06:05:03 PM PDT 24
Peak memory 207012 kb
Host smart-4bf1a4ae-902e-4513-951a-649259201959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31777
81797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3177781797
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.81692363
Short name T2671
Test name
Test status
Simulation time 177098440 ps
CPU time 0.91 seconds
Started Aug 07 06:05:07 PM PDT 24
Finished Aug 07 06:05:08 PM PDT 24
Peak memory 206992 kb
Host smart-a9b563d6-c481-4839-a8cb-2b6ca4a3f7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81692
363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.81692363
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1438707944
Short name T1877
Test name
Test status
Simulation time 155056070 ps
CPU time 0.86 seconds
Started Aug 07 06:05:07 PM PDT 24
Finished Aug 07 06:05:08 PM PDT 24
Peak memory 206904 kb
Host smart-1e5e7681-fd0a-4764-a161-e85baadbc392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14387
07944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1438707944
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.411343156
Short name T1383
Test name
Test status
Simulation time 178460409 ps
CPU time 0.88 seconds
Started Aug 07 06:05:06 PM PDT 24
Finished Aug 07 06:05:07 PM PDT 24
Peak memory 206944 kb
Host smart-e3109898-8a2d-4077-8809-a2ecddccb6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41134
3156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.411343156
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.2625810466
Short name T3029
Test name
Test status
Simulation time 237731761 ps
CPU time 1.07 seconds
Started Aug 07 06:05:10 PM PDT 24
Finished Aug 07 06:05:11 PM PDT 24
Peak memory 207004 kb
Host smart-d5f29f23-3e2a-4b26-9079-c7338c963829
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2625810466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.2625810466
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1289463353
Short name T1816
Test name
Test status
Simulation time 157590823 ps
CPU time 0.85 seconds
Started Aug 07 06:05:08 PM PDT 24
Finished Aug 07 06:05:09 PM PDT 24
Peak memory 206864 kb
Host smart-712f26e4-3b3e-43a9-936d-4c0c688e4fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12894
63353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1289463353
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1925658573
Short name T1306
Test name
Test status
Simulation time 59585604 ps
CPU time 0.7 seconds
Started Aug 07 06:05:07 PM PDT 24
Finished Aug 07 06:05:08 PM PDT 24
Peak memory 206972 kb
Host smart-904e1861-7cde-43d7-a856-d41e5490b98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19256
58573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1925658573
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.914367003
Short name T266
Test name
Test status
Simulation time 9223195607 ps
CPU time 23.3 seconds
Started Aug 07 06:05:06 PM PDT 24
Finished Aug 07 06:05:30 PM PDT 24
Peak memory 215488 kb
Host smart-415ee80f-ca75-4d8f-98bf-1e6bab623f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91436
7003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.914367003
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2761928124
Short name T599
Test name
Test status
Simulation time 193136937 ps
CPU time 0.93 seconds
Started Aug 07 06:05:06 PM PDT 24
Finished Aug 07 06:05:07 PM PDT 24
Peak memory 206956 kb
Host smart-61c013ba-f873-4c8e-a3bb-e10a25494fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27619
28124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2761928124
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2874701697
Short name T755
Test name
Test status
Simulation time 212314831 ps
CPU time 0.98 seconds
Started Aug 07 06:05:22 PM PDT 24
Finished Aug 07 06:05:23 PM PDT 24
Peak memory 206904 kb
Host smart-5e3bfb70-cdd7-45c1-ab47-7df662fff87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28747
01697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2874701697
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1605680689
Short name T1560
Test name
Test status
Simulation time 219515733 ps
CPU time 1.01 seconds
Started Aug 07 06:05:06 PM PDT 24
Finished Aug 07 06:05:07 PM PDT 24
Peak memory 207000 kb
Host smart-cffd7a9c-f611-487f-b0ce-6a1f9c4c4f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16056
80689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1605680689
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.1711800239
Short name T1910
Test name
Test status
Simulation time 169030306 ps
CPU time 0.91 seconds
Started Aug 07 06:05:07 PM PDT 24
Finished Aug 07 06:05:08 PM PDT 24
Peak memory 207016 kb
Host smart-23368ad3-9e67-40bf-86da-c6c7d55c0d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17118
00239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1711800239
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3507870965
Short name T952
Test name
Test status
Simulation time 180970437 ps
CPU time 0.89 seconds
Started Aug 07 06:05:05 PM PDT 24
Finished Aug 07 06:05:06 PM PDT 24
Peak memory 206956 kb
Host smart-60f3c94d-4dc3-4205-8e7d-ca2ec1c4fe5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35078
70965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3507870965
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_rx_full.405069109
Short name T1295
Test name
Test status
Simulation time 266135551 ps
CPU time 1.1 seconds
Started Aug 07 06:05:10 PM PDT 24
Finished Aug 07 06:05:11 PM PDT 24
Peak memory 206956 kb
Host smart-1b4ca179-2b37-4304-bdb3-192d79e7a1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40506
9109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.405069109
Directory /workspace/30.usbdev_rx_full/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2464923971
Short name T989
Test name
Test status
Simulation time 165147669 ps
CPU time 0.86 seconds
Started Aug 07 06:05:12 PM PDT 24
Finished Aug 07 06:05:13 PM PDT 24
Peak memory 206960 kb
Host smart-fa40694e-638f-4d0d-85b1-a328ff224e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24649
23971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2464923971
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1672960215
Short name T40
Test name
Test status
Simulation time 151801482 ps
CPU time 0.86 seconds
Started Aug 07 06:05:14 PM PDT 24
Finished Aug 07 06:05:15 PM PDT 24
Peak memory 207016 kb
Host smart-f1a39355-1511-4cf7-ba62-2c8348d4e544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16729
60215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1672960215
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1804884916
Short name T2326
Test name
Test status
Simulation time 231846510 ps
CPU time 1.01 seconds
Started Aug 07 06:05:23 PM PDT 24
Finished Aug 07 06:05:24 PM PDT 24
Peak memory 206944 kb
Host smart-1b46c19f-7602-4698-a47e-f99e6e7b334a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18048
84916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1804884916
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2795743407
Short name T170
Test name
Test status
Simulation time 2542409892 ps
CPU time 25.62 seconds
Started Aug 07 06:05:16 PM PDT 24
Finished Aug 07 06:05:41 PM PDT 24
Peak memory 217352 kb
Host smart-05822a52-e417-4366-8bac-fa7bc65ec710
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2795743407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2795743407
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3120090816
Short name T735
Test name
Test status
Simulation time 187536528 ps
CPU time 0.94 seconds
Started Aug 07 06:05:15 PM PDT 24
Finished Aug 07 06:05:16 PM PDT 24
Peak memory 206988 kb
Host smart-5924a1d5-e28e-4309-b1ef-fc8d1e53b609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31200
90816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3120090816
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2012975934
Short name T583
Test name
Test status
Simulation time 201229786 ps
CPU time 0.87 seconds
Started Aug 07 06:05:15 PM PDT 24
Finished Aug 07 06:05:16 PM PDT 24
Peak memory 207220 kb
Host smart-27e907f6-4ad3-4c16-b9b1-9bdf14324a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20129
75934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2012975934
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.1659607944
Short name T603
Test name
Test status
Simulation time 1200356558 ps
CPU time 2.79 seconds
Started Aug 07 06:05:10 PM PDT 24
Finished Aug 07 06:05:13 PM PDT 24
Peak memory 207072 kb
Host smart-42150e44-7f54-4b57-b769-4daa4e564dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16596
07944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.1659607944
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.583481698
Short name T1073
Test name
Test status
Simulation time 2276340337 ps
CPU time 22.66 seconds
Started Aug 07 06:05:14 PM PDT 24
Finished Aug 07 06:05:36 PM PDT 24
Peak memory 216576 kb
Host smart-76655364-90f0-4def-b9d2-b4921fe905a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58348
1698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.583481698
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.120801925
Short name T983
Test name
Test status
Simulation time 3350735177 ps
CPU time 30.01 seconds
Started Aug 07 06:05:00 PM PDT 24
Finished Aug 07 06:05:30 PM PDT 24
Peak memory 207468 kb
Host smart-6e70b6b1-faa4-4ea2-87b4-68507cb26bce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120801925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_host
_handshake.120801925
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2109842597
Short name T2217
Test name
Test status
Simulation time 36791896 ps
CPU time 0.68 seconds
Started Aug 07 06:05:35 PM PDT 24
Finished Aug 07 06:05:36 PM PDT 24
Peak memory 206880 kb
Host smart-9cd7b548-97f9-4b7b-aa2d-fbc29d62e197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2109842597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2109842597
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1571725764
Short name T798
Test name
Test status
Simulation time 7261102575 ps
CPU time 9.22 seconds
Started Aug 07 06:05:12 PM PDT 24
Finished Aug 07 06:05:21 PM PDT 24
Peak memory 215508 kb
Host smart-5470e9cf-1bf6-4eb0-b420-a81042591fe1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571725764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.1571725764
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3562065243
Short name T823
Test name
Test status
Simulation time 18587099125 ps
CPU time 25.38 seconds
Started Aug 07 06:05:19 PM PDT 24
Finished Aug 07 06:05:44 PM PDT 24
Peak memory 207252 kb
Host smart-83a863c4-f1bf-4c9e-ac09-c541aec02422
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562065243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3562065243
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3815360418
Short name T1409
Test name
Test status
Simulation time 30958675239 ps
CPU time 35.01 seconds
Started Aug 07 06:05:18 PM PDT 24
Finished Aug 07 06:05:54 PM PDT 24
Peak memory 207288 kb
Host smart-e7fed4d5-955a-4489-b390-2020cf143328
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815360418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.3815360418
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.4101684408
Short name T2809
Test name
Test status
Simulation time 188675022 ps
CPU time 0.94 seconds
Started Aug 07 06:05:16 PM PDT 24
Finished Aug 07 06:05:17 PM PDT 24
Peak memory 206980 kb
Host smart-08f1d8eb-ea45-4735-be76-04791fb79d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41016
84408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.4101684408
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3194597044
Short name T71
Test name
Test status
Simulation time 219743410 ps
CPU time 0.92 seconds
Started Aug 07 06:05:17 PM PDT 24
Finished Aug 07 06:05:18 PM PDT 24
Peak memory 206976 kb
Host smart-173799fc-270a-4762-bb2b-6326cef2c434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31945
97044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3194597044
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.1151935176
Short name T1748
Test name
Test status
Simulation time 528762284 ps
CPU time 1.74 seconds
Started Aug 07 06:05:18 PM PDT 24
Finished Aug 07 06:05:19 PM PDT 24
Peak memory 207012 kb
Host smart-5dcd01a0-e321-45cb-91c9-a334a5259936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11519
35176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.1151935176
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.1836979474
Short name T1742
Test name
Test status
Simulation time 830306479 ps
CPU time 2.24 seconds
Started Aug 07 06:05:20 PM PDT 24
Finished Aug 07 06:05:23 PM PDT 24
Peak memory 207188 kb
Host smart-bfaaaa77-68c1-40da-ae6b-58f69b73755f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1836979474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.1836979474
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.3076013411
Short name T178
Test name
Test status
Simulation time 59038225800 ps
CPU time 90.05 seconds
Started Aug 07 06:05:18 PM PDT 24
Finished Aug 07 06:06:49 PM PDT 24
Peak memory 207300 kb
Host smart-6915696c-8237-42cf-8bd8-dbb136fadf11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30760
13411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.3076013411
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.356721618
Short name T2262
Test name
Test status
Simulation time 1433537192 ps
CPU time 35.22 seconds
Started Aug 07 06:05:18 PM PDT 24
Finished Aug 07 06:05:53 PM PDT 24
Peak memory 207168 kb
Host smart-998f9ede-29ba-42a5-9090-c356b5683014
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356721618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.356721618
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.111894433
Short name T2767
Test name
Test status
Simulation time 466047142 ps
CPU time 1.39 seconds
Started Aug 07 06:05:19 PM PDT 24
Finished Aug 07 06:05:20 PM PDT 24
Peak memory 207004 kb
Host smart-7da59f3c-f501-423a-a522-8ed68c061860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11189
4433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.111894433
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.4289517358
Short name T2683
Test name
Test status
Simulation time 146030399 ps
CPU time 0.81 seconds
Started Aug 07 06:05:24 PM PDT 24
Finished Aug 07 06:05:25 PM PDT 24
Peak memory 206972 kb
Host smart-10da6977-cd60-4de3-8b2a-cfa72730d7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42895
17358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.4289517358
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2248132761
Short name T1811
Test name
Test status
Simulation time 47059999 ps
CPU time 0.71 seconds
Started Aug 07 06:05:27 PM PDT 24
Finished Aug 07 06:05:27 PM PDT 24
Peak memory 206856 kb
Host smart-39e346ad-4afd-45da-b13e-d611b87861bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22481
32761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2248132761
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2911113504
Short name T1356
Test name
Test status
Simulation time 966991588 ps
CPU time 2.34 seconds
Started Aug 07 06:05:30 PM PDT 24
Finished Aug 07 06:05:33 PM PDT 24
Peak memory 206676 kb
Host smart-e0689472-b257-43e3-9557-61e3011690f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29111
13504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2911113504
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_types.2109306132
Short name T361
Test name
Test status
Simulation time 609309702 ps
CPU time 1.68 seconds
Started Aug 07 06:05:27 PM PDT 24
Finished Aug 07 06:05:28 PM PDT 24
Peak memory 206888 kb
Host smart-3ea9965b-5462-4d40-bf25-e0bdd4c3239c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2109306132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.2109306132
Directory /workspace/31.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2495246577
Short name T1586
Test name
Test status
Simulation time 156916076 ps
CPU time 1.43 seconds
Started Aug 07 06:05:26 PM PDT 24
Finished Aug 07 06:05:28 PM PDT 24
Peak memory 207172 kb
Host smart-c29b0fbd-ff10-400b-9303-7f669461934f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24952
46577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2495246577
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.904600576
Short name T777
Test name
Test status
Simulation time 188732605 ps
CPU time 1.04 seconds
Started Aug 07 06:05:20 PM PDT 24
Finished Aug 07 06:05:21 PM PDT 24
Peak memory 207160 kb
Host smart-d453e02a-6791-4a4a-a88b-939d2499daa3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=904600576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.904600576
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2878070082
Short name T1305
Test name
Test status
Simulation time 139037781 ps
CPU time 0.85 seconds
Started Aug 07 06:05:25 PM PDT 24
Finished Aug 07 06:05:25 PM PDT 24
Peak memory 206968 kb
Host smart-b7daee6c-47c8-493e-b7b8-be8e5a91bb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28780
70082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2878070082
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.88740337
Short name T2175
Test name
Test status
Simulation time 198304073 ps
CPU time 0.95 seconds
Started Aug 07 06:05:32 PM PDT 24
Finished Aug 07 06:05:33 PM PDT 24
Peak memory 206952 kb
Host smart-43e0a6ee-422f-484f-8279-c91b93766e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88740
337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.88740337
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.83163775
Short name T1612
Test name
Test status
Simulation time 3522693981 ps
CPU time 28.15 seconds
Started Aug 07 06:05:32 PM PDT 24
Finished Aug 07 06:06:00 PM PDT 24
Peak memory 216772 kb
Host smart-229c0f0e-ba62-4b26-a6c1-3c5b6ce76066
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=83163775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.83163775
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.655577732
Short name T1772
Test name
Test status
Simulation time 6327626861 ps
CPU time 43.12 seconds
Started Aug 07 06:05:22 PM PDT 24
Finished Aug 07 06:06:05 PM PDT 24
Peak memory 207308 kb
Host smart-afcd059c-e871-4437-b40e-a38938db68a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=655577732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.655577732
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1447843837
Short name T2965
Test name
Test status
Simulation time 215898391 ps
CPU time 0.95 seconds
Started Aug 07 06:05:22 PM PDT 24
Finished Aug 07 06:05:23 PM PDT 24
Peak memory 207028 kb
Host smart-cddbaa6c-6018-4305-8f75-8b8e07737b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14478
43837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1447843837
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1828189304
Short name T802
Test name
Test status
Simulation time 25026871637 ps
CPU time 28.51 seconds
Started Aug 07 06:05:30 PM PDT 24
Finished Aug 07 06:05:59 PM PDT 24
Peak memory 215460 kb
Host smart-7a8e5446-abd7-4441-b97d-1bd4d2dbd150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18281
89304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1828189304
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1644479611
Short name T2947
Test name
Test status
Simulation time 3408694214 ps
CPU time 5.54 seconds
Started Aug 07 06:05:22 PM PDT 24
Finished Aug 07 06:05:27 PM PDT 24
Peak memory 207260 kb
Host smart-f225b09b-b8e2-4734-a0ae-829f2a86d0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16444
79611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1644479611
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1408775823
Short name T2780
Test name
Test status
Simulation time 4927464108 ps
CPU time 47.56 seconds
Started Aug 07 06:05:31 PM PDT 24
Finished Aug 07 06:06:19 PM PDT 24
Peak memory 217580 kb
Host smart-7bbea0ff-543f-4ca2-ae00-1f37f309e6bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14087
75823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1408775823
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1576495733
Short name T2184
Test name
Test status
Simulation time 1916204712 ps
CPU time 16.03 seconds
Started Aug 07 06:05:22 PM PDT 24
Finished Aug 07 06:05:38 PM PDT 24
Peak memory 207136 kb
Host smart-b22b3af9-e4d1-4c6d-bae2-d114c1ae0ac5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1576495733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1576495733
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.4101003065
Short name T2990
Test name
Test status
Simulation time 335088919 ps
CPU time 1.21 seconds
Started Aug 07 06:05:25 PM PDT 24
Finished Aug 07 06:05:27 PM PDT 24
Peak memory 206884 kb
Host smart-13dbd11b-1cd0-4a24-8b23-1f1151389449
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4101003065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.4101003065
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1091911719
Short name T1559
Test name
Test status
Simulation time 205377196 ps
CPU time 0.99 seconds
Started Aug 07 06:05:30 PM PDT 24
Finished Aug 07 06:05:31 PM PDT 24
Peak memory 206380 kb
Host smart-df0e6364-1fc8-4f68-a8d4-a55c25d53f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10919
11719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1091911719
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2425593455
Short name T544
Test name
Test status
Simulation time 2113863257 ps
CPU time 21.51 seconds
Started Aug 07 06:05:33 PM PDT 24
Finished Aug 07 06:05:54 PM PDT 24
Peak memory 215360 kb
Host smart-22d901c7-85e5-4806-a189-44047ca0b9c6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2425593455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2425593455
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.168768029
Short name T2403
Test name
Test status
Simulation time 207340837 ps
CPU time 0.89 seconds
Started Aug 07 06:05:26 PM PDT 24
Finished Aug 07 06:05:27 PM PDT 24
Peak memory 206972 kb
Host smart-0d1eaf25-f264-4e33-b28c-6fb4d7d38597
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=168768029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.168768029
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.701369430
Short name T1013
Test name
Test status
Simulation time 164416247 ps
CPU time 0.88 seconds
Started Aug 07 06:05:27 PM PDT 24
Finished Aug 07 06:05:28 PM PDT 24
Peak memory 207040 kb
Host smart-24a8e706-690f-4cfe-a75b-f6d1de9ef8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70136
9430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.701369430
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1371313696
Short name T142
Test name
Test status
Simulation time 194035419 ps
CPU time 0.89 seconds
Started Aug 07 06:05:25 PM PDT 24
Finished Aug 07 06:05:26 PM PDT 24
Peak memory 206980 kb
Host smart-d97cfb7d-08cf-48c8-a6a5-327fbd622938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13713
13696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1371313696
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.900880933
Short name T100
Test name
Test status
Simulation time 203072393 ps
CPU time 0.93 seconds
Started Aug 07 06:05:34 PM PDT 24
Finished Aug 07 06:05:35 PM PDT 24
Peak memory 206992 kb
Host smart-09588cac-1e70-4a77-9518-f912aa1a778e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90088
0933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.900880933
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1761685691
Short name T1839
Test name
Test status
Simulation time 172263683 ps
CPU time 0.89 seconds
Started Aug 07 06:05:34 PM PDT 24
Finished Aug 07 06:05:35 PM PDT 24
Peak memory 206992 kb
Host smart-7b0c6695-429e-4fab-8838-0f5e420a1b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17616
85691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1761685691
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3711427944
Short name T1886
Test name
Test status
Simulation time 173621148 ps
CPU time 0.9 seconds
Started Aug 07 06:05:28 PM PDT 24
Finished Aug 07 06:05:29 PM PDT 24
Peak memory 206956 kb
Host smart-1c6e7665-fe5b-49a6-bc54-a939730aa13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37114
27944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3711427944
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2415504207
Short name T2074
Test name
Test status
Simulation time 179230378 ps
CPU time 0.89 seconds
Started Aug 07 06:05:27 PM PDT 24
Finished Aug 07 06:05:28 PM PDT 24
Peak memory 206988 kb
Host smart-4e4c3736-86d6-43d6-a750-4e135230d442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24155
04207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2415504207
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.2953076258
Short name T2107
Test name
Test status
Simulation time 212300919 ps
CPU time 0.95 seconds
Started Aug 07 06:05:25 PM PDT 24
Finished Aug 07 06:05:26 PM PDT 24
Peak memory 206992 kb
Host smart-77b6663e-ba6c-43ed-a60c-4329c9c64feb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2953076258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.2953076258
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3719411
Short name T872
Test name
Test status
Simulation time 180990104 ps
CPU time 0.85 seconds
Started Aug 07 06:05:27 PM PDT 24
Finished Aug 07 06:05:28 PM PDT 24
Peak memory 206952 kb
Host smart-6b47df4f-fb74-4595-9e84-c7f19b621bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37194
11 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3719411
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.745101823
Short name T962
Test name
Test status
Simulation time 34919650 ps
CPU time 0.69 seconds
Started Aug 07 06:05:28 PM PDT 24
Finished Aug 07 06:05:29 PM PDT 24
Peak memory 206984 kb
Host smart-087dbeb5-186e-44bc-bfbe-895eea5d198b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74510
1823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.745101823
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1108163483
Short name T299
Test name
Test status
Simulation time 5948550089 ps
CPU time 15.19 seconds
Started Aug 07 06:05:28 PM PDT 24
Finished Aug 07 06:05:44 PM PDT 24
Peak memory 215568 kb
Host smart-6840d1c6-8787-4db8-ae06-d2fb353753ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11081
63483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1108163483
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.607357601
Short name T3110
Test name
Test status
Simulation time 194877419 ps
CPU time 0.84 seconds
Started Aug 07 06:05:31 PM PDT 24
Finished Aug 07 06:05:32 PM PDT 24
Peak memory 206988 kb
Host smart-f92e832e-2d1a-46b6-bc06-ddc980614f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60735
7601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.607357601
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.898088543
Short name T2801
Test name
Test status
Simulation time 223478783 ps
CPU time 1.02 seconds
Started Aug 07 06:05:35 PM PDT 24
Finished Aug 07 06:05:36 PM PDT 24
Peak memory 207016 kb
Host smart-a1d24767-8002-402b-97fa-79bf6c2c1b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89808
8543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.898088543
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.269324395
Short name T2012
Test name
Test status
Simulation time 197150272 ps
CPU time 0.97 seconds
Started Aug 07 06:05:35 PM PDT 24
Finished Aug 07 06:05:36 PM PDT 24
Peak memory 206904 kb
Host smart-516f1049-b0c8-45ee-9460-efe456c32900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26932
4395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.269324395
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.198354513
Short name T2852
Test name
Test status
Simulation time 195518268 ps
CPU time 0.89 seconds
Started Aug 07 06:05:34 PM PDT 24
Finished Aug 07 06:05:35 PM PDT 24
Peak memory 206860 kb
Host smart-97e84638-fb7e-45db-92b9-240594703ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19835
4513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.198354513
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.149874665
Short name T781
Test name
Test status
Simulation time 172894979 ps
CPU time 0.91 seconds
Started Aug 07 06:05:34 PM PDT 24
Finished Aug 07 06:05:35 PM PDT 24
Peak memory 207192 kb
Host smart-6820bc47-5ad2-4c26-b8cf-6eb3513949f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14987
4665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.149874665
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_rx_full.794940229
Short name T2397
Test name
Test status
Simulation time 329562705 ps
CPU time 1.17 seconds
Started Aug 07 06:05:33 PM PDT 24
Finished Aug 07 06:05:34 PM PDT 24
Peak memory 206972 kb
Host smart-df19c5ec-a57e-41bc-9f54-42618bc70a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79494
0229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.794940229
Directory /workspace/31.usbdev_rx_full/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.26760909
Short name T240
Test name
Test status
Simulation time 149387713 ps
CPU time 0.83 seconds
Started Aug 07 06:05:31 PM PDT 24
Finished Aug 07 06:05:32 PM PDT 24
Peak memory 206884 kb
Host smart-3d21b896-e3fd-4b41-a281-cac53981320e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26760
909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.26760909
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3559444147
Short name T1555
Test name
Test status
Simulation time 157309480 ps
CPU time 0.87 seconds
Started Aug 07 06:05:32 PM PDT 24
Finished Aug 07 06:05:33 PM PDT 24
Peak memory 207016 kb
Host smart-1dc5cded-10e4-4e34-bd5b-5abb248b51fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35594
44147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3559444147
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2575434382
Short name T1178
Test name
Test status
Simulation time 258799975 ps
CPU time 1.1 seconds
Started Aug 07 06:05:32 PM PDT 24
Finished Aug 07 06:05:34 PM PDT 24
Peak memory 206996 kb
Host smart-2d59166c-acf4-4cd9-9388-51b63924f825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25754
34382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2575434382
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.114716161
Short name T2607
Test name
Test status
Simulation time 2988372260 ps
CPU time 22.47 seconds
Started Aug 07 06:05:32 PM PDT 24
Finished Aug 07 06:05:55 PM PDT 24
Peak memory 207296 kb
Host smart-b30b7fe2-8f8e-42cb-b883-585a6270c6fd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=114716161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.114716161
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.4119116877
Short name T1736
Test name
Test status
Simulation time 200346221 ps
CPU time 0.96 seconds
Started Aug 07 06:05:31 PM PDT 24
Finished Aug 07 06:05:32 PM PDT 24
Peak memory 206964 kb
Host smart-a2b9a0ee-e678-4757-8882-ac49a0e2b536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41191
16877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.4119116877
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.4010938214
Short name T2121
Test name
Test status
Simulation time 204608095 ps
CPU time 0.9 seconds
Started Aug 07 06:05:34 PM PDT 24
Finished Aug 07 06:05:36 PM PDT 24
Peak memory 207040 kb
Host smart-3b361a2b-dd0d-4698-ba23-423d6ad20b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109
38214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.4010938214
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2618050226
Short name T1926
Test name
Test status
Simulation time 329520147 ps
CPU time 1.17 seconds
Started Aug 07 06:05:35 PM PDT 24
Finished Aug 07 06:05:37 PM PDT 24
Peak memory 206832 kb
Host smart-bb071913-f994-4781-9562-c69d18e30562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26180
50226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2618050226
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1725040496
Short name T2551
Test name
Test status
Simulation time 1874556462 ps
CPU time 20.26 seconds
Started Aug 07 06:05:33 PM PDT 24
Finished Aug 07 06:05:53 PM PDT 24
Peak memory 223484 kb
Host smart-0746e51d-7f3a-4048-83e1-d7d4144a4473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17250
40496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1725040496
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.1353862192
Short name T651
Test name
Test status
Simulation time 4364266742 ps
CPU time 28.88 seconds
Started Aug 07 06:05:16 PM PDT 24
Finished Aug 07 06:05:45 PM PDT 24
Peak memory 207304 kb
Host smart-cc2d995e-536e-4360-8674-ff873012db54
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353862192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.1353862192
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.1216030053
Short name T2789
Test name
Test status
Simulation time 62634495 ps
CPU time 0.74 seconds
Started Aug 07 06:06:06 PM PDT 24
Finished Aug 07 06:06:07 PM PDT 24
Peak memory 207004 kb
Host smart-03073045-4585-432f-9ae1-2361e4585574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1216030053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.1216030053
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.1751841440
Short name T1190
Test name
Test status
Simulation time 6967362736 ps
CPU time 8.68 seconds
Started Aug 07 06:05:35 PM PDT 24
Finished Aug 07 06:05:44 PM PDT 24
Peak memory 215488 kb
Host smart-885682a7-90d5-4891-81a4-ee629f73ae47
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751841440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.1751841440
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3039616830
Short name T2210
Test name
Test status
Simulation time 13373637946 ps
CPU time 18.26 seconds
Started Aug 07 06:05:33 PM PDT 24
Finished Aug 07 06:05:52 PM PDT 24
Peak memory 215476 kb
Host smart-08f25ea7-c4c5-41c2-9023-ea988a3019ad
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039616830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3039616830
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.2237441482
Short name T1172
Test name
Test status
Simulation time 23779429440 ps
CPU time 26.23 seconds
Started Aug 07 06:05:42 PM PDT 24
Finished Aug 07 06:06:09 PM PDT 24
Peak memory 215364 kb
Host smart-bc188ea9-3a84-4f1e-90b8-f2f51e9c2cd2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237441482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.2237441482
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.4293318783
Short name T626
Test name
Test status
Simulation time 148918281 ps
CPU time 0.86 seconds
Started Aug 07 06:05:37 PM PDT 24
Finished Aug 07 06:05:38 PM PDT 24
Peak memory 206992 kb
Host smart-3c507551-239e-4def-a07c-a50d198567e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42933
18783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.4293318783
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2714270467
Short name T1992
Test name
Test status
Simulation time 161982172 ps
CPU time 0.85 seconds
Started Aug 07 06:05:37 PM PDT 24
Finished Aug 07 06:05:38 PM PDT 24
Peak memory 206932 kb
Host smart-9549a5b7-44cb-4381-a8f6-f3af3c9b1fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27142
70467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2714270467
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.2082022049
Short name T2610
Test name
Test status
Simulation time 604706314 ps
CPU time 1.91 seconds
Started Aug 07 06:05:40 PM PDT 24
Finished Aug 07 06:05:42 PM PDT 24
Peak memory 207036 kb
Host smart-2f12ea63-eb78-449c-a655-9bd0f2352f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20820
22049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.2082022049
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3662586143
Short name T1536
Test name
Test status
Simulation time 389106205 ps
CPU time 1.24 seconds
Started Aug 07 06:05:44 PM PDT 24
Finished Aug 07 06:05:45 PM PDT 24
Peak memory 206960 kb
Host smart-f3c1d84a-56a6-44e2-b7eb-3773e7f85aac
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3662586143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3662586143
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.2652757905
Short name T2018
Test name
Test status
Simulation time 37865521305 ps
CPU time 53.2 seconds
Started Aug 07 06:05:38 PM PDT 24
Finished Aug 07 06:06:32 PM PDT 24
Peak memory 207376 kb
Host smart-57a8a3fb-5659-407a-8403-8b746f12eeac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26527
57905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.2652757905
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.2708802368
Short name T2454
Test name
Test status
Simulation time 4341240316 ps
CPU time 39.26 seconds
Started Aug 07 06:05:39 PM PDT 24
Finished Aug 07 06:06:18 PM PDT 24
Peak memory 207292 kb
Host smart-410bb247-74f0-4c34-b66b-6ea110ce6b56
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708802368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.2708802368
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.346421098
Short name T2866
Test name
Test status
Simulation time 861938805 ps
CPU time 1.79 seconds
Started Aug 07 06:05:39 PM PDT 24
Finished Aug 07 06:05:41 PM PDT 24
Peak memory 206984 kb
Host smart-16086208-ed75-4720-95e7-f52d8c308ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34642
1098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.346421098
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.127717640
Short name T1534
Test name
Test status
Simulation time 148582273 ps
CPU time 0.83 seconds
Started Aug 07 06:05:40 PM PDT 24
Finished Aug 07 06:05:41 PM PDT 24
Peak memory 206984 kb
Host smart-ce915e26-e113-4e67-aabd-a6220f029f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12771
7640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.127717640
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.1903932693
Short name T990
Test name
Test status
Simulation time 111410099 ps
CPU time 0.76 seconds
Started Aug 07 06:05:37 PM PDT 24
Finished Aug 07 06:05:38 PM PDT 24
Peak memory 206952 kb
Host smart-26bc662e-8164-4e6c-8941-7f978d7c59d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19039
32693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1903932693
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1094567203
Short name T901
Test name
Test status
Simulation time 916087999 ps
CPU time 2.4 seconds
Started Aug 07 06:05:46 PM PDT 24
Finished Aug 07 06:05:49 PM PDT 24
Peak memory 207280 kb
Host smart-8a5a670b-f022-4197-9a58-8fc3565c566c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10945
67203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1094567203
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_types.2048571480
Short name T469
Test name
Test status
Simulation time 198811798 ps
CPU time 0.91 seconds
Started Aug 07 06:05:48 PM PDT 24
Finished Aug 07 06:05:49 PM PDT 24
Peak memory 206968 kb
Host smart-3bfa44e1-9d01-4a1f-a3a0-325cc715800f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2048571480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.2048571480
Directory /workspace/32.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3817644762
Short name T2567
Test name
Test status
Simulation time 190556534 ps
CPU time 1.44 seconds
Started Aug 07 06:05:45 PM PDT 24
Finished Aug 07 06:05:47 PM PDT 24
Peak memory 207172 kb
Host smart-80c67540-dc18-49a7-891e-d720c1831b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176
44762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3817644762
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.805171042
Short name T904
Test name
Test status
Simulation time 236200509 ps
CPU time 1.1 seconds
Started Aug 07 06:05:51 PM PDT 24
Finished Aug 07 06:05:53 PM PDT 24
Peak memory 215376 kb
Host smart-0ddcb639-d29b-4224-9a6f-f53abf189bd9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=805171042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.805171042
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2189779342
Short name T1615
Test name
Test status
Simulation time 197748239 ps
CPU time 0.86 seconds
Started Aug 07 06:05:49 PM PDT 24
Finished Aug 07 06:05:49 PM PDT 24
Peak memory 206948 kb
Host smart-853b51fa-4cdc-4fad-8daa-2744d681220e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21897
79342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2189779342
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2679555599
Short name T2680
Test name
Test status
Simulation time 238846908 ps
CPU time 0.99 seconds
Started Aug 07 06:05:48 PM PDT 24
Finished Aug 07 06:05:49 PM PDT 24
Peak memory 207016 kb
Host smart-6911fc04-61ed-462e-9f3c-65658dd7cb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26795
55599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2679555599
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.3326718244
Short name T1085
Test name
Test status
Simulation time 5086806001 ps
CPU time 146.6 seconds
Started Aug 07 06:05:49 PM PDT 24
Finished Aug 07 06:08:16 PM PDT 24
Peak memory 215496 kb
Host smart-0f2bb2da-95c7-4904-8c19-645cc7b14721
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3326718244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.3326718244
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.1525956414
Short name T3017
Test name
Test status
Simulation time 11106584303 ps
CPU time 82.99 seconds
Started Aug 07 06:05:51 PM PDT 24
Finished Aug 07 06:07:14 PM PDT 24
Peak memory 207260 kb
Host smart-0bbde926-89b7-4a12-8452-2f565313cce7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1525956414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.1525956414
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1049765820
Short name T619
Test name
Test status
Simulation time 249097266 ps
CPU time 0.95 seconds
Started Aug 07 06:05:45 PM PDT 24
Finished Aug 07 06:05:46 PM PDT 24
Peak memory 207028 kb
Host smart-81208c8a-e399-4621-883b-4f927c1021f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10497
65820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1049765820
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2630525772
Short name T2540
Test name
Test status
Simulation time 5606431840 ps
CPU time 7.69 seconds
Started Aug 07 06:05:48 PM PDT 24
Finished Aug 07 06:05:56 PM PDT 24
Peak memory 215484 kb
Host smart-8793c072-0abf-42a8-b3fb-38ea21486183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26305
25772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2630525772
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3105685750
Short name T772
Test name
Test status
Simulation time 9726055616 ps
CPU time 13.84 seconds
Started Aug 07 06:05:48 PM PDT 24
Finished Aug 07 06:06:02 PM PDT 24
Peak memory 207284 kb
Host smart-8fd06307-490a-496d-8df2-60aa7c3b9803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31056
85750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3105685750
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.698046129
Short name T1575
Test name
Test status
Simulation time 3430081198 ps
CPU time 99.25 seconds
Started Aug 07 06:05:51 PM PDT 24
Finished Aug 07 06:07:30 PM PDT 24
Peak memory 217856 kb
Host smart-92bb1052-6fce-4777-9f8c-d5ae2116f6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69804
6129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.698046129
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3302589135
Short name T994
Test name
Test status
Simulation time 2940417138 ps
CPU time 31.88 seconds
Started Aug 07 06:05:49 PM PDT 24
Finished Aug 07 06:06:21 PM PDT 24
Peak memory 217108 kb
Host smart-e8fb99ef-b8f9-4ee9-a360-e3c0ee44409c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3302589135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3302589135
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3663408242
Short name T1031
Test name
Test status
Simulation time 268632358 ps
CPU time 1.09 seconds
Started Aug 07 06:05:51 PM PDT 24
Finished Aug 07 06:05:53 PM PDT 24
Peak memory 206980 kb
Host smart-979820fb-e694-47f4-a4fe-fa53346c0531
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3663408242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3663408242
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3996383899
Short name T1282
Test name
Test status
Simulation time 194003200 ps
CPU time 0.92 seconds
Started Aug 07 06:05:52 PM PDT 24
Finished Aug 07 06:05:53 PM PDT 24
Peak memory 206940 kb
Host smart-69897506-e426-4c8b-8883-cf16015a5a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39963
83899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3996383899
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.2737880866
Short name T2499
Test name
Test status
Simulation time 4122044367 ps
CPU time 117.78 seconds
Started Aug 07 06:05:50 PM PDT 24
Finished Aug 07 06:07:48 PM PDT 24
Peak memory 216912 kb
Host smart-91e84779-915b-4ca8-9b1d-70f55f81856d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2737880866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.2737880866
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2700258710
Short name T2630
Test name
Test status
Simulation time 156206789 ps
CPU time 0.89 seconds
Started Aug 07 06:05:53 PM PDT 24
Finished Aug 07 06:05:54 PM PDT 24
Peak memory 206940 kb
Host smart-a8558c16-85a9-44f4-afa7-2e89bd51863d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2700258710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2700258710
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1212731306
Short name T1292
Test name
Test status
Simulation time 181408548 ps
CPU time 0.86 seconds
Started Aug 07 06:05:55 PM PDT 24
Finished Aug 07 06:05:56 PM PDT 24
Peak memory 207216 kb
Host smart-931a8ec6-3538-48bb-b97f-2ac269098486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12127
31306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1212731306
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2238834290
Short name T2486
Test name
Test status
Simulation time 234031687 ps
CPU time 1.01 seconds
Started Aug 07 06:05:53 PM PDT 24
Finished Aug 07 06:05:54 PM PDT 24
Peak memory 206924 kb
Host smart-830f2970-de0a-4ade-a07b-c0b98c358328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22388
34290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2238834290
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1845591795
Short name T1113
Test name
Test status
Simulation time 168400691 ps
CPU time 0.93 seconds
Started Aug 07 06:05:50 PM PDT 24
Finished Aug 07 06:05:52 PM PDT 24
Peak memory 206904 kb
Host smart-6495053f-292d-4acc-adff-7eb029555350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18455
91795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1845591795
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.212664553
Short name T658
Test name
Test status
Simulation time 210717568 ps
CPU time 0.94 seconds
Started Aug 07 06:05:58 PM PDT 24
Finished Aug 07 06:05:59 PM PDT 24
Peak memory 206956 kb
Host smart-1de079be-2bfd-4969-9d43-6783f8c87f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21266
4553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.212664553
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3171962348
Short name T1271
Test name
Test status
Simulation time 179316245 ps
CPU time 0.87 seconds
Started Aug 07 06:06:00 PM PDT 24
Finished Aug 07 06:06:01 PM PDT 24
Peak memory 206956 kb
Host smart-58c09034-e67a-4244-b712-8963168468f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31719
62348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3171962348
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2402736158
Short name T1504
Test name
Test status
Simulation time 152357380 ps
CPU time 0.82 seconds
Started Aug 07 06:05:58 PM PDT 24
Finished Aug 07 06:05:59 PM PDT 24
Peak memory 207012 kb
Host smart-1d0682ff-89c4-4253-90e2-d4d30575ae47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24027
36158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2402736158
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.3580835663
Short name T2336
Test name
Test status
Simulation time 207753693 ps
CPU time 0.98 seconds
Started Aug 07 06:06:59 PM PDT 24
Finished Aug 07 06:07:00 PM PDT 24
Peak memory 206984 kb
Host smart-0e098f18-797c-41fd-978b-cca83ab9938f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3580835663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.3580835663
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1636854241
Short name T2160
Test name
Test status
Simulation time 152442636 ps
CPU time 0.88 seconds
Started Aug 07 06:05:57 PM PDT 24
Finished Aug 07 06:05:58 PM PDT 24
Peak memory 206984 kb
Host smart-73c85260-9088-41ae-9ee0-c48f69b54352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16368
54241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1636854241
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1776102345
Short name T2457
Test name
Test status
Simulation time 28297067 ps
CPU time 0.67 seconds
Started Aug 07 06:05:55 PM PDT 24
Finished Aug 07 06:05:56 PM PDT 24
Peak memory 206944 kb
Host smart-7e2f9c5d-78b0-4a87-9384-97a9f0ecdcfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17761
02345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1776102345
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1002050403
Short name T955
Test name
Test status
Simulation time 8234784727 ps
CPU time 22.02 seconds
Started Aug 07 06:05:59 PM PDT 24
Finished Aug 07 06:06:21 PM PDT 24
Peak memory 215440 kb
Host smart-9cabe767-fc66-43e0-90cd-c1fe1c935a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10020
50403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1002050403
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.939320247
Short name T2254
Test name
Test status
Simulation time 191767815 ps
CPU time 1.01 seconds
Started Aug 07 06:05:59 PM PDT 24
Finished Aug 07 06:06:00 PM PDT 24
Peak memory 207004 kb
Host smart-f5a0d80a-0d3b-47e7-beb1-39e60e2546a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93932
0247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.939320247
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2008809597
Short name T3097
Test name
Test status
Simulation time 237495974 ps
CPU time 1.02 seconds
Started Aug 07 06:06:00 PM PDT 24
Finished Aug 07 06:06:02 PM PDT 24
Peak memory 206976 kb
Host smart-aae4f930-e623-42b9-b6ae-a506bae0450d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20088
09597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2008809597
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2988150925
Short name T1222
Test name
Test status
Simulation time 163965691 ps
CPU time 0.95 seconds
Started Aug 07 06:06:00 PM PDT 24
Finished Aug 07 06:06:01 PM PDT 24
Peak memory 206980 kb
Host smart-6b878a71-9659-4618-8232-cd802e8b5b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29881
50925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2988150925
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.3915410450
Short name T516
Test name
Test status
Simulation time 197098742 ps
CPU time 0.97 seconds
Started Aug 07 06:06:02 PM PDT 24
Finished Aug 07 06:06:03 PM PDT 24
Peak memory 207004 kb
Host smart-c058506c-7fdf-4e13-86b1-e38bd970cae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39154
10450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.3915410450
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2396203830
Short name T2536
Test name
Test status
Simulation time 140345909 ps
CPU time 0.79 seconds
Started Aug 07 06:06:02 PM PDT 24
Finished Aug 07 06:06:03 PM PDT 24
Peak memory 206928 kb
Host smart-b215f4be-97ab-4725-a8be-a9f06e97ffe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23962
03830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2396203830
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_rx_full.1574543127
Short name T2720
Test name
Test status
Simulation time 305419154 ps
CPU time 1.15 seconds
Started Aug 07 06:06:03 PM PDT 24
Finished Aug 07 06:06:05 PM PDT 24
Peak memory 206992 kb
Host smart-5dc5f073-deec-4cde-a3a1-5b9c2b26494a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15745
43127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.1574543127
Directory /workspace/32.usbdev_rx_full/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2902260815
Short name T2864
Test name
Test status
Simulation time 149536673 ps
CPU time 0.82 seconds
Started Aug 07 06:06:05 PM PDT 24
Finished Aug 07 06:06:06 PM PDT 24
Peak memory 206952 kb
Host smart-d503b34d-5df5-4bc3-a06f-ef5cd69e0455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29022
60815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2902260815
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.4285765522
Short name T1492
Test name
Test status
Simulation time 149580014 ps
CPU time 0.88 seconds
Started Aug 07 06:07:00 PM PDT 24
Finished Aug 07 06:07:01 PM PDT 24
Peak memory 206924 kb
Host smart-be4b8846-d385-4171-9e01-f1f5c71d58fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42857
65522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.4285765522
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2445693155
Short name T597
Test name
Test status
Simulation time 233759222 ps
CPU time 1.01 seconds
Started Aug 07 06:06:03 PM PDT 24
Finished Aug 07 06:06:04 PM PDT 24
Peak memory 206984 kb
Host smart-d5f58bcd-02d6-4cfa-a9ec-fbf722729c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24456
93155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2445693155
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2856160386
Short name T169
Test name
Test status
Simulation time 2889588889 ps
CPU time 30.7 seconds
Started Aug 07 06:06:05 PM PDT 24
Finished Aug 07 06:06:36 PM PDT 24
Peak memory 217548 kb
Host smart-51c7f8fb-b8d0-45fc-9c4e-c68d7872bc04
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2856160386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2856160386
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.769704880
Short name T1685
Test name
Test status
Simulation time 177007839 ps
CPU time 0.89 seconds
Started Aug 07 06:06:04 PM PDT 24
Finished Aug 07 06:06:05 PM PDT 24
Peak memory 206968 kb
Host smart-486c8b94-5b58-4d82-87d8-2413968e13cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76970
4880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.769704880
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3793092775
Short name T2491
Test name
Test status
Simulation time 210979881 ps
CPU time 0.99 seconds
Started Aug 07 06:06:02 PM PDT 24
Finished Aug 07 06:06:03 PM PDT 24
Peak memory 207012 kb
Host smart-76f9b55b-820f-4227-8982-8097bcb1d11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37930
92775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3793092775
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.378421083
Short name T1578
Test name
Test status
Simulation time 1283870411 ps
CPU time 3.34 seconds
Started Aug 07 06:06:05 PM PDT 24
Finished Aug 07 06:06:08 PM PDT 24
Peak memory 207148 kb
Host smart-e708fa2f-9efc-480f-8fdb-27bc5a495fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37842
1083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.378421083
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.1374747605
Short name T1636
Test name
Test status
Simulation time 3786633181 ps
CPU time 28.78 seconds
Started Aug 07 06:06:04 PM PDT 24
Finished Aug 07 06:06:33 PM PDT 24
Peak memory 217156 kb
Host smart-67e6231b-287a-4d9d-b159-31cf1cbe35d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13747
47605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.1374747605
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.3221690324
Short name T55
Test name
Test status
Simulation time 7036074393 ps
CPU time 44.34 seconds
Started Aug 07 06:05:38 PM PDT 24
Finished Aug 07 06:06:23 PM PDT 24
Peak memory 207348 kb
Host smart-5c1f060f-0001-4b11-bff5-5b7691b71159
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221690324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.3221690324
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.1222599803
Short name T3078
Test name
Test status
Simulation time 41678888 ps
CPU time 0.7 seconds
Started Aug 07 06:06:32 PM PDT 24
Finished Aug 07 06:06:33 PM PDT 24
Peak memory 207036 kb
Host smart-ef32798e-7b25-44c8-a26d-516566789f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1222599803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.1222599803
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.3131981798
Short name T2537
Test name
Test status
Simulation time 6038753828 ps
CPU time 9.18 seconds
Started Aug 07 06:06:04 PM PDT 24
Finished Aug 07 06:06:14 PM PDT 24
Peak memory 215436 kb
Host smart-aa63934c-ed04-4450-8f16-d8d11aa5ebba
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131981798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.3131981798
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3950826939
Short name T2823
Test name
Test status
Simulation time 14995636219 ps
CPU time 15.62 seconds
Started Aug 07 06:06:02 PM PDT 24
Finished Aug 07 06:06:18 PM PDT 24
Peak memory 215428 kb
Host smart-bb4a5519-aa6d-4ee3-a614-7222857d089c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950826939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3950826939
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2817772197
Short name T943
Test name
Test status
Simulation time 29565896120 ps
CPU time 34.31 seconds
Started Aug 07 06:06:04 PM PDT 24
Finished Aug 07 06:06:39 PM PDT 24
Peak memory 207260 kb
Host smart-979f3115-5aab-49de-aa61-f145099fb654
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817772197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.2817772197
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3305019485
Short name T1389
Test name
Test status
Simulation time 190692363 ps
CPU time 0.95 seconds
Started Aug 07 06:06:13 PM PDT 24
Finished Aug 07 06:06:14 PM PDT 24
Peak memory 207024 kb
Host smart-96b2d547-f231-4a36-bd39-f4a5d452e710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33050
19485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3305019485
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.229731963
Short name T754
Test name
Test status
Simulation time 159339845 ps
CPU time 0.84 seconds
Started Aug 07 06:06:11 PM PDT 24
Finished Aug 07 06:06:12 PM PDT 24
Peak memory 206952 kb
Host smart-29479250-947c-48e9-a573-966e0f79ae69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22973
1963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.229731963
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.3426968803
Short name T768
Test name
Test status
Simulation time 452028290 ps
CPU time 1.58 seconds
Started Aug 07 06:06:10 PM PDT 24
Finished Aug 07 06:06:11 PM PDT 24
Peak memory 206980 kb
Host smart-0322b9ed-c891-45f0-a59c-436a1dce54e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34269
68803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.3426968803
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.391386342
Short name T1276
Test name
Test status
Simulation time 889389808 ps
CPU time 2.36 seconds
Started Aug 07 06:06:11 PM PDT 24
Finished Aug 07 06:06:13 PM PDT 24
Peak memory 207164 kb
Host smart-8991228c-c678-4497-ba3b-e03060e4ae49
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=391386342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.391386342
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.702395638
Short name T2983
Test name
Test status
Simulation time 289926244 ps
CPU time 4.81 seconds
Started Aug 07 06:06:14 PM PDT 24
Finished Aug 07 06:06:19 PM PDT 24
Peak memory 207380 kb
Host smart-0ad369e7-14a8-49e9-be63-84b3a930a905
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702395638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.702395638
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.387928822
Short name T1855
Test name
Test status
Simulation time 686304386 ps
CPU time 1.77 seconds
Started Aug 07 06:06:12 PM PDT 24
Finished Aug 07 06:06:14 PM PDT 24
Peak memory 206948 kb
Host smart-4bf577cd-125c-4f02-bbd2-642966642062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38792
8822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.387928822
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2127419840
Short name T1932
Test name
Test status
Simulation time 146874746 ps
CPU time 0.87 seconds
Started Aug 07 06:06:09 PM PDT 24
Finished Aug 07 06:06:10 PM PDT 24
Peak memory 206884 kb
Host smart-e1742856-3e3a-45ec-89b5-f68c4682703b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21274
19840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2127419840
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.3167192972
Short name T1094
Test name
Test status
Simulation time 32656808 ps
CPU time 0.69 seconds
Started Aug 07 06:06:12 PM PDT 24
Finished Aug 07 06:06:13 PM PDT 24
Peak memory 206916 kb
Host smart-637d7a6a-a912-41eb-a5d5-c7687a6b051b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31671
92972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3167192972
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.747072126
Short name T926
Test name
Test status
Simulation time 917962928 ps
CPU time 2.25 seconds
Started Aug 07 06:06:10 PM PDT 24
Finished Aug 07 06:06:13 PM PDT 24
Peak memory 207144 kb
Host smart-d39f6d49-3db4-4df7-b8c7-c1b1deeae5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74707
2126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.747072126
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3629834040
Short name T1562
Test name
Test status
Simulation time 382222575 ps
CPU time 2.89 seconds
Started Aug 07 06:06:11 PM PDT 24
Finished Aug 07 06:06:14 PM PDT 24
Peak memory 207128 kb
Host smart-a4e4e226-014a-422f-b812-506b84cc49a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36298
34040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3629834040
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2367788841
Short name T2309
Test name
Test status
Simulation time 243231598 ps
CPU time 1.22 seconds
Started Aug 07 06:06:12 PM PDT 24
Finished Aug 07 06:06:13 PM PDT 24
Peak memory 215244 kb
Host smart-8e3b9ac3-a39a-45e0-8887-983524719bb5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2367788841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2367788841
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.320223050
Short name T1976
Test name
Test status
Simulation time 147833501 ps
CPU time 0.86 seconds
Started Aug 07 06:06:19 PM PDT 24
Finished Aug 07 06:06:20 PM PDT 24
Peak memory 206952 kb
Host smart-816aac75-d9e3-45f0-a410-64d951604498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32022
3050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.320223050
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2336004006
Short name T1701
Test name
Test status
Simulation time 244063159 ps
CPU time 1.01 seconds
Started Aug 07 06:06:14 PM PDT 24
Finished Aug 07 06:06:15 PM PDT 24
Peak memory 207016 kb
Host smart-84796777-60dd-4a4c-8cb8-6697bbd7db13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23360
04006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2336004006
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.905968559
Short name T2479
Test name
Test status
Simulation time 4407117671 ps
CPU time 136.79 seconds
Started Aug 07 06:06:13 PM PDT 24
Finished Aug 07 06:08:29 PM PDT 24
Peak memory 215484 kb
Host smart-59f3aa5e-780d-4656-a2ba-77b26f187d49
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=905968559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.905968559
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2389067294
Short name T2670
Test name
Test status
Simulation time 9644435671 ps
CPU time 120.9 seconds
Started Aug 07 06:07:01 PM PDT 24
Finished Aug 07 06:09:02 PM PDT 24
Peak memory 207296 kb
Host smart-32f75d7d-794f-4128-9703-34069886ae5e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2389067294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2389067294
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3887994972
Short name T2038
Test name
Test status
Simulation time 190615097 ps
CPU time 0.94 seconds
Started Aug 07 06:06:18 PM PDT 24
Finished Aug 07 06:06:19 PM PDT 24
Peak memory 206992 kb
Host smart-2284d06b-de30-49a6-934b-5c30401753b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38879
94972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3887994972
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.4050824796
Short name T36
Test name
Test status
Simulation time 12506054196 ps
CPU time 17.36 seconds
Started Aug 07 06:06:18 PM PDT 24
Finished Aug 07 06:06:35 PM PDT 24
Peak memory 207252 kb
Host smart-882241f7-0c54-4c9e-8361-dca3a1e58896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40508
24796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.4050824796
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3852764335
Short name T800
Test name
Test status
Simulation time 11474394654 ps
CPU time 15.51 seconds
Started Aug 07 06:06:19 PM PDT 24
Finished Aug 07 06:06:34 PM PDT 24
Peak memory 207292 kb
Host smart-a52c8cdf-4876-4f30-aa90-3f89935d73ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38527
64335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3852764335
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.3922879066
Short name T1928
Test name
Test status
Simulation time 4350005836 ps
CPU time 40.18 seconds
Started Aug 07 06:06:17 PM PDT 24
Finished Aug 07 06:06:57 PM PDT 24
Peak memory 218068 kb
Host smart-e676acba-35c0-4525-b7f1-368f7a8d1897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39228
79066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.3922879066
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.733187116
Short name T562
Test name
Test status
Simulation time 3257155462 ps
CPU time 25.59 seconds
Started Aug 07 06:06:19 PM PDT 24
Finished Aug 07 06:06:45 PM PDT 24
Peak memory 215448 kb
Host smart-93ea9869-b53d-4b60-97db-c7cda113b0e2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=733187116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.733187116
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.3399920446
Short name T728
Test name
Test status
Simulation time 247703529 ps
CPU time 0.96 seconds
Started Aug 07 06:06:15 PM PDT 24
Finished Aug 07 06:06:16 PM PDT 24
Peak memory 206952 kb
Host smart-068823aa-eafd-4e4a-b102-3e1b0310c7ee
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3399920446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.3399920446
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3807568982
Short name T1267
Test name
Test status
Simulation time 191872125 ps
CPU time 1 seconds
Started Aug 07 06:06:17 PM PDT 24
Finished Aug 07 06:06:18 PM PDT 24
Peak memory 206976 kb
Host smart-798bdd55-7060-4137-ba54-01c60eae9bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38075
68982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3807568982
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.3230430925
Short name T1890
Test name
Test status
Simulation time 2455193452 ps
CPU time 70.26 seconds
Started Aug 07 06:06:15 PM PDT 24
Finished Aug 07 06:07:25 PM PDT 24
Peak memory 216880 kb
Host smart-5bf3e429-1cbc-4611-9c2d-2d59b109057a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3230430925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3230430925
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.857403530
Short name T893
Test name
Test status
Simulation time 155187407 ps
CPU time 0.87 seconds
Started Aug 07 06:06:22 PM PDT 24
Finished Aug 07 06:06:23 PM PDT 24
Peak memory 207000 kb
Host smart-28721b8f-c1c1-485e-a84e-6adc1da917a3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=857403530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.857403530
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2875976247
Short name T921
Test name
Test status
Simulation time 143019507 ps
CPU time 0.8 seconds
Started Aug 07 06:07:00 PM PDT 24
Finished Aug 07 06:07:01 PM PDT 24
Peak memory 206896 kb
Host smart-f03cff19-5342-4fba-8cd9-930b9ef5c73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28759
76247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2875976247
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2382087032
Short name T132
Test name
Test status
Simulation time 165189619 ps
CPU time 0.89 seconds
Started Aug 07 06:06:21 PM PDT 24
Finished Aug 07 06:06:22 PM PDT 24
Peak memory 206996 kb
Host smart-9be3d125-7abb-4c62-9192-3c3f38d77664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23820
87032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2382087032
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.1369343807
Short name T1523
Test name
Test status
Simulation time 192380335 ps
CPU time 0.9 seconds
Started Aug 07 06:06:21 PM PDT 24
Finished Aug 07 06:06:22 PM PDT 24
Peak memory 206988 kb
Host smart-18b03673-9a1c-421f-8877-3cd8ceb54ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13693
43807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.1369343807
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.915524200
Short name T3103
Test name
Test status
Simulation time 160953194 ps
CPU time 0.9 seconds
Started Aug 07 06:06:22 PM PDT 24
Finished Aug 07 06:06:23 PM PDT 24
Peak memory 206988 kb
Host smart-a7a801b7-16fd-4dc9-acb6-1a01030f21fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91552
4200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.915524200
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3352086846
Short name T2500
Test name
Test status
Simulation time 161479941 ps
CPU time 0.83 seconds
Started Aug 07 06:06:22 PM PDT 24
Finished Aug 07 06:06:23 PM PDT 24
Peak memory 207000 kb
Host smart-fe7bc1b9-7850-43a4-b04b-10ad8479ca3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33520
86846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3352086846
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2401572283
Short name T2353
Test name
Test status
Simulation time 149132919 ps
CPU time 0.86 seconds
Started Aug 07 06:06:24 PM PDT 24
Finished Aug 07 06:06:24 PM PDT 24
Peak memory 207004 kb
Host smart-a21a71fc-db79-4852-809a-610ece638f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24015
72283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2401572283
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3510476975
Short name T2556
Test name
Test status
Simulation time 243636818 ps
CPU time 1.04 seconds
Started Aug 07 06:06:20 PM PDT 24
Finished Aug 07 06:06:21 PM PDT 24
Peak memory 207008 kb
Host smart-e440f5cc-8033-413d-8480-0e2d3ef481a0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3510476975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3510476975
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3656936501
Short name T911
Test name
Test status
Simulation time 147898204 ps
CPU time 0.84 seconds
Started Aug 07 06:06:22 PM PDT 24
Finished Aug 07 06:06:23 PM PDT 24
Peak memory 206828 kb
Host smart-1f5f4cd2-9bbc-4cb3-a39f-79e1e0bfc3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36569
36501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3656936501
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1231444599
Short name T2027
Test name
Test status
Simulation time 56830596 ps
CPU time 0.7 seconds
Started Aug 07 06:06:24 PM PDT 24
Finished Aug 07 06:06:25 PM PDT 24
Peak memory 207004 kb
Host smart-674f6b02-a903-4e4b-bcbc-eee50ea14dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12314
44599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1231444599
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2404125372
Short name T265
Test name
Test status
Simulation time 16337172408 ps
CPU time 45.27 seconds
Started Aug 07 06:06:26 PM PDT 24
Finished Aug 07 06:07:11 PM PDT 24
Peak memory 223660 kb
Host smart-5fdb8396-4abd-4c8a-8f90-ffe3fa1d591d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24041
25372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2404125372
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1494881624
Short name T3000
Test name
Test status
Simulation time 177915473 ps
CPU time 0.87 seconds
Started Aug 07 06:06:29 PM PDT 24
Finished Aug 07 06:06:30 PM PDT 24
Peak memory 206988 kb
Host smart-6670c611-5d8f-4861-ae6d-e8fd675b17da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14948
81624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1494881624
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.697846271
Short name T1177
Test name
Test status
Simulation time 183741242 ps
CPU time 0.89 seconds
Started Aug 07 06:06:30 PM PDT 24
Finished Aug 07 06:06:31 PM PDT 24
Peak memory 206952 kb
Host smart-9e684d68-ca10-4ed3-922f-e90e16217fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69784
6271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.697846271
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.1865205549
Short name T1658
Test name
Test status
Simulation time 195486356 ps
CPU time 0.87 seconds
Started Aug 07 06:06:28 PM PDT 24
Finished Aug 07 06:06:29 PM PDT 24
Peak memory 207036 kb
Host smart-10a9cde5-3f8f-4b74-991a-086f54abda10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18652
05549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.1865205549
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.2397660714
Short name T1702
Test name
Test status
Simulation time 182264322 ps
CPU time 0.96 seconds
Started Aug 07 06:06:28 PM PDT 24
Finished Aug 07 06:06:29 PM PDT 24
Peak memory 207004 kb
Host smart-5d570995-c4e9-4eb5-ba05-da0cd9d0c162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23976
60714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.2397660714
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1261889686
Short name T1535
Test name
Test status
Simulation time 138524321 ps
CPU time 0.85 seconds
Started Aug 07 06:06:27 PM PDT 24
Finished Aug 07 06:06:28 PM PDT 24
Peak memory 206940 kb
Host smart-1052a764-57a2-4bf2-97a7-5d6f303b5b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12618
89686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1261889686
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_rx_full.2459822665
Short name T1606
Test name
Test status
Simulation time 368853022 ps
CPU time 1.35 seconds
Started Aug 07 06:06:30 PM PDT 24
Finished Aug 07 06:06:32 PM PDT 24
Peak memory 206972 kb
Host smart-71fc282e-bedd-4406-8bec-ed3f9033dba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24598
22665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.2459822665
Directory /workspace/33.usbdev_rx_full/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2614810666
Short name T1906
Test name
Test status
Simulation time 157764171 ps
CPU time 0.83 seconds
Started Aug 07 06:06:26 PM PDT 24
Finished Aug 07 06:06:27 PM PDT 24
Peak memory 206948 kb
Host smart-82dc41f0-1cf8-4a36-8bff-44769559dee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26148
10666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2614810666
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2822862936
Short name T953
Test name
Test status
Simulation time 170877347 ps
CPU time 0.87 seconds
Started Aug 07 06:06:28 PM PDT 24
Finished Aug 07 06:06:29 PM PDT 24
Peak memory 206992 kb
Host smart-68e2d68b-eba7-4df1-906b-facab2ff3e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28228
62936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2822862936
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1006207607
Short name T1466
Test name
Test status
Simulation time 206569370 ps
CPU time 1 seconds
Started Aug 07 06:06:26 PM PDT 24
Finished Aug 07 06:06:27 PM PDT 24
Peak memory 206968 kb
Host smart-34e56834-55c2-41eb-998e-4c36122f611d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10062
07607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1006207607
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1804001871
Short name T1363
Test name
Test status
Simulation time 1975261398 ps
CPU time 56.7 seconds
Started Aug 07 06:06:26 PM PDT 24
Finished Aug 07 06:07:23 PM PDT 24
Peak memory 223504 kb
Host smart-3fba6133-c121-47f9-bee3-8fc4c3138bc0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1804001871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1804001871
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.177960806
Short name T2127
Test name
Test status
Simulation time 202704400 ps
CPU time 0.84 seconds
Started Aug 07 06:06:32 PM PDT 24
Finished Aug 07 06:06:34 PM PDT 24
Peak memory 206960 kb
Host smart-d175dde4-c1c7-4822-bf11-b1d15772a266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17796
0806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.177960806
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1296543221
Short name T1817
Test name
Test status
Simulation time 183584850 ps
CPU time 0.93 seconds
Started Aug 07 06:06:32 PM PDT 24
Finished Aug 07 06:06:33 PM PDT 24
Peak memory 206972 kb
Host smart-26885455-7ad4-4f3d-8c94-c4c9d77debd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12965
43221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1296543221
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.1873286735
Short name T2461
Test name
Test status
Simulation time 321192410 ps
CPU time 1.14 seconds
Started Aug 07 06:06:32 PM PDT 24
Finished Aug 07 06:06:33 PM PDT 24
Peak memory 206960 kb
Host smart-4a1f1c6e-2bd6-4998-bcdc-224073a0c13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18732
86735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1873286735
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.234701055
Short name T2126
Test name
Test status
Simulation time 2507752569 ps
CPU time 72.2 seconds
Started Aug 07 06:06:31 PM PDT 24
Finished Aug 07 06:07:43 PM PDT 24
Peak memory 216848 kb
Host smart-31383d2d-466e-44b5-971e-5c1dbf03f4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23470
1055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.234701055
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.4208397781
Short name T1966
Test name
Test status
Simulation time 2558645898 ps
CPU time 17.45 seconds
Started Aug 07 06:06:11 PM PDT 24
Finished Aug 07 06:06:29 PM PDT 24
Peak memory 207312 kb
Host smart-b7c8261f-7fa6-4008-bfc7-9cab8d223556
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208397781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.4208397781
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.752454497
Short name T1048
Test name
Test status
Simulation time 68875509 ps
CPU time 0.71 seconds
Started Aug 07 06:07:04 PM PDT 24
Finished Aug 07 06:07:04 PM PDT 24
Peak memory 207056 kb
Host smart-d0ebeaac-97b5-4b4d-939b-10d591025679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=752454497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.752454497
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3435246121
Short name T1507
Test name
Test status
Simulation time 9104014536 ps
CPU time 12.36 seconds
Started Aug 07 06:06:31 PM PDT 24
Finished Aug 07 06:06:43 PM PDT 24
Peak memory 207304 kb
Host smart-0921c911-3446-4b45-a32d-08e610029350
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435246121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.3435246121
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.509197413
Short name T2069
Test name
Test status
Simulation time 13312211615 ps
CPU time 16.34 seconds
Started Aug 07 06:06:30 PM PDT 24
Finished Aug 07 06:06:47 PM PDT 24
Peak memory 215468 kb
Host smart-7dfbab3a-bff4-4f03-a3ef-bed4c72ce724
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=509197413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.509197413
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.2318937621
Short name T1110
Test name
Test status
Simulation time 25184906065 ps
CPU time 30.52 seconds
Started Aug 07 06:06:30 PM PDT 24
Finished Aug 07 06:07:00 PM PDT 24
Peak memory 215480 kb
Host smart-9cc0617e-a87e-4905-ac16-6739c2ab710d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318937621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.2318937621
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3541371854
Short name T540
Test name
Test status
Simulation time 152673383 ps
CPU time 0.89 seconds
Started Aug 07 06:06:37 PM PDT 24
Finished Aug 07 06:06:38 PM PDT 24
Peak memory 207000 kb
Host smart-eacb1f2f-f3c4-475c-962f-3fb71176795f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35413
71854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3541371854
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1955481701
Short name T1879
Test name
Test status
Simulation time 142820789 ps
CPU time 0.89 seconds
Started Aug 07 06:06:37 PM PDT 24
Finished Aug 07 06:06:38 PM PDT 24
Peak memory 206892 kb
Host smart-930dd010-6b66-4e0f-9880-06bec97b934d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19554
81701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1955481701
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2862234474
Short name T671
Test name
Test status
Simulation time 165939132 ps
CPU time 0.92 seconds
Started Aug 07 06:06:37 PM PDT 24
Finished Aug 07 06:06:38 PM PDT 24
Peak memory 206924 kb
Host smart-127653f4-3487-458b-a5ff-41deb43798b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28622
34474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2862234474
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1063566374
Short name T857
Test name
Test status
Simulation time 1153505334 ps
CPU time 3.26 seconds
Started Aug 07 06:06:37 PM PDT 24
Finished Aug 07 06:06:41 PM PDT 24
Peak memory 207148 kb
Host smart-bdb7f783-7a36-46d3-b53d-631e73fae1b5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1063566374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1063566374
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.3150961557
Short name T1367
Test name
Test status
Simulation time 30677761803 ps
CPU time 44.63 seconds
Started Aug 07 06:06:37 PM PDT 24
Finished Aug 07 06:07:22 PM PDT 24
Peak memory 207180 kb
Host smart-d2dde83c-7a4b-42e1-83cd-8cd6e647e1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31509
61557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3150961557
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.2240701135
Short name T2854
Test name
Test status
Simulation time 404842469 ps
CPU time 7.91 seconds
Started Aug 07 06:06:37 PM PDT 24
Finished Aug 07 06:06:45 PM PDT 24
Peak memory 207216 kb
Host smart-1dbb23d5-b77a-4449-bb75-fc599e21a9cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240701135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.2240701135
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.4136953807
Short name T422
Test name
Test status
Simulation time 656443277 ps
CPU time 1.58 seconds
Started Aug 07 06:06:39 PM PDT 24
Finished Aug 07 06:06:40 PM PDT 24
Peak memory 206984 kb
Host smart-9c8ad0d9-a40c-49f7-ac98-d3beaf2d5651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41369
53807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.4136953807
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2692331990
Short name T2513
Test name
Test status
Simulation time 153764051 ps
CPU time 0.81 seconds
Started Aug 07 06:06:37 PM PDT 24
Finished Aug 07 06:06:38 PM PDT 24
Peak memory 206956 kb
Host smart-6b411053-0f54-4db7-83f1-0ecb6cfc6935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26923
31990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2692331990
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3705576745
Short name T1418
Test name
Test status
Simulation time 45920103 ps
CPU time 0.72 seconds
Started Aug 07 06:06:35 PM PDT 24
Finished Aug 07 06:06:36 PM PDT 24
Peak memory 206956 kb
Host smart-7fdc48c8-99ce-4abc-ae6d-602f816dcfe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37055
76745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3705576745
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2083354307
Short name T2373
Test name
Test status
Simulation time 945873569 ps
CPU time 2.59 seconds
Started Aug 07 06:06:34 PM PDT 24
Finished Aug 07 06:06:37 PM PDT 24
Peak memory 207136 kb
Host smart-3e983347-23bc-43db-a51d-26cba75acf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20833
54307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2083354307
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_types.448978138
Short name T368
Test name
Test status
Simulation time 793296261 ps
CPU time 1.83 seconds
Started Aug 07 06:06:40 PM PDT 24
Finished Aug 07 06:06:42 PM PDT 24
Peak memory 206976 kb
Host smart-d73b4b80-cf9b-4d59-8e16-3c369b885ec6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=448978138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.448978138
Directory /workspace/34.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.28993426
Short name T2943
Test name
Test status
Simulation time 239614539 ps
CPU time 1.92 seconds
Started Aug 07 06:06:44 PM PDT 24
Finished Aug 07 06:06:46 PM PDT 24
Peak memory 207132 kb
Host smart-c1d4db19-04eb-4d59-afa7-d46d5758a660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28993
426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.28993426
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1329448501
Short name T93
Test name
Test status
Simulation time 228744538 ps
CPU time 1.19 seconds
Started Aug 07 06:07:03 PM PDT 24
Finished Aug 07 06:07:04 PM PDT 24
Peak memory 207204 kb
Host smart-f8e0addc-2c7a-4ec8-ad0d-b3fc30a2168a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1329448501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1329448501
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2407410510
Short name T1224
Test name
Test status
Simulation time 144126336 ps
CPU time 0.85 seconds
Started Aug 07 06:06:46 PM PDT 24
Finished Aug 07 06:06:46 PM PDT 24
Peak memory 206960 kb
Host smart-567c941f-e70a-42f5-b22b-c7e9d37933e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24074
10510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2407410510
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1537941077
Short name T1669
Test name
Test status
Simulation time 166919195 ps
CPU time 0.89 seconds
Started Aug 07 06:06:44 PM PDT 24
Finished Aug 07 06:06:45 PM PDT 24
Peak memory 207028 kb
Host smart-c072ba18-570c-4722-92ed-df3c13c1ec9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15379
41077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1537941077
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.2179231891
Short name T2659
Test name
Test status
Simulation time 4261949054 ps
CPU time 34.83 seconds
Started Aug 07 06:06:41 PM PDT 24
Finished Aug 07 06:07:16 PM PDT 24
Peak memory 223672 kb
Host smart-e1773cce-8875-423f-b3f9-917915a60512
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2179231891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2179231891
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.381332837
Short name T751
Test name
Test status
Simulation time 4022224225 ps
CPU time 28.88 seconds
Started Aug 07 06:06:42 PM PDT 24
Finished Aug 07 06:07:11 PM PDT 24
Peak memory 207268 kb
Host smart-cf4dfe21-2c0f-413f-bcfd-40fc7a5f4b0e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=381332837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.381332837
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3292984646
Short name T2590
Test name
Test status
Simulation time 218322828 ps
CPU time 0.98 seconds
Started Aug 07 06:06:52 PM PDT 24
Finished Aug 07 06:06:53 PM PDT 24
Peak memory 206992 kb
Host smart-462496d3-5cf1-437e-b4ab-42ae59581b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32929
84646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3292984646
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.793777494
Short name T2402
Test name
Test status
Simulation time 30081903184 ps
CPU time 44.56 seconds
Started Aug 07 06:06:46 PM PDT 24
Finished Aug 07 06:07:31 PM PDT 24
Peak memory 207288 kb
Host smart-e7246780-59b3-4489-b18f-4413f7b1ce30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79377
7494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.793777494
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2862752704
Short name T1712
Test name
Test status
Simulation time 6152596386 ps
CPU time 7.87 seconds
Started Aug 07 06:06:48 PM PDT 24
Finished Aug 07 06:06:56 PM PDT 24
Peak memory 216156 kb
Host smart-b388037d-c9a1-4609-88d4-24f9c299b07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28627
52704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2862752704
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2024580684
Short name T2862
Test name
Test status
Simulation time 3648852120 ps
CPU time 106.7 seconds
Started Aug 07 06:06:48 PM PDT 24
Finished Aug 07 06:08:35 PM PDT 24
Peak memory 217872 kb
Host smart-123f5e50-c610-4e89-bbe5-0efac6443524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20245
80684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2024580684
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3401283693
Short name T2668
Test name
Test status
Simulation time 2658604158 ps
CPU time 76.35 seconds
Started Aug 07 06:06:52 PM PDT 24
Finished Aug 07 06:08:09 PM PDT 24
Peak memory 215476 kb
Host smart-73f47ac7-2c9d-4ff6-9bb5-b85159a5368f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3401283693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3401283693
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.4138063329
Short name T1461
Test name
Test status
Simulation time 246563505 ps
CPU time 1 seconds
Started Aug 07 06:06:46 PM PDT 24
Finished Aug 07 06:06:47 PM PDT 24
Peak memory 206984 kb
Host smart-3467b83e-2d8e-4f4f-9c17-ec20c8e6b2c4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4138063329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.4138063329
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1225917017
Short name T521
Test name
Test status
Simulation time 183577668 ps
CPU time 0.91 seconds
Started Aug 07 06:06:46 PM PDT 24
Finished Aug 07 06:06:47 PM PDT 24
Peak memory 206976 kb
Host smart-4b4bfd10-362c-4b88-8b50-08978d42d923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12259
17017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1225917017
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.1696364081
Short name T1157
Test name
Test status
Simulation time 3652213420 ps
CPU time 104.97 seconds
Started Aug 07 06:06:53 PM PDT 24
Finished Aug 07 06:08:39 PM PDT 24
Peak memory 215476 kb
Host smart-37b786e1-c2ec-4bc8-a02d-d9db0965f3db
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1696364081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.1696364081
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.878114647
Short name T2387
Test name
Test status
Simulation time 161499095 ps
CPU time 0.88 seconds
Started Aug 07 06:06:50 PM PDT 24
Finished Aug 07 06:06:51 PM PDT 24
Peak memory 206996 kb
Host smart-f2d4239e-5c3b-467c-b919-eb1fe8f5371e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=878114647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.878114647
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3870818109
Short name T598
Test name
Test status
Simulation time 212372656 ps
CPU time 0.94 seconds
Started Aug 07 06:06:46 PM PDT 24
Finished Aug 07 06:06:47 PM PDT 24
Peak memory 207012 kb
Host smart-ae87b3e1-6a9e-4af5-9bcc-7897d34515a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38708
18109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3870818109
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3648723155
Short name T137
Test name
Test status
Simulation time 188692720 ps
CPU time 0.94 seconds
Started Aug 07 06:06:51 PM PDT 24
Finished Aug 07 06:06:52 PM PDT 24
Peak memory 207000 kb
Host smart-de1b8c7a-6ced-4c7e-be59-a58ae987cab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36487
23155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3648723155
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3038292419
Short name T1569
Test name
Test status
Simulation time 166332951 ps
CPU time 0.89 seconds
Started Aug 07 06:06:53 PM PDT 24
Finished Aug 07 06:06:54 PM PDT 24
Peak memory 207004 kb
Host smart-f17f5518-c21c-40b7-8559-50a9425e05bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30382
92419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3038292419
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.4271960072
Short name T1595
Test name
Test status
Simulation time 198548971 ps
CPU time 0.98 seconds
Started Aug 07 06:06:53 PM PDT 24
Finished Aug 07 06:06:54 PM PDT 24
Peak memory 206968 kb
Host smart-eac8892c-550b-46f5-b093-55b067a1517c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42719
60072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.4271960072
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3617565284
Short name T1896
Test name
Test status
Simulation time 159233397 ps
CPU time 0.85 seconds
Started Aug 07 06:06:54 PM PDT 24
Finished Aug 07 06:06:55 PM PDT 24
Peak memory 206884 kb
Host smart-f2128d74-58d5-45e7-8344-ae4b02c7ea5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36175
65284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3617565284
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1171394647
Short name T1053
Test name
Test status
Simulation time 158347472 ps
CPU time 0.9 seconds
Started Aug 07 06:06:53 PM PDT 24
Finished Aug 07 06:06:54 PM PDT 24
Peak memory 206996 kb
Host smart-027e1d68-3ced-4b6b-a07e-6672a239e8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11713
94647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1171394647
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1421613142
Short name T3001
Test name
Test status
Simulation time 225262676 ps
CPU time 1.04 seconds
Started Aug 07 06:06:53 PM PDT 24
Finished Aug 07 06:06:54 PM PDT 24
Peak memory 206896 kb
Host smart-cd9fce29-0b6a-4142-8f53-17c68949b10f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1421613142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1421613142
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.4250594069
Short name T710
Test name
Test status
Simulation time 204564039 ps
CPU time 0.91 seconds
Started Aug 07 06:06:53 PM PDT 24
Finished Aug 07 06:06:54 PM PDT 24
Peak memory 206924 kb
Host smart-5cd964af-27f5-411e-8b33-e5ae3b1c495d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42505
94069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.4250594069
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3997409028
Short name T1588
Test name
Test status
Simulation time 41079226 ps
CPU time 0.69 seconds
Started Aug 07 06:06:51 PM PDT 24
Finished Aug 07 06:06:52 PM PDT 24
Peak memory 206960 kb
Host smart-efffe028-f727-499d-86cd-7d1b4020dcfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39974
09028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3997409028
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3562431346
Short name T2727
Test name
Test status
Simulation time 7858928789 ps
CPU time 21.88 seconds
Started Aug 07 06:06:51 PM PDT 24
Finished Aug 07 06:07:13 PM PDT 24
Peak memory 215504 kb
Host smart-9e46819b-ba78-46db-b16d-36609c59e98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35624
31346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3562431346
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.287317542
Short name T1843
Test name
Test status
Simulation time 199389411 ps
CPU time 1.03 seconds
Started Aug 07 06:06:50 PM PDT 24
Finished Aug 07 06:06:51 PM PDT 24
Peak memory 206972 kb
Host smart-430f6e72-99a2-4306-930f-93ecbbf3b13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28731
7542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.287317542
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2833849175
Short name T880
Test name
Test status
Simulation time 196447705 ps
CPU time 0.96 seconds
Started Aug 07 06:07:00 PM PDT 24
Finished Aug 07 06:07:01 PM PDT 24
Peak memory 206884 kb
Host smart-b788e6ad-6c27-4b3e-aebd-6887ed94b847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28338
49175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2833849175
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3880079543
Short name T1220
Test name
Test status
Simulation time 229679585 ps
CPU time 0.97 seconds
Started Aug 07 06:06:55 PM PDT 24
Finished Aug 07 06:06:57 PM PDT 24
Peak memory 206972 kb
Host smart-52382889-35e6-4816-9908-ab837869efb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38800
79543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3880079543
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.3520651097
Short name T2183
Test name
Test status
Simulation time 195777844 ps
CPU time 0.9 seconds
Started Aug 07 06:06:55 PM PDT 24
Finished Aug 07 06:06:56 PM PDT 24
Peak memory 206992 kb
Host smart-5dd7a074-7aba-4b93-b32a-15ad9b8da209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35206
51097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.3520651097
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.4185374012
Short name T1438
Test name
Test status
Simulation time 220212383 ps
CPU time 0.99 seconds
Started Aug 07 06:07:00 PM PDT 24
Finished Aug 07 06:07:01 PM PDT 24
Peak memory 206912 kb
Host smart-dff03df4-996e-49a7-9003-3988e376d4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41853
74012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.4185374012
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_rx_full.2984000988
Short name T50
Test name
Test status
Simulation time 278893002 ps
CPU time 1.11 seconds
Started Aug 07 06:06:56 PM PDT 24
Finished Aug 07 06:06:57 PM PDT 24
Peak memory 206960 kb
Host smart-8a7f1495-94f6-480c-a927-2a8a628f0282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29840
00988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.2984000988
Directory /workspace/34.usbdev_rx_full/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1143875422
Short name T1869
Test name
Test status
Simulation time 151654282 ps
CPU time 0.84 seconds
Started Aug 07 06:06:56 PM PDT 24
Finished Aug 07 06:06:58 PM PDT 24
Peak memory 206980 kb
Host smart-30199119-6793-4c18-9f9c-f43cb39cce27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11438
75422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1143875422
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.4144308085
Short name T1068
Test name
Test status
Simulation time 151908966 ps
CPU time 0.82 seconds
Started Aug 07 06:06:58 PM PDT 24
Finished Aug 07 06:06:59 PM PDT 24
Peak memory 206988 kb
Host smart-e2f6c558-0954-4934-abe9-68c920077ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41443
08085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.4144308085
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.435865719
Short name T645
Test name
Test status
Simulation time 190642029 ps
CPU time 0.94 seconds
Started Aug 07 06:06:55 PM PDT 24
Finished Aug 07 06:06:57 PM PDT 24
Peak memory 206988 kb
Host smart-a2119128-7a6b-4b51-a463-32cdbd041c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43586
5719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.435865719
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.3058738849
Short name T1968
Test name
Test status
Simulation time 3583328072 ps
CPU time 26.76 seconds
Started Aug 07 06:06:57 PM PDT 24
Finished Aug 07 06:07:23 PM PDT 24
Peak memory 207292 kb
Host smart-dcb55161-9dda-487e-b6ae-ec2376421cf1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3058738849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.3058738849
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2297295453
Short name T2370
Test name
Test status
Simulation time 152837235 ps
CPU time 0.82 seconds
Started Aug 07 06:06:57 PM PDT 24
Finished Aug 07 06:06:58 PM PDT 24
Peak memory 207024 kb
Host smart-4401e385-f63e-49c2-88b0-225c9c53952d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22972
95453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2297295453
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1835875503
Short name T693
Test name
Test status
Simulation time 155266811 ps
CPU time 0.84 seconds
Started Aug 07 06:06:58 PM PDT 24
Finished Aug 07 06:06:59 PM PDT 24
Peak memory 206992 kb
Host smart-509b1e00-c10e-4c38-83ac-588ce6a81137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18358
75503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1835875503
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.2303822431
Short name T1395
Test name
Test status
Simulation time 1020271256 ps
CPU time 2.38 seconds
Started Aug 07 06:06:56 PM PDT 24
Finished Aug 07 06:06:58 PM PDT 24
Peak memory 207160 kb
Host smart-40fbf3d3-742f-44e4-9497-2e41246abd2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23038
22431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.2303822431
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.3603435840
Short name T759
Test name
Test status
Simulation time 2002574031 ps
CPU time 57.33 seconds
Started Aug 07 06:06:58 PM PDT 24
Finished Aug 07 06:07:56 PM PDT 24
Peak memory 216696 kb
Host smart-6ab5b997-959f-4ed8-b84a-bb911b710bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36034
35840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.3603435840
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.325008303
Short name T1716
Test name
Test status
Simulation time 896510660 ps
CPU time 5.63 seconds
Started Aug 07 06:06:38 PM PDT 24
Finished Aug 07 06:06:44 PM PDT 24
Peak memory 207212 kb
Host smart-8c04d7f6-d0ba-4086-b512-23614c45aa3e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325008303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_host
_handshake.325008303
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.2602143423
Short name T2792
Test name
Test status
Simulation time 35381003 ps
CPU time 0.66 seconds
Started Aug 07 06:07:33 PM PDT 24
Finished Aug 07 06:07:34 PM PDT 24
Peak memory 206984 kb
Host smart-32f81056-f391-4df1-b7c7-8e20c5149fe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2602143423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2602143423
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3019774070
Short name T695
Test name
Test status
Simulation time 4245095413 ps
CPU time 7.02 seconds
Started Aug 07 06:07:02 PM PDT 24
Finished Aug 07 06:07:09 PM PDT 24
Peak memory 215488 kb
Host smart-4d9eb06e-008b-4036-8ac2-5257d36734e6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019774070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.3019774070
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3710764970
Short name T2016
Test name
Test status
Simulation time 15017161270 ps
CPU time 17.34 seconds
Started Aug 07 06:07:07 PM PDT 24
Finished Aug 07 06:07:25 PM PDT 24
Peak memory 215436 kb
Host smart-9cae215c-673c-44a6-a6b7-96c23509dd0f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710764970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3710764970
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.230372854
Short name T2317
Test name
Test status
Simulation time 24391220908 ps
CPU time 28.02 seconds
Started Aug 07 06:07:04 PM PDT 24
Finished Aug 07 06:07:32 PM PDT 24
Peak memory 215452 kb
Host smart-4f280655-e667-45bd-b159-5139f5bb341d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230372854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ao
n_wake_resume.230372854
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.833202262
Short name T2000
Test name
Test status
Simulation time 213122191 ps
CPU time 0.91 seconds
Started Aug 07 06:07:06 PM PDT 24
Finished Aug 07 06:07:07 PM PDT 24
Peak memory 206988 kb
Host smart-a518fec7-33ee-4d83-ae45-27f064101512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83320
2262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.833202262
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.821532016
Short name T1211
Test name
Test status
Simulation time 179374876 ps
CPU time 0.9 seconds
Started Aug 07 06:07:02 PM PDT 24
Finished Aug 07 06:07:03 PM PDT 24
Peak memory 206968 kb
Host smart-717f0ee4-896a-4133-9d56-7134ad67359b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82153
2016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.821532016
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2397915654
Short name T870
Test name
Test status
Simulation time 528242804 ps
CPU time 1.77 seconds
Started Aug 07 06:07:03 PM PDT 24
Finished Aug 07 06:07:05 PM PDT 24
Peak memory 207012 kb
Host smart-34fde493-575b-4e0c-a1d8-f7695cafa9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23979
15654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2397915654
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.2555949765
Short name T849
Test name
Test status
Simulation time 969162400 ps
CPU time 2.59 seconds
Started Aug 07 06:07:05 PM PDT 24
Finished Aug 07 06:07:08 PM PDT 24
Peak memory 207048 kb
Host smart-b8e4cf13-c15e-4f48-8a83-fead8134df3e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2555949765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.2555949765
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.4190933026
Short name T2777
Test name
Test status
Simulation time 31719366954 ps
CPU time 49.75 seconds
Started Aug 07 06:07:08 PM PDT 24
Finished Aug 07 06:07:58 PM PDT 24
Peak memory 207236 kb
Host smart-5c8de9fb-8c67-43c1-8be1-28c8fcbf9be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41909
33026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.4190933026
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.315095570
Short name T2368
Test name
Test status
Simulation time 2445667740 ps
CPU time 22.66 seconds
Started Aug 07 06:07:02 PM PDT 24
Finished Aug 07 06:07:25 PM PDT 24
Peak memory 207332 kb
Host smart-f1b6d98a-3b09-4682-a27c-b2444cfd1015
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315095570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.315095570
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.43262017
Short name T1423
Test name
Test status
Simulation time 896003305 ps
CPU time 2.12 seconds
Started Aug 07 06:07:12 PM PDT 24
Finished Aug 07 06:07:15 PM PDT 24
Peak memory 206968 kb
Host smart-6c876254-b094-4e83-8c0a-551744bbbd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43262
017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.43262017
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.535822382
Short name T2524
Test name
Test status
Simulation time 180149311 ps
CPU time 0.87 seconds
Started Aug 07 06:07:07 PM PDT 24
Finished Aug 07 06:07:08 PM PDT 24
Peak memory 207008 kb
Host smart-a242c215-7709-4dc7-80a4-762b1592ae98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53582
2382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.535822382
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.998796644
Short name T512
Test name
Test status
Simulation time 63092947 ps
CPU time 0.74 seconds
Started Aug 07 06:07:08 PM PDT 24
Finished Aug 07 06:07:08 PM PDT 24
Peak memory 206952 kb
Host smart-612587ff-9bfa-4326-816f-1d400db7c1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99879
6644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.998796644
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.327369107
Short name T237
Test name
Test status
Simulation time 937824959 ps
CPU time 2.65 seconds
Started Aug 07 06:07:10 PM PDT 24
Finished Aug 07 06:07:12 PM PDT 24
Peak memory 207256 kb
Host smart-d17287c3-c61b-47c3-bca5-f146245602de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32736
9107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.327369107
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_types.4291798654
Short name T463
Test name
Test status
Simulation time 316863548 ps
CPU time 1.17 seconds
Started Aug 07 06:07:07 PM PDT 24
Finished Aug 07 06:07:09 PM PDT 24
Peak memory 206948 kb
Host smart-f51d5934-788d-4208-add7-4e69ed863966
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4291798654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.4291798654
Directory /workspace/35.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.893224480
Short name T2642
Test name
Test status
Simulation time 200314544 ps
CPU time 2.64 seconds
Started Aug 07 06:07:09 PM PDT 24
Finished Aug 07 06:07:12 PM PDT 24
Peak memory 207164 kb
Host smart-ef6f793b-a79f-4e2a-83d1-48ba443db5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89322
4480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.893224480
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1638821503
Short name T3042
Test name
Test status
Simulation time 220264765 ps
CPU time 1.06 seconds
Started Aug 07 06:07:10 PM PDT 24
Finished Aug 07 06:07:11 PM PDT 24
Peak memory 207168 kb
Host smart-5c756cb1-7334-4b1a-8e7c-90a5c0330387
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1638821503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1638821503
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3335239264
Short name T2627
Test name
Test status
Simulation time 162286654 ps
CPU time 0.94 seconds
Started Aug 07 06:07:06 PM PDT 24
Finished Aug 07 06:07:07 PM PDT 24
Peak memory 206984 kb
Host smart-a1e6e815-5850-4bbd-952a-2259e9f2b85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33352
39264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3335239264
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.512435086
Short name T1269
Test name
Test status
Simulation time 159659866 ps
CPU time 0.91 seconds
Started Aug 07 06:07:12 PM PDT 24
Finished Aug 07 06:07:13 PM PDT 24
Peak memory 206940 kb
Host smart-31da1f49-0fc5-47f3-8e90-9ea9dd9217cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51243
5086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.512435086
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.185916642
Short name T1155
Test name
Test status
Simulation time 4684878065 ps
CPU time 34.02 seconds
Started Aug 07 06:07:08 PM PDT 24
Finished Aug 07 06:07:42 PM PDT 24
Peak memory 223680 kb
Host smart-f0fb09fc-59c4-4616-b359-e22fe2241140
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=185916642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.185916642
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.2430235232
Short name T2771
Test name
Test status
Simulation time 5122331763 ps
CPU time 63.61 seconds
Started Aug 07 06:07:09 PM PDT 24
Finished Aug 07 06:08:12 PM PDT 24
Peak memory 207172 kb
Host smart-c7d5c475-9581-4d5e-bf56-c0423ca2b9d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2430235232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.2430235232
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.81144483
Short name T1528
Test name
Test status
Simulation time 242058289 ps
CPU time 0.97 seconds
Started Aug 07 06:07:14 PM PDT 24
Finished Aug 07 06:07:15 PM PDT 24
Peak memory 206912 kb
Host smart-55668b87-1be9-4a96-ad54-adfdf3dc0c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81144
483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.81144483
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1078264822
Short name T2811
Test name
Test status
Simulation time 28683155468 ps
CPU time 40.71 seconds
Started Aug 07 06:07:20 PM PDT 24
Finished Aug 07 06:08:01 PM PDT 24
Peak memory 207216 kb
Host smart-71360534-88d8-4876-ba9f-ff86afc80fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10782
64822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1078264822
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2537748115
Short name T785
Test name
Test status
Simulation time 9576427406 ps
CPU time 11.35 seconds
Started Aug 07 06:07:12 PM PDT 24
Finished Aug 07 06:07:23 PM PDT 24
Peak memory 207292 kb
Host smart-77c4e97f-711f-4add-93c1-4c836df04169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25377
48115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2537748115
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.3363365597
Short name T1895
Test name
Test status
Simulation time 4631190043 ps
CPU time 133.61 seconds
Started Aug 07 06:07:21 PM PDT 24
Finished Aug 07 06:09:35 PM PDT 24
Peak memory 217984 kb
Host smart-595bcabe-674f-4c94-aac5-daf400f9cfb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33633
65597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.3363365597
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.1619951409
Short name T1337
Test name
Test status
Simulation time 2582458497 ps
CPU time 75.88 seconds
Started Aug 07 06:07:15 PM PDT 24
Finished Aug 07 06:08:31 PM PDT 24
Peak memory 217020 kb
Host smart-fe487489-1732-4a75-8e0f-84071a70741a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1619951409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.1619951409
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.120319360
Short name T1647
Test name
Test status
Simulation time 265827403 ps
CPU time 1.03 seconds
Started Aug 07 06:07:13 PM PDT 24
Finished Aug 07 06:07:14 PM PDT 24
Peak memory 206960 kb
Host smart-62231657-577c-4296-9766-0cda7ba1dbc8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=120319360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.120319360
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3726447878
Short name T1603
Test name
Test status
Simulation time 192975984 ps
CPU time 0.91 seconds
Started Aug 07 06:07:15 PM PDT 24
Finished Aug 07 06:07:16 PM PDT 24
Peak memory 206944 kb
Host smart-c7f8a003-5d47-422c-843b-563d27bcd491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37264
47878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3726447878
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.3870110762
Short name T559
Test name
Test status
Simulation time 2180141188 ps
CPU time 16.32 seconds
Started Aug 07 06:07:19 PM PDT 24
Finished Aug 07 06:07:36 PM PDT 24
Peak memory 215448 kb
Host smart-236cd465-0b69-4758-86ad-288bdf59b72f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3870110762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.3870110762
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.863419018
Short name T3022
Test name
Test status
Simulation time 190428564 ps
CPU time 0.87 seconds
Started Aug 07 06:07:15 PM PDT 24
Finished Aug 07 06:07:16 PM PDT 24
Peak memory 207004 kb
Host smart-9c88718f-705a-4bce-88b7-dc487c447e47
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=863419018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.863419018
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3133325813
Short name T2870
Test name
Test status
Simulation time 144881023 ps
CPU time 0.8 seconds
Started Aug 07 06:07:15 PM PDT 24
Finished Aug 07 06:07:16 PM PDT 24
Peak memory 206980 kb
Host smart-491dac07-bcfc-42d5-a5aa-44abe15d6197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31333
25813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3133325813
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.1732166679
Short name T151
Test name
Test status
Simulation time 216897214 ps
CPU time 0.94 seconds
Started Aug 07 06:07:13 PM PDT 24
Finished Aug 07 06:07:14 PM PDT 24
Peak memory 207000 kb
Host smart-f6acd030-6fed-41a0-8df9-6102c9dcf792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17321
66679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1732166679
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3395595328
Short name T2688
Test name
Test status
Simulation time 172009590 ps
CPU time 0.83 seconds
Started Aug 07 06:07:21 PM PDT 24
Finished Aug 07 06:07:22 PM PDT 24
Peak memory 206904 kb
Host smart-68ef9973-23a9-4a28-8caa-cec2d6beba9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33955
95328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3395595328
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3316006294
Short name T2755
Test name
Test status
Simulation time 171150208 ps
CPU time 0.86 seconds
Started Aug 07 06:07:19 PM PDT 24
Finished Aug 07 06:07:20 PM PDT 24
Peak memory 206964 kb
Host smart-adaa2349-ab8e-49ae-acfd-f4f590528887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33160
06294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3316006294
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1200609987
Short name T1024
Test name
Test status
Simulation time 147862226 ps
CPU time 0.82 seconds
Started Aug 07 06:07:21 PM PDT 24
Finished Aug 07 06:07:22 PM PDT 24
Peak memory 207000 kb
Host smart-428d6ef8-a568-484e-95aa-771bd8ffb8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12006
09987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1200609987
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2106744766
Short name T195
Test name
Test status
Simulation time 161890314 ps
CPU time 0.87 seconds
Started Aug 07 06:07:21 PM PDT 24
Finished Aug 07 06:07:22 PM PDT 24
Peak memory 207016 kb
Host smart-bca52c99-b237-406f-ad9e-f9acf4eec3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21067
44766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2106744766
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.3254087739
Short name T838
Test name
Test status
Simulation time 259984766 ps
CPU time 1.05 seconds
Started Aug 07 06:07:21 PM PDT 24
Finished Aug 07 06:07:23 PM PDT 24
Peak memory 206976 kb
Host smart-518bf75b-b7b5-4a14-ba23-d1164f464536
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3254087739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.3254087739
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3143740373
Short name T209
Test name
Test status
Simulation time 145652494 ps
CPU time 0.84 seconds
Started Aug 07 06:07:24 PM PDT 24
Finished Aug 07 06:07:25 PM PDT 24
Peak memory 207004 kb
Host smart-76fcaea3-bd6d-4380-9f1b-fa96574b5b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31437
40373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3143740373
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1293057531
Short name T2521
Test name
Test status
Simulation time 56033661 ps
CPU time 0.72 seconds
Started Aug 07 06:07:22 PM PDT 24
Finished Aug 07 06:07:23 PM PDT 24
Peak memory 207008 kb
Host smart-bc6c45ce-474f-4179-9b44-ea45a62ed749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12930
57531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1293057531
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.359811845
Short name T293
Test name
Test status
Simulation time 7974606346 ps
CPU time 18.64 seconds
Started Aug 07 06:07:22 PM PDT 24
Finished Aug 07 06:07:40 PM PDT 24
Peak memory 215484 kb
Host smart-2984ac8f-5b20-4e42-8083-6eb7a234aea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35981
1845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.359811845
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.4136978877
Short name T2938
Test name
Test status
Simulation time 165253040 ps
CPU time 0.93 seconds
Started Aug 07 06:07:24 PM PDT 24
Finished Aug 07 06:07:25 PM PDT 24
Peak memory 207004 kb
Host smart-533078dc-5d5f-4547-bcbe-38938a899dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41369
78877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.4136978877
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2504061757
Short name T1072
Test name
Test status
Simulation time 252124259 ps
CPU time 0.96 seconds
Started Aug 07 06:07:27 PM PDT 24
Finished Aug 07 06:07:28 PM PDT 24
Peak memory 206952 kb
Host smart-9405edbf-eeae-4a40-82f6-f5a6297066f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25040
61757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2504061757
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.267656220
Short name T907
Test name
Test status
Simulation time 241549596 ps
CPU time 1 seconds
Started Aug 07 06:07:26 PM PDT 24
Finished Aug 07 06:07:27 PM PDT 24
Peak memory 206984 kb
Host smart-acd6b6cb-6c29-4c57-b73c-8ef379cef262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26765
6220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.267656220
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3195553591
Short name T2219
Test name
Test status
Simulation time 170486654 ps
CPU time 0.86 seconds
Started Aug 07 06:07:27 PM PDT 24
Finished Aug 07 06:07:28 PM PDT 24
Peak memory 206992 kb
Host smart-e394d5db-f43b-481f-baf2-591b8baf7acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31955
53591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3195553591
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.118322418
Short name T1802
Test name
Test status
Simulation time 140909793 ps
CPU time 0.82 seconds
Started Aug 07 06:07:27 PM PDT 24
Finished Aug 07 06:07:28 PM PDT 24
Peak memory 206952 kb
Host smart-b3114d8b-1e85-4a95-b66f-c30ef5098f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11832
2418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.118322418
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_rx_full.2713313209
Short name T1470
Test name
Test status
Simulation time 360543012 ps
CPU time 1.31 seconds
Started Aug 07 06:07:30 PM PDT 24
Finished Aug 07 06:07:31 PM PDT 24
Peak memory 206912 kb
Host smart-0ea838e0-c959-4a1c-aa86-e01d87f39142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27133
13209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.2713313209
Directory /workspace/35.usbdev_rx_full/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2600913496
Short name T2176
Test name
Test status
Simulation time 164178769 ps
CPU time 0.84 seconds
Started Aug 07 06:08:07 PM PDT 24
Finished Aug 07 06:08:08 PM PDT 24
Peak memory 206980 kb
Host smart-e9cfc21d-b64b-4932-9a10-3fc5400fe060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26009
13496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2600913496
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3666070079
Short name T1121
Test name
Test status
Simulation time 154640289 ps
CPU time 0.89 seconds
Started Aug 07 06:07:30 PM PDT 24
Finished Aug 07 06:07:31 PM PDT 24
Peak memory 206924 kb
Host smart-4a338b0d-ffb3-4d5d-8de3-4844255b728d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36660
70079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3666070079
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2749898664
Short name T1027
Test name
Test status
Simulation time 263329145 ps
CPU time 1.1 seconds
Started Aug 07 06:07:25 PM PDT 24
Finished Aug 07 06:07:26 PM PDT 24
Peak memory 206968 kb
Host smart-f741cfb6-0e20-4888-9dfb-8566ae7ef624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27498
98664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2749898664
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.3183624839
Short name T1518
Test name
Test status
Simulation time 2562499626 ps
CPU time 72.23 seconds
Started Aug 07 06:07:27 PM PDT 24
Finished Aug 07 06:08:39 PM PDT 24
Peak memory 215440 kb
Host smart-e946896e-d3e0-4b79-9438-8a77ea00d31c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3183624839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.3183624839
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2248931093
Short name T2532
Test name
Test status
Simulation time 176034761 ps
CPU time 0.88 seconds
Started Aug 07 06:07:24 PM PDT 24
Finished Aug 07 06:07:25 PM PDT 24
Peak memory 206980 kb
Host smart-0f99a511-2d69-45fb-b6b1-b28c2e194b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22489
31093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2248931093
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3760528856
Short name T2106
Test name
Test status
Simulation time 165326530 ps
CPU time 0.86 seconds
Started Aug 07 06:07:32 PM PDT 24
Finished Aug 07 06:07:33 PM PDT 24
Peak memory 207012 kb
Host smart-09b5b851-0cd3-4c1c-b92f-4e88aada6cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37605
28856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3760528856
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.4182122423
Short name T1300
Test name
Test status
Simulation time 1360944668 ps
CPU time 3.16 seconds
Started Aug 07 06:07:31 PM PDT 24
Finished Aug 07 06:07:34 PM PDT 24
Peak memory 207168 kb
Host smart-ffd1d86c-43e7-49e6-9f0e-29b708335fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41821
22423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.4182122423
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2994631044
Short name T2155
Test name
Test status
Simulation time 3264752633 ps
CPU time 25.15 seconds
Started Aug 07 06:07:34 PM PDT 24
Finished Aug 07 06:07:59 PM PDT 24
Peak memory 215548 kb
Host smart-774b4db1-abcf-46d7-b96d-634e1855d485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29946
31044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2994631044
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.4110972019
Short name T2216
Test name
Test status
Simulation time 3622079448 ps
CPU time 23.52 seconds
Started Aug 07 06:07:02 PM PDT 24
Finished Aug 07 06:07:26 PM PDT 24
Peak memory 207372 kb
Host smart-1381595e-9a6a-4fd3-8f41-055f7230bfa4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110972019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.4110972019
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.1647936882
Short name T2971
Test name
Test status
Simulation time 35836827 ps
CPU time 0.68 seconds
Started Aug 07 06:08:02 PM PDT 24
Finished Aug 07 06:08:03 PM PDT 24
Peak memory 207084 kb
Host smart-5a54f721-3b47-43ab-ba05-1fb8ebba0881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1647936882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.1647936882
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2561991724
Short name T1275
Test name
Test status
Simulation time 5793374835 ps
CPU time 8.08 seconds
Started Aug 07 06:07:34 PM PDT 24
Finished Aug 07 06:07:42 PM PDT 24
Peak memory 215440 kb
Host smart-6dc39663-a540-4821-af96-194c85caacd2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561991724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.2561991724
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1329917146
Short name T663
Test name
Test status
Simulation time 18950745308 ps
CPU time 20.18 seconds
Started Aug 07 06:07:31 PM PDT 24
Finished Aug 07 06:07:51 PM PDT 24
Peak memory 207252 kb
Host smart-1386d249-cabe-400c-a377-1bd5d6c7716e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329917146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1329917146
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.958176374
Short name T1783
Test name
Test status
Simulation time 24903323403 ps
CPU time 29.3 seconds
Started Aug 07 06:07:34 PM PDT 24
Finished Aug 07 06:08:03 PM PDT 24
Peak memory 215472 kb
Host smart-2ae4ea85-e500-4446-860c-dbba85d78469
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958176374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_ao
n_wake_resume.958176374
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.633193246
Short name T2515
Test name
Test status
Simulation time 161903096 ps
CPU time 0.9 seconds
Started Aug 07 06:07:31 PM PDT 24
Finished Aug 07 06:07:32 PM PDT 24
Peak memory 206964 kb
Host smart-035ddd9f-fd14-44db-ac76-0bc927d0ef96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63319
3246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.633193246
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.4238989959
Short name T1253
Test name
Test status
Simulation time 182355879 ps
CPU time 0.9 seconds
Started Aug 07 06:07:34 PM PDT 24
Finished Aug 07 06:07:35 PM PDT 24
Peak memory 206956 kb
Host smart-42e2bdac-beee-4b80-8670-8286a8c41538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389
89959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.4238989959
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.4250124259
Short name T2850
Test name
Test status
Simulation time 219487133 ps
CPU time 1.03 seconds
Started Aug 07 06:07:32 PM PDT 24
Finished Aug 07 06:07:33 PM PDT 24
Peak memory 207004 kb
Host smart-ceb4f5b0-26fb-4ce3-a143-375f14d149bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42501
24259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.4250124259
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.136620202
Short name T1527
Test name
Test status
Simulation time 963265993 ps
CPU time 2.61 seconds
Started Aug 07 06:07:32 PM PDT 24
Finished Aug 07 06:07:35 PM PDT 24
Peak memory 207232 kb
Host smart-73d979fc-0cc0-413a-8b4a-d1ff893d2e01
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=136620202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.136620202
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1380493506
Short name T2916
Test name
Test status
Simulation time 31864880102 ps
CPU time 52.18 seconds
Started Aug 07 06:07:33 PM PDT 24
Finished Aug 07 06:08:26 PM PDT 24
Peak memory 207304 kb
Host smart-2a9cd310-af4c-4455-af0a-e6d81c254fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13804
93506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1380493506
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.2341285645
Short name T1911
Test name
Test status
Simulation time 1455601091 ps
CPU time 33.06 seconds
Started Aug 07 06:07:37 PM PDT 24
Finished Aug 07 06:08:10 PM PDT 24
Peak memory 207176 kb
Host smart-1a730044-a567-4c82-aa92-7fe1d12b2e24
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341285645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.2341285645
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.598153262
Short name T1303
Test name
Test status
Simulation time 1150363009 ps
CPU time 2.63 seconds
Started Aug 07 06:07:38 PM PDT 24
Finished Aug 07 06:07:41 PM PDT 24
Peak memory 206980 kb
Host smart-d04ee6d0-ac3a-408a-81d3-b0d4c7171b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59815
3262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.598153262
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1888023972
Short name T3058
Test name
Test status
Simulation time 140881316 ps
CPU time 0.84 seconds
Started Aug 07 06:07:38 PM PDT 24
Finished Aug 07 06:07:38 PM PDT 24
Peak memory 206960 kb
Host smart-c60fea76-d8ec-456a-81b9-6fd88804bdb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18880
23972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1888023972
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.393484048
Short name T1378
Test name
Test status
Simulation time 31295730 ps
CPU time 0.7 seconds
Started Aug 07 06:07:36 PM PDT 24
Finished Aug 07 06:07:37 PM PDT 24
Peak memory 206864 kb
Host smart-4d7304a0-abf8-436a-b051-a56d19a1c931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39348
4048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.393484048
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.4240139401
Short name T548
Test name
Test status
Simulation time 715518657 ps
CPU time 2.03 seconds
Started Aug 07 06:07:39 PM PDT 24
Finished Aug 07 06:07:41 PM PDT 24
Peak memory 207184 kb
Host smart-8529733c-988b-4bd9-8f9d-8bbf69117d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42401
39401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.4240139401
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_types.4187823927
Short name T462
Test name
Test status
Simulation time 216244136 ps
CPU time 1.1 seconds
Started Aug 07 06:07:38 PM PDT 24
Finished Aug 07 06:07:40 PM PDT 24
Peak memory 206864 kb
Host smart-12e63bd4-275d-4c25-9041-62a09d6e2906
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4187823927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.4187823927
Directory /workspace/36.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.601169343
Short name T3055
Test name
Test status
Simulation time 304071801 ps
CPU time 2.55 seconds
Started Aug 07 06:07:37 PM PDT 24
Finished Aug 07 06:07:39 PM PDT 24
Peak memory 207100 kb
Host smart-8591ec35-15be-424d-9746-4388a890e99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60116
9343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.601169343
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3017647206
Short name T561
Test name
Test status
Simulation time 173013151 ps
CPU time 0.97 seconds
Started Aug 07 06:07:39 PM PDT 24
Finished Aug 07 06:07:40 PM PDT 24
Peak memory 215480 kb
Host smart-72be855b-f5d0-4216-b485-366bf561fd66
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3017647206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3017647206
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3228136147
Short name T610
Test name
Test status
Simulation time 180192734 ps
CPU time 0.85 seconds
Started Aug 07 06:07:41 PM PDT 24
Finished Aug 07 06:07:42 PM PDT 24
Peak memory 207012 kb
Host smart-bf4f9abb-2e17-4459-93cc-56c8e25890f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32281
36147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3228136147
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2496374
Short name T2538
Test name
Test status
Simulation time 230622141 ps
CPU time 1 seconds
Started Aug 07 06:07:40 PM PDT 24
Finished Aug 07 06:07:41 PM PDT 24
Peak memory 206972 kb
Host smart-f89d04ed-488f-4684-950e-ba9ac9094e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24963
74 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2496374
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.110741791
Short name T1731
Test name
Test status
Simulation time 4550857158 ps
CPU time 129.48 seconds
Started Aug 07 06:07:40 PM PDT 24
Finished Aug 07 06:09:50 PM PDT 24
Peak memory 217148 kb
Host smart-b8d72957-f937-4ce4-950b-1668990e5cb8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=110741791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.110741791
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.1081802579
Short name T1893
Test name
Test status
Simulation time 6638618570 ps
CPU time 82.62 seconds
Started Aug 07 06:07:47 PM PDT 24
Finished Aug 07 06:09:10 PM PDT 24
Peak memory 207256 kb
Host smart-c0bbda8a-7f57-4dcf-8a25-cf87dca06214
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1081802579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.1081802579
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2323411885
Short name T2061
Test name
Test status
Simulation time 184636899 ps
CPU time 0.86 seconds
Started Aug 07 06:07:47 PM PDT 24
Finished Aug 07 06:07:48 PM PDT 24
Peak memory 206984 kb
Host smart-d2087eb4-c820-480e-8b00-e56525fdcd07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23234
11885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2323411885
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.2781204705
Short name T1335
Test name
Test status
Simulation time 10329051084 ps
CPU time 14.59 seconds
Started Aug 07 06:07:48 PM PDT 24
Finished Aug 07 06:08:02 PM PDT 24
Peak memory 207200 kb
Host smart-355dae6c-2f48-4e7a-acdb-c09f5d78a664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27812
04705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.2781204705
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2920838097
Short name T3011
Test name
Test status
Simulation time 9573992781 ps
CPU time 14.17 seconds
Started Aug 07 06:07:46 PM PDT 24
Finished Aug 07 06:08:01 PM PDT 24
Peak memory 207272 kb
Host smart-79e3e956-8b29-44f3-b9f9-2cd570e979a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29208
38097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2920838097
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2934757601
Short name T1784
Test name
Test status
Simulation time 3868172504 ps
CPU time 29.02 seconds
Started Aug 07 06:07:44 PM PDT 24
Finished Aug 07 06:08:13 PM PDT 24
Peak memory 223680 kb
Host smart-f9676861-cb51-4056-b63b-4869c93aef0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29347
57601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2934757601
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1892545186
Short name T1270
Test name
Test status
Simulation time 2376113502 ps
CPU time 66.84 seconds
Started Aug 07 06:07:46 PM PDT 24
Finished Aug 07 06:08:53 PM PDT 24
Peak memory 215512 kb
Host smart-64c75204-f0c6-4608-bd3e-a11bb4c22f82
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1892545186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1892545186
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.365483995
Short name T2381
Test name
Test status
Simulation time 239775765 ps
CPU time 0.97 seconds
Started Aug 07 06:07:45 PM PDT 24
Finished Aug 07 06:07:46 PM PDT 24
Peak memory 207020 kb
Host smart-0f6f50fe-861c-4bcb-9291-6aecc321b67c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=365483995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.365483995
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.3188499764
Short name T2173
Test name
Test status
Simulation time 193078380 ps
CPU time 0.92 seconds
Started Aug 07 06:07:46 PM PDT 24
Finished Aug 07 06:07:47 PM PDT 24
Peak memory 207040 kb
Host smart-086833d3-2c3f-4d90-9e16-2dd8a9503504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31884
99764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3188499764
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.331428444
Short name T1181
Test name
Test status
Simulation time 3030689166 ps
CPU time 30.62 seconds
Started Aug 07 06:07:48 PM PDT 24
Finished Aug 07 06:08:19 PM PDT 24
Peak memory 215448 kb
Host smart-1f970f41-96aa-4a75-a543-78d6d93e6f16
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=331428444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.331428444
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.4240412436
Short name T1169
Test name
Test status
Simulation time 217167873 ps
CPU time 0.95 seconds
Started Aug 07 06:07:52 PM PDT 24
Finished Aug 07 06:07:53 PM PDT 24
Peak memory 207216 kb
Host smart-1aef0c83-a3f9-4be4-a32f-5c255490d107
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4240412436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.4240412436
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2910628056
Short name T782
Test name
Test status
Simulation time 200860929 ps
CPU time 0.9 seconds
Started Aug 07 06:07:51 PM PDT 24
Finished Aug 07 06:07:52 PM PDT 24
Peak memory 207000 kb
Host smart-0a9831a3-2628-4660-9f62-ecce493f9090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29106
28056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2910628056
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.175518157
Short name T145
Test name
Test status
Simulation time 249737990 ps
CPU time 1.07 seconds
Started Aug 07 06:07:55 PM PDT 24
Finished Aug 07 06:07:56 PM PDT 24
Peak memory 206972 kb
Host smart-32072f14-643f-4321-9aad-97ce9e2ccedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17551
8157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.175518157
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3421316103
Short name T2960
Test name
Test status
Simulation time 213494096 ps
CPU time 0.99 seconds
Started Aug 07 06:07:53 PM PDT 24
Finished Aug 07 06:07:54 PM PDT 24
Peak memory 206992 kb
Host smart-f0804a7c-091b-4e35-ac69-85f22eb988b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34213
16103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3421316103
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2545482900
Short name T868
Test name
Test status
Simulation time 156274079 ps
CPU time 0.86 seconds
Started Aug 07 06:07:55 PM PDT 24
Finished Aug 07 06:07:56 PM PDT 24
Peak memory 206972 kb
Host smart-aa9829af-5187-4dbf-a874-6437402645a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25454
82900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2545482900
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.718681451
Short name T1515
Test name
Test status
Simulation time 149425314 ps
CPU time 0.82 seconds
Started Aug 07 06:07:53 PM PDT 24
Finished Aug 07 06:07:54 PM PDT 24
Peak memory 206996 kb
Host smart-b0c32f7b-2189-414a-b49b-28f3e72f1a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71868
1451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.718681451
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2033546541
Short name T2020
Test name
Test status
Simulation time 152397332 ps
CPU time 0.85 seconds
Started Aug 07 06:07:50 PM PDT 24
Finished Aug 07 06:07:51 PM PDT 24
Peak memory 206972 kb
Host smart-3eb83db4-ecec-4c43-bdd3-b8b1a276fa3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20335
46541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2033546541
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.518756644
Short name T31
Test name
Test status
Simulation time 265638101 ps
CPU time 1.05 seconds
Started Aug 07 06:07:55 PM PDT 24
Finished Aug 07 06:07:56 PM PDT 24
Peak memory 206964 kb
Host smart-b1f1a266-80e1-4b61-bc31-3c63461efdfb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=518756644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.518756644
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1627813464
Short name T2260
Test name
Test status
Simulation time 162400119 ps
CPU time 0.84 seconds
Started Aug 07 06:07:50 PM PDT 24
Finished Aug 07 06:07:51 PM PDT 24
Peak memory 206928 kb
Host smart-8f394aec-2a34-4e4c-a611-53fab50b1081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16278
13464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1627813464
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.4054235751
Short name T875
Test name
Test status
Simulation time 38515354 ps
CPU time 0.67 seconds
Started Aug 07 06:07:51 PM PDT 24
Finished Aug 07 06:07:52 PM PDT 24
Peak memory 206912 kb
Host smart-36b0112a-2867-4713-acd8-6841af4257b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40542
35751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.4054235751
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2591245634
Short name T2794
Test name
Test status
Simulation time 21738808959 ps
CPU time 50.22 seconds
Started Aug 07 06:07:50 PM PDT 24
Finished Aug 07 06:08:40 PM PDT 24
Peak memory 215412 kb
Host smart-e6007dfb-8a5c-4e4d-869b-27acde81bfe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25912
45634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2591245634
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2251337147
Short name T2786
Test name
Test status
Simulation time 170163679 ps
CPU time 0.92 seconds
Started Aug 07 06:07:50 PM PDT 24
Finished Aug 07 06:07:52 PM PDT 24
Peak memory 206952 kb
Host smart-b262329f-1c9a-4d67-9518-3ba612e57b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22513
37147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2251337147
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.818900358
Short name T1016
Test name
Test status
Simulation time 262569228 ps
CPU time 1.03 seconds
Started Aug 07 06:07:54 PM PDT 24
Finished Aug 07 06:07:55 PM PDT 24
Peak memory 206848 kb
Host smart-59ba1c63-fe66-4ec4-b6f9-c602fea5e927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81890
0358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.818900358
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.128348303
Short name T519
Test name
Test status
Simulation time 222858229 ps
CPU time 0.93 seconds
Started Aug 07 06:07:51 PM PDT 24
Finished Aug 07 06:07:52 PM PDT 24
Peak memory 207000 kb
Host smart-f5007db7-66a3-4476-8841-88082320f688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12834
8303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.128348303
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2614096514
Short name T826
Test name
Test status
Simulation time 179781866 ps
CPU time 0.88 seconds
Started Aug 07 06:07:56 PM PDT 24
Finished Aug 07 06:07:57 PM PDT 24
Peak memory 206908 kb
Host smart-d9c16640-22cc-4f01-a7c4-d7849cb3e1c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26140
96514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2614096514
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3741058457
Short name T2072
Test name
Test status
Simulation time 198002796 ps
CPU time 0.87 seconds
Started Aug 07 06:07:58 PM PDT 24
Finished Aug 07 06:07:59 PM PDT 24
Peak memory 207044 kb
Host smart-0a6dc981-86c9-4dcb-b8cc-a6efd573bc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37410
58457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3741058457
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_rx_full.3011050080
Short name T1761
Test name
Test status
Simulation time 419968410 ps
CPU time 1.3 seconds
Started Aug 07 06:07:58 PM PDT 24
Finished Aug 07 06:08:00 PM PDT 24
Peak memory 206960 kb
Host smart-e51d8311-716e-4e0f-88f7-affe74ec8373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30110
50080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.3011050080
Directory /workspace/36.usbdev_rx_full/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.979181589
Short name T2017
Test name
Test status
Simulation time 150168817 ps
CPU time 0.92 seconds
Started Aug 07 06:07:57 PM PDT 24
Finished Aug 07 06:07:58 PM PDT 24
Peak memory 206984 kb
Host smart-e4a3552e-4eeb-49b9-a3ca-d84a6212173c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97918
1589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.979181589
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.584189569
Short name T1262
Test name
Test status
Simulation time 212983857 ps
CPU time 0.85 seconds
Started Aug 07 06:07:56 PM PDT 24
Finished Aug 07 06:07:57 PM PDT 24
Peak memory 206964 kb
Host smart-1fc2e835-085d-4480-bf43-99f6b0034918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58418
9569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.584189569
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3159360023
Short name T3010
Test name
Test status
Simulation time 189842577 ps
CPU time 0.97 seconds
Started Aug 07 06:07:56 PM PDT 24
Finished Aug 07 06:07:58 PM PDT 24
Peak memory 206968 kb
Host smart-08ae8ef2-bb2e-45de-bfce-f604f771c345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31593
60023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3159360023
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.3098208637
Short name T3052
Test name
Test status
Simulation time 1638781075 ps
CPU time 16.08 seconds
Started Aug 07 06:07:57 PM PDT 24
Finished Aug 07 06:08:13 PM PDT 24
Peak memory 216856 kb
Host smart-e4bcf088-f9e8-45de-b6ef-a8f812a30bdc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3098208637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.3098208637
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3178958062
Short name T984
Test name
Test status
Simulation time 194998721 ps
CPU time 0.88 seconds
Started Aug 07 06:08:03 PM PDT 24
Finished Aug 07 06:08:04 PM PDT 24
Peak memory 207000 kb
Host smart-2e574f23-6cca-4897-a03f-1e12e4adad7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31789
58062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3178958062
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.1309294297
Short name T2749
Test name
Test status
Simulation time 229124879 ps
CPU time 0.98 seconds
Started Aug 07 06:08:02 PM PDT 24
Finished Aug 07 06:08:04 PM PDT 24
Peak memory 206984 kb
Host smart-6fbff02c-9e71-4f2e-acb3-37b894090749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13092
94297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1309294297
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.2494559323
Short name T1526
Test name
Test status
Simulation time 842955081 ps
CPU time 2.03 seconds
Started Aug 07 06:08:05 PM PDT 24
Finished Aug 07 06:08:07 PM PDT 24
Peak memory 207104 kb
Host smart-01da1de5-ac7f-4b26-a712-db843e4cf3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24945
59323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.2494559323
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.2147072317
Short name T2658
Test name
Test status
Simulation time 2703699716 ps
CPU time 21.38 seconds
Started Aug 07 06:08:14 PM PDT 24
Finished Aug 07 06:08:35 PM PDT 24
Peak memory 217184 kb
Host smart-1223ed2f-734e-479c-aa5e-ed8c8afe2263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21470
72317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.2147072317
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.3720548439
Short name T1858
Test name
Test status
Simulation time 4286640371 ps
CPU time 37.71 seconds
Started Aug 07 06:07:38 PM PDT 24
Finished Aug 07 06:08:16 PM PDT 24
Peak memory 207308 kb
Host smart-b603282c-556c-4978-8a19-ed8cc2b92a2c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720548439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.3720548439
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3991673077
Short name T1835
Test name
Test status
Simulation time 35169369 ps
CPU time 0.67 seconds
Started Aug 07 06:08:42 PM PDT 24
Finished Aug 07 06:08:43 PM PDT 24
Peak memory 207000 kb
Host smart-ef0dde02-11eb-4c9e-bab4-61f45d857b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3991673077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3991673077
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2086772034
Short name T3083
Test name
Test status
Simulation time 5144539969 ps
CPU time 7 seconds
Started Aug 07 06:08:01 PM PDT 24
Finished Aug 07 06:08:08 PM PDT 24
Peak memory 215512 kb
Host smart-0d3c321f-4e0f-4b8e-87e1-aa355da599b1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086772034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.2086772034
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.534101537
Short name T1251
Test name
Test status
Simulation time 19554675874 ps
CPU time 21.03 seconds
Started Aug 07 06:08:02 PM PDT 24
Finished Aug 07 06:08:23 PM PDT 24
Peak memory 207300 kb
Host smart-994a59c8-cbae-4f43-bdc1-0b41257ad77a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=534101537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.534101537
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.4269179270
Short name T1104
Test name
Test status
Simulation time 157844604 ps
CPU time 0.86 seconds
Started Aug 07 06:08:04 PM PDT 24
Finished Aug 07 06:08:05 PM PDT 24
Peak memory 206984 kb
Host smart-14c7394d-bafe-47ea-bb04-69a0da750108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42691
79270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.4269179270
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.4148763210
Short name T74
Test name
Test status
Simulation time 183403253 ps
CPU time 0.95 seconds
Started Aug 07 06:08:01 PM PDT 24
Finished Aug 07 06:08:02 PM PDT 24
Peak memory 206996 kb
Host smart-0bf9ec34-b600-4a82-848c-fea35d2d2ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
63210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.4148763210
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2944044611
Short name T1156
Test name
Test status
Simulation time 523260365 ps
CPU time 1.81 seconds
Started Aug 07 06:08:06 PM PDT 24
Finished Aug 07 06:08:07 PM PDT 24
Peak memory 206904 kb
Host smart-1fcc749d-6398-410d-84a4-1bc70ef9f3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29440
44611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2944044611
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3703500224
Short name T1880
Test name
Test status
Simulation time 1230480939 ps
CPU time 3.07 seconds
Started Aug 07 06:08:00 PM PDT 24
Finished Aug 07 06:08:03 PM PDT 24
Peak memory 207164 kb
Host smart-2837ef34-63fd-4c1d-b678-f9506f515db4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3703500224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3703500224
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1271314304
Short name T1959
Test name
Test status
Simulation time 49190779127 ps
CPU time 78.29 seconds
Started Aug 07 06:08:12 PM PDT 24
Finished Aug 07 06:09:30 PM PDT 24
Peak memory 207324 kb
Host smart-8b41dd22-654c-496d-a72f-b093b98ada1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12713
14304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1271314304
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.2646793123
Short name T2587
Test name
Test status
Simulation time 1044594016 ps
CPU time 23.63 seconds
Started Aug 07 06:08:07 PM PDT 24
Finished Aug 07 06:08:31 PM PDT 24
Peak memory 207104 kb
Host smart-485c33e1-7da7-4614-ad99-bd42f255497e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646793123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.2646793123
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2569171668
Short name T2773
Test name
Test status
Simulation time 675570550 ps
CPU time 1.65 seconds
Started Aug 07 06:08:06 PM PDT 24
Finished Aug 07 06:08:08 PM PDT 24
Peak memory 206972 kb
Host smart-22a621fa-2d62-436f-9ef6-9ba7e81da8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25691
71668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2569171668
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3507753893
Short name T2276
Test name
Test status
Simulation time 166290264 ps
CPU time 0.83 seconds
Started Aug 07 06:08:09 PM PDT 24
Finished Aug 07 06:08:10 PM PDT 24
Peak memory 206968 kb
Host smart-c19d36b7-6cc8-47b4-94a9-a91b3c8d2632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35077
53893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3507753893
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3547626296
Short name T2114
Test name
Test status
Simulation time 51832716 ps
CPU time 0.75 seconds
Started Aug 07 06:08:12 PM PDT 24
Finished Aug 07 06:08:12 PM PDT 24
Peak memory 206948 kb
Host smart-40365eca-059b-40d8-ac2e-585c388aae5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35476
26296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3547626296
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.4001199399
Short name T717
Test name
Test status
Simulation time 671226041 ps
CPU time 2.08 seconds
Started Aug 07 06:08:08 PM PDT 24
Finished Aug 07 06:08:10 PM PDT 24
Peak memory 207244 kb
Host smart-d9484ed5-aa57-4148-86ae-adcf7c703389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40011
99399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.4001199399
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_types.575305795
Short name T371
Test name
Test status
Simulation time 498612660 ps
CPU time 1.49 seconds
Started Aug 07 06:08:15 PM PDT 24
Finished Aug 07 06:08:17 PM PDT 24
Peak memory 206860 kb
Host smart-30688ae4-ebcc-4673-9884-c5208c74c6c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=575305795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.575305795
Directory /workspace/37.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.186275082
Short name T2592
Test name
Test status
Simulation time 287211281 ps
CPU time 1.9 seconds
Started Aug 07 06:08:13 PM PDT 24
Finished Aug 07 06:08:15 PM PDT 24
Peak memory 207044 kb
Host smart-5e79041c-a432-43ed-aad6-d63df347afc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18627
5082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.186275082
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2894083489
Short name T1243
Test name
Test status
Simulation time 222413478 ps
CPU time 0.99 seconds
Started Aug 07 06:08:13 PM PDT 24
Finished Aug 07 06:08:14 PM PDT 24
Peak memory 207184 kb
Host smart-480b138e-0528-4e73-aa9c-c7d53a8a390d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2894083489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2894083489
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.4105495597
Short name T2447
Test name
Test status
Simulation time 148648871 ps
CPU time 0.86 seconds
Started Aug 07 06:08:13 PM PDT 24
Finished Aug 07 06:08:14 PM PDT 24
Peak memory 206964 kb
Host smart-7384b0da-6fb1-402d-a1e1-5b11fbfae46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41054
95597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.4105495597
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.316355320
Short name T569
Test name
Test status
Simulation time 168899557 ps
CPU time 0.87 seconds
Started Aug 07 06:08:21 PM PDT 24
Finished Aug 07 06:08:22 PM PDT 24
Peak memory 206968 kb
Host smart-3fba521d-7a48-4ac2-b6a7-d3a46feab849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31635
5320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.316355320
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.2443568961
Short name T2544
Test name
Test status
Simulation time 3989741746 ps
CPU time 40.82 seconds
Started Aug 07 06:08:12 PM PDT 24
Finished Aug 07 06:08:53 PM PDT 24
Peak memory 217300 kb
Host smart-70b0fc0e-b5da-4b31-92ea-596e96b8c23f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2443568961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.2443568961
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.3690695571
Short name T2010
Test name
Test status
Simulation time 7562529469 ps
CPU time 51.96 seconds
Started Aug 07 06:08:19 PM PDT 24
Finished Aug 07 06:09:11 PM PDT 24
Peak memory 207312 kb
Host smart-25f7cf0c-a621-4e27-bf51-248ef69aa6f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3690695571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.3690695571
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.504541489
Short name T1440
Test name
Test status
Simulation time 200873053 ps
CPU time 0.92 seconds
Started Aug 07 06:08:18 PM PDT 24
Finished Aug 07 06:08:19 PM PDT 24
Peak memory 206968 kb
Host smart-94eb7189-6b26-414c-a690-8e06821cc84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50454
1489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.504541489
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.314237411
Short name T2539
Test name
Test status
Simulation time 25586232585 ps
CPU time 29.37 seconds
Started Aug 07 06:08:20 PM PDT 24
Finished Aug 07 06:08:50 PM PDT 24
Peak memory 215484 kb
Host smart-3d046df9-e91b-4e9f-89dc-a53292bdcd57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31423
7411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.314237411
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.6341467
Short name T1047
Test name
Test status
Simulation time 5111773569 ps
CPU time 8.25 seconds
Started Aug 07 06:08:21 PM PDT 24
Finished Aug 07 06:08:30 PM PDT 24
Peak memory 216292 kb
Host smart-198642e4-bb2d-40d9-970b-acac216c64ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63414
67 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.6341467
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.1939754515
Short name T589
Test name
Test status
Simulation time 3057114823 ps
CPU time 82.28 seconds
Started Aug 07 06:08:18 PM PDT 24
Finished Aug 07 06:09:40 PM PDT 24
Peak memory 223696 kb
Host smart-30a6bd97-0b65-4f71-bf1f-77ba4e3ff5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19397
54515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1939754515
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3139532540
Short name T2178
Test name
Test status
Simulation time 2699273432 ps
CPU time 20.55 seconds
Started Aug 07 06:08:51 PM PDT 24
Finished Aug 07 06:09:12 PM PDT 24
Peak memory 215496 kb
Host smart-2fa40637-ed26-4b30-935c-c9e8cf9c56be
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3139532540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3139532540
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.516915994
Short name T2438
Test name
Test status
Simulation time 237419238 ps
CPU time 1.01 seconds
Started Aug 07 06:08:26 PM PDT 24
Finished Aug 07 06:08:27 PM PDT 24
Peak memory 207000 kb
Host smart-281fa556-1102-4bbb-b39b-d8b5148529af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=516915994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.516915994
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1505924524
Short name T2321
Test name
Test status
Simulation time 205655874 ps
CPU time 0.96 seconds
Started Aug 07 06:08:27 PM PDT 24
Finished Aug 07 06:08:28 PM PDT 24
Peak memory 207036 kb
Host smart-22bcd41f-13a7-4ed9-ab25-d5d8fe6b7eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15059
24524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1505924524
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.242040478
Short name T3047
Test name
Test status
Simulation time 2702740491 ps
CPU time 79.82 seconds
Started Aug 07 06:08:26 PM PDT 24
Finished Aug 07 06:09:46 PM PDT 24
Peak memory 215480 kb
Host smart-3718cd5e-a9e3-41ce-81c0-2e2322d77c8a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=242040478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.242040478
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1585901579
Short name T514
Test name
Test status
Simulation time 185614432 ps
CPU time 0.94 seconds
Started Aug 07 06:08:27 PM PDT 24
Finished Aug 07 06:08:28 PM PDT 24
Peak memory 207032 kb
Host smart-c74870c9-0870-4b26-8055-0c4f6b40af71
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1585901579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1585901579
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2876895395
Short name T2344
Test name
Test status
Simulation time 169885675 ps
CPU time 0.89 seconds
Started Aug 07 06:08:25 PM PDT 24
Finished Aug 07 06:08:26 PM PDT 24
Peak memory 206968 kb
Host smart-37f013dd-6348-4d7a-9aaf-5a3547d8635c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28768
95395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2876895395
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2666662587
Short name T152
Test name
Test status
Simulation time 176877415 ps
CPU time 0.88 seconds
Started Aug 07 06:08:25 PM PDT 24
Finished Aug 07 06:08:26 PM PDT 24
Peak memory 206964 kb
Host smart-289ea659-be46-41f4-b601-a3ce4e7f21cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26666
62587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2666662587
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3129837160
Short name T2603
Test name
Test status
Simulation time 162304228 ps
CPU time 0.89 seconds
Started Aug 07 06:08:38 PM PDT 24
Finished Aug 07 06:08:39 PM PDT 24
Peak memory 206892 kb
Host smart-200818be-a28f-4868-8fee-6e7d3e082366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31298
37160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3129837160
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.577811825
Short name T2362
Test name
Test status
Simulation time 167965474 ps
CPU time 0.9 seconds
Started Aug 07 06:08:41 PM PDT 24
Finished Aug 07 06:08:42 PM PDT 24
Peak memory 206888 kb
Host smart-7062596c-c547-404f-bc06-97f61bc9856f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57781
1825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.577811825
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.73919478
Short name T2467
Test name
Test status
Simulation time 182557803 ps
CPU time 0.95 seconds
Started Aug 07 06:08:39 PM PDT 24
Finished Aug 07 06:08:40 PM PDT 24
Peak memory 206960 kb
Host smart-417b0714-0a4f-40cf-a508-197b53fc913b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73919
478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.73919478
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1698661842
Short name T168
Test name
Test status
Simulation time 191200701 ps
CPU time 0.9 seconds
Started Aug 07 06:08:42 PM PDT 24
Finished Aug 07 06:08:43 PM PDT 24
Peak memory 206908 kb
Host smart-68c2428c-0f4b-41b4-9cb3-df0cb95b6891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16986
61842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1698661842
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.2331944356
Short name T818
Test name
Test status
Simulation time 226669512 ps
CPU time 0.99 seconds
Started Aug 07 06:08:37 PM PDT 24
Finished Aug 07 06:08:38 PM PDT 24
Peak memory 206944 kb
Host smart-5ed7a7a7-f3b7-4173-a56a-431100c80c37
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2331944356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.2331944356
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1941624928
Short name T2504
Test name
Test status
Simulation time 164358256 ps
CPU time 0.85 seconds
Started Aug 07 06:08:43 PM PDT 24
Finished Aug 07 06:08:44 PM PDT 24
Peak memory 206960 kb
Host smart-0f6105ca-9154-4071-82a8-756a694a7a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19416
24928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1941624928
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2165205422
Short name T1246
Test name
Test status
Simulation time 39936976 ps
CPU time 0.68 seconds
Started Aug 07 06:08:41 PM PDT 24
Finished Aug 07 06:08:42 PM PDT 24
Peak memory 206912 kb
Host smart-eaa42794-9a62-444f-aa7b-1f2c31410072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21652
05422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2165205422
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.318186212
Short name T949
Test name
Test status
Simulation time 23079508492 ps
CPU time 57.56 seconds
Started Aug 07 06:08:45 PM PDT 24
Finished Aug 07 06:09:43 PM PDT 24
Peak memory 215488 kb
Host smart-1efa4339-b463-471e-938b-d309dece4c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31818
6212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.318186212
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.40396903
Short name T1274
Test name
Test status
Simulation time 195783982 ps
CPU time 0.95 seconds
Started Aug 07 06:08:43 PM PDT 24
Finished Aug 07 06:08:44 PM PDT 24
Peak memory 206972 kb
Host smart-7a23b1a1-ad15-4628-b54d-ecf4ff043e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.40396903
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2571106402
Short name T2810
Test name
Test status
Simulation time 243891751 ps
CPU time 1.01 seconds
Started Aug 07 06:08:43 PM PDT 24
Finished Aug 07 06:08:44 PM PDT 24
Peak memory 206944 kb
Host smart-baa96e72-6056-4c86-89af-7f8e2ea9a49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25711
06402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2571106402
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2905530359
Short name T972
Test name
Test status
Simulation time 179548214 ps
CPU time 0.86 seconds
Started Aug 07 06:08:44 PM PDT 24
Finished Aug 07 06:08:45 PM PDT 24
Peak memory 206992 kb
Host smart-6cebd761-e2e0-424a-9b4d-bdc62c7704e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29055
30359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2905530359
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.1981590921
Short name T729
Test name
Test status
Simulation time 186018077 ps
CPU time 0.94 seconds
Started Aug 07 06:08:43 PM PDT 24
Finished Aug 07 06:08:44 PM PDT 24
Peak memory 206992 kb
Host smart-9cf83f14-f3eb-44c4-a031-0f54fde36f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19815
90921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.1981590921
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3169077326
Short name T72
Test name
Test status
Simulation time 150601328 ps
CPU time 0.85 seconds
Started Aug 07 06:08:43 PM PDT 24
Finished Aug 07 06:08:44 PM PDT 24
Peak memory 206960 kb
Host smart-04101275-f1ba-479d-aec4-336ba93d4c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31690
77326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3169077326
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_rx_full.41263389
Short name T1645
Test name
Test status
Simulation time 298178474 ps
CPU time 1.19 seconds
Started Aug 07 06:08:42 PM PDT 24
Finished Aug 07 06:08:44 PM PDT 24
Peak memory 206904 kb
Host smart-7cb870cc-c699-4519-bafc-acf94ccd74f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41263
389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.41263389
Directory /workspace/37.usbdev_rx_full/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.4202052641
Short name T481
Test name
Test status
Simulation time 153432385 ps
CPU time 0.84 seconds
Started Aug 07 06:08:42 PM PDT 24
Finished Aug 07 06:08:43 PM PDT 24
Peak memory 206968 kb
Host smart-6fb3c75d-ca5b-4105-affd-d801b5b675dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42020
52641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.4202052641
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1781797012
Short name T2376
Test name
Test status
Simulation time 197244136 ps
CPU time 0.9 seconds
Started Aug 07 06:08:46 PM PDT 24
Finished Aug 07 06:08:47 PM PDT 24
Peak memory 207008 kb
Host smart-a7d9e8e2-c86c-4966-902d-b9acccd2790d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17817
97012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1781797012
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1565535270
Short name T2917
Test name
Test status
Simulation time 231139259 ps
CPU time 1.06 seconds
Started Aug 07 06:08:40 PM PDT 24
Finished Aug 07 06:08:42 PM PDT 24
Peak memory 206904 kb
Host smart-153e940b-c0a5-46ea-bf53-6d809169c6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15655
35270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1565535270
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.800868329
Short name T2449
Test name
Test status
Simulation time 3303380508 ps
CPU time 91.85 seconds
Started Aug 07 06:08:39 PM PDT 24
Finished Aug 07 06:10:11 PM PDT 24
Peak memory 217280 kb
Host smart-4d06d511-f57a-4e8a-8559-e8e749657ed9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=800868329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.800868329
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.790785106
Short name T915
Test name
Test status
Simulation time 183945552 ps
CPU time 0.92 seconds
Started Aug 07 06:08:39 PM PDT 24
Finished Aug 07 06:08:40 PM PDT 24
Peak memory 206992 kb
Host smart-d625cf61-712b-48f3-b500-88f5ea03b584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79078
5106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.790785106
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3161566466
Short name T881
Test name
Test status
Simulation time 192232930 ps
CPU time 0.91 seconds
Started Aug 07 06:08:43 PM PDT 24
Finished Aug 07 06:08:44 PM PDT 24
Peak memory 206992 kb
Host smart-2e38b857-8af1-4420-8340-10b7577b4d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31615
66466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3161566466
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.4182216028
Short name T883
Test name
Test status
Simulation time 974981063 ps
CPU time 2.73 seconds
Started Aug 07 06:08:47 PM PDT 24
Finished Aug 07 06:08:49 PM PDT 24
Peak memory 207160 kb
Host smart-bf242970-7ecf-46db-b90d-2c56fd770626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41822
16028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.4182216028
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2847076720
Short name T2875
Test name
Test status
Simulation time 3034387682 ps
CPU time 83.95 seconds
Started Aug 07 06:08:38 PM PDT 24
Finished Aug 07 06:10:02 PM PDT 24
Peak memory 215452 kb
Host smart-f5374c63-52e8-497d-8bf4-c0e720e17513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28470
76720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2847076720
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.38888407
Short name T2256
Test name
Test status
Simulation time 7053876393 ps
CPU time 45.9 seconds
Started Aug 07 06:08:12 PM PDT 24
Finished Aug 07 06:08:58 PM PDT 24
Peak memory 207164 kb
Host smart-3a30c511-4c96-41f5-bfa3-b937c142c489
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38888407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_host_
handshake.38888407
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.1329301825
Short name T687
Test name
Test status
Simulation time 40949977 ps
CPU time 0.69 seconds
Started Aug 07 06:09:20 PM PDT 24
Finished Aug 07 06:09:21 PM PDT 24
Peak memory 207072 kb
Host smart-94c2fa3b-68ea-414d-954d-e73b92460799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1329301825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1329301825
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.319988604
Short name T895
Test name
Test status
Simulation time 5845528281 ps
CPU time 7.52 seconds
Started Aug 07 06:08:46 PM PDT 24
Finished Aug 07 06:08:54 PM PDT 24
Peak memory 215476 kb
Host smart-b1074e6b-3597-4c10-987c-38a069d931c7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319988604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ao
n_wake_disconnect.319988604
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.2181443706
Short name T1015
Test name
Test status
Simulation time 18415498293 ps
CPU time 27.15 seconds
Started Aug 07 06:08:44 PM PDT 24
Finished Aug 07 06:09:11 PM PDT 24
Peak memory 207240 kb
Host smart-3460f214-ddf3-49a9-9485-37ba88af9363
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181443706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.2181443706
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.874121733
Short name T2583
Test name
Test status
Simulation time 25916012739 ps
CPU time 32.02 seconds
Started Aug 07 06:08:43 PM PDT 24
Finished Aug 07 06:09:15 PM PDT 24
Peak memory 215460 kb
Host smart-42f356a2-bec4-4386-8c09-cd846d5d2156
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874121733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ao
n_wake_resume.874121733
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2555008098
Short name T1204
Test name
Test status
Simulation time 167064532 ps
CPU time 0.87 seconds
Started Aug 07 06:08:50 PM PDT 24
Finished Aug 07 06:08:51 PM PDT 24
Peak memory 206892 kb
Host smart-f0a4addb-d204-4744-974b-ac2e173179cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25550
08098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2555008098
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2566913491
Short name T2692
Test name
Test status
Simulation time 144090164 ps
CPU time 0.84 seconds
Started Aug 07 06:08:48 PM PDT 24
Finished Aug 07 06:08:49 PM PDT 24
Peak memory 206996 kb
Host smart-e04ca026-786f-4077-bb09-16ef89a71f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25669
13491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2566913491
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.394830243
Short name T522
Test name
Test status
Simulation time 222030184 ps
CPU time 1.05 seconds
Started Aug 07 06:08:48 PM PDT 24
Finished Aug 07 06:08:49 PM PDT 24
Peak memory 206996 kb
Host smart-5c48f015-f16c-45c5-a04c-da5b946084e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39483
0243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.394830243
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.193541414
Short name T56
Test name
Test status
Simulation time 469280888 ps
CPU time 1.61 seconds
Started Aug 07 06:08:51 PM PDT 24
Finished Aug 07 06:08:53 PM PDT 24
Peak memory 206920 kb
Host smart-32bcfba3-5684-4ab2-946c-8476a0f1123f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=193541414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.193541414
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3092720012
Short name T1743
Test name
Test status
Simulation time 20089850221 ps
CPU time 38.39 seconds
Started Aug 07 06:08:46 PM PDT 24
Finished Aug 07 06:09:25 PM PDT 24
Peak memory 207256 kb
Host smart-949c1a4e-96aa-4ef1-821c-e918e733b8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30927
20012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3092720012
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.3101748959
Short name T2514
Test name
Test status
Simulation time 846080758 ps
CPU time 5.26 seconds
Started Aug 07 06:08:46 PM PDT 24
Finished Aug 07 06:08:51 PM PDT 24
Peak memory 207204 kb
Host smart-4f54983c-f4f9-44c4-83ed-b20a2f24f95a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101748959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.3101748959
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.533525917
Short name T1705
Test name
Test status
Simulation time 795558973 ps
CPU time 1.86 seconds
Started Aug 07 06:08:51 PM PDT 24
Finished Aug 07 06:08:53 PM PDT 24
Peak memory 206888 kb
Host smart-db0e6a23-72ff-4af4-b0e8-39804495e26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53352
5917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.533525917
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2258673693
Short name T1933
Test name
Test status
Simulation time 163482098 ps
CPU time 0.88 seconds
Started Aug 07 06:08:49 PM PDT 24
Finished Aug 07 06:08:50 PM PDT 24
Peak memory 206956 kb
Host smart-77224dec-9fd1-467e-9a20-d0c2545a7378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22586
73693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2258673693
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2981262682
Short name T538
Test name
Test status
Simulation time 48729907 ps
CPU time 0.74 seconds
Started Aug 07 06:08:50 PM PDT 24
Finished Aug 07 06:08:51 PM PDT 24
Peak memory 206900 kb
Host smart-f2f84bfb-ad76-4601-a139-3633be7a57af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29812
62682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2981262682
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3371623567
Short name T2769
Test name
Test status
Simulation time 830709431 ps
CPU time 2.24 seconds
Started Aug 07 06:08:48 PM PDT 24
Finished Aug 07 06:08:50 PM PDT 24
Peak memory 207176 kb
Host smart-f87796cf-fdbf-4829-95d2-bf281e0ae7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33716
23567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3371623567
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1989650759
Short name T942
Test name
Test status
Simulation time 211980131 ps
CPU time 1.86 seconds
Started Aug 07 06:08:55 PM PDT 24
Finished Aug 07 06:08:56 PM PDT 24
Peak memory 207136 kb
Host smart-b65f89d6-c896-430c-9909-9d03212835d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19896
50759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1989650759
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.726259079
Short name T2464
Test name
Test status
Simulation time 197198217 ps
CPU time 1.03 seconds
Started Aug 07 06:08:55 PM PDT 24
Finished Aug 07 06:08:56 PM PDT 24
Peak memory 207156 kb
Host smart-55274939-e92e-4808-99d8-260e3bebd07b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=726259079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.726259079
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1552450403
Short name T900
Test name
Test status
Simulation time 152816371 ps
CPU time 0.82 seconds
Started Aug 07 06:08:52 PM PDT 24
Finished Aug 07 06:08:53 PM PDT 24
Peak memory 206876 kb
Host smart-afc08134-810f-4fa8-b6c2-5e6c6bec7bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15524
50403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1552450403
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1970167733
Short name T1233
Test name
Test status
Simulation time 223355718 ps
CPU time 0.99 seconds
Started Aug 07 06:08:55 PM PDT 24
Finished Aug 07 06:08:56 PM PDT 24
Peak memory 206984 kb
Host smart-9fca781c-894c-44a6-83b2-ae18b94ad8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19701
67733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1970167733
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.1846142423
Short name T1922
Test name
Test status
Simulation time 4053384073 ps
CPU time 116.78 seconds
Started Aug 07 06:08:52 PM PDT 24
Finished Aug 07 06:10:49 PM PDT 24
Peak memory 215444 kb
Host smart-689f1ba5-59b1-40a7-8ca4-ee90baa69a02
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1846142423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.1846142423
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.2949380262
Short name T1154
Test name
Test status
Simulation time 13705743770 ps
CPU time 99.21 seconds
Started Aug 07 06:08:50 PM PDT 24
Finished Aug 07 06:10:30 PM PDT 24
Peak memory 207236 kb
Host smart-2a1e811a-4bb3-4276-b3c9-c1a139a7bb2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2949380262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.2949380262
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3303824392
Short name T1137
Test name
Test status
Simulation time 240760699 ps
CPU time 0.97 seconds
Started Aug 07 06:09:00 PM PDT 24
Finished Aug 07 06:09:01 PM PDT 24
Peak memory 206884 kb
Host smart-ab132972-9323-493f-8720-8722b1771a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33038
24392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3303824392
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.94744351
Short name T682
Test name
Test status
Simulation time 29774147333 ps
CPU time 48.41 seconds
Started Aug 07 06:09:00 PM PDT 24
Finished Aug 07 06:09:49 PM PDT 24
Peak memory 207152 kb
Host smart-3d282a8d-5865-40c6-8925-a963d3386be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94744
351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.94744351
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.170666292
Short name T1321
Test name
Test status
Simulation time 4295886297 ps
CPU time 6.43 seconds
Started Aug 07 06:08:59 PM PDT 24
Finished Aug 07 06:09:06 PM PDT 24
Peak memory 215440 kb
Host smart-dabc8726-a54e-4d26-9e84-587b70a9298c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17066
6292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.170666292
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.955937843
Short name T862
Test name
Test status
Simulation time 3320363450 ps
CPU time 94.53 seconds
Started Aug 07 06:08:58 PM PDT 24
Finished Aug 07 06:10:33 PM PDT 24
Peak memory 223672 kb
Host smart-0c4a1604-65f9-4705-9795-b14761a2edd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95593
7843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.955937843
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2986163557
Short name T3102
Test name
Test status
Simulation time 3343735044 ps
CPU time 94.89 seconds
Started Aug 07 06:09:00 PM PDT 24
Finished Aug 07 06:10:35 PM PDT 24
Peak memory 216820 kb
Host smart-8cf46e4c-23be-47c4-a9dd-02aa6ac12ceb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2986163557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2986163557
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.971052150
Short name T1629
Test name
Test status
Simulation time 251937899 ps
CPU time 0.99 seconds
Started Aug 07 06:08:57 PM PDT 24
Finished Aug 07 06:08:58 PM PDT 24
Peak memory 207020 kb
Host smart-62cf482e-818c-47ff-a2c9-0a0da3c23e9f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=971052150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.971052150
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1762888553
Short name T501
Test name
Test status
Simulation time 193448575 ps
CPU time 0.96 seconds
Started Aug 07 06:09:02 PM PDT 24
Finished Aug 07 06:09:03 PM PDT 24
Peak memory 207004 kb
Host smart-8a22631d-3c6d-41ec-ac7e-badfb3c9b78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17628
88553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1762888553
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.661392287
Short name T1741
Test name
Test status
Simulation time 2254747035 ps
CPU time 22.25 seconds
Started Aug 07 06:09:01 PM PDT 24
Finished Aug 07 06:09:24 PM PDT 24
Peak memory 216676 kb
Host smart-d98a23a7-1f03-4f89-9951-0fc0c87f3157
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=661392287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.661392287
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.2240060626
Short name T1353
Test name
Test status
Simulation time 161447398 ps
CPU time 0.89 seconds
Started Aug 07 06:09:06 PM PDT 24
Finished Aug 07 06:09:07 PM PDT 24
Peak memory 206912 kb
Host smart-7ae41797-4075-47be-9d97-4cde06a3a98b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2240060626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.2240060626
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.927468150
Short name T814
Test name
Test status
Simulation time 180406146 ps
CPU time 0.94 seconds
Started Aug 07 06:09:05 PM PDT 24
Finished Aug 07 06:09:06 PM PDT 24
Peak memory 206920 kb
Host smart-d45baae6-2e66-4c71-97d2-8ce4ccac1834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92746
8150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.927468150
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.315042307
Short name T1171
Test name
Test status
Simulation time 154643902 ps
CPU time 0.86 seconds
Started Aug 07 06:09:01 PM PDT 24
Finished Aug 07 06:09:02 PM PDT 24
Peak memory 206956 kb
Host smart-295f0c44-66e6-4940-ab93-7bab42b20f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31504
2307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.315042307
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.557872416
Short name T1905
Test name
Test status
Simulation time 185531174 ps
CPU time 0.9 seconds
Started Aug 07 06:09:02 PM PDT 24
Finished Aug 07 06:09:03 PM PDT 24
Peak memory 206956 kb
Host smart-542852bb-d50f-469e-9d15-04f873f5b6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55787
2416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.557872416
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3277324291
Short name T1324
Test name
Test status
Simulation time 218716664 ps
CPU time 0.89 seconds
Started Aug 07 06:09:12 PM PDT 24
Finished Aug 07 06:09:13 PM PDT 24
Peak memory 206900 kb
Host smart-95ee97fd-ad54-4f95-a596-9d6f50de3b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32773
24291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3277324291
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.690558509
Short name T2633
Test name
Test status
Simulation time 163294407 ps
CPU time 0.87 seconds
Started Aug 07 06:09:14 PM PDT 24
Finished Aug 07 06:09:14 PM PDT 24
Peak memory 206904 kb
Host smart-f8da3aa7-fe27-47b1-a116-208dc03770fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69055
8509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.690558509
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.1177611718
Short name T1315
Test name
Test status
Simulation time 222132342 ps
CPU time 1 seconds
Started Aug 07 06:09:14 PM PDT 24
Finished Aug 07 06:09:15 PM PDT 24
Peak memory 206976 kb
Host smart-3413c5d5-a89e-48d9-adba-cd19310609e0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1177611718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.1177611718
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.4180622616
Short name T1838
Test name
Test status
Simulation time 148992395 ps
CPU time 0.81 seconds
Started Aug 07 06:09:12 PM PDT 24
Finished Aug 07 06:09:13 PM PDT 24
Peak memory 206932 kb
Host smart-8b906022-eb76-4b8a-8d56-63f20d09afff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41806
22616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.4180622616
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3625853171
Short name T1610
Test name
Test status
Simulation time 97500765 ps
CPU time 0.79 seconds
Started Aug 07 06:09:22 PM PDT 24
Finished Aug 07 06:09:23 PM PDT 24
Peak memory 206872 kb
Host smart-d8bb8595-fae3-4c9c-82ff-a3e1a88851b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36258
53171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3625853171
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.3850931612
Short name T295
Test name
Test status
Simulation time 11538978231 ps
CPU time 29.63 seconds
Started Aug 07 06:09:23 PM PDT 24
Finished Aug 07 06:09:52 PM PDT 24
Peak memory 215492 kb
Host smart-6cc6c563-2667-4642-8203-df7cffd09bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38509
31612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.3850931612
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3968845772
Short name T2690
Test name
Test status
Simulation time 194352542 ps
CPU time 0.91 seconds
Started Aug 07 06:09:23 PM PDT 24
Finished Aug 07 06:09:24 PM PDT 24
Peak memory 206976 kb
Host smart-2b6673a2-8516-4565-bf07-53253d77f179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39688
45772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3968845772
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3957109680
Short name T617
Test name
Test status
Simulation time 224225052 ps
CPU time 0.93 seconds
Started Aug 07 06:09:20 PM PDT 24
Finished Aug 07 06:09:21 PM PDT 24
Peak memory 206896 kb
Host smart-06c43c22-0d75-4a03-b7e4-151a1c4d40e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39571
09680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3957109680
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2408525815
Short name T2472
Test name
Test status
Simulation time 192311489 ps
CPU time 0.87 seconds
Started Aug 07 06:09:19 PM PDT 24
Finished Aug 07 06:09:20 PM PDT 24
Peak memory 207036 kb
Host smart-d00447fa-199c-4a18-958c-ef800075f891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24085
25815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2408525815
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3710930875
Short name T1524
Test name
Test status
Simulation time 225133738 ps
CPU time 0.99 seconds
Started Aug 07 06:09:21 PM PDT 24
Finished Aug 07 06:09:22 PM PDT 24
Peak memory 206904 kb
Host smart-dde5f341-6788-44c9-8eaf-765da3b2ee05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37109
30875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3710930875
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3922698871
Short name T1256
Test name
Test status
Simulation time 190259157 ps
CPU time 0.91 seconds
Started Aug 07 06:09:23 PM PDT 24
Finished Aug 07 06:09:24 PM PDT 24
Peak memory 206884 kb
Host smart-8dc3b90c-794c-4de8-9036-0d797dd46a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39226
98871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3922698871
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3180192142
Short name T2005
Test name
Test status
Simulation time 161132617 ps
CPU time 0.85 seconds
Started Aug 07 06:09:21 PM PDT 24
Finished Aug 07 06:09:22 PM PDT 24
Peak memory 206956 kb
Host smart-55d8d85b-87cd-4840-ab3e-be2ab982e8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31801
92142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3180192142
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1928494254
Short name T2944
Test name
Test status
Simulation time 155422591 ps
CPU time 0.86 seconds
Started Aug 07 06:09:22 PM PDT 24
Finished Aug 07 06:09:23 PM PDT 24
Peak memory 206952 kb
Host smart-500557a5-75fc-4983-9a51-e756a25c1285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19284
94254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1928494254
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.261235606
Short name T916
Test name
Test status
Simulation time 218689255 ps
CPU time 1.02 seconds
Started Aug 07 06:09:20 PM PDT 24
Finished Aug 07 06:09:21 PM PDT 24
Peak memory 206928 kb
Host smart-efa7721c-780d-4e0f-a298-941af7458f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26123
5606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.261235606
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.2304855202
Short name T1717
Test name
Test status
Simulation time 2640670810 ps
CPU time 71.74 seconds
Started Aug 07 06:09:19 PM PDT 24
Finished Aug 07 06:10:31 PM PDT 24
Peak memory 215448 kb
Host smart-fc967633-ec90-4c54-95e6-606f18ee84a3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2304855202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.2304855202
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3092025112
Short name T1950
Test name
Test status
Simulation time 164860686 ps
CPU time 0.85 seconds
Started Aug 07 06:09:23 PM PDT 24
Finished Aug 07 06:09:24 PM PDT 24
Peak memory 206992 kb
Host smart-2aa1b96c-423c-4e13-af5d-28f37680be1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30920
25112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3092025112
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.886282765
Short name T1435
Test name
Test status
Simulation time 183790591 ps
CPU time 0.92 seconds
Started Aug 07 06:09:19 PM PDT 24
Finished Aug 07 06:09:20 PM PDT 24
Peak memory 206988 kb
Host smart-75bb29ce-bf08-4b71-9cba-c53874cde729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88628
2765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.886282765
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.3030174736
Short name T1456
Test name
Test status
Simulation time 545101359 ps
CPU time 1.57 seconds
Started Aug 07 06:09:23 PM PDT 24
Finished Aug 07 06:09:25 PM PDT 24
Peak memory 206972 kb
Host smart-66ff4562-8a7f-4248-8740-e648149ca57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30301
74736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.3030174736
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.976167666
Short name T523
Test name
Test status
Simulation time 2205013776 ps
CPU time 16.47 seconds
Started Aug 07 06:09:20 PM PDT 24
Finished Aug 07 06:09:36 PM PDT 24
Peak memory 207276 kb
Host smart-d86ccfde-4f82-4247-803c-ed7cd4f8f3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97616
7666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.976167666
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.987647439
Short name T2231
Test name
Test status
Simulation time 3367287991 ps
CPU time 28.02 seconds
Started Aug 07 06:08:48 PM PDT 24
Finished Aug 07 06:09:16 PM PDT 24
Peak memory 207380 kb
Host smart-381c8b88-4d04-4c0d-a92b-c3feb9e743e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987647439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_host
_handshake.987647439
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.3686202
Short name T2632
Test name
Test status
Simulation time 54469843 ps
CPU time 0.69 seconds
Started Aug 07 06:10:08 PM PDT 24
Finished Aug 07 06:10:08 PM PDT 24
Peak memory 207080 kb
Host smart-9526d28c-c3d1-4407-8128-96884b4bea5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3686202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.3686202
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3104059
Short name T2974
Test name
Test status
Simulation time 5028714876 ps
CPU time 6.98 seconds
Started Aug 07 06:09:18 PM PDT 24
Finished Aug 07 06:09:25 PM PDT 24
Peak memory 215440 kb
Host smart-6da68856-11e6-4891-a905-453a6c12fe1c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us
bdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_
wake_disconnect.3104059
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1668415782
Short name T896
Test name
Test status
Simulation time 19896292433 ps
CPU time 22.44 seconds
Started Aug 07 06:09:22 PM PDT 24
Finished Aug 07 06:09:44 PM PDT 24
Peak memory 207292 kb
Host smart-65a60cff-72d2-4bfb-804e-377195df32bc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668415782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1668415782
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.826119643
Short name T1525
Test name
Test status
Simulation time 26224966554 ps
CPU time 32.7 seconds
Started Aug 07 06:09:28 PM PDT 24
Finished Aug 07 06:10:01 PM PDT 24
Peak memory 215416 kb
Host smart-15d736c8-760d-4b85-9d3b-9b6c55b8ecdb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826119643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ao
n_wake_resume.826119643
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.240738284
Short name T778
Test name
Test status
Simulation time 153085128 ps
CPU time 0.9 seconds
Started Aug 07 06:09:29 PM PDT 24
Finished Aug 07 06:09:30 PM PDT 24
Peak memory 207004 kb
Host smart-cc2916ca-5a23-409a-9760-42b0f01725f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24073
8284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.240738284
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.3381613675
Short name T2167
Test name
Test status
Simulation time 150557024 ps
CPU time 0.87 seconds
Started Aug 07 06:09:31 PM PDT 24
Finished Aug 07 06:09:32 PM PDT 24
Peak memory 206976 kb
Host smart-a63407e8-3cfb-429b-85b6-8f79dd87511d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33816
13675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3381613675
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.3731638906
Short name T2040
Test name
Test status
Simulation time 405938081 ps
CPU time 1.33 seconds
Started Aug 07 06:09:28 PM PDT 24
Finished Aug 07 06:09:30 PM PDT 24
Peak memory 206908 kb
Host smart-25eef4b6-c9c9-46e1-a1f1-e3a29342fffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37316
38906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.3731638906
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1854057541
Short name T670
Test name
Test status
Simulation time 1116326141 ps
CPU time 3.23 seconds
Started Aug 07 06:09:31 PM PDT 24
Finished Aug 07 06:09:34 PM PDT 24
Peak memory 207084 kb
Host smart-4cad0776-ff27-41d4-a3b8-48d1028074bf
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1854057541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1854057541
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.4263916316
Short name T1374
Test name
Test status
Simulation time 46687707162 ps
CPU time 73.27 seconds
Started Aug 07 06:09:28 PM PDT 24
Finished Aug 07 06:10:42 PM PDT 24
Peak memory 207276 kb
Host smart-97a49cd5-8cae-4482-9616-de49b0e710ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42639
16316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.4263916316
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.2146430934
Short name T2062
Test name
Test status
Simulation time 435823612 ps
CPU time 7.94 seconds
Started Aug 07 06:09:30 PM PDT 24
Finished Aug 07 06:09:38 PM PDT 24
Peak memory 207148 kb
Host smart-4b23623a-78e4-4498-a530-55a65857e7e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146430934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.2146430934
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1400832502
Short name T898
Test name
Test status
Simulation time 836281237 ps
CPU time 1.86 seconds
Started Aug 07 06:09:29 PM PDT 24
Finished Aug 07 06:09:31 PM PDT 24
Peak memory 206964 kb
Host smart-b556f01c-370f-4e60-9b60-4c4f9e081adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14008
32502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1400832502
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2470188396
Short name T2442
Test name
Test status
Simulation time 139816655 ps
CPU time 0.86 seconds
Started Aug 07 06:09:34 PM PDT 24
Finished Aug 07 06:09:35 PM PDT 24
Peak memory 207164 kb
Host smart-403a6049-65b6-4a68-9e9a-7835abf48fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24701
88396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2470188396
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3879393193
Short name T1057
Test name
Test status
Simulation time 38906471 ps
CPU time 0.71 seconds
Started Aug 07 06:09:34 PM PDT 24
Finished Aug 07 06:09:35 PM PDT 24
Peak memory 206948 kb
Host smart-10bee245-2be7-4c3c-91c2-4d0d7abe5c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38793
93193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3879393193
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.3693730843
Short name T732
Test name
Test status
Simulation time 840939837 ps
CPU time 2.3 seconds
Started Aug 07 06:09:34 PM PDT 24
Finished Aug 07 06:09:37 PM PDT 24
Peak memory 207456 kb
Host smart-877b1d72-b4f8-4a4c-a548-6f3a9a579e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36937
30843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.3693730843
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_types.2768843903
Short name T416
Test name
Test status
Simulation time 396431250 ps
CPU time 1.22 seconds
Started Aug 07 06:09:32 PM PDT 24
Finished Aug 07 06:09:34 PM PDT 24
Peak memory 206932 kb
Host smart-525015f9-ff88-4566-acb9-fb7861230708
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2768843903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.2768843903
Directory /workspace/39.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.900910972
Short name T783
Test name
Test status
Simulation time 234910456 ps
CPU time 1.75 seconds
Started Aug 07 06:09:31 PM PDT 24
Finished Aug 07 06:09:33 PM PDT 24
Peak memory 207040 kb
Host smart-a5e367cd-d20e-4704-9be8-233b910d8149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90091
0972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.900910972
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.414719665
Short name T165
Test name
Test status
Simulation time 242115842 ps
CPU time 1.2 seconds
Started Aug 07 06:09:34 PM PDT 24
Finished Aug 07 06:09:35 PM PDT 24
Peak memory 207168 kb
Host smart-ffd0c6ec-670d-4ce1-b72b-4bc7329dcf6b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=414719665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.414719665
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.595349408
Short name T1722
Test name
Test status
Simulation time 176530244 ps
CPU time 0.85 seconds
Started Aug 07 06:09:30 PM PDT 24
Finished Aug 07 06:09:31 PM PDT 24
Peak memory 206884 kb
Host smart-5bcf7661-4e97-4aec-a6f1-711d9df625c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59534
9408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.595349408
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3025420386
Short name T914
Test name
Test status
Simulation time 186751099 ps
CPU time 0.86 seconds
Started Aug 07 06:09:28 PM PDT 24
Finished Aug 07 06:09:29 PM PDT 24
Peak memory 207012 kb
Host smart-2ee7a28e-3d01-4755-8d13-c119a50efd60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30254
20386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3025420386
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.1339060255
Short name T683
Test name
Test status
Simulation time 4871835367 ps
CPU time 145.68 seconds
Started Aug 07 06:09:31 PM PDT 24
Finished Aug 07 06:11:57 PM PDT 24
Peak memory 215444 kb
Host smart-96f718ff-19a6-4361-b000-34951108aa9c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1339060255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.1339060255
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.937859111
Short name T711
Test name
Test status
Simulation time 5766700533 ps
CPU time 64.27 seconds
Started Aug 07 06:09:38 PM PDT 24
Finished Aug 07 06:10:42 PM PDT 24
Peak memory 207284 kb
Host smart-885f72b8-1459-4dbb-867f-18367856655e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=937859111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.937859111
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.3855525196
Short name T1668
Test name
Test status
Simulation time 247698681 ps
CPU time 1.03 seconds
Started Aug 07 06:09:39 PM PDT 24
Finished Aug 07 06:09:40 PM PDT 24
Peak memory 207000 kb
Host smart-11dc678e-5813-4151-a637-7f0724f2b375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38555
25196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.3855525196
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.238910904
Short name T1347
Test name
Test status
Simulation time 31008220185 ps
CPU time 42.69 seconds
Started Aug 07 06:09:36 PM PDT 24
Finished Aug 07 06:10:19 PM PDT 24
Peak memory 207304 kb
Host smart-6034078d-8fcf-41f6-8979-e0abe2d672d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23891
0904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.238910904
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1967446306
Short name T2595
Test name
Test status
Simulation time 9246705508 ps
CPU time 13.37 seconds
Started Aug 07 06:09:37 PM PDT 24
Finished Aug 07 06:09:51 PM PDT 24
Peak memory 207284 kb
Host smart-a96873be-82c6-402e-9b8c-fc8a0b384ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19674
46306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1967446306
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.3133492867
Short name T1946
Test name
Test status
Simulation time 3520850842 ps
CPU time 32.9 seconds
Started Aug 07 06:09:40 PM PDT 24
Finished Aug 07 06:10:13 PM PDT 24
Peak memory 217112 kb
Host smart-6c3a6af5-ab93-4b00-b530-bcc1296d227c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3133492867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.3133492867
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.1035681761
Short name T2797
Test name
Test status
Simulation time 233228688 ps
CPU time 0.94 seconds
Started Aug 07 06:09:39 PM PDT 24
Finished Aug 07 06:09:40 PM PDT 24
Peak memory 206992 kb
Host smart-be618b44-9c56-4210-a663-0fae765d20a2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1035681761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.1035681761
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2040847610
Short name T2411
Test name
Test status
Simulation time 194189545 ps
CPU time 0.9 seconds
Started Aug 07 06:09:39 PM PDT 24
Finished Aug 07 06:09:40 PM PDT 24
Peak memory 207012 kb
Host smart-01f65a5d-8223-4ebd-b413-203149eebe46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20408
47610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2040847610
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1831622603
Short name T2715
Test name
Test status
Simulation time 3466443640 ps
CPU time 99.65 seconds
Started Aug 07 06:09:40 PM PDT 24
Finished Aug 07 06:11:20 PM PDT 24
Peak memory 217184 kb
Host smart-e344b657-ed65-473f-960d-0fc698ddea7a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1831622603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1831622603
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.84161346
Short name T665
Test name
Test status
Simulation time 162029105 ps
CPU time 0.89 seconds
Started Aug 07 06:09:38 PM PDT 24
Finished Aug 07 06:09:39 PM PDT 24
Peak memory 206996 kb
Host smart-83930937-4055-4d0e-8ca0-03ce9202550c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=84161346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.84161346
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3387734010
Short name T1882
Test name
Test status
Simulation time 164088975 ps
CPU time 0.85 seconds
Started Aug 07 06:09:39 PM PDT 24
Finished Aug 07 06:09:40 PM PDT 24
Peak memory 207028 kb
Host smart-a9b04a6c-b090-4554-8364-cc82c9c6769b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33877
34010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3387734010
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3628924723
Short name T3023
Test name
Test status
Simulation time 206764423 ps
CPU time 1 seconds
Started Aug 07 06:09:38 PM PDT 24
Finished Aug 07 06:09:39 PM PDT 24
Peak memory 206992 kb
Host smart-7872bfea-fc99-4019-af77-083b5ed8229f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36289
24723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3628924723
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.669323284
Short name T22
Test name
Test status
Simulation time 150721090 ps
CPU time 0.87 seconds
Started Aug 07 06:09:38 PM PDT 24
Finished Aug 07 06:09:39 PM PDT 24
Peak memory 206992 kb
Host smart-912d77fd-b2da-4c90-af16-9a35e9d03df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66932
3284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.669323284
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1393209624
Short name T1314
Test name
Test status
Simulation time 165026612 ps
CPU time 0.89 seconds
Started Aug 07 06:09:37 PM PDT 24
Finished Aug 07 06:09:38 PM PDT 24
Peak memory 206988 kb
Host smart-d3814490-00da-4afe-b456-e0ae29be3dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13932
09624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1393209624
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.224749093
Short name T2375
Test name
Test status
Simulation time 190948917 ps
CPU time 0.92 seconds
Started Aug 07 06:09:37 PM PDT 24
Finished Aug 07 06:09:38 PM PDT 24
Peak memory 206856 kb
Host smart-544ec3b3-0e6e-4581-bb68-9ee0f242292b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22474
9093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.224749093
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.162144691
Short name T1919
Test name
Test status
Simulation time 151488072 ps
CPU time 0.86 seconds
Started Aug 07 06:09:47 PM PDT 24
Finished Aug 07 06:09:48 PM PDT 24
Peak memory 207016 kb
Host smart-5fece241-78ff-4c82-8970-d84df7ac647e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16214
4691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.162144691
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.495422069
Short name T2315
Test name
Test status
Simulation time 213936567 ps
CPU time 1 seconds
Started Aug 07 06:09:47 PM PDT 24
Finished Aug 07 06:09:48 PM PDT 24
Peak memory 206980 kb
Host smart-0947737b-40cb-4b29-a82e-4e8d5d51a874
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=495422069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.495422069
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3840683265
Short name T1227
Test name
Test status
Simulation time 144873896 ps
CPU time 0.85 seconds
Started Aug 07 06:09:46 PM PDT 24
Finished Aug 07 06:09:47 PM PDT 24
Peak memory 206980 kb
Host smart-a12bd60e-d7aa-4265-ba79-19bdcb7e78e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38406
83265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3840683265
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3520413669
Short name T2625
Test name
Test status
Simulation time 72670078 ps
CPU time 0.73 seconds
Started Aug 07 06:09:48 PM PDT 24
Finished Aug 07 06:09:49 PM PDT 24
Peak memory 206872 kb
Host smart-716551a4-05ad-4d10-823b-917dd76e644e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35204
13669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3520413669
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2490632781
Short name T297
Test name
Test status
Simulation time 6539227311 ps
CPU time 18.24 seconds
Started Aug 07 06:09:45 PM PDT 24
Finished Aug 07 06:10:03 PM PDT 24
Peak memory 215496 kb
Host smart-cc11a2e7-c33a-4eaa-97dd-09c45f5b92d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24906
32781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2490632781
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1068441908
Short name T1549
Test name
Test status
Simulation time 152392304 ps
CPU time 0.88 seconds
Started Aug 07 06:09:46 PM PDT 24
Finished Aug 07 06:09:47 PM PDT 24
Peak memory 207020 kb
Host smart-35bc6a3c-a8d5-4a31-a8aa-8cee2ebdbf7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10684
41908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1068441908
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2562707384
Short name T2839
Test name
Test status
Simulation time 181114185 ps
CPU time 0.87 seconds
Started Aug 07 06:09:48 PM PDT 24
Finished Aug 07 06:09:49 PM PDT 24
Peak memory 206952 kb
Host smart-2ea7f78e-483b-4971-867c-a45fbef1ac62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25627
07384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2562707384
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3646166686
Short name T1805
Test name
Test status
Simulation time 171901750 ps
CPU time 0.86 seconds
Started Aug 07 06:09:47 PM PDT 24
Finished Aug 07 06:09:48 PM PDT 24
Peak memory 207040 kb
Host smart-a6f99882-6b6c-446a-95c2-8aa07652098e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36461
66686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3646166686
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.1982874249
Short name T2600
Test name
Test status
Simulation time 199105391 ps
CPU time 0.96 seconds
Started Aug 07 06:09:48 PM PDT 24
Finished Aug 07 06:09:49 PM PDT 24
Peak memory 207004 kb
Host smart-7f598b47-60b7-4194-8045-151d2975f8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19828
74249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.1982874249
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2993966072
Short name T1088
Test name
Test status
Simulation time 163212916 ps
CPU time 0.84 seconds
Started Aug 07 06:09:56 PM PDT 24
Finished Aug 07 06:09:57 PM PDT 24
Peak memory 206988 kb
Host smart-da18d87b-91a3-4d26-a3ff-ce780b578489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29939
66072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2993966072
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_rx_full.1355554770
Short name T1498
Test name
Test status
Simulation time 321501737 ps
CPU time 1.32 seconds
Started Aug 07 06:09:55 PM PDT 24
Finished Aug 07 06:09:57 PM PDT 24
Peak memory 206904 kb
Host smart-75239e07-42e5-4feb-a90a-76a288e5ed68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13555
54770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.1355554770
Directory /workspace/39.usbdev_rx_full/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2115815863
Short name T2615
Test name
Test status
Simulation time 150320474 ps
CPU time 0.83 seconds
Started Aug 07 06:09:55 PM PDT 24
Finished Aug 07 06:09:56 PM PDT 24
Peak memory 206912 kb
Host smart-54b79ef7-b81c-4054-a98d-2a20253d974b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21158
15863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2115815863
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2371360245
Short name T1348
Test name
Test status
Simulation time 153034017 ps
CPU time 0.89 seconds
Started Aug 07 06:09:54 PM PDT 24
Finished Aug 07 06:09:55 PM PDT 24
Peak memory 206992 kb
Host smart-61394f66-eb43-4eca-a37c-4d3b1da9bfce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23713
60245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2371360245
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2007701820
Short name T2146
Test name
Test status
Simulation time 255553116 ps
CPU time 1.14 seconds
Started Aug 07 06:09:59 PM PDT 24
Finished Aug 07 06:10:00 PM PDT 24
Peak memory 206980 kb
Host smart-8416716e-9a18-4ca3-9873-401b2a8ab3a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20077
01820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2007701820
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.2431542390
Short name T2841
Test name
Test status
Simulation time 2569116796 ps
CPU time 24.6 seconds
Started Aug 07 06:09:57 PM PDT 24
Finished Aug 07 06:10:22 PM PDT 24
Peak memory 216852 kb
Host smart-5bd2a282-0b17-456e-8e9c-06c676150372
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2431542390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.2431542390
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.802580270
Short name T656
Test name
Test status
Simulation time 210245078 ps
CPU time 0.92 seconds
Started Aug 07 06:09:59 PM PDT 24
Finished Aug 07 06:10:00 PM PDT 24
Peak memory 206988 kb
Host smart-56f3c2aa-c8b5-40d1-844e-3f22c4a3fb48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80258
0270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.802580270
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3865347305
Short name T2011
Test name
Test status
Simulation time 170462454 ps
CPU time 0.88 seconds
Started Aug 07 06:09:58 PM PDT 24
Finished Aug 07 06:09:59 PM PDT 24
Peak memory 206984 kb
Host smart-d4415621-a16a-4c1c-b7c0-af556c93be13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38653
47305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3865347305
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3354934754
Short name T3077
Test name
Test status
Simulation time 915559625 ps
CPU time 2.26 seconds
Started Aug 07 06:10:08 PM PDT 24
Finished Aug 07 06:10:11 PM PDT 24
Peak memory 207204 kb
Host smart-658ba9d6-af9e-4efb-8336-2296f49e3a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33549
34754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3354934754
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1603962192
Short name T1244
Test name
Test status
Simulation time 3587570493 ps
CPU time 105.39 seconds
Started Aug 07 06:10:09 PM PDT 24
Finished Aug 07 06:11:54 PM PDT 24
Peak memory 215532 kb
Host smart-f6bfe980-9165-4f9c-b4fa-a4f4c19b7067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16039
62192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1603962192
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.3806510591
Short name T654
Test name
Test status
Simulation time 640771070 ps
CPU time 4.77 seconds
Started Aug 07 06:09:29 PM PDT 24
Finished Aug 07 06:09:34 PM PDT 24
Peak memory 207224 kb
Host smart-3b003933-1ef9-4352-92be-517439e8836e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806510591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.3806510591
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.1714289233
Short name T2360
Test name
Test status
Simulation time 36051447 ps
CPU time 0.65 seconds
Started Aug 07 05:59:39 PM PDT 24
Finished Aug 07 05:59:40 PM PDT 24
Peak memory 207092 kb
Host smart-0135ce2f-1218-4c65-acb2-0fbebab5a131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1714289233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1714289233
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.3573155113
Short name T2693
Test name
Test status
Simulation time 5761839610 ps
CPU time 7.81 seconds
Started Aug 07 05:59:19 PM PDT 24
Finished Aug 07 05:59:27 PM PDT 24
Peak memory 215692 kb
Host smart-8bf06d6d-7448-4a33-8e1c-efe38367ea24
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573155113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.3573155113
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2324571235
Short name T1179
Test name
Test status
Simulation time 14443018059 ps
CPU time 19.59 seconds
Started Aug 07 05:59:17 PM PDT 24
Finished Aug 07 05:59:37 PM PDT 24
Peak memory 215448 kb
Host smart-348701d0-68dc-4bb6-b892-89499f13e9d3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324571235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2324571235
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.4015226636
Short name T2740
Test name
Test status
Simulation time 31526211330 ps
CPU time 42.31 seconds
Started Aug 07 05:59:16 PM PDT 24
Finished Aug 07 05:59:59 PM PDT 24
Peak memory 207252 kb
Host smart-a80e2024-41f4-4460-9e55-7598469c04b8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015226636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.4015226636
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1917689704
Short name T2025
Test name
Test status
Simulation time 197475001 ps
CPU time 0.88 seconds
Started Aug 07 05:59:19 PM PDT 24
Finished Aug 07 05:59:20 PM PDT 24
Peak memory 206984 kb
Host smart-a8b68f53-daa5-4659-9725-1b7891e07632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19176
89704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1917689704
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.1778535584
Short name T52
Test name
Test status
Simulation time 209491974 ps
CPU time 0.88 seconds
Started Aug 07 05:59:18 PM PDT 24
Finished Aug 07 05:59:19 PM PDT 24
Peak memory 206976 kb
Host smart-a503b5cb-5fc2-4de0-9dbb-b5e9052356ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17785
35584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.1778535584
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2405543312
Short name T21
Test name
Test status
Simulation time 157255856 ps
CPU time 0.87 seconds
Started Aug 07 05:59:20 PM PDT 24
Finished Aug 07 05:59:21 PM PDT 24
Peak memory 206944 kb
Host smart-ffa340c4-d057-4925-8a32-88aff5bdcc1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24055
43312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2405543312
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2310728075
Short name T2758
Test name
Test status
Simulation time 142124510 ps
CPU time 0.84 seconds
Started Aug 07 05:59:19 PM PDT 24
Finished Aug 07 05:59:20 PM PDT 24
Peak memory 207012 kb
Host smart-3a1ade25-0833-4b92-a4e4-d70018d8e87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23107
28075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2310728075
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.3566326897
Short name T97
Test name
Test status
Simulation time 161604493 ps
CPU time 0.85 seconds
Started Aug 07 05:59:23 PM PDT 24
Finished Aug 07 05:59:23 PM PDT 24
Peak memory 206952 kb
Host smart-2fa8317d-f558-42fd-adc0-3373defccbc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35663
26897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.3566326897
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1053825919
Short name T2207
Test name
Test status
Simulation time 468178195 ps
CPU time 1.48 seconds
Started Aug 07 05:59:22 PM PDT 24
Finished Aug 07 05:59:24 PM PDT 24
Peak memory 207028 kb
Host smart-bd3025e0-3ed9-4dd5-b9e1-946050683c02
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1053825919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1053825919
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2589454472
Short name T379
Test name
Test status
Simulation time 30495400582 ps
CPU time 58.09 seconds
Started Aug 07 05:59:22 PM PDT 24
Finished Aug 07 06:00:20 PM PDT 24
Peak memory 207312 kb
Host smart-5f646522-ffb6-4dda-81ce-e0969b37aa10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25894
54472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2589454472
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.2180892421
Short name T2550
Test name
Test status
Simulation time 1805532560 ps
CPU time 44.44 seconds
Started Aug 07 05:59:24 PM PDT 24
Finished Aug 07 06:00:08 PM PDT 24
Peak memory 207156 kb
Host smart-345b21b2-7a8c-497e-8498-690d6ea78650
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180892421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.2180892421
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.3087935181
Short name T378
Test name
Test status
Simulation time 1065064962 ps
CPU time 2.11 seconds
Started Aug 07 05:59:23 PM PDT 24
Finished Aug 07 05:59:25 PM PDT 24
Peak memory 206916 kb
Host smart-c12b6b92-d424-4270-b65d-d6d08bcc1d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30879
35181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.3087935181
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2229132048
Short name T2842
Test name
Test status
Simulation time 142428715 ps
CPU time 0.9 seconds
Started Aug 07 05:59:23 PM PDT 24
Finished Aug 07 05:59:24 PM PDT 24
Peak memory 206988 kb
Host smart-5e033a50-6920-49c1-b161-509af0d88d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22291
32048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2229132048
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.327882730
Short name T2189
Test name
Test status
Simulation time 52234167 ps
CPU time 0.72 seconds
Started Aug 07 05:59:27 PM PDT 24
Finished Aug 07 05:59:28 PM PDT 24
Peak memory 206948 kb
Host smart-12bfe6b2-60bb-480e-9001-ee532d05ffb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32788
2730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.327882730
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3633330577
Short name T3015
Test name
Test status
Simulation time 805106802 ps
CPU time 2.11 seconds
Started Aug 07 05:59:24 PM PDT 24
Finished Aug 07 05:59:26 PM PDT 24
Peak memory 207196 kb
Host smart-63cb6257-b8b5-419f-b5d2-39f935c2d90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36333
30577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3633330577
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_types.2435641694
Short name T460
Test name
Test status
Simulation time 532492446 ps
CPU time 1.59 seconds
Started Aug 07 05:59:23 PM PDT 24
Finished Aug 07 05:59:25 PM PDT 24
Peak memory 206932 kb
Host smart-734d3b9d-c883-4ec2-b4d0-9547661416c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2435641694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.2435641694
Directory /workspace/4.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.647912252
Short name T2621
Test name
Test status
Simulation time 354894561 ps
CPU time 2.72 seconds
Started Aug 07 05:59:23 PM PDT 24
Finished Aug 07 05:59:25 PM PDT 24
Peak memory 207160 kb
Host smart-9497050e-3ec8-42fd-ad94-8a2418612f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64791
2252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.647912252
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2308873143
Short name T1411
Test name
Test status
Simulation time 91206503834 ps
CPU time 129.99 seconds
Started Aug 07 05:59:30 PM PDT 24
Finished Aug 07 06:01:40 PM PDT 24
Peak memory 207300 kb
Host smart-65cd2840-293a-4f6f-89cd-29e0bbe06053
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2308873143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2308873143
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.3019223407
Short name T1757
Test name
Test status
Simulation time 87288911685 ps
CPU time 135.1 seconds
Started Aug 07 05:59:30 PM PDT 24
Finished Aug 07 06:01:45 PM PDT 24
Peak memory 207264 kb
Host smart-c203d934-6fbf-46e2-965a-f77c4346d1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019223407 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.3019223407
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.685730629
Short name T1355
Test name
Test status
Simulation time 121137297979 ps
CPU time 174.95 seconds
Started Aug 07 05:59:28 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 207296 kb
Host smart-64fd9b58-0064-46a6-9bab-480f9a5f3fc3
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=685730629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.685730629
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.3493507627
Short name T2186
Test name
Test status
Simulation time 119194197425 ps
CPU time 189.45 seconds
Started Aug 07 05:59:31 PM PDT 24
Finished Aug 07 06:02:40 PM PDT 24
Peak memory 207296 kb
Host smart-afd573dd-90d9-4e3b-ae9a-9498c58a004c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493507627 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.3493507627
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.3270877274
Short name T330
Test name
Test status
Simulation time 106160350881 ps
CPU time 162.93 seconds
Started Aug 07 05:59:27 PM PDT 24
Finished Aug 07 06:02:10 PM PDT 24
Peak memory 207360 kb
Host smart-ed62657e-b00a-482c-9760-91f411388bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32708
77274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3270877274
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3703707740
Short name T2195
Test name
Test status
Simulation time 239175989 ps
CPU time 1.17 seconds
Started Aug 07 05:59:30 PM PDT 24
Finished Aug 07 05:59:31 PM PDT 24
Peak memory 207176 kb
Host smart-90a9399e-4211-4808-944b-029c770f228c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3703707740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3703707740
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.4034379007
Short name T2629
Test name
Test status
Simulation time 144816550 ps
CPU time 0.8 seconds
Started Aug 07 05:59:28 PM PDT 24
Finished Aug 07 05:59:29 PM PDT 24
Peak memory 206956 kb
Host smart-7fcecac9-911e-446a-9bdd-f42f51acf309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40343
79007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.4034379007
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1279228516
Short name T2255
Test name
Test status
Simulation time 239472714 ps
CPU time 1.01 seconds
Started Aug 07 05:59:30 PM PDT 24
Finished Aug 07 05:59:32 PM PDT 24
Peak memory 206988 kb
Host smart-1bfcfbc4-13fc-4461-8a19-0276d8c83899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12792
28516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1279228516
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.2534338801
Short name T2484
Test name
Test status
Simulation time 4276032369 ps
CPU time 121.82 seconds
Started Aug 07 05:59:30 PM PDT 24
Finished Aug 07 06:01:32 PM PDT 24
Peak memory 223596 kb
Host smart-00c56363-9d43-4c9f-8022-310393fb8212
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2534338801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.2534338801
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.2230019745
Short name T2641
Test name
Test status
Simulation time 10331497597 ps
CPU time 116.74 seconds
Started Aug 07 05:59:27 PM PDT 24
Finished Aug 07 06:01:24 PM PDT 24
Peak memory 207284 kb
Host smart-db601f05-3727-4954-bac4-19176cb9de48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2230019745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.2230019745
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3374640268
Short name T2350
Test name
Test status
Simulation time 224363620 ps
CPU time 1 seconds
Started Aug 07 05:59:28 PM PDT 24
Finished Aug 07 05:59:29 PM PDT 24
Peak memory 206908 kb
Host smart-aafa2f09-cdc3-4b07-bf80-b3820a8810a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33746
40268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3374640268
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.40195493
Short name T1431
Test name
Test status
Simulation time 13177643316 ps
CPU time 19.89 seconds
Started Aug 07 05:59:31 PM PDT 24
Finished Aug 07 05:59:51 PM PDT 24
Peak memory 207288 kb
Host smart-8a61d82e-43b9-494d-898d-dba9d6ca5a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40195
493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.40195493
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.4217967596
Short name T116
Test name
Test status
Simulation time 3922113471 ps
CPU time 5.44 seconds
Started Aug 07 05:59:29 PM PDT 24
Finished Aug 07 05:59:35 PM PDT 24
Peak memory 215488 kb
Host smart-83e525d9-a3f1-4d3f-8ad4-1d95583fefe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42179
67596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.4217967596
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.1466213662
Short name T2775
Test name
Test status
Simulation time 3924419622 ps
CPU time 113.09 seconds
Started Aug 07 05:59:28 PM PDT 24
Finished Aug 07 06:01:21 PM PDT 24
Peak memory 223656 kb
Host smart-c1b4f491-ae46-4406-b349-05df9ffda83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14662
13662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.1466213662
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2015189269
Short name T714
Test name
Test status
Simulation time 2041550071 ps
CPU time 55.24 seconds
Started Aug 07 05:59:32 PM PDT 24
Finished Aug 07 06:00:27 PM PDT 24
Peak memory 215380 kb
Host smart-6eebd31a-6466-4ace-a42c-31682b51f097
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2015189269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2015189269
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2638875335
Short name T2714
Test name
Test status
Simulation time 247598303 ps
CPU time 1.02 seconds
Started Aug 07 05:59:28 PM PDT 24
Finished Aug 07 05:59:29 PM PDT 24
Peak memory 206952 kb
Host smart-f9947640-8780-4dc0-a17a-9915e8e94871
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2638875335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2638875335
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.67204834
Short name T1656
Test name
Test status
Simulation time 185303687 ps
CPU time 0.99 seconds
Started Aug 07 05:59:28 PM PDT 24
Finished Aug 07 05:59:30 PM PDT 24
Peak memory 206972 kb
Host smart-3a67fea3-b44e-4495-aca9-54a9e1b1c9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67204
834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.67204834
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.4100217211
Short name T1132
Test name
Test status
Simulation time 2040668190 ps
CPU time 16.82 seconds
Started Aug 07 05:59:29 PM PDT 24
Finished Aug 07 05:59:46 PM PDT 24
Peak memory 223504 kb
Host smart-b1da79cd-4793-4ff7-8c33-1140301b373f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41002
17211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.4100217211
Directory /workspace/4.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.306108325
Short name T2194
Test name
Test status
Simulation time 2608720026 ps
CPU time 20.69 seconds
Started Aug 07 05:59:31 PM PDT 24
Finished Aug 07 05:59:51 PM PDT 24
Peak memory 207316 kb
Host smart-1a8879e9-2042-480e-94c9-c2f46f1ccd49
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=306108325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.306108325
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.237319363
Short name T2601
Test name
Test status
Simulation time 2070698998 ps
CPU time 15.66 seconds
Started Aug 07 05:59:31 PM PDT 24
Finished Aug 07 05:59:47 PM PDT 24
Peak memory 215356 kb
Host smart-b74956bc-5979-475c-a4f8-44bf19f74808
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=237319363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.237319363
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1121156670
Short name T1118
Test name
Test status
Simulation time 156799978 ps
CPU time 0.84 seconds
Started Aug 07 05:59:28 PM PDT 24
Finished Aug 07 05:59:29 PM PDT 24
Peak memory 206900 kb
Host smart-53413e93-587f-4b5d-bbc8-61f844d1488d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1121156670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1121156670
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.771407364
Short name T2230
Test name
Test status
Simulation time 221674350 ps
CPU time 0.89 seconds
Started Aug 07 05:59:29 PM PDT 24
Finished Aug 07 05:59:30 PM PDT 24
Peak memory 207016 kb
Host smart-28392430-d85d-4e92-a9ef-5a170bcb7410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77140
7364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.771407364
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2689203774
Short name T148
Test name
Test status
Simulation time 239041291 ps
CPU time 1.01 seconds
Started Aug 07 05:59:28 PM PDT 24
Finished Aug 07 05:59:29 PM PDT 24
Peak memory 206960 kb
Host smart-958d785a-458c-4899-846b-6e421932073b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26892
03774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2689203774
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2706417273
Short name T2874
Test name
Test status
Simulation time 207567235 ps
CPU time 0.92 seconds
Started Aug 07 05:59:30 PM PDT 24
Finished Aug 07 05:59:31 PM PDT 24
Peak memory 206980 kb
Host smart-06aca1b0-32e8-43ab-b63a-e98654a526a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27064
17273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2706417273
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.4117141326
Short name T2747
Test name
Test status
Simulation time 195050443 ps
CPU time 0.92 seconds
Started Aug 07 05:59:31 PM PDT 24
Finished Aug 07 05:59:32 PM PDT 24
Peak memory 206944 kb
Host smart-3657a8c8-1675-440d-a878-9ccd4705bfbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41171
41326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.4117141326
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2482396651
Short name T1494
Test name
Test status
Simulation time 153212489 ps
CPU time 0.81 seconds
Started Aug 07 05:59:34 PM PDT 24
Finished Aug 07 05:59:34 PM PDT 24
Peak memory 207020 kb
Host smart-89a5a19e-a552-48d0-b0ad-05ad8029d162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24823
96651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2482396651
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3348009019
Short name T197
Test name
Test status
Simulation time 147367066 ps
CPU time 0.94 seconds
Started Aug 07 05:59:33 PM PDT 24
Finished Aug 07 05:59:34 PM PDT 24
Peak memory 207008 kb
Host smart-ea17ac1a-0a67-48c6-8e0d-ae6e0ce1cce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33480
09019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3348009019
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.95988206
Short name T1848
Test name
Test status
Simulation time 234577974 ps
CPU time 0.98 seconds
Started Aug 07 05:59:32 PM PDT 24
Finished Aug 07 05:59:33 PM PDT 24
Peak memory 206908 kb
Host smart-441531b9-83a5-4cac-bdfd-b9b019971ff1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=95988206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.95988206
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.1376560975
Short name T1605
Test name
Test status
Simulation time 204289846 ps
CPU time 0.93 seconds
Started Aug 07 05:59:33 PM PDT 24
Finished Aug 07 05:59:34 PM PDT 24
Peak memory 206912 kb
Host smart-fa295196-c356-41ac-87f2-5ffd9908be42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13765
60975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.1376560975
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1470199057
Short name T1150
Test name
Test status
Simulation time 150282934 ps
CPU time 0.84 seconds
Started Aug 07 05:59:35 PM PDT 24
Finished Aug 07 05:59:36 PM PDT 24
Peak memory 206972 kb
Host smart-ebeb3e7d-3f18-49a5-8c48-8ebef3c98b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14701
99057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1470199057
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2525219076
Short name T2557
Test name
Test status
Simulation time 32012265 ps
CPU time 0.72 seconds
Started Aug 07 05:59:37 PM PDT 24
Finished Aug 07 05:59:38 PM PDT 24
Peak memory 206924 kb
Host smart-187c4d26-355e-44b0-91e2-27e05fd4c7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25252
19076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2525219076
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3159722684
Short name T2962
Test name
Test status
Simulation time 10833003090 ps
CPU time 29.13 seconds
Started Aug 07 05:59:52 PM PDT 24
Finished Aug 07 06:00:21 PM PDT 24
Peak memory 215452 kb
Host smart-9865d1d5-7601-4a36-b387-c57aa9500b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31597
22684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3159722684
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.436037822
Short name T3056
Test name
Test status
Simulation time 174186951 ps
CPU time 0.93 seconds
Started Aug 07 05:59:52 PM PDT 24
Finished Aug 07 05:59:53 PM PDT 24
Peak memory 207020 kb
Host smart-fb9f150e-c9dc-4045-af0f-7b9ceb1477ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43603
7822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.436037822
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.780040061
Short name T2199
Test name
Test status
Simulation time 223733259 ps
CPU time 0.97 seconds
Started Aug 07 05:59:37 PM PDT 24
Finished Aug 07 05:59:38 PM PDT 24
Peak memory 206996 kb
Host smart-e2b076bd-94a3-4c65-a201-717fa58903c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78004
0061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.780040061
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.658842487
Short name T2290
Test name
Test status
Simulation time 2990194291 ps
CPU time 16.11 seconds
Started Aug 07 05:59:34 PM PDT 24
Finished Aug 07 05:59:50 PM PDT 24
Peak memory 223680 kb
Host smart-7be8de99-9074-483f-a119-fd3ab21a15ed
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=658842487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.658842487
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.1873290997
Short name T1362
Test name
Test status
Simulation time 6754702820 ps
CPU time 99.1 seconds
Started Aug 07 05:59:35 PM PDT 24
Finished Aug 07 06:01:14 PM PDT 24
Peak memory 218324 kb
Host smart-4a1cdbcd-3903-4687-b4bf-2a0d620899dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873290997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1873290997
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.2231005374
Short name T1694
Test name
Test status
Simulation time 205798837 ps
CPU time 0.93 seconds
Started Aug 07 05:59:37 PM PDT 24
Finished Aug 07 05:59:38 PM PDT 24
Peak memory 206944 kb
Host smart-2fb829e1-b0bc-40fb-ae30-badf9dbbe69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22310
05374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.2231005374
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1679126243
Short name T1823
Test name
Test status
Simulation time 172363182 ps
CPU time 0.9 seconds
Started Aug 07 05:59:34 PM PDT 24
Finished Aug 07 05:59:35 PM PDT 24
Peak memory 207012 kb
Host smart-0d3f7052-c7a0-41eb-bf69-224bf7abe728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16791
26243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1679126243
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_resume_link_active.1714389302
Short name T2804
Test name
Test status
Simulation time 20163239713 ps
CPU time 22.58 seconds
Started Aug 07 05:59:55 PM PDT 24
Finished Aug 07 06:00:18 PM PDT 24
Peak memory 207072 kb
Host smart-c591b192-9103-49fb-b5f8-a856a4fa93b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17143
89302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.1714389302
Directory /workspace/4.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3325401527
Short name T552
Test name
Test status
Simulation time 165915456 ps
CPU time 0.85 seconds
Started Aug 07 05:59:38 PM PDT 24
Finished Aug 07 05:59:39 PM PDT 24
Peak memory 206904 kb
Host smart-243a6935-dced-4c5e-b9d5-a41aea7a0052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33254
01527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3325401527
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_full.1676005981
Short name T1897
Test name
Test status
Simulation time 260307874 ps
CPU time 1.12 seconds
Started Aug 07 05:59:35 PM PDT 24
Finished Aug 07 05:59:36 PM PDT 24
Peak memory 206960 kb
Host smart-cd7ce98f-6d5e-413b-980d-a7e3d788deee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16760
05981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.1676005981
Directory /workspace/4.usbdev_rx_full/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.3687786486
Short name T2711
Test name
Test status
Simulation time 168301632 ps
CPU time 0.91 seconds
Started Aug 07 05:59:37 PM PDT 24
Finished Aug 07 05:59:38 PM PDT 24
Peak memory 206980 kb
Host smart-926ce63b-4b72-4191-b67b-cf03016f2c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36877
86486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.3687786486
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1991601036
Short name T214
Test name
Test status
Simulation time 685261392 ps
CPU time 1.49 seconds
Started Aug 07 05:59:40 PM PDT 24
Finished Aug 07 05:59:41 PM PDT 24
Peak memory 222948 kb
Host smart-597ff654-53ec-4fe4-a5fb-b2b4ed157c16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1991601036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1991601036
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.682843054
Short name T44
Test name
Test status
Simulation time 381338012 ps
CPU time 1.3 seconds
Started Aug 07 05:59:34 PM PDT 24
Finished Aug 07 05:59:35 PM PDT 24
Peak memory 206972 kb
Host smart-28e5608d-37dc-4378-9af5-2ffc933b00d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68284
3054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.682843054
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.1181826937
Short name T884
Test name
Test status
Simulation time 226396679 ps
CPU time 1.13 seconds
Started Aug 07 05:59:38 PM PDT 24
Finished Aug 07 05:59:39 PM PDT 24
Peak memory 207016 kb
Host smart-9e06c94e-bb68-4e49-b696-ad38805373d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11818
26937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.1181826937
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3444664237
Short name T1130
Test name
Test status
Simulation time 161371205 ps
CPU time 0.87 seconds
Started Aug 07 05:59:33 PM PDT 24
Finished Aug 07 05:59:34 PM PDT 24
Peak memory 206952 kb
Host smart-b323d0e3-df45-4daa-a7c8-f1e671a5f039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34446
64237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3444664237
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3517093022
Short name T1810
Test name
Test status
Simulation time 185469970 ps
CPU time 0.84 seconds
Started Aug 07 05:59:33 PM PDT 24
Finished Aug 07 05:59:34 PM PDT 24
Peak memory 206980 kb
Host smart-63bf1776-86a6-4c5f-9ef7-404eaec70b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35170
93022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3517093022
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1038098084
Short name T2745
Test name
Test status
Simulation time 219381383 ps
CPU time 1.05 seconds
Started Aug 07 05:59:35 PM PDT 24
Finished Aug 07 05:59:36 PM PDT 24
Peak memory 206960 kb
Host smart-d4164321-e938-44a3-8e87-62633afc5325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10380
98084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1038098084
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1000649819
Short name T1054
Test name
Test status
Simulation time 2398081790 ps
CPU time 18.42 seconds
Started Aug 07 05:59:33 PM PDT 24
Finished Aug 07 05:59:51 PM PDT 24
Peak memory 223620 kb
Host smart-30753ecd-3354-4e78-9f99-775e4622a7ed
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1000649819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1000649819
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1319354822
Short name T2169
Test name
Test status
Simulation time 188893245 ps
CPU time 0.89 seconds
Started Aug 07 05:59:39 PM PDT 24
Finished Aug 07 05:59:40 PM PDT 24
Peak memory 206968 kb
Host smart-945a8391-bc43-4e17-bf48-6b01e1b15911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13193
54822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1319354822
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.691254706
Short name T2542
Test name
Test status
Simulation time 247451121 ps
CPU time 0.97 seconds
Started Aug 07 05:59:40 PM PDT 24
Finished Aug 07 05:59:41 PM PDT 24
Peak memory 206900 kb
Host smart-75127750-e50a-4d60-8757-11c37aac5991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69125
4706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.691254706
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.1795956612
Short name T590
Test name
Test status
Simulation time 1333289345 ps
CPU time 3.25 seconds
Started Aug 07 05:59:40 PM PDT 24
Finished Aug 07 05:59:43 PM PDT 24
Peak memory 207144 kb
Host smart-6ae66552-2abc-4c04-bdc6-0ff80746da4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17959
56612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.1795956612
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.4100254117
Short name T2337
Test name
Test status
Simulation time 2784411373 ps
CPU time 80.28 seconds
Started Aug 07 05:59:40 PM PDT 24
Finished Aug 07 06:01:01 PM PDT 24
Peak memory 216940 kb
Host smart-158f99e1-c0d7-4bcb-80a4-cc73d3c0c73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41002
54117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.4100254117
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.2996078645
Short name T839
Test name
Test status
Simulation time 2488688342 ps
CPU time 21.97 seconds
Started Aug 07 05:59:21 PM PDT 24
Finished Aug 07 05:59:43 PM PDT 24
Peak memory 207352 kb
Host smart-b74e9a14-0d8f-46ff-9614-2835eb042d40
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996078645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.2996078645
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3604056430
Short name T203
Test name
Test status
Simulation time 55549049 ps
CPU time 0.67 seconds
Started Aug 07 06:10:21 PM PDT 24
Finished Aug 07 06:10:22 PM PDT 24
Peak memory 207068 kb
Host smart-39915556-263d-4ed8-be54-6fba6aa97418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3604056430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3604056430
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1890323023
Short name T15
Test name
Test status
Simulation time 9572306519 ps
CPU time 11.8 seconds
Started Aug 07 06:10:06 PM PDT 24
Finished Aug 07 06:10:18 PM PDT 24
Peak memory 207324 kb
Host smart-358ffbf7-48e3-4c51-8e5d-458f99338bf3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890323023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.1890323023
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2528777082
Short name T964
Test name
Test status
Simulation time 18915898619 ps
CPU time 27.06 seconds
Started Aug 07 06:10:09 PM PDT 24
Finished Aug 07 06:10:36 PM PDT 24
Peak memory 207292 kb
Host smart-deca6845-50c9-4ef1-b1bc-bc327dbe60d0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528777082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2528777082
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.384702713
Short name T1699
Test name
Test status
Simulation time 24272451302 ps
CPU time 28.23 seconds
Started Aug 07 06:10:06 PM PDT 24
Finished Aug 07 06:10:35 PM PDT 24
Peak memory 215492 kb
Host smart-1dbd92a3-d758-424a-99c2-77d76d44b5f0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384702713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_ao
n_wake_resume.384702713
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2905475764
Short name T2694
Test name
Test status
Simulation time 183419861 ps
CPU time 0.9 seconds
Started Aug 07 06:10:07 PM PDT 24
Finished Aug 07 06:10:08 PM PDT 24
Peak memory 206972 kb
Host smart-c154458c-8bab-4ad6-a795-36f1cb039d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29054
75764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2905475764
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.2871629940
Short name T1874
Test name
Test status
Simulation time 150784017 ps
CPU time 0.84 seconds
Started Aug 07 06:10:06 PM PDT 24
Finished Aug 07 06:10:07 PM PDT 24
Peak memory 206956 kb
Host smart-224b219e-25b9-4bbd-9291-441548183bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28716
29940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.2871629940
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.607147985
Short name T2490
Test name
Test status
Simulation time 480608863 ps
CPU time 1.65 seconds
Started Aug 07 06:10:08 PM PDT 24
Finished Aug 07 06:10:09 PM PDT 24
Peak memory 206964 kb
Host smart-fdfc8072-b224-4a7d-90fa-d911b97bec36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60714
7985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.607147985
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2776859072
Short name T85
Test name
Test status
Simulation time 937727396 ps
CPU time 2.31 seconds
Started Aug 07 06:10:08 PM PDT 24
Finished Aug 07 06:10:11 PM PDT 24
Peak memory 207084 kb
Host smart-fdf2b699-341e-453d-9c2d-e547322d8198
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2776859072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2776859072
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1848416541
Short name T1261
Test name
Test status
Simulation time 48211181867 ps
CPU time 87.05 seconds
Started Aug 07 06:10:06 PM PDT 24
Finished Aug 07 06:11:33 PM PDT 24
Peak memory 207272 kb
Host smart-6a709171-4a79-433d-82cc-d421614b4506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18484
16541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1848416541
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.384222735
Short name T1513
Test name
Test status
Simulation time 2220803350 ps
CPU time 14.8 seconds
Started Aug 07 06:10:08 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 207296 kb
Host smart-0d78d4d0-d904-41ce-87a5-78d3a61be881
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384222735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.384222735
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2243152419
Short name T1540
Test name
Test status
Simulation time 909592177 ps
CPU time 2.12 seconds
Started Aug 07 06:10:06 PM PDT 24
Finished Aug 07 06:10:09 PM PDT 24
Peak memory 206896 kb
Host smart-7d857616-a601-4820-9eb9-776186e04549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22431
52419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2243152419
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.4100899732
Short name T792
Test name
Test status
Simulation time 149951863 ps
CPU time 0.86 seconds
Started Aug 07 06:10:20 PM PDT 24
Finished Aug 07 06:10:21 PM PDT 24
Peak memory 206940 kb
Host smart-f8569423-b455-43a5-84f0-35d8ebc3c720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41008
99732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.4100899732
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.3843710002
Short name T1789
Test name
Test status
Simulation time 50285954 ps
CPU time 0.71 seconds
Started Aug 07 06:10:19 PM PDT 24
Finished Aug 07 06:10:20 PM PDT 24
Peak memory 206932 kb
Host smart-f33572d9-78fd-47eb-8b84-c6c62b6a0da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38437
10002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3843710002
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.4225065172
Short name T2843
Test name
Test status
Simulation time 1061443209 ps
CPU time 3.05 seconds
Started Aug 07 06:10:18 PM PDT 24
Finished Aug 07 06:10:21 PM PDT 24
Peak memory 207168 kb
Host smart-84a2cc1b-14b5-4215-91d4-2d0d1298989b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42250
65172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.4225065172
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_types.2648528426
Short name T121
Test name
Test status
Simulation time 516040232 ps
CPU time 1.45 seconds
Started Aug 07 06:10:24 PM PDT 24
Finished Aug 07 06:10:26 PM PDT 24
Peak memory 206880 kb
Host smart-dc3c35ec-d7a4-4de9-ab97-fb01ecc7ca62
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2648528426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.2648528426
Directory /workspace/40.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3107303442
Short name T2498
Test name
Test status
Simulation time 334832276 ps
CPU time 2.4 seconds
Started Aug 07 06:10:24 PM PDT 24
Finished Aug 07 06:10:27 PM PDT 24
Peak memory 207032 kb
Host smart-a9ace3bb-6628-4ed5-9cd9-1eca16e949ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31073
03442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3107303442
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1794433545
Short name T2886
Test name
Test status
Simulation time 225978029 ps
CPU time 1.13 seconds
Started Aug 07 06:10:19 PM PDT 24
Finished Aug 07 06:10:20 PM PDT 24
Peak memory 215368 kb
Host smart-edce8d77-e02b-4771-9c6f-d59d24a2353c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1794433545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1794433545
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1428474706
Short name T563
Test name
Test status
Simulation time 151478843 ps
CPU time 0.9 seconds
Started Aug 07 06:10:21 PM PDT 24
Finished Aug 07 06:10:22 PM PDT 24
Peak memory 206944 kb
Host smart-2fe493bc-1dc6-4e5d-9429-3f4018a70939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14284
74706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1428474706
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3993854970
Short name T2240
Test name
Test status
Simulation time 236264390 ps
CPU time 0.97 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 206956 kb
Host smart-751487d4-3b8a-4a5c-9f8f-9099c8f2defd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39938
54970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3993854970
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2876795869
Short name T890
Test name
Test status
Simulation time 4232465736 ps
CPU time 128.02 seconds
Started Aug 07 06:10:21 PM PDT 24
Finished Aug 07 06:12:29 PM PDT 24
Peak memory 217928 kb
Host smart-60926f3e-048e-46da-b2ec-b1b9b8d4d312
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2876795869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2876795869
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.174351738
Short name T2547
Test name
Test status
Simulation time 7266148519 ps
CPU time 49.22 seconds
Started Aug 07 06:10:23 PM PDT 24
Finished Aug 07 06:11:12 PM PDT 24
Peak memory 207496 kb
Host smart-3cdfdd40-06fe-4fd6-88f8-8869e2395e5c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=174351738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.174351738
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.584590173
Short name T652
Test name
Test status
Simulation time 233116257 ps
CPU time 0.98 seconds
Started Aug 07 06:10:20 PM PDT 24
Finished Aug 07 06:10:21 PM PDT 24
Peak memory 206968 kb
Host smart-23352027-76e9-4d0e-88c8-388126e76e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58459
0173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.584590173
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.867234717
Short name T1199
Test name
Test status
Simulation time 31571738033 ps
CPU time 44.3 seconds
Started Aug 07 06:10:23 PM PDT 24
Finished Aug 07 06:11:08 PM PDT 24
Peak memory 207500 kb
Host smart-363f27de-a288-4639-957c-553ea1c19235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86723
4717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.867234717
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3498624227
Short name T1503
Test name
Test status
Simulation time 9568628180 ps
CPU time 14.29 seconds
Started Aug 07 06:10:20 PM PDT 24
Finished Aug 07 06:10:34 PM PDT 24
Peak memory 207268 kb
Host smart-aaeb6d0b-da00-43e8-ae74-e2c7352a7498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34986
24227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3498624227
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1246505078
Short name T2393
Test name
Test status
Simulation time 2485479804 ps
CPU time 19.16 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:41 PM PDT 24
Peak memory 223680 kb
Host smart-b935641a-3d91-4ff8-917d-5fca9a4e02f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12465
05078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1246505078
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.3097500113
Short name T689
Test name
Test status
Simulation time 2730113466 ps
CPU time 26.8 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:49 PM PDT 24
Peak memory 223584 kb
Host smart-b3b7c19d-1319-4c4f-bc6f-8d78e5c0f6ef
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3097500113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.3097500113
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.3883401241
Short name T1640
Test name
Test status
Simulation time 233500114 ps
CPU time 0.99 seconds
Started Aug 07 06:10:18 PM PDT 24
Finished Aug 07 06:10:19 PM PDT 24
Peak memory 206956 kb
Host smart-7b580d72-54fe-4cf6-bfd6-9f503a228061
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3883401241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3883401241
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.4047435576
Short name T2138
Test name
Test status
Simulation time 194462603 ps
CPU time 0.94 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 206956 kb
Host smart-5663c80a-fb6a-4bd6-977e-273194f9d92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40474
35576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.4047435576
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.3973902239
Short name T1686
Test name
Test status
Simulation time 1782199150 ps
CPU time 13.41 seconds
Started Aug 07 06:10:18 PM PDT 24
Finished Aug 07 06:10:31 PM PDT 24
Peak memory 215408 kb
Host smart-23bb7082-9727-498c-b3ea-0c751436efa6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3973902239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.3973902239
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.2884692387
Short name T2925
Test name
Test status
Simulation time 182508808 ps
CPU time 0.92 seconds
Started Aug 07 06:10:18 PM PDT 24
Finished Aug 07 06:10:19 PM PDT 24
Peak memory 206972 kb
Host smart-f0a9f012-9201-4f67-b7dd-e0baf5dc4392
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2884692387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2884692387
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3326182537
Short name T2912
Test name
Test status
Simulation time 142061761 ps
CPU time 0.85 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 207000 kb
Host smart-00aa0446-347b-41da-a22d-30db508fb8a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33261
82537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3326182537
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.4122818591
Short name T143
Test name
Test status
Simulation time 226057548 ps
CPU time 0.97 seconds
Started Aug 07 06:10:21 PM PDT 24
Finished Aug 07 06:10:22 PM PDT 24
Peak memory 206944 kb
Host smart-dd5336ad-ad1b-43a9-adaf-45c34897d8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41228
18591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.4122818591
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3901831179
Short name T2380
Test name
Test status
Simulation time 199228604 ps
CPU time 0.95 seconds
Started Aug 07 06:10:19 PM PDT 24
Finished Aug 07 06:10:20 PM PDT 24
Peak memory 206972 kb
Host smart-cc2d6078-b9d7-4729-ae2e-fddc751a6efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39018
31179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3901831179
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2273927367
Short name T534
Test name
Test status
Simulation time 176481655 ps
CPU time 0.95 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 206992 kb
Host smart-ed1a1db9-92e0-44f3-b3a0-cbccd417d99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22739
27367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2273927367
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3255579302
Short name T238
Test name
Test status
Simulation time 191292932 ps
CPU time 0.93 seconds
Started Aug 07 06:10:21 PM PDT 24
Finished Aug 07 06:10:22 PM PDT 24
Peak memory 207000 kb
Host smart-d4ee0856-9bb4-4db4-899b-a61270b51a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32555
79302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3255579302
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1458812067
Short name T1653
Test name
Test status
Simulation time 204560257 ps
CPU time 0.94 seconds
Started Aug 07 06:10:21 PM PDT 24
Finished Aug 07 06:10:22 PM PDT 24
Peak memory 206900 kb
Host smart-b5081c32-71e2-4576-9f8e-25d71ba96d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14588
12067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1458812067
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.1455609032
Short name T1915
Test name
Test status
Simulation time 250557351 ps
CPU time 1.1 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:24 PM PDT 24
Peak memory 207004 kb
Host smart-ab6a3b56-2b70-491b-8a57-5215e0a9f3b7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1455609032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.1455609032
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2120575585
Short name T821
Test name
Test status
Simulation time 146138338 ps
CPU time 0.83 seconds
Started Aug 07 06:10:24 PM PDT 24
Finished Aug 07 06:10:25 PM PDT 24
Peak memory 206952 kb
Host smart-fdedee84-a911-41bc-b2b9-b26299b8b1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21205
75585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2120575585
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.612938628
Short name T1158
Test name
Test status
Simulation time 46450259 ps
CPU time 0.68 seconds
Started Aug 07 06:10:20 PM PDT 24
Finished Aug 07 06:10:20 PM PDT 24
Peak memory 206864 kb
Host smart-5e9fc123-a0f7-493e-b8f7-b0cd878e04bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61293
8628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.612938628
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.297950211
Short name T1909
Test name
Test status
Simulation time 8427907698 ps
CPU time 20.73 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:43 PM PDT 24
Peak memory 215500 kb
Host smart-cf2af85a-9f16-49ac-a50b-24c66b9ea6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29795
0211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.297950211
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1843188397
Short name T2666
Test name
Test status
Simulation time 191454382 ps
CPU time 0.91 seconds
Started Aug 07 06:10:24 PM PDT 24
Finished Aug 07 06:10:25 PM PDT 24
Peak memory 206884 kb
Host smart-7e9ea32d-ab34-4e23-aff3-88b8e7d3331f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18431
88397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1843188397
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1565062914
Short name T1483
Test name
Test status
Simulation time 244619021 ps
CPU time 1.04 seconds
Started Aug 07 06:10:25 PM PDT 24
Finished Aug 07 06:10:26 PM PDT 24
Peak memory 206980 kb
Host smart-9c9d3c1a-e1c6-418d-ad40-1abdc008f9fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15650
62914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1565062914
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.2912643913
Short name T1962
Test name
Test status
Simulation time 181126088 ps
CPU time 0.91 seconds
Started Aug 07 06:10:18 PM PDT 24
Finished Aug 07 06:10:19 PM PDT 24
Peak memory 207016 kb
Host smart-590431d2-16bc-4b62-a342-1dbd8b67d447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29126
43913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.2912643913
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1257687884
Short name T2377
Test name
Test status
Simulation time 178851517 ps
CPU time 0.87 seconds
Started Aug 07 06:10:25 PM PDT 24
Finished Aug 07 06:10:26 PM PDT 24
Peak memory 206984 kb
Host smart-34116724-247d-4b2c-939d-3ee704a15902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12576
87884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1257687884
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.1215552578
Short name T2053
Test name
Test status
Simulation time 141215973 ps
CPU time 0.85 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 206876 kb
Host smart-48d85e71-11e0-4b84-8f51-668402411dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12155
52578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.1215552578
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_rx_full.3144282951
Short name T2754
Test name
Test status
Simulation time 276549447 ps
CPU time 1.09 seconds
Started Aug 07 06:10:18 PM PDT 24
Finished Aug 07 06:10:19 PM PDT 24
Peak memory 206904 kb
Host smart-cdcb3c9f-0822-468b-b6bf-5e690d3d1854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31442
82951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.3144282951
Directory /workspace/40.usbdev_rx_full/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.202749461
Short name T536
Test name
Test status
Simulation time 208573420 ps
CPU time 0.92 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 207012 kb
Host smart-ad053ffd-c081-4a63-a3ff-ad8e92e005e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20274
9461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.202749461
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2854829981
Short name T903
Test name
Test status
Simulation time 185335943 ps
CPU time 0.89 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 206868 kb
Host smart-ac72fe8e-3235-4797-9ea7-94265f27ffe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28548
29981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2854829981
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.408876924
Short name T2759
Test name
Test status
Simulation time 213395043 ps
CPU time 1.09 seconds
Started Aug 07 06:10:19 PM PDT 24
Finished Aug 07 06:10:20 PM PDT 24
Peak memory 206988 kb
Host smart-23036205-d6e5-4e03-934a-7d6c24ad2136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40887
6924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.408876924
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2844516408
Short name T950
Test name
Test status
Simulation time 2208712471 ps
CPU time 62.27 seconds
Started Aug 07 06:10:21 PM PDT 24
Finished Aug 07 06:11:23 PM PDT 24
Peak memory 216928 kb
Host smart-00ecda76-0cc9-4c63-9f9f-0662b3065ba9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2844516408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2844516408
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1988731239
Short name T2119
Test name
Test status
Simulation time 177428587 ps
CPU time 0.87 seconds
Started Aug 07 06:10:20 PM PDT 24
Finished Aug 07 06:10:21 PM PDT 24
Peak memory 207024 kb
Host smart-600cefba-a14b-4833-8b0e-398efbb191f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19887
31239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1988731239
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.254719596
Short name T1102
Test name
Test status
Simulation time 171799853 ps
CPU time 0.9 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 207012 kb
Host smart-1a3d77b7-36b4-42e6-91f7-0725693fd7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25471
9596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.254719596
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.395516414
Short name T775
Test name
Test status
Simulation time 1135052722 ps
CPU time 3.07 seconds
Started Aug 07 06:10:19 PM PDT 24
Finished Aug 07 06:10:22 PM PDT 24
Peak memory 207192 kb
Host smart-e5dae14e-e926-46d9-aa73-fa47c3df418f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39551
6414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.395516414
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1941963247
Short name T1997
Test name
Test status
Simulation time 4385989041 ps
CPU time 33.56 seconds
Started Aug 07 06:10:21 PM PDT 24
Finished Aug 07 06:10:54 PM PDT 24
Peak memory 217072 kb
Host smart-6b296fb5-891a-493e-b722-bcc9a21eff46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19419
63247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1941963247
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.3985148487
Short name T2294
Test name
Test status
Simulation time 1812645622 ps
CPU time 45.71 seconds
Started Aug 07 06:10:10 PM PDT 24
Finished Aug 07 06:10:56 PM PDT 24
Peak memory 207120 kb
Host smart-dc2639f7-e15d-4605-94bb-85ec206c5841
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985148487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.3985148487
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1671738728
Short name T601
Test name
Test status
Simulation time 124904354 ps
CPU time 0.76 seconds
Started Aug 07 06:10:45 PM PDT 24
Finished Aug 07 06:10:46 PM PDT 24
Peak memory 207000 kb
Host smart-3a4fcf6b-6618-4225-bc42-b9d2cc403296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1671738728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1671738728
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2473667127
Short name T3044
Test name
Test status
Simulation time 9179576798 ps
CPU time 11.47 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:33 PM PDT 24
Peak memory 207276 kb
Host smart-cee621e0-fd10-4faf-aada-07cc5379144e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473667127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.2473667127
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.394110170
Short name T1203
Test name
Test status
Simulation time 16231871866 ps
CPU time 18.28 seconds
Started Aug 07 06:10:21 PM PDT 24
Finished Aug 07 06:10:40 PM PDT 24
Peak memory 215488 kb
Host smart-2639bb89-8f0e-42d6-b556-fca5769c7218
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=394110170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.394110170
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2580349997
Short name T16
Test name
Test status
Simulation time 24388847851 ps
CPU time 28.95 seconds
Started Aug 07 06:10:24 PM PDT 24
Finished Aug 07 06:10:53 PM PDT 24
Peak memory 215660 kb
Host smart-08a3d37d-3dd1-4850-9f4d-1807c41d948b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580349997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.2580349997
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3352439476
Short name T1448
Test name
Test status
Simulation time 189297241 ps
CPU time 0.92 seconds
Started Aug 07 06:10:21 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 206992 kb
Host smart-64ca0243-4eda-4fa8-af9d-bce73031b442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33524
39476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3352439476
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.3684074361
Short name T1788
Test name
Test status
Simulation time 166825289 ps
CPU time 0.9 seconds
Started Aug 07 06:10:22 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 206900 kb
Host smart-bd2e135a-c203-4851-bdd9-02fb440338c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36840
74361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.3684074361
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3896989307
Short name T2705
Test name
Test status
Simulation time 649577940 ps
CPU time 1.91 seconds
Started Aug 07 06:10:19 PM PDT 24
Finished Aug 07 06:10:21 PM PDT 24
Peak memory 207148 kb
Host smart-8d30d4b2-53c8-477b-a8e4-24729092172e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38969
89307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3896989307
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.863795550
Short name T2631
Test name
Test status
Simulation time 803109408 ps
CPU time 2.24 seconds
Started Aug 07 06:10:20 PM PDT 24
Finished Aug 07 06:10:23 PM PDT 24
Peak memory 207148 kb
Host smart-532b87ed-72ff-4767-8b6b-08b33258c5f0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=863795550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.863795550
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.3859481950
Short name T2949
Test name
Test status
Simulation time 25209775897 ps
CPU time 42.86 seconds
Started Aug 07 06:10:19 PM PDT 24
Finished Aug 07 06:11:02 PM PDT 24
Peak memory 207268 kb
Host smart-95be937c-0f36-4c9f-b799-a7285daf5c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38594
81950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.3859481950
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.3035935526
Short name T2492
Test name
Test status
Simulation time 1574138908 ps
CPU time 13.58 seconds
Started Aug 07 06:10:33 PM PDT 24
Finished Aug 07 06:10:47 PM PDT 24
Peak memory 207240 kb
Host smart-81957480-af68-4d08-93d5-ccdde6df07e1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035935526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.3035935526
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.725507234
Short name T1310
Test name
Test status
Simulation time 705795492 ps
CPU time 1.54 seconds
Started Aug 07 06:10:30 PM PDT 24
Finished Aug 07 06:10:32 PM PDT 24
Peak memory 206984 kb
Host smart-da2ffb1a-141a-4614-9fda-9c4a1516da3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72550
7234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.725507234
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1989829570
Short name T1945
Test name
Test status
Simulation time 136958332 ps
CPU time 0.84 seconds
Started Aug 07 06:10:33 PM PDT 24
Finished Aug 07 06:10:34 PM PDT 24
Peak memory 206948 kb
Host smart-3c40d62f-eb23-45f2-b7b9-5abe3340868a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19898
29570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1989829570
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3574109164
Short name T764
Test name
Test status
Simulation time 39435841 ps
CPU time 0.68 seconds
Started Aug 07 06:10:35 PM PDT 24
Finished Aug 07 06:10:36 PM PDT 24
Peak memory 206920 kb
Host smart-cad5efd5-aca9-400a-804b-a8e3f57586bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35741
09164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3574109164
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.4262806631
Short name T2354
Test name
Test status
Simulation time 953119971 ps
CPU time 2.47 seconds
Started Aug 07 06:10:42 PM PDT 24
Finished Aug 07 06:10:45 PM PDT 24
Peak memory 207264 kb
Host smart-0c4b3fc2-ef7a-459a-9282-08007b2dbdcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42628
06631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.4262806631
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_types.375343269
Short name T360
Test name
Test status
Simulation time 348330767 ps
CPU time 1.17 seconds
Started Aug 07 06:10:42 PM PDT 24
Finished Aug 07 06:10:43 PM PDT 24
Peak memory 206996 kb
Host smart-9802ca8e-ea1e-486b-b863-dec778c0f58f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=375343269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.375343269
Directory /workspace/41.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2480398381
Short name T897
Test name
Test status
Simulation time 196384625 ps
CPU time 2.44 seconds
Started Aug 07 06:10:42 PM PDT 24
Finished Aug 07 06:10:44 PM PDT 24
Peak memory 207268 kb
Host smart-10bca912-953f-40ee-a628-446e9b23e7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24803
98381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2480398381
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.2942191551
Short name T1862
Test name
Test status
Simulation time 186763999 ps
CPU time 1.07 seconds
Started Aug 07 06:10:42 PM PDT 24
Finished Aug 07 06:10:43 PM PDT 24
Peak memory 207224 kb
Host smart-41d7ab63-6c85-4349-aa27-cd2bfc80fc29
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2942191551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2942191551
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2779449563
Short name T2238
Test name
Test status
Simulation time 148211329 ps
CPU time 0.81 seconds
Started Aug 07 06:10:34 PM PDT 24
Finished Aug 07 06:10:35 PM PDT 24
Peak memory 206828 kb
Host smart-527c00fe-0dab-4e39-9c71-73762ca60de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27794
49563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2779449563
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1673813515
Short name T2879
Test name
Test status
Simulation time 197880188 ps
CPU time 0.99 seconds
Started Aug 07 06:10:32 PM PDT 24
Finished Aug 07 06:10:33 PM PDT 24
Peak memory 207016 kb
Host smart-56aababa-f39f-4587-8fbd-bb806d918183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16738
13515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1673813515
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.3620104130
Short name T1604
Test name
Test status
Simulation time 5438714034 ps
CPU time 52.51 seconds
Started Aug 07 06:10:41 PM PDT 24
Finished Aug 07 06:11:34 PM PDT 24
Peak memory 223756 kb
Host smart-5a97a0e6-6081-4127-8553-ffa60f98a38b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3620104130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.3620104130
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.2470779523
Short name T844
Test name
Test status
Simulation time 11925542136 ps
CPU time 146.13 seconds
Started Aug 07 06:10:34 PM PDT 24
Finished Aug 07 06:13:00 PM PDT 24
Peak memory 207212 kb
Host smart-3ee43202-c559-4e90-8473-58dafa5906a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2470779523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.2470779523
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.3232788049
Short name T1063
Test name
Test status
Simulation time 233080643 ps
CPU time 0.99 seconds
Started Aug 07 06:10:35 PM PDT 24
Finished Aug 07 06:10:36 PM PDT 24
Peak memory 207044 kb
Host smart-ec24d951-2fe3-41f6-8999-56822db9b738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32327
88049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3232788049
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.788921532
Short name T1923
Test name
Test status
Simulation time 28319635075 ps
CPU time 43.59 seconds
Started Aug 07 06:10:34 PM PDT 24
Finished Aug 07 06:11:18 PM PDT 24
Peak memory 207308 kb
Host smart-7733849a-e2a8-4a68-a9a7-424322522e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78892
1532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.788921532
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2532639149
Short name T119
Test name
Test status
Simulation time 4392336065 ps
CPU time 6.58 seconds
Started Aug 07 06:10:32 PM PDT 24
Finished Aug 07 06:10:38 PM PDT 24
Peak memory 216360 kb
Host smart-24d8fe29-1a4c-4399-a0d3-a09ff4e03c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25326
39149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2532639149
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.3063389188
Short name T1144
Test name
Test status
Simulation time 4804996870 ps
CPU time 50.02 seconds
Started Aug 07 06:10:32 PM PDT 24
Finished Aug 07 06:11:22 PM PDT 24
Peak memory 218144 kb
Host smart-713908dc-d42e-48e7-b965-f7b5619782aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30633
89188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.3063389188
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1938139361
Short name T763
Test name
Test status
Simulation time 2845341772 ps
CPU time 22.7 seconds
Started Aug 07 06:10:34 PM PDT 24
Finished Aug 07 06:10:57 PM PDT 24
Peak memory 217328 kb
Host smart-edce1895-bf78-4c23-854c-205fb18261fc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1938139361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1938139361
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.2072878958
Short name T1229
Test name
Test status
Simulation time 239089905 ps
CPU time 0.99 seconds
Started Aug 07 06:10:32 PM PDT 24
Finished Aug 07 06:10:34 PM PDT 24
Peak memory 207020 kb
Host smart-84486264-fed1-46b4-be1c-358864dab526
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2072878958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.2072878958
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2019268209
Short name T2080
Test name
Test status
Simulation time 198460993 ps
CPU time 0.95 seconds
Started Aug 07 06:10:34 PM PDT 24
Finished Aug 07 06:10:35 PM PDT 24
Peak memory 206988 kb
Host smart-11d2fa72-5cfe-4259-bd3a-201426c7cfec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20192
68209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2019268209
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.3293918502
Short name T1328
Test name
Test status
Simulation time 2083126441 ps
CPU time 20.43 seconds
Started Aug 07 06:10:35 PM PDT 24
Finished Aug 07 06:10:55 PM PDT 24
Peak memory 216736 kb
Host smart-21542663-3d32-454e-9246-a4eb946f8a05
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3293918502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.3293918502
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.3447761850
Short name T2191
Test name
Test status
Simulation time 177419691 ps
CPU time 0.83 seconds
Started Aug 07 06:10:36 PM PDT 24
Finished Aug 07 06:10:37 PM PDT 24
Peak memory 206956 kb
Host smart-2d74b4c5-ea48-4ac8-a7a5-aaa201ba34a0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3447761850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.3447761850
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1340933238
Short name T1648
Test name
Test status
Simulation time 227235574 ps
CPU time 0.95 seconds
Started Aug 07 06:10:33 PM PDT 24
Finished Aug 07 06:10:34 PM PDT 24
Peak memory 206980 kb
Host smart-84d63b78-656e-42c6-b9b1-7e5653a41264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13409
33238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1340933238
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.198134574
Short name T2134
Test name
Test status
Simulation time 206533927 ps
CPU time 0.91 seconds
Started Aug 07 06:10:34 PM PDT 24
Finished Aug 07 06:10:35 PM PDT 24
Peak memory 206904 kb
Host smart-475f2bbf-f070-472b-91fa-d38435e73c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19813
4574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.198134574
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2824658490
Short name T1558
Test name
Test status
Simulation time 203586584 ps
CPU time 0.95 seconds
Started Aug 07 06:10:32 PM PDT 24
Finished Aug 07 06:10:33 PM PDT 24
Peak memory 206988 kb
Host smart-b6d27c6d-a18f-4684-ab4c-6207d4b14ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28246
58490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2824658490
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2007757629
Short name T643
Test name
Test status
Simulation time 175796605 ps
CPU time 0.96 seconds
Started Aug 07 06:10:34 PM PDT 24
Finished Aug 07 06:10:35 PM PDT 24
Peak memory 206944 kb
Host smart-e109e6e4-5d7a-4bf3-99d4-9090b033f095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20077
57629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2007757629
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1317538966
Short name T771
Test name
Test status
Simulation time 193052288 ps
CPU time 0.88 seconds
Started Aug 07 06:10:31 PM PDT 24
Finished Aug 07 06:10:32 PM PDT 24
Peak memory 207000 kb
Host smart-555b748a-ebcd-4ef7-8c23-0d0165b228ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13175
38966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1317538966
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2068906658
Short name T1346
Test name
Test status
Simulation time 153570967 ps
CPU time 0.81 seconds
Started Aug 07 06:10:35 PM PDT 24
Finished Aug 07 06:10:35 PM PDT 24
Peak memory 206972 kb
Host smart-efc79577-c1fd-4d32-93d8-093ca31f09da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20689
06658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2068906658
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.946146156
Short name T807
Test name
Test status
Simulation time 251642139 ps
CPU time 1.04 seconds
Started Aug 07 06:10:32 PM PDT 24
Finished Aug 07 06:10:33 PM PDT 24
Peak memory 207028 kb
Host smart-a2079b34-8b9e-494e-8418-7d970592327c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=946146156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.946146156
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1578683761
Short name T2131
Test name
Test status
Simulation time 150051676 ps
CPU time 0.88 seconds
Started Aug 07 06:10:35 PM PDT 24
Finished Aug 07 06:10:36 PM PDT 24
Peak memory 207004 kb
Host smart-5e0c710a-120a-411a-83a0-67f365a93528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15786
83761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1578683761
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2793448122
Short name T2008
Test name
Test status
Simulation time 38596037 ps
CPU time 0.71 seconds
Started Aug 07 06:10:35 PM PDT 24
Finished Aug 07 06:10:36 PM PDT 24
Peak memory 206956 kb
Host smart-1f523449-70a8-409d-a006-9aa78cd3cd1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27934
48122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2793448122
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2951913353
Short name T1122
Test name
Test status
Simulation time 17557111086 ps
CPU time 44.93 seconds
Started Aug 07 06:10:32 PM PDT 24
Finished Aug 07 06:11:17 PM PDT 24
Peak memory 215464 kb
Host smart-9fb6a6cb-e87c-429e-85fe-93933154c29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29519
13353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2951913353
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.754572015
Short name T790
Test name
Test status
Simulation time 144192897 ps
CPU time 0.83 seconds
Started Aug 07 06:10:42 PM PDT 24
Finished Aug 07 06:10:43 PM PDT 24
Peak memory 207032 kb
Host smart-7bfa4c2e-2a6b-4645-a2e5-05e3a6714e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75457
2015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.754572015
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1734937620
Short name T2371
Test name
Test status
Simulation time 246525347 ps
CPU time 1.03 seconds
Started Aug 07 06:10:32 PM PDT 24
Finished Aug 07 06:10:33 PM PDT 24
Peak memory 206992 kb
Host smart-e978d327-eabf-4052-b38f-98dafa280113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17349
37620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1734937620
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3473488174
Short name T2221
Test name
Test status
Simulation time 208975401 ps
CPU time 0.94 seconds
Started Aug 07 06:10:41 PM PDT 24
Finished Aug 07 06:10:42 PM PDT 24
Peak memory 206988 kb
Host smart-e13cf3da-11ec-4722-99b4-445ff324cc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34734
88174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3473488174
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.4219111534
Short name T1548
Test name
Test status
Simulation time 196996081 ps
CPU time 1.07 seconds
Started Aug 07 06:10:41 PM PDT 24
Finished Aug 07 06:10:42 PM PDT 24
Peak memory 207000 kb
Host smart-e65b6abb-7796-4f8f-ae9c-b6069acbc4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42191
11534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.4219111534
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.4118847364
Short name T1847
Test name
Test status
Simulation time 215224003 ps
CPU time 0.89 seconds
Started Aug 07 06:10:40 PM PDT 24
Finished Aug 07 06:10:41 PM PDT 24
Peak memory 206980 kb
Host smart-4ffc453a-d353-4dd7-a117-cce1fc492a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41188
47364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.4118847364
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_rx_full.1743759602
Short name T2476
Test name
Test status
Simulation time 277192403 ps
CPU time 1.14 seconds
Started Aug 07 06:10:40 PM PDT 24
Finished Aug 07 06:10:41 PM PDT 24
Peak memory 206960 kb
Host smart-992c93a2-a2a7-46d2-829a-a51cdca9ff14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17437
59602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.1743759602
Directory /workspace/41.usbdev_rx_full/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3031779921
Short name T2130
Test name
Test status
Simulation time 228886301 ps
CPU time 0.97 seconds
Started Aug 07 06:10:40 PM PDT 24
Finished Aug 07 06:10:41 PM PDT 24
Peak memory 206956 kb
Host smart-a967f708-a366-44e5-8aa8-99c952f3d6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30317
79921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3031779921
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3012155570
Short name T1485
Test name
Test status
Simulation time 168926571 ps
CPU time 0.91 seconds
Started Aug 07 06:10:39 PM PDT 24
Finished Aug 07 06:10:40 PM PDT 24
Peak memory 206972 kb
Host smart-88a68524-101d-4b2d-974b-8aa8107bad17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30121
55570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3012155570
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.605356837
Short name T1650
Test name
Test status
Simulation time 207323781 ps
CPU time 0.97 seconds
Started Aug 07 06:10:39 PM PDT 24
Finished Aug 07 06:10:40 PM PDT 24
Peak memory 207004 kb
Host smart-2bc45669-c07a-4c4e-a246-a5b7f505449c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60535
6837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.605356837
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2944899217
Short name T2661
Test name
Test status
Simulation time 1770225542 ps
CPU time 13.39 seconds
Started Aug 07 06:10:40 PM PDT 24
Finished Aug 07 06:10:54 PM PDT 24
Peak memory 223468 kb
Host smart-fac8e646-0efe-424f-8773-5aeed41e51ab
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2944899217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2944899217
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2432552354
Short name T130
Test name
Test status
Simulation time 176859094 ps
CPU time 0.86 seconds
Started Aug 07 06:10:39 PM PDT 24
Finished Aug 07 06:10:40 PM PDT 24
Peak memory 206980 kb
Host smart-d9938030-d8f4-411f-8fb3-861a8f129800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24325
52354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2432552354
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2821231083
Short name T528
Test name
Test status
Simulation time 147228738 ps
CPU time 0.88 seconds
Started Aug 07 06:10:39 PM PDT 24
Finished Aug 07 06:10:40 PM PDT 24
Peak memory 207040 kb
Host smart-fee5078d-9eaa-4bfc-b395-1140c7c630e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28212
31083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2821231083
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.2465130493
Short name T2446
Test name
Test status
Simulation time 1209558831 ps
CPU time 2.86 seconds
Started Aug 07 06:10:46 PM PDT 24
Finished Aug 07 06:10:49 PM PDT 24
Peak memory 207108 kb
Host smart-05b0e2e1-aefc-4b47-9d7b-84b06249c953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24651
30493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.2465130493
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.3495804140
Short name T1463
Test name
Test status
Simulation time 3519845662 ps
CPU time 34.89 seconds
Started Aug 07 06:10:45 PM PDT 24
Finished Aug 07 06:11:20 PM PDT 24
Peak memory 215484 kb
Host smart-7a3f0134-4385-40fd-a4b3-a48ab239640c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34958
04140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3495804140
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.731517253
Short name T573
Test name
Test status
Simulation time 275525306 ps
CPU time 4.39 seconds
Started Aug 07 06:10:36 PM PDT 24
Finished Aug 07 06:10:40 PM PDT 24
Peak memory 207136 kb
Host smart-19b8ce9a-4864-40d5-aeae-5c92d9dd8862
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731517253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_host
_handshake.731517253
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2769239021
Short name T968
Test name
Test status
Simulation time 64428967 ps
CPU time 0.7 seconds
Started Aug 07 06:11:11 PM PDT 24
Finished Aug 07 06:11:12 PM PDT 24
Peak memory 207096 kb
Host smart-c653f320-eb6a-4a07-8464-7db2ce625f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2769239021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2769239021
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3500592791
Short name T1425
Test name
Test status
Simulation time 9494984210 ps
CPU time 13.47 seconds
Started Aug 07 06:10:46 PM PDT 24
Finished Aug 07 06:11:00 PM PDT 24
Peak memory 207240 kb
Host smart-9b845ca9-77ab-4a6c-8470-fda9c83a897e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500592791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.3500592791
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3456756586
Short name T2887
Test name
Test status
Simulation time 14206354034 ps
CPU time 18.75 seconds
Started Aug 07 06:10:41 PM PDT 24
Finished Aug 07 06:11:00 PM PDT 24
Peak memory 215368 kb
Host smart-9cb5f0de-0873-4baf-aead-001f386ab467
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456756586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3456756586
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1444444165
Short name T1791
Test name
Test status
Simulation time 23848193029 ps
CPU time 27.88 seconds
Started Aug 07 06:10:51 PM PDT 24
Finished Aug 07 06:11:19 PM PDT 24
Peak memory 215468 kb
Host smart-4d7b0715-2602-4ca8-9786-d93e6019f791
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444444165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.1444444165
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2038142173
Short name T591
Test name
Test status
Simulation time 158770472 ps
CPU time 0.84 seconds
Started Aug 07 06:10:47 PM PDT 24
Finished Aug 07 06:10:48 PM PDT 24
Peak memory 206980 kb
Host smart-fe514c2f-b970-4bba-ae7c-b2fdd50234a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20381
42173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2038142173
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.833274140
Short name T2470
Test name
Test status
Simulation time 149529519 ps
CPU time 0.84 seconds
Started Aug 07 06:10:47 PM PDT 24
Finished Aug 07 06:10:48 PM PDT 24
Peak memory 207020 kb
Host smart-9f8ade44-d74a-457d-b538-f9657291d4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83327
4140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.833274140
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.948871480
Short name T2282
Test name
Test status
Simulation time 241516389 ps
CPU time 1.07 seconds
Started Aug 07 06:10:47 PM PDT 24
Finished Aug 07 06:10:49 PM PDT 24
Peak memory 206904 kb
Host smart-4825f7e1-3a35-46fe-9db5-4812c81c0041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94887
1480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.948871480
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.948210053
Short name T1250
Test name
Test status
Simulation time 1116609856 ps
CPU time 2.96 seconds
Started Aug 07 06:10:51 PM PDT 24
Finished Aug 07 06:10:54 PM PDT 24
Peak memory 207256 kb
Host smart-6ece032d-6848-4d2e-a5dc-3e4b314f2fd6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=948210053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.948210053
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.1898019408
Short name T1734
Test name
Test status
Simulation time 29373953181 ps
CPU time 42.55 seconds
Started Aug 07 06:10:47 PM PDT 24
Finished Aug 07 06:11:30 PM PDT 24
Peak memory 207304 kb
Host smart-2cc68671-bbdd-458f-8c0d-5471f7cf1647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18980
19408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1898019408
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.3535210241
Short name T832
Test name
Test status
Simulation time 3915994431 ps
CPU time 32.45 seconds
Started Aug 07 06:10:47 PM PDT 24
Finished Aug 07 06:11:20 PM PDT 24
Peak memory 207292 kb
Host smart-9ccfa890-efa0-4752-9ba1-d4684cf7b72e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535210241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.3535210241
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.2302085851
Short name T2236
Test name
Test status
Simulation time 1202758162 ps
CPU time 2.47 seconds
Started Aug 07 06:10:53 PM PDT 24
Finished Aug 07 06:10:55 PM PDT 24
Peak memory 206984 kb
Host smart-dd3b842c-c8f0-4b57-a82e-ea5d9ea7c21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23020
85851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.2302085851
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2711678906
Short name T2520
Test name
Test status
Simulation time 138011790 ps
CPU time 0.82 seconds
Started Aug 07 06:10:50 PM PDT 24
Finished Aug 07 06:10:51 PM PDT 24
Peak memory 206972 kb
Host smart-9e545725-70f2-4ec0-a606-d1a99347eef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27116
78906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2711678906
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.240867601
Short name T853
Test name
Test status
Simulation time 34337891 ps
CPU time 0.69 seconds
Started Aug 07 06:10:49 PM PDT 24
Finished Aug 07 06:10:49 PM PDT 24
Peak memory 206912 kb
Host smart-753b717b-5bdc-40d2-ba86-00f051197a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24086
7601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.240867601
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.1375645060
Short name T532
Test name
Test status
Simulation time 802314575 ps
CPU time 2.27 seconds
Started Aug 07 06:10:47 PM PDT 24
Finished Aug 07 06:10:50 PM PDT 24
Peak memory 207160 kb
Host smart-5cb64e2a-1d5c-40d9-a37e-fbf983bc603c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13756
45060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.1375645060
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_types.3766522914
Short name T2892
Test name
Test status
Simulation time 548869040 ps
CPU time 1.59 seconds
Started Aug 07 06:10:45 PM PDT 24
Finished Aug 07 06:10:47 PM PDT 24
Peak memory 206896 kb
Host smart-1115fb41-255f-4dba-b42e-6c78076013a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3766522914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.3766522914
Directory /workspace/42.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.509846824
Short name T905
Test name
Test status
Simulation time 170553543 ps
CPU time 1.86 seconds
Started Aug 07 06:10:52 PM PDT 24
Finished Aug 07 06:10:54 PM PDT 24
Peak memory 207132 kb
Host smart-71e53aca-6df8-4228-9da2-9d8ad31f0df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50984
6824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.509846824
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.896749950
Short name T2732
Test name
Test status
Simulation time 170424285 ps
CPU time 1.01 seconds
Started Aug 07 06:10:45 PM PDT 24
Finished Aug 07 06:10:46 PM PDT 24
Peak memory 206996 kb
Host smart-7a66e39b-d4b7-480d-ad28-a930f4d8ef2c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=896749950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.896749950
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.335672837
Short name T1627
Test name
Test status
Simulation time 145989681 ps
CPU time 0.86 seconds
Started Aug 07 06:10:49 PM PDT 24
Finished Aug 07 06:10:50 PM PDT 24
Peak memory 206972 kb
Host smart-e95209a8-697d-4c0b-8614-cd368e2454af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33567
2837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.335672837
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.3356444516
Short name T2564
Test name
Test status
Simulation time 160238395 ps
CPU time 0.89 seconds
Started Aug 07 06:10:54 PM PDT 24
Finished Aug 07 06:10:55 PM PDT 24
Peak memory 206988 kb
Host smart-02782772-d1d7-46ba-b1e9-2924e0513d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33564
44516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3356444516
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.3761226101
Short name T1042
Test name
Test status
Simulation time 5152756246 ps
CPU time 155.04 seconds
Started Aug 07 06:10:46 PM PDT 24
Finished Aug 07 06:13:21 PM PDT 24
Peak memory 217780 kb
Host smart-bae62fcd-e3f9-4df4-8988-4e9b87d816f8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3761226101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.3761226101
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.881654758
Short name T784
Test name
Test status
Simulation time 11638649202 ps
CPU time 82.16 seconds
Started Aug 07 06:10:48 PM PDT 24
Finished Aug 07 06:12:10 PM PDT 24
Peak memory 207280 kb
Host smart-68294e7a-cbc0-49f9-ac88-1e56f8a8b745
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=881654758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.881654758
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.962770674
Short name T2439
Test name
Test status
Simulation time 174601799 ps
CPU time 0.9 seconds
Started Aug 07 06:10:57 PM PDT 24
Finished Aug 07 06:10:58 PM PDT 24
Peak memory 206952 kb
Host smart-21da438f-d5ac-44c7-8a72-f4d8fdbd1fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96277
0674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.962770674
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1996733161
Short name T1046
Test name
Test status
Simulation time 7400421731 ps
CPU time 11.43 seconds
Started Aug 07 06:10:59 PM PDT 24
Finished Aug 07 06:11:11 PM PDT 24
Peak memory 207492 kb
Host smart-db8970d2-4f37-48bf-8411-0d9505c3bdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19967
33161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1996733161
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.3394375814
Short name T843
Test name
Test status
Simulation time 9995461409 ps
CPU time 12.67 seconds
Started Aug 07 06:10:56 PM PDT 24
Finished Aug 07 06:11:09 PM PDT 24
Peak memory 207268 kb
Host smart-d5a00e66-0344-4cc5-81d3-39fc261b3147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33943
75814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.3394375814
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.176193381
Short name T1982
Test name
Test status
Simulation time 3494592171 ps
CPU time 25.93 seconds
Started Aug 07 06:10:56 PM PDT 24
Finished Aug 07 06:11:22 PM PDT 24
Peak memory 223644 kb
Host smart-b32db95c-a293-429a-9e0d-392bdd657ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17619
3381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.176193381
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3246038946
Short name T2577
Test name
Test status
Simulation time 2416231845 ps
CPU time 68.58 seconds
Started Aug 07 06:10:56 PM PDT 24
Finished Aug 07 06:12:05 PM PDT 24
Peak memory 215468 kb
Host smart-d3cb6946-edb9-4138-b3f3-add692594e4b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3246038946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3246038946
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.3590529333
Short name T1785
Test name
Test status
Simulation time 274945184 ps
CPU time 1.05 seconds
Started Aug 07 06:11:01 PM PDT 24
Finished Aug 07 06:11:02 PM PDT 24
Peak memory 206856 kb
Host smart-22de2d81-83fb-42c6-8a5d-78aa3291eb4e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3590529333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.3590529333
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2466598666
Short name T2555
Test name
Test status
Simulation time 227058423 ps
CPU time 0.99 seconds
Started Aug 07 06:10:57 PM PDT 24
Finished Aug 07 06:10:58 PM PDT 24
Peak memory 206988 kb
Host smart-fc9029e6-b306-4269-b061-bc97a5c42952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24665
98666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2466598666
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.403095938
Short name T2284
Test name
Test status
Simulation time 2632138278 ps
CPU time 74.98 seconds
Started Aug 07 06:10:56 PM PDT 24
Finished Aug 07 06:12:11 PM PDT 24
Peak memory 215480 kb
Host smart-b83c0d44-4ef4-424b-a347-cc83180555d6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=403095938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.403095938
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.4016880994
Short name T991
Test name
Test status
Simulation time 154209865 ps
CPU time 0.83 seconds
Started Aug 07 06:10:58 PM PDT 24
Finished Aug 07 06:10:59 PM PDT 24
Peak memory 206984 kb
Host smart-b6b42efd-5746-4897-8412-6ceed0311563
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4016880994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.4016880994
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3443850188
Short name T592
Test name
Test status
Simulation time 144564842 ps
CPU time 0.83 seconds
Started Aug 07 06:10:56 PM PDT 24
Finished Aug 07 06:10:57 PM PDT 24
Peak memory 207016 kb
Host smart-3a4a0ed3-51e5-440e-a727-8aafa084c45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34438
50188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3443850188
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1346340789
Short name T149
Test name
Test status
Simulation time 231570125 ps
CPU time 0.99 seconds
Started Aug 07 06:10:55 PM PDT 24
Finished Aug 07 06:10:56 PM PDT 24
Peak memory 206996 kb
Host smart-b002cd56-ff12-42f9-b523-7c2301b7431c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13463
40789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1346340789
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.4164131938
Short name T810
Test name
Test status
Simulation time 169140030 ps
CPU time 0.91 seconds
Started Aug 07 06:10:56 PM PDT 24
Finished Aug 07 06:10:57 PM PDT 24
Peak memory 207012 kb
Host smart-6fa2470b-d631-4eaf-9273-ec83fe32979d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41641
31938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.4164131938
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.4058045724
Short name T841
Test name
Test status
Simulation time 163364201 ps
CPU time 0.86 seconds
Started Aug 07 06:10:58 PM PDT 24
Finished Aug 07 06:10:59 PM PDT 24
Peak memory 206948 kb
Host smart-959dccfc-691d-4eff-8377-ae1b1d2cea01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40580
45724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.4058045724
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2099250825
Short name T2723
Test name
Test status
Simulation time 175382996 ps
CPU time 0.89 seconds
Started Aug 07 06:10:55 PM PDT 24
Finished Aug 07 06:10:56 PM PDT 24
Peak memory 206980 kb
Host smart-0c1c08f7-952f-471f-aaa4-77076c71ab7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20992
50825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2099250825
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.508197064
Short name T3
Test name
Test status
Simulation time 150749793 ps
CPU time 0.85 seconds
Started Aug 07 06:11:01 PM PDT 24
Finished Aug 07 06:11:02 PM PDT 24
Peak memory 206832 kb
Host smart-67a7f517-c978-46a2-8cc6-dcd98d011196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50819
7064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.508197064
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.960313393
Short name T547
Test name
Test status
Simulation time 215655788 ps
CPU time 1.03 seconds
Started Aug 07 06:10:55 PM PDT 24
Finished Aug 07 06:10:56 PM PDT 24
Peak memory 207028 kb
Host smart-ff04e432-36ca-4ca0-966d-f252d26d4de5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=960313393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.960313393
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2710493311
Short name T3061
Test name
Test status
Simulation time 178536071 ps
CPU time 0.87 seconds
Started Aug 07 06:10:55 PM PDT 24
Finished Aug 07 06:10:55 PM PDT 24
Peak memory 206876 kb
Host smart-86647386-c24b-4b7f-ab43-e9220df7e875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27104
93311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2710493311
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1010354525
Short name T969
Test name
Test status
Simulation time 53651786 ps
CPU time 0.72 seconds
Started Aug 07 06:10:55 PM PDT 24
Finished Aug 07 06:10:56 PM PDT 24
Peak memory 206960 kb
Host smart-04a17795-dec1-418e-a3e2-b7c7918d4ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10103
54525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1010354525
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2674469379
Short name T292
Test name
Test status
Simulation time 22129474521 ps
CPU time 62.57 seconds
Started Aug 07 06:10:57 PM PDT 24
Finished Aug 07 06:11:59 PM PDT 24
Peak memory 220440 kb
Host smart-e91c7448-0d1e-4482-9f39-dd5c6c27593a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26744
69379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2674469379
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3780038445
Short name T1019
Test name
Test status
Simulation time 188662509 ps
CPU time 0.89 seconds
Started Aug 07 06:11:00 PM PDT 24
Finished Aug 07 06:11:01 PM PDT 24
Peak memory 206936 kb
Host smart-2b131de7-d206-4d2a-9fb9-5e7e5711d712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37800
38445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3780038445
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.311267237
Short name T1616
Test name
Test status
Simulation time 194230840 ps
CPU time 0.89 seconds
Started Aug 07 06:10:55 PM PDT 24
Finished Aug 07 06:10:56 PM PDT 24
Peak memory 206956 kb
Host smart-f5f6fd0a-adc4-4eff-89c5-302789d82acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31126
7237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.311267237
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.321261820
Short name T1547
Test name
Test status
Simulation time 155099099 ps
CPU time 0.88 seconds
Started Aug 07 06:10:56 PM PDT 24
Finished Aug 07 06:10:57 PM PDT 24
Peak memory 207016 kb
Host smart-0ebdb8fd-d1b5-4c62-98df-a8de0c148d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32126
1820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.321261820
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3974760215
Short name T2877
Test name
Test status
Simulation time 162208011 ps
CPU time 0.85 seconds
Started Aug 07 06:10:58 PM PDT 24
Finished Aug 07 06:10:59 PM PDT 24
Peak memory 206948 kb
Host smart-e45480ce-f2de-44cb-991b-885d22f1b9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39747
60215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3974760215
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3439407035
Short name T2921
Test name
Test status
Simulation time 166624123 ps
CPU time 0.89 seconds
Started Aug 07 06:11:08 PM PDT 24
Finished Aug 07 06:11:09 PM PDT 24
Peak memory 206992 kb
Host smart-800d1a08-2170-403b-9ceb-c113fd53c9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34394
07035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3439407035
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_rx_full.739711404
Short name T3111
Test name
Test status
Simulation time 244113143 ps
CPU time 1.08 seconds
Started Aug 07 06:11:10 PM PDT 24
Finished Aug 07 06:11:12 PM PDT 24
Peak memory 206972 kb
Host smart-1ef0bb26-f3ab-4677-a19b-a924f14bb4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73971
1404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.739711404
Directory /workspace/42.usbdev_rx_full/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3397407461
Short name T2655
Test name
Test status
Simulation time 192400116 ps
CPU time 0.89 seconds
Started Aug 07 06:11:06 PM PDT 24
Finished Aug 07 06:11:07 PM PDT 24
Peak memory 206872 kb
Host smart-49dfcd39-2ec0-4bcc-b464-a1f0968573b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33974
07461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3397407461
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.527644041
Short name T747
Test name
Test status
Simulation time 168108695 ps
CPU time 0.89 seconds
Started Aug 07 06:11:07 PM PDT 24
Finished Aug 07 06:11:08 PM PDT 24
Peak memory 206960 kb
Host smart-13e16bc2-4f09-4eb2-ab14-47b675276a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52764
4041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.527644041
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.173401958
Short name T724
Test name
Test status
Simulation time 186929091 ps
CPU time 0.96 seconds
Started Aug 07 06:11:11 PM PDT 24
Finished Aug 07 06:11:12 PM PDT 24
Peak memory 206984 kb
Host smart-ba5794ca-2308-45d1-8eb8-d9d885d83ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17340
1958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.173401958
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.3294104847
Short name T854
Test name
Test status
Simulation time 3366643452 ps
CPU time 32.2 seconds
Started Aug 07 06:11:10 PM PDT 24
Finished Aug 07 06:11:42 PM PDT 24
Peak memory 223696 kb
Host smart-4b8a3ba8-2972-4bf7-b86d-a1236926b860
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3294104847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.3294104847
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.768030142
Short name T2089
Test name
Test status
Simulation time 157619410 ps
CPU time 0.85 seconds
Started Aug 07 06:11:05 PM PDT 24
Finished Aug 07 06:11:06 PM PDT 24
Peak memory 207012 kb
Host smart-86bddae3-0ba5-4cf9-a313-65549d911d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76803
0142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.768030142
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.4251133168
Short name T1210
Test name
Test status
Simulation time 208448472 ps
CPU time 0.91 seconds
Started Aug 07 06:11:07 PM PDT 24
Finished Aug 07 06:11:08 PM PDT 24
Peak memory 207008 kb
Host smart-497df069-6c55-470b-b5d3-4066a860eb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42511
33168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.4251133168
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.2104542292
Short name T1698
Test name
Test status
Simulation time 289300219 ps
CPU time 1.11 seconds
Started Aug 07 06:11:04 PM PDT 24
Finished Aug 07 06:11:05 PM PDT 24
Peak memory 206932 kb
Host smart-a8d49ba2-fc14-4de7-b98e-a55d81079603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21045
42292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.2104542292
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2768893777
Short name T2647
Test name
Test status
Simulation time 2246165264 ps
CPU time 17.52 seconds
Started Aug 07 06:11:08 PM PDT 24
Finished Aug 07 06:11:25 PM PDT 24
Peak memory 223640 kb
Host smart-51bc78a8-281e-40d9-9924-29cf1ecc57c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27688
93777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2768893777
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.221821716
Short name T1613
Test name
Test status
Simulation time 623271882 ps
CPU time 5.15 seconds
Started Aug 07 06:10:49 PM PDT 24
Finished Aug 07 06:10:54 PM PDT 24
Peak memory 207404 kb
Host smart-8fcbae3e-d82c-4e70-a187-66422750f221
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221821716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_host
_handshake.221821716
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.3765143446
Short name T236
Test name
Test status
Simulation time 77369005 ps
CPU time 0.72 seconds
Started Aug 07 06:11:15 PM PDT 24
Finished Aug 07 06:11:16 PM PDT 24
Peak memory 207068 kb
Host smart-7b3221aa-cdec-4b04-a3a5-92b80c5b3041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3765143446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.3765143446
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.2269897387
Short name T1309
Test name
Test status
Simulation time 5283343071 ps
CPU time 7.37 seconds
Started Aug 07 06:11:07 PM PDT 24
Finished Aug 07 06:11:15 PM PDT 24
Peak memory 215408 kb
Host smart-aa0b60dd-7e91-4f03-a3b6-7a0d774821a2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269897387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.2269897387
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.4191879974
Short name T796
Test name
Test status
Simulation time 19048337638 ps
CPU time 27.69 seconds
Started Aug 07 06:11:08 PM PDT 24
Finished Aug 07 06:11:35 PM PDT 24
Peak memory 207268 kb
Host smart-64dd5249-0cd9-4d8f-88fe-f2b5a4fa354d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191879974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.4191879974
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.2421205342
Short name T861
Test name
Test status
Simulation time 24531093048 ps
CPU time 31.38 seconds
Started Aug 07 06:11:08 PM PDT 24
Finished Aug 07 06:11:39 PM PDT 24
Peak memory 215472 kb
Host smart-12338230-adb1-4960-8b64-236f90f4a398
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421205342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.2421205342
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.32734303
Short name T2220
Test name
Test status
Simulation time 185106864 ps
CPU time 0.89 seconds
Started Aug 07 06:11:08 PM PDT 24
Finished Aug 07 06:11:09 PM PDT 24
Peak memory 206908 kb
Host smart-fb6ec107-4198-4242-bbdf-f309542575aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32734
303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.32734303
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.416937196
Short name T2945
Test name
Test status
Simulation time 159233201 ps
CPU time 0.88 seconds
Started Aug 07 06:11:09 PM PDT 24
Finished Aug 07 06:11:10 PM PDT 24
Peak memory 207004 kb
Host smart-2a71e0da-402c-4e89-822f-ac7fcaabf4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41693
7196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.416937196
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2098784945
Short name T2783
Test name
Test status
Simulation time 410535506 ps
CPU time 1.46 seconds
Started Aug 07 06:11:10 PM PDT 24
Finished Aug 07 06:11:12 PM PDT 24
Peak memory 206984 kb
Host smart-e7d9894a-1ad9-4676-a6f8-a29dae21dc9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20987
84945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2098784945
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1776100310
Short name T1412
Test name
Test status
Simulation time 684632312 ps
CPU time 1.96 seconds
Started Aug 07 06:11:06 PM PDT 24
Finished Aug 07 06:11:08 PM PDT 24
Peak memory 206984 kb
Host smart-873ef4e1-9554-4db3-887d-efd942cbeb7d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1776100310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1776100310
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.2197488728
Short name T2181
Test name
Test status
Simulation time 40692035260 ps
CPU time 62.65 seconds
Started Aug 07 06:11:10 PM PDT 24
Finished Aug 07 06:12:12 PM PDT 24
Peak memory 207296 kb
Host smart-b361e1d7-6822-416a-9a75-6097314ab991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21974
88728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2197488728
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.1798898797
Short name T57
Test name
Test status
Simulation time 1957995285 ps
CPU time 48.57 seconds
Started Aug 07 06:11:06 PM PDT 24
Finished Aug 07 06:11:55 PM PDT 24
Peak memory 207144 kb
Host smart-854bc0b3-e7c1-4f3d-8357-81c1d34ba291
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798898797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.1798898797
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.699101349
Short name T1368
Test name
Test status
Simulation time 870287813 ps
CPU time 2.12 seconds
Started Aug 07 06:11:08 PM PDT 24
Finished Aug 07 06:11:11 PM PDT 24
Peak memory 206832 kb
Host smart-e86782b2-83dd-4e73-a4d9-8f929a3e9eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69910
1349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.699101349
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3055722506
Short name T1255
Test name
Test status
Simulation time 164924740 ps
CPU time 0.85 seconds
Started Aug 07 06:11:07 PM PDT 24
Finished Aug 07 06:11:08 PM PDT 24
Peak memory 206940 kb
Host smart-29f4d6a0-baef-4c23-9e77-e7b012e29100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30557
22506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3055722506
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1777735187
Short name T3091
Test name
Test status
Simulation time 106182857 ps
CPU time 0.79 seconds
Started Aug 07 06:11:06 PM PDT 24
Finished Aug 07 06:11:07 PM PDT 24
Peak memory 206980 kb
Host smart-5b66ba0f-6f94-4afd-8360-d5842e45d45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17777
35187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1777735187
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1680893420
Short name T2042
Test name
Test status
Simulation time 957411727 ps
CPU time 2.48 seconds
Started Aug 07 06:11:03 PM PDT 24
Finished Aug 07 06:11:06 PM PDT 24
Peak memory 207164 kb
Host smart-9111c380-9540-42a2-aa71-1a879bc63613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16808
93420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1680893420
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_types.2901933619
Short name T400
Test name
Test status
Simulation time 817031346 ps
CPU time 1.87 seconds
Started Aug 07 06:11:07 PM PDT 24
Finished Aug 07 06:11:09 PM PDT 24
Peak memory 206948 kb
Host smart-37bb86a9-38a0-4115-a5fd-ae636efa7d1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2901933619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.2901933619
Directory /workspace/43.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.617410695
Short name T1100
Test name
Test status
Simulation time 398299091 ps
CPU time 2.9 seconds
Started Aug 07 06:11:08 PM PDT 24
Finished Aug 07 06:11:11 PM PDT 24
Peak memory 207112 kb
Host smart-358c4a15-73aa-4848-87a3-7ed1100fb815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61741
0695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.617410695
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.1723918439
Short name T515
Test name
Test status
Simulation time 221291876 ps
CPU time 1.06 seconds
Started Aug 07 06:11:10 PM PDT 24
Finished Aug 07 06:11:12 PM PDT 24
Peak memory 207180 kb
Host smart-aec79054-7adb-450f-a637-f16fbc82de4e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1723918439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.1723918439
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3073268420
Short name T2761
Test name
Test status
Simulation time 200327567 ps
CPU time 0.92 seconds
Started Aug 07 06:11:09 PM PDT 24
Finished Aug 07 06:11:10 PM PDT 24
Peak memory 206940 kb
Host smart-5ec74b53-09aa-4d3a-a618-57420b49e49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30732
68420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3073268420
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.4079365775
Short name T234
Test name
Test status
Simulation time 212973059 ps
CPU time 0.96 seconds
Started Aug 07 06:11:06 PM PDT 24
Finished Aug 07 06:11:07 PM PDT 24
Peak memory 206988 kb
Host smart-37d9eaec-23fd-4ecd-9456-d8a126077c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40793
65775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.4079365775
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.2584117586
Short name T2554
Test name
Test status
Simulation time 4212183930 ps
CPU time 41.98 seconds
Started Aug 07 06:11:07 PM PDT 24
Finished Aug 07 06:11:49 PM PDT 24
Peak memory 223532 kb
Host smart-af73724c-0cd6-47a9-8067-adbffe7c1895
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2584117586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.2584117586
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.895189127
Short name T1076
Test name
Test status
Simulation time 161397718 ps
CPU time 0.92 seconds
Started Aug 07 06:11:11 PM PDT 24
Finished Aug 07 06:11:12 PM PDT 24
Peak memory 206984 kb
Host smart-1a88a65c-a637-4888-8104-379a4a1206b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89518
9127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.895189127
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1010076896
Short name T2077
Test name
Test status
Simulation time 28642767541 ps
CPU time 45.44 seconds
Started Aug 07 06:11:08 PM PDT 24
Finished Aug 07 06:11:54 PM PDT 24
Peak memory 215588 kb
Host smart-d1a227c9-38f1-42b6-925f-5a8805f764f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10100
76896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1010076896
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1850600357
Short name T1343
Test name
Test status
Simulation time 11162077788 ps
CPU time 14.81 seconds
Started Aug 07 06:11:10 PM PDT 24
Finished Aug 07 06:11:25 PM PDT 24
Peak memory 207292 kb
Host smart-e72fb062-34b4-4af2-98c5-92ff42594097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18506
00357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1850600357
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2286517373
Short name T1278
Test name
Test status
Simulation time 3783723789 ps
CPU time 29.76 seconds
Started Aug 07 06:11:06 PM PDT 24
Finished Aug 07 06:11:36 PM PDT 24
Peak memory 215580 kb
Host smart-34d69d08-9199-441a-b27e-a6482b34651d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22865
17373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2286517373
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.3587971321
Short name T3073
Test name
Test status
Simulation time 2953615324 ps
CPU time 30.49 seconds
Started Aug 07 06:11:13 PM PDT 24
Finished Aug 07 06:11:44 PM PDT 24
Peak memory 215504 kb
Host smart-0fc16476-0cee-4c9d-b09b-904a3717a1c4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3587971321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.3587971321
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.309433549
Short name T2677
Test name
Test status
Simulation time 247440927 ps
CPU time 1.01 seconds
Started Aug 07 06:11:09 PM PDT 24
Finished Aug 07 06:11:11 PM PDT 24
Peak memory 206992 kb
Host smart-a8b1813e-8dab-4a68-a31e-75063cd53f6e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=309433549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.309433549
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1740595579
Short name T1252
Test name
Test status
Simulation time 192901842 ps
CPU time 0.93 seconds
Started Aug 07 06:11:10 PM PDT 24
Finished Aug 07 06:11:11 PM PDT 24
Peak memory 207004 kb
Host smart-b1cc8fe5-081d-4933-8eef-9d9a239800fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17405
95579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1740595579
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3400151940
Short name T606
Test name
Test status
Simulation time 2354571942 ps
CPU time 68.77 seconds
Started Aug 07 06:11:11 PM PDT 24
Finished Aug 07 06:12:20 PM PDT 24
Peak memory 215488 kb
Host smart-9a9ac86f-d313-475a-aea7-5dc21de2d462
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3400151940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3400151940
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.976276633
Short name T718
Test name
Test status
Simulation time 159538530 ps
CPU time 0.89 seconds
Started Aug 07 06:11:09 PM PDT 24
Finished Aug 07 06:11:10 PM PDT 24
Peak memory 207020 kb
Host smart-2c435059-6592-4194-a4bd-3acfba7944ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=976276633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.976276633
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.295827973
Short name T664
Test name
Test status
Simulation time 163175511 ps
CPU time 0.92 seconds
Started Aug 07 06:11:10 PM PDT 24
Finished Aug 07 06:11:11 PM PDT 24
Peak memory 207028 kb
Host smart-f9bdd202-5610-4dad-a990-03c6981ba624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29582
7973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.295827973
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1478225280
Short name T158
Test name
Test status
Simulation time 206190552 ps
CPU time 0.94 seconds
Started Aug 07 06:11:11 PM PDT 24
Finished Aug 07 06:11:12 PM PDT 24
Peak memory 206984 kb
Host smart-96fa3666-c290-49c9-a2e5-a20a1d5d2959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14782
25280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1478225280
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.1450634729
Short name T2855
Test name
Test status
Simulation time 205033199 ps
CPU time 0.94 seconds
Started Aug 07 06:11:06 PM PDT 24
Finished Aug 07 06:11:07 PM PDT 24
Peak memory 206892 kb
Host smart-34831577-86e8-458e-9d5f-81ecff71e99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14506
34729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1450634729
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.4117296261
Short name T1771
Test name
Test status
Simulation time 198747109 ps
CPU time 0.92 seconds
Started Aug 07 06:11:05 PM PDT 24
Finished Aug 07 06:11:06 PM PDT 24
Peak memory 206980 kb
Host smart-a4be9068-d086-43a0-9215-ce45c56d8e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41172
96261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.4117296261
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1601156385
Short name T2828
Test name
Test status
Simulation time 193780874 ps
CPU time 0.92 seconds
Started Aug 07 06:11:19 PM PDT 24
Finished Aug 07 06:11:20 PM PDT 24
Peak memory 207008 kb
Host smart-bfdd3edf-9655-4177-8540-1a63db16d87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16011
56385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1601156385
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2288192036
Short name T2626
Test name
Test status
Simulation time 148710580 ps
CPU time 0.82 seconds
Started Aug 07 06:11:18 PM PDT 24
Finished Aug 07 06:11:19 PM PDT 24
Peak memory 206912 kb
Host smart-ee47690a-bc5f-4440-8d34-25cad51e41b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22881
92036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2288192036
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.2756666754
Short name T1464
Test name
Test status
Simulation time 221108493 ps
CPU time 1.09 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:18 PM PDT 24
Peak memory 207028 kb
Host smart-354363ec-76f4-4dfe-a436-f9c55056d9db
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2756666754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.2756666754
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1745192026
Short name T211
Test name
Test status
Simulation time 159684624 ps
CPU time 0.9 seconds
Started Aug 07 06:11:17 PM PDT 24
Finished Aug 07 06:11:18 PM PDT 24
Peak memory 206944 kb
Host smart-17ee8563-3513-4fd1-ba00-d95f04837487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17451
92026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1745192026
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2141376913
Short name T2650
Test name
Test status
Simulation time 40220692 ps
CPU time 0.71 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:16 PM PDT 24
Peak memory 206964 kb
Host smart-9dc9cf70-d921-4d88-b8e7-f5dee703aa45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21413
76913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2141376913
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.4685065
Short name T1780
Test name
Test status
Simulation time 19701083837 ps
CPU time 48.7 seconds
Started Aug 07 06:11:19 PM PDT 24
Finished Aug 07 06:12:08 PM PDT 24
Peak memory 223544 kb
Host smart-685f43c1-940a-45b6-8049-e69e13a6f1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46850
65 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.4685065
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2405512205
Short name T1758
Test name
Test status
Simulation time 206288672 ps
CPU time 0.91 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:17 PM PDT 24
Peak memory 206992 kb
Host smart-c641ab0a-99d6-4fc6-b279-3a789cb34b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24055
12205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2405512205
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2103018242
Short name T1248
Test name
Test status
Simulation time 181237779 ps
CPU time 0.9 seconds
Started Aug 07 06:11:19 PM PDT 24
Finished Aug 07 06:11:20 PM PDT 24
Peak memory 206860 kb
Host smart-de1bd78c-a6c7-48bf-a9a6-ca38d60dde69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21030
18242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2103018242
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.2399253044
Short name T1372
Test name
Test status
Simulation time 164757200 ps
CPU time 0.92 seconds
Started Aug 07 06:11:15 PM PDT 24
Finished Aug 07 06:11:16 PM PDT 24
Peak memory 206968 kb
Host smart-59047c66-9c2c-4480-8ba7-a78125bfe5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23992
53044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2399253044
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.123815185
Short name T3005
Test name
Test status
Simulation time 165798666 ps
CPU time 0.87 seconds
Started Aug 07 06:11:15 PM PDT 24
Finished Aug 07 06:11:16 PM PDT 24
Peak memory 206988 kb
Host smart-bf0ff07c-f14e-44d3-a695-ce40323f8072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12381
5185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.123815185
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2994589077
Short name T1322
Test name
Test status
Simulation time 162870598 ps
CPU time 0.84 seconds
Started Aug 07 06:11:21 PM PDT 24
Finished Aug 07 06:11:22 PM PDT 24
Peak memory 207004 kb
Host smart-4a1f82d5-2196-4509-a2c4-d949bf59696f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29945
89077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2994589077
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_rx_full.4061638114
Short name T311
Test name
Test status
Simulation time 247664285 ps
CPU time 1.08 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:17 PM PDT 24
Peak memory 207016 kb
Host smart-2cbb7316-ae59-4395-8b67-65d2db5eb9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40616
38114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.4061638114
Directory /workspace/43.usbdev_rx_full/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2017612046
Short name T847
Test name
Test status
Simulation time 152332943 ps
CPU time 0.83 seconds
Started Aug 07 06:11:18 PM PDT 24
Finished Aug 07 06:11:19 PM PDT 24
Peak memory 207012 kb
Host smart-273bdb18-8d6f-4707-bae7-fb924077eb99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20176
12046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2017612046
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3425904547
Short name T3122
Test name
Test status
Simulation time 175858272 ps
CPU time 0.87 seconds
Started Aug 07 06:11:14 PM PDT 24
Finished Aug 07 06:11:15 PM PDT 24
Peak memory 207000 kb
Host smart-9860ed8c-7be5-4660-a22b-2fbd399c1ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34259
04547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3425904547
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.227455202
Short name T2802
Test name
Test status
Simulation time 259596807 ps
CPU time 1.07 seconds
Started Aug 07 06:11:18 PM PDT 24
Finished Aug 07 06:11:19 PM PDT 24
Peak memory 206936 kb
Host smart-9fd44906-a69c-4ee1-b3a7-96ca5eb3908b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22745
5202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.227455202
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2318436926
Short name T1951
Test name
Test status
Simulation time 2344231227 ps
CPU time 70.4 seconds
Started Aug 07 06:11:18 PM PDT 24
Finished Aug 07 06:12:28 PM PDT 24
Peak memory 217172 kb
Host smart-4563dc09-5897-4d33-a0f1-e2b94f55db09
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2318436926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2318436926
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.125360563
Short name T2308
Test name
Test status
Simulation time 145293059 ps
CPU time 0.87 seconds
Started Aug 07 06:11:19 PM PDT 24
Finished Aug 07 06:11:20 PM PDT 24
Peak memory 206904 kb
Host smart-08896b49-34ee-4c5f-9c54-8aab0a95ba6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12536
0563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.125360563
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.1138032697
Short name T2137
Test name
Test status
Simulation time 167702756 ps
CPU time 0.84 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:17 PM PDT 24
Peak memory 207016 kb
Host smart-e98f17f8-436c-46c1-a0f2-45781188cc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11380
32697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1138032697
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.1522347642
Short name T1739
Test name
Test status
Simulation time 1263971139 ps
CPU time 3.13 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:20 PM PDT 24
Peak memory 207196 kb
Host smart-04655328-77e6-4aac-a227-dce34fbc73ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15223
47642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.1522347642
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1239364072
Short name T1759
Test name
Test status
Simulation time 3557722842 ps
CPU time 102.97 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:13:00 PM PDT 24
Peak memory 216796 kb
Host smart-d5dd5151-a619-415d-93e4-0874f670cff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12393
64072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1239364072
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.1796979890
Short name T1441
Test name
Test status
Simulation time 2951553590 ps
CPU time 25.83 seconds
Started Aug 07 06:11:05 PM PDT 24
Finished Aug 07 06:11:31 PM PDT 24
Peak memory 207328 kb
Host smart-ab9da5a8-e8eb-4841-bd46-299dbd68881c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796979890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.1796979890
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.1705226762
Short name T2580
Test name
Test status
Simulation time 44178335 ps
CPU time 0.7 seconds
Started Aug 07 06:11:37 PM PDT 24
Finished Aug 07 06:11:38 PM PDT 24
Peak memory 207096 kb
Host smart-e86b2210-33d6-462d-885e-6aedb9ee1341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1705226762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.1705226762
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2432890259
Short name T655
Test name
Test status
Simulation time 11363677098 ps
CPU time 17 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:33 PM PDT 24
Peak memory 207268 kb
Host smart-596968c2-efb6-4567-8b42-f6bd1c0813c5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432890259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.2432890259
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3771590303
Short name T2425
Test name
Test status
Simulation time 13723025209 ps
CPU time 18.03 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:34 PM PDT 24
Peak memory 215436 kb
Host smart-805e7c63-ef26-46fd-9c90-63efc903f3c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771590303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3771590303
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.754093718
Short name T1768
Test name
Test status
Simulation time 25358853460 ps
CPU time 30.5 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:47 PM PDT 24
Peak memory 215484 kb
Host smart-2dd2d4a4-d43f-412e-a198-a50756b84d25
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754093718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_ao
n_wake_resume.754093718
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2492633033
Short name T1081
Test name
Test status
Simulation time 268382452 ps
CPU time 0.98 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:17 PM PDT 24
Peak memory 206964 kb
Host smart-f80521d5-e1ad-4b5b-8bfc-59d86495c249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24926
33033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2492633033
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.2955329318
Short name T1651
Test name
Test status
Simulation time 155257958 ps
CPU time 0.84 seconds
Started Aug 07 06:11:15 PM PDT 24
Finished Aug 07 06:11:15 PM PDT 24
Peak memory 206996 kb
Host smart-d2de848f-adf7-4308-8afd-ed00aeefa5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29553
29318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2955329318
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.472187647
Short name T1850
Test name
Test status
Simulation time 204854313 ps
CPU time 0.95 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:17 PM PDT 24
Peak memory 206996 kb
Host smart-5dc74c62-dad9-4691-9605-e0b317b50d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47218
7647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.472187647
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2653199970
Short name T3033
Test name
Test status
Simulation time 407752723 ps
CPU time 1.33 seconds
Started Aug 07 06:11:15 PM PDT 24
Finished Aug 07 06:11:16 PM PDT 24
Peak memory 207012 kb
Host smart-3bb99a9f-ce07-42f6-a002-afdf0063977c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2653199970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2653199970
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1659191790
Short name T187
Test name
Test status
Simulation time 14694284618 ps
CPU time 24.52 seconds
Started Aug 07 06:11:14 PM PDT 24
Finished Aug 07 06:11:38 PM PDT 24
Peak memory 207304 kb
Host smart-ef63bdcd-0b50-4ee2-8b6e-e1feeb1092e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591
91790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1659191790
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.146880390
Short name T2861
Test name
Test status
Simulation time 2514887376 ps
CPU time 21.37 seconds
Started Aug 07 06:11:12 PM PDT 24
Finished Aug 07 06:11:34 PM PDT 24
Peak memory 207260 kb
Host smart-f598a9d6-9fb8-4392-bfc2-ab1ac8b0b376
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146880390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.146880390
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.647776157
Short name T486
Test name
Test status
Simulation time 950569965 ps
CPU time 2.42 seconds
Started Aug 07 06:11:17 PM PDT 24
Finished Aug 07 06:11:20 PM PDT 24
Peak memory 206984 kb
Host smart-33caebda-88ce-4ade-8431-2fb4b4127d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64777
6157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.647776157
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.254958646
Short name T2568
Test name
Test status
Simulation time 148644609 ps
CPU time 0.83 seconds
Started Aug 07 06:11:17 PM PDT 24
Finished Aug 07 06:11:18 PM PDT 24
Peak memory 206952 kb
Host smart-e0ec7842-68f5-4468-abab-ea635b054e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25495
8646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.254958646
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2822985714
Short name T2959
Test name
Test status
Simulation time 62820884 ps
CPU time 0.71 seconds
Started Aug 07 06:11:16 PM PDT 24
Finished Aug 07 06:11:17 PM PDT 24
Peak memory 206976 kb
Host smart-c3b8ff41-21fe-4a47-8378-cd9a087a8c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28229
85714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2822985714
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.449136402
Short name T1003
Test name
Test status
Simulation time 871581178 ps
CPU time 2.25 seconds
Started Aug 07 06:11:18 PM PDT 24
Finished Aug 07 06:11:20 PM PDT 24
Peak memory 207196 kb
Host smart-64cc18e6-64af-488f-b483-4997d9b88085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44913
6402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.449136402
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_types.187031793
Short name T957
Test name
Test status
Simulation time 161731396 ps
CPU time 0.88 seconds
Started Aug 07 06:11:28 PM PDT 24
Finished Aug 07 06:11:29 PM PDT 24
Peak memory 207004 kb
Host smart-ad28f827-0706-4aea-9ffd-f3e74d0f2e7b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=187031793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.187031793
Directory /workspace/44.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2730582272
Short name T1205
Test name
Test status
Simulation time 234115081 ps
CPU time 1.56 seconds
Started Aug 07 06:11:25 PM PDT 24
Finished Aug 07 06:11:27 PM PDT 24
Peak memory 207224 kb
Host smart-da986a0c-31c8-422c-a565-74dbb6448299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27305
82272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2730582272
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2930872193
Short name T1577
Test name
Test status
Simulation time 183947665 ps
CPU time 0.94 seconds
Started Aug 07 06:11:27 PM PDT 24
Finished Aug 07 06:11:28 PM PDT 24
Peak memory 207008 kb
Host smart-8077946f-4be7-4e93-83d0-ca1325d1c695
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2930872193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2930872193
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.626447976
Short name T1120
Test name
Test status
Simulation time 167106390 ps
CPU time 0.85 seconds
Started Aug 07 06:11:28 PM PDT 24
Finished Aug 07 06:11:29 PM PDT 24
Peak memory 206940 kb
Host smart-fabfac82-b924-4c2a-9dc5-4e1d314bddd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62644
7976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.626447976
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2882493293
Short name T2468
Test name
Test status
Simulation time 189649019 ps
CPU time 0.99 seconds
Started Aug 07 06:11:28 PM PDT 24
Finished Aug 07 06:11:29 PM PDT 24
Peak memory 206908 kb
Host smart-a77c9e12-4c06-4ae5-bbb8-4437b2773b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28824
93293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2882493293
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.2262652302
Short name T1459
Test name
Test status
Simulation time 4386058881 ps
CPU time 33.08 seconds
Started Aug 07 06:11:26 PM PDT 24
Finished Aug 07 06:12:00 PM PDT 24
Peak memory 215584 kb
Host smart-7352e5a3-bb63-4b99-bba9-09e07b3fb936
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2262652302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.2262652302
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1539167643
Short name T2432
Test name
Test status
Simulation time 213525957 ps
CPU time 0.96 seconds
Started Aug 07 06:11:25 PM PDT 24
Finished Aug 07 06:11:26 PM PDT 24
Peak memory 206968 kb
Host smart-b9ddf550-e84c-49db-9895-cf670b3e201f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15391
67643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1539167643
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.648733564
Short name T1070
Test name
Test status
Simulation time 24065930252 ps
CPU time 37.93 seconds
Started Aug 07 06:11:27 PM PDT 24
Finished Aug 07 06:12:05 PM PDT 24
Peak memory 215576 kb
Host smart-e77e41a2-4f90-42ca-afe5-82ead88b408b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64873
3564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.648733564
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1197749785
Short name T2034
Test name
Test status
Simulation time 9921632613 ps
CPU time 13.23 seconds
Started Aug 07 06:11:27 PM PDT 24
Finished Aug 07 06:11:40 PM PDT 24
Peak memory 207304 kb
Host smart-76354aa6-4f26-4997-bdc2-432ecf19ba31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11977
49785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1197749785
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.2328665478
Short name T1713
Test name
Test status
Simulation time 4476824371 ps
CPU time 43.94 seconds
Started Aug 07 06:11:26 PM PDT 24
Finished Aug 07 06:12:10 PM PDT 24
Peak memory 218184 kb
Host smart-a1fc888f-67f3-408d-a8f7-fa85517db516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23286
65478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.2328665478
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.4004980518
Short name T2364
Test name
Test status
Simulation time 1849055002 ps
CPU time 52.93 seconds
Started Aug 07 06:11:27 PM PDT 24
Finished Aug 07 06:12:20 PM PDT 24
Peak memory 216828 kb
Host smart-2898c1d4-082e-4bfe-ab47-defda7e551e4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4004980518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.4004980518
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.3018096782
Short name T1426
Test name
Test status
Simulation time 325224140 ps
CPU time 1.11 seconds
Started Aug 07 06:11:25 PM PDT 24
Finished Aug 07 06:11:26 PM PDT 24
Peak memory 207008 kb
Host smart-9cf38d9e-f655-4336-ac96-f17d66deb6d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3018096782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.3018096782
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.4019945945
Short name T2829
Test name
Test status
Simulation time 187142951 ps
CPU time 0.93 seconds
Started Aug 07 06:11:24 PM PDT 24
Finished Aug 07 06:11:25 PM PDT 24
Peak memory 206904 kb
Host smart-c9d1893e-3ad2-4cfa-aa71-466393572d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40199
45945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.4019945945
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.394368878
Short name T3124
Test name
Test status
Simulation time 3733775517 ps
CPU time 102.6 seconds
Started Aug 07 06:11:25 PM PDT 24
Finished Aug 07 06:13:07 PM PDT 24
Peak memory 215560 kb
Host smart-dafacc34-b830-4eb3-b651-14520604c0e0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=394368878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.394368878
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2216011204
Short name T2203
Test name
Test status
Simulation time 172286696 ps
CPU time 0.91 seconds
Started Aug 07 06:11:28 PM PDT 24
Finished Aug 07 06:11:29 PM PDT 24
Peak memory 206936 kb
Host smart-7947f8f6-b4aa-450e-8c35-1bb5f3424145
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2216011204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2216011204
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.669031823
Short name T2073
Test name
Test status
Simulation time 145945791 ps
CPU time 0.84 seconds
Started Aug 07 06:11:29 PM PDT 24
Finished Aug 07 06:11:30 PM PDT 24
Peak memory 206944 kb
Host smart-b84d8773-3915-431a-923a-15d6debe559c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66903
1823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.669031823
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.75582603
Short name T153
Test name
Test status
Simulation time 196011269 ps
CPU time 0.96 seconds
Started Aug 07 06:11:29 PM PDT 24
Finished Aug 07 06:11:30 PM PDT 24
Peak memory 206992 kb
Host smart-137c1c72-b4ef-45c2-af1d-37d71b210838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75582
603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.75582603
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2601957079
Short name T982
Test name
Test status
Simulation time 183810545 ps
CPU time 0.88 seconds
Started Aug 07 06:11:27 PM PDT 24
Finished Aug 07 06:11:28 PM PDT 24
Peak memory 207004 kb
Host smart-543fd40c-978c-4cc6-a64e-a7599bef423c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26019
57079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2601957079
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2038756461
Short name T2781
Test name
Test status
Simulation time 155012891 ps
CPU time 0.86 seconds
Started Aug 07 06:11:29 PM PDT 24
Finished Aug 07 06:11:30 PM PDT 24
Peak memory 206992 kb
Host smart-b5fe4615-2b43-4dcb-8e56-51db6ab39f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20387
56461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2038756461
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3080091041
Short name T1735
Test name
Test status
Simulation time 219843443 ps
CPU time 1.02 seconds
Started Aug 07 06:11:26 PM PDT 24
Finished Aug 07 06:11:27 PM PDT 24
Peak memory 206956 kb
Host smart-9d346579-5809-4396-9a34-67b91065f64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30800
91041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3080091041
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1503125893
Short name T1597
Test name
Test status
Simulation time 150356207 ps
CPU time 0.85 seconds
Started Aug 07 06:11:23 PM PDT 24
Finished Aug 07 06:11:24 PM PDT 24
Peak memory 207016 kb
Host smart-17b05f56-1ef5-4444-925f-7b1ec2ba0bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15031
25893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1503125893
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1628620140
Short name T1881
Test name
Test status
Simulation time 259574239 ps
CPU time 1.13 seconds
Started Aug 07 06:11:26 PM PDT 24
Finished Aug 07 06:11:27 PM PDT 24
Peak memory 206984 kb
Host smart-8bbc3185-4536-4732-8257-6688ade8d807
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1628620140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1628620140
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1025700704
Short name T1820
Test name
Test status
Simulation time 160724486 ps
CPU time 0.86 seconds
Started Aug 07 06:11:26 PM PDT 24
Finished Aug 07 06:11:27 PM PDT 24
Peak memory 206964 kb
Host smart-9a3bf0a2-4260-4b66-ae2f-a44c49b4a2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10257
00704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1025700704
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3698649464
Short name T2525
Test name
Test status
Simulation time 67109501 ps
CPU time 0.71 seconds
Started Aug 07 06:11:28 PM PDT 24
Finished Aug 07 06:11:29 PM PDT 24
Peak memory 206876 kb
Host smart-c8bf8d22-9d01-4be9-999d-12053d179afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36986
49464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3698649464
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3296323048
Short name T2401
Test name
Test status
Simulation time 14114388474 ps
CPU time 35.51 seconds
Started Aug 07 06:11:24 PM PDT 24
Finished Aug 07 06:12:00 PM PDT 24
Peak memory 215540 kb
Host smart-e7cb1c22-4e07-41f6-bd7f-247380f6c1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32963
23048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3296323048
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3070700535
Short name T659
Test name
Test status
Simulation time 173568502 ps
CPU time 0.95 seconds
Started Aug 07 06:11:28 PM PDT 24
Finished Aug 07 06:11:29 PM PDT 24
Peak memory 207024 kb
Host smart-89379efd-ade7-40a5-b51c-b188ddc81ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30707
00535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3070700535
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.878306324
Short name T2549
Test name
Test status
Simulation time 205279959 ps
CPU time 0.92 seconds
Started Aug 07 06:11:24 PM PDT 24
Finished Aug 07 06:11:25 PM PDT 24
Peak memory 206892 kb
Host smart-87cd11d9-d9c1-42bb-a990-45fab69818e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87830
6324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.878306324
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.3556740110
Short name T855
Test name
Test status
Simulation time 202038629 ps
CPU time 0.91 seconds
Started Aug 07 06:11:29 PM PDT 24
Finished Aug 07 06:11:30 PM PDT 24
Peak memory 206948 kb
Host smart-480080c8-84b5-40ff-a9f3-d1710f129d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35567
40110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.3556740110
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1989522170
Short name T2611
Test name
Test status
Simulation time 147735858 ps
CPU time 0.82 seconds
Started Aug 07 06:11:25 PM PDT 24
Finished Aug 07 06:11:26 PM PDT 24
Peak memory 206976 kb
Host smart-7ce32cf4-a92a-4a57-92ca-3f55e932d7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
22170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1989522170
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.746337350
Short name T1133
Test name
Test status
Simulation time 174843590 ps
CPU time 0.87 seconds
Started Aug 07 06:11:25 PM PDT 24
Finished Aug 07 06:11:26 PM PDT 24
Peak memory 206872 kb
Host smart-a214d17c-7e1a-4301-a694-3f329ea7f479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74633
7350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.746337350
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_rx_full.2922251491
Short name T973
Test name
Test status
Simulation time 409876302 ps
CPU time 1.42 seconds
Started Aug 07 06:11:23 PM PDT 24
Finished Aug 07 06:11:25 PM PDT 24
Peak memory 206980 kb
Host smart-c2d58386-a762-4ea2-8c7e-1a08e554d6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29222
51491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.2922251491
Directory /workspace/44.usbdev_rx_full/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2920440025
Short name T2164
Test name
Test status
Simulation time 169579677 ps
CPU time 0.88 seconds
Started Aug 07 06:11:28 PM PDT 24
Finished Aug 07 06:11:29 PM PDT 24
Peak memory 206900 kb
Host smart-19c706bb-8282-4522-a757-364bb99d3fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29204
40025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2920440025
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2051603647
Short name T699
Test name
Test status
Simulation time 165264146 ps
CPU time 0.86 seconds
Started Aug 07 06:11:39 PM PDT 24
Finished Aug 07 06:11:40 PM PDT 24
Peak memory 206988 kb
Host smart-2fcd386f-2d07-4ede-a95f-f1e360b6292a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20516
03647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2051603647
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.4014608087
Short name T1327
Test name
Test status
Simulation time 206240363 ps
CPU time 0.97 seconds
Started Aug 07 06:11:34 PM PDT 24
Finished Aug 07 06:11:36 PM PDT 24
Peak memory 206996 kb
Host smart-b08abfc6-b1fe-43fd-ad7c-86a824c7195c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40146
08087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.4014608087
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.245356886
Short name T1519
Test name
Test status
Simulation time 2137909286 ps
CPU time 16.97 seconds
Started Aug 07 06:11:36 PM PDT 24
Finished Aug 07 06:11:53 PM PDT 24
Peak memory 217120 kb
Host smart-fbc44a10-c349-4a56-b31d-2c22a1b6a04f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=245356886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.245356886
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1750089074
Short name T476
Test name
Test status
Simulation time 174045896 ps
CPU time 0.88 seconds
Started Aug 07 06:11:36 PM PDT 24
Finished Aug 07 06:11:37 PM PDT 24
Peak memory 206988 kb
Host smart-7279b78c-8748-4293-9767-de407eb6b3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17500
89074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1750089074
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1613615033
Short name T1482
Test name
Test status
Simulation time 183621174 ps
CPU time 0.89 seconds
Started Aug 07 06:11:36 PM PDT 24
Finished Aug 07 06:11:37 PM PDT 24
Peak memory 207000 kb
Host smart-241e6b2e-e3fd-47d5-8ffc-a71194872d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16136
15033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1613615033
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.3526587373
Short name T608
Test name
Test status
Simulation time 440252128 ps
CPU time 1.29 seconds
Started Aug 07 06:11:33 PM PDT 24
Finished Aug 07 06:11:35 PM PDT 24
Peak memory 206872 kb
Host smart-8a99f439-b58f-4875-a9ef-7944d6398b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35265
87373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.3526587373
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.2815558933
Short name T758
Test name
Test status
Simulation time 2968939977 ps
CPU time 86.42 seconds
Started Aug 07 06:11:37 PM PDT 24
Finished Aug 07 06:13:04 PM PDT 24
Peak memory 217124 kb
Host smart-56c448bd-cb9e-4df5-a375-42a37bfc89e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28155
58933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.2815558933
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.3233877026
Short name T615
Test name
Test status
Simulation time 2464808499 ps
CPU time 21.17 seconds
Started Aug 07 06:11:15 PM PDT 24
Finished Aug 07 06:11:36 PM PDT 24
Peak memory 207372 kb
Host smart-20efa37f-90d7-4bf3-95b0-bd6556adccff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233877026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos
t_handshake.3233877026
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3346581234
Short name T1364
Test name
Test status
Simulation time 51936770 ps
CPU time 0.7 seconds
Started Aug 07 06:11:52 PM PDT 24
Finished Aug 07 06:11:53 PM PDT 24
Peak memory 207096 kb
Host smart-7c956a73-7c4c-4c1a-a072-c78a45a5ad10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3346581234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3346581234
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1238879128
Short name T14
Test name
Test status
Simulation time 10888916822 ps
CPU time 13.24 seconds
Started Aug 07 06:11:33 PM PDT 24
Finished Aug 07 06:11:46 PM PDT 24
Peak memory 207288 kb
Host smart-cc390346-b648-445b-ae61-d20bafabbb58
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238879128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.1238879128
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.280495190
Short name T2798
Test name
Test status
Simulation time 14207740450 ps
CPU time 19.78 seconds
Started Aug 07 06:11:38 PM PDT 24
Finished Aug 07 06:11:58 PM PDT 24
Peak memory 215480 kb
Host smart-2090a07b-3769-496a-9199-49fd032c6af0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=280495190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.280495190
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3634833261
Short name T111
Test name
Test status
Simulation time 30921811686 ps
CPU time 40.86 seconds
Started Aug 07 06:11:34 PM PDT 24
Finished Aug 07 06:12:15 PM PDT 24
Peak memory 207264 kb
Host smart-c8ab3952-12a1-4ea6-a193-ef66d3c6d8e5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634833261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.3634833261
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.156217693
Short name T2023
Test name
Test status
Simulation time 147422839 ps
CPU time 0.87 seconds
Started Aug 07 06:11:38 PM PDT 24
Finished Aug 07 06:11:39 PM PDT 24
Peak memory 206988 kb
Host smart-44b6e1b3-c246-4934-be5f-c13b08a45e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15621
7693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.156217693
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2249560763
Short name T1065
Test name
Test status
Simulation time 157114415 ps
CPU time 0.87 seconds
Started Aug 07 06:11:32 PM PDT 24
Finished Aug 07 06:11:33 PM PDT 24
Peak memory 206956 kb
Host smart-dfc30a64-8dd0-4d49-b312-d1f76ac1b255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22495
60763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2249560763
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.3345761276
Short name T2712
Test name
Test status
Simulation time 452200705 ps
CPU time 1.55 seconds
Started Aug 07 06:11:33 PM PDT 24
Finished Aug 07 06:11:34 PM PDT 24
Peak memory 206916 kb
Host smart-03f43cf2-696a-46e2-b50a-022886c1b63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33457
61276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3345761276
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2401908499
Short name T2250
Test name
Test status
Simulation time 696422638 ps
CPU time 1.87 seconds
Started Aug 07 06:11:44 PM PDT 24
Finished Aug 07 06:11:46 PM PDT 24
Peak memory 207276 kb
Host smart-cdfb5c49-e9f8-4213-9eae-4890a2d9ef3b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2401908499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2401908499
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.2488786412
Short name T1738
Test name
Test status
Simulation time 53177523284 ps
CPU time 85.9 seconds
Started Aug 07 06:11:36 PM PDT 24
Finished Aug 07 06:13:02 PM PDT 24
Peak memory 207272 kb
Host smart-1870c896-2b90-4907-b19c-ffeadcdc16f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24887
86412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.2488786412
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.4147375815
Short name T1561
Test name
Test status
Simulation time 4998856650 ps
CPU time 35.36 seconds
Started Aug 07 06:11:35 PM PDT 24
Finished Aug 07 06:12:10 PM PDT 24
Peak memory 207204 kb
Host smart-3b18e469-16cd-4831-bd88-2503507a4e4e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147375815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.4147375815
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.921380649
Short name T1888
Test name
Test status
Simulation time 563965345 ps
CPU time 1.61 seconds
Started Aug 07 06:11:40 PM PDT 24
Finished Aug 07 06:11:41 PM PDT 24
Peak memory 206952 kb
Host smart-80f07dc8-e05e-4c1a-8ab8-f9d599e81624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92138
0649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.921380649
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2282090359
Short name T1730
Test name
Test status
Simulation time 135845100 ps
CPU time 0.84 seconds
Started Aug 07 06:11:34 PM PDT 24
Finished Aug 07 06:11:35 PM PDT 24
Peak memory 206912 kb
Host smart-cb968a31-aaa4-4920-91cf-7cbc0ad3d89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22820
90359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2282090359
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.4228751303
Short name T1543
Test name
Test status
Simulation time 76915431 ps
CPU time 0.77 seconds
Started Aug 07 06:11:37 PM PDT 24
Finished Aug 07 06:11:38 PM PDT 24
Peak memory 207008 kb
Host smart-ce81083a-fb13-4fdf-b841-4a3cfcfeffc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42287
51303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.4228751303
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.4085966123
Short name T1859
Test name
Test status
Simulation time 1018287347 ps
CPU time 2.73 seconds
Started Aug 07 06:11:34 PM PDT 24
Finished Aug 07 06:11:36 PM PDT 24
Peak memory 207172 kb
Host smart-7b812348-1d2e-45c6-be0c-a762aa16906d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40859
66123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.4085966123
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_types.4221336437
Short name T388
Test name
Test status
Simulation time 352778184 ps
CPU time 1.24 seconds
Started Aug 07 06:11:34 PM PDT 24
Finished Aug 07 06:11:35 PM PDT 24
Peak memory 206976 kb
Host smart-424d61e4-3392-4b3b-98cc-92dddf02bbf6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4221336437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.4221336437
Directory /workspace/45.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.4113400836
Short name T1949
Test name
Test status
Simulation time 208318685 ps
CPU time 1.41 seconds
Started Aug 07 06:11:34 PM PDT 24
Finished Aug 07 06:11:35 PM PDT 24
Peak memory 207192 kb
Host smart-dac11d5b-4ace-4e97-a7ec-fec1883a7550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41134
00836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.4113400836
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3463831456
Short name T2911
Test name
Test status
Simulation time 221691272 ps
CPU time 1.1 seconds
Started Aug 07 06:11:35 PM PDT 24
Finished Aug 07 06:11:36 PM PDT 24
Peak memory 207188 kb
Host smart-2f1c3a73-4b1a-4850-a20f-0d9974b4498a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3463831456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3463831456
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1670947008
Short name T856
Test name
Test status
Simulation time 224482300 ps
CPU time 0.95 seconds
Started Aug 07 06:11:43 PM PDT 24
Finished Aug 07 06:11:44 PM PDT 24
Peak memory 207012 kb
Host smart-b4edc7d1-dc04-42e0-9b16-987e611ee0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16709
47008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1670947008
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2499009210
Short name T1861
Test name
Test status
Simulation time 227140602 ps
CPU time 1.01 seconds
Started Aug 07 06:11:37 PM PDT 24
Finished Aug 07 06:11:38 PM PDT 24
Peak memory 206888 kb
Host smart-add2d7fe-7b0f-4fcc-93ec-67df478c86ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24990
09210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2499009210
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.2362571661
Short name T1812
Test name
Test status
Simulation time 3221421003 ps
CPU time 31.8 seconds
Started Aug 07 06:11:36 PM PDT 24
Finished Aug 07 06:12:08 PM PDT 24
Peak memory 217296 kb
Host smart-5b583f07-af86-4474-9550-53667ead2fe6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2362571661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2362571661
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.171950701
Short name T1684
Test name
Test status
Simulation time 15111773657 ps
CPU time 98.16 seconds
Started Aug 07 06:11:37 PM PDT 24
Finished Aug 07 06:13:15 PM PDT 24
Peak memory 207268 kb
Host smart-cb4d682f-9b80-40e5-9b53-bc2cab561ba6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=171950701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.171950701
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2953422238
Short name T3018
Test name
Test status
Simulation time 189342673 ps
CPU time 0.97 seconds
Started Aug 07 06:11:39 PM PDT 24
Finished Aug 07 06:11:40 PM PDT 24
Peak memory 206984 kb
Host smart-0fb0b954-8a34-42ce-954a-1616120df1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29534
22238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2953422238
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2179726218
Short name T2078
Test name
Test status
Simulation time 26044338394 ps
CPU time 42.1 seconds
Started Aug 07 06:11:34 PM PDT 24
Finished Aug 07 06:12:17 PM PDT 24
Peak memory 207240 kb
Host smart-7e4cb9b4-0101-4d71-8550-725167feb1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21797
26218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2179726218
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2137493187
Short name T206
Test name
Test status
Simulation time 10161518054 ps
CPU time 13.33 seconds
Started Aug 07 06:11:38 PM PDT 24
Finished Aug 07 06:11:51 PM PDT 24
Peak memory 207300 kb
Host smart-7ac0fd55-2986-45db-ae36-6f9d0248402a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21374
93187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2137493187
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.4273808414
Short name T1350
Test name
Test status
Simulation time 5099954288 ps
CPU time 39.52 seconds
Started Aug 07 06:11:43 PM PDT 24
Finished Aug 07 06:12:23 PM PDT 24
Peak memory 223780 kb
Host smart-f55190aa-e79b-43eb-8f65-426ea2474841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42738
08414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.4273808414
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.2846914424
Short name T757
Test name
Test status
Simulation time 3011602471 ps
CPU time 89.89 seconds
Started Aug 07 06:11:35 PM PDT 24
Finished Aug 07 06:13:05 PM PDT 24
Peak memory 217028 kb
Host smart-aa6247e8-cd45-4f79-b123-0eccaad20d2e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2846914424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.2846914424
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.4027947120
Short name T2431
Test name
Test status
Simulation time 255912413 ps
CPU time 1.09 seconds
Started Aug 07 06:11:44 PM PDT 24
Finished Aug 07 06:11:45 PM PDT 24
Peak memory 206992 kb
Host smart-8fc4a76e-e674-4b9e-8593-21b66520386c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4027947120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.4027947120
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.4188910340
Short name T2956
Test name
Test status
Simulation time 209809799 ps
CPU time 0.96 seconds
Started Aug 07 06:11:35 PM PDT 24
Finished Aug 07 06:11:36 PM PDT 24
Peak memory 207016 kb
Host smart-b102bcc7-aaff-4459-9362-05df392a1be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41889
10340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.4188910340
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1231874577
Short name T2534
Test name
Test status
Simulation time 185593008 ps
CPU time 0.93 seconds
Started Aug 07 06:11:38 PM PDT 24
Finished Aug 07 06:11:39 PM PDT 24
Peak memory 207008 kb
Host smart-3185c979-eab6-45d2-aa84-9ab6d2a696bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1231874577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1231874577
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1447220207
Short name T3064
Test name
Test status
Simulation time 141095777 ps
CPU time 0.89 seconds
Started Aug 07 06:11:36 PM PDT 24
Finished Aug 07 06:11:37 PM PDT 24
Peak memory 206968 kb
Host smart-fe4868c4-c77b-43e9-97b4-408de43fd4e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14472
20207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1447220207
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1601514035
Short name T2310
Test name
Test status
Simulation time 202331366 ps
CPU time 0.95 seconds
Started Aug 07 06:11:49 PM PDT 24
Finished Aug 07 06:11:50 PM PDT 24
Peak memory 207000 kb
Host smart-8ac110f9-6c76-4ef5-a5dd-5323541a083c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16015
14035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1601514035
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.863920098
Short name T743
Test name
Test status
Simulation time 198468677 ps
CPU time 0.96 seconds
Started Aug 07 06:11:45 PM PDT 24
Finished Aug 07 06:11:46 PM PDT 24
Peak memory 206968 kb
Host smart-92ae1270-796e-484b-a265-b688958d410a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86392
0098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.863920098
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.4217452995
Short name T1478
Test name
Test status
Simulation time 166543582 ps
CPU time 0.85 seconds
Started Aug 07 06:11:43 PM PDT 24
Finished Aug 07 06:11:44 PM PDT 24
Peak memory 207016 kb
Host smart-777558ed-e0c8-46dd-b1fc-d9d654901e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42174
52995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.4217452995
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.441551045
Short name T1134
Test name
Test status
Simulation time 161743537 ps
CPU time 0.83 seconds
Started Aug 07 06:11:45 PM PDT 24
Finished Aug 07 06:11:46 PM PDT 24
Peak memory 206940 kb
Host smart-1bba50cc-d14d-4225-a4a0-e871b89d023d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44155
1045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.441551045
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1885123519
Short name T1794
Test name
Test status
Simulation time 157660187 ps
CPU time 0.85 seconds
Started Aug 07 06:11:47 PM PDT 24
Finished Aug 07 06:11:48 PM PDT 24
Peak memory 206904 kb
Host smart-1aca6314-9627-40cf-ab2e-176389ad4960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18851
23519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1885123519
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3370078739
Short name T789
Test name
Test status
Simulation time 269348033 ps
CPU time 1.06 seconds
Started Aug 07 06:11:43 PM PDT 24
Finished Aug 07 06:11:44 PM PDT 24
Peak memory 206980 kb
Host smart-d4298093-69ad-466d-acde-6ef18425d972
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3370078739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3370078739
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.824760400
Short name T2149
Test name
Test status
Simulation time 138331626 ps
CPU time 0.85 seconds
Started Aug 07 06:11:46 PM PDT 24
Finished Aug 07 06:11:47 PM PDT 24
Peak memory 206876 kb
Host smart-4d4bf93c-4077-4214-a682-2ed16b66c751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82476
0400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.824760400
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2234472489
Short name T34
Test name
Test status
Simulation time 71609628 ps
CPU time 0.74 seconds
Started Aug 07 06:11:41 PM PDT 24
Finished Aug 07 06:11:42 PM PDT 24
Peak memory 206980 kb
Host smart-f9366edb-7ce4-4e16-a409-69b0c75a3552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22344
72489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2234472489
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.221834992
Short name T2417
Test name
Test status
Simulation time 12279543374 ps
CPU time 29.34 seconds
Started Aug 07 06:11:47 PM PDT 24
Finished Aug 07 06:12:16 PM PDT 24
Peak memory 219744 kb
Host smart-3d4236bc-ea35-4f82-881e-9e44ed573c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22183
4992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.221834992
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.4179301337
Short name T2296
Test name
Test status
Simulation time 176975492 ps
CPU time 0.91 seconds
Started Aug 07 06:11:43 PM PDT 24
Finished Aug 07 06:11:44 PM PDT 24
Peak memory 206996 kb
Host smart-e1a6c97a-e623-41e8-bf49-9f5b6bf2f9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41793
01337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.4179301337
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2878125004
Short name T1749
Test name
Test status
Simulation time 187182890 ps
CPU time 0.88 seconds
Started Aug 07 06:11:43 PM PDT 24
Finished Aug 07 06:11:44 PM PDT 24
Peak memory 207012 kb
Host smart-ae75dcf4-da47-4947-9134-1cae07db89af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28781
25004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2878125004
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.1530235582
Short name T1697
Test name
Test status
Simulation time 231778880 ps
CPU time 1 seconds
Started Aug 07 06:11:43 PM PDT 24
Finished Aug 07 06:11:45 PM PDT 24
Peak memory 206980 kb
Host smart-e54a6857-0e02-4ec5-8a04-8b94d0c14cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15302
35582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.1530235582
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.230958982
Short name T1111
Test name
Test status
Simulation time 165295126 ps
CPU time 0.93 seconds
Started Aug 07 06:11:42 PM PDT 24
Finished Aug 07 06:11:43 PM PDT 24
Peak memory 206960 kb
Host smart-1442356f-4894-4ac6-8b2a-8acb510af3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23095
8982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.230958982
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.3952238783
Short name T1824
Test name
Test status
Simulation time 153924847 ps
CPU time 0.86 seconds
Started Aug 07 06:11:42 PM PDT 24
Finished Aug 07 06:11:43 PM PDT 24
Peak memory 206984 kb
Host smart-bce5dbdf-a6ba-4f5f-89ea-ddab7378c5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39522
38783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.3952238783
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_rx_full.3275450853
Short name T47
Test name
Test status
Simulation time 357118674 ps
CPU time 1.3 seconds
Started Aug 07 06:11:42 PM PDT 24
Finished Aug 07 06:11:44 PM PDT 24
Peak memory 206916 kb
Host smart-012379c3-921f-4341-a597-20f62e5cd697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32754
50853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.3275450853
Directory /workspace/45.usbdev_rx_full/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2241055647
Short name T2295
Test name
Test status
Simulation time 155835590 ps
CPU time 0.82 seconds
Started Aug 07 06:11:45 PM PDT 24
Finished Aug 07 06:11:46 PM PDT 24
Peak memory 206872 kb
Host smart-185f2a64-5c9b-4497-8cc0-f9d5ad371bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22410
55647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2241055647
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.761231156
Short name T541
Test name
Test status
Simulation time 150580136 ps
CPU time 0.81 seconds
Started Aug 07 06:11:43 PM PDT 24
Finished Aug 07 06:11:43 PM PDT 24
Peak memory 206980 kb
Host smart-1722a99b-ab92-4cb2-94cc-43286d95c43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76123
1156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.761231156
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3065478599
Short name T3009
Test name
Test status
Simulation time 237919464 ps
CPU time 1.05 seconds
Started Aug 07 06:11:47 PM PDT 24
Finished Aug 07 06:11:48 PM PDT 24
Peak memory 206904 kb
Host smart-b8a99d76-2096-423d-af94-c1aaa081b9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30654
78599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3065478599
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3461894778
Short name T3032
Test name
Test status
Simulation time 3834659967 ps
CPU time 112.18 seconds
Started Aug 07 06:11:43 PM PDT 24
Finished Aug 07 06:13:35 PM PDT 24
Peak memory 216996 kb
Host smart-617217a7-66b6-47f3-aa5b-ac13fc3b20b8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3461894778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3461894778
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2271710204
Short name T2455
Test name
Test status
Simulation time 189796208 ps
CPU time 0.98 seconds
Started Aug 07 06:11:44 PM PDT 24
Finished Aug 07 06:11:45 PM PDT 24
Peak memory 206944 kb
Host smart-4c946b97-c967-4817-9645-00136fd6312b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22717
10204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2271710204
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1679657998
Short name T1581
Test name
Test status
Simulation time 208504618 ps
CPU time 0.92 seconds
Started Aug 07 06:11:41 PM PDT 24
Finished Aug 07 06:11:42 PM PDT 24
Peak memory 206920 kb
Host smart-c50aaf04-4055-45d6-a8ad-6f8ea86c4c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16796
57998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1679657998
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.3923105952
Short name T1232
Test name
Test status
Simulation time 238362780 ps
CPU time 1.03 seconds
Started Aug 07 06:11:52 PM PDT 24
Finished Aug 07 06:11:54 PM PDT 24
Peak memory 206928 kb
Host smart-b3e2b560-a4d9-42b6-b92e-a2711a945933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39231
05952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.3923105952
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.3156536057
Short name T2799
Test name
Test status
Simulation time 2227499379 ps
CPU time 17.16 seconds
Started Aug 07 06:11:42 PM PDT 24
Finished Aug 07 06:11:59 PM PDT 24
Peak memory 215512 kb
Host smart-98dc6849-1e3c-48f3-814f-5a00bcd2ff8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31565
36057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3156536057
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.54481856
Short name T3031
Test name
Test status
Simulation time 6390965234 ps
CPU time 40.34 seconds
Started Aug 07 06:11:33 PM PDT 24
Finished Aug 07 06:12:14 PM PDT 24
Peak memory 207276 kb
Host smart-8739ff05-3490-45d7-869b-f83d8c66cde4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54481856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_host_
handshake.54481856
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.352004900
Short name T1168
Test name
Test status
Simulation time 52870512 ps
CPU time 0.66 seconds
Started Aug 07 06:12:03 PM PDT 24
Finished Aug 07 06:12:03 PM PDT 24
Peak memory 207024 kb
Host smart-297eb694-7182-4e2f-b1db-9005da6d25d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=352004900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.352004900
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3984827038
Short name T1103
Test name
Test status
Simulation time 10843790305 ps
CPU time 12.88 seconds
Started Aug 07 06:11:52 PM PDT 24
Finished Aug 07 06:12:05 PM PDT 24
Peak memory 207308 kb
Host smart-f2cdae6e-00c4-4e75-913f-8479565c6103
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984827038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.3984827038
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.555061117
Short name T2441
Test name
Test status
Simulation time 18763867586 ps
CPU time 21.3 seconds
Started Aug 07 06:11:54 PM PDT 24
Finished Aug 07 06:12:15 PM PDT 24
Peak memory 207276 kb
Host smart-afda3be7-4ba2-4b8a-b689-d3262280dfd1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=555061117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.555061117
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.1399742239
Short name T2765
Test name
Test status
Simulation time 29288019068 ps
CPU time 32.23 seconds
Started Aug 07 06:11:54 PM PDT 24
Finished Aug 07 06:12:26 PM PDT 24
Peak memory 207172 kb
Host smart-aea1f5e2-7faa-476d-ae43-2918d9de974f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399742239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.1399742239
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3972807107
Short name T1336
Test name
Test status
Simulation time 175967808 ps
CPU time 0.88 seconds
Started Aug 07 06:11:53 PM PDT 24
Finished Aug 07 06:11:54 PM PDT 24
Peak memory 206972 kb
Host smart-a741339c-55e3-4d66-b0da-02a1bf7816b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39728
07107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3972807107
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3808026915
Short name T2985
Test name
Test status
Simulation time 158534235 ps
CPU time 0.88 seconds
Started Aug 07 06:11:53 PM PDT 24
Finished Aug 07 06:11:54 PM PDT 24
Peak memory 206976 kb
Host smart-9cacffe1-203b-4981-89fb-4326b09e02cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38080
26915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3808026915
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.1463928747
Short name T1369
Test name
Test status
Simulation time 391494742 ps
CPU time 1.45 seconds
Started Aug 07 06:11:55 PM PDT 24
Finished Aug 07 06:11:57 PM PDT 24
Peak memory 206996 kb
Host smart-b034ef47-313b-47f0-a452-12283d5b382f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14639
28747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.1463928747
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3072061713
Short name T1773
Test name
Test status
Simulation time 1329526940 ps
CPU time 3.46 seconds
Started Aug 07 06:11:52 PM PDT 24
Finished Aug 07 06:11:56 PM PDT 24
Peak memory 207100 kb
Host smart-0f198eb5-c0fb-417c-bce8-7d78b683a91b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3072061713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3072061713
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2414036812
Short name T2834
Test name
Test status
Simulation time 22702693079 ps
CPU time 35.59 seconds
Started Aug 07 06:11:51 PM PDT 24
Finished Aug 07 06:12:26 PM PDT 24
Peak memory 207324 kb
Host smart-a174d3b2-df0e-40a3-ab48-3c0ad15adb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24140
36812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2414036812
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.1348624807
Short name T2868
Test name
Test status
Simulation time 3463715390 ps
CPU time 29.93 seconds
Started Aug 07 06:11:50 PM PDT 24
Finished Aug 07 06:12:20 PM PDT 24
Peak memory 207256 kb
Host smart-57f129c5-2576-483d-a7a8-62cd5ce0d1a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348624807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.1348624807
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.593653368
Short name T1819
Test name
Test status
Simulation time 944036810 ps
CPU time 2.06 seconds
Started Aug 07 06:11:52 PM PDT 24
Finished Aug 07 06:11:55 PM PDT 24
Peak memory 206956 kb
Host smart-9f167702-ae25-4218-998e-9c5fbf633543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59365
3368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.593653368
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.1456223829
Short name T676
Test name
Test status
Simulation time 138580442 ps
CPU time 0.79 seconds
Started Aug 07 06:11:49 PM PDT 24
Finished Aug 07 06:11:50 PM PDT 24
Peak memory 206872 kb
Host smart-0ac9eb30-befd-4579-8843-810873ccfe05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14562
23829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.1456223829
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.1550635472
Short name T1860
Test name
Test status
Simulation time 80257143 ps
CPU time 0.73 seconds
Started Aug 07 06:11:58 PM PDT 24
Finished Aug 07 06:11:59 PM PDT 24
Peak memory 206948 kb
Host smart-27c814e6-2e7d-4878-93e9-3ee21e6a7642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15506
35472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1550635472
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3019635470
Short name T712
Test name
Test status
Simulation time 764145588 ps
CPU time 2.29 seconds
Started Aug 07 06:11:52 PM PDT 24
Finished Aug 07 06:11:54 PM PDT 24
Peak memory 207228 kb
Host smart-ab669e43-1cbc-422c-8e2a-7bfa0a4eb465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30196
35470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3019635470
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_types.3257013242
Short name T233
Test name
Test status
Simulation time 632621623 ps
CPU time 1.68 seconds
Started Aug 07 06:11:52 PM PDT 24
Finished Aug 07 06:11:54 PM PDT 24
Peak memory 206960 kb
Host smart-610fdcd8-5b32-40ef-a45b-0735931762fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3257013242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.3257013242
Directory /workspace/46.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3202908337
Short name T2110
Test name
Test status
Simulation time 284640538 ps
CPU time 2.33 seconds
Started Aug 07 06:11:52 PM PDT 24
Finished Aug 07 06:11:54 PM PDT 24
Peak memory 207108 kb
Host smart-14f067dc-9168-4c26-80a2-9cffd6ba0c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32029
08337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3202908337
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2032887424
Short name T2979
Test name
Test status
Simulation time 219864712 ps
CPU time 1.14 seconds
Started Aug 07 06:11:55 PM PDT 24
Finished Aug 07 06:11:56 PM PDT 24
Peak memory 207152 kb
Host smart-7928617f-3981-47d7-b2b7-19e3ad6915fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2032887424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2032887424
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1526485706
Short name T1404
Test name
Test status
Simulation time 155020799 ps
CPU time 0.99 seconds
Started Aug 07 06:11:51 PM PDT 24
Finished Aug 07 06:11:52 PM PDT 24
Peak memory 206984 kb
Host smart-776215c2-cecf-4dc3-81d5-9f18e9d1eefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15264
85706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1526485706
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1470049621
Short name T1428
Test name
Test status
Simulation time 186056901 ps
CPU time 1.03 seconds
Started Aug 07 06:11:53 PM PDT 24
Finished Aug 07 06:11:55 PM PDT 24
Peak memory 207004 kb
Host smart-d17fbfee-1dc4-4827-8b04-c21aec3f962d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14700
49621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1470049621
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.1964909173
Short name T1330
Test name
Test status
Simulation time 4211075266 ps
CPU time 126.59 seconds
Started Aug 07 06:11:56 PM PDT 24
Finished Aug 07 06:14:03 PM PDT 24
Peak memory 215572 kb
Host smart-bd1587ed-b0da-4220-895e-688da49c5f6b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1964909173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.1964909173
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1168325486
Short name T2814
Test name
Test status
Simulation time 186428139 ps
CPU time 0.87 seconds
Started Aug 07 06:11:56 PM PDT 24
Finished Aug 07 06:11:57 PM PDT 24
Peak memory 207040 kb
Host smart-6d8441e8-fc79-4f85-b313-b19bd2db31ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11683
25486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1168325486
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.1877236426
Short name T2172
Test name
Test status
Simulation time 31170767940 ps
CPU time 48.06 seconds
Started Aug 07 06:11:52 PM PDT 24
Finished Aug 07 06:12:40 PM PDT 24
Peak memory 207296 kb
Host smart-b1c79e5b-8b1c-4853-80df-9cbca673992e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18772
36426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.1877236426
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2756708423
Short name T1628
Test name
Test status
Simulation time 10041548343 ps
CPU time 13.9 seconds
Started Aug 07 06:11:57 PM PDT 24
Finished Aug 07 06:12:11 PM PDT 24
Peak memory 207272 kb
Host smart-42169e5a-5c70-4197-8578-19698f9a3a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27567
08423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2756708423
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.1718811297
Short name T1989
Test name
Test status
Simulation time 2618983327 ps
CPU time 72.92 seconds
Started Aug 07 06:11:51 PM PDT 24
Finished Aug 07 06:13:04 PM PDT 24
Peak memory 217940 kb
Host smart-2748c49f-1598-4ae9-b45b-9e3826fbfcf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17188
11297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.1718811297
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.4022856800
Short name T2858
Test name
Test status
Simulation time 2118135235 ps
CPU time 21.7 seconds
Started Aug 07 06:11:51 PM PDT 24
Finished Aug 07 06:12:13 PM PDT 24
Peak memory 216740 kb
Host smart-fb92c61f-2a81-407a-acb2-b58f8c4dc1fd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4022856800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.4022856800
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3867481693
Short name T1625
Test name
Test status
Simulation time 241572172 ps
CPU time 0.99 seconds
Started Aug 07 06:11:54 PM PDT 24
Finished Aug 07 06:11:55 PM PDT 24
Peak memory 207008 kb
Host smart-894238d6-0528-4a48-9b97-ea6b5b57238c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3867481693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3867481693
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.475745404
Short name T1338
Test name
Test status
Simulation time 220723593 ps
CPU time 0.97 seconds
Started Aug 07 06:11:58 PM PDT 24
Finished Aug 07 06:11:59 PM PDT 24
Peak memory 207012 kb
Host smart-609e3ff1-b761-4bca-9b90-b3b4358f921a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47574
5404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.475745404
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2620879895
Short name T1854
Test name
Test status
Simulation time 3204103265 ps
CPU time 91.26 seconds
Started Aug 07 06:11:59 PM PDT 24
Finished Aug 07 06:13:31 PM PDT 24
Peak memory 216904 kb
Host smart-e921b5ff-289e-480c-bc60-d3b9da72920c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2620879895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2620879895
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1818755239
Short name T1381
Test name
Test status
Simulation time 149200149 ps
CPU time 0.88 seconds
Started Aug 07 06:11:55 PM PDT 24
Finished Aug 07 06:11:56 PM PDT 24
Peak memory 206972 kb
Host smart-222a2f59-9734-4eec-a56c-4cea91e13ac4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1818755239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1818755239
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2987359621
Short name T2111
Test name
Test status
Simulation time 183360506 ps
CPU time 0.88 seconds
Started Aug 07 06:11:55 PM PDT 24
Finished Aug 07 06:11:56 PM PDT 24
Peak memory 207004 kb
Host smart-6843f54e-574a-4503-b64c-ce07888d6399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29873
59621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2987359621
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2618512644
Short name T147
Test name
Test status
Simulation time 187327069 ps
CPU time 0.95 seconds
Started Aug 07 06:11:52 PM PDT 24
Finished Aug 07 06:11:53 PM PDT 24
Peak memory 206992 kb
Host smart-fa2dd821-124c-4500-a90c-0a2f294771f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26185
12644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2618512644
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1135997525
Short name T1755
Test name
Test status
Simulation time 205777188 ps
CPU time 0.97 seconds
Started Aug 07 06:11:56 PM PDT 24
Finished Aug 07 06:11:57 PM PDT 24
Peak memory 206968 kb
Host smart-67f20ad3-9774-4a81-914e-e53930bd5433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11359
97525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1135997525
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2743593765
Short name T3036
Test name
Test status
Simulation time 190729884 ps
CPU time 0.94 seconds
Started Aug 07 06:12:06 PM PDT 24
Finished Aug 07 06:12:07 PM PDT 24
Peak memory 206904 kb
Host smart-e682368a-7c1c-4a77-a522-94651d5fc1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27435
93765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2743593765
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2622156027
Short name T1489
Test name
Test status
Simulation time 174821056 ps
CPU time 0.85 seconds
Started Aug 07 06:12:06 PM PDT 24
Finished Aug 07 06:12:07 PM PDT 24
Peak memory 206972 kb
Host smart-8729577d-0d71-4edb-ba63-3c347968eda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26221
56027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2622156027
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.4120497489
Short name T1938
Test name
Test status
Simulation time 150096055 ps
CPU time 0.91 seconds
Started Aug 07 06:12:03 PM PDT 24
Finished Aug 07 06:12:04 PM PDT 24
Peak memory 206932 kb
Host smart-407e979d-8bbc-4e92-8ca3-02b7328d012b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41204
97489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.4120497489
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.4111736930
Short name T1044
Test name
Test status
Simulation time 238166749 ps
CPU time 1.07 seconds
Started Aug 07 06:12:02 PM PDT 24
Finished Aug 07 06:12:04 PM PDT 24
Peak memory 206940 kb
Host smart-725aa720-5709-423d-bfcf-a43ebff461df
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4111736930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.4111736930
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.157219203
Short name T2251
Test name
Test status
Simulation time 143494952 ps
CPU time 0.83 seconds
Started Aug 07 06:12:06 PM PDT 24
Finished Aug 07 06:12:07 PM PDT 24
Peak memory 206944 kb
Host smart-09e4a509-d668-4a75-aa54-bc13f6023290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15721
9203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.157219203
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3185219803
Short name T1225
Test name
Test status
Simulation time 31095568 ps
CPU time 0.7 seconds
Started Aug 07 06:12:05 PM PDT 24
Finished Aug 07 06:12:06 PM PDT 24
Peak memory 206948 kb
Host smart-33eb7bb2-2325-4a74-babe-4262c6ee15ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31852
19803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3185219803
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.4025610005
Short name T2300
Test name
Test status
Simulation time 20257614097 ps
CPU time 53.64 seconds
Started Aug 07 06:12:05 PM PDT 24
Finished Aug 07 06:12:59 PM PDT 24
Peak memory 215520 kb
Host smart-e6208f84-c36e-4c05-9ef7-a69b860150bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40256
10005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.4025610005
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1166198130
Short name T2392
Test name
Test status
Simulation time 160648623 ps
CPU time 0.87 seconds
Started Aug 07 06:12:10 PM PDT 24
Finished Aug 07 06:12:11 PM PDT 24
Peak memory 206856 kb
Host smart-15977721-e456-4063-b386-88e0cdbb90ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11661
98130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1166198130
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1358966683
Short name T998
Test name
Test status
Simulation time 179576351 ps
CPU time 0.95 seconds
Started Aug 07 06:12:02 PM PDT 24
Finished Aug 07 06:12:03 PM PDT 24
Peak memory 206972 kb
Host smart-5bca335c-1248-4033-8fce-775a5517ac54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13589
66683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1358966683
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.2800040789
Short name T1996
Test name
Test status
Simulation time 201226713 ps
CPU time 0.94 seconds
Started Aug 07 06:12:04 PM PDT 24
Finished Aug 07 06:12:05 PM PDT 24
Peak memory 206964 kb
Host smart-cef54d99-491c-4608-b0c0-955301dd1dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28000
40789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.2800040789
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1577208383
Short name T1147
Test name
Test status
Simulation time 176826773 ps
CPU time 0.9 seconds
Started Aug 07 06:12:04 PM PDT 24
Finished Aug 07 06:12:05 PM PDT 24
Peak memory 206984 kb
Host smart-af5cc0c0-48cb-472d-a369-2b80f80e1c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15772
08383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1577208383
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.193189192
Short name T73
Test name
Test status
Simulation time 165222236 ps
CPU time 0.86 seconds
Started Aug 07 06:12:02 PM PDT 24
Finished Aug 07 06:12:03 PM PDT 24
Peak memory 206916 kb
Host smart-53b8b847-3df7-4b27-835b-78cc3ac17171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19318
9192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.193189192
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_rx_full.1913194861
Short name T51
Test name
Test status
Simulation time 243145058 ps
CPU time 1.02 seconds
Started Aug 07 06:12:04 PM PDT 24
Finished Aug 07 06:12:05 PM PDT 24
Peak memory 206988 kb
Host smart-e2cbdaf7-b0d9-4b82-8a85-5535d43b8b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19131
94861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.1913194861
Directory /workspace/46.usbdev_rx_full/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3610150235
Short name T633
Test name
Test status
Simulation time 144412506 ps
CPU time 0.85 seconds
Started Aug 07 06:12:02 PM PDT 24
Finished Aug 07 06:12:03 PM PDT 24
Peak memory 206960 kb
Host smart-d7d739b1-fbe4-474a-80ca-3ee150aaabb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36101
50235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3610150235
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2772898186
Short name T2497
Test name
Test status
Simulation time 191446236 ps
CPU time 0.9 seconds
Started Aug 07 06:12:07 PM PDT 24
Finished Aug 07 06:12:08 PM PDT 24
Peak memory 207004 kb
Host smart-6bb191f8-c5dc-4a7a-affa-b5a6ef6a2b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27728
98186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2772898186
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2916286597
Short name T1952
Test name
Test status
Simulation time 248295756 ps
CPU time 1.06 seconds
Started Aug 07 06:12:05 PM PDT 24
Finished Aug 07 06:12:06 PM PDT 24
Peak memory 207000 kb
Host smart-eaf76527-3915-47cc-82c7-4afbc466420c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29162
86597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2916286597
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.257147414
Short name T1830
Test name
Test status
Simulation time 2301251029 ps
CPU time 23.23 seconds
Started Aug 07 06:12:03 PM PDT 24
Finished Aug 07 06:12:27 PM PDT 24
Peak memory 217396 kb
Host smart-5a6ec797-552c-4477-b8ea-1c42ed85c4d1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=257147414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.257147414
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.913657801
Short name T1936
Test name
Test status
Simulation time 227386123 ps
CPU time 0.97 seconds
Started Aug 07 06:12:02 PM PDT 24
Finished Aug 07 06:12:03 PM PDT 24
Peak memory 206988 kb
Host smart-17998b0a-eecc-48a3-ac0b-887cee19f01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91365
7801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.913657801
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2500361886
Short name T2206
Test name
Test status
Simulation time 166126579 ps
CPU time 0.85 seconds
Started Aug 07 06:12:05 PM PDT 24
Finished Aug 07 06:12:06 PM PDT 24
Peak memory 207040 kb
Host smart-0994bb2d-0f03-43a6-a791-524bade26df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25003
61886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2500361886
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.2890009305
Short name T231
Test name
Test status
Simulation time 755612868 ps
CPU time 2.1 seconds
Started Aug 07 06:12:08 PM PDT 24
Finished Aug 07 06:12:10 PM PDT 24
Peak memory 207192 kb
Host smart-108c7771-9556-4716-a276-3b5cd55bd9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28900
09305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2890009305
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.2941335121
Short name T1198
Test name
Test status
Simulation time 3895086796 ps
CPU time 30.41 seconds
Started Aug 07 06:12:02 PM PDT 24
Finished Aug 07 06:12:33 PM PDT 24
Peak memory 217144 kb
Host smart-ec4ddfc9-0f68-4d86-bb71-e274e3e0c30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29413
35121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.2941335121
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.4099554116
Short name T2816
Test name
Test status
Simulation time 1438026683 ps
CPU time 31.81 seconds
Started Aug 07 06:11:54 PM PDT 24
Finished Aug 07 06:12:26 PM PDT 24
Peak memory 206992 kb
Host smart-0fe94e18-57c1-4563-b90f-6ef465a13e57
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099554116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.4099554116
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.959359035
Short name T1607
Test name
Test status
Simulation time 37222067 ps
CPU time 0.65 seconds
Started Aug 07 06:12:13 PM PDT 24
Finished Aug 07 06:12:14 PM PDT 24
Peak memory 207068 kb
Host smart-36b3f7bb-31ca-43a9-9770-6ecfdd23435e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=959359035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.959359035
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.4213008720
Short name T1593
Test name
Test status
Simulation time 6223306460 ps
CPU time 7.71 seconds
Started Aug 07 06:12:06 PM PDT 24
Finished Aug 07 06:12:14 PM PDT 24
Peak memory 215472 kb
Host smart-2da8273a-fd1a-42eb-bb5b-3bbb81cf010f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213008720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.4213008720
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1611197789
Short name T1234
Test name
Test status
Simulation time 20915925305 ps
CPU time 25.18 seconds
Started Aug 07 06:12:06 PM PDT 24
Finished Aug 07 06:12:32 PM PDT 24
Peak memory 207284 kb
Host smart-cfde597a-c998-4fa2-8fcb-964ac42af3d0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611197789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1611197789
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3144843152
Short name T1148
Test name
Test status
Simulation time 24012883320 ps
CPU time 26.63 seconds
Started Aug 07 06:12:04 PM PDT 24
Finished Aug 07 06:12:31 PM PDT 24
Peak memory 215432 kb
Host smart-6bc6717c-2c6f-46c6-963c-ab3b598bef79
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144843152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.3144843152
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1324887280
Short name T2174
Test name
Test status
Simulation time 145602587 ps
CPU time 0.88 seconds
Started Aug 07 06:12:08 PM PDT 24
Finished Aug 07 06:12:09 PM PDT 24
Peak memory 207196 kb
Host smart-1740c9b6-9f7a-41fc-836d-52a3c8654076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13248
87280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1324887280
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.3222853208
Short name T3021
Test name
Test status
Simulation time 145576934 ps
CPU time 0.82 seconds
Started Aug 07 06:12:04 PM PDT 24
Finished Aug 07 06:12:05 PM PDT 24
Peak memory 206964 kb
Host smart-0eca252a-a624-49fc-995e-27790004fa97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32228
53208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.3222853208
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.2280182412
Short name T1297
Test name
Test status
Simulation time 291211641 ps
CPU time 1.12 seconds
Started Aug 07 06:12:05 PM PDT 24
Finished Aug 07 06:12:06 PM PDT 24
Peak memory 207000 kb
Host smart-e40d5391-6b82-4240-9c93-1eecdba8e898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22801
82412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2280182412
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.151929242
Short name T3048
Test name
Test status
Simulation time 444322416 ps
CPU time 1.34 seconds
Started Aug 07 06:12:01 PM PDT 24
Finished Aug 07 06:12:03 PM PDT 24
Peak memory 206908 kb
Host smart-580a0ac4-96d8-4033-a573-9d2d3a7e34a8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=151929242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.151929242
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.2091492451
Short name T2972
Test name
Test status
Simulation time 37233478760 ps
CPU time 70.85 seconds
Started Aug 07 06:12:02 PM PDT 24
Finished Aug 07 06:13:13 PM PDT 24
Peak memory 207304 kb
Host smart-23963135-f95c-44ab-8f66-f43d0b6872ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20914
92451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.2091492451
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.2367146507
Short name T3092
Test name
Test status
Simulation time 744912782 ps
CPU time 4.98 seconds
Started Aug 07 06:12:02 PM PDT 24
Finished Aug 07 06:12:07 PM PDT 24
Peak memory 207196 kb
Host smart-68b70079-ab05-4a65-a366-e7dd1750f8de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367146507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.2367146507
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1344399260
Short name T2856
Test name
Test status
Simulation time 637498806 ps
CPU time 1.53 seconds
Started Aug 07 06:12:04 PM PDT 24
Finished Aug 07 06:12:06 PM PDT 24
Peak memory 206972 kb
Host smart-78f9fe74-ef2a-484a-8542-77e9aac86470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13443
99260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1344399260
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1129045354
Short name T1333
Test name
Test status
Simulation time 133715120 ps
CPU time 0.79 seconds
Started Aug 07 06:12:04 PM PDT 24
Finished Aug 07 06:12:05 PM PDT 24
Peak memory 206988 kb
Host smart-db3fb477-1eb8-421e-9da5-71b01bcfa670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11290
45354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1129045354
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3913628366
Short name T2412
Test name
Test status
Simulation time 47182338 ps
CPU time 0.73 seconds
Started Aug 07 06:12:04 PM PDT 24
Finished Aug 07 06:12:05 PM PDT 24
Peak memory 206920 kb
Host smart-87eed8c2-4e0e-4dc5-aed6-a59bc3470bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39136
28366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3913628366
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1280186351
Short name T688
Test name
Test status
Simulation time 1008576942 ps
CPU time 2.82 seconds
Started Aug 07 06:12:01 PM PDT 24
Finished Aug 07 06:12:04 PM PDT 24
Peak memory 207248 kb
Host smart-d84a4261-2a23-4622-9a59-1bbf43ed4b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12801
86351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1280186351
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3462676604
Short name T3014
Test name
Test status
Simulation time 172123020 ps
CPU time 2 seconds
Started Aug 07 06:12:08 PM PDT 24
Finished Aug 07 06:12:10 PM PDT 24
Peak memory 207424 kb
Host smart-aecf6f77-d27e-48c4-a076-2edcacdfe180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34626
76604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3462676604
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3869687424
Short name T2122
Test name
Test status
Simulation time 158174067 ps
CPU time 0.89 seconds
Started Aug 07 06:12:08 PM PDT 24
Finished Aug 07 06:12:09 PM PDT 24
Peak memory 207188 kb
Host smart-94ab7630-1521-4cc5-b9e8-eb6452b04fb9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3869687424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3869687424
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2659122730
Short name T2909
Test name
Test status
Simulation time 157094481 ps
CPU time 0.86 seconds
Started Aug 07 06:12:04 PM PDT 24
Finished Aug 07 06:12:05 PM PDT 24
Peak memory 206928 kb
Host smart-c97a4671-7fce-4044-a057-d918cb448ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
22730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2659122730
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.4138242363
Short name T632
Test name
Test status
Simulation time 265975027 ps
CPU time 1.04 seconds
Started Aug 07 06:12:07 PM PDT 24
Finished Aug 07 06:12:08 PM PDT 24
Peak memory 207000 kb
Host smart-bbd5663b-6bd0-44f6-810b-0594e96d7434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41382
42363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.4138242363
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.900455018
Short name T1473
Test name
Test status
Simulation time 4077040462 ps
CPU time 121.32 seconds
Started Aug 07 06:12:04 PM PDT 24
Finished Aug 07 06:14:05 PM PDT 24
Peak memory 217360 kb
Host smart-3d7d5bfa-da10-4853-8b34-7cc13c1a483e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=900455018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.900455018
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.1045362490
Short name T750
Test name
Test status
Simulation time 13692360983 ps
CPU time 97.25 seconds
Started Aug 07 06:12:01 PM PDT 24
Finished Aug 07 06:13:39 PM PDT 24
Peak memory 207284 kb
Host smart-e183e381-6acd-47ec-8e68-fc209406b9e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1045362490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.1045362490
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3201477653
Short name T1342
Test name
Test status
Simulation time 220354048 ps
CPU time 0.99 seconds
Started Aug 07 06:12:13 PM PDT 24
Finished Aug 07 06:12:14 PM PDT 24
Peak memory 206980 kb
Host smart-8c503c07-2c98-4603-897f-682053bc00df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32014
77653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3201477653
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.3318715153
Short name T1301
Test name
Test status
Simulation time 14480955914 ps
CPU time 19.54 seconds
Started Aug 07 06:12:15 PM PDT 24
Finished Aug 07 06:12:34 PM PDT 24
Peak memory 207276 kb
Host smart-f5d87ec3-367d-425c-8aae-ce1e9337027a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33187
15153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.3318715153
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1483400882
Short name T208
Test name
Test status
Simulation time 5982254417 ps
CPU time 8.71 seconds
Started Aug 07 06:12:14 PM PDT 24
Finished Aug 07 06:12:23 PM PDT 24
Peak memory 215480 kb
Host smart-f50cba1e-390d-4e9e-a07d-229d233ac195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14834
00882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1483400882
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.1938779537
Short name T2248
Test name
Test status
Simulation time 4541091296 ps
CPU time 33.07 seconds
Started Aug 07 06:12:18 PM PDT 24
Finished Aug 07 06:12:51 PM PDT 24
Peak memory 223732 kb
Host smart-5467792c-8d03-46c3-ac4c-46c91a02a521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19387
79537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.1938779537
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.1682671654
Short name T966
Test name
Test status
Simulation time 2930670222 ps
CPU time 31.34 seconds
Started Aug 07 06:12:17 PM PDT 24
Finished Aug 07 06:12:49 PM PDT 24
Peak memory 217064 kb
Host smart-051d76e3-3655-4a1a-ba12-642af8eff021
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1682671654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.1682671654
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.2889637580
Short name T722
Test name
Test status
Simulation time 244315506 ps
CPU time 0.97 seconds
Started Aug 07 06:12:15 PM PDT 24
Finished Aug 07 06:12:16 PM PDT 24
Peak memory 206996 kb
Host smart-e734f91b-8260-4828-8ee8-10f706391fb0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2889637580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.2889637580
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.777483404
Short name T622
Test name
Test status
Simulation time 267324875 ps
CPU time 1.02 seconds
Started Aug 07 06:12:15 PM PDT 24
Finished Aug 07 06:12:16 PM PDT 24
Peak memory 206996 kb
Host smart-854d2666-f708-4d78-bc76-ad05ed8c6784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77748
3404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.777483404
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3982844346
Short name T1056
Test name
Test status
Simulation time 3607848565 ps
CPU time 28.5 seconds
Started Aug 07 06:12:17 PM PDT 24
Finished Aug 07 06:12:46 PM PDT 24
Peak memory 215516 kb
Host smart-b8dc8792-4dad-43f1-9316-39f782a1db5f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3982844346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3982844346
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.547767273
Short name T1756
Test name
Test status
Simulation time 245097115 ps
CPU time 0.96 seconds
Started Aug 07 06:12:15 PM PDT 24
Finished Aug 07 06:12:16 PM PDT 24
Peak memory 206940 kb
Host smart-1454a901-7958-4f5e-9628-12e7058aa25c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=547767273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.547767273
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3866792356
Short name T1947
Test name
Test status
Simulation time 187394366 ps
CPU time 0.89 seconds
Started Aug 07 06:12:15 PM PDT 24
Finished Aug 07 06:12:16 PM PDT 24
Peak memory 206916 kb
Host smart-826e282d-c796-437c-9924-5d0f8d6e883d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38667
92356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3866792356
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.922887715
Short name T134
Test name
Test status
Simulation time 206612367 ps
CPU time 0.98 seconds
Started Aug 07 06:12:15 PM PDT 24
Finished Aug 07 06:12:16 PM PDT 24
Peak memory 206984 kb
Host smart-ebcb2261-3d25-4c3d-9792-ffd44633ec74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92288
7715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.922887715
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3421662025
Short name T1051
Test name
Test status
Simulation time 203229290 ps
CPU time 0.94 seconds
Started Aug 07 06:12:16 PM PDT 24
Finished Aug 07 06:12:17 PM PDT 24
Peak memory 207008 kb
Host smart-c002e9fa-fb86-4fca-912b-d6350d3baebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34216
62025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3421662025
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2834146287
Short name T1174
Test name
Test status
Simulation time 185357717 ps
CPU time 0.89 seconds
Started Aug 07 06:12:14 PM PDT 24
Finished Aug 07 06:12:15 PM PDT 24
Peak memory 207016 kb
Host smart-503ace35-d630-4a92-b11c-31ffda2430b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28341
46287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2834146287
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1059700694
Short name T2413
Test name
Test status
Simulation time 146394898 ps
CPU time 0.86 seconds
Started Aug 07 06:12:17 PM PDT 24
Finished Aug 07 06:12:18 PM PDT 24
Peak memory 207008 kb
Host smart-ade4d0b0-66f9-462b-ad4d-202193ae940d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10597
00694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1059700694
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3307267124
Short name T2024
Test name
Test status
Simulation time 163243015 ps
CPU time 0.86 seconds
Started Aug 07 06:12:14 PM PDT 24
Finished Aug 07 06:12:15 PM PDT 24
Peak memory 207000 kb
Host smart-0bcbbb0e-e2ce-4cce-b14d-0f3b88f1e05d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33072
67124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3307267124
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.2928070000
Short name T2981
Test name
Test status
Simulation time 235263304 ps
CPU time 1.04 seconds
Started Aug 07 06:12:12 PM PDT 24
Finished Aug 07 06:12:13 PM PDT 24
Peak memory 206924 kb
Host smart-c76cb464-32cd-464c-a429-8720b2c5a0b4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2928070000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.2928070000
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.594643789
Short name T555
Test name
Test status
Simulation time 182106390 ps
CPU time 0.91 seconds
Started Aug 07 06:12:13 PM PDT 24
Finished Aug 07 06:12:14 PM PDT 24
Peak memory 206956 kb
Host smart-c199ed11-1f18-40f2-a386-38b1a3d6eee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59464
3789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.594643789
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2658092423
Short name T2923
Test name
Test status
Simulation time 41092736 ps
CPU time 0.7 seconds
Started Aug 07 06:12:15 PM PDT 24
Finished Aug 07 06:12:16 PM PDT 24
Peak memory 206976 kb
Host smart-b8a56476-a1fa-4b9d-bcf6-f7686fee37e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26580
92423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2658092423
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1472877185
Short name T2910
Test name
Test status
Simulation time 16355326838 ps
CPU time 44.82 seconds
Started Aug 07 06:12:14 PM PDT 24
Finished Aug 07 06:12:59 PM PDT 24
Peak memory 215544 kb
Host smart-a465a04a-0117-49d0-a585-db08aebd82cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14728
77185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1472877185
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3930149015
Short name T2418
Test name
Test status
Simulation time 207660074 ps
CPU time 0.96 seconds
Started Aug 07 06:12:13 PM PDT 24
Finished Aug 07 06:12:14 PM PDT 24
Peak memory 207000 kb
Host smart-b38a2f3c-c489-4cc7-a5a7-f85c948f5c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39301
49015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3930149015
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2417009570
Short name T2322
Test name
Test status
Simulation time 227184955 ps
CPU time 0.96 seconds
Started Aug 07 06:12:12 PM PDT 24
Finished Aug 07 06:12:13 PM PDT 24
Peak memory 206956 kb
Host smart-b703530e-7d18-4bbc-add7-c941d9e47979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24170
09570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2417009570
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.1687370983
Short name T1652
Test name
Test status
Simulation time 213161437 ps
CPU time 0.98 seconds
Started Aug 07 06:12:19 PM PDT 24
Finished Aug 07 06:12:21 PM PDT 24
Peak memory 207040 kb
Host smart-2e4fe0d3-9a77-4ae5-abdd-da7d0d33a11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16873
70983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1687370983
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.4146195481
Short name T2746
Test name
Test status
Simulation time 184826607 ps
CPU time 0.93 seconds
Started Aug 07 06:12:12 PM PDT 24
Finished Aug 07 06:12:13 PM PDT 24
Peak memory 207012 kb
Host smart-a1c3b779-7a0a-4d64-9c9b-d96804cdb3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41461
95481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.4146195481
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.2026337143
Short name T2562
Test name
Test status
Simulation time 181849032 ps
CPU time 0.88 seconds
Started Aug 07 06:12:15 PM PDT 24
Finished Aug 07 06:12:16 PM PDT 24
Peak memory 206952 kb
Host smart-1ddaabdc-8675-48f1-a9b8-ee9953c4be53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20263
37143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.2026337143
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_rx_full.1246629823
Short name T2142
Test name
Test status
Simulation time 388537150 ps
CPU time 1.32 seconds
Started Aug 07 06:12:18 PM PDT 24
Finished Aug 07 06:12:19 PM PDT 24
Peak memory 207044 kb
Host smart-84c401ac-1437-423c-b6de-a3aeb2aa1dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12466
29823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.1246629823
Directory /workspace/47.usbdev_rx_full/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2731315025
Short name T581
Test name
Test status
Simulation time 162071784 ps
CPU time 0.83 seconds
Started Aug 07 06:12:17 PM PDT 24
Finished Aug 07 06:12:18 PM PDT 24
Peak memory 207008 kb
Host smart-45946ca2-1f70-418c-bffd-4ce918bb3383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27313
15025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2731315025
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.202802410
Short name T2448
Test name
Test status
Simulation time 152562578 ps
CPU time 0.92 seconds
Started Aug 07 06:12:11 PM PDT 24
Finished Aug 07 06:12:12 PM PDT 24
Peak memory 206912 kb
Host smart-d3f4abfe-ecbb-4f03-948d-34ef0ef6de19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20280
2410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.202802410
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.4051855614
Short name T2824
Test name
Test status
Simulation time 246402703 ps
CPU time 1.05 seconds
Started Aug 07 06:12:14 PM PDT 24
Finished Aug 07 06:12:15 PM PDT 24
Peak memory 207016 kb
Host smart-2a1e3044-431e-4cf9-a334-f5dfbab0d7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40518
55614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.4051855614
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.635934217
Short name T1602
Test name
Test status
Simulation time 2546970449 ps
CPU time 25.78 seconds
Started Aug 07 06:12:14 PM PDT 24
Finished Aug 07 06:12:40 PM PDT 24
Peak memory 217380 kb
Host smart-1918df85-6074-414a-95af-98afcb4ea872
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=635934217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.635934217
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1183758970
Short name T475
Test name
Test status
Simulation time 172516721 ps
CPU time 0.87 seconds
Started Aug 07 06:12:17 PM PDT 24
Finished Aug 07 06:12:18 PM PDT 24
Peak memory 207216 kb
Host smart-04e10d6b-4546-49f0-b537-54280ed09e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11837
58970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1183758970
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1579957956
Short name T2599
Test name
Test status
Simulation time 177479440 ps
CPU time 0.86 seconds
Started Aug 07 06:12:14 PM PDT 24
Finished Aug 07 06:12:15 PM PDT 24
Peak memory 206992 kb
Host smart-07a574dc-eef9-46f0-9359-341f2926a34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15799
57956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1579957956
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1353377956
Short name T1994
Test name
Test status
Simulation time 1372433903 ps
CPU time 3.27 seconds
Started Aug 07 06:12:15 PM PDT 24
Finished Aug 07 06:12:19 PM PDT 24
Peak memory 207076 kb
Host smart-17f46509-f234-41d1-862c-991de4fb60f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13533
77956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1353377956
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2419610979
Short name T496
Test name
Test status
Simulation time 2465910568 ps
CPU time 68.49 seconds
Started Aug 07 06:12:15 PM PDT 24
Finished Aug 07 06:13:23 PM PDT 24
Peak memory 215500 kb
Host smart-896646c3-8934-4c70-99a7-9a86adb1e56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24196
10979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2419610979
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.1956677832
Short name T1359
Test name
Test status
Simulation time 1594142507 ps
CPU time 12.62 seconds
Started Aug 07 06:12:05 PM PDT 24
Finished Aug 07 06:12:18 PM PDT 24
Peak memory 207212 kb
Host smart-866ddd96-8f04-4a4e-876b-17225970c050
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956677832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.1956677832
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.541589671
Short name T2057
Test name
Test status
Simulation time 28021205 ps
CPU time 0.67 seconds
Started Aug 07 06:12:43 PM PDT 24
Finished Aug 07 06:12:44 PM PDT 24
Peak memory 207056 kb
Host smart-53e4a397-b9d8-4d02-82a9-b7987f63c584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=541589671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.541589671
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.2295971216
Short name T918
Test name
Test status
Simulation time 7033939290 ps
CPU time 9.61 seconds
Started Aug 07 06:12:15 PM PDT 24
Finished Aug 07 06:12:24 PM PDT 24
Peak memory 215488 kb
Host smart-32748f8c-6508-41dc-bc91-dbf9400b3b6b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295971216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.2295971216
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.289495167
Short name T2201
Test name
Test status
Simulation time 13389104749 ps
CPU time 14.86 seconds
Started Aug 07 06:12:13 PM PDT 24
Finished Aug 07 06:12:28 PM PDT 24
Peak memory 215464 kb
Host smart-0746166c-613a-4714-8000-9dce8424f580
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=289495167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.289495167
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.999942361
Short name T117
Test name
Test status
Simulation time 24651373950 ps
CPU time 27.6 seconds
Started Aug 07 06:12:13 PM PDT 24
Finished Aug 07 06:12:41 PM PDT 24
Peak memory 215488 kb
Host smart-c3d38ce3-9bfa-4046-95ce-ee142de2c2dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999942361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ao
n_wake_resume.999942361
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3079395769
Short name T1382
Test name
Test status
Simulation time 159867051 ps
CPU time 0.87 seconds
Started Aug 07 06:12:28 PM PDT 24
Finished Aug 07 06:12:30 PM PDT 24
Peak memory 206984 kb
Host smart-dc613cae-b4a8-467c-8863-0179f2dbf671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30793
95769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3079395769
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.213468175
Short name T760
Test name
Test status
Simulation time 201227642 ps
CPU time 0.88 seconds
Started Aug 07 06:12:25 PM PDT 24
Finished Aug 07 06:12:26 PM PDT 24
Peak memory 206952 kb
Host smart-ac05905b-0a88-4cf2-a95d-1638962ea3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21346
8175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.213468175
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1706663075
Short name T2113
Test name
Test status
Simulation time 402069534 ps
CPU time 1.54 seconds
Started Aug 07 06:12:28 PM PDT 24
Finished Aug 07 06:12:30 PM PDT 24
Peak memory 206904 kb
Host smart-71f3d618-d869-426f-a756-5ec8364eb26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17066
63075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1706663075
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1215035361
Short name T692
Test name
Test status
Simulation time 774638268 ps
CPU time 2.19 seconds
Started Aug 07 06:12:32 PM PDT 24
Finished Aug 07 06:12:35 PM PDT 24
Peak memory 206920 kb
Host smart-797dc9b6-882d-4b34-85fb-24b6226e309d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1215035361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1215035361
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.3049367184
Short name T1673
Test name
Test status
Simulation time 870435169 ps
CPU time 5.38 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:12:32 PM PDT 24
Peak memory 207184 kb
Host smart-05298ce4-382a-428a-857e-47c663845d86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049367184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.3049367184
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.674402037
Short name T1084
Test name
Test status
Simulation time 729927358 ps
CPU time 1.83 seconds
Started Aug 07 06:12:23 PM PDT 24
Finished Aug 07 06:12:25 PM PDT 24
Peak memory 206936 kb
Host smart-567742e0-bf27-43cb-99e0-1df5807aabaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67440
2037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.674402037
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1762462050
Short name T2970
Test name
Test status
Simulation time 151856039 ps
CPU time 0.86 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:12:27 PM PDT 24
Peak memory 206984 kb
Host smart-2c4966e8-9235-4800-aef6-8d1702d9983c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17624
62050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1762462050
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.2330918421
Short name T1831
Test name
Test status
Simulation time 39083456 ps
CPU time 0.71 seconds
Started Aug 07 06:12:29 PM PDT 24
Finished Aug 07 06:12:29 PM PDT 24
Peak memory 206968 kb
Host smart-d8923c53-9594-40a5-a1b2-552e745dd900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23309
18421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2330918421
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2086303629
Short name T882
Test name
Test status
Simulation time 1015136179 ps
CPU time 2.61 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:12:29 PM PDT 24
Peak memory 207092 kb
Host smart-608eb4de-d066-45b5-b81b-649f28126fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20863
03629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2086303629
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_types.1135790476
Short name T3065
Test name
Test status
Simulation time 812422903 ps
CPU time 1.95 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:12:28 PM PDT 24
Peak memory 206948 kb
Host smart-4ee57b85-be51-4288-b6b4-dfc06d563300
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1135790476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.1135790476
Directory /workspace/48.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.650042171
Short name T1683
Test name
Test status
Simulation time 154397028 ps
CPU time 1.29 seconds
Started Aug 07 06:12:28 PM PDT 24
Finished Aug 07 06:12:29 PM PDT 24
Peak memory 207156 kb
Host smart-b05a5beb-b53d-4af5-9498-fd269d991725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65004
2171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.650042171
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.635880166
Short name T877
Test name
Test status
Simulation time 261373252 ps
CPU time 1.17 seconds
Started Aug 07 06:12:23 PM PDT 24
Finished Aug 07 06:12:24 PM PDT 24
Peak memory 207200 kb
Host smart-2878d231-b7d8-40db-8dde-4dac80201b16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=635880166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.635880166
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2934713484
Short name T1160
Test name
Test status
Simulation time 179217523 ps
CPU time 0.86 seconds
Started Aug 07 06:12:25 PM PDT 24
Finished Aug 07 06:12:26 PM PDT 24
Peak memory 206956 kb
Host smart-1aeb7f92-4e6b-4a75-9d8f-68b864b48b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29347
13484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2934713484
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2672822807
Short name T1792
Test name
Test status
Simulation time 238852816 ps
CPU time 1 seconds
Started Aug 07 06:12:24 PM PDT 24
Finished Aug 07 06:12:25 PM PDT 24
Peak memory 206976 kb
Host smart-ff9661f0-b592-4341-a655-023cfea4e72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26728
22807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2672822807
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.188256721
Short name T1476
Test name
Test status
Simulation time 4029580385 ps
CPU time 119.48 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:14:25 PM PDT 24
Peak memory 217220 kb
Host smart-3817c3ed-4e38-4be4-9abf-f3930a4f6b00
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=188256721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.188256721
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.1065397984
Short name T3002
Test name
Test status
Simulation time 10758590802 ps
CPU time 131.77 seconds
Started Aug 07 06:12:25 PM PDT 24
Finished Aug 07 06:14:37 PM PDT 24
Peak memory 207288 kb
Host smart-30704ab1-4a81-4ad3-8be2-0495ed6a4846
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1065397984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.1065397984
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3165143249
Short name T869
Test name
Test status
Simulation time 189495470 ps
CPU time 0.97 seconds
Started Aug 07 06:12:25 PM PDT 24
Finished Aug 07 06:12:26 PM PDT 24
Peak memory 206932 kb
Host smart-c20b0751-a8ce-4bc4-a73c-0c5621199ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31651
43249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3165143249
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.51712926
Short name T2179
Test name
Test status
Simulation time 9312025628 ps
CPU time 11.42 seconds
Started Aug 07 06:12:27 PM PDT 24
Finished Aug 07 06:12:38 PM PDT 24
Peak memory 207260 kb
Host smart-684a51ad-5ec4-40ab-914a-c4f5c75ea229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51712
926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.51712926
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.615873612
Short name T3004
Test name
Test status
Simulation time 3403783290 ps
CPU time 31.89 seconds
Started Aug 07 06:12:32 PM PDT 24
Finished Aug 07 06:13:04 PM PDT 24
Peak memory 216320 kb
Host smart-eddad54d-7503-4656-9c29-182d2244126c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61587
3612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.615873612
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.948400099
Short name T634
Test name
Test status
Simulation time 2791921580 ps
CPU time 78.65 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:13:45 PM PDT 24
Peak memory 215540 kb
Host smart-455afb9d-ed4c-46d1-9fb2-cc8d91555e51
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=948400099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.948400099
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3405593606
Short name T1352
Test name
Test status
Simulation time 240589884 ps
CPU time 1.02 seconds
Started Aug 07 06:12:24 PM PDT 24
Finished Aug 07 06:12:25 PM PDT 24
Peak memory 206972 kb
Host smart-9ccd6101-e26a-489e-a0bb-fda5578a1d0b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3405593606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3405593606
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.129411190
Short name T848
Test name
Test status
Simulation time 188945162 ps
CPU time 0.96 seconds
Started Aug 07 06:12:25 PM PDT 24
Finished Aug 07 06:12:26 PM PDT 24
Peak memory 206920 kb
Host smart-9a5d1478-9ac3-4110-88db-18277beecefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12941
1190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.129411190
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.336796755
Short name T631
Test name
Test status
Simulation time 2678277679 ps
CPU time 20.61 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:12:47 PM PDT 24
Peak memory 217164 kb
Host smart-e6614763-a250-40e0-8359-ce664ebbc808
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=336796755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.336796755
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.4101886557
Short name T560
Test name
Test status
Simulation time 155525910 ps
CPU time 0.89 seconds
Started Aug 07 06:12:27 PM PDT 24
Finished Aug 07 06:12:28 PM PDT 24
Peak memory 206908 kb
Host smart-1143f68c-146c-453a-826b-8f646faeac93
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4101886557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.4101886557
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1696954851
Short name T2937
Test name
Test status
Simulation time 140968361 ps
CPU time 0.82 seconds
Started Aug 07 06:12:28 PM PDT 24
Finished Aug 07 06:12:29 PM PDT 24
Peak memory 206944 kb
Host smart-b8bb95e4-ed4c-4873-9a13-5053bc85ab9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16969
54851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1696954851
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3867302016
Short name T161
Test name
Test status
Simulation time 191203896 ps
CPU time 0.93 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:12:27 PM PDT 24
Peak memory 206904 kb
Host smart-55272470-0805-4b8f-a8d5-3a366e89e517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38673
02016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3867302016
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3023978851
Short name T1319
Test name
Test status
Simulation time 154346404 ps
CPU time 0.91 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:12:27 PM PDT 24
Peak memory 206984 kb
Host smart-9adb67fb-8d0f-4e8f-817a-60316232b6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30239
78851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3023978851
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2306392439
Short name T1608
Test name
Test status
Simulation time 223068750 ps
CPU time 0.9 seconds
Started Aug 07 06:12:23 PM PDT 24
Finished Aug 07 06:12:24 PM PDT 24
Peak memory 206908 kb
Host smart-6e868ffa-4f05-4f6e-b87e-229fe3d84b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23063
92439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2306392439
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.462579437
Short name T18
Test name
Test status
Simulation time 187619257 ps
CPU time 0.89 seconds
Started Aug 07 06:12:31 PM PDT 24
Finished Aug 07 06:12:32 PM PDT 24
Peak memory 206884 kb
Host smart-d6c6fd25-cef6-4f0a-93da-201a4aaff622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46257
9437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.462579437
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.4094846121
Short name T1927
Test name
Test status
Simulation time 154692152 ps
CPU time 0.84 seconds
Started Aug 07 06:12:24 PM PDT 24
Finished Aug 07 06:12:25 PM PDT 24
Peak memory 206972 kb
Host smart-0ed59a71-0604-412f-92c5-d2071b7b82c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40948
46121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.4094846121
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.968625083
Short name T803
Test name
Test status
Simulation time 216405240 ps
CPU time 1.05 seconds
Started Aug 07 06:12:28 PM PDT 24
Finished Aug 07 06:12:30 PM PDT 24
Peak memory 206996 kb
Host smart-bbaecf01-62f2-4c91-994a-05e69e4967b9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=968625083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.968625083
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.485177038
Short name T1207
Test name
Test status
Simulation time 144146928 ps
CPU time 0.85 seconds
Started Aug 07 06:12:27 PM PDT 24
Finished Aug 07 06:12:28 PM PDT 24
Peak memory 206956 kb
Host smart-5d8adf4d-1519-4d94-bf8f-8d61635becfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48517
7038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.485177038
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1394949035
Short name T2584
Test name
Test status
Simulation time 66161223 ps
CPU time 0.72 seconds
Started Aug 07 06:12:27 PM PDT 24
Finished Aug 07 06:12:27 PM PDT 24
Peak memory 206864 kb
Host smart-9250a13b-d17a-498c-9afe-3de722d955b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13949
49035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1394949035
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2886772178
Short name T269
Test name
Test status
Simulation time 15121657013 ps
CPU time 39.49 seconds
Started Aug 07 06:12:29 PM PDT 24
Finished Aug 07 06:13:09 PM PDT 24
Peak memory 223716 kb
Host smart-c5cfd7e3-9f16-4858-a9a9-4159bd642686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28867
72178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2886772178
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3222953518
Short name T2579
Test name
Test status
Simulation time 167856731 ps
CPU time 0.88 seconds
Started Aug 07 06:12:31 PM PDT 24
Finished Aug 07 06:12:32 PM PDT 24
Peak memory 207012 kb
Host smart-0151403b-3eef-4265-82a4-80124ca9dd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32229
53518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3222953518
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3538508890
Short name T1145
Test name
Test status
Simulation time 171496854 ps
CPU time 0.91 seconds
Started Aug 07 06:12:29 PM PDT 24
Finished Aug 07 06:12:30 PM PDT 24
Peak memory 207024 kb
Host smart-8c0904a1-5c70-4765-afbf-0a01b6a122f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35385
08890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3538508890
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.955807689
Short name T3106
Test name
Test status
Simulation time 229271272 ps
CPU time 0.99 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:12:27 PM PDT 24
Peak memory 206992 kb
Host smart-648fe408-3d7d-4a04-8ead-d522460e8e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95580
7689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.955807689
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2544525634
Short name T2351
Test name
Test status
Simulation time 187058856 ps
CPU time 0.89 seconds
Started Aug 07 06:12:29 PM PDT 24
Finished Aug 07 06:12:30 PM PDT 24
Peak memory 207024 kb
Host smart-69171c71-8b48-4abb-af54-5d2be38886a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25445
25634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2544525634
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1677843253
Short name T127
Test name
Test status
Simulation time 146706000 ps
CPU time 0.83 seconds
Started Aug 07 06:12:30 PM PDT 24
Finished Aug 07 06:12:31 PM PDT 24
Peak memory 207008 kb
Host smart-d23990c5-7bf0-4816-80fc-9f637e356c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16778
43253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1677843253
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2348397771
Short name T1621
Test name
Test status
Simulation time 198494138 ps
CPU time 1.07 seconds
Started Aug 07 06:12:29 PM PDT 24
Finished Aug 07 06:12:30 PM PDT 24
Peak memory 207008 kb
Host smart-6f6d1743-4edb-4d20-bb35-96554cad611a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23483
97771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2348397771
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3911557597
Short name T2059
Test name
Test status
Simulation time 162553964 ps
CPU time 0.88 seconds
Started Aug 07 06:12:31 PM PDT 24
Finished Aug 07 06:12:32 PM PDT 24
Peak memory 207008 kb
Host smart-8fbc2840-7804-4738-b930-8d9ea8b89a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39115
57597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3911557597
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3060087757
Short name T837
Test name
Test status
Simulation time 243194185 ps
CPU time 1.06 seconds
Started Aug 07 06:12:26 PM PDT 24
Finished Aug 07 06:12:27 PM PDT 24
Peak memory 206904 kb
Host smart-54fa7cd3-01b1-4c36-b1f2-95112de67ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30600
87757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3060087757
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1368372441
Short name T1320
Test name
Test status
Simulation time 3068604648 ps
CPU time 88.7 seconds
Started Aug 07 06:12:25 PM PDT 24
Finished Aug 07 06:13:54 PM PDT 24
Peak memory 217192 kb
Host smart-50f33ff6-ccb8-49a7-b689-45d270d5ac26
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1368372441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1368372441
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.638944773
Short name T2904
Test name
Test status
Simulation time 180024098 ps
CPU time 0.91 seconds
Started Aug 07 06:12:31 PM PDT 24
Finished Aug 07 06:12:32 PM PDT 24
Peak memory 207008 kb
Host smart-f936bc78-e76d-4730-a3ab-77eccdcf63ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63894
4773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.638944773
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.4171982194
Short name T3079
Test name
Test status
Simulation time 155149147 ps
CPU time 0.9 seconds
Started Aug 07 06:12:27 PM PDT 24
Finished Aug 07 06:12:28 PM PDT 24
Peak memory 206904 kb
Host smart-ec6c34c0-818a-4d72-97d8-56da9ccd155d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41719
82194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.4171982194
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.1455025749
Short name T1194
Test name
Test status
Simulation time 693181812 ps
CPU time 1.77 seconds
Started Aug 07 06:12:32 PM PDT 24
Finished Aug 07 06:12:34 PM PDT 24
Peak memory 206940 kb
Host smart-95bab54a-5e20-426c-b4e0-91084f16840f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14550
25749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.1455025749
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3105734595
Short name T1127
Test name
Test status
Simulation time 3634408946 ps
CPU time 37.82 seconds
Started Aug 07 06:12:28 PM PDT 24
Finished Aug 07 06:13:06 PM PDT 24
Peak memory 215500 kb
Host smart-f30a8e50-8335-4bd8-a9ed-be7a06402a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31057
34595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3105734595
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.245091389
Short name T2721
Test name
Test status
Simulation time 3386004833 ps
CPU time 30.43 seconds
Started Aug 07 06:12:30 PM PDT 24
Finished Aug 07 06:13:01 PM PDT 24
Peak memory 207368 kb
Host smart-71e35aff-b985-4fbc-bd73-1c4a2170278c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245091389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_host
_handshake.245091389
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.2514872617
Short name T1002
Test name
Test status
Simulation time 41194519 ps
CPU time 0.65 seconds
Started Aug 07 06:12:44 PM PDT 24
Finished Aug 07 06:12:45 PM PDT 24
Peak memory 207056 kb
Host smart-71be99b3-8c1f-4958-b529-920b4ec92489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2514872617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.2514872617
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.517952388
Short name T2664
Test name
Test status
Simulation time 5848685822 ps
CPU time 7.59 seconds
Started Aug 07 06:12:32 PM PDT 24
Finished Aug 07 06:12:40 PM PDT 24
Peak memory 215436 kb
Host smart-4b09f60c-9235-44e6-ae98-261f15549fab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517952388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_ao
n_wake_disconnect.517952388
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.1497950379
Short name T878
Test name
Test status
Simulation time 21340099494 ps
CPU time 23.78 seconds
Started Aug 07 06:12:33 PM PDT 24
Finished Aug 07 06:12:58 PM PDT 24
Peak memory 207248 kb
Host smart-18500d36-ac94-4e29-b4b1-8b638bef618d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497950379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.1497950379
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1109842707
Short name T1467
Test name
Test status
Simulation time 23627584803 ps
CPU time 28.36 seconds
Started Aug 07 06:12:32 PM PDT 24
Finished Aug 07 06:13:00 PM PDT 24
Peak memory 215440 kb
Host smart-cc80b0e3-3e38-423e-806d-7b1ac6dbfdf3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109842707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.1109842707
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.2260167999
Short name T1283
Test name
Test status
Simulation time 152356638 ps
CPU time 0.85 seconds
Started Aug 07 06:12:44 PM PDT 24
Finished Aug 07 06:12:45 PM PDT 24
Peak memory 206968 kb
Host smart-946c9482-729c-4e34-958e-595b4ef26084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22601
67999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2260167999
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.3869518773
Short name T2133
Test name
Test status
Simulation time 203395487 ps
CPU time 0.94 seconds
Started Aug 07 06:12:33 PM PDT 24
Finished Aug 07 06:12:35 PM PDT 24
Peak memory 206964 kb
Host smart-dd5d6200-e4b1-4e5e-8bef-5dea77b8e544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38695
18773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.3869518773
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.3887797293
Short name T1258
Test name
Test status
Simulation time 366871453 ps
CPU time 1.37 seconds
Started Aug 07 06:12:34 PM PDT 24
Finished Aug 07 06:12:36 PM PDT 24
Peak memory 207004 kb
Host smart-aecff0b2-67e2-4e72-9928-a2970136cc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38877
97293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.3887797293
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.826201556
Short name T1446
Test name
Test status
Simulation time 422844205 ps
CPU time 1.36 seconds
Started Aug 07 06:12:32 PM PDT 24
Finished Aug 07 06:12:34 PM PDT 24
Peak memory 207008 kb
Host smart-4b520917-c250-4282-9b4b-d5b99f31b44e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=826201556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.826201556
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2268456952
Short name T2028
Test name
Test status
Simulation time 16877301247 ps
CPU time 28.11 seconds
Started Aug 07 06:12:32 PM PDT 24
Finished Aug 07 06:13:00 PM PDT 24
Peak memory 207220 kb
Host smart-7a42b010-1160-4edb-87d8-7a90e34b807a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22684
56952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2268456952
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.1269262220
Short name T951
Test name
Test status
Simulation time 3876350445 ps
CPU time 33.26 seconds
Started Aug 07 06:12:36 PM PDT 24
Finished Aug 07 06:13:09 PM PDT 24
Peak memory 207364 kb
Host smart-7e2712a9-10d9-47ac-943d-c3c460f65be0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269262220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.1269262220
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.3748368480
Short name T342
Test name
Test status
Simulation time 769330116 ps
CPU time 1.79 seconds
Started Aug 07 06:12:35 PM PDT 24
Finished Aug 07 06:12:37 PM PDT 24
Peak memory 206964 kb
Host smart-1eaaa871-0714-467f-8cb3-de7510652e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37483
68480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.3748368480
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1470378653
Short name T1497
Test name
Test status
Simulation time 138434856 ps
CPU time 0.82 seconds
Started Aug 07 06:12:34 PM PDT 24
Finished Aug 07 06:12:35 PM PDT 24
Peak memory 206964 kb
Host smart-615f5a2f-95a3-4a8e-8206-6e880ce34e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14703
78653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1470378653
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.1289475595
Short name T1012
Test name
Test status
Simulation time 38707750 ps
CPU time 0.7 seconds
Started Aug 07 06:12:42 PM PDT 24
Finished Aug 07 06:12:43 PM PDT 24
Peak memory 206924 kb
Host smart-344a78bd-355d-4ac9-86eb-6370352802b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12894
75595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1289475595
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.368348964
Short name T2728
Test name
Test status
Simulation time 852579114 ps
CPU time 2.25 seconds
Started Aug 07 06:12:35 PM PDT 24
Finished Aug 07 06:12:37 PM PDT 24
Peak memory 207196 kb
Host smart-d374d3f9-a5dd-4b48-a92e-054d960ea635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36834
8964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.368348964
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_types.2182059603
Short name T2118
Test name
Test status
Simulation time 193037092 ps
CPU time 0.97 seconds
Started Aug 07 06:12:32 PM PDT 24
Finished Aug 07 06:12:33 PM PDT 24
Peak memory 206908 kb
Host smart-562a083c-4536-46f1-9a87-ff79032d808d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2182059603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.2182059603
Directory /workspace/49.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1075982556
Short name T776
Test name
Test status
Simulation time 347400595 ps
CPU time 2.35 seconds
Started Aug 07 06:12:32 PM PDT 24
Finished Aug 07 06:12:34 PM PDT 24
Peak memory 207188 kb
Host smart-c11cb8f7-6900-4f0a-ade4-de6019973498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10759
82556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1075982556
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1985470324
Short name T530
Test name
Test status
Simulation time 169989162 ps
CPU time 0.93 seconds
Started Aug 07 06:12:42 PM PDT 24
Finished Aug 07 06:12:43 PM PDT 24
Peak memory 206968 kb
Host smart-98d821f0-ed49-40f6-bd71-c18d8bd0ba21
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1985470324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1985470324
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.493321071
Short name T2440
Test name
Test status
Simulation time 148411461 ps
CPU time 0.86 seconds
Started Aug 07 06:12:34 PM PDT 24
Finished Aug 07 06:12:35 PM PDT 24
Peak memory 206976 kb
Host smart-e73a6e7f-5371-43a1-83ff-b8626e489def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49332
1071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.493321071
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3351322785
Short name T2209
Test name
Test status
Simulation time 259888002 ps
CPU time 1.01 seconds
Started Aug 07 06:12:31 PM PDT 24
Finished Aug 07 06:12:32 PM PDT 24
Peak memory 206984 kb
Host smart-bc9840fd-308d-497b-9788-5e7635bc936f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33513
22785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3351322785
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.991170056
Short name T1285
Test name
Test status
Simulation time 3319255105 ps
CPU time 31.52 seconds
Started Aug 07 06:12:48 PM PDT 24
Finished Aug 07 06:13:20 PM PDT 24
Peak memory 223636 kb
Host smart-47dc4abf-8411-49a5-9350-fd4abaa7cd9a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=991170056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.991170056
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1448607665
Short name T1071
Test name
Test status
Simulation time 192748525 ps
CPU time 0.99 seconds
Started Aug 07 06:12:33 PM PDT 24
Finished Aug 07 06:12:35 PM PDT 24
Peak memory 207016 kb
Host smart-1e679244-9afe-47dc-93a8-18bb5d5c6bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14486
07665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1448607665
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.548312332
Short name T685
Test name
Test status
Simulation time 11062051549 ps
CPU time 14.42 seconds
Started Aug 07 06:12:42 PM PDT 24
Finished Aug 07 06:12:57 PM PDT 24
Peak memory 207284 kb
Host smart-c4b6cdf7-4517-4a49-b807-76eeb9505b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54831
2332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.548312332
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3557719072
Short name T938
Test name
Test status
Simulation time 5271090155 ps
CPU time 7.09 seconds
Started Aug 07 06:12:43 PM PDT 24
Finished Aug 07 06:12:50 PM PDT 24
Peak memory 215432 kb
Host smart-6a7b27e6-dc65-4b7b-900d-e7fb94553afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35577
19072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3557719072
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.2700160114
Short name T2591
Test name
Test status
Simulation time 4639253611 ps
CPU time 134.2 seconds
Started Aug 07 06:12:39 PM PDT 24
Finished Aug 07 06:14:54 PM PDT 24
Peak memory 223520 kb
Host smart-4ce5f127-0c81-49af-ae81-075e9542a8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27001
60114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.2700160114
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.1122170438
Short name T554
Test name
Test status
Simulation time 4173946806 ps
CPU time 41.31 seconds
Started Aug 07 06:12:32 PM PDT 24
Finished Aug 07 06:13:13 PM PDT 24
Peak memory 215512 kb
Host smart-50705a91-08e5-4e32-9a14-dddfc6f28466
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1122170438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.1122170438
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3735777588
Short name T1163
Test name
Test status
Simulation time 247185482 ps
CPU time 0.99 seconds
Started Aug 07 06:12:39 PM PDT 24
Finished Aug 07 06:12:41 PM PDT 24
Peak memory 206884 kb
Host smart-7987fcb7-fffe-4000-92a8-db70b5acc12f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3735777588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3735777588
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2184869178
Short name T3012
Test name
Test status
Simulation time 209963799 ps
CPU time 0.93 seconds
Started Aug 07 06:12:36 PM PDT 24
Finished Aug 07 06:12:37 PM PDT 24
Peak memory 207016 kb
Host smart-d865430a-80ee-4055-b714-9bee4ab7e675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21848
69178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2184869178
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.2818829309
Short name T2697
Test name
Test status
Simulation time 2796518237 ps
CPU time 76.65 seconds
Started Aug 07 06:12:34 PM PDT 24
Finished Aug 07 06:13:50 PM PDT 24
Peak memory 215496 kb
Host smart-b9f1ed55-ce39-45ee-aa14-cb26c720f3f8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2818829309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.2818829309
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1503234131
Short name T2129
Test name
Test status
Simulation time 180339894 ps
CPU time 0.89 seconds
Started Aug 07 06:12:34 PM PDT 24
Finished Aug 07 06:12:35 PM PDT 24
Peak memory 206988 kb
Host smart-5a8d45af-0af9-4c03-8013-014686f14b72
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1503234131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1503234131
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2204745140
Short name T2982
Test name
Test status
Simulation time 154423675 ps
CPU time 0.83 seconds
Started Aug 07 06:12:33 PM PDT 24
Finished Aug 07 06:12:34 PM PDT 24
Peak memory 206908 kb
Host smart-55e23060-b2ba-466c-b122-56d826305a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22047
45140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2204745140
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1520131455
Short name T2303
Test name
Test status
Simulation time 245956354 ps
CPU time 0.96 seconds
Started Aug 07 06:12:33 PM PDT 24
Finished Aug 07 06:12:35 PM PDT 24
Peak memory 206972 kb
Host smart-ac32260f-8a36-4eec-827f-a44651885d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15201
31455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1520131455
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.349910714
Short name T1538
Test name
Test status
Simulation time 214904514 ps
CPU time 1.02 seconds
Started Aug 07 06:12:39 PM PDT 24
Finished Aug 07 06:12:40 PM PDT 24
Peak memory 206884 kb
Host smart-26fb60c2-a71a-41f5-a438-3e8b8866b722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34991
0714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.349910714
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.749403161
Short name T2084
Test name
Test status
Simulation time 170664474 ps
CPU time 0.86 seconds
Started Aug 07 06:12:34 PM PDT 24
Finished Aug 07 06:12:35 PM PDT 24
Peak memory 206972 kb
Host smart-8fa970d3-1cf1-4b95-809c-3f34a9a85020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74940
3161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.749403161
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1543843608
Short name T596
Test name
Test status
Simulation time 162352618 ps
CPU time 0.86 seconds
Started Aug 07 06:12:34 PM PDT 24
Finished Aug 07 06:12:36 PM PDT 24
Peak memory 206984 kb
Host smart-d1c8d59d-b954-4763-b54e-e2b45ba3839e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15438
43608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1543843608
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3739693126
Short name T1316
Test name
Test status
Simulation time 150656758 ps
CPU time 0.84 seconds
Started Aug 07 06:12:34 PM PDT 24
Finished Aug 07 06:12:35 PM PDT 24
Peak memory 206988 kb
Host smart-9ed1753f-0edd-4245-8291-ad39a5e98e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37396
93126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3739693126
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3818578418
Short name T864
Test name
Test status
Simulation time 199509798 ps
CPU time 0.95 seconds
Started Aug 07 06:12:33 PM PDT 24
Finished Aug 07 06:12:34 PM PDT 24
Peak memory 206960 kb
Host smart-8a53dcb5-1eea-4961-ac84-4f115722b8b2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3818578418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3818578418
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2780746177
Short name T646
Test name
Test status
Simulation time 192740977 ps
CPU time 0.89 seconds
Started Aug 07 06:12:31 PM PDT 24
Finished Aug 07 06:12:32 PM PDT 24
Peak memory 206964 kb
Host smart-7085ab1d-c3cb-468f-abd9-eb9ea52b9664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27807
46177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2780746177
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3671680284
Short name T1296
Test name
Test status
Simulation time 30910302 ps
CPU time 0.69 seconds
Started Aug 07 06:12:32 PM PDT 24
Finished Aug 07 06:12:32 PM PDT 24
Peak memory 206884 kb
Host smart-ddbf9c81-4148-4e2d-8731-0e5914540627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36716
80284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3671680284
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.625915241
Short name T2006
Test name
Test status
Simulation time 17680281645 ps
CPU time 43.98 seconds
Started Aug 07 06:12:33 PM PDT 24
Finished Aug 07 06:13:17 PM PDT 24
Peak memory 215536 kb
Host smart-4b55a2c0-0b89-4c03-a0c2-f6b3d9659b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62591
5241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.625915241
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3304662773
Short name T2278
Test name
Test status
Simulation time 180109933 ps
CPU time 0.92 seconds
Started Aug 07 06:12:33 PM PDT 24
Finished Aug 07 06:12:34 PM PDT 24
Peak memory 207196 kb
Host smart-ab67b8b0-0583-4b54-94ca-e58f0e41a25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33046
62773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3304662773
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.993560760
Short name T2795
Test name
Test status
Simulation time 235989785 ps
CPU time 0.94 seconds
Started Aug 07 06:12:41 PM PDT 24
Finished Aug 07 06:12:42 PM PDT 24
Peak memory 206916 kb
Host smart-de85aaf8-3c72-4832-b695-87d7de7457b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99356
0760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.993560760
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3213588761
Short name T507
Test name
Test status
Simulation time 230205459 ps
CPU time 0.92 seconds
Started Aug 07 06:12:45 PM PDT 24
Finished Aug 07 06:12:46 PM PDT 24
Peak memory 207012 kb
Host smart-41015b10-81a4-48dc-815a-528b9c70227a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32135
88761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3213588761
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.1628164389
Short name T1995
Test name
Test status
Simulation time 179714952 ps
CPU time 0.89 seconds
Started Aug 07 06:12:41 PM PDT 24
Finished Aug 07 06:12:42 PM PDT 24
Peak memory 206904 kb
Host smart-f3ba3e4c-bb7d-4aed-a907-470480e4f019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16281
64389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.1628164389
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.782003098
Short name T2471
Test name
Test status
Simulation time 181599170 ps
CPU time 0.89 seconds
Started Aug 07 06:12:41 PM PDT 24
Finished Aug 07 06:12:42 PM PDT 24
Peak memory 206992 kb
Host smart-6b302510-ca66-4ad8-ad04-474b328bbda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78200
3098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.782003098
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_rx_full.587111909
Short name T1417
Test name
Test status
Simulation time 419146139 ps
CPU time 1.34 seconds
Started Aug 07 06:12:42 PM PDT 24
Finished Aug 07 06:12:44 PM PDT 24
Peak memory 206992 kb
Host smart-3fa4ef44-94a3-4065-804d-52bb865ccf14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58711
1909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.587111909
Directory /workspace/49.usbdev_rx_full/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1187999788
Short name T2426
Test name
Test status
Simulation time 145405346 ps
CPU time 0.89 seconds
Started Aug 07 06:12:45 PM PDT 24
Finished Aug 07 06:12:46 PM PDT 24
Peak memory 206968 kb
Host smart-da001e98-7fcf-4eda-ba8e-1011a5be7d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11879
99788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1187999788
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2258401309
Short name T1887
Test name
Test status
Simulation time 153468790 ps
CPU time 0.9 seconds
Started Aug 07 06:12:45 PM PDT 24
Finished Aug 07 06:12:46 PM PDT 24
Peak memory 207032 kb
Host smart-10b6a939-5219-4403-8df6-6a235769bc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22584
01309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2258401309
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.817488968
Short name T1083
Test name
Test status
Simulation time 243564991 ps
CPU time 1.09 seconds
Started Aug 07 06:12:42 PM PDT 24
Finished Aug 07 06:12:44 PM PDT 24
Peak memory 206992 kb
Host smart-efff4301-0805-4a82-bd15-44b8bc06bb39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81748
8968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.817488968
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.85378193
Short name T494
Test name
Test status
Simulation time 3127164532 ps
CPU time 31.54 seconds
Started Aug 07 06:12:43 PM PDT 24
Finished Aug 07 06:13:14 PM PDT 24
Peak memory 223680 kb
Host smart-f7125d4f-1a83-49c8-a11e-457565810509
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=85378193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.85378193
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.243508075
Short name T2453
Test name
Test status
Simulation time 165686615 ps
CPU time 0.89 seconds
Started Aug 07 06:12:45 PM PDT 24
Finished Aug 07 06:12:46 PM PDT 24
Peak memory 207004 kb
Host smart-11035cd5-a5ac-4fc4-817c-3d1ec85cb49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24350
8075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.243508075
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3481970530
Short name T797
Test name
Test status
Simulation time 185889028 ps
CPU time 0.88 seconds
Started Aug 07 06:12:44 PM PDT 24
Finished Aug 07 06:12:45 PM PDT 24
Peak memory 207024 kb
Host smart-1e977d78-ab16-4019-9258-57c873ac2018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34819
70530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3481970530
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.2865521424
Short name T1774
Test name
Test status
Simulation time 1124622428 ps
CPU time 2.61 seconds
Started Aug 07 06:12:41 PM PDT 24
Finished Aug 07 06:12:44 PM PDT 24
Peak memory 207128 kb
Host smart-82e43f07-7db3-4e09-89de-0df2d17e1fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28655
21424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2865521424
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2525605229
Short name T3093
Test name
Test status
Simulation time 1909896631 ps
CPU time 54.4 seconds
Started Aug 07 06:12:43 PM PDT 24
Finished Aug 07 06:13:38 PM PDT 24
Peak memory 216716 kb
Host smart-fec0ef9c-3779-4293-b025-097ac142781f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25256
05229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2525605229
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.2387025432
Short name T765
Test name
Test status
Simulation time 315505704 ps
CPU time 4.67 seconds
Started Aug 07 06:12:35 PM PDT 24
Finished Aug 07 06:12:40 PM PDT 24
Peak memory 207164 kb
Host smart-476ab370-2e8a-47f1-a67a-f1e4f3074fd0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387025432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.2387025432
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.2527382819
Short name T865
Test name
Test status
Simulation time 43285320 ps
CPU time 0.69 seconds
Started Aug 07 05:59:55 PM PDT 24
Finished Aug 07 05:59:55 PM PDT 24
Peak memory 207048 kb
Host smart-47c3d64c-0ad7-4d30-947b-09fa97aa5021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2527382819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2527382819
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.3498519510
Short name T616
Test name
Test status
Simulation time 6439034402 ps
CPU time 8.53 seconds
Started Aug 07 05:59:40 PM PDT 24
Finished Aug 07 05:59:49 PM PDT 24
Peak memory 215440 kb
Host smart-6a6e09bc-8b1b-4922-8b09-dfd58817d01f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498519510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.3498519510
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.806222994
Short name T1191
Test name
Test status
Simulation time 19586611747 ps
CPU time 21.16 seconds
Started Aug 07 05:59:39 PM PDT 24
Finished Aug 07 06:00:00 PM PDT 24
Peak memory 207304 kb
Host smart-6ef7b617-3eeb-4331-9872-8ddc17e666c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=806222994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.806222994
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1432640605
Short name T681
Test name
Test status
Simulation time 30995622972 ps
CPU time 33.85 seconds
Started Aug 07 05:59:38 PM PDT 24
Finished Aug 07 06:00:12 PM PDT 24
Peak memory 207308 kb
Host smart-6ab3448b-b538-4268-8db8-cc478e544d2b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432640605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.1432640605
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3755065783
Short name T558
Test name
Test status
Simulation time 146270279 ps
CPU time 0.82 seconds
Started Aug 07 05:59:38 PM PDT 24
Finished Aug 07 05:59:39 PM PDT 24
Peak memory 206924 kb
Host smart-b0a9a2fa-175a-4661-ac00-4b4e589dcab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37550
65783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3755065783
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.4065474525
Short name T1128
Test name
Test status
Simulation time 181604364 ps
CPU time 0.88 seconds
Started Aug 07 05:59:40 PM PDT 24
Finished Aug 07 05:59:41 PM PDT 24
Peak memory 206952 kb
Host smart-bc3b9505-5125-4b00-93c0-722f205bbf3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40654
74525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.4065474525
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.3937846143
Short name T2050
Test name
Test status
Simulation time 565205307 ps
CPU time 1.89 seconds
Started Aug 07 05:59:41 PM PDT 24
Finished Aug 07 05:59:43 PM PDT 24
Peak memory 206948 kb
Host smart-ae14de7e-adaf-4df6-823d-102ffb684db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39378
46143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.3937846143
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.624256994
Short name T806
Test name
Test status
Simulation time 925482539 ps
CPU time 2.36 seconds
Started Aug 07 05:59:40 PM PDT 24
Finished Aug 07 05:59:42 PM PDT 24
Peak memory 207092 kb
Host smart-942e78e6-6e3b-4703-bafb-03ac1361ece8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=624256994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.624256994
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3774295785
Short name T180
Test name
Test status
Simulation time 52242790414 ps
CPU time 85.75 seconds
Started Aug 07 05:59:40 PM PDT 24
Finished Aug 07 06:01:06 PM PDT 24
Peak memory 207364 kb
Host smart-968cf44d-191b-4eb8-b0cd-bd161db87db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37742
95785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3774295785
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.2062880504
Short name T3062
Test name
Test status
Simulation time 1617751211 ps
CPU time 10.71 seconds
Started Aug 07 05:59:40 PM PDT 24
Finished Aug 07 05:59:51 PM PDT 24
Peak memory 207196 kb
Host smart-a9b6f27f-fb6d-4ad2-aca8-8a73333d8f27
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062880504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.2062880504
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3487524874
Short name T909
Test name
Test status
Simulation time 894701628 ps
CPU time 2.03 seconds
Started Aug 07 05:59:38 PM PDT 24
Finished Aug 07 05:59:40 PM PDT 24
Peak memory 206984 kb
Host smart-870d78cd-0175-4842-8a71-9c8761a5cc7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34875
24874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3487524874
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2386418042
Short name T1711
Test name
Test status
Simulation time 136106792 ps
CPU time 0.8 seconds
Started Aug 07 05:59:40 PM PDT 24
Finished Aug 07 05:59:41 PM PDT 24
Peak memory 206864 kb
Host smart-79f782ae-3f14-4324-ba91-46e716db15aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23864
18042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2386418042
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.235465161
Short name T1241
Test name
Test status
Simulation time 60616757 ps
CPU time 0.76 seconds
Started Aug 07 05:59:41 PM PDT 24
Finished Aug 07 05:59:42 PM PDT 24
Peak memory 206908 kb
Host smart-d93e878f-3697-4884-b7e1-fb845cadb098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23546
5161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.235465161
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.2803386799
Short name T2559
Test name
Test status
Simulation time 948456349 ps
CPU time 2.38 seconds
Started Aug 07 05:59:44 PM PDT 24
Finished Aug 07 05:59:46 PM PDT 24
Peak memory 207228 kb
Host smart-92695bc5-a318-4ae7-988f-071f58546d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28033
86799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.2803386799
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3670251457
Short name T1554
Test name
Test status
Simulation time 251658438 ps
CPU time 1.76 seconds
Started Aug 07 05:59:45 PM PDT 24
Finished Aug 07 05:59:47 PM PDT 24
Peak memory 207136 kb
Host smart-3ef455b5-6f8d-4aef-adc4-7fa75bd031df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36702
51457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3670251457
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.1008446858
Short name T2420
Test name
Test status
Simulation time 216771262 ps
CPU time 1.03 seconds
Started Aug 07 05:59:45 PM PDT 24
Finished Aug 07 05:59:46 PM PDT 24
Peak memory 207172 kb
Host smart-f6f06e64-24dd-4a3a-9098-0fc898f76712
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1008446858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.1008446858
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.423838532
Short name T2496
Test name
Test status
Simulation time 139778466 ps
CPU time 0.82 seconds
Started Aug 07 05:59:42 PM PDT 24
Finished Aug 07 05:59:43 PM PDT 24
Peak memory 206972 kb
Host smart-937e5066-43ad-4d95-8f24-3df796d21809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42383
8532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.423838532
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3105861534
Short name T1827
Test name
Test status
Simulation time 255256262 ps
CPU time 1.03 seconds
Started Aug 07 05:59:43 PM PDT 24
Finished Aug 07 05:59:44 PM PDT 24
Peak memory 206904 kb
Host smart-64c91f6b-493d-4a84-bae4-ac48b5a27da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31058
61534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3105861534
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.620926784
Short name T2652
Test name
Test status
Simulation time 4496198075 ps
CPU time 42.86 seconds
Started Aug 07 05:59:44 PM PDT 24
Finished Aug 07 06:00:27 PM PDT 24
Peak memory 218092 kb
Host smart-97ff16de-93f2-4cee-93ac-e117a116520a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=620926784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.620926784
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.2317037318
Short name T2246
Test name
Test status
Simulation time 3342568101 ps
CPU time 38.81 seconds
Started Aug 07 05:59:48 PM PDT 24
Finished Aug 07 06:00:27 PM PDT 24
Peak memory 207252 kb
Host smart-08a13c63-c5c7-4d3f-8276-acbe9bdb0101
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2317037318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.2317037318
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1024549019
Short name T944
Test name
Test status
Simulation time 223973152 ps
CPU time 0.97 seconds
Started Aug 07 05:59:43 PM PDT 24
Finished Aug 07 05:59:44 PM PDT 24
Peak memory 206980 kb
Host smart-5edf3463-6aee-46b5-a4bd-9614925cc15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10245
49019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1024549019
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.3988414589
Short name T1354
Test name
Test status
Simulation time 24449646121 ps
CPU time 39.77 seconds
Started Aug 07 05:59:42 PM PDT 24
Finished Aug 07 06:00:22 PM PDT 24
Peak memory 207164 kb
Host smart-b9836495-b36c-42d0-9391-1d97720f64e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39884
14589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.3988414589
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.218757853
Short name T2324
Test name
Test status
Simulation time 9409908387 ps
CPU time 11.37 seconds
Started Aug 07 05:59:46 PM PDT 24
Finished Aug 07 05:59:57 PM PDT 24
Peak memory 207292 kb
Host smart-c3030fb8-514a-43e6-8c1f-5b1800b1db97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21875
7853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.218757853
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.2388829182
Short name T3054
Test name
Test status
Simulation time 3562827195 ps
CPU time 99.36 seconds
Started Aug 07 05:59:43 PM PDT 24
Finished Aug 07 06:01:22 PM PDT 24
Peak memory 217800 kb
Host smart-2d0f54cb-b300-4920-b822-0b95fc0c7b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23888
29182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.2388829182
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2026685864
Short name T1505
Test name
Test status
Simulation time 3022053671 ps
CPU time 30.64 seconds
Started Aug 07 05:59:48 PM PDT 24
Finished Aug 07 06:00:19 PM PDT 24
Peak memory 215528 kb
Host smart-2bdab9eb-fcb1-47a2-9e14-72dd3e195063
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2026685864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2026685864
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.1439641868
Short name T2
Test name
Test status
Simulation time 250863852 ps
CPU time 1 seconds
Started Aug 07 05:59:42 PM PDT 24
Finished Aug 07 05:59:44 PM PDT 24
Peak memory 206980 kb
Host smart-71cef825-6505-4065-a2e8-7657931f262e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1439641868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1439641868
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3160507725
Short name T1340
Test name
Test status
Simulation time 191993567 ps
CPU time 0.93 seconds
Started Aug 07 05:59:42 PM PDT 24
Finished Aug 07 05:59:43 PM PDT 24
Peak memory 206992 kb
Host smart-75b39d70-670b-4d87-a531-e3f9b7444d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31605
07725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3160507725
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.2293625655
Short name T2752
Test name
Test status
Simulation time 2594666621 ps
CPU time 79.49 seconds
Started Aug 07 05:59:43 PM PDT 24
Finished Aug 07 06:01:03 PM PDT 24
Peak memory 223616 kb
Host smart-154d0c88-3b0c-4b62-9f6c-34db0b786a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22936
25655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.2293625655
Directory /workspace/5.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.3801009309
Short name T1917
Test name
Test status
Simulation time 3564511109 ps
CPU time 30.99 seconds
Started Aug 07 05:59:48 PM PDT 24
Finished Aug 07 06:00:19 PM PDT 24
Peak memory 207272 kb
Host smart-b06c7521-89d8-451e-8f2c-a9df138a19ec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3801009309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3801009309
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.204679014
Short name T1709
Test name
Test status
Simulation time 2908884336 ps
CPU time 31.11 seconds
Started Aug 07 05:59:43 PM PDT 24
Finished Aug 07 06:00:14 PM PDT 24
Peak memory 223672 kb
Host smart-634f2297-7161-4aee-9827-7b4085996108
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=204679014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.204679014
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.465382183
Short name T497
Test name
Test status
Simulation time 165709320 ps
CPU time 0.89 seconds
Started Aug 07 05:59:44 PM PDT 24
Finished Aug 07 05:59:45 PM PDT 24
Peak memory 207012 kb
Host smart-3493e642-68d0-40c6-aafc-3c03e06e0c66
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=465382183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.465382183
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1803289324
Short name T889
Test name
Test status
Simulation time 150233606 ps
CPU time 0.83 seconds
Started Aug 07 05:59:42 PM PDT 24
Finished Aug 07 05:59:43 PM PDT 24
Peak memory 207020 kb
Host smart-c3cc7998-c573-45fc-b000-621e8b8ae446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18032
89324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1803289324
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3334651863
Short name T1153
Test name
Test status
Simulation time 185322129 ps
CPU time 0.96 seconds
Started Aug 07 05:59:49 PM PDT 24
Finished Aug 07 05:59:50 PM PDT 24
Peak memory 207012 kb
Host smart-74c3927e-4a5d-491a-9b16-0054e681c1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33346
51863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3334651863
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2250051955
Short name T851
Test name
Test status
Simulation time 173305865 ps
CPU time 0.97 seconds
Started Aug 07 05:59:50 PM PDT 24
Finished Aug 07 05:59:51 PM PDT 24
Peak memory 206992 kb
Host smart-800dd16d-125b-40c5-9d66-9aafa5ecc57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22500
51955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2250051955
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1711443991
Short name T684
Test name
Test status
Simulation time 186157703 ps
CPU time 0.9 seconds
Started Aug 07 05:59:49 PM PDT 24
Finished Aug 07 05:59:50 PM PDT 24
Peak memory 206996 kb
Host smart-a420e1fd-58f1-4af6-91c5-0949cb0a33d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17114
43991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1711443991
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.2467189482
Short name T3088
Test name
Test status
Simulation time 155813717 ps
CPU time 0.85 seconds
Started Aug 07 05:59:49 PM PDT 24
Finished Aug 07 05:59:50 PM PDT 24
Peak memory 206968 kb
Host smart-a52a5ff1-d55e-4117-a448-c896917f2a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24671
89482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.2467189482
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.3452673255
Short name T3085
Test name
Test status
Simulation time 222141102 ps
CPU time 0.97 seconds
Started Aug 07 05:59:48 PM PDT 24
Finished Aug 07 05:59:49 PM PDT 24
Peak memory 206980 kb
Host smart-5ce6032f-8b13-45e5-9352-7e19ec0e0628
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3452673255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.3452673255
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.967535431
Short name T1718
Test name
Test status
Simulation time 176957366 ps
CPU time 0.88 seconds
Started Aug 07 05:59:50 PM PDT 24
Finished Aug 07 05:59:50 PM PDT 24
Peak memory 206948 kb
Host smart-3a370f50-99c8-418f-b98f-c2e92a11039a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96753
5431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.967535431
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2455027851
Short name T1188
Test name
Test status
Simulation time 37432349 ps
CPU time 0.66 seconds
Started Aug 07 05:59:52 PM PDT 24
Finished Aug 07 05:59:53 PM PDT 24
Peak memory 206976 kb
Host smart-7c35870c-1dd1-46fd-ba38-c92d017d06bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24550
27851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2455027851
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3872225617
Short name T2510
Test name
Test status
Simulation time 11000763044 ps
CPU time 25.4 seconds
Started Aug 07 05:59:49 PM PDT 24
Finished Aug 07 06:00:15 PM PDT 24
Peak memory 215520 kb
Host smart-38fabb20-705e-41f4-8b76-008379f142df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38722
25617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3872225617
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2999631785
Short name T526
Test name
Test status
Simulation time 198058913 ps
CPU time 0.86 seconds
Started Aug 07 05:59:49 PM PDT 24
Finished Aug 07 05:59:50 PM PDT 24
Peak memory 207016 kb
Host smart-f75a6b56-0cc5-41cc-96f5-94758833214d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29996
31785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2999631785
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.760791679
Short name T2287
Test name
Test status
Simulation time 178106420 ps
CPU time 0.86 seconds
Started Aug 07 05:59:56 PM PDT 24
Finished Aug 07 05:59:57 PM PDT 24
Peak memory 206976 kb
Host smart-0883b92e-31b6-4a15-8b23-d0f08ffdeb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76079
1679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.760791679
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1497551576
Short name T2691
Test name
Test status
Simulation time 6307799567 ps
CPU time 27.06 seconds
Started Aug 07 05:59:49 PM PDT 24
Finished Aug 07 06:00:16 PM PDT 24
Peak memory 223616 kb
Host smart-789f2188-6dc5-4c83-81bb-06d785178598
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497551576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1497551576
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2270997585
Short name T2372
Test name
Test status
Simulation time 2952508227 ps
CPU time 59.24 seconds
Started Aug 07 05:59:50 PM PDT 24
Finished Aug 07 06:00:49 PM PDT 24
Peak memory 223656 kb
Host smart-33cafd53-e9a9-47ce-a981-f1ef8a716b24
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2270997585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2270997585
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3298933341
Short name T981
Test name
Test status
Simulation time 10571208655 ps
CPU time 76.04 seconds
Started Aug 07 05:59:50 PM PDT 24
Finished Aug 07 06:01:06 PM PDT 24
Peak memory 218116 kb
Host smart-b3792e0a-1fab-4eab-b94e-8c3339452ca9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298933341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3298933341
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3114389646
Short name T1689
Test name
Test status
Simulation time 214655840 ps
CPU time 0.94 seconds
Started Aug 07 05:59:52 PM PDT 24
Finished Aug 07 05:59:53 PM PDT 24
Peak memory 207004 kb
Host smart-85ab3bfa-09c8-493a-9abc-4d5485ca26c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31143
89646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3114389646
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.2975546349
Short name T3107
Test name
Test status
Simulation time 147225285 ps
CPU time 0.84 seconds
Started Aug 07 05:59:49 PM PDT 24
Finished Aug 07 05:59:50 PM PDT 24
Peak memory 207000 kb
Host smart-387d3bd5-3c91-400e-82ce-cff0018706a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29755
46349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.2975546349
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_resume_link_active.162904298
Short name T1061
Test name
Test status
Simulation time 20182544708 ps
CPU time 22.15 seconds
Started Aug 07 05:59:50 PM PDT 24
Finished Aug 07 06:00:12 PM PDT 24
Peak memory 207072 kb
Host smart-67f86ee5-ff2c-4561-907c-daf2ff5e4957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16290
4298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.162904298
Directory /workspace/5.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.353718241
Short name T1437
Test name
Test status
Simulation time 141065992 ps
CPU time 0.83 seconds
Started Aug 07 05:59:52 PM PDT 24
Finished Aug 07 05:59:53 PM PDT 24
Peak memory 206972 kb
Host smart-d1fddbf0-46f6-428c-95f4-d49e2d2a9b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35371
8241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.353718241
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_rx_full.3300971193
Short name T2768
Test name
Test status
Simulation time 273764046 ps
CPU time 1.13 seconds
Started Aug 07 05:59:50 PM PDT 24
Finished Aug 07 05:59:52 PM PDT 24
Peak memory 207004 kb
Host smart-41952704-b591-4657-b5d6-eb33d8d458c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33009
71193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.3300971193
Directory /workspace/5.usbdev_rx_full/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2449867110
Short name T835
Test name
Test status
Simulation time 159111685 ps
CPU time 0.84 seconds
Started Aug 07 05:59:52 PM PDT 24
Finished Aug 07 05:59:53 PM PDT 24
Peak memory 206976 kb
Host smart-9d02924c-d9cd-467c-bdeb-9bef517a1f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24498
67110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2449867110
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.4029644232
Short name T1490
Test name
Test status
Simulation time 172762973 ps
CPU time 0.85 seconds
Started Aug 07 05:59:50 PM PDT 24
Finished Aug 07 05:59:51 PM PDT 24
Peak memory 207016 kb
Host smart-aa9ac187-f1ba-4c3d-b7c6-1128e6764d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40296
44232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.4029644232
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3319485067
Short name T723
Test name
Test status
Simulation time 216106013 ps
CPU time 1.01 seconds
Started Aug 07 05:59:50 PM PDT 24
Finished Aug 07 05:59:51 PM PDT 24
Peak memory 206904 kb
Host smart-a613802c-9d3c-4fd2-baf0-6babadf0e7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33194
85067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3319485067
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.1202737188
Short name T1458
Test name
Test status
Simulation time 2382028311 ps
CPU time 22.24 seconds
Started Aug 07 05:59:52 PM PDT 24
Finished Aug 07 06:00:14 PM PDT 24
Peak memory 223880 kb
Host smart-28f55fd0-efff-4283-bd43-8d27a005e13e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1202737188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.1202737188
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2467638110
Short name T1247
Test name
Test status
Simulation time 211310846 ps
CPU time 0.91 seconds
Started Aug 07 05:59:54 PM PDT 24
Finished Aug 07 05:59:55 PM PDT 24
Peak memory 206980 kb
Host smart-c4de88ad-55ae-4121-9a48-c88753926de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24676
38110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2467638110
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.479732543
Short name T2452
Test name
Test status
Simulation time 207787897 ps
CPU time 0.92 seconds
Started Aug 07 05:59:56 PM PDT 24
Finished Aug 07 05:59:57 PM PDT 24
Peak memory 207008 kb
Host smart-89a7a633-e135-44e4-8d7b-a3256c9a6f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47973
2543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.479732543
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2818895642
Short name T2675
Test name
Test status
Simulation time 466113404 ps
CPU time 1.44 seconds
Started Aug 07 05:59:56 PM PDT 24
Finished Aug 07 05:59:58 PM PDT 24
Peak memory 206980 kb
Host smart-24c9498d-33c2-4a79-b8ab-575ed08bed5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28188
95642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2818895642
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2755442573
Short name T1223
Test name
Test status
Simulation time 2566775627 ps
CPU time 19.03 seconds
Started Aug 07 05:59:54 PM PDT 24
Finished Aug 07 06:00:13 PM PDT 24
Peak memory 215496 kb
Host smart-00c5de44-2fcd-4a3b-9f0c-7027680bd833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27554
42573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2755442573
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.2926994020
Short name T715
Test name
Test status
Simulation time 886288875 ps
CPU time 19.92 seconds
Started Aug 07 05:59:40 PM PDT 24
Finished Aug 07 06:00:00 PM PDT 24
Peak memory 207112 kb
Host smart-c0df4aa8-e112-4eca-8149-2ad7eed7b1a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926994020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.2926994020
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/50.usbdev_endpoint_types.1320734043
Short name T364
Test name
Test status
Simulation time 522134333 ps
CPU time 1.37 seconds
Started Aug 07 06:12:43 PM PDT 24
Finished Aug 07 06:12:45 PM PDT 24
Peak memory 206976 kb
Host smart-12e8e189-82c1-4e57-a99c-a1128e73ddc8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1320734043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.1320734043
Directory /workspace/50.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/51.usbdev_endpoint_types.4115202308
Short name T319
Test name
Test status
Simulation time 268210910 ps
CPU time 1.08 seconds
Started Aug 07 06:12:44 PM PDT 24
Finished Aug 07 06:12:45 PM PDT 24
Peak memory 206964 kb
Host smart-06932cba-a5b9-40f6-b083-15c6da7d8ac1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4115202308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.4115202308
Directory /workspace/51.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/52.usbdev_endpoint_types.3424290280
Short name T359
Test name
Test status
Simulation time 271480122 ps
CPU time 1.06 seconds
Started Aug 07 06:12:43 PM PDT 24
Finished Aug 07 06:12:44 PM PDT 24
Peak memory 206976 kb
Host smart-ef57d15d-d1db-4a21-a9c4-9242ef674587
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3424290280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.3424290280
Directory /workspace/52.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/53.usbdev_endpoint_types.2890146164
Short name T478
Test name
Test status
Simulation time 414942209 ps
CPU time 1.23 seconds
Started Aug 07 06:12:41 PM PDT 24
Finished Aug 07 06:12:43 PM PDT 24
Peak memory 206940 kb
Host smart-b3c253bb-78b9-4667-a690-e0cb858f7622
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2890146164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.2890146164
Directory /workspace/53.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/54.usbdev_endpoint_types.1547202481
Short name T3059
Test name
Test status
Simulation time 750207177 ps
CPU time 1.66 seconds
Started Aug 07 06:12:42 PM PDT 24
Finished Aug 07 06:12:44 PM PDT 24
Peak memory 206912 kb
Host smart-ea232d0d-3b9d-46aa-aac2-8343dfe56160
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1547202481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.1547202481
Directory /workspace/54.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/55.usbdev_endpoint_types.4040418271
Short name T410
Test name
Test status
Simulation time 443102619 ps
CPU time 1.35 seconds
Started Aug 07 06:12:41 PM PDT 24
Finished Aug 07 06:12:43 PM PDT 24
Peak memory 206952 kb
Host smart-b68cf170-0060-4ffa-a6c6-00e813595541
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4040418271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.4040418271
Directory /workspace/55.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/56.usbdev_endpoint_types.85735886
Short name T2456
Test name
Test status
Simulation time 768652473 ps
CPU time 1.77 seconds
Started Aug 07 06:12:41 PM PDT 24
Finished Aug 07 06:12:43 PM PDT 24
Peak memory 206932 kb
Host smart-0b010db1-0bd9-4c2f-a413-e660928d5e4e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=85735886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.85735886
Directory /workspace/56.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/57.usbdev_endpoint_types.2506983144
Short name T415
Test name
Test status
Simulation time 297104722 ps
CPU time 1.17 seconds
Started Aug 07 06:12:43 PM PDT 24
Finished Aug 07 06:12:44 PM PDT 24
Peak memory 206976 kb
Host smart-62f99160-7513-4a59-8467-b92d339575c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2506983144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.2506983144
Directory /workspace/57.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/59.usbdev_endpoint_types.2637713305
Short name T365
Test name
Test status
Simulation time 475565725 ps
CPU time 1.29 seconds
Started Aug 07 06:12:47 PM PDT 24
Finished Aug 07 06:12:49 PM PDT 24
Peak memory 206944 kb
Host smart-b6779399-16e7-4f20-96e8-4d56cfe01aea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2637713305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.2637713305
Directory /workspace/59.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.378691690
Short name T2335
Test name
Test status
Simulation time 65933126 ps
CPU time 0.7 seconds
Started Aug 07 06:00:08 PM PDT 24
Finished Aug 07 06:00:09 PM PDT 24
Peak memory 206968 kb
Host smart-c3ada0c1-8cc1-4a75-8f07-1a0716115b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=378691690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.378691690
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.2207586901
Short name T979
Test name
Test status
Simulation time 5013937693 ps
CPU time 6.81 seconds
Started Aug 07 05:59:57 PM PDT 24
Finished Aug 07 06:00:04 PM PDT 24
Peak memory 215460 kb
Host smart-184c1753-3351-4397-b636-9b23208c2577
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207586901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.2207586901
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3541789914
Short name T2845
Test name
Test status
Simulation time 18896938168 ps
CPU time 26.03 seconds
Started Aug 07 05:59:57 PM PDT 24
Finished Aug 07 06:00:23 PM PDT 24
Peak memory 207252 kb
Host smart-11087e3d-feb4-4288-b240-29cfba33925c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541789914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3541789914
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1741508131
Short name T3100
Test name
Test status
Simulation time 30232473126 ps
CPU time 44.46 seconds
Started Aug 07 05:59:55 PM PDT 24
Finished Aug 07 06:00:40 PM PDT 24
Peak memory 207288 kb
Host smart-87fa1212-6830-4075-8582-08d0d80d1048
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741508131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.1741508131
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.663445074
Short name T1268
Test name
Test status
Simulation time 178795127 ps
CPU time 0.96 seconds
Started Aug 07 05:59:57 PM PDT 24
Finished Aug 07 05:59:58 PM PDT 24
Peak memory 207044 kb
Host smart-a4a0f0b8-c6a7-4147-8cac-63ffdb84f3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66344
5074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.663445074
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1034052335
Short name T1574
Test name
Test status
Simulation time 145023242 ps
CPU time 0.84 seconds
Started Aug 07 05:59:55 PM PDT 24
Finished Aug 07 05:59:56 PM PDT 24
Peak memory 206984 kb
Host smart-620694bb-926e-48fc-a5fc-e254f2f02240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10340
52335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1034052335
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.2094144070
Short name T2604
Test name
Test status
Simulation time 166082114 ps
CPU time 0.93 seconds
Started Aug 07 05:59:54 PM PDT 24
Finished Aug 07 05:59:56 PM PDT 24
Peak memory 206972 kb
Host smart-6886754c-2eb5-40b9-a1c5-0d18157c9f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20941
44070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.2094144070
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.4212531367
Short name T1635
Test name
Test status
Simulation time 1020752649 ps
CPU time 2.69 seconds
Started Aug 07 05:59:55 PM PDT 24
Finished Aug 07 05:59:58 PM PDT 24
Peak memory 207192 kb
Host smart-9c9c1046-5e56-4c25-ac29-572015096bc4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4212531367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.4212531367
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.111475780
Short name T2032
Test name
Test status
Simulation time 55826375863 ps
CPU time 82.35 seconds
Started Aug 07 05:59:57 PM PDT 24
Finished Aug 07 06:01:19 PM PDT 24
Peak memory 207336 kb
Host smart-86db1c26-6cd0-4649-9ec0-93221e7bc0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11147
5780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.111475780
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.568094270
Short name T2571
Test name
Test status
Simulation time 751139266 ps
CPU time 14.98 seconds
Started Aug 07 05:59:57 PM PDT 24
Finished Aug 07 06:00:12 PM PDT 24
Peak memory 207116 kb
Host smart-e7b7a106-7cbd-4a57-8cfe-466825574a64
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568094270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.568094270
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3777344992
Short name T2838
Test name
Test status
Simulation time 742185671 ps
CPU time 1.93 seconds
Started Aug 07 05:59:56 PM PDT 24
Finished Aug 07 05:59:58 PM PDT 24
Peak memory 207008 kb
Host smart-bb66d26c-6919-414c-9db8-2f3a79beed01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37773
44992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3777344992
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3041423240
Short name T1077
Test name
Test status
Simulation time 138206505 ps
CPU time 0.91 seconds
Started Aug 07 05:59:55 PM PDT 24
Finished Aug 07 05:59:56 PM PDT 24
Peak memory 206848 kb
Host smart-efa1a89b-ba9d-43aa-a535-f643c186cad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30414
23240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3041423240
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2954855405
Short name T2485
Test name
Test status
Simulation time 38639878 ps
CPU time 0.73 seconds
Started Aug 07 05:59:58 PM PDT 24
Finished Aug 07 05:59:59 PM PDT 24
Peak memory 206980 kb
Host smart-c0f1fef0-57bb-446d-b9f0-353f1387340a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29548
55405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2954855405
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3308427253
Short name T2742
Test name
Test status
Simulation time 824518578 ps
CPU time 2.18 seconds
Started Aug 07 05:59:56 PM PDT 24
Finished Aug 07 05:59:58 PM PDT 24
Peak memory 207220 kb
Host smart-647cc574-d08e-463f-9921-2959b17dc027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33084
27253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3308427253
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_types.1218123269
Short name T457
Test name
Test status
Simulation time 847677157 ps
CPU time 1.81 seconds
Started Aug 07 05:59:54 PM PDT 24
Finished Aug 07 05:59:56 PM PDT 24
Peak memory 206944 kb
Host smart-66b6161f-c057-40fd-8ede-24e5e158c9fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1218123269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.1218123269
Directory /workspace/6.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2222656724
Short name T2726
Test name
Test status
Simulation time 193970747 ps
CPU time 1.49 seconds
Started Aug 07 05:59:53 PM PDT 24
Finished Aug 07 05:59:55 PM PDT 24
Peak memory 207184 kb
Host smart-6bd66742-afbc-432b-b38f-fcfe5bf071ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
56724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2222656724
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.4022203840
Short name T2157
Test name
Test status
Simulation time 212825323 ps
CPU time 1.09 seconds
Started Aug 07 05:59:56 PM PDT 24
Finished Aug 07 05:59:57 PM PDT 24
Peak memory 215368 kb
Host smart-d878ad34-f90c-4cb3-9707-979e6e1d0cd3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4022203840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.4022203840
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2106811114
Short name T1038
Test name
Test status
Simulation time 148251189 ps
CPU time 0.81 seconds
Started Aug 07 05:59:56 PM PDT 24
Finished Aug 07 05:59:57 PM PDT 24
Peak memory 206984 kb
Host smart-22f6ef72-8533-4b07-b0a7-69340293da27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21068
11114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2106811114
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1642866561
Short name T2068
Test name
Test status
Simulation time 237352567 ps
CPU time 1.04 seconds
Started Aug 07 05:59:55 PM PDT 24
Finished Aug 07 05:59:56 PM PDT 24
Peak memory 207012 kb
Host smart-8f2ba160-4732-4e63-bda1-64674b8ebf5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16428
66561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1642866561
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.2153163698
Short name T2788
Test name
Test status
Simulation time 2385539327 ps
CPU time 68.15 seconds
Started Aug 07 05:59:56 PM PDT 24
Finished Aug 07 06:01:04 PM PDT 24
Peak memory 217872 kb
Host smart-d35f6a2c-a048-4917-b143-b29fa5e9cd85
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2153163698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.2153163698
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.623451580
Short name T1931
Test name
Test status
Simulation time 9095966220 ps
CPU time 111.74 seconds
Started Aug 07 06:00:03 PM PDT 24
Finished Aug 07 06:01:58 PM PDT 24
Peak memory 207264 kb
Host smart-9c2f1b58-426d-427c-a725-ba836422e980
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=623451580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.623451580
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2720617755
Short name T2366
Test name
Test status
Simulation time 180151398 ps
CPU time 0.85 seconds
Started Aug 07 05:59:59 PM PDT 24
Finished Aug 07 06:00:00 PM PDT 24
Peak memory 206984 kb
Host smart-aa531e0e-2116-4153-b478-306e1efc73ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27206
17755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2720617755
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.790851073
Short name T110
Test name
Test status
Simulation time 28866049291 ps
CPU time 39.34 seconds
Started Aug 07 06:00:04 PM PDT 24
Finished Aug 07 06:00:45 PM PDT 24
Peak memory 207224 kb
Host smart-9eac7135-0a38-4c3c-b387-b40c15d6ce63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79085
1073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.790851073
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.524282509
Short name T2399
Test name
Test status
Simulation time 10431532343 ps
CPU time 13 seconds
Started Aug 07 06:00:02 PM PDT 24
Finished Aug 07 06:00:19 PM PDT 24
Peak memory 207284 kb
Host smart-c0488ea5-c469-4f97-bfaf-7df7129381e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52428
2509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.524282509
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2026556931
Short name T2218
Test name
Test status
Simulation time 4396823570 ps
CPU time 36.69 seconds
Started Aug 07 06:00:04 PM PDT 24
Finished Aug 07 06:00:43 PM PDT 24
Peak memory 217996 kb
Host smart-27842c63-1982-45a0-9138-614e3fc6bece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20265
56931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2026556931
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.1020637695
Short name T1114
Test name
Test status
Simulation time 238485408 ps
CPU time 0.97 seconds
Started Aug 07 06:00:04 PM PDT 24
Finished Aug 07 06:00:07 PM PDT 24
Peak memory 206940 kb
Host smart-6e144faf-6439-4202-9a0c-f5ed17e4259b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1020637695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.1020637695
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1474452015
Short name T3076
Test name
Test status
Simulation time 199490220 ps
CPU time 1.01 seconds
Started Aug 07 06:00:01 PM PDT 24
Finished Aug 07 06:00:02 PM PDT 24
Peak memory 206952 kb
Host smart-82072c38-bbad-49f7-bf91-737e33eb692f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14744
52015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1474452015
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.3886136983
Short name T996
Test name
Test status
Simulation time 1843832135 ps
CPU time 14.17 seconds
Started Aug 07 06:00:04 PM PDT 24
Finished Aug 07 06:00:20 PM PDT 24
Peak memory 215376 kb
Host smart-c8a1b55d-cfe5-40b3-93fa-044c4d7a898b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38861
36983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.3886136983
Directory /workspace/6.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3297432287
Short name T1407
Test name
Test status
Simulation time 2246507371 ps
CPU time 66.83 seconds
Started Aug 07 06:00:01 PM PDT 24
Finished Aug 07 06:01:08 PM PDT 24
Peak memory 215500 kb
Host smart-cc8b3841-dfce-4f33-a278-261248b3b256
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3297432287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3297432287
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.1426422199
Short name T2581
Test name
Test status
Simulation time 157138835 ps
CPU time 0.84 seconds
Started Aug 07 06:00:03 PM PDT 24
Finished Aug 07 06:00:07 PM PDT 24
Peak memory 206892 kb
Host smart-900cc196-83e7-406d-8a58-c8eb54e1321b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1426422199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.1426422199
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2798159584
Short name T17
Test name
Test status
Simulation time 152725787 ps
CPU time 0.87 seconds
Started Aug 07 06:00:03 PM PDT 24
Finished Aug 07 06:00:07 PM PDT 24
Peak memory 206960 kb
Host smart-e954ad2e-0760-4b2b-acf2-477896fec79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27981
59584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2798159584
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1816222879
Short name T2738
Test name
Test status
Simulation time 182414342 ps
CPU time 0.91 seconds
Started Aug 07 06:00:02 PM PDT 24
Finished Aug 07 06:00:07 PM PDT 24
Peak memory 206980 kb
Host smart-c9324c87-0559-4b95-9e51-8dc04a8bbee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18162
22879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1816222879
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.48275245
Short name T1502
Test name
Test status
Simulation time 157906520 ps
CPU time 0.89 seconds
Started Aug 07 06:00:01 PM PDT 24
Finished Aug 07 06:00:07 PM PDT 24
Peak memory 206908 kb
Host smart-16cc9899-95a6-4c09-8bc8-df7dca91b29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48275
245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.48275245
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.939989344
Short name T2569
Test name
Test status
Simulation time 169614725 ps
CPU time 0.86 seconds
Started Aug 07 06:00:07 PM PDT 24
Finished Aug 07 06:00:08 PM PDT 24
Peak memory 207196 kb
Host smart-acc954f5-43a2-4dae-842a-f0fe344c32b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93998
9344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.939989344
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1916122536
Short name T1450
Test name
Test status
Simulation time 145629217 ps
CPU time 0.83 seconds
Started Aug 07 06:00:02 PM PDT 24
Finished Aug 07 06:00:07 PM PDT 24
Peak memory 207004 kb
Host smart-6101287f-1109-4dbf-8097-4d608104741f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19161
22536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1916122536
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1453365813
Short name T1884
Test name
Test status
Simulation time 169238362 ps
CPU time 0.87 seconds
Started Aug 07 06:00:04 PM PDT 24
Finished Aug 07 06:00:07 PM PDT 24
Peak memory 206920 kb
Host smart-6f03f228-6484-4cbb-9643-424ac01fc036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14533
65813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1453365813
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.2329684413
Short name T1279
Test name
Test status
Simulation time 263001818 ps
CPU time 1.2 seconds
Started Aug 07 06:00:03 PM PDT 24
Finished Aug 07 06:00:07 PM PDT 24
Peak memory 206988 kb
Host smart-5028f04c-d50d-4526-9b2a-581ca6454090
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2329684413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.2329684413
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3037626589
Short name T913
Test name
Test status
Simulation time 162378553 ps
CPU time 0.8 seconds
Started Aug 07 06:00:01 PM PDT 24
Finished Aug 07 06:00:02 PM PDT 24
Peak memory 206988 kb
Host smart-e207c3e8-14f5-4a5c-a7fd-202f2a2a37b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30376
26589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3037626589
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.282937158
Short name T1107
Test name
Test status
Simulation time 37538149 ps
CPU time 0.72 seconds
Started Aug 07 06:00:07 PM PDT 24
Finished Aug 07 06:00:08 PM PDT 24
Peak memory 206704 kb
Host smart-909f53c4-c374-444b-86c8-deed428ca414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28293
7158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.282937158
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.588875614
Short name T3096
Test name
Test status
Simulation time 9681147984 ps
CPU time 24.23 seconds
Started Aug 07 05:59:59 PM PDT 24
Finished Aug 07 06:00:24 PM PDT 24
Peak memory 215560 kb
Host smart-f9b68b89-c832-4f20-afb9-f86cb77e464e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58887
5614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.588875614
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.204491987
Short name T2445
Test name
Test status
Simulation time 194126931 ps
CPU time 0.91 seconds
Started Aug 07 06:00:07 PM PDT 24
Finished Aug 07 06:00:08 PM PDT 24
Peak memory 206784 kb
Host smart-e460ae1e-5837-4373-b0ed-3988899a975d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20449
1987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.204491987
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.574133876
Short name T704
Test name
Test status
Simulation time 167109047 ps
CPU time 0.91 seconds
Started Aug 07 06:00:10 PM PDT 24
Finished Aug 07 06:00:11 PM PDT 24
Peak memory 206948 kb
Host smart-bf4a1b3d-d26f-4cfd-a885-82da8c35f3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57413
3876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.574133876
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.190778505
Short name T1023
Test name
Test status
Simulation time 6185258366 ps
CPU time 83.09 seconds
Started Aug 07 06:00:11 PM PDT 24
Finished Aug 07 06:01:35 PM PDT 24
Peak memory 218844 kb
Host smart-adc609e8-4e0c-47ff-b806-c39591c0693c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=190778505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.190778505
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.4064845826
Short name T207
Test name
Test status
Simulation time 7235663868 ps
CPU time 192.48 seconds
Started Aug 07 06:00:10 PM PDT 24
Finished Aug 07 06:03:22 PM PDT 24
Peak memory 217840 kb
Host smart-a37d1aa2-481a-4b64-b50a-558131e5a49a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4064845826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.4064845826
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1534887107
Short name T2124
Test name
Test status
Simulation time 5441170850 ps
CPU time 22.38 seconds
Started Aug 07 06:00:11 PM PDT 24
Finished Aug 07 06:00:34 PM PDT 24
Peak memory 218720 kb
Host smart-78454894-d8c8-4a27-ae98-f8f98f052b99
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534887107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1534887107
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2233570774
Short name T956
Test name
Test status
Simulation time 203052616 ps
CPU time 0.91 seconds
Started Aug 07 06:00:07 PM PDT 24
Finished Aug 07 06:00:08 PM PDT 24
Peak memory 206992 kb
Host smart-02b40e2d-51c3-4be2-810a-31a0e7bb9f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22335
70774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2233570774
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.4023184552
Short name T961
Test name
Test status
Simulation time 143845674 ps
CPU time 0.85 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:00:10 PM PDT 24
Peak memory 206908 kb
Host smart-1363ce4b-d24e-4635-ae69-045da69dd6ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40231
84552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.4023184552
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_resume_link_active.2931733002
Short name T2319
Test name
Test status
Simulation time 20167717079 ps
CPU time 23.67 seconds
Started Aug 07 06:00:10 PM PDT 24
Finished Aug 07 06:00:33 PM PDT 24
Peak memory 207072 kb
Host smart-008a5d5a-b21c-4e1b-b616-7290d0d6d823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29317
33002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.2931733002
Directory /workspace/6.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/6.usbdev_rx_full.3491266719
Short name T313
Test name
Test status
Simulation time 244413197 ps
CPU time 1.07 seconds
Started Aug 07 06:00:08 PM PDT 24
Finished Aug 07 06:00:10 PM PDT 24
Peak memory 206988 kb
Host smart-006ac4a2-a205-41b3-87b0-540471bfeeaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34912
66719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.3491266719
Directory /workspace/6.usbdev_rx_full/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1100541584
Short name T1209
Test name
Test status
Simulation time 163572554 ps
CPU time 0.85 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:00:10 PM PDT 24
Peak memory 206976 kb
Host smart-8a526c39-4540-4a66-a322-1a08835fdd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11005
41584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1100541584
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.4251388242
Short name T1690
Test name
Test status
Simulation time 164706140 ps
CPU time 0.82 seconds
Started Aug 07 06:00:07 PM PDT 24
Finished Aug 07 06:00:08 PM PDT 24
Peak memory 206980 kb
Host smart-58e8c853-1c03-4d0a-b300-c9eb8936b727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42513
88242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.4251388242
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.752958847
Short name T2039
Test name
Test status
Simulation time 231958252 ps
CPU time 1.04 seconds
Started Aug 07 06:00:08 PM PDT 24
Finished Aug 07 06:00:09 PM PDT 24
Peak memory 206948 kb
Host smart-b99e0d52-3b58-49f5-98d6-c99ef6015fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75295
8847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.752958847
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1145682319
Short name T167
Test name
Test status
Simulation time 3785046734 ps
CPU time 111.09 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:02:00 PM PDT 24
Peak memory 215476 kb
Host smart-512a1bf2-6407-4a59-9108-9dacc0c66acf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1145682319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1145682319
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.4209014480
Short name T1795
Test name
Test status
Simulation time 183258959 ps
CPU time 0.93 seconds
Started Aug 07 06:00:11 PM PDT 24
Finished Aug 07 06:00:12 PM PDT 24
Peak memory 206980 kb
Host smart-e5ad113f-8e25-49d3-8e59-484ffc991107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42090
14480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.4209014480
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.589095209
Short name T1744
Test name
Test status
Simulation time 186664034 ps
CPU time 0.91 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:00:11 PM PDT 24
Peak memory 206992 kb
Host smart-cc8e509f-bbbc-4a81-8dd5-5740f856fc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58909
5209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.589095209
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.2113197422
Short name T1358
Test name
Test status
Simulation time 436567249 ps
CPU time 1.33 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:00:11 PM PDT 24
Peak memory 206964 kb
Host smart-bb034c0e-7388-46f1-811e-fd9a90dac0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21131
97422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.2113197422
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.987155808
Short name T1522
Test name
Test status
Simulation time 2254769340 ps
CPU time 22.55 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:00:32 PM PDT 24
Peak memory 223692 kb
Host smart-91d1dea1-83ff-45e7-9f17-9e0eb0668e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98715
5808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.987155808
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.3781390196
Short name T2785
Test name
Test status
Simulation time 3873084313 ps
CPU time 36.34 seconds
Started Aug 07 05:59:54 PM PDT 24
Finished Aug 07 06:00:31 PM PDT 24
Peak memory 207292 kb
Host smart-22a5cf4f-e841-4a7d-a57f-843d87a437f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781390196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.3781390196
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/60.usbdev_endpoint_types.1583961335
Short name T363
Test name
Test status
Simulation time 479820864 ps
CPU time 1.33 seconds
Started Aug 07 06:12:44 PM PDT 24
Finished Aug 07 06:12:46 PM PDT 24
Peak memory 206976 kb
Host smart-8f520084-a8eb-47a2-ada3-7e674bd5be02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1583961335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.1583961335
Directory /workspace/60.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/61.usbdev_endpoint_types.513642702
Short name T322
Test name
Test status
Simulation time 470402152 ps
CPU time 1.37 seconds
Started Aug 07 06:12:47 PM PDT 24
Finished Aug 07 06:12:48 PM PDT 24
Peak memory 206944 kb
Host smart-c4c42280-ed0f-4ce7-8129-52d7d66c5da2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=513642702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.513642702
Directory /workspace/61.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/62.usbdev_endpoint_types.2906965514
Short name T459
Test name
Test status
Simulation time 227852240 ps
CPU time 1 seconds
Started Aug 07 06:12:42 PM PDT 24
Finished Aug 07 06:12:43 PM PDT 24
Peak memory 206984 kb
Host smart-fc41cdc3-6b29-48c3-bca6-35a40b329864
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2906965514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.2906965514
Directory /workspace/62.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/63.usbdev_endpoint_types.389571267
Short name T925
Test name
Test status
Simulation time 261128310 ps
CPU time 1.06 seconds
Started Aug 07 06:12:46 PM PDT 24
Finished Aug 07 06:12:48 PM PDT 24
Peak memory 206864 kb
Host smart-b8dc8e26-6aa1-4151-8b00-839437e4bc98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=389571267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.389571267
Directory /workspace/63.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/64.usbdev_endpoint_types.2640920637
Short name T405
Test name
Test status
Simulation time 723425608 ps
CPU time 1.61 seconds
Started Aug 07 06:12:44 PM PDT 24
Finished Aug 07 06:12:46 PM PDT 24
Peak memory 206976 kb
Host smart-7f3e0bcd-691f-4294-b2c9-ec148503e6a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2640920637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.2640920637
Directory /workspace/64.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/65.usbdev_endpoint_types.3282623004
Short name T346
Test name
Test status
Simulation time 349441795 ps
CPU time 1.06 seconds
Started Aug 07 06:12:42 PM PDT 24
Finished Aug 07 06:12:44 PM PDT 24
Peak memory 206968 kb
Host smart-1969384d-d8c9-4755-b8f4-ae87187c187a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3282623004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.3282623004
Directory /workspace/65.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/66.usbdev_endpoint_types.3238337090
Short name T473
Test name
Test status
Simulation time 157288638 ps
CPU time 0.9 seconds
Started Aug 07 06:12:53 PM PDT 24
Finished Aug 07 06:12:54 PM PDT 24
Peak memory 207004 kb
Host smart-aeb01bf6-fd7a-4e82-be25-4bbed61686d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3238337090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.3238337090
Directory /workspace/66.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/68.usbdev_endpoint_types.1309966399
Short name T427
Test name
Test status
Simulation time 258848985 ps
CPU time 0.98 seconds
Started Aug 07 06:12:52 PM PDT 24
Finished Aug 07 06:12:53 PM PDT 24
Peak memory 206972 kb
Host smart-23c43b35-2eae-416b-b0ea-94a41c91ae41
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1309966399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.1309966399
Directory /workspace/68.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/69.usbdev_endpoint_types.3176295556
Short name T1733
Test name
Test status
Simulation time 256436102 ps
CPU time 1 seconds
Started Aug 07 06:12:51 PM PDT 24
Finished Aug 07 06:12:52 PM PDT 24
Peak memory 207008 kb
Host smart-7b27ff48-4f1b-4795-a80d-eaff420fb0d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3176295556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.3176295556
Directory /workspace/69.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.378806547
Short name T2283
Test name
Test status
Simulation time 43310954 ps
CPU time 0.69 seconds
Started Aug 07 06:00:20 PM PDT 24
Finished Aug 07 06:00:21 PM PDT 24
Peak memory 207080 kb
Host smart-8af97604-5d6a-4add-9583-25a6d57e91e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=378806547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.378806547
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2979269919
Short name T2967
Test name
Test status
Simulation time 6137665098 ps
CPU time 9.89 seconds
Started Aug 07 06:00:12 PM PDT 24
Finished Aug 07 06:00:22 PM PDT 24
Peak memory 215416 kb
Host smart-a8042894-9a40-4358-bf01-afe534f47780
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979269919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.2979269919
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2534563
Short name T1312
Test name
Test status
Simulation time 19228220565 ps
CPU time 23.46 seconds
Started Aug 07 06:00:10 PM PDT 24
Finished Aug 07 06:00:33 PM PDT 24
Peak memory 207276 kb
Host smart-505fd522-e31e-40de-893d-91e1ad0b6388
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2534563
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.1563618014
Short name T3067
Test name
Test status
Simulation time 31194564252 ps
CPU time 38.69 seconds
Started Aug 07 06:00:08 PM PDT 24
Finished Aug 07 06:00:46 PM PDT 24
Peak memory 207252 kb
Host smart-71366faa-979c-4027-9c9a-66e61ec7d7c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563618014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.1563618014
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1753326379
Short name T703
Test name
Test status
Simulation time 182822472 ps
CPU time 0.92 seconds
Started Aug 07 06:00:10 PM PDT 24
Finished Aug 07 06:00:11 PM PDT 24
Peak memory 207016 kb
Host smart-f3c94b07-52d7-4115-ba1c-c1b636287140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17533
26379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1753326379
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3219146176
Short name T2429
Test name
Test status
Simulation time 139783683 ps
CPU time 0.82 seconds
Started Aug 07 06:00:10 PM PDT 24
Finished Aug 07 06:00:10 PM PDT 24
Peak memory 206876 kb
Host smart-6f89000a-54d6-4801-9080-eea877ae6fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32191
46176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3219146176
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.2171659078
Short name T910
Test name
Test status
Simulation time 405477773 ps
CPU time 1.39 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:00:11 PM PDT 24
Peak memory 206964 kb
Host smart-816e5245-c1b9-4fa9-941e-7408b76def2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21716
59078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2171659078
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.730213224
Short name T1379
Test name
Test status
Simulation time 281729454 ps
CPU time 1.06 seconds
Started Aug 07 06:00:13 PM PDT 24
Finished Aug 07 06:00:14 PM PDT 24
Peak memory 206896 kb
Host smart-8f80f883-c966-4b9d-9fab-c5d601a9466e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=730213224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.730213224
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.1910745819
Short name T1620
Test name
Test status
Simulation time 18959952226 ps
CPU time 27.15 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:00:36 PM PDT 24
Peak memory 207344 kb
Host smart-16cb3e05-36f9-47a6-84fd-485450106758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19107
45819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.1910745819
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.645684419
Short name T2702
Test name
Test status
Simulation time 274463397 ps
CPU time 4.54 seconds
Started Aug 07 06:00:10 PM PDT 24
Finished Aug 07 06:00:15 PM PDT 24
Peak memory 207212 kb
Host smart-2bda04fc-e75c-45d4-bf18-4c1c5aeb6c22
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645684419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.645684419
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.3979253704
Short name T1112
Test name
Test status
Simulation time 727529212 ps
CPU time 1.86 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:00:11 PM PDT 24
Peak memory 206936 kb
Host smart-4afe67c1-7e0a-40e8-9065-1bed17ce24bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39792
53704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3979253704
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3045885136
Short name T1202
Test name
Test status
Simulation time 182903092 ps
CPU time 0.88 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:00:10 PM PDT 24
Peak memory 206940 kb
Host smart-13a74acc-ebbe-4c4c-813a-f83b44db39cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30458
85136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3045885136
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.1706021694
Short name T19
Test name
Test status
Simulation time 30616583 ps
CPU time 0.71 seconds
Started Aug 07 06:00:19 PM PDT 24
Finished Aug 07 06:00:20 PM PDT 24
Peak memory 206972 kb
Host smart-b81dcfc9-639b-43e7-9080-a1b499eb387b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17060
21694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1706021694
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2507841029
Short name T2423
Test name
Test status
Simulation time 918517146 ps
CPU time 2.36 seconds
Started Aug 07 06:00:16 PM PDT 24
Finished Aug 07 06:00:18 PM PDT 24
Peak memory 207212 kb
Host smart-5fc480d9-02c9-4d6b-ab74-a984978eb779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25078
41029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2507841029
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_types.1965269706
Short name T398
Test name
Test status
Simulation time 763203573 ps
CPU time 1.8 seconds
Started Aug 07 06:00:18 PM PDT 24
Finished Aug 07 06:00:21 PM PDT 24
Peak memory 206900 kb
Host smart-4813e0f7-8185-4228-b0f9-038eea2fae27
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1965269706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.1965269706
Directory /workspace/7.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2452727018
Short name T1750
Test name
Test status
Simulation time 265454325 ps
CPU time 2.26 seconds
Started Aug 07 06:00:14 PM PDT 24
Finished Aug 07 06:00:17 PM PDT 24
Peak memory 207208 kb
Host smart-2f24c8b4-708f-41fb-b33a-70b7ec287d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24527
27018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2452727018
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2676628521
Short name T1074
Test name
Test status
Simulation time 182537777 ps
CPU time 1.06 seconds
Started Aug 07 06:00:15 PM PDT 24
Finished Aug 07 06:00:16 PM PDT 24
Peak memory 215340 kb
Host smart-413bcb94-f0cf-4aae-a676-506ba9ad5f5f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2676628521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2676628521
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1885188099
Short name T1236
Test name
Test status
Simulation time 150107980 ps
CPU time 0.85 seconds
Started Aug 07 06:00:15 PM PDT 24
Finished Aug 07 06:00:16 PM PDT 24
Peak memory 206872 kb
Host smart-945a1cd0-b137-4d7a-a593-ab5f3ccab7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18851
88099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1885188099
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.663386045
Short name T2339
Test name
Test status
Simulation time 189410720 ps
CPU time 0.93 seconds
Started Aug 07 06:00:16 PM PDT 24
Finished Aug 07 06:00:17 PM PDT 24
Peak memory 207016 kb
Host smart-2eb08ffb-3e45-45c5-989f-36b29dfabf3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66338
6045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.663386045
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.381807512
Short name T1213
Test name
Test status
Simulation time 5720601928 ps
CPU time 38.33 seconds
Started Aug 07 06:00:15 PM PDT 24
Finished Aug 07 06:00:53 PM PDT 24
Peak memory 207288 kb
Host smart-dfce0677-30f6-49cc-8ea9-8f98a52cbdf6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=381807512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.381807512
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2074300552
Short name T2115
Test name
Test status
Simulation time 217106430 ps
CPU time 0.94 seconds
Started Aug 07 06:00:20 PM PDT 24
Finished Aug 07 06:00:22 PM PDT 24
Peak memory 206904 kb
Host smart-468f1e25-507f-4271-9f22-d75237dd6706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20743
00552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2074300552
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2833278943
Short name T967
Test name
Test status
Simulation time 23684601252 ps
CPU time 38.65 seconds
Started Aug 07 06:00:20 PM PDT 24
Finished Aug 07 06:00:59 PM PDT 24
Peak memory 207176 kb
Host smart-78c7f084-8e65-4cc6-afe7-4eafb1ac0b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28332
78943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2833278943
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.675074699
Short name T1970
Test name
Test status
Simulation time 5008223975 ps
CPU time 6.9 seconds
Started Aug 07 06:00:14 PM PDT 24
Finished Aug 07 06:00:22 PM PDT 24
Peak memory 215492 kb
Host smart-05484cf9-30cc-4e71-bf41-9131238acd5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67507
4699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.675074699
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1927203121
Short name T318
Test name
Test status
Simulation time 3666873282 ps
CPU time 97.64 seconds
Started Aug 07 06:00:19 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 217828 kb
Host smart-26529a1a-32e7-49d6-b553-d4e72ce68770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19272
03121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1927203121
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3770874870
Short name T992
Test name
Test status
Simulation time 3979636413 ps
CPU time 40.36 seconds
Started Aug 07 06:00:15 PM PDT 24
Finished Aug 07 06:00:55 PM PDT 24
Peak memory 217008 kb
Host smart-a191182d-b053-4383-a0ba-fa34609acba3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3770874870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3770874870
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.1069651355
Short name T2357
Test name
Test status
Simulation time 295345810 ps
CPU time 1.1 seconds
Started Aug 07 06:00:14 PM PDT 24
Finished Aug 07 06:00:16 PM PDT 24
Peak memory 206896 kb
Host smart-eabe0f76-3574-45b9-879c-85f3863cbc6b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1069651355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.1069651355
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3271429956
Short name T101
Test name
Test status
Simulation time 199686511 ps
CPU time 0.92 seconds
Started Aug 07 06:00:18 PM PDT 24
Finished Aug 07 06:00:20 PM PDT 24
Peak memory 207004 kb
Host smart-63e3c686-92e7-4def-9dd4-7abe55b7a3dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32714
29956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3271429956
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.3157131757
Short name T1365
Test name
Test status
Simulation time 1791601664 ps
CPU time 13.7 seconds
Started Aug 07 06:00:21 PM PDT 24
Finished Aug 07 06:00:34 PM PDT 24
Peak memory 207168 kb
Host smart-e6cf3630-2db7-48cb-bfc8-1bcc85404d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31571
31757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.3157131757
Directory /workspace/7.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.191525594
Short name T1826
Test name
Test status
Simulation time 2420461344 ps
CPU time 74.17 seconds
Started Aug 07 06:00:15 PM PDT 24
Finished Aug 07 06:01:29 PM PDT 24
Peak memory 223660 kb
Host smart-35e38e1b-83b4-47b4-88ec-66b4557e5b32
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=191525594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.191525594
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1709070430
Short name T2672
Test name
Test status
Simulation time 2820879737 ps
CPU time 21.15 seconds
Started Aug 07 06:00:15 PM PDT 24
Finished Aug 07 06:00:37 PM PDT 24
Peak memory 207284 kb
Host smart-fc4a89a5-e103-4afb-a800-a98864812ccb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1709070430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1709070430
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.2502720139
Short name T1260
Test name
Test status
Simulation time 212972725 ps
CPU time 0.95 seconds
Started Aug 07 06:00:21 PM PDT 24
Finished Aug 07 06:00:22 PM PDT 24
Peak memory 207020 kb
Host smart-0c6685d9-6a75-4d71-8716-dd47f7c84e4f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2502720139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.2502720139
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1088789855
Short name T2021
Test name
Test status
Simulation time 141629998 ps
CPU time 0.86 seconds
Started Aug 07 06:00:19 PM PDT 24
Finished Aug 07 06:00:20 PM PDT 24
Peak memory 206940 kb
Host smart-dc7cec4d-4e27-4d52-8562-be6549d42a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10887
89855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1088789855
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1796176342
Short name T2899
Test name
Test status
Simulation time 225889290 ps
CPU time 1 seconds
Started Aug 07 06:00:16 PM PDT 24
Finished Aug 07 06:00:17 PM PDT 24
Peak memory 206980 kb
Host smart-062df0f8-c3b0-4f8a-be49-93f97d250b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17961
76342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1796176342
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.108796821
Short name T2535
Test name
Test status
Simulation time 167884795 ps
CPU time 0.87 seconds
Started Aug 07 06:00:15 PM PDT 24
Finished Aug 07 06:00:16 PM PDT 24
Peak memory 206992 kb
Host smart-0a6a8c97-82fc-4fe5-aa12-fb850c76612c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10879
6821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.108796821
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3018468872
Short name T1623
Test name
Test status
Simulation time 189534126 ps
CPU time 0.92 seconds
Started Aug 07 06:00:15 PM PDT 24
Finished Aug 07 06:00:16 PM PDT 24
Peak memory 206960 kb
Host smart-633b3ffc-c8ec-4f94-8f8c-2a6a09af74e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30184
68872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3018468872
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2364018720
Short name T2678
Test name
Test status
Simulation time 212122794 ps
CPU time 0.88 seconds
Started Aug 07 06:00:15 PM PDT 24
Finished Aug 07 06:00:16 PM PDT 24
Peak memory 206972 kb
Host smart-2d9283e9-63c6-42ae-b98d-89acc2c9679e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23640
18720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2364018720
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2870148902
Short name T1639
Test name
Test status
Simulation time 159690248 ps
CPU time 0.88 seconds
Started Aug 07 06:00:16 PM PDT 24
Finished Aug 07 06:00:17 PM PDT 24
Peak memory 207000 kb
Host smart-68f8a348-4d22-4747-80b8-7199519cbed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28701
48902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2870148902
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.4051201090
Short name T1106
Test name
Test status
Simulation time 186401803 ps
CPU time 0.93 seconds
Started Aug 07 06:00:19 PM PDT 24
Finished Aug 07 06:00:20 PM PDT 24
Peak memory 207000 kb
Host smart-f1546fc1-2669-4c04-8c80-dedb41e10a5d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4051201090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.4051201090
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2293718940
Short name T2009
Test name
Test status
Simulation time 142053703 ps
CPU time 0.82 seconds
Started Aug 07 06:00:16 PM PDT 24
Finished Aug 07 06:00:17 PM PDT 24
Peak memory 206980 kb
Host smart-d515b7e4-d3ce-445a-a1ee-ad4a6a40400f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22937
18940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2293718940
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2083417758
Short name T824
Test name
Test status
Simulation time 34138694 ps
CPU time 0.73 seconds
Started Aug 07 06:00:20 PM PDT 24
Finished Aug 07 06:00:21 PM PDT 24
Peak memory 206872 kb
Host smart-74278455-8931-47d5-8afb-07514070d8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20834
17758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2083417758
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.440847872
Short name T2253
Test name
Test status
Simulation time 12644350905 ps
CPU time 31.43 seconds
Started Aug 07 06:00:18 PM PDT 24
Finished Aug 07 06:00:50 PM PDT 24
Peak memory 215472 kb
Host smart-383b33b6-3b82-4788-bc23-f6a719cd6092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44084
7872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.440847872
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.402537674
Short name T577
Test name
Test status
Simulation time 183418634 ps
CPU time 0.94 seconds
Started Aug 07 06:00:21 PM PDT 24
Finished Aug 07 06:00:22 PM PDT 24
Peak memory 207020 kb
Host smart-2a4ade89-8844-49d9-8e5e-b21a962a6a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40253
7674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.402537674
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.253686810
Short name T1752
Test name
Test status
Simulation time 207631328 ps
CPU time 0.9 seconds
Started Aug 07 06:00:16 PM PDT 24
Finished Aug 07 06:00:17 PM PDT 24
Peak memory 206984 kb
Host smart-3aa712a0-4803-435a-a160-29fe5b0524de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25368
6810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.253686810
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3789052546
Short name T1715
Test name
Test status
Simulation time 2845682653 ps
CPU time 79.94 seconds
Started Aug 07 06:00:21 PM PDT 24
Finished Aug 07 06:01:41 PM PDT 24
Peak memory 217816 kb
Host smart-5c68ce5b-4279-4b78-bd0a-6a3eb494509c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789052546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3789052546
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1519942973
Short name T3113
Test name
Test status
Simulation time 2055770907 ps
CPU time 51.89 seconds
Started Aug 07 06:00:23 PM PDT 24
Finished Aug 07 06:01:15 PM PDT 24
Peak memory 217924 kb
Host smart-c454b749-04a7-4a75-9dbc-86b709dca34b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1519942973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1519942973
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.3023186728
Short name T922
Test name
Test status
Simulation time 5678880878 ps
CPU time 20.01 seconds
Started Aug 07 06:00:21 PM PDT 24
Finished Aug 07 06:00:41 PM PDT 24
Peak memory 223600 kb
Host smart-ab1d2559-96ef-416a-9477-efeed9e98d72
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023186728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.3023186728
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.4142906481
Short name T1833
Test name
Test status
Simulation time 199471474 ps
CPU time 0.91 seconds
Started Aug 07 06:00:19 PM PDT 24
Finished Aug 07 06:00:20 PM PDT 24
Peak memory 206904 kb
Host smart-50b54f0e-221d-4751-bf4a-d498c843f4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41429
06481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.4142906481
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2376439343
Short name T1631
Test name
Test status
Simulation time 176599633 ps
CPU time 0.89 seconds
Started Aug 07 06:00:18 PM PDT 24
Finished Aug 07 06:00:19 PM PDT 24
Peak memory 206912 kb
Host smart-c0cfd40e-0886-444c-97ce-33c902917da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23764
39343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2376439343
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_resume_link_active.1525110263
Short name T114
Test name
Test status
Simulation time 20165175565 ps
CPU time 24.05 seconds
Started Aug 07 06:00:23 PM PDT 24
Finished Aug 07 06:00:47 PM PDT 24
Peak memory 207080 kb
Host smart-d98422dc-7acd-4ff8-82cd-403da954d3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15251
10263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.1525110263
Directory /workspace/7.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.854652690
Short name T1584
Test name
Test status
Simulation time 137537482 ps
CPU time 0.84 seconds
Started Aug 07 06:00:22 PM PDT 24
Finished Aug 07 06:00:23 PM PDT 24
Peak memory 206976 kb
Host smart-fc8eb2d0-ca24-43aa-97eb-49eeb415d8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85465
2690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.854652690
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_rx_full.1241856877
Short name T46
Test name
Test status
Simulation time 374201576 ps
CPU time 1.33 seconds
Started Aug 07 06:00:23 PM PDT 24
Finished Aug 07 06:00:24 PM PDT 24
Peak memory 207008 kb
Host smart-96e596b5-409e-4b32-a672-8a11a3365b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12418
56877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.1241856877
Directory /workspace/7.usbdev_rx_full/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1069565317
Short name T1803
Test name
Test status
Simulation time 183077034 ps
CPU time 0.87 seconds
Started Aug 07 06:00:20 PM PDT 24
Finished Aug 07 06:00:21 PM PDT 24
Peak memory 207008 kb
Host smart-e750cca3-6f87-42d5-bf21-92dd4a7a9fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10695
65317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1069565317
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3988204380
Short name T2505
Test name
Test status
Simulation time 147546826 ps
CPU time 0.87 seconds
Started Aug 07 06:00:23 PM PDT 24
Finished Aug 07 06:00:24 PM PDT 24
Peak memory 207016 kb
Host smart-9c8c9eef-a285-4754-ae93-bc74a7ec682c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39882
04380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3988204380
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.759905148
Short name T2427
Test name
Test status
Simulation time 216727215 ps
CPU time 1.05 seconds
Started Aug 07 06:00:24 PM PDT 24
Finished Aug 07 06:00:25 PM PDT 24
Peak memory 206900 kb
Host smart-b4290ffd-0749-4516-b29b-d5d19c555dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75990
5148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.759905148
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3398655837
Short name T2644
Test name
Test status
Simulation time 2062488721 ps
CPU time 56.94 seconds
Started Aug 07 06:00:22 PM PDT 24
Finished Aug 07 06:01:19 PM PDT 24
Peak memory 216844 kb
Host smart-90b5a707-f880-4015-a1a8-7002b79cca16
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3398655837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3398655837
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3127859228
Short name T2258
Test name
Test status
Simulation time 171297287 ps
CPU time 0.89 seconds
Started Aug 07 06:00:23 PM PDT 24
Finished Aug 07 06:00:24 PM PDT 24
Peak memory 206948 kb
Host smart-e411dbe4-41ae-45af-89d4-49d41b501759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31278
59228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3127859228
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3828981163
Short name T840
Test name
Test status
Simulation time 183772795 ps
CPU time 0.85 seconds
Started Aug 07 06:00:21 PM PDT 24
Finished Aug 07 06:00:22 PM PDT 24
Peak memory 207016 kb
Host smart-8bd3fb99-f9be-4114-8d2a-45185bc2c5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38289
81163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3828981163
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.3481627131
Short name T1408
Test name
Test status
Simulation time 1315238789 ps
CPU time 3 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:00:30 PM PDT 24
Peak memory 207164 kb
Host smart-11855647-9e3f-4647-a7b3-4a518a45b23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34816
27131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.3481627131
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1874789184
Short name T804
Test name
Test status
Simulation time 2678027091 ps
CPU time 19.99 seconds
Started Aug 07 06:00:21 PM PDT 24
Finished Aug 07 06:00:41 PM PDT 24
Peak memory 215500 kb
Host smart-b84d8567-657d-45c4-a605-3890858bf2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18747
89184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1874789184
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.1110342531
Short name T194
Test name
Test status
Simulation time 4739336793 ps
CPU time 42.67 seconds
Started Aug 07 06:00:09 PM PDT 24
Finished Aug 07 06:00:52 PM PDT 24
Peak memory 207308 kb
Host smart-944fc8ff-4770-420c-a886-514dd9a4ab1b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110342531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.1110342531
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/70.usbdev_endpoint_types.1642531817
Short name T419
Test name
Test status
Simulation time 439528056 ps
CPU time 1.4 seconds
Started Aug 07 06:12:56 PM PDT 24
Finished Aug 07 06:12:57 PM PDT 24
Peak memory 206956 kb
Host smart-5851d176-99af-4bf9-8978-b8f4a5fb3fff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1642531817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.1642531817
Directory /workspace/70.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/71.usbdev_endpoint_types.2307889123
Short name T438
Test name
Test status
Simulation time 305370927 ps
CPU time 1.32 seconds
Started Aug 07 06:12:52 PM PDT 24
Finished Aug 07 06:12:53 PM PDT 24
Peak memory 206864 kb
Host smart-5c267ee7-57eb-4505-8d78-5f64ddaeff09
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2307889123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.2307889123
Directory /workspace/71.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/72.usbdev_endpoint_types.3750673993
Short name T3020
Test name
Test status
Simulation time 214979980 ps
CPU time 0.99 seconds
Started Aug 07 06:12:49 PM PDT 24
Finished Aug 07 06:12:50 PM PDT 24
Peak memory 206940 kb
Host smart-c3756e94-f040-4f7b-803c-7ff101ea523e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3750673993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.3750673993
Directory /workspace/72.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/73.usbdev_endpoint_types.291067241
Short name T352
Test name
Test status
Simulation time 409678381 ps
CPU time 1.24 seconds
Started Aug 07 06:12:49 PM PDT 24
Finished Aug 07 06:12:50 PM PDT 24
Peak memory 206944 kb
Host smart-36eee29c-a908-48f0-bc93-d490408c1369
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=291067241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.291067241
Directory /workspace/73.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/74.usbdev_endpoint_types.1837014275
Short name T323
Test name
Test status
Simulation time 529239779 ps
CPU time 1.58 seconds
Started Aug 07 06:12:54 PM PDT 24
Finished Aug 07 06:12:56 PM PDT 24
Peak memory 206960 kb
Host smart-04178959-ff9c-44f1-968f-6c64adae52d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1837014275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.1837014275
Directory /workspace/74.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/75.usbdev_endpoint_types.488886165
Short name T2731
Test name
Test status
Simulation time 224291528 ps
CPU time 0.99 seconds
Started Aug 07 06:12:51 PM PDT 24
Finished Aug 07 06:12:52 PM PDT 24
Peak memory 206932 kb
Host smart-0c1d5f46-40f0-4cfb-96a6-bbdd246141ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=488886165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.488886165
Directory /workspace/75.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/76.usbdev_endpoint_types.198065684
Short name T397
Test name
Test status
Simulation time 299078155 ps
CPU time 1.15 seconds
Started Aug 07 06:12:51 PM PDT 24
Finished Aug 07 06:12:53 PM PDT 24
Peak memory 206948 kb
Host smart-81696c7b-ddeb-4590-a35e-0e37394de696
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=198065684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.198065684
Directory /workspace/76.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/77.usbdev_endpoint_types.1447733606
Short name T347
Test name
Test status
Simulation time 743627840 ps
CPU time 1.78 seconds
Started Aug 07 06:12:50 PM PDT 24
Finished Aug 07 06:12:52 PM PDT 24
Peak memory 206972 kb
Host smart-e7d27aae-020f-4768-93ee-393b49fcf29d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1447733606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.1447733606
Directory /workspace/77.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/78.usbdev_endpoint_types.2960197275
Short name T2908
Test name
Test status
Simulation time 439101914 ps
CPU time 1.35 seconds
Started Aug 07 06:12:52 PM PDT 24
Finished Aug 07 06:12:54 PM PDT 24
Peak memory 206912 kb
Host smart-a87a0f2f-80e3-4877-8ac2-e74798d06307
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2960197275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.2960197275
Directory /workspace/78.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/79.usbdev_endpoint_types.1050602404
Short name T2812
Test name
Test status
Simulation time 167035099 ps
CPU time 0.87 seconds
Started Aug 07 06:12:51 PM PDT 24
Finished Aug 07 06:12:52 PM PDT 24
Peak memory 206936 kb
Host smart-b4707158-94cc-4f4a-bfe7-89e554806263
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1050602404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.1050602404
Directory /workspace/79.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1429491885
Short name T730
Test name
Test status
Simulation time 41509327 ps
CPU time 0.7 seconds
Started Aug 07 06:00:39 PM PDT 24
Finished Aug 07 06:00:39 PM PDT 24
Peak memory 207276 kb
Host smart-8e9f37e6-8628-46df-8e22-e45a9c77411e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1429491885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1429491885
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.2095752618
Short name T2951
Test name
Test status
Simulation time 5231965267 ps
CPU time 7.66 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:00:35 PM PDT 24
Peak memory 215480 kb
Host smart-9ab2d590-dc1f-4d59-9454-a1f09d46eccd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095752618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.2095752618
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3711934442
Short name T1030
Test name
Test status
Simulation time 14778468600 ps
CPU time 16.59 seconds
Started Aug 07 06:00:21 PM PDT 24
Finished Aug 07 06:00:38 PM PDT 24
Peak memory 215436 kb
Host smart-b77cacf9-d9f8-4f49-8251-9ff9a17a90af
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711934442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3711934442
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.760696654
Short name T1231
Test name
Test status
Simulation time 26201376936 ps
CPU time 30.89 seconds
Started Aug 07 06:00:24 PM PDT 24
Finished Aug 07 06:00:55 PM PDT 24
Peak memory 215448 kb
Host smart-a45637f1-c724-466c-8328-202db6c2be21
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760696654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon
_wake_resume.760696654
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1250180853
Short name T1385
Test name
Test status
Simulation time 166955824 ps
CPU time 0.89 seconds
Started Aug 07 06:00:29 PM PDT 24
Finished Aug 07 06:00:30 PM PDT 24
Peak memory 207012 kb
Host smart-9984f59f-0f20-4ee6-8126-db61b693c4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12501
80853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1250180853
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3857329641
Short name T1264
Test name
Test status
Simulation time 171348650 ps
CPU time 0.83 seconds
Started Aug 07 06:00:25 PM PDT 24
Finished Aug 07 06:00:26 PM PDT 24
Peak memory 206944 kb
Host smart-fdc69d29-690c-47ad-a8e3-a88ecc4d70c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38573
29641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3857329641
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3333989490
Short name T2394
Test name
Test status
Simulation time 319121758 ps
CPU time 1.21 seconds
Started Aug 07 06:00:28 PM PDT 24
Finished Aug 07 06:00:29 PM PDT 24
Peak memory 207012 kb
Host smart-2b4ef92c-d5f7-4707-ac59-0374437ac7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33339
89490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3333989490
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2764323853
Short name T1351
Test name
Test status
Simulation time 672697910 ps
CPU time 1.91 seconds
Started Aug 07 06:00:24 PM PDT 24
Finished Aug 07 06:00:26 PM PDT 24
Peak memory 206972 kb
Host smart-71fe910a-dd86-4302-ad9e-0d19c0b67580
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2764323853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2764323853
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.1594780189
Short name T1885
Test name
Test status
Simulation time 22730202106 ps
CPU time 34.51 seconds
Started Aug 07 06:00:29 PM PDT 24
Finished Aug 07 06:01:03 PM PDT 24
Peak memory 207352 kb
Host smart-a8226090-020e-44f6-a3a9-1c4ed4dd4201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15947
80189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1594780189
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.1160874968
Short name T193
Test name
Test status
Simulation time 4255169546 ps
CPU time 27.25 seconds
Started Aug 07 06:00:28 PM PDT 24
Finished Aug 07 06:00:56 PM PDT 24
Peak memory 207344 kb
Host smart-01388b05-877a-4776-9f24-183c703c708a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160874968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.1160874968
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.345062372
Short name T2104
Test name
Test status
Simulation time 577382040 ps
CPU time 1.6 seconds
Started Aug 07 06:00:23 PM PDT 24
Finished Aug 07 06:00:24 PM PDT 24
Peak memory 206952 kb
Host smart-0d26d503-d5aa-4306-9f36-88ca0e9e5088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34506
2372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.345062372
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.3581162832
Short name T60
Test name
Test status
Simulation time 150260548 ps
CPU time 0.85 seconds
Started Aug 07 06:00:21 PM PDT 24
Finished Aug 07 06:00:22 PM PDT 24
Peak memory 206976 kb
Host smart-99a0a995-3f1b-48b4-9fb4-795106474569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35811
62832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.3581162832
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.1601384594
Short name T1955
Test name
Test status
Simulation time 47281680 ps
CPU time 0.7 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:00:28 PM PDT 24
Peak memory 206972 kb
Host smart-d4267bd5-ce39-4997-b3c2-7544a664bbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16013
84594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1601384594
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1355875174
Short name T553
Test name
Test status
Simulation time 815013569 ps
CPU time 2.17 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:00:30 PM PDT 24
Peak memory 207156 kb
Host smart-7fc338b8-221e-4622-af84-78acd1ac3f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13558
75174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1355875174
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_types.2077522215
Short name T2924
Test name
Test status
Simulation time 696288465 ps
CPU time 1.83 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:00:29 PM PDT 24
Peak memory 206936 kb
Host smart-c54aa4ee-c20b-4ac6-a9a3-60e514f6a117
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2077522215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.2077522215
Directory /workspace/8.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2888197054
Short name T3074
Test name
Test status
Simulation time 181044950 ps
CPU time 1.93 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:00:29 PM PDT 24
Peak memory 207148 kb
Host smart-d673336f-2087-415d-ac11-c1c7c6be868c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28881
97054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2888197054
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3979141290
Short name T2400
Test name
Test status
Simulation time 203041318 ps
CPU time 1.04 seconds
Started Aug 07 06:00:31 PM PDT 24
Finished Aug 07 06:00:32 PM PDT 24
Peak memory 207124 kb
Host smart-9169f06b-be76-4577-9211-6fd6130f5024
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3979141290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3979141290
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.913756724
Short name T2628
Test name
Test status
Simulation time 150736163 ps
CPU time 0.83 seconds
Started Aug 07 06:00:28 PM PDT 24
Finished Aug 07 06:00:29 PM PDT 24
Peak memory 206984 kb
Host smart-a7a81816-ed88-480d-9e54-47fe4afbed1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91375
6724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.913756724
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.613096078
Short name T2144
Test name
Test status
Simulation time 169618603 ps
CPU time 0.98 seconds
Started Aug 07 06:00:29 PM PDT 24
Finished Aug 07 06:00:31 PM PDT 24
Peak memory 206988 kb
Host smart-e26b74a8-ef94-46f2-b084-e6f46a43b039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61309
6078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.613096078
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.606909739
Short name T2893
Test name
Test status
Simulation time 4969793161 ps
CPU time 146.83 seconds
Started Aug 07 06:00:31 PM PDT 24
Finished Aug 07 06:02:58 PM PDT 24
Peak memory 215468 kb
Host smart-e6ba7415-cdf0-44ed-874b-ef288db599b2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=606909739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.606909739
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.621774929
Short name T1582
Test name
Test status
Simulation time 5176655795 ps
CPU time 33.33 seconds
Started Aug 07 06:00:25 PM PDT 24
Finished Aug 07 06:00:59 PM PDT 24
Peak memory 207264 kb
Host smart-3d29b1f1-1163-41a2-809c-f2222bfed236
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=621774929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.621774929
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3137610241
Short name T2996
Test name
Test status
Simulation time 182868546 ps
CPU time 0.92 seconds
Started Aug 07 06:00:31 PM PDT 24
Finished Aug 07 06:00:32 PM PDT 24
Peak memory 207016 kb
Host smart-25ec6efb-74d8-4c91-b7f9-03a71a1f2999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31376
10241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3137610241
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.3067042283
Short name T38
Test name
Test status
Simulation time 32759203204 ps
CPU time 50.73 seconds
Started Aug 07 06:00:26 PM PDT 24
Finished Aug 07 06:01:17 PM PDT 24
Peak memory 207292 kb
Host smart-094e8253-d567-4e94-b5a3-d57daae15104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30670
42283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3067042283
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2687556613
Short name T2722
Test name
Test status
Simulation time 10318357085 ps
CPU time 12.66 seconds
Started Aug 07 06:00:29 PM PDT 24
Finished Aug 07 06:00:42 PM PDT 24
Peak memory 207288 kb
Host smart-5bf43bf4-851f-4ad8-8492-979dd403bfeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26875
56613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2687556613
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.2183923517
Short name T1151
Test name
Test status
Simulation time 2711467879 ps
CPU time 20.67 seconds
Started Aug 07 06:00:28 PM PDT 24
Finished Aug 07 06:00:48 PM PDT 24
Peak memory 215520 kb
Host smart-c39580d5-4111-40c5-ac13-e26d1a2e8011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21839
23517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2183923517
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.145188811
Short name T1284
Test name
Test status
Simulation time 4185059594 ps
CPU time 132.79 seconds
Started Aug 07 06:00:28 PM PDT 24
Finished Aug 07 06:02:41 PM PDT 24
Peak memory 216828 kb
Host smart-137076dd-aeba-4ca8-b9fd-0ad8a052a8b3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=145188811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.145188811
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3867762192
Short name T500
Test name
Test status
Simulation time 294308343 ps
CPU time 1.04 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:00:29 PM PDT 24
Peak memory 207016 kb
Host smart-698ff4d3-c461-4d41-b9e0-809570d4a8f0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3867762192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3867762192
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1122467557
Short name T1594
Test name
Test status
Simulation time 211670635 ps
CPU time 0.93 seconds
Started Aug 07 06:00:31 PM PDT 24
Finished Aug 07 06:00:32 PM PDT 24
Peak memory 207020 kb
Host smart-dda83847-4203-4611-9f57-2a8bab93f144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11224
67557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1122467557
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.2723476372
Short name T3024
Test name
Test status
Simulation time 2775734899 ps
CPU time 84.45 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:01:52 PM PDT 24
Peak memory 217188 kb
Host smart-5b0835f1-163d-44a8-91c2-f03faf76b488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27234
76372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.2723476372
Directory /workspace/8.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.3616044538
Short name T2274
Test name
Test status
Simulation time 4160422126 ps
CPU time 129.53 seconds
Started Aug 07 06:00:30 PM PDT 24
Finished Aug 07 06:02:39 PM PDT 24
Peak memory 215504 kb
Host smart-2f834084-c16e-4945-97df-40adbb756ad7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3616044538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.3616044538
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.929783937
Short name T2277
Test name
Test status
Simulation time 2650461284 ps
CPU time 25.78 seconds
Started Aug 07 06:00:26 PM PDT 24
Finished Aug 07 06:00:52 PM PDT 24
Peak memory 217176 kb
Host smart-d6d549de-99e6-4d0f-8533-867bebdbbab4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=929783937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.929783937
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3353048854
Short name T2102
Test name
Test status
Simulation time 150465378 ps
CPU time 0.84 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:00:28 PM PDT 24
Peak memory 207032 kb
Host smart-9b484818-0155-43da-a516-7740869f8fd6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3353048854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3353048854
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2386596545
Short name T702
Test name
Test status
Simulation time 152238758 ps
CPU time 0.86 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:00:28 PM PDT 24
Peak memory 206996 kb
Host smart-4060f57e-8a92-4223-86a8-bd53be2f8347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23865
96545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2386596545
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.4128428309
Short name T155
Test name
Test status
Simulation time 224083445 ps
CPU time 0.98 seconds
Started Aug 07 06:00:30 PM PDT 24
Finished Aug 07 06:00:31 PM PDT 24
Peak memory 206984 kb
Host smart-794507cd-e10e-4b34-b067-1cb11f4b1b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41284
28309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.4128428309
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1554921232
Short name T502
Test name
Test status
Simulation time 220105413 ps
CPU time 0.94 seconds
Started Aug 07 06:00:30 PM PDT 24
Finished Aug 07 06:00:31 PM PDT 24
Peak memory 206952 kb
Host smart-69bcad00-3d30-4a45-9bb2-b0b3f3376dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15549
21232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1554921232
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1854796963
Short name T828
Test name
Test status
Simulation time 197481202 ps
CPU time 0.97 seconds
Started Aug 07 06:00:30 PM PDT 24
Finished Aug 07 06:00:31 PM PDT 24
Peak memory 206912 kb
Host smart-84a9cd31-e8b4-4932-9300-ec9d4d429aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547
96963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1854796963
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2354494103
Short name T2487
Test name
Test status
Simulation time 164122422 ps
CPU time 0.84 seconds
Started Aug 07 06:00:31 PM PDT 24
Finished Aug 07 06:00:32 PM PDT 24
Peak memory 206980 kb
Host smart-09b422d5-ec9c-4ad3-8aa3-f61051332d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23544
94103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2354494103
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.202283596
Short name T2192
Test name
Test status
Simulation time 159236605 ps
CPU time 0.92 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:00:28 PM PDT 24
Peak memory 206988 kb
Host smart-3f4e8cb3-dc64-4b73-bea8-440afbf8e469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20228
3596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.202283596
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.737767624
Short name T2681
Test name
Test status
Simulation time 237680890 ps
CPU time 0.99 seconds
Started Aug 07 06:00:27 PM PDT 24
Finished Aug 07 06:00:28 PM PDT 24
Peak memory 206976 kb
Host smart-e74032a6-e21c-4640-86ae-2c5cac0695fc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=737767624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.737767624
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.4063306143
Short name T1779
Test name
Test status
Simulation time 155386804 ps
CPU time 0.84 seconds
Started Aug 07 06:00:31 PM PDT 24
Finished Aug 07 06:00:32 PM PDT 24
Peak memory 206988 kb
Host smart-75a097d5-c0d3-48d1-9b84-b2f34101c28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40633
06143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.4063306143
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.539163144
Short name T2716
Test name
Test status
Simulation time 32989089 ps
CPU time 0.69 seconds
Started Aug 07 06:00:30 PM PDT 24
Finished Aug 07 06:00:31 PM PDT 24
Peak memory 206908 kb
Host smart-fba53d64-6421-4307-bccf-eca31f16920c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53916
3144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.539163144
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3588728745
Short name T1386
Test name
Test status
Simulation time 11356465075 ps
CPU time 27.72 seconds
Started Aug 07 06:00:28 PM PDT 24
Finished Aug 07 06:00:56 PM PDT 24
Peak memory 219616 kb
Host smart-220fa03a-be71-49d3-92c6-7be91ea3b05d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35887
28745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3588728745
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.199917421
Short name T39
Test name
Test status
Simulation time 177599121 ps
CPU time 0.91 seconds
Started Aug 07 06:00:29 PM PDT 24
Finished Aug 07 06:00:30 PM PDT 24
Peak memory 206980 kb
Host smart-7382ad95-bec6-473d-be44-242bbc9aeea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19991
7421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.199917421
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.921752125
Short name T1512
Test name
Test status
Simulation time 188477306 ps
CPU time 0.92 seconds
Started Aug 07 06:00:29 PM PDT 24
Finished Aug 07 06:00:30 PM PDT 24
Peak memory 206932 kb
Host smart-17b00e90-bbe3-49ab-bb5b-d7de4ce7cb85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92175
2125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.921752125
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.4175124733
Short name T1472
Test name
Test status
Simulation time 10984709834 ps
CPU time 58.83 seconds
Started Aug 07 06:00:35 PM PDT 24
Finished Aug 07 06:01:34 PM PDT 24
Peak memory 215496 kb
Host smart-ee64e73d-84d7-4dcd-924b-7803ba41120c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175124733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.4175124733
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.940592455
Short name T1837
Test name
Test status
Simulation time 6552918096 ps
CPU time 59.52 seconds
Started Aug 07 06:00:37 PM PDT 24
Finished Aug 07 06:01:37 PM PDT 24
Peak memory 217956 kb
Host smart-83e9e2c0-bdcc-405e-92b0-c2679f71eb90
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=940592455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.940592455
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.2546474129
Short name T2480
Test name
Test status
Simulation time 7491446359 ps
CPU time 114.66 seconds
Started Aug 07 06:00:35 PM PDT 24
Finished Aug 07 06:02:30 PM PDT 24
Peak memory 218916 kb
Host smart-5b421aa1-3e35-4c92-b9eb-99357dc83d63
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546474129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2546474129
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2226125959
Short name T506
Test name
Test status
Simulation time 223190805 ps
CPU time 0.96 seconds
Started Aug 07 06:00:28 PM PDT 24
Finished Aug 07 06:00:29 PM PDT 24
Peak memory 206988 kb
Host smart-0bc7cb6e-b7d7-418e-8e1c-c1a262dabace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22261
25959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2226125959
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.500718457
Short name T2459
Test name
Test status
Simulation time 212832348 ps
CPU time 0.91 seconds
Started Aug 07 06:00:28 PM PDT 24
Finished Aug 07 06:00:29 PM PDT 24
Peak memory 206984 kb
Host smart-4db6ba36-f8c3-4d27-a601-7be9322f8225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50071
8457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.500718457
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_resume_link_active.1356459395
Short name T1242
Test name
Test status
Simulation time 20151042128 ps
CPU time 24.24 seconds
Started Aug 07 06:00:35 PM PDT 24
Finished Aug 07 06:00:59 PM PDT 24
Peak memory 207104 kb
Host smart-135f4513-7c39-421e-abe2-7c5506291b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13564
59395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.1356459395
Directory /workspace/8.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.172015388
Short name T490
Test name
Test status
Simulation time 194806334 ps
CPU time 0.89 seconds
Started Aug 07 06:00:36 PM PDT 24
Finished Aug 07 06:00:37 PM PDT 24
Peak memory 206984 kb
Host smart-99053264-b070-4b9b-848e-1b3e7c536831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17201
5388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.172015388
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_rx_full.949726868
Short name T1313
Test name
Test status
Simulation time 285947964 ps
CPU time 1.14 seconds
Started Aug 07 06:00:36 PM PDT 24
Finished Aug 07 06:00:38 PM PDT 24
Peak memory 206968 kb
Host smart-4fe7dc07-9995-41dd-9fbb-c83b088fc5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94972
6868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.949726868
Directory /workspace/8.usbdev_rx_full/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2270689567
Short name T2185
Test name
Test status
Simulation time 162346295 ps
CPU time 0.86 seconds
Started Aug 07 06:00:38 PM PDT 24
Finished Aug 07 06:00:39 PM PDT 24
Peak memory 206848 kb
Host smart-d9858859-8e83-4f7a-a80d-6416eea61d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22706
89567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2270689567
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2782522506
Short name T2594
Test name
Test status
Simulation time 161497246 ps
CPU time 0.88 seconds
Started Aug 07 06:00:34 PM PDT 24
Finished Aug 07 06:00:35 PM PDT 24
Peak memory 207016 kb
Host smart-6dd25b73-1232-41e6-89cc-fa2a9fa89061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27825
22506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2782522506
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.405942867
Short name T1857
Test name
Test status
Simulation time 218415049 ps
CPU time 0.95 seconds
Started Aug 07 06:00:34 PM PDT 24
Finished Aug 07 06:00:35 PM PDT 24
Peak memory 206972 kb
Host smart-6f3a4ba2-bc9e-41a1-b80f-27dcb03bb639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40594
2867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.405942867
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.759869086
Short name T1219
Test name
Test status
Simulation time 2538896660 ps
CPU time 19.22 seconds
Started Aug 07 06:00:42 PM PDT 24
Finished Aug 07 06:01:01 PM PDT 24
Peak memory 215492 kb
Host smart-a385caad-6a44-4d86-bef2-471624613af0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=759869086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.759869086
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1472710662
Short name T2347
Test name
Test status
Simulation time 189606415 ps
CPU time 0.91 seconds
Started Aug 07 06:00:36 PM PDT 24
Finished Aug 07 06:00:37 PM PDT 24
Peak memory 207016 kb
Host smart-eb3b1bf3-5c8a-4252-81c6-42b43d3743d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14727
10662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1472710662
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2578317041
Short name T1477
Test name
Test status
Simulation time 178691605 ps
CPU time 0.88 seconds
Started Aug 07 06:00:36 PM PDT 24
Finished Aug 07 06:00:37 PM PDT 24
Peak memory 207012 kb
Host smart-c9027ccd-cddf-4e51-95f7-b9839e1e0f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25783
17041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2578317041
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2191608101
Short name T1288
Test name
Test status
Simulation time 490730504 ps
CPU time 1.41 seconds
Started Aug 07 06:00:35 PM PDT 24
Finished Aug 07 06:00:37 PM PDT 24
Peak memory 206876 kb
Host smart-02bbd405-d9a0-485a-84c6-558a4262d451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21916
08101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2191608101
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.698433248
Short name T1078
Test name
Test status
Simulation time 1797901396 ps
CPU time 13.41 seconds
Started Aug 07 06:00:37 PM PDT 24
Finished Aug 07 06:00:51 PM PDT 24
Peak memory 223520 kb
Host smart-1c113779-7f50-46d9-a467-5d7436dbb226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69843
3248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.698433248
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.3440101619
Short name T3016
Test name
Test status
Simulation time 6359395666 ps
CPU time 40.91 seconds
Started Aug 07 06:00:24 PM PDT 24
Finished Aug 07 06:01:05 PM PDT 24
Peak memory 207244 kb
Host smart-a37c28b6-cddb-42f8-8208-a49d0cb05938
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440101619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.3440101619
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/80.usbdev_endpoint_types.3303686688
Short name T2091
Test name
Test status
Simulation time 154903846 ps
CPU time 0.9 seconds
Started Aug 07 06:12:52 PM PDT 24
Finished Aug 07 06:12:53 PM PDT 24
Peak memory 206944 kb
Host smart-9f460185-9013-4bd0-8ea8-8fd8efacfd0a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3303686688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.3303686688
Directory /workspace/80.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/83.usbdev_endpoint_types.974630978
Short name T2818
Test name
Test status
Simulation time 573379544 ps
CPU time 1.51 seconds
Started Aug 07 06:12:50 PM PDT 24
Finished Aug 07 06:12:52 PM PDT 24
Peak memory 206976 kb
Host smart-ea05ad46-42ea-40a6-8ade-fdd1542c3907
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=974630978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.974630978
Directory /workspace/83.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/84.usbdev_endpoint_types.423189932
Short name T391
Test name
Test status
Simulation time 404113014 ps
CPU time 1.28 seconds
Started Aug 07 06:12:54 PM PDT 24
Finished Aug 07 06:12:55 PM PDT 24
Peak memory 206956 kb
Host smart-19c2d580-24c7-4f3c-af3a-16ef95c3585e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=423189932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.423189932
Directory /workspace/84.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/86.usbdev_endpoint_types.1515928222
Short name T3071
Test name
Test status
Simulation time 279935755 ps
CPU time 1.04 seconds
Started Aug 07 06:12:54 PM PDT 24
Finished Aug 07 06:12:55 PM PDT 24
Peak memory 206956 kb
Host smart-d7eb478b-86f7-480c-9429-f064f5aa76b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1515928222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.1515928222
Directory /workspace/86.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/88.usbdev_endpoint_types.203628796
Short name T375
Test name
Test status
Simulation time 584778950 ps
CPU time 1.58 seconds
Started Aug 07 06:12:51 PM PDT 24
Finished Aug 07 06:12:53 PM PDT 24
Peak memory 206960 kb
Host smart-c1a9eb67-2de1-4f89-84c5-99d3e844a4bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=203628796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.203628796
Directory /workspace/88.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/89.usbdev_endpoint_types.1053606857
Short name T407
Test name
Test status
Simulation time 578147497 ps
CPU time 1.58 seconds
Started Aug 07 06:12:57 PM PDT 24
Finished Aug 07 06:12:58 PM PDT 24
Peak memory 206956 kb
Host smart-1bc548b8-4ad1-48ab-a8e3-d423f77f1250
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1053606857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.1053606857
Directory /workspace/89.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.1000643777
Short name T1032
Test name
Test status
Simulation time 48972595 ps
CPU time 0.72 seconds
Started Aug 07 06:00:53 PM PDT 24
Finished Aug 07 06:00:54 PM PDT 24
Peak memory 207280 kb
Host smart-4d71a98c-c8c3-410c-ade2-33e9730f664d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1000643777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1000643777
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.674940100
Short name T2880
Test name
Test status
Simulation time 11718006427 ps
CPU time 14.86 seconds
Started Aug 07 06:00:36 PM PDT 24
Finished Aug 07 06:00:51 PM PDT 24
Peak memory 207264 kb
Host smart-62d7f7d4-6fc7-4f15-8070-dea89b86fff9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674940100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon
_wake_disconnect.674940100
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.2598294126
Short name T11
Test name
Test status
Simulation time 19386989582 ps
CPU time 21.5 seconds
Started Aug 07 06:00:35 PM PDT 24
Finished Aug 07 06:00:57 PM PDT 24
Peak memory 207284 kb
Host smart-093fa8b7-c3e9-473e-88aa-2ed35ef7d6fe
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598294126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.2598294126
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.3765715498
Short name T118
Test name
Test status
Simulation time 23767593872 ps
CPU time 25.66 seconds
Started Aug 07 06:00:38 PM PDT 24
Finished Aug 07 06:01:04 PM PDT 24
Peak memory 215468 kb
Host smart-b3f9cc79-3885-4ce9-bd6c-93fdceeb1cc5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765715498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.3765715498
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3875106746
Short name T1725
Test name
Test status
Simulation time 157227995 ps
CPU time 0.83 seconds
Started Aug 07 06:00:34 PM PDT 24
Finished Aug 07 06:00:35 PM PDT 24
Peak memory 206940 kb
Host smart-457440b6-aeb7-4832-8643-81c876e1cc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38751
06746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3875106746
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.2801691823
Short name T2684
Test name
Test status
Simulation time 149061129 ps
CPU time 0.85 seconds
Started Aug 07 06:00:37 PM PDT 24
Finished Aug 07 06:00:38 PM PDT 24
Peak memory 207012 kb
Host smart-a0c6c250-9719-49ed-ba91-608cb174733e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28016
91823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.2801691823
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.3044660113
Short name T1277
Test name
Test status
Simulation time 374785681 ps
CPU time 1.54 seconds
Started Aug 07 06:00:42 PM PDT 24
Finished Aug 07 06:00:44 PM PDT 24
Peak memory 206996 kb
Host smart-5533c45e-a17d-40d2-ab59-96444b06660d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30446
60113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.3044660113
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3042694676
Short name T2419
Test name
Test status
Simulation time 1158775851 ps
CPU time 2.76 seconds
Started Aug 07 06:00:38 PM PDT 24
Finished Aug 07 06:00:41 PM PDT 24
Peak memory 207196 kb
Host smart-a2159d3b-6064-4ac8-8fad-c94a4c2cc1bb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3042694676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3042694676
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.2832797594
Short name T186
Test name
Test status
Simulation time 48839151245 ps
CPU time 72.73 seconds
Started Aug 07 06:00:35 PM PDT 24
Finished Aug 07 06:01:48 PM PDT 24
Peak memory 207136 kb
Host smart-6b1f527d-4624-4a1b-8829-017cbf1183a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28327
97594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.2832797594
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.3831938549
Short name T2883
Test name
Test status
Simulation time 2461721501 ps
CPU time 19.91 seconds
Started Aug 07 06:00:38 PM PDT 24
Finished Aug 07 06:00:58 PM PDT 24
Peak memory 207320 kb
Host smart-4d94d615-b508-443d-9076-64bfca4b5ab4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831938549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.3831938549
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.2473235560
Short name T2193
Test name
Test status
Simulation time 787682066 ps
CPU time 2.01 seconds
Started Aug 07 06:00:37 PM PDT 24
Finished Aug 07 06:00:39 PM PDT 24
Peak memory 206976 kb
Host smart-9d192c47-b947-426e-9858-d9b290c5559c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24732
35560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.2473235560
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1519964801
Short name T1798
Test name
Test status
Simulation time 144279338 ps
CPU time 0.84 seconds
Started Aug 07 06:00:37 PM PDT 24
Finished Aug 07 06:00:38 PM PDT 24
Peak memory 207000 kb
Host smart-44f6cdaf-6a7a-46a1-97dd-b4d791583144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15199
64801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1519964801
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2320074119
Short name T550
Test name
Test status
Simulation time 96342933 ps
CPU time 0.77 seconds
Started Aug 07 06:00:35 PM PDT 24
Finished Aug 07 06:00:36 PM PDT 24
Peak memory 206932 kb
Host smart-c5245c9b-b394-4bdf-a277-0505a847592c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23200
74119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2320074119
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.333229353
Short name T1196
Test name
Test status
Simulation time 706926555 ps
CPU time 2.04 seconds
Started Aug 07 06:00:35 PM PDT 24
Finished Aug 07 06:00:37 PM PDT 24
Peak memory 207228 kb
Host smart-dab1931f-5ae0-4c53-adc8-59dd0f95804e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33322
9353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.333229353
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_types.3284925477
Short name T345
Test name
Test status
Simulation time 657022900 ps
CPU time 1.55 seconds
Started Aug 07 06:00:42 PM PDT 24
Finished Aug 07 06:00:44 PM PDT 24
Peak memory 206972 kb
Host smart-f07c3611-8b14-434e-a43b-f7848f5ed138
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3284925477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.3284925477
Directory /workspace/9.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3522685992
Short name T2757
Test name
Test status
Simulation time 266714746 ps
CPU time 1.86 seconds
Started Aug 07 06:00:44 PM PDT 24
Finished Aug 07 06:00:46 PM PDT 24
Peak memory 207008 kb
Host smart-652579f7-efa9-4fa7-998d-ce8b0f5f8786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35226
85992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3522685992
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2169628163
Short name T1769
Test name
Test status
Simulation time 252447731 ps
CPU time 1.09 seconds
Started Aug 07 06:00:43 PM PDT 24
Finished Aug 07 06:00:44 PM PDT 24
Peak memory 207204 kb
Host smart-da59286d-4aa9-4272-8f3e-b2faeec8e745
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2169628163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2169628163
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1206725710
Short name T1657
Test name
Test status
Simulation time 150213626 ps
CPU time 0.84 seconds
Started Aug 07 06:00:43 PM PDT 24
Finished Aug 07 06:00:44 PM PDT 24
Peak memory 206916 kb
Host smart-466daa5c-01f6-49dd-a584-5441fc61b076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12067
25710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1206725710
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3947005703
Short name T1568
Test name
Test status
Simulation time 254326864 ps
CPU time 0.97 seconds
Started Aug 07 06:00:47 PM PDT 24
Finished Aug 07 06:00:48 PM PDT 24
Peak memory 206444 kb
Host smart-32030c23-06ac-4b14-b2d6-25ba0300539a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39470
05703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3947005703
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.1721156746
Short name T1991
Test name
Test status
Simulation time 3794741773 ps
CPU time 28.8 seconds
Started Aug 07 06:00:42 PM PDT 24
Finished Aug 07 06:01:11 PM PDT 24
Peak memory 223668 kb
Host smart-335b114d-63b1-4570-8236-79590468188b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1721156746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.1721156746
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2321879426
Short name T2860
Test name
Test status
Simulation time 205773677 ps
CPU time 0.9 seconds
Started Aug 07 06:00:42 PM PDT 24
Finished Aug 07 06:00:43 PM PDT 24
Peak memory 207000 kb
Host smart-c9310471-f0ac-4ecd-a674-c7e8e65ee499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23218
79426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2321879426
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1977236432
Short name T2695
Test name
Test status
Simulation time 31937689395 ps
CPU time 44.34 seconds
Started Aug 07 06:00:41 PM PDT 24
Finished Aug 07 06:01:26 PM PDT 24
Peak memory 207212 kb
Host smart-ac14ef0a-7831-427f-a9db-c4f5fddd5713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19772
36432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1977236432
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.4052078697
Short name T2153
Test name
Test status
Simulation time 4640023274 ps
CPU time 7 seconds
Started Aug 07 06:00:41 PM PDT 24
Finished Aug 07 06:00:49 PM PDT 24
Peak memory 215580 kb
Host smart-f3b930e6-e34e-4938-8c45-252507a47c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40520
78697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.4052078697
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.1030401235
Short name T963
Test name
Test status
Simulation time 3795268459 ps
CPU time 113.1 seconds
Started Aug 07 06:00:41 PM PDT 24
Finished Aug 07 06:02:35 PM PDT 24
Peak memory 223700 kb
Host smart-f91e89c8-133b-4209-a586-84bb97d93b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10304
01235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1030401235
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.456848759
Short name T805
Test name
Test status
Simulation time 1779844693 ps
CPU time 47.19 seconds
Started Aug 07 06:00:47 PM PDT 24
Finished Aug 07 06:01:35 PM PDT 24
Peak memory 216312 kb
Host smart-28ca69b2-a8c5-44d3-a13b-1048782307da
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=456848759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.456848759
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2800079379
Short name T2493
Test name
Test status
Simulation time 320322725 ps
CPU time 1.06 seconds
Started Aug 07 06:00:45 PM PDT 24
Finished Aug 07 06:00:46 PM PDT 24
Peak memory 206984 kb
Host smart-4a79054a-127f-4905-96ba-5059933ae97c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2800079379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2800079379
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1714164116
Short name T2878
Test name
Test status
Simulation time 195160150 ps
CPU time 0.92 seconds
Started Aug 07 06:00:41 PM PDT 24
Finished Aug 07 06:00:42 PM PDT 24
Peak memory 206976 kb
Host smart-1cd8ea98-b87b-4e84-b8bc-c711cc8ed654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17141
64116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1714164116
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.3649809959
Short name T675
Test name
Test status
Simulation time 2366835664 ps
CPU time 69.32 seconds
Started Aug 07 06:00:44 PM PDT 24
Finished Aug 07 06:01:53 PM PDT 24
Peak memory 217256 kb
Host smart-3cfe0e35-6175-4d4a-836f-da39079dc3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36498
09959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.3649809959
Directory /workspace/9.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.1848846674
Short name T1545
Test name
Test status
Simulation time 3182061883 ps
CPU time 39.23 seconds
Started Aug 07 06:00:41 PM PDT 24
Finished Aug 07 06:01:20 PM PDT 24
Peak memory 223684 kb
Host smart-04bb8f54-4b1b-4c64-95a3-a66f0159393a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1848846674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.1848846674
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3790663846
Short name T1596
Test name
Test status
Simulation time 2698279977 ps
CPU time 24.73 seconds
Started Aug 07 06:00:43 PM PDT 24
Finished Aug 07 06:01:08 PM PDT 24
Peak memory 223820 kb
Host smart-231326ec-3cd8-4e23-8250-05ab522a3047
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3790663846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3790663846
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.4195941376
Short name T1293
Test name
Test status
Simulation time 163919178 ps
CPU time 0.95 seconds
Started Aug 07 06:00:44 PM PDT 24
Finished Aug 07 06:00:45 PM PDT 24
Peak memory 206984 kb
Host smart-07bb6d3e-ecd7-4ef5-a91e-9a273533ef5a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4195941376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.4195941376
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2961962273
Short name T1206
Test name
Test status
Simulation time 147939574 ps
CPU time 0.81 seconds
Started Aug 07 06:00:42 PM PDT 24
Finished Aug 07 06:00:43 PM PDT 24
Peak memory 207020 kb
Host smart-60312c2e-55d7-4ab1-aaf4-4cb0bfd0d9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29619
62273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2961962273
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1301190528
Short name T1200
Test name
Test status
Simulation time 203904893 ps
CPU time 0.96 seconds
Started Aug 07 06:00:46 PM PDT 24
Finished Aug 07 06:00:47 PM PDT 24
Peak memory 207004 kb
Host smart-85e15e22-8588-4366-8447-1abbd82b942c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13011
90528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1301190528
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3008855321
Short name T1764
Test name
Test status
Simulation time 208229282 ps
CPU time 1.03 seconds
Started Aug 07 06:00:47 PM PDT 24
Finished Aug 07 06:00:48 PM PDT 24
Peak memory 206444 kb
Host smart-350ea257-7df0-4d4f-96ab-fe19678f7876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30088
55321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3008855321
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1702622968
Short name T2252
Test name
Test status
Simulation time 235227379 ps
CPU time 1.01 seconds
Started Aug 07 06:00:48 PM PDT 24
Finished Aug 07 06:00:49 PM PDT 24
Peak memory 206444 kb
Host smart-6033c0f6-055a-491f-93c0-4ced26b92fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17026
22968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1702622968
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1596726454
Short name T2744
Test name
Test status
Simulation time 188134168 ps
CPU time 0.91 seconds
Started Aug 07 06:00:50 PM PDT 24
Finished Aug 07 06:00:52 PM PDT 24
Peak memory 206900 kb
Host smart-e0ab7bfb-e305-43de-8267-c6b042674607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15967
26454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1596726454
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3733042169
Short name T1775
Test name
Test status
Simulation time 155450500 ps
CPU time 0.86 seconds
Started Aug 07 06:00:48 PM PDT 24
Finished Aug 07 06:00:49 PM PDT 24
Peak memory 207012 kb
Host smart-626a1176-4453-4938-9443-be99eb75edbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37330
42169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3733042169
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.799511887
Short name T2906
Test name
Test status
Simulation time 260241392 ps
CPU time 1.08 seconds
Started Aug 07 06:00:48 PM PDT 24
Finished Aug 07 06:00:49 PM PDT 24
Peak memory 206988 kb
Host smart-38886866-d1e0-473f-bc44-b6cea33df991
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=799511887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.799511887
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2569355292
Short name T3026
Test name
Test status
Simulation time 190958761 ps
CPU time 0.91 seconds
Started Aug 07 06:00:49 PM PDT 24
Finished Aug 07 06:00:50 PM PDT 24
Peak memory 206864 kb
Host smart-0aba7d66-7f63-4fec-8344-739395621901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25693
55292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2569355292
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1445406163
Short name T35
Test name
Test status
Simulation time 42358346 ps
CPU time 0.7 seconds
Started Aug 07 06:00:53 PM PDT 24
Finished Aug 07 06:00:54 PM PDT 24
Peak memory 207184 kb
Host smart-164417ae-205f-4626-a6c1-dde4ade86df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14454
06163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1445406163
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1398027655
Short name T300
Test name
Test status
Simulation time 8170991490 ps
CPU time 21.28 seconds
Started Aug 07 06:00:47 PM PDT 24
Finished Aug 07 06:01:09 PM PDT 24
Peak memory 215416 kb
Host smart-b2fed41b-a5be-41a6-b7c2-3f0a4da291e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13980
27655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1398027655
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3921045992
Short name T41
Test name
Test status
Simulation time 187612676 ps
CPU time 0.91 seconds
Started Aug 07 06:00:47 PM PDT 24
Finished Aug 07 06:00:48 PM PDT 24
Peak memory 206996 kb
Host smart-470430eb-6c21-470d-899f-d7671b7fd0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39210
45992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3921045992
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1688200458
Short name T27
Test name
Test status
Simulation time 235730968 ps
CPU time 1.01 seconds
Started Aug 07 06:00:50 PM PDT 24
Finished Aug 07 06:00:51 PM PDT 24
Peak memory 206920 kb
Host smart-b8f0a2f9-4b38-4eea-bf58-69bb1ef2da0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16882
00458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1688200458
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2588035149
Short name T2598
Test name
Test status
Simulation time 7003646193 ps
CPU time 44.21 seconds
Started Aug 07 06:00:49 PM PDT 24
Finished Aug 07 06:01:34 PM PDT 24
Peak memory 215464 kb
Host smart-a9f5d2d9-694d-4ca0-9f48-c50f8fb064c2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588035149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2588035149
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1120178695
Short name T174
Test name
Test status
Simulation time 4805182115 ps
CPU time 122.98 seconds
Started Aug 07 06:00:51 PM PDT 24
Finished Aug 07 06:02:54 PM PDT 24
Peak memory 217724 kb
Host smart-eeb27caa-5101-4e09-b5ca-7f4806774e75
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1120178695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1120178695
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1018745563
Short name T3043
Test name
Test status
Simulation time 5468745908 ps
CPU time 21.65 seconds
Started Aug 07 06:00:52 PM PDT 24
Finished Aug 07 06:01:14 PM PDT 24
Peak memory 215528 kb
Host smart-eb9b553a-2d4a-41f6-ad82-856701ba5b0d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018745563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1018745563
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.4083451193
Short name T1059
Test name
Test status
Simulation time 219454110 ps
CPU time 0.97 seconds
Started Aug 07 06:00:49 PM PDT 24
Finished Aug 07 06:00:50 PM PDT 24
Peak memory 206904 kb
Host smart-5bf8de84-cc12-495e-9849-6785278c8096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40834
51193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.4083451193
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2133309567
Short name T1633
Test name
Test status
Simulation time 162382338 ps
CPU time 0.88 seconds
Started Aug 07 06:00:52 PM PDT 24
Finished Aug 07 06:00:53 PM PDT 24
Peak memory 206980 kb
Host smart-70edfe33-49a1-4494-a4e2-7359162446f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21333
09567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2133309567
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_resume_link_active.3687939127
Short name T1050
Test name
Test status
Simulation time 20172105442 ps
CPU time 24.57 seconds
Started Aug 07 06:00:48 PM PDT 24
Finished Aug 07 06:01:13 PM PDT 24
Peak memory 207068 kb
Host smart-8887df35-5e7a-4807-851d-cb3dc3c42cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36879
39127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.3687939127
Directory /workspace/9.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3819749739
Short name T69
Test name
Test status
Simulation time 138547945 ps
CPU time 0.82 seconds
Started Aug 07 06:00:49 PM PDT 24
Finished Aug 07 06:00:50 PM PDT 24
Peak memory 206948 kb
Host smart-18fb9317-e052-4115-a6ff-f28bf5231c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38197
49739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3819749739
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_rx_full.2387485677
Short name T48
Test name
Test status
Simulation time 326418314 ps
CPU time 1.16 seconds
Started Aug 07 06:00:52 PM PDT 24
Finished Aug 07 06:00:53 PM PDT 24
Peak memory 206992 kb
Host smart-4044080a-afdd-405c-8471-5c23f0b17042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23874
85677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.2387485677
Directory /workspace/9.usbdev_rx_full/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2999499165
Short name T2927
Test name
Test status
Simulation time 156378769 ps
CPU time 0.9 seconds
Started Aug 07 06:00:50 PM PDT 24
Finished Aug 07 06:00:52 PM PDT 24
Peak memory 206984 kb
Host smart-0c295045-4150-4427-b74c-9a6766d60a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29994
99165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2999499165
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3553184787
Short name T941
Test name
Test status
Simulation time 172894640 ps
CPU time 0.86 seconds
Started Aug 07 06:00:47 PM PDT 24
Finished Aug 07 06:00:48 PM PDT 24
Peak memory 206960 kb
Host smart-d925fa7c-ddee-4a9b-b5c4-9d5610ccbec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35531
84787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3553184787
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3325372586
Short name T564
Test name
Test status
Simulation time 191419885 ps
CPU time 0.92 seconds
Started Aug 07 06:00:50 PM PDT 24
Finished Aug 07 06:00:51 PM PDT 24
Peak memory 207000 kb
Host smart-a294016f-33bb-4a3c-ae56-b3253f7a8f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33253
72586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3325372586
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2722883634
Short name T1453
Test name
Test status
Simulation time 208176887 ps
CPU time 0.9 seconds
Started Aug 07 06:00:49 PM PDT 24
Finished Aug 07 06:00:50 PM PDT 24
Peak memory 206968 kb
Host smart-b278ef40-a790-4c35-8f81-ce56079d4f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27228
83634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2722883634
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3650254277
Short name T2851
Test name
Test status
Simulation time 188532145 ps
CPU time 0.89 seconds
Started Aug 07 06:00:47 PM PDT 24
Finished Aug 07 06:00:48 PM PDT 24
Peak memory 206996 kb
Host smart-89f25c3a-21a1-413e-9f6c-5ee1ec4656ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36502
54277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3650254277
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.598612354
Short name T808
Test name
Test status
Simulation time 690896580 ps
CPU time 1.97 seconds
Started Aug 07 06:00:50 PM PDT 24
Finished Aug 07 06:00:52 PM PDT 24
Peak memory 206964 kb
Host smart-38469401-ec3d-40f1-924b-a7524cc6769d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59861
2354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.598612354
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.184504728
Short name T1539
Test name
Test status
Simulation time 1751210639 ps
CPU time 50.61 seconds
Started Aug 07 06:00:48 PM PDT 24
Finished Aug 07 06:01:39 PM PDT 24
Peak memory 216840 kb
Host smart-70fe047e-a55e-479b-9162-25799f796811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18450
4728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.184504728
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.3922482450
Short name T2299
Test name
Test status
Simulation time 3867790216 ps
CPU time 35.53 seconds
Started Aug 07 06:00:35 PM PDT 24
Finished Aug 07 06:01:11 PM PDT 24
Peak memory 207272 kb
Host smart-24607247-491b-4e0f-8dc7-0af3bbf7c31b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922482450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.3922482450
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/90.usbdev_endpoint_types.198971928
Short name T2772
Test name
Test status
Simulation time 589149937 ps
CPU time 1.59 seconds
Started Aug 07 06:12:52 PM PDT 24
Finished Aug 07 06:12:54 PM PDT 24
Peak memory 206952 kb
Host smart-bc481fc3-9898-473f-b3a3-bd965eec37b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=198971928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.198971928
Directory /workspace/90.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/91.usbdev_endpoint_types.379189953
Short name T2323
Test name
Test status
Simulation time 379976384 ps
CPU time 1.25 seconds
Started Aug 07 06:12:54 PM PDT 24
Finished Aug 07 06:12:56 PM PDT 24
Peak memory 206960 kb
Host smart-912b56fe-015e-4433-9fa1-c57d89b1dda7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=379189953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.379189953
Directory /workspace/91.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/92.usbdev_endpoint_types.1663412629
Short name T386
Test name
Test status
Simulation time 719215919 ps
CPU time 1.71 seconds
Started Aug 07 06:12:55 PM PDT 24
Finished Aug 07 06:12:57 PM PDT 24
Peak memory 206880 kb
Host smart-7fc5846c-833a-4dbb-aaa2-34ac0b919e7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1663412629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.1663412629
Directory /workspace/92.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/94.usbdev_endpoint_types.360592813
Short name T471
Test name
Test status
Simulation time 488707869 ps
CPU time 1.5 seconds
Started Aug 07 06:12:57 PM PDT 24
Finished Aug 07 06:12:58 PM PDT 24
Peak memory 206956 kb
Host smart-feabae8d-9ed5-455d-aad7-1a5e98c20106
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=360592813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.360592813
Directory /workspace/94.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/95.usbdev_endpoint_types.6550397
Short name T87
Test name
Test status
Simulation time 473798170 ps
CPU time 1.31 seconds
Started Aug 07 06:12:49 PM PDT 24
Finished Aug 07 06:12:51 PM PDT 24
Peak memory 206936 kb
Host smart-e1045b57-46ea-464b-aedf-b512e146d9a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=6550397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.6550397
Directory /workspace/95.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/96.usbdev_endpoint_types.158185035
Short name T433
Test name
Test status
Simulation time 229413367 ps
CPU time 1.04 seconds
Started Aug 07 06:12:49 PM PDT 24
Finished Aug 07 06:12:51 PM PDT 24
Peak memory 206948 kb
Host smart-9e48cb8b-b3f2-4867-8939-292cf5d87c57
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=158185035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.158185035
Directory /workspace/96.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/97.usbdev_endpoint_types.2895729818
Short name T3040
Test name
Test status
Simulation time 582568146 ps
CPU time 1.46 seconds
Started Aug 07 06:12:55 PM PDT 24
Finished Aug 07 06:12:57 PM PDT 24
Peak memory 206952 kb
Host smart-b7c1aa18-afdd-403f-b5ab-075ec651305f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2895729818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.2895729818
Directory /workspace/97.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/98.usbdev_endpoint_types.1092406184
Short name T458
Test name
Test status
Simulation time 440265414 ps
CPU time 1.56 seconds
Started Aug 07 06:12:49 PM PDT 24
Finished Aug 07 06:12:51 PM PDT 24
Peak memory 206952 kb
Host smart-913d6bc4-da71-4bd1-9014-ba5fa603edcc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1092406184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.1092406184
Directory /workspace/98.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/99.usbdev_endpoint_types.1019529034
Short name T421
Test name
Test status
Simulation time 759004491 ps
CPU time 1.74 seconds
Started Aug 07 06:12:50 PM PDT 24
Finished Aug 07 06:12:52 PM PDT 24
Peak memory 206968 kb
Host smart-e0267171-25e8-4734-83c5-e309f06bb1eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1019529034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.1019529034
Directory /workspace/99.usbdev_endpoint_types/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%