Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	92173	1			T1	3		T2	3		T3	2
all_values[1]	92173	1			T1	3		T2	3		T3	2
all_values[2]	92173	1			T1	3		T2	3		T3	2
all_values[3]	92173	1			T1	3		T2	3		T3	2
all_values[4]	92173	1			T1	3		T2	3		T3	2
all_values[5]	92173	1			T1	3		T2	3		T3	2
all_values[6]	92173	1			T1	3		T2	3		T3	2
all_values[7]	92173	1			T1	3		T2	3		T3	2
all_values[8]	92173	1			T1	3		T2	3		T3	2
all_values[9]	92173	1			T1	3		T2	3		T3	2
all_values[10]	92173	1			T1	3		T2	3		T3	2
all_values[11]	92173	1			T1	3		T2	3		T3	2
all_values[12]	92173	1			T1	3		T2	3		T3	2
all_values[13]	92173	1			T1	3		T2	3		T3	2
all_values[14]	92173	1			T1	3		T2	3		T3	2
all_values[15]	92173	1			T1	3		T2	3		T3	2
all_values[16]	92173	1			T1	3		T2	3		T3	2
all_values[17]	92173	1			T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2939758

1

T1

96

T2

96

T3

64

auto[1]

9778

1

T30

3

T31

5

T32

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2464528

1

T1

87

T2

80

T3

57

auto[1]

485008

1

T1

9

T2

16

T3

7

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	63544	1			T1	3		T3	2		T38	3
all_values[0]	auto[0]	auto[1]	25295	1			T2	3		T62	4		T90	1
all_values[0]	auto[1]	auto[0]	3232	1			T31	5		T32	5		T33	5
all_values[0]	auto[1]	auto[1]	102	1			T353	1		T354	1		T355	1
all_values[1]	auto[0]	auto[0]	87665	1			T1	3		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	3103	1			T2	1		T31	3		T32	3
all_values[1]	auto[1]	auto[0]	521	1			T30	2		T37	2		T7	1
all_values[1]	auto[1]	auto[1]	884	1			T30	1		T37	1		T7	1
all_values[2]	auto[0]	auto[0]	4233	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	87672	1			T1	2		T2	2		T3	1
all_values[2]	auto[1]	auto[0]	138	1			T67	1		T68	1		T69	1
all_values[2]	auto[1]	auto[1]	130	1			T67	1		T68	1		T69	1
all_values[3]	auto[0]	auto[0]	90283	1			T1	3		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	290	1			T5	1		T6	1		T70	1
all_values[3]	auto[1]	auto[0]	1529	1			T71	1428		T223	1		T226	1
all_values[3]	auto[1]	auto[1]	71	1			T71	1		T223	1		T227	2
all_values[4]	auto[0]	auto[0]	4219	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	87789	1			T1	2		T2	2		T3	1
all_values[4]	auto[1]	auto[0]	104	1			T72	1		T223	1		T226	3
all_values[4]	auto[1]	auto[1]	61	1			T72	1		T226	1		T224	3
all_values[5]	auto[0]	auto[0]	91665	1			T1	2		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	355	1			T1	1		T38	1		T5	1
all_values[5]	auto[1]	auto[0]	96	1			T223	2		T224	2		T225	1
all_values[5]	auto[1]	auto[1]	57	1			T223	2		T224	2		T225	5
all_values[6]	auto[0]	auto[0]	91732	1			T1	3		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	208	1			T5	1		T70	1		T288	1
all_values[6]	auto[1]	auto[0]	115	1			T223	4		T226	2		T224	1
all_values[6]	auto[1]	auto[1]	118	1			T46	1		T21	1		T47	1
all_values[7]	auto[0]	auto[0]	35563	1			T1	2		T38	2		T39	2
all_values[7]	auto[0]	auto[1]	56436	1			T1	1		T2	3		T3	2
all_values[7]	auto[1]	auto[0]	121	1			T48	1		T49	1		T50	1
all_values[7]	auto[1]	auto[1]	53	1			T48	1		T49	1		T50	1
all_values[8]	auto[0]	auto[0]	91417	1			T1	3		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	50	1			T223	1		T226	3		T340	2
all_values[8]	auto[1]	auto[0]	610	1			T54	10		T55	10		T56	10
all_values[8]	auto[1]	auto[1]	96	1			T51	1		T52	1		T53	1
all_values[9]	auto[0]	auto[0]	91910	1			T1	3		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	61	1			T223	1		T225	3		T340	2
all_values[9]	auto[1]	auto[0]	118	1			T64	3		T65	3		T66	3
all_values[9]	auto[1]	auto[1]	84	1			T64	2		T65	2		T66	2
all_values[10]	auto[0]	auto[0]	91642	1			T1	3		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	389	1			T36	3		T62	2		T63	1
all_values[10]	auto[1]	auto[0]	94	1			T225	4		T227	1		T319	1
all_values[10]	auto[1]	auto[1]	48	1			T226	1		T227	1		T342	3
all_values[11]	auto[0]	auto[0]	91114	1			T1	3		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	803	1			T31	3		T32	3		T35	3
all_values[11]	auto[1]	auto[0]	136	1			T76	1		T77	1		T78	1
all_values[11]	auto[1]	auto[1]	120	1			T76	1		T77	1		T78	1
all_values[12]	auto[0]	auto[0]	91786	1			T1	3		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	190	1			T80	1		T81	3		T84	3
all_values[12]	auto[1]	auto[0]	125	1			T79	2		T82	2		T83	2
all_values[12]	auto[1]	auto[1]	72	1			T79	1		T82	1		T83	1
all_values[13]	auto[0]	auto[0]	91850	1			T1	3		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	56	1			T80	1		T88	1		T89	1
all_values[13]	auto[1]	auto[0]	155	1			T85	1		T86	1		T87	1
all_values[13]	auto[1]	auto[1]	112	1			T85	1		T86	1		T87	1
all_values[14]	auto[0]	auto[0]	18176	1			T1	3		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	73839	1			T4	1		T5	1		T63	1
all_values[14]	auto[1]	auto[0]	88	1			T223	3		T226	3		T224	4
all_values[14]	auto[1]	auto[1]	70	1			T223	1		T226	1		T224	2
all_values[15]	auto[0]	auto[0]	4258	1			T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	87752	1			T1	2		T2	2		T3	1
all_values[15]	auto[1]	auto[0]	111	1			T223	2		T224	4		T225	5
all_values[15]	auto[1]	auto[1]	52	1			T223	2		T224	1		T227	1
all_values[16]	auto[0]	auto[0]	91148	1			T1	3		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	851	1			T29	1		T31	3		T32	3
all_values[16]	auto[1]	auto[0]	103	1			T73	4		T74	4		T75	4
all_values[16]	auto[1]	auto[1]	71	1			T73	4		T74	4		T75	4
all_values[17]	auto[0]	auto[0]	34395	1			T1	2		T38	2		T39	2
all_values[17]	auto[0]	auto[1]	57597	1			T1	1		T2	3		T3	2
all_values[17]	auto[1]	auto[0]	110	1			T60	1		T61	1		T223	1
all_values[17]	auto[1]	auto[1]	71	1			T60	1		T61	1		T225	3