Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1905	1			T107	2		T334	1		T121	1
range_16_to_126	153594	1			T3	1		T39	14		T29	1
fifteen	1687	1			T17	5		T248	1		T115	3
range_2_to_14	24374	1			T2	2		T39	4		T108	1
seven	735	1			T39	1		T126	1		T191	1
one	758	1			T108	1		T334	1		T191	1
zero	1308	1			T125	1		T120	1		T181	77

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

13901

1

T93

3

T107

2

T108

1

three

12084

1

T2

2

T33

3

T95

1

---

Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	148	1			T114	1		T383	1		T115	1
range_127	three	151	1			T121	1		T116	1		T499	2
range_16_to_126	seven	12088	1			T93	3		T107	2		T108	1
range_16_to_126	three	10285	1			T33	3		T95	1		T76	1
fifteen	seven	38	1			T500	2		T393	1		T408	1
fifteen	three	55	1			T500	2		T135	2		T444	1
range_2_to_14	seven	1473	1			T334	1		T268	69		T112	4
range_2_to_14	three	1486	1			T2	2		T333	1		T268	62
seven	seven	37	1			T501	2		T405	1		T499	1
seven	three	28	1			T501	2		T338	1		T502	1
one	seven	45	1			T115	1		T503	1		T504	3
one	three	38	1			T191	1		T115	1		T117	1
zero	seven	109	1			T120	1		T116	1		T505	2
zero	three	69	1			T331	1		T116	1		T506	1