Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120371

1

T2

1

T39

13

T29

1

auto[1]

45330

1

T2

1

T30

1

T31

3

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29989	1			T4	2		T6	176		T328	5
max_len_m1	777	1			T5	2		T62	2		T70	2
max_len_m2	845	1			T34	1		T70	4		T268	4
max_len_m3	846	1			T18	1		T515	1		T268	3
five	1108	1			T5	4		T160	1		T268	8
four	1200	1			T4	2		T92	1		T19	2
three	730	1			T93	1		T515	1		T160	1
one	842	1			T31	1		T515	1		T268	16
zero	11404	1			T34	1		T35	1		T63	16

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24305	1			T4	1		T328	5		T17	5
max_len	auto[1]	5684	1			T4	1		T6	176		T118	1
max_len_m1	auto[0]	539	1			T5	1		T62	1		T70	1
max_len_m1	auto[1]	238	1			T5	1		T62	1		T70	1
max_len_m2	auto[0]	582	1			T34	1		T70	2		T268	4
max_len_m2	auto[1]	263	1			T70	2		T161	2		T516	1
max_len_m3	auto[0]	590	1			T515	1		T268	3		T161	3
max_len_m3	auto[1]	256	1			T18	1		T161	1		T191	2
five	auto[0]	580	1			T5	2		T268	3		T163	3
five	auto[1]	528	1			T5	2		T160	1		T268	5
four	auto[0]	609	1			T4	1		T19	1		T160	1
four	auto[1]	591	1			T4	1		T92	1		T19	1
three	auto[0]	383	1			T93	1		T515	1		T160	1
three	auto[1]	347	1			T268	12		T290	3		T291	4
one	auto[0]	389	1			T31	1		T515	1		T268	4
one	auto[1]	453	1			T268	12		T517	1		T12	1
zero	auto[0]	533	1			T35	1		T329	1		T19	1
zero	auto[1]	10871	1			T34	1		T63	16		T119	3