Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
56.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	96	48	48	50.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	48	48	50.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70257

1

T2

1

T29

1

T30

1

auto[1]

39465

1

T30

1

T31

3

T32

3

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	8429	1			T29	1		T32	7		T34	3
endpoints[0x1]	9701	1			T106	6		T70	16		T19	2
endpoints[0x2]	10265	1			T4	114		T119	3		T94	3
endpoints[0x3]	7465	1			T2	1		T33	3		T95	1
endpoints[0x4]	9343	1			T31	3		T33	6		T35	3
endpoints[0x5]	12728	1			T31	7		T35	7		T63	16
endpoints[0x6]	8535	1			T5	24		T62	2		T107	1
endpoints[0x7]	9556	1			T93	3		T108	1		T70	16
endpoints[0x8]	7924	1			T36	3		T93	6		T70	16
endpoints[0x9]	9813	1			T30	2		T36	7		T37	2
endpoints[0xa]	8267	1			T5	24		T19	2		T327	1
endpoints[0xb]	7696	1			T32	3		T92	3		T79	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
nak	0	1	1
ack	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

data1

51261

1

T31

6

T32

6

T33

6

data0

58444

1

T2

1

T29

1

T30

2

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	48	48	50.00	48

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	*	*	--	--	48

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	endpoints[0x0]	2327	1			T32	2		T34	1		T92	2
data1	auto[0]	endpoints[0x1]	2787	1			T106	2		T70	4		T268	19
data1	auto[0]	endpoints[0x2]	2965	1			T4	19		T94	1		T162	1
data1	auto[0]	endpoints[0x3]	1596	1			T33	1		T94	2		T162	2
data1	auto[0]	endpoints[0x4]	2794	1			T31	1		T33	2		T35	1
data1	auto[0]	endpoints[0x5]	4132	1			T31	2		T35	2		T18	2
data1	auto[0]	endpoints[0x6]	2058	1			T5	5		T328	2		T24	1
data1	auto[0]	endpoints[0x7]	2663	1			T93	1		T70	3		T20	1
data1	auto[0]	endpoints[0x8]	1963	1			T36	1		T93	2		T70	4
data1	auto[0]	endpoints[0x9]	2790	1			T36	2		T17	2		T23	2
data1	auto[0]	endpoints[0xa]	1986	1			T5	4		T160	2		T268	16
data1	auto[0]	endpoints[0xb]	1961	1			T32	1		T92	1		T5	6
data1	auto[1]	endpoints[0x0]	1598	1			T32	2		T92	2		T106	1
data1	auto[1]	endpoints[0x1]	1742	1			T106	2		T70	4		T268	16
data1	auto[1]	endpoints[0x2]	1894	1			T4	38		T119	1		T94	1
data1	auto[1]	endpoints[0x3]	1802	1			T33	1		T94	2		T176	9
data1	auto[1]	endpoints[0x4]	1628	1			T31	1		T33	2		T35	1
data1	auto[1]	endpoints[0x5]	1858	1			T31	2		T35	2		T63	8
data1	auto[1]	endpoints[0x6]	1903	1			T5	7		T24	1		T118	2
data1	auto[1]	endpoints[0x7]	1826	1			T93	1		T70	4		T20	1
data1	auto[1]	endpoints[0x8]	1706	1			T36	1		T93	2		T70	4
data1	auto[1]	endpoints[0x9]	1781	1			T36	2		T160	1		T268	21
data1	auto[1]	endpoints[0xa]	1835	1			T5	8		T160	2		T268	15
data1	auto[1]	endpoints[0xb]	1666	1			T32	1		T92	1		T5	6
data0	auto[0]	endpoints[0x0]	3122	1			T29	1		T32	2		T34	1
data0	auto[0]	endpoints[0x1]	3695	1			T106	2		T70	4		T19	1
data0	auto[0]	endpoints[0x2]	3855	1			T4	38		T94	1		T162	1
data0	auto[0]	endpoints[0x3]	2489	1			T2	1		T33	1		T95	1
data0	auto[0]	endpoints[0x4]	3454	1			T31	1		T33	2		T35	1
data0	auto[0]	endpoints[0x5]	5124	1			T31	3		T35	3		T18	2
data0	auto[0]	endpoints[0x6]	2967	1			T5	7		T62	1		T328	3
data0	auto[0]	endpoints[0x7]	3522	1			T93	1		T70	5		T19	1
data0	auto[0]	endpoints[0x8]	2743	1			T36	1		T93	2		T70	4
data0	auto[0]	endpoints[0x9]	3733	1			T30	1		T36	2		T37	1
data0	auto[0]	endpoints[0xa]	2852	1			T5	8		T19	1		T327	1
data0	auto[0]	endpoints[0xb]	2662	1			T32	1		T92	1		T5	6
data0	auto[1]	endpoints[0x0]	1380	1			T34	1		T329	1		T330	1
data0	auto[1]	endpoints[0x1]	1476	1			T70	4		T19	1		T268	17
data0	auto[1]	endpoints[0x2]	1551	1			T4	19		T119	2		T70	4
data0	auto[1]	endpoints[0x3]	1577	1			T176	6		T19	1		T268	16
data0	auto[1]	endpoints[0x4]	1465	1			T5	4		T70	3		T19	1
data0	auto[1]	endpoints[0x5]	1610	1			T63	8		T19	1		T22	1
data0	auto[1]	endpoints[0x6]	1605	1			T5	5		T62	1		T107	1
data0	auto[1]	endpoints[0x7]	1545	1			T108	1		T70	4		T19	1
data0	auto[1]	endpoints[0x8]	1510	1			T70	4		T19	1		T268	16
data0	auto[1]	endpoints[0x9]	1508	1			T30	1		T36	1		T37	1
data0	auto[1]	endpoints[0xa]	1593	1			T5	4		T19	1		T160	1
data0	auto[1]	endpoints[0xb]	1406	1			T5	6		T70	3		T19	1