Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	6	10	62.50

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	6	10	62.50	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6937

1

T39

1

T107

2

T108

1

auto[1]

51841

1

T2

1

T3

1

T39

2

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52551

1

T3

1

T39

2

T30

1

auto[1]

6227

1

T2

1

T39

1

T108

1

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53369

1

T2

1

T39

1

T30

1

auto[1]

5409

1

T3

1

T39

2

T107

2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

345

1

T191

5

T331

6

T332

7

pkt_types[PidTypeInToken]

58433

1

T2

1

T3

1

T39

3

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	6	10	62.50	6

Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes

cp_pid	cp_in_enable	cp_in_iso	cp_in_stall	COUNT	AT LEAST	NUMBER	STATUS
[ignore_pre[PidTypePre]]	*	[auto[0]]	[auto[1]]	--	--	2
[ignore_pre[PidTypePre]]	*	[auto[1]]	*	--	--	4

Covered bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

172

1

T191

3

T331

5

T332

5

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

173

1

T191

2

T331

1

T332

2

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3985

1

T39

1

T333

1

T80

3

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2680

1

T107

2

T108

1

T334

3

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

49

1

T120

1

T335

2

T336

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

51

1

T337

1

T336

1

T338

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

42922

1

T30

1

T31

3

T32

3

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2619

1

T3

1

T39

1

T334

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

6068

1

T2

1

T108

1

T6

194

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

59

1

T39

1

T336

1

T339

1