Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	92173	1			T1	3		T2	3		T3	2
all_pins[1]	92173	1			T1	3		T2	3		T3	2
all_pins[2]	92173	1			T1	3		T2	3		T3	2
all_pins[3]	92173	1			T1	3		T2	3		T3	2
all_pins[4]	92173	1			T1	3		T2	3		T3	2
all_pins[5]	92173	1			T1	3		T2	3		T3	2
all_pins[6]	92173	1			T1	3		T2	3		T3	2
all_pins[7]	92173	1			T1	3		T2	3		T3	2
all_pins[8]	92173	1			T1	3		T2	3		T3	2
all_pins[9]	92173	1			T1	3		T2	3		T3	2
all_pins[10]	92173	1			T1	3		T2	3		T3	2
all_pins[11]	92173	1			T1	3		T2	3		T3	2
all_pins[12]	92173	1			T1	3		T2	3		T3	2
all_pins[13]	92173	1			T1	3		T2	3		T3	2
all_pins[14]	92173	1			T1	3		T2	3		T3	2
all_pins[15]	92173	1			T1	3		T2	3		T3	2
all_pins[16]	92173	1			T1	3		T2	3		T3	2
all_pins[17]	92173	1			T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2947264	1			T1	96		T2	96		T3	64
values[0x1]	2272	1			T30	1		T37	1		T76	1
transitions[0x0=>0x1]	1997	1			T30	1		T37	1		T76	1
transitions[0x1=>0x0]	1997	1			T30	1		T37	1		T76	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	92071	1			T1	3		T2	3		T3	2
all_pins[0]	values[0x1]	102	1			T353	1		T354	1		T355	1
all_pins[0]	transitions[0x0=>0x1]	85	1			T353	1		T354	1		T355	1
all_pins[0]	transitions[0x1=>0x0]	867	1			T30	1		T37	1		T7	1
all_pins[1]	values[0x0]	91289	1			T1	3		T2	3		T3	2
all_pins[1]	values[0x1]	884	1			T30	1		T37	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	870	1			T30	1		T37	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	116	1			T67	1		T68	1		T69	1
all_pins[2]	values[0x0]	92043	1			T1	3		T2	3		T3	2
all_pins[2]	values[0x1]	130	1			T67	1		T68	1		T69	1
all_pins[2]	transitions[0x0=>0x1]	109	1			T67	1		T68	1		T69	1
all_pins[2]	transitions[0x1=>0x0]	50	1			T71	1		T223	1		T227	2
all_pins[3]	values[0x0]	92102	1			T1	3		T2	3		T3	2
all_pins[3]	values[0x1]	71	1			T71	1		T223	1		T227	2
all_pins[3]	transitions[0x0=>0x1]	55	1			T71	1		T223	1		T227	2
all_pins[3]	transitions[0x1=>0x0]	45	1			T72	1		T226	1		T224	3
all_pins[4]	values[0x0]	92112	1			T1	3		T2	3		T3	2
all_pins[4]	values[0x1]	61	1			T72	1		T226	1		T224	3
all_pins[4]	transitions[0x0=>0x1]	36	1			T72	1		T226	1		T224	1
all_pins[4]	transitions[0x1=>0x0]	32	1			T223	2		T225	2		T227	3
all_pins[5]	values[0x0]	92116	1			T1	3		T2	3		T3	2
all_pins[5]	values[0x1]	57	1			T223	2		T224	2		T225	5
all_pins[5]	transitions[0x0=>0x1]	41	1			T223	2		T224	2		T225	4
all_pins[5]	transitions[0x1=>0x0]	102	1			T46	1		T21	1		T47	1
all_pins[6]	values[0x0]	92055	1			T1	3		T2	3		T3	2
all_pins[6]	values[0x1]	118	1			T46	1		T21	1		T47	1
all_pins[6]	transitions[0x0=>0x1]	108	1			T46	1		T21	1		T47	1
all_pins[6]	transitions[0x1=>0x0]	43	1			T48	1		T49	1		T50	1
all_pins[7]	values[0x0]	92120	1			T1	3		T2	3		T3	2
all_pins[7]	values[0x1]	53	1			T48	1		T49	1		T50	1
all_pins[7]	transitions[0x0=>0x1]	37	1			T48	1		T49	1		T50	1
all_pins[7]	transitions[0x1=>0x0]	80	1			T51	1		T52	1		T53	1
all_pins[8]	values[0x0]	92077	1			T1	3		T2	3		T3	2
all_pins[8]	values[0x1]	96	1			T51	1		T52	1		T53	1
all_pins[8]	transitions[0x0=>0x1]	80	1			T51	1		T52	1		T53	1
all_pins[8]	transitions[0x1=>0x0]	68	1			T64	2		T65	2		T66	2
all_pins[9]	values[0x0]	92089	1			T1	3		T2	3		T3	2
all_pins[9]	values[0x1]	84	1			T64	2		T65	2		T66	2
all_pins[9]	transitions[0x0=>0x1]	64	1			T64	2		T65	2		T66	2
all_pins[9]	transitions[0x1=>0x0]	28	1			T226	1		T227	1		T320	3
all_pins[10]	values[0x0]	92125	1			T1	3		T2	3		T3	2
all_pins[10]	values[0x1]	48	1			T226	1		T227	1		T342	3
all_pins[10]	transitions[0x0=>0x1]	33	1			T226	1		T342	2		T320	2
all_pins[10]	transitions[0x1=>0x0]	105	1			T76	1		T77	1		T78	1
all_pins[11]	values[0x0]	92053	1			T1	3		T2	3		T3	2
all_pins[11]	values[0x1]	120	1			T76	1		T77	1		T78	1
all_pins[11]	transitions[0x0=>0x1]	104	1			T76	1		T77	1		T78	1
all_pins[11]	transitions[0x1=>0x0]	56	1			T79	1		T82	1		T83	1
all_pins[12]	values[0x0]	92101	1			T1	3		T2	3		T3	2
all_pins[12]	values[0x1]	72	1			T79	1		T82	1		T83	1
all_pins[12]	transitions[0x0=>0x1]	59	1			T79	1		T82	1		T83	1
all_pins[12]	transitions[0x1=>0x0]	99	1			T85	1		T86	1		T87	1
all_pins[13]	values[0x0]	92061	1			T1	3		T2	3		T3	2
all_pins[13]	values[0x1]	112	1			T85	1		T86	1		T87	1
all_pins[13]	transitions[0x0=>0x1]	97	1			T85	1		T86	1		T87	1
all_pins[13]	transitions[0x1=>0x0]	55	1			T223	1		T226	1		T224	2
all_pins[14]	values[0x0]	92103	1			T1	3		T2	3		T3	2
all_pins[14]	values[0x1]	70	1			T223	1		T226	1		T224	2
all_pins[14]	transitions[0x0=>0x1]	60	1			T223	1		T226	1		T224	2
all_pins[14]	transitions[0x1=>0x0]	42	1			T223	2		T224	1		T227	1
all_pins[15]	values[0x0]	92121	1			T1	3		T2	3		T3	2
all_pins[15]	values[0x1]	52	1			T223	2		T224	1		T227	1
all_pins[15]	transitions[0x0=>0x1]	33	1			T223	2		T224	1		T227	1
all_pins[15]	transitions[0x1=>0x0]	52	1			T73	4		T74	4		T75	4
all_pins[16]	values[0x0]	92102	1			T1	3		T2	3		T3	2
all_pins[16]	values[0x1]	71	1			T73	4		T74	4		T75	4
all_pins[16]	transitions[0x0=>0x1]	55	1			T73	4		T74	4		T75	4
all_pins[16]	transitions[0x1=>0x0]	55	1			T60	1		T61	1		T225	3
all_pins[17]	values[0x0]	92102	1			T1	3		T2	3		T3	2
all_pins[17]	values[0x1]	71	1			T60	1		T61	1		T225	3
all_pins[17]	transitions[0x0=>0x1]	71	1			T60	1		T61	1		T225	3