Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4992	1			T39	2		T108	4		T80	1
invalid_ep[0xd]	4924	1			T39	1		T163	14		T120	1
invalid_ep[0xe]	4940	1			T39	1		T163	15		T120	2
invalid_ep[0xf]	5022	1			T39	1		T108	1		T163	17
endpoints[0x0]	12912	1			T39	1		T29	1		T32	7
endpoints[0x1]	14097	1			T3	1		T39	3		T106	7
endpoints[0x2]	15115	1			T39	1		T4	115		T119	3
endpoints[0x3]	12084	1			T2	2		T33	3		T95	1
endpoints[0x4]	14101	1			T39	1		T31	3		T33	6
endpoints[0x5]	16816	1			T39	2		T31	7		T35	7
endpoints[0x6]	13160	1			T39	1		T5	25		T62	2
endpoints[0x7]	13901	1			T93	3		T107	2		T108	1
endpoints[0x8]	12612	1			T39	2		T36	3		T93	6
endpoints[0x9]	14413	1			T39	2		T30	2		T36	7
endpoints[0xa]	12368	1			T5	25		T107	2		T270	1
endpoints[0xb]	12169	1			T32	3		T92	3		T79	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	24493	1			T39	8		T31	3		T32	4
pkt_types[PidTypeOutToken]	77280	1			T2	1		T39	3		T29	1
pkt_types[PidTypeInToken]	62759	1			T2	1		T3	1		T39	5

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1142	1			T337	2		T115	25		T339	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1094	1			T115	21		T116	21		T117	18
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1111	1			T115	24		T116	21		T389	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1122	1			T39	1		T384	1		T335	1
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1608	1			T39	1		T32	3		T92	2
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1708	1			T39	2		T106	2		T161	4
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1755	1			T39	1		T4	27		T94	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1659	1			T33	1		T94	3		T108	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1494	1			T31	1		T33	2		T35	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1655	1			T39	1		T31	2		T35	2
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1734	1			T5	5		T107	1		T24	1
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1737	1			T93	1		T107	1		T334	1
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1588	1			T39	1		T36	1		T93	2
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1744	1			T39	1		T36	2		T160	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1674	1			T5	7		T270	1		T160	2
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1668	1			T32	1		T92	1		T108	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1620	1			T108	2		T80	1		T163	14
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1613	1			T39	1		T163	14		T161	12
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1623	1			T39	1		T163	15		T120	1
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1725	1			T108	1		T163	17		T120	1
pkt_types[PidTypeOutToken]	endpoints[0x0]	5608	1			T29	1		T32	2		T34	2
pkt_types[PidTypeOutToken]	endpoints[0x1]	6592	1			T106	3		T70	8		T19	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	6782	1			T4	30		T94	1		T107	4
pkt_types[PidTypeOutToken]	endpoints[0x3]	4128	1			T2	1		T33	1		T95	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	6481	1			T31	1		T33	2		T35	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	9137	1			T31	3		T35	3		T334	2
pkt_types[PidTypeOutToken]	endpoints[0x6]	4844	1			T39	1		T5	7		T62	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	6129	1			T93	1		T70	5		T19	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	4895	1			T36	1		T93	2		T108	2
pkt_types[PidTypeOutToken]	endpoints[0x9]	6590	1			T30	1		T36	2		T37	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	4751	1			T5	5		T19	1		T327	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	4762	1			T32	1		T92	1		T79	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1093	1			T39	2		T383	1		T336	1
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1052	1			T120	1		T248	2		T424	1
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1128	1			T248	1		T337	1		T383	1
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1053	1			T384	1		T337	1		T115	30
pkt_types[PidTypeInToken]	endpoints[0x0]	4462	1			T32	2		T34	1		T92	2
pkt_types[PidTypeInToken]	endpoints[0x1]	4507	1			T3	1		T39	1		T106	2
pkt_types[PidTypeInToken]	endpoints[0x2]	5319	1			T4	58		T119	3		T94	1
pkt_types[PidTypeInToken]	endpoints[0x3]	5078	1			T2	1		T33	1		T94	2
pkt_types[PidTypeInToken]	endpoints[0x4]	4891	1			T39	1		T31	1		T33	2
pkt_types[PidTypeInToken]	endpoints[0x5]	4858	1			T31	2		T35	2		T63	16
pkt_types[PidTypeInToken]	endpoints[0x6]	5380	1			T5	13		T62	1		T107	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4790	1			T93	1		T108	1		T70	9
pkt_types[PidTypeInToken]	endpoints[0x8]	4948	1			T39	1		T36	1		T93	2
pkt_types[PidTypeInToken]	endpoints[0x9]	4901	1			T30	1		T36	3		T37	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4737	1			T5	13		T107	1		T125	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4562	1			T32	1		T92	1		T5	13