Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T223	4		T226	4		T224	7
all_values[1]	278	1			T223	4		T226	4		T224	7
all_values[2]	278	1			T223	4		T226	4		T224	7
all_values[3]	278	1			T223	4		T226	4		T224	7
all_values[4]	278	1			T223	4		T226	4		T224	7
all_values[5]	278	1			T223	4		T226	4		T224	7
all_values[6]	278	1			T223	4		T226	4		T224	7
all_values[7]	278	1			T223	4		T226	4		T224	7
all_values[8]	278	1			T223	4		T226	4		T224	7
all_values[9]	278	1			T223	4		T226	4		T224	7
all_values[10]	278	1			T223	4		T226	4		T224	7
all_values[11]	278	1			T223	4		T226	4		T224	7
all_values[12]	278	1			T223	4		T226	4		T224	7
all_values[13]	278	1			T223	4		T226	4		T224	7
all_values[14]	278	1			T223	4		T226	4		T224	7
all_values[15]	278	1			T223	4		T226	4		T224	7
all_values[16]	278	1			T223	4		T226	4		T224	7
all_values[17]	278	1			T223	4		T226	4		T224	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6658

1

T223

92

T226

101

T224

157

auto[1]

2238

1

T223

36

T226

27

T224

67

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6117

1

T223

83

T226

88

T224

161

auto[1]

2779

1

T223

45

T226

40

T224

63

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5208

1

T223

73

T226

80

T224

136

auto[1]

3688

1

T223

55

T226

48

T224

88

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	88	1			T226	2		T224	3		T225	2
all_values[0]	auto[0]	auto[1]	auto[0]	89	1			T223	3		T226	1		T224	1
all_values[0]	auto[1]	auto[0]	auto[1]	61	1			T226	1		T224	1		T225	4
all_values[0]	auto[1]	auto[1]	auto[1]	40	1			T223	1		T224	2		T225	1
all_values[1]	auto[0]	auto[0]	auto[0]	88	1			T223	1		T226	2		T224	2
all_values[1]	auto[0]	auto[1]	auto[0]	73	1			T223	1		T224	1		T225	1
all_values[1]	auto[1]	auto[0]	auto[1]	68	1			T223	1		T226	2		T224	2
all_values[1]	auto[1]	auto[1]	auto[1]	49	1			T223	1		T224	2		T319	1
all_values[2]	auto[0]	auto[0]	auto[0]	38	1			T340	2		T320	1		T341	1
all_values[2]	auto[0]	auto[0]	auto[1]	44	1			T226	1		T225	1		T319	1
all_values[2]	auto[0]	auto[1]	auto[0]	38	1			T224	2		T227	2		T319	2
all_values[2]	auto[0]	auto[1]	auto[1]	35	1			T223	1		T226	2		T224	1
all_values[2]	auto[1]	auto[0]	auto[1]	74	1			T223	2		T226	1		T224	1
all_values[2]	auto[1]	auto[1]	auto[1]	49	1			T223	1		T224	3		T225	2
all_values[3]	auto[0]	auto[0]	auto[0]	63	1			T223	2		T226	2		T224	4
all_values[3]	auto[0]	auto[0]	auto[1]	22	1			T226	1		T340	1		T320	2
all_values[3]	auto[0]	auto[1]	auto[0]	48	1			T225	3		T227	2		T319	1
all_values[3]	auto[0]	auto[1]	auto[1]	29	1			T223	1		T227	1		T340	2
all_values[3]	auto[1]	auto[0]	auto[1]	62	1			T226	1		T224	1		T319	1
all_values[3]	auto[1]	auto[1]	auto[1]	54	1			T223	1		T224	2		T225	1
all_values[4]	auto[0]	auto[0]	auto[0]	60	1			T226	1		T224	1		T225	2
all_values[4]	auto[0]	auto[0]	auto[1]	27	1			T223	2		T225	1		T340	1
all_values[4]	auto[0]	auto[1]	auto[0]	49	1			T223	1		T226	1		T224	2
all_values[4]	auto[0]	auto[1]	auto[1]	21	1			T224	1		T225	1		T320	1
all_values[4]	auto[1]	auto[0]	auto[1]	69	1			T225	1		T227	2		T319	1
all_values[4]	auto[1]	auto[1]	auto[1]	52	1			T223	1		T226	2		T224	3
all_values[5]	auto[0]	auto[0]	auto[0]	64	1			T224	4		T340	3		T342	1
all_values[5]	auto[0]	auto[0]	auto[1]	33	1			T223	1		T226	3		T319	1
all_values[5]	auto[0]	auto[1]	auto[0]	47	1			T227	1		T340	2		T342	1
all_values[5]	auto[0]	auto[1]	auto[1]	19	1			T223	1		T224	1		T225	1
all_values[5]	auto[1]	auto[0]	auto[1]	63	1			T223	1		T226	1		T224	1
all_values[5]	auto[1]	auto[1]	auto[1]	52	1			T223	1		T224	1		T225	4
all_values[6]	auto[0]	auto[0]	auto[0]	60	1			T226	1		T224	3		T340	2
all_values[6]	auto[0]	auto[0]	auto[1]	21	1			T223	1		T224	1		T225	1
all_values[6]	auto[0]	auto[1]	auto[0]	50	1			T223	2		T224	1		T227	1
all_values[6]	auto[0]	auto[1]	auto[1]	31	1			T226	1		T319	1		T340	1
all_values[6]	auto[1]	auto[0]	auto[1]	63	1			T223	1		T224	2		T225	4
all_values[6]	auto[1]	auto[1]	auto[1]	53	1			T226	2		T225	2		T227	1
all_values[7]	auto[0]	auto[0]	auto[0]	107	1			T226	2		T224	1		T225	2
all_values[7]	auto[0]	auto[1]	auto[0]	76	1			T223	2		T224	3		T225	1
all_values[7]	auto[1]	auto[0]	auto[1]	54	1			T226	2		T224	2		T225	2
all_values[7]	auto[1]	auto[1]	auto[1]	41	1			T223	2		T224	1		T225	2
all_values[8]	auto[0]	auto[0]	auto[0]	81	1			T223	1		T226	1		T224	4
all_values[8]	auto[0]	auto[1]	auto[0]	76	1			T223	1		T224	2		T225	2
all_values[8]	auto[1]	auto[0]	auto[1]	63	1			T223	1		T226	3		T225	1
all_values[8]	auto[1]	auto[1]	auto[1]	58	1			T223	1		T224	1		T225	3
all_values[9]	auto[0]	auto[0]	auto[0]	60	1			T226	1		T224	1		T227	3
all_values[9]	auto[0]	auto[0]	auto[1]	25	1			T223	1		T225	2		T340	2
all_values[9]	auto[0]	auto[1]	auto[0]	40	1			T226	3		T224	2		T319	2
all_values[9]	auto[0]	auto[1]	auto[1]	26	1			T223	1		T342	1		T341	1
all_values[9]	auto[1]	auto[0]	auto[1]	67	1			T223	1		T224	2		T225	2
all_values[9]	auto[1]	auto[1]	auto[1]	60	1			T223	1		T224	2		T225	3
all_values[10]	auto[0]	auto[0]	auto[0]	69	1			T224	4		T225	2		T227	1
all_values[10]	auto[0]	auto[0]	auto[1]	32	1			T223	1		T226	2		T224	2
all_values[10]	auto[0]	auto[1]	auto[0]	44	1			T225	2		T227	1		T340	1
all_values[10]	auto[0]	auto[1]	auto[1]	25	1			T342	3		T320	2		T343	1
all_values[10]	auto[1]	auto[0]	auto[1]	70	1			T223	3		T226	2		T224	1
all_values[10]	auto[1]	auto[1]	auto[1]	38	1			T225	1		T227	1		T340	1
all_values[11]	auto[0]	auto[0]	auto[0]	60	1			T226	2		T225	1		T319	2
all_values[11]	auto[0]	auto[0]	auto[1]	27	1			T224	1		T225	1		T227	1
all_values[11]	auto[0]	auto[1]	auto[0]	42	1			T223	4		T226	1		T225	1
all_values[11]	auto[0]	auto[1]	auto[1]	31	1			T224	4		T225	2		T342	1
all_values[11]	auto[1]	auto[0]	auto[1]	69	1			T224	1		T225	2		T227	1
all_values[11]	auto[1]	auto[1]	auto[1]	49	1			T226	1		T224	1		T227	1
all_values[12]	auto[0]	auto[0]	auto[0]	63	1			T223	2		T224	2		T227	2
all_values[12]	auto[0]	auto[0]	auto[1]	25	1			T340	1		T342	1		T341	1
all_values[12]	auto[0]	auto[1]	auto[0]	47	1			T224	2		T225	5		T227	2
all_values[12]	auto[0]	auto[1]	auto[1]	31	1			T226	1		T224	1		T340	2
all_values[12]	auto[1]	auto[0]	auto[1]	56	1			T223	2		T226	1		T225	1
all_values[12]	auto[1]	auto[1]	auto[1]	56	1			T226	2		T224	2		T225	1
all_values[13]	auto[0]	auto[0]	auto[0]	81	1			T223	1		T226	1		T224	3
all_values[13]	auto[0]	auto[0]	auto[1]	15	1			T341	1		T343	1		T344	2
all_values[13]	auto[0]	auto[1]	auto[0]	46	1			T226	1		T224	2		T225	3
all_values[13]	auto[0]	auto[1]	auto[1]	28	1			T223	1		T226	1		T227	1
all_values[13]	auto[1]	auto[0]	auto[1]	51	1			T223	1		T340	2		T342	1
all_values[13]	auto[1]	auto[1]	auto[1]	57	1			T223	1		T226	1		T224	2
all_values[14]	auto[0]	auto[0]	auto[0]	63	1			T226	1		T224	2		T225	2
all_values[14]	auto[0]	auto[0]	auto[1]	23	1			T342	2		T341	1		T345	1
all_values[14]	auto[0]	auto[1]	auto[0]	35	1			T223	2		T226	2		T227	2
all_values[14]	auto[0]	auto[1]	auto[1]	28	1			T224	1		T225	1		T227	1
all_values[14]	auto[1]	auto[0]	auto[1]	76	1			T226	1		T225	1		T319	1
all_values[14]	auto[1]	auto[1]	auto[1]	53	1			T223	2		T224	4		T225	3
all_values[15]	auto[0]	auto[0]	auto[0]	44	1			T223	2		T227	1		T340	1
all_values[15]	auto[0]	auto[0]	auto[1]	33	1			T226	1		T224	1		T225	1
all_values[15]	auto[0]	auto[1]	auto[0]	53	1			T224	2		T225	4		T340	3
all_values[15]	auto[0]	auto[1]	auto[1]	19	1			T223	1		T319	1		T346	1
all_values[15]	auto[1]	auto[0]	auto[1]	77	1			T226	3		T224	1		T225	1
all_values[15]	auto[1]	auto[1]	auto[1]	52	1			T223	1		T224	3		T225	1
all_values[16]	auto[0]	auto[0]	auto[0]	77	1			T226	1		T225	2		T227	1
all_values[16]	auto[0]	auto[0]	auto[1]	24	1			T223	2		T224	1		T227	1
all_values[16]	auto[0]	auto[1]	auto[0]	46	1			T226	3		T224	3		T225	1
all_values[16]	auto[0]	auto[1]	auto[1]	20	1			T224	1		T320	1		T343	1
all_values[16]	auto[1]	auto[0]	auto[1]	65	1			T223	2		T224	2		T225	2
all_values[16]	auto[1]	auto[1]	auto[1]	46	1			T225	2		T319	1		T340	1
all_values[17]	auto[0]	auto[0]	auto[0]	82	1			T223	2		T226	1		T224	1
all_values[17]	auto[0]	auto[1]	auto[0]	78	1			T226	2		T224	5		T225	2
all_values[17]	auto[1]	auto[0]	auto[1]	59	1			T223	2		T226	1		T224	1
all_values[17]	auto[1]	auto[1]	auto[1]	59	1			T225	3		T319	1		T342	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal